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source: vbox/trunk/src/recompiler_new/tcg/i386/tcg-target.c@ 15284

最後變更 在這個檔案從15284是 15173,由 vboxsync 提交於 16 年 前

an attempt to fix MacOS alignment issues
檔案大小: 41.0 KB
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1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24/*
25 * Sun LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
26 * other than GPL or LGPL is available it will apply instead, Sun elects to use only
27 * the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
28 * a choice of LGPL license versions is made available with the language indicating
29 * that LGPLv2 or any later version may be used, or where a choice of which version
30 * of the LGPL is applied is otherwise unspecified.
31 */
32#ifndef NDEBUG
33static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
34 "%eax",
35 "%ecx",
36 "%edx",
37 "%ebx",
38 "%esp",
39 "%ebp",
40 "%esi",
41 "%edi",
42};
43#endif
44
45static const int tcg_target_reg_alloc_order[] = {
46 TCG_REG_EAX,
47 TCG_REG_EDX,
48 TCG_REG_ECX,
49 TCG_REG_EBX,
50 TCG_REG_ESI,
51 TCG_REG_EDI,
52 TCG_REG_EBP,
53};
54
55static const int tcg_target_call_iarg_regs[3] = { TCG_REG_EAX, TCG_REG_EDX, TCG_REG_ECX };
56static const int tcg_target_call_oarg_regs[2] = { TCG_REG_EAX, TCG_REG_EDX };
57
58static uint8_t *tb_ret_addr;
59
60static void patch_reloc(uint8_t *code_ptr, int type,
61 tcg_target_long value, tcg_target_long addend)
62{
63 value += addend;
64 switch(type) {
65 case R_386_32:
66 *(uint32_t *)code_ptr = value;
67 break;
68 case R_386_PC32:
69 *(uint32_t *)code_ptr = value - (long)code_ptr;
70 break;
71 default:
72 tcg_abort();
73 }
74}
75
76#ifdef VBOX
77/* emits stack alignment checks for strict builds. */
78DECLINLINE(void) tcg_gen_stack_alignment_check(TCGContext *s)
79{
80# if defined(RT_STRICT) && defined(RT_OS_DARWIN) /** @todo all OSes? */
81 tcg_out8(s, 0xf7); tcg_out8(s, 0xc4); /* test %esp, 1fh */
82 tcg_out32(s, TCG_TARGET_STACK_ALIGN - 1);
83 tcg_out8(s, 0x74); /* jz imm8 */
84 tcg_out8(s, 1); /* $+3 (over int3) */
85 tcg_out8(s, 0xcc); /* int3 */
86# else
87 NOREF(s);
88# endif
89}
90#endif /* VBOX */
91
92/* maximum number of register used for input function arguments */
93#ifndef VBOX
94static inline int tcg_target_get_call_iarg_regs_count(int flags)
95#else /* VBOX */
96DECLINLINE(int) tcg_target_get_call_iarg_regs_count(int flags)
97#endif /* VBOX */
98{
99 flags &= TCG_CALL_TYPE_MASK;
100 switch(flags) {
101 case TCG_CALL_TYPE_STD:
102 return 0;
103 case TCG_CALL_TYPE_REGPARM_1:
104 case TCG_CALL_TYPE_REGPARM_2:
105 case TCG_CALL_TYPE_REGPARM:
106 return flags - TCG_CALL_TYPE_REGPARM_1 + 1;
107 default:
108 tcg_abort();
109 }
110}
111
112/* parse target specific constraints */
113static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
114{
115 const char *ct_str;
116
117 ct_str = *pct_str;
118 switch(ct_str[0]) {
119 case 'a':
120 ct->ct |= TCG_CT_REG;
121 tcg_regset_set_reg(ct->u.regs, TCG_REG_EAX);
122 break;
123 case 'b':
124 ct->ct |= TCG_CT_REG;
125 tcg_regset_set_reg(ct->u.regs, TCG_REG_EBX);
126 break;
127 case 'c':
128 ct->ct |= TCG_CT_REG;
129 tcg_regset_set_reg(ct->u.regs, TCG_REG_ECX);
130 break;
131 case 'd':
132 ct->ct |= TCG_CT_REG;
133 tcg_regset_set_reg(ct->u.regs, TCG_REG_EDX);
134 break;
135 case 'S':
136 ct->ct |= TCG_CT_REG;
137 tcg_regset_set_reg(ct->u.regs, TCG_REG_ESI);
138 break;
139 case 'D':
140 ct->ct |= TCG_CT_REG;
141 tcg_regset_set_reg(ct->u.regs, TCG_REG_EDI);
142 break;
143 case 'q':
144 ct->ct |= TCG_CT_REG;
145 tcg_regset_set32(ct->u.regs, 0, 0xf);
146 break;
147 case 'r':
148 ct->ct |= TCG_CT_REG;
149 tcg_regset_set32(ct->u.regs, 0, 0xff);
150 break;
151
152 /* qemu_ld/st address constraint */
153 case 'L':
154 ct->ct |= TCG_CT_REG;
155 tcg_regset_set32(ct->u.regs, 0, 0xff);
156 tcg_regset_reset_reg(ct->u.regs, TCG_REG_EAX);
157 tcg_regset_reset_reg(ct->u.regs, TCG_REG_EDX);
158 break;
159 default:
160 return -1;
161 }
162 ct_str++;
163 *pct_str = ct_str;
164 return 0;
165}
166
167/* test if a constant matches the constraint */
168#ifndef VBOX
169static inline int tcg_target_const_match(tcg_target_long val,
170#else /* VBOX */
171DECLINLINE(int) tcg_target_const_match(tcg_target_long val,
172#endif /* VBOX */
173 const TCGArgConstraint *arg_ct)
174{
175 int ct;
176 ct = arg_ct->ct;
177 if (ct & TCG_CT_CONST)
178 return 1;
179 else
180 return 0;
181}
182
183#define ARITH_ADD 0
184#define ARITH_OR 1
185#define ARITH_ADC 2
186#define ARITH_SBB 3
187#define ARITH_AND 4
188#define ARITH_SUB 5
189#define ARITH_XOR 6
190#define ARITH_CMP 7
191
192#define SHIFT_SHL 4
193#define SHIFT_SHR 5
194#define SHIFT_SAR 7
195
196#define JCC_JMP (-1)
197#define JCC_JO 0x0
198#define JCC_JNO 0x1
199#define JCC_JB 0x2
200#define JCC_JAE 0x3
201#define JCC_JE 0x4
202#define JCC_JNE 0x5
203#define JCC_JBE 0x6
204#define JCC_JA 0x7
205#define JCC_JS 0x8
206#define JCC_JNS 0x9
207#define JCC_JP 0xa
208#define JCC_JNP 0xb
209#define JCC_JL 0xc
210#define JCC_JGE 0xd
211#define JCC_JLE 0xe
212#define JCC_JG 0xf
213
214#define P_EXT 0x100 /* 0x0f opcode prefix */
215
216#if !defined(VBOX) || !defined(_MSC_VER)
217static const uint8_t tcg_cond_to_jcc[10] = {
218 [TCG_COND_EQ] = JCC_JE,
219 [TCG_COND_NE] = JCC_JNE,
220 [TCG_COND_LT] = JCC_JL,
221 [TCG_COND_GE] = JCC_JGE,
222 [TCG_COND_LE] = JCC_JLE,
223 [TCG_COND_GT] = JCC_JG,
224 [TCG_COND_LTU] = JCC_JB,
225 [TCG_COND_GEU] = JCC_JAE,
226 [TCG_COND_LEU] = JCC_JBE,
227 [TCG_COND_GTU] = JCC_JA,
228};
229#else
230/* Fortunately, ordering is right */
231static const uint8_t tcg_cond_to_jcc[10] = {
232 JCC_JE,
233 JCC_JNE,
234 JCC_JL,
235 JCC_JGE,
236 JCC_JLE,
237 JCC_JG,
238 JCC_JB,
239 JCC_JAE,
240 JCC_JBE,
241 JCC_JA,
242};
243#endif
244
245#ifndef VBOX
246static inline void tcg_out_opc(TCGContext *s, int opc)
247#else /* VBOX */
248DECLINLINE(void) tcg_out_opc(TCGContext *s, int opc)
249#endif /* VBOX */
250{
251 if (opc & P_EXT)
252 tcg_out8(s, 0x0f);
253 tcg_out8(s, opc);
254}
255
256#ifndef VBOX
257static inline void tcg_out_modrm(TCGContext *s, int opc, int r, int rm)
258#else /* VBOX */
259DECLINLINE(void) tcg_out_modrm(TCGContext *s, int opc, int r, int rm)
260#endif /* VBOX */
261{
262 tcg_out_opc(s, opc);
263 tcg_out8(s, 0xc0 | (r << 3) | rm);
264}
265
266/* rm == -1 means no register index */
267#ifndef VBOX
268static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm,
269#else /* VBOX */
270DECLINLINE(void) tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm,
271#endif /* VBOX */
272 int32_t offset)
273{
274 tcg_out_opc(s, opc);
275 if (rm == -1) {
276 tcg_out8(s, 0x05 | (r << 3));
277 tcg_out32(s, offset);
278 } else if (offset == 0 && rm != TCG_REG_EBP) {
279 if (rm == TCG_REG_ESP) {
280 tcg_out8(s, 0x04 | (r << 3));
281 tcg_out8(s, 0x24);
282 } else {
283 tcg_out8(s, 0x00 | (r << 3) | rm);
284 }
285 } else if ((int8_t)offset == offset) {
286 if (rm == TCG_REG_ESP) {
287 tcg_out8(s, 0x44 | (r << 3));
288 tcg_out8(s, 0x24);
289 } else {
290 tcg_out8(s, 0x40 | (r << 3) | rm);
291 }
292 tcg_out8(s, offset);
293 } else {
294 if (rm == TCG_REG_ESP) {
295 tcg_out8(s, 0x84 | (r << 3));
296 tcg_out8(s, 0x24);
297 } else {
298 tcg_out8(s, 0x80 | (r << 3) | rm);
299 }
300 tcg_out32(s, offset);
301 }
302}
303
304#ifndef VBOX
305static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
306#else /* VBOX */
307DECLINLINE(void) tcg_out_mov(TCGContext *s, int ret, int arg)
308#endif /* VBOX */
309{
310 if (arg != ret)
311 tcg_out_modrm(s, 0x8b, ret, arg);
312}
313
314#ifndef VBOX
315static inline void tcg_out_movi(TCGContext *s, TCGType type,
316#else /* VBOX */
317DECLINLINE(void) tcg_out_movi(TCGContext *s, TCGType type,
318#endif /* VBOX */
319 int ret, int32_t arg)
320{
321 if (arg == 0) {
322 /* xor r0,r0 */
323 tcg_out_modrm(s, 0x01 | (ARITH_XOR << 3), ret, ret);
324 } else {
325 tcg_out8(s, 0xb8 + ret);
326 tcg_out32(s, arg);
327 }
328}
329
330#ifndef VBOX
331static inline void tcg_out_push(TCGContext *s, int reg)
332#else /* VBOX */
333DECLINLINE(void) tcg_out_push(TCGContext *s, int reg)
334#endif /* VBOX */
335{
336 tcg_out_opc(s, 0x50 + reg);
337}
338
339#ifndef VBOX
340static inline void tcg_out_pop(TCGContext *s, int reg)
341#else /* VBOX */
342DECLINLINE(void) tcg_out_pop(TCGContext *s, int reg)
343#endif /* VBOX */
344{
345 tcg_out_opc(s, 0x58 + reg);
346}
347
348#ifndef VBOX
349static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret,
350#else /* VBOX */
351DECLINLINE(void) tcg_out_ld(TCGContext *s, TCGType type, int ret,
352#endif /* VBOX */
353 int arg1, tcg_target_long arg2)
354{
355 /* movl */
356 tcg_out_modrm_offset(s, 0x8b, ret, arg1, arg2);
357}
358
359#ifndef VBOX
360static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
361#else /* VBOX */
362DECLINLINE(void) tcg_out_st(TCGContext *s, TCGType type, int arg,
363#endif /* VBOX */
364 int arg1, tcg_target_long arg2)
365{
366 /* movl */
367 tcg_out_modrm_offset(s, 0x89, arg, arg1, arg2);
368}
369
370#ifndef VBOX
371static inline void tgen_arithi(TCGContext *s, int c, int r0, int32_t val)
372#else /* VBOX */
373DECLINLINE(void) tgen_arithi(TCGContext *s, int c, int r0, int32_t val)
374#endif /* VBOX */
375{
376 if (val == (int8_t)val) {
377 tcg_out_modrm(s, 0x83, c, r0);
378 tcg_out8(s, val);
379 } else {
380 tcg_out_modrm(s, 0x81, c, r0);
381 tcg_out32(s, val);
382 }
383}
384
385void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
386{
387 if (val != 0)
388 tgen_arithi(s, ARITH_ADD, reg, val);
389}
390
391static void tcg_out_jxx(TCGContext *s, int opc, int label_index)
392{
393 int32_t val, val1;
394 TCGLabel *l = &s->labels[label_index];
395
396 if (l->has_value) {
397 val = l->u.value - (tcg_target_long)s->code_ptr;
398 val1 = val - 2;
399 if ((int8_t)val1 == val1) {
400 if (opc == -1)
401 tcg_out8(s, 0xeb);
402 else
403 tcg_out8(s, 0x70 + opc);
404 tcg_out8(s, val1);
405 } else {
406 if (opc == -1) {
407 tcg_out8(s, 0xe9);
408 tcg_out32(s, val - 5);
409 } else {
410 tcg_out8(s, 0x0f);
411 tcg_out8(s, 0x80 + opc);
412 tcg_out32(s, val - 6);
413 }
414 }
415 } else {
416 if (opc == -1) {
417 tcg_out8(s, 0xe9);
418 } else {
419 tcg_out8(s, 0x0f);
420 tcg_out8(s, 0x80 + opc);
421 }
422 tcg_out_reloc(s, s->code_ptr, R_386_PC32, label_index, -4);
423 s->code_ptr += 4;
424 }
425}
426
427static void tcg_out_brcond(TCGContext *s, int cond,
428 TCGArg arg1, TCGArg arg2, int const_arg2,
429 int label_index)
430{
431 if (const_arg2) {
432 if (arg2 == 0) {
433 /* test r, r */
434 tcg_out_modrm(s, 0x85, arg1, arg1);
435 } else {
436 tgen_arithi(s, ARITH_CMP, arg1, arg2);
437 }
438 } else {
439 tcg_out_modrm(s, 0x01 | (ARITH_CMP << 3), arg2, arg1);
440 }
441 tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index);
442}
443
444#ifdef VBOX
445DECLINLINE(void)
446tcg_out_long_call(TCGContext *s, void* dst)
447{
448 intptr_t disp;
449# ifdef VBOX
450 tcg_gen_stack_alignment_check(s);
451# endif
452 disp = (uintptr_t)dst - (uintptr_t)s->code_ptr - 5;
453 tcg_out8(s, 0xe8); /* call disp32 */
454 tcg_out32(s, disp); /* disp32 */
455}
456DECLINLINE(void)
457tcg_out_long_jmp(TCGContext *s, void* dst)
458{
459 intptr_t disp = (uintptr_t)dst - (uintptr_t)s->code_ptr - 5;
460 tcg_out8(s, 0xe9); /* jmp disp32 */
461 tcg_out32(s, disp); /* disp32 */
462}
463#endif /* VBOX */
464
465
466/* XXX: we implement it at the target level to avoid having to
467 handle cross basic blocks temporaries */
468static void tcg_out_brcond2(TCGContext *s,
469 const TCGArg *args, const int *const_args)
470{
471 int label_next;
472 label_next = gen_new_label();
473 switch(args[4]) {
474 case TCG_COND_EQ:
475 tcg_out_brcond(s, TCG_COND_NE, args[0], args[2], const_args[2], label_next);
476 tcg_out_brcond(s, TCG_COND_EQ, args[1], args[3], const_args[3], args[5]);
477 break;
478 case TCG_COND_NE:
479 tcg_out_brcond(s, TCG_COND_NE, args[0], args[2], const_args[2], args[5]);
480 tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], args[5]);
481 break;
482 case TCG_COND_LT:
483 tcg_out_brcond(s, TCG_COND_LT, args[1], args[3], const_args[3], args[5]);
484 tcg_out_jxx(s, JCC_JNE, label_next);
485 tcg_out_brcond(s, TCG_COND_LTU, args[0], args[2], const_args[2], args[5]);
486 break;
487 case TCG_COND_LE:
488 tcg_out_brcond(s, TCG_COND_LT, args[1], args[3], const_args[3], args[5]);
489 tcg_out_jxx(s, JCC_JNE, label_next);
490 tcg_out_brcond(s, TCG_COND_LEU, args[0], args[2], const_args[2], args[5]);
491 break;
492 case TCG_COND_GT:
493 tcg_out_brcond(s, TCG_COND_GT, args[1], args[3], const_args[3], args[5]);
494 tcg_out_jxx(s, JCC_JNE, label_next);
495 tcg_out_brcond(s, TCG_COND_GTU, args[0], args[2], const_args[2], args[5]);
496 break;
497 case TCG_COND_GE:
498 tcg_out_brcond(s, TCG_COND_GT, args[1], args[3], const_args[3], args[5]);
499 tcg_out_jxx(s, JCC_JNE, label_next);
500 tcg_out_brcond(s, TCG_COND_GEU, args[0], args[2], const_args[2], args[5]);
501 break;
502 case TCG_COND_LTU:
503 tcg_out_brcond(s, TCG_COND_LTU, args[1], args[3], const_args[3], args[5]);
504 tcg_out_jxx(s, JCC_JNE, label_next);
505 tcg_out_brcond(s, TCG_COND_LTU, args[0], args[2], const_args[2], args[5]);
506 break;
507 case TCG_COND_LEU:
508 tcg_out_brcond(s, TCG_COND_LTU, args[1], args[3], const_args[3], args[5]);
509 tcg_out_jxx(s, JCC_JNE, label_next);
510 tcg_out_brcond(s, TCG_COND_LEU, args[0], args[2], const_args[2], args[5]);
511 break;
512 case TCG_COND_GTU:
513 tcg_out_brcond(s, TCG_COND_GTU, args[1], args[3], const_args[3], args[5]);
514 tcg_out_jxx(s, JCC_JNE, label_next);
515 tcg_out_brcond(s, TCG_COND_GTU, args[0], args[2], const_args[2], args[5]);
516 break;
517 case TCG_COND_GEU:
518 tcg_out_brcond(s, TCG_COND_GTU, args[1], args[3], const_args[3], args[5]);
519 tcg_out_jxx(s, JCC_JNE, label_next);
520 tcg_out_brcond(s, TCG_COND_GEU, args[0], args[2], const_args[2], args[5]);
521 break;
522 default:
523 tcg_abort();
524 }
525 tcg_out_label(s, label_next, (tcg_target_long)s->code_ptr);
526}
527
528#if defined(CONFIG_SOFTMMU)
529
530#include "../../softmmu_defs.h"
531
532static void *qemu_ld_helpers[4] = {
533 __ldb_mmu,
534 __ldw_mmu,
535 __ldl_mmu,
536 __ldq_mmu,
537};
538
539static void *qemu_st_helpers[4] = {
540 __stb_mmu,
541 __stw_mmu,
542 __stl_mmu,
543 __stq_mmu,
544};
545#endif
546
547#if defined(VBOX) && defined(REM_PHYS_ADDR_IN_TLB)
548static void *vbox_ld_helpers[] = {
549 __ldub_vbox_phys,
550 __lduw_vbox_phys,
551 __ldul_vbox_phys,
552 __ldq_vbox_phys,
553 __ldb_vbox_phys,
554 __ldw_vbox_phys,
555 __ldl_vbox_phys,
556 __ldq_vbox_phys,
557};
558
559static void *vbox_st_helpers[] = {
560 __stb_vbox_phys,
561 __stw_vbox_phys,
562 __stl_vbox_phys,
563 __stq_vbox_phys
564};
565
566static void tcg_out_vbox_phys_read(TCGContext *s, int index,
567 int addr_reg,
568 int data_reg, int data_reg2)
569{
570 int useReg2 = ((index & 3) == 3);
571
572 /** @todo: should we make phys addess accessors fastcalls - probably not a big deal */
573 /* out parameter (address), note that phys address is always 64-bit */
574 AssertMsg(sizeof(RTGCPHYS) == 8, ("Physical address must be 64-bits, update caller\n"));
575
576#if 0
577 tcg_out8(s, 0x6a); tcg_out8(s, 0x00); /* push $0 */
578 tcg_out_push(s, addr_reg);
579#else
580 /* mov addr_reg, %eax */
581 tcg_out_mov(s, TCG_REG_EAX, addr_reg);
582#endif
583
584 tcg_out_long_call(s, vbox_ld_helpers[index]);
585
586 /* mov %eax, data_reg */
587 tcg_out_mov(s, data_reg, TCG_REG_EAX);
588
589 /* returned 64-bit value */
590 if (useReg2)
591 tcg_out_mov(s, data_reg2, TCG_REG_EDX);
592}
593
594static void tcg_out_vbox_phys_write(TCGContext *s, int index,
595 int addr_reg,
596 int val_reg, int val_reg2) {
597 int useReg2 = ((index & 3) == 3);
598
599#if 0
600 /* out parameter (value2) */
601 if (useReg2)
602 tcg_out_push(s, val_reg2);
603 /* out parameter (value) */
604 tcg_out_push(s, val_reg);
605 /* out parameter (address), note that phys address is always 64-bit */
606 AssertMsg(sizeof(RTGCPHYS) == 8, ("Physical address must be 64-bits, update caller\n"));
607 tcg_out8(s, 0x6a); tcg_out8(s, 0x00); /* push $0 */
608 tcg_out_push(s, addr_reg);
609#else
610 Assert(val_reg != TCG_REG_EAX && (!useReg2 || (val_reg2 != TCG_REG_EAX)));
611 /* mov addr_reg, %eax */
612 tcg_out_mov(s, TCG_REG_EAX, addr_reg);
613 Assert(!useReg2 || (val_reg2 != TCG_REG_EDX));
614 /* mov val_reg, %edx */
615 tcg_out_mov(s, TCG_REG_EDX, val_reg);
616 if (useReg2)
617 tcg_out_mov(s, TCG_REG_ECX, val_reg2);
618
619#endif
620 /* call it */
621 tcg_out_long_call(s, vbox_st_helpers[index]);
622
623 /* clean stack after us */
624#if 0
625 tcg_out_addi(s, TCG_REG_ESP, 8 + (useReg2 ? 8 : 4));
626# endif
627}
628
629#endif /* defined(VBOX) && defined(REM_PHYS_ADDR_IN_TLB) */
630
631/* XXX: qemu_ld and qemu_st could be modified to clobber only EDX and
632 EAX. It will be useful once fixed registers globals are less
633 common. */
634static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
635 int opc)
636{
637 int addr_reg, data_reg, data_reg2, r0, r1, mem_index, s_bits, bswap;
638#if defined(CONFIG_SOFTMMU)
639 uint8_t *label1_ptr, *label2_ptr;
640#endif
641#if TARGET_LONG_BITS == 64
642#if defined(CONFIG_SOFTMMU)
643 uint8_t *label3_ptr;
644#endif
645 int addr_reg2;
646#endif
647
648 data_reg = *args++;
649 if (opc == 3)
650 data_reg2 = *args++;
651 else
652 data_reg2 = 0;
653 addr_reg = *args++;
654#if TARGET_LONG_BITS == 64
655 addr_reg2 = *args++;
656#endif
657 mem_index = *args;
658 s_bits = opc & 3;
659
660 r0 = TCG_REG_EAX;
661 r1 = TCG_REG_EDX;
662
663#if defined(CONFIG_SOFTMMU)
664 tcg_out_mov(s, r1, addr_reg);
665
666 tcg_out_mov(s, r0, addr_reg);
667
668 tcg_out_modrm(s, 0xc1, 5, r1); /* shr $x, r1 */
669 tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
670
671 tcg_out_modrm(s, 0x81, 4, r0); /* andl $x, r0 */
672 tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
673
674 tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
675 tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
676
677#ifndef VBOX
678 tcg_out_opc(s, 0x8d); /* lea offset(r1, %ebp), r1 */
679 tcg_out8(s, 0x80 | (r1 << 3) | 0x04);
680 tcg_out8(s, (5 << 3) | r1);
681 tcg_out32(s, offsetof(CPUState, tlb_table[mem_index][0].addr_read));
682#else
683 tcg_out_opc(s, 0x8d); /* lea offset(r1, env), r1 */
684 tcg_out8(s, 0x80 | (r1 << 3) | 0x04);
685 tcg_out8(s, (TCG_AREG0 << 3) | r1);
686 tcg_out32(s, offsetof(CPUState, tlb_table[mem_index][0].addr_read));
687#endif
688
689 /* cmp 0(r1), r0 */
690 tcg_out_modrm_offset(s, 0x3b, r0, r1, 0);
691
692 tcg_out_mov(s, r0, addr_reg);
693
694#if TARGET_LONG_BITS == 32
695 /* je label1 */
696 tcg_out8(s, 0x70 + JCC_JE);
697 label1_ptr = s->code_ptr;
698 s->code_ptr++;
699#else
700 /* jne label3 */
701 tcg_out8(s, 0x70 + JCC_JNE);
702 label3_ptr = s->code_ptr;
703 s->code_ptr++;
704
705 /* cmp 4(r1), addr_reg2 */
706 tcg_out_modrm_offset(s, 0x3b, addr_reg2, r1, 4);
707
708 /* je label1 */
709 tcg_out8(s, 0x70 + JCC_JE);
710 label1_ptr = s->code_ptr;
711 s->code_ptr++;
712
713 /* label3: */
714 *label3_ptr = s->code_ptr - label3_ptr - 1;
715#endif
716
717 /* XXX: move that code at the end of the TB */
718#if TARGET_LONG_BITS == 32
719 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_EDX, mem_index);
720#else
721 tcg_out_mov(s, TCG_REG_EDX, addr_reg2);
722 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_ECX, mem_index);
723#endif
724#ifdef VBOX
725 tcg_gen_stack_alignment_check(s);
726#endif
727 tcg_out8(s, 0xe8);
728 tcg_out32(s, (tcg_target_long)qemu_ld_helpers[s_bits] -
729 (tcg_target_long)s->code_ptr - 4);
730
731 switch(opc) {
732 case 0 | 4:
733 /* movsbl */
734 tcg_out_modrm(s, 0xbe | P_EXT, data_reg, TCG_REG_EAX);
735 break;
736 case 1 | 4:
737 /* movswl */
738 tcg_out_modrm(s, 0xbf | P_EXT, data_reg, TCG_REG_EAX);
739 break;
740 case 0:
741 case 1:
742 case 2:
743 default:
744 tcg_out_mov(s, data_reg, TCG_REG_EAX);
745 break;
746 case 3:
747 if (data_reg == TCG_REG_EDX) {
748 tcg_out_opc(s, 0x90 + TCG_REG_EDX); /* xchg %edx, %eax */
749 tcg_out_mov(s, data_reg2, TCG_REG_EAX);
750 } else {
751 tcg_out_mov(s, data_reg, TCG_REG_EAX);
752 tcg_out_mov(s, data_reg2, TCG_REG_EDX);
753 }
754 break;
755 }
756
757 /* jmp label2 */
758 tcg_out8(s, 0xeb);
759 label2_ptr = s->code_ptr;
760 s->code_ptr++;
761
762 /* label1: */
763 *label1_ptr = s->code_ptr - label1_ptr - 1;
764
765 /* add x(r1), r0 */
766 tcg_out_modrm_offset(s, 0x03, r0, r1, offsetof(CPUTLBEntry, addend) -
767 offsetof(CPUTLBEntry, addr_read));
768#else
769 r0 = addr_reg;
770#endif
771
772#if !defined(VBOX) || !defined(REM_PHYS_ADDR_IN_TLB)
773#ifdef TARGET_WORDS_BIGENDIAN
774 bswap = 1;
775#else
776 bswap = 0;
777#endif
778 switch(opc) {
779 case 0:
780 /* movzbl */
781 tcg_out_modrm_offset(s, 0xb6 | P_EXT, data_reg, r0, 0);
782 break;
783 case 0 | 4:
784 /* movsbl */
785 tcg_out_modrm_offset(s, 0xbe | P_EXT, data_reg, r0, 0);
786 break;
787 case 1:
788 /* movzwl */
789 tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, 0);
790 if (bswap) {
791 /* rolw $8, data_reg */
792 tcg_out8(s, 0x66);
793 tcg_out_modrm(s, 0xc1, 0, data_reg);
794 tcg_out8(s, 8);
795 }
796 break;
797 case 1 | 4:
798 /* movswl */
799 tcg_out_modrm_offset(s, 0xbf | P_EXT, data_reg, r0, 0);
800 if (bswap) {
801 /* rolw $8, data_reg */
802 tcg_out8(s, 0x66);
803 tcg_out_modrm(s, 0xc1, 0, data_reg);
804 tcg_out8(s, 8);
805
806 /* movswl data_reg, data_reg */
807 tcg_out_modrm(s, 0xbf | P_EXT, data_reg, data_reg);
808 }
809 break;
810 case 2:
811 /* movl (r0), data_reg */
812 tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 0);
813 if (bswap) {
814 /* bswap */
815 tcg_out_opc(s, (0xc8 + data_reg) | P_EXT);
816 }
817 break;
818 case 3:
819 /* XXX: could be nicer */
820 if (r0 == data_reg) {
821 r1 = TCG_REG_EDX;
822 if (r1 == data_reg)
823 r1 = TCG_REG_EAX;
824 tcg_out_mov(s, r1, r0);
825 r0 = r1;
826 }
827 if (!bswap) {
828 tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 0);
829 tcg_out_modrm_offset(s, 0x8b, data_reg2, r0, 4);
830 } else {
831 tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 4);
832 tcg_out_opc(s, (0xc8 + data_reg) | P_EXT);
833
834 tcg_out_modrm_offset(s, 0x8b, data_reg2, r0, 0);
835 /* bswap */
836 tcg_out_opc(s, (0xc8 + data_reg2) | P_EXT);
837 }
838 break;
839 default:
840 tcg_abort();
841 }
842#else /* VBOX */
843 tcg_out_vbox_phys_read(s, opc, r0, data_reg, data_reg2);
844#endif
845
846
847#if defined(CONFIG_SOFTMMU)
848 /* label2: */
849 *label2_ptr = s->code_ptr - label2_ptr - 1;
850# ifdef VBOX
851 Assert((unsigned)(s->code_ptr - label2_ptr - 1) <= 127);
852# endif
853#endif
854}
855
856
857static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
858 int opc)
859{
860 int addr_reg, data_reg, data_reg2, r0, r1, mem_index, s_bits, bswap;
861#if defined(CONFIG_SOFTMMU)
862 uint8_t *label1_ptr, *label2_ptr;
863#endif
864#if TARGET_LONG_BITS == 64
865#if defined(CONFIG_SOFTMMU)
866 uint8_t *label3_ptr;
867#endif
868 int addr_reg2;
869#endif
870
871 data_reg = *args++;
872 if (opc == 3)
873 data_reg2 = *args++;
874 else
875 data_reg2 = 0;
876 addr_reg = *args++;
877#if TARGET_LONG_BITS == 64
878 addr_reg2 = *args++;
879#endif
880 mem_index = *args;
881
882 s_bits = opc;
883
884 r0 = TCG_REG_EAX;
885 r1 = TCG_REG_EDX;
886
887#if defined(CONFIG_SOFTMMU)
888 tcg_out_mov(s, r1, addr_reg);
889
890 tcg_out_mov(s, r0, addr_reg);
891
892 tcg_out_modrm(s, 0xc1, 5, r1); /* shr $x, r1 */
893 tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
894
895 tcg_out_modrm(s, 0x81, 4, r0); /* andl $x, r0 */
896 tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
897
898 tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
899 tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
900
901#ifndef VBOX
902 tcg_out_opc(s, 0x8d); /* lea offset(r1, %ebp), r1 */
903 tcg_out8(s, 0x80 | (r1 << 3) | 0x04);
904 tcg_out8(s, (5 << 3) | r1);
905 tcg_out32(s, offsetof(CPUState, tlb_table[mem_index][0].addr_write));
906#else
907 tcg_out_opc(s, 0x8d); /* lea offset(r1, env), r1 */
908 tcg_out8(s, 0x80 | (r1 << 3) | 0x04);
909 tcg_out8(s, (TCG_AREG0 << 3) | r1);
910 tcg_out32(s, offsetof(CPUState, tlb_table[mem_index][0].addr_write));
911#endif
912
913 /* cmp 0(r1), r0 */
914 tcg_out_modrm_offset(s, 0x3b, r0, r1, 0);
915
916 tcg_out_mov(s, r0, addr_reg);
917
918#if TARGET_LONG_BITS == 32
919 /* je label1 */
920 tcg_out8(s, 0x70 + JCC_JE);
921 label1_ptr = s->code_ptr;
922 s->code_ptr++;
923#else
924 /* jne label3 */
925 tcg_out8(s, 0x70 + JCC_JNE);
926 label3_ptr = s->code_ptr;
927 s->code_ptr++;
928
929 /* cmp 4(r1), addr_reg2 */
930 tcg_out_modrm_offset(s, 0x3b, addr_reg2, r1, 4);
931
932 /* je label1 */
933 tcg_out8(s, 0x70 + JCC_JE);
934 label1_ptr = s->code_ptr;
935 s->code_ptr++;
936
937 /* label3: */
938 *label3_ptr = s->code_ptr - label3_ptr - 1;
939#endif
940
941 /* XXX: move that code at the end of the TB */
942#if TARGET_LONG_BITS == 32
943 if (opc == 3) {
944 tcg_out_mov(s, TCG_REG_EDX, data_reg);
945 tcg_out_mov(s, TCG_REG_ECX, data_reg2);
946 tcg_out8(s, 0x6a); /* push Ib */
947 tcg_out8(s, mem_index);
948# ifdef VBOX
949 tcg_gen_stack_alignment_check(s);
950# endif
951 tcg_out8(s, 0xe8);
952 tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] -
953 (tcg_target_long)s->code_ptr - 4);
954 tcg_out_addi(s, TCG_REG_ESP, 4);
955 } else {
956 switch(opc) {
957 case 0:
958 /* movzbl */
959 tcg_out_modrm(s, 0xb6 | P_EXT, TCG_REG_EDX, data_reg);
960 break;
961 case 1:
962 /* movzwl */
963 tcg_out_modrm(s, 0xb7 | P_EXT, TCG_REG_EDX, data_reg);
964 break;
965 case 2:
966 tcg_out_mov(s, TCG_REG_EDX, data_reg);
967 break;
968 }
969 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_ECX, mem_index);
970# ifdef VBOX
971 tcg_gen_stack_alignment_check(s);
972# endif
973 tcg_out8(s, 0xe8);
974 tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] -
975 (tcg_target_long)s->code_ptr - 4);
976 }
977#else
978 if (opc == 3) {
979 tcg_out_mov(s, TCG_REG_EDX, addr_reg2);
980 tcg_out8(s, 0x6a); /* push Ib */
981 tcg_out8(s, mem_index);
982 tcg_out_opc(s, 0x50 + data_reg2); /* push */
983 tcg_out_opc(s, 0x50 + data_reg); /* push */
984# ifdef VBOX
985 tcg_gen_stack_alignment_check(s);
986# endif
987 tcg_out8(s, 0xe8);
988 tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] -
989 (tcg_target_long)s->code_ptr - 4);
990 tcg_out_addi(s, TCG_REG_ESP, 12);
991 } else {
992 tcg_out_mov(s, TCG_REG_EDX, addr_reg2);
993 switch(opc) {
994 case 0:
995 /* movzbl */
996 tcg_out_modrm(s, 0xb6 | P_EXT, TCG_REG_ECX, data_reg);
997 break;
998 case 1:
999 /* movzwl */
1000 tcg_out_modrm(s, 0xb7 | P_EXT, TCG_REG_ECX, data_reg);
1001 break;
1002 case 2:
1003 tcg_out_mov(s, TCG_REG_ECX, data_reg);
1004 break;
1005 }
1006# if defined(VBOX) && defined(RT_OS_DARWIN)
1007 tgen_arithi(s, ARITH_SUB, TCG_REG_ESP, 12); /** @todo FIXME: This is not 100% correct (assumes a bunch of things), but it works around the current issue it seems... */
1008# endif
1009 tcg_out8(s, 0x6a); /* push Ib */
1010 tcg_out8(s, mem_index);
1011# ifdef VBOX
1012 tcg_gen_stack_alignment_check(s);
1013# endif
1014
1015 tcg_out8(s, 0xe8);
1016 tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] -
1017 (tcg_target_long)s->code_ptr - 4);
1018# if defined(VBOX) && defined(RT_OS_DARWIN)
1019 tcg_out_addi(s, TCG_REG_ESP, 12+4);
1020# else
1021 tcg_out_addi(s, TCG_REG_ESP, 4);
1022# endif
1023 }
1024#endif
1025
1026 /* jmp label2 */
1027 tcg_out8(s, 0xeb);
1028 label2_ptr = s->code_ptr;
1029 s->code_ptr++;
1030
1031 /* label1: */
1032 *label1_ptr = s->code_ptr - label1_ptr - 1;
1033
1034 /* add x(r1), r0 */
1035 tcg_out_modrm_offset(s, 0x03, r0, r1, offsetof(CPUTLBEntry, addend) -
1036 offsetof(CPUTLBEntry, addr_write));
1037#else
1038 r0 = addr_reg;
1039#endif
1040
1041#if !defined(VBOX) || !defined(REM_PHYS_ADDR_IN_TLB)
1042#ifdef TARGET_WORDS_BIGENDIAN
1043 bswap = 1;
1044#else
1045 bswap = 0;
1046#endif
1047 switch(opc) {
1048 case 0:
1049 /* movb */
1050 tcg_out_modrm_offset(s, 0x88, data_reg, r0, 0);
1051 break;
1052 case 1:
1053 if (bswap) {
1054 tcg_out_mov(s, r1, data_reg);
1055 tcg_out8(s, 0x66); /* rolw $8, %ecx */
1056 tcg_out_modrm(s, 0xc1, 0, r1);
1057 tcg_out8(s, 8);
1058 data_reg = r1;
1059 }
1060 /* movw */
1061 tcg_out8(s, 0x66);
1062 tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
1063 break;
1064 case 2:
1065 if (bswap) {
1066 tcg_out_mov(s, r1, data_reg);
1067 /* bswap data_reg */
1068 tcg_out_opc(s, (0xc8 + r1) | P_EXT);
1069 data_reg = r1;
1070 }
1071 /* movl */
1072 tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
1073 break;
1074 case 3:
1075 if (bswap) {
1076 tcg_out_mov(s, r1, data_reg2);
1077 /* bswap data_reg */
1078 tcg_out_opc(s, (0xc8 + r1) | P_EXT);
1079 tcg_out_modrm_offset(s, 0x89, r1, r0, 0);
1080 tcg_out_mov(s, r1, data_reg);
1081 /* bswap data_reg */
1082 tcg_out_opc(s, (0xc8 + r1) | P_EXT);
1083 tcg_out_modrm_offset(s, 0x89, r1, r0, 4);
1084 } else {
1085 tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
1086 tcg_out_modrm_offset(s, 0x89, data_reg2, r0, 4);
1087 }
1088 break;
1089 default:
1090 tcg_abort();
1091 }
1092#else
1093 tcg_out_vbox_phys_write(s, opc, r0, data_reg, data_reg2);
1094#endif
1095
1096#if defined(CONFIG_SOFTMMU)
1097 /* label2: */
1098 *label2_ptr = s->code_ptr - label2_ptr - 1;
1099# ifdef VBOX
1100 Assert((unsigned)(s->code_ptr - label2_ptr - 1) <= 127);
1101# endif
1102#endif
1103}
1104
1105#ifndef VBOX
1106static inline void tcg_out_op(TCGContext *s, int opc,
1107#else /* VBOX */
1108DECLINLINE(void) tcg_out_op(TCGContext *s, int opc,
1109#endif /* VBOX */
1110 const TCGArg *args, const int *const_args)
1111{
1112 int c;
1113
1114 switch(opc) {
1115 case INDEX_op_exit_tb:
1116 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_EAX, args[0]);
1117 tcg_out8(s, 0xe9); /* jmp tb_ret_addr */
1118 tcg_out32(s, tb_ret_addr - s->code_ptr - 4);
1119 break;
1120 case INDEX_op_goto_tb:
1121 if (s->tb_jmp_offset) {
1122 /* direct jump method */
1123 tcg_out8(s, 0xe9); /* jmp im */
1124 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1125 tcg_out32(s, 0);
1126 } else {
1127 /* indirect jump method */
1128 /* jmp Ev */
1129 tcg_out_modrm_offset(s, 0xff, 4, -1,
1130 (tcg_target_long)(s->tb_next + args[0]));
1131 }
1132 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1133 break;
1134 case INDEX_op_call:
1135#ifdef VBOX
1136 tcg_gen_stack_alignment_check(s);
1137#endif
1138 if (const_args[0]) {
1139 tcg_out8(s, 0xe8);
1140 tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4);
1141 } else {
1142 tcg_out_modrm(s, 0xff, 2, args[0]);
1143 }
1144 break;
1145 case INDEX_op_jmp:
1146 if (const_args[0]) {
1147 tcg_out8(s, 0xe9);
1148 tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4);
1149 } else {
1150 tcg_out_modrm(s, 0xff, 4, args[0]);
1151 }
1152 break;
1153 case INDEX_op_br:
1154 tcg_out_jxx(s, JCC_JMP, args[0]);
1155 break;
1156 case INDEX_op_movi_i32:
1157 tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
1158 break;
1159 case INDEX_op_ld8u_i32:
1160 /* movzbl */
1161 tcg_out_modrm_offset(s, 0xb6 | P_EXT, args[0], args[1], args[2]);
1162 break;
1163 case INDEX_op_ld8s_i32:
1164 /* movsbl */
1165 tcg_out_modrm_offset(s, 0xbe | P_EXT, args[0], args[1], args[2]);
1166 break;
1167 case INDEX_op_ld16u_i32:
1168 /* movzwl */
1169 tcg_out_modrm_offset(s, 0xb7 | P_EXT, args[0], args[1], args[2]);
1170 break;
1171 case INDEX_op_ld16s_i32:
1172 /* movswl */
1173 tcg_out_modrm_offset(s, 0xbf | P_EXT, args[0], args[1], args[2]);
1174 break;
1175 case INDEX_op_ld_i32:
1176 /* movl */
1177 tcg_out_modrm_offset(s, 0x8b, args[0], args[1], args[2]);
1178 break;
1179 case INDEX_op_st8_i32:
1180 /* movb */
1181 tcg_out_modrm_offset(s, 0x88, args[0], args[1], args[2]);
1182 break;
1183 case INDEX_op_st16_i32:
1184 /* movw */
1185 tcg_out8(s, 0x66);
1186 tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
1187 break;
1188 case INDEX_op_st_i32:
1189 /* movl */
1190 tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
1191 break;
1192 case INDEX_op_sub_i32:
1193 c = ARITH_SUB;
1194 goto gen_arith;
1195 case INDEX_op_and_i32:
1196 c = ARITH_AND;
1197 goto gen_arith;
1198 case INDEX_op_or_i32:
1199 c = ARITH_OR;
1200 goto gen_arith;
1201 case INDEX_op_xor_i32:
1202 c = ARITH_XOR;
1203 goto gen_arith;
1204 case INDEX_op_add_i32:
1205 c = ARITH_ADD;
1206 gen_arith:
1207 if (const_args[2]) {
1208 tgen_arithi(s, c, args[0], args[2]);
1209 } else {
1210 tcg_out_modrm(s, 0x01 | (c << 3), args[2], args[0]);
1211 }
1212 break;
1213 case INDEX_op_mul_i32:
1214 if (const_args[2]) {
1215 int32_t val;
1216 val = args[2];
1217 if (val == (int8_t)val) {
1218 tcg_out_modrm(s, 0x6b, args[0], args[0]);
1219 tcg_out8(s, val);
1220 } else {
1221 tcg_out_modrm(s, 0x69, args[0], args[0]);
1222 tcg_out32(s, val);
1223 }
1224 } else {
1225 tcg_out_modrm(s, 0xaf | P_EXT, args[0], args[2]);
1226 }
1227 break;
1228 case INDEX_op_mulu2_i32:
1229 tcg_out_modrm(s, 0xf7, 4, args[3]);
1230 break;
1231 case INDEX_op_div2_i32:
1232 tcg_out_modrm(s, 0xf7, 7, args[4]);
1233 break;
1234 case INDEX_op_divu2_i32:
1235 tcg_out_modrm(s, 0xf7, 6, args[4]);
1236 break;
1237 case INDEX_op_shl_i32:
1238 c = SHIFT_SHL;
1239 gen_shift32:
1240 if (const_args[2]) {
1241 if (args[2] == 1) {
1242 tcg_out_modrm(s, 0xd1, c, args[0]);
1243 } else {
1244 tcg_out_modrm(s, 0xc1, c, args[0]);
1245 tcg_out8(s, args[2]);
1246 }
1247 } else {
1248 tcg_out_modrm(s, 0xd3, c, args[0]);
1249 }
1250 break;
1251 case INDEX_op_shr_i32:
1252 c = SHIFT_SHR;
1253 goto gen_shift32;
1254 case INDEX_op_sar_i32:
1255 c = SHIFT_SAR;
1256 goto gen_shift32;
1257
1258 case INDEX_op_add2_i32:
1259 if (const_args[4])
1260 tgen_arithi(s, ARITH_ADD, args[0], args[4]);
1261 else
1262 tcg_out_modrm(s, 0x01 | (ARITH_ADD << 3), args[4], args[0]);
1263 if (const_args[5])
1264 tgen_arithi(s, ARITH_ADC, args[1], args[5]);
1265 else
1266 tcg_out_modrm(s, 0x01 | (ARITH_ADC << 3), args[5], args[1]);
1267 break;
1268 case INDEX_op_sub2_i32:
1269 if (const_args[4])
1270 tgen_arithi(s, ARITH_SUB, args[0], args[4]);
1271 else
1272 tcg_out_modrm(s, 0x01 | (ARITH_SUB << 3), args[4], args[0]);
1273 if (const_args[5])
1274 tgen_arithi(s, ARITH_SBB, args[1], args[5]);
1275 else
1276 tcg_out_modrm(s, 0x01 | (ARITH_SBB << 3), args[5], args[1]);
1277 break;
1278 case INDEX_op_brcond_i32:
1279 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], args[3]);
1280 break;
1281 case INDEX_op_brcond2_i32:
1282 tcg_out_brcond2(s, args, const_args);
1283 break;
1284
1285 case INDEX_op_qemu_ld8u:
1286 tcg_out_qemu_ld(s, args, 0);
1287 break;
1288 case INDEX_op_qemu_ld8s:
1289 tcg_out_qemu_ld(s, args, 0 | 4);
1290 break;
1291 case INDEX_op_qemu_ld16u:
1292 tcg_out_qemu_ld(s, args, 1);
1293 break;
1294 case INDEX_op_qemu_ld16s:
1295 tcg_out_qemu_ld(s, args, 1 | 4);
1296 break;
1297 case INDEX_op_qemu_ld32u:
1298 tcg_out_qemu_ld(s, args, 2);
1299 break;
1300 case INDEX_op_qemu_ld64:
1301 tcg_out_qemu_ld(s, args, 3);
1302 break;
1303
1304 case INDEX_op_qemu_st8:
1305 tcg_out_qemu_st(s, args, 0);
1306 break;
1307 case INDEX_op_qemu_st16:
1308 tcg_out_qemu_st(s, args, 1);
1309 break;
1310 case INDEX_op_qemu_st32:
1311 tcg_out_qemu_st(s, args, 2);
1312 break;
1313 case INDEX_op_qemu_st64:
1314 tcg_out_qemu_st(s, args, 3);
1315 break;
1316
1317 default:
1318 tcg_abort();
1319 }
1320}
1321
1322static const TCGTargetOpDef x86_op_defs[] = {
1323 { INDEX_op_exit_tb, {"", "" } },
1324 { INDEX_op_goto_tb, {"", "" } },
1325 { INDEX_op_call, { "ri", "", } },
1326 { INDEX_op_jmp, { "ri", ""} },
1327 { INDEX_op_br, {"", "" } },
1328 { INDEX_op_mov_i32, { "r", "r" } },
1329 { INDEX_op_movi_i32, { "r" } },
1330 { INDEX_op_ld8u_i32, { "r", "r" } },
1331 { INDEX_op_ld8s_i32, { "r", "r" } },
1332 { INDEX_op_ld16u_i32, { "r", "r" } },
1333 { INDEX_op_ld16s_i32, { "r", "r" } },
1334 { INDEX_op_ld_i32, { "r", "r" } },
1335 { INDEX_op_st8_i32, { "q", "r" } },
1336 { INDEX_op_st16_i32, { "r", "r" } },
1337 { INDEX_op_st_i32, { "r", "r" } },
1338
1339 { INDEX_op_add_i32, { "r", "0", "ri" } },
1340 { INDEX_op_sub_i32, { "r", "0", "ri" } },
1341 { INDEX_op_mul_i32, { "r", "0", "ri" } },
1342 { INDEX_op_mulu2_i32, { "a", "d", "a", "r" } },
1343 { INDEX_op_div2_i32, { "a", "d", "0", "1", "r" } },
1344 { INDEX_op_divu2_i32, { "a", "d", "0", "1", "r" } },
1345 { INDEX_op_and_i32, { "r", "0", "ri" } },
1346 { INDEX_op_or_i32, { "r", "0", "ri" } },
1347 { INDEX_op_xor_i32, { "r", "0", "ri" } },
1348
1349 { INDEX_op_shl_i32, { "r", "0", "ci" } },
1350 { INDEX_op_shr_i32, { "r", "0", "ci" } },
1351 { INDEX_op_sar_i32, { "r", "0", "ci" } },
1352
1353 { INDEX_op_brcond_i32, { "r", "ri" } },
1354
1355 { INDEX_op_add2_i32, { "r", "r", "0", "1", "ri", "ri" } },
1356 { INDEX_op_sub2_i32, { "r", "r", "0", "1", "ri", "ri" } },
1357 { INDEX_op_brcond2_i32, { "r", "r", "ri", "ri" } },
1358
1359#if TARGET_LONG_BITS == 32
1360 { INDEX_op_qemu_ld8u, { "r", "L" } },
1361 { INDEX_op_qemu_ld8s, { "r", "L" } },
1362 { INDEX_op_qemu_ld16u, { "r", "L" } },
1363 { INDEX_op_qemu_ld16s, { "r", "L" } },
1364 { INDEX_op_qemu_ld32u, { "r", "L" } },
1365 { INDEX_op_qemu_ld64, { "r", "r", "L" } },
1366
1367 { INDEX_op_qemu_st8, { "cb", "L" } },
1368 { INDEX_op_qemu_st16, { "L", "L" } },
1369 { INDEX_op_qemu_st32, { "L", "L" } },
1370 { INDEX_op_qemu_st64, { "L", "L", "L" } },
1371#else
1372 { INDEX_op_qemu_ld8u, { "r", "L", "L" } },
1373 { INDEX_op_qemu_ld8s, { "r", "L", "L" } },
1374 { INDEX_op_qemu_ld16u, { "r", "L", "L" } },
1375 { INDEX_op_qemu_ld16s, { "r", "L", "L" } },
1376 { INDEX_op_qemu_ld32u, { "r", "L", "L" } },
1377 { INDEX_op_qemu_ld64, { "r", "r", "L", "L" } },
1378
1379 { INDEX_op_qemu_st8, { "cb", "L", "L" } },
1380 { INDEX_op_qemu_st16, { "L", "L", "L" } },
1381 { INDEX_op_qemu_st32, { "L", "L", "L" } },
1382 { INDEX_op_qemu_st64, { "L", "L", "L", "L" } },
1383#endif
1384#ifndef VBOX
1385 { -1 },
1386#else
1387 { -1, {"", "", "", ""} },
1388#endif
1389};
1390
1391static int tcg_target_callee_save_regs[] = {
1392#ifndef VBOX
1393 /* TCG_REG_EBP, */ /* currently used for the global env, so no
1394 need to save */
1395 TCG_REG_EBX,
1396 TCG_REG_ESI,
1397 TCG_REG_EDI,
1398#else
1399 TCG_REG_EBP,
1400 TCG_REG_EBX,
1401 /* TCG_REG_ESI, */ /* currently used for the global env, so no
1402 need to save */
1403 TCG_REG_EDI,
1404#endif
1405};
1406
1407/* Generate global QEMU prologue and epilogue code */
1408void tcg_target_qemu_prologue(TCGContext *s)
1409{
1410 int i, frame_size, push_size, stack_addend;
1411
1412 /* TB prologue */
1413 /* save all callee saved registers */
1414 for(i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
1415 tcg_out_push(s, tcg_target_callee_save_regs[i]);
1416 }
1417 /* reserve some stack space */
1418 push_size = 4 + ARRAY_SIZE(tcg_target_callee_save_regs) * 4;
1419 frame_size = push_size + TCG_STATIC_CALL_ARGS_SIZE;
1420 frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
1421 ~(TCG_TARGET_STACK_ALIGN - 1);
1422 stack_addend = frame_size - push_size;
1423 tcg_out_addi(s, TCG_REG_ESP, -stack_addend);
1424# ifdef VBOX
1425 tcg_gen_stack_alignment_check(s);
1426# endif
1427
1428 tcg_out_modrm(s, 0xff, 4, TCG_REG_EAX); /* jmp *%eax */
1429
1430 /* TB epilogue */
1431 tb_ret_addr = s->code_ptr;
1432 tcg_out_addi(s, TCG_REG_ESP, stack_addend);
1433 for(i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) {
1434 tcg_out_pop(s, tcg_target_callee_save_regs[i]);
1435 }
1436 tcg_out8(s, 0xc3); /* ret */
1437}
1438
1439void tcg_target_init(TCGContext *s)
1440{
1441 /* fail safe */
1442 if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
1443 tcg_abort();
1444
1445 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xff);
1446 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1447 (1 << TCG_REG_EAX) |
1448 (1 << TCG_REG_EDX) |
1449 (1 << TCG_REG_ECX));
1450
1451 tcg_regset_clear(s->reserved_regs);
1452 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ESP);
1453
1454 tcg_add_target_add_op_defs(x86_op_defs);
1455}
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