tcg-target.c@ 15135

最後變更在這個檔案從15135是 15135,由 vboxsync 提交於 16 年前
i386/tcg-target.c: darwin alignment fixes and checks.
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1	/*
2	* Tiny Code Generator for QEMU
3	*
4	* Copyright (c) 2008 Fabrice Bellard
5	*
6	* Permission is hereby granted, free of charge, to any person obtaining a copy
7	* of this software and associated documentation files (the "Software"), to deal
8	* in the Software without restriction, including without limitation the rights
9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10	* copies of the Software, and to permit persons to whom the Software is
11	* furnished to do so, subject to the following conditions:
12	*
13	* The above copyright notice and this permission notice shall be included in
14	* all copies or substantial portions of the Software.
15	*
16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22	* THE SOFTWARE.
23	*/
24	/*
25	* Sun LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
26	* other than GPL or LGPL is available it will apply instead, Sun elects to use only
27	* the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
28	* a choice of LGPL license versions is made available with the language indicating
29	* that LGPLv2 or any later version may be used, or where a choice of which version
30	* of the LGPL is applied is otherwise unspecified.
31	*/
32	#ifndef NDEBUG
33	static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
34	"%eax",
35	"%ecx",
36	"%edx",
37	"%ebx",
38	"%esp",
39	"%ebp",
40	"%esi",
41	"%edi",
42	};
43	#endif
44
45	static const int tcg_target_reg_alloc_order[] = {
46	TCG_REG_EAX,
47	TCG_REG_EDX,
48	TCG_REG_ECX,
49	TCG_REG_EBX,
50	#ifndef VBOX
51	TCG_REG_ESI,
52	#endif
53	TCG_REG_EDI,
54	TCG_REG_EBP,
55	};
56
57	static const int tcg_target_call_iarg_regs[3] = { TCG_REG_EAX, TCG_REG_EDX, TCG_REG_ECX };
58	static const int tcg_target_call_oarg_regs[2] = { TCG_REG_EAX, TCG_REG_EDX };
59
60	static uint8_t *tb_ret_addr;
61
62	static void patch_reloc(uint8_t *code_ptr, int type,
63	tcg_target_long value, tcg_target_long addend)
64	{
65	value += addend;
66	switch(type) {
67	case R_386_32:
68	(uint32_t )code_ptr = value;
69	break;
70	case R_386_PC32:
71	(uint32_t )code_ptr = value - (long)code_ptr;
72	break;
73	default:
74	tcg_abort();
75	}
76	}
77
78	#ifdef VBOX
79	/* emits stack alignment checks for strict builds. */
80	DECLINLINE(void) tcg_gen_stack_alignment_check(TCGContext *s)
81	{
82	# if defined(RT_STRICT) && defined(RT_OS_DARWIN) /** @todo all OSes? */
83	tcg_out8(s, 0xf7); tcg_out8(s, 0xc4); /* test %esp, 1fh */
84	tcg_out32(s, TCG_TARGET_STACK_ALIGN - 1);
85	tcg_out8(s, 0x74); /* jz imm8 */
86	tcg_out8(s, 1); /* $+3 (over int3) */
87	tcg_out8(s, 0xcc); /* int3 */
88	# else
89	NOREF(s);
90	# endif
91	}
92	#endif /* VBOX */
93
94	/* maximum number of register used for input function arguments */
95	#ifndef VBOX
96	static inline int tcg_target_get_call_iarg_regs_count(int flags)
97	#else /* VBOX */
98	DECLINLINE(int) tcg_target_get_call_iarg_regs_count(int flags)
99	#endif /* VBOX */
100	{
101	flags &= TCG_CALL_TYPE_MASK;
102	switch(flags) {
103	case TCG_CALL_TYPE_STD:
104	return 0;
105	case TCG_CALL_TYPE_REGPARM_1:
106	case TCG_CALL_TYPE_REGPARM_2:
107	case TCG_CALL_TYPE_REGPARM:
108	return flags - TCG_CALL_TYPE_REGPARM_1 + 1;
109	default:
110	tcg_abort();
111	}
112	}
113
114	/* parse target specific constraints */
115	static int target_parse_constraint(TCGArgConstraint ct, const char *pct_str)
116	{
117	const char *ct_str;
118
119	ct_str = *pct_str;
120	switch(ct_str[0]) {
121	case 'a':
122	ct->ct \|= TCG_CT_REG;
123	tcg_regset_set_reg(ct->u.regs, TCG_REG_EAX);
124	break;
125	case 'b':
126	ct->ct \|= TCG_CT_REG;
127	tcg_regset_set_reg(ct->u.regs, TCG_REG_EBX);
128	break;
129	case 'c':
130	ct->ct \|= TCG_CT_REG;
131	tcg_regset_set_reg(ct->u.regs, TCG_REG_ECX);
132	break;
133	case 'd':
134	ct->ct \|= TCG_CT_REG;
135	tcg_regset_set_reg(ct->u.regs, TCG_REG_EDX);
136	break;
137	case 'S':
138	ct->ct \|= TCG_CT_REG;
139	tcg_regset_set_reg(ct->u.regs, TCG_REG_ESI);
140	break;
141	case 'D':
142	ct->ct \|= TCG_CT_REG;
143	tcg_regset_set_reg(ct->u.regs, TCG_REG_EDI);
144	break;
145	case 'q':
146	ct->ct \|= TCG_CT_REG;
147	tcg_regset_set32(ct->u.regs, 0, 0xf);
148	break;
149	case 'r':
150	ct->ct \|= TCG_CT_REG;
151	tcg_regset_set32(ct->u.regs, 0, 0xff);
152	break;
153
154	/* qemu_ld/st address constraint */
155	case 'L':
156	ct->ct \|= TCG_CT_REG;
157	tcg_regset_set32(ct->u.regs, 0, 0xff);
158	tcg_regset_reset_reg(ct->u.regs, TCG_REG_EAX);
159	tcg_regset_reset_reg(ct->u.regs, TCG_REG_EDX);
160	break;
161	default:
162	return -1;
163	}
164	ct_str++;
165	*pct_str = ct_str;
166	return 0;
167	}
168
169	/* test if a constant matches the constraint */
170	#ifndef VBOX
171	static inline int tcg_target_const_match(tcg_target_long val,
172	#else /* VBOX */
173	DECLINLINE(int) tcg_target_const_match(tcg_target_long val,
174	#endif /* VBOX */
175	const TCGArgConstraint *arg_ct)
176	{
177	int ct;
178	ct = arg_ct->ct;
179	if (ct & TCG_CT_CONST)
180	return 1;
181	else
182	return 0;
183	}
184
185	#define ARITH_ADD 0
186	#define ARITH_OR 1
187	#define ARITH_ADC 2
188	#define ARITH_SBB 3
189	#define ARITH_AND 4
190	#define ARITH_SUB 5
191	#define ARITH_XOR 6
192	#define ARITH_CMP 7
193
194	#define SHIFT_SHL 4
195	#define SHIFT_SHR 5
196	#define SHIFT_SAR 7
197
198	#define JCC_JMP (-1)
199	#define JCC_JO 0x0
200	#define JCC_JNO 0x1
201	#define JCC_JB 0x2
202	#define JCC_JAE 0x3
203	#define JCC_JE 0x4
204	#define JCC_JNE 0x5
205	#define JCC_JBE 0x6
206	#define JCC_JA 0x7
207	#define JCC_JS 0x8
208	#define JCC_JNS 0x9
209	#define JCC_JP 0xa
210	#define JCC_JNP 0xb
211	#define JCC_JL 0xc
212	#define JCC_JGE 0xd
213	#define JCC_JLE 0xe
214	#define JCC_JG 0xf
215
216	#define P_EXT 0x100 /* 0x0f opcode prefix */
217
218	#if !defined(VBOX) \|\| !defined(_MSC_VER)
219	static const uint8_t tcg_cond_to_jcc[10] = {
220	[TCG_COND_EQ] = JCC_JE,
221	[TCG_COND_NE] = JCC_JNE,
222	[TCG_COND_LT] = JCC_JL,
223	[TCG_COND_GE] = JCC_JGE,
224	[TCG_COND_LE] = JCC_JLE,
225	[TCG_COND_GT] = JCC_JG,
226	[TCG_COND_LTU] = JCC_JB,
227	[TCG_COND_GEU] = JCC_JAE,
228	[TCG_COND_LEU] = JCC_JBE,
229	[TCG_COND_GTU] = JCC_JA,
230	};
231	#else
232	/* Fortunately, ordering is right */
233	static const uint8_t tcg_cond_to_jcc[10] = {
234	JCC_JE,
235	JCC_JNE,
236	JCC_JL,
237	JCC_JGE,
238	JCC_JLE,
239	JCC_JG,
240	JCC_JB,
241	JCC_JAE,
242	JCC_JBE,
243	JCC_JA,
244	};
245	#endif
246
247	#ifndef VBOX
248	static inline void tcg_out_opc(TCGContext *s, int opc)
249	#else /* VBOX */
250	DECLINLINE(void) tcg_out_opc(TCGContext *s, int opc)
251	#endif /* VBOX */
252	{
253	if (opc & P_EXT)
254	tcg_out8(s, 0x0f);
255	tcg_out8(s, opc);
256	}
257
258	#ifndef VBOX
259	static inline void tcg_out_modrm(TCGContext *s, int opc, int r, int rm)
260	#else /* VBOX */
261	DECLINLINE(void) tcg_out_modrm(TCGContext *s, int opc, int r, int rm)
262	#endif /* VBOX */
263	{
264	tcg_out_opc(s, opc);
265	tcg_out8(s, 0xc0 \| (r << 3) \| rm);
266	}
267
268	/* rm == -1 means no register index */
269	#ifndef VBOX
270	static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm,
271	#else /* VBOX */
272	DECLINLINE(void) tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm,
273	#endif /* VBOX */
274	int32_t offset)
275	{
276	tcg_out_opc(s, opc);
277	if (rm == -1) {
278	tcg_out8(s, 0x05 \| (r << 3));
279	tcg_out32(s, offset);
280	} else if (offset == 0 && rm != TCG_REG_EBP) {
281	if (rm == TCG_REG_ESP) {
282	tcg_out8(s, 0x04 \| (r << 3));
283	tcg_out8(s, 0x24);
284	} else {
285	tcg_out8(s, 0x00 \| (r << 3) \| rm);
286	}
287	} else if ((int8_t)offset == offset) {
288	if (rm == TCG_REG_ESP) {
289	tcg_out8(s, 0x44 \| (r << 3));
290	tcg_out8(s, 0x24);
291	} else {
292	tcg_out8(s, 0x40 \| (r << 3) \| rm);
293	}
294	tcg_out8(s, offset);
295	} else {
296	if (rm == TCG_REG_ESP) {
297	tcg_out8(s, 0x84 \| (r << 3));
298	tcg_out8(s, 0x24);
299	} else {
300	tcg_out8(s, 0x80 \| (r << 3) \| rm);
301	}
302	tcg_out32(s, offset);
303	}
304	}
305
306	#ifndef VBOX
307	static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
308	#else /* VBOX */
309	DECLINLINE(void) tcg_out_mov(TCGContext *s, int ret, int arg)
310	#endif /* VBOX */
311	{
312	if (arg != ret)
313	tcg_out_modrm(s, 0x8b, ret, arg);
314	}
315
316	#ifndef VBOX
317	static inline void tcg_out_movi(TCGContext *s, TCGType type,
318	#else /* VBOX */
319	DECLINLINE(void) tcg_out_movi(TCGContext *s, TCGType type,
320	#endif /* VBOX */
321	int ret, int32_t arg)
322	{
323	if (arg == 0) {
324	/* xor r0,r0 */
325	tcg_out_modrm(s, 0x01 \| (ARITH_XOR << 3), ret, ret);
326	} else {
327	tcg_out8(s, 0xb8 + ret);
328	tcg_out32(s, arg);
329	}
330	}
331
332	#ifndef VBOX
333	static inline void tcg_out_push(TCGContext *s, int reg)
334	#else /* VBOX */
335	DECLINLINE(void) tcg_out_push(TCGContext *s, int reg)
336	#endif /* VBOX */
337	{
338	tcg_out_opc(s, 0x50 + reg);
339	}
340
341	#ifndef VBOX
342	static inline void tcg_out_pop(TCGContext *s, int reg)
343	#else /* VBOX */
344	DECLINLINE(void) tcg_out_pop(TCGContext *s, int reg)
345	#endif /* VBOX */
346	{
347	tcg_out_opc(s, 0x58 + reg);
348	}
349
350	#ifndef VBOX
351	static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret,
352	#else /* VBOX */
353	DECLINLINE(void) tcg_out_ld(TCGContext *s, TCGType type, int ret,
354	#endif /* VBOX */
355	int arg1, tcg_target_long arg2)
356	{
357	/* movl */
358	tcg_out_modrm_offset(s, 0x8b, ret, arg1, arg2);
359	}
360
361	#ifndef VBOX
362	static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
363	#else /* VBOX */
364	DECLINLINE(void) tcg_out_st(TCGContext *s, TCGType type, int arg,
365	#endif /* VBOX */
366	int arg1, tcg_target_long arg2)
367	{
368	/* movl */
369	tcg_out_modrm_offset(s, 0x89, arg, arg1, arg2);
370	}
371
372	#ifndef VBOX
373	static inline void tgen_arithi(TCGContext *s, int c, int r0, int32_t val)
374	#else /* VBOX */
375	DECLINLINE(void) tgen_arithi(TCGContext *s, int c, int r0, int32_t val)
376	#endif /* VBOX */
377	{
378	if (val == (int8_t)val) {
379	tcg_out_modrm(s, 0x83, c, r0);
380	tcg_out8(s, val);
381	} else {
382	tcg_out_modrm(s, 0x81, c, r0);
383	tcg_out32(s, val);
384	}
385	}
386
387	void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
388	{
389	if (val != 0)
390	tgen_arithi(s, ARITH_ADD, reg, val);
391	}
392
393	static void tcg_out_jxx(TCGContext *s, int opc, int label_index)
394	{
395	int32_t val, val1;
396	TCGLabel *l = &s->labels[label_index];
397
398	if (l->has_value) {
399	val = l->u.value - (tcg_target_long)s->code_ptr;
400	val1 = val - 2;
401	if ((int8_t)val1 == val1) {
402	if (opc == -1)
403	tcg_out8(s, 0xeb);
404	else
405	tcg_out8(s, 0x70 + opc);
406	tcg_out8(s, val1);
407	} else {
408	if (opc == -1) {
409	tcg_out8(s, 0xe9);
410	tcg_out32(s, val - 5);
411	} else {
412	tcg_out8(s, 0x0f);
413	tcg_out8(s, 0x80 + opc);
414	tcg_out32(s, val - 6);
415	}
416	}
417	} else {
418	if (opc == -1) {
419	tcg_out8(s, 0xe9);
420	} else {
421	tcg_out8(s, 0x0f);
422	tcg_out8(s, 0x80 + opc);
423	}
424	tcg_out_reloc(s, s->code_ptr, R_386_PC32, label_index, -4);
425	s->code_ptr += 4;
426	}
427	}
428
429	static void tcg_out_brcond(TCGContext *s, int cond,
430	TCGArg arg1, TCGArg arg2, int const_arg2,
431	int label_index)
432	{
433	if (const_arg2) {
434	if (arg2 == 0) {
435	/* test r, r */
436	tcg_out_modrm(s, 0x85, arg1, arg1);
437	} else {
438	tgen_arithi(s, ARITH_CMP, arg1, arg2);
439	}
440	} else {
441	tcg_out_modrm(s, 0x01 \| (ARITH_CMP << 3), arg2, arg1);
442	}
443	tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index);
444	}
445
446	#ifdef VBOX
447	DECLINLINE(void)
448	tcg_out_long_call(TCGContext s, void dst)
449	{
450	intptr_t disp;
451	# ifdef VBOX
452	tcg_gen_stack_alignment_check(s);
453	# endif
454	disp = (uintptr_t)dst - (uintptr_t)s->code_ptr - 5;
455	tcg_out8(s, 0xe8); /* call disp32 */
456	tcg_out32(s, disp); /* disp32 */
457	}
458	DECLINLINE(void)
459	tcg_out_long_jmp(TCGContext s, void dst)
460	{
461	intptr_t disp = (uintptr_t)dst - (uintptr_t)s->code_ptr - 5;
462	tcg_out8(s, 0xe9); /* jmp disp32 */
463	tcg_out32(s, disp); /* disp32 */
464	}
465	#endif /* VBOX */
466
467
468	/* XXX: we implement it at the target level to avoid having to
469	handle cross basic blocks temporaries */
470	static void tcg_out_brcond2(TCGContext *s,
471	const TCGArg args, const int const_args)
472	{
473	int label_next;
474	label_next = gen_new_label();
475	switch(args[4]) {
476	case TCG_COND_EQ:
477	tcg_out_brcond(s, TCG_COND_NE, args[0], args[2], const_args[2], label_next);
478	tcg_out_brcond(s, TCG_COND_EQ, args[1], args[3], const_args[3], args[5]);
479	break;
480	case TCG_COND_NE:
481	tcg_out_brcond(s, TCG_COND_NE, args[0], args[2], const_args[2], args[5]);
482	tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], args[5]);
483	break;
484	case TCG_COND_LT:
485	tcg_out_brcond(s, TCG_COND_LT, args[1], args[3], const_args[3], args[5]);
486	tcg_out_jxx(s, JCC_JNE, label_next);
487	tcg_out_brcond(s, TCG_COND_LTU, args[0], args[2], const_args[2], args[5]);
488	break;
489	case TCG_COND_LE:
490	tcg_out_brcond(s, TCG_COND_LT, args[1], args[3], const_args[3], args[5]);
491	tcg_out_jxx(s, JCC_JNE, label_next);
492	tcg_out_brcond(s, TCG_COND_LEU, args[0], args[2], const_args[2], args[5]);
493	break;
494	case TCG_COND_GT:
495	tcg_out_brcond(s, TCG_COND_GT, args[1], args[3], const_args[3], args[5]);
496	tcg_out_jxx(s, JCC_JNE, label_next);
497	tcg_out_brcond(s, TCG_COND_GTU, args[0], args[2], const_args[2], args[5]);
498	break;
499	case TCG_COND_GE:
500	tcg_out_brcond(s, TCG_COND_GT, args[1], args[3], const_args[3], args[5]);
501	tcg_out_jxx(s, JCC_JNE, label_next);
502	tcg_out_brcond(s, TCG_COND_GEU, args[0], args[2], const_args[2], args[5]);
503	break;
504	case TCG_COND_LTU:
505	tcg_out_brcond(s, TCG_COND_LTU, args[1], args[3], const_args[3], args[5]);
506	tcg_out_jxx(s, JCC_JNE, label_next);
507	tcg_out_brcond(s, TCG_COND_LTU, args[0], args[2], const_args[2], args[5]);
508	break;
509	case TCG_COND_LEU:
510	tcg_out_brcond(s, TCG_COND_LTU, args[1], args[3], const_args[3], args[5]);
511	tcg_out_jxx(s, JCC_JNE, label_next);
512	tcg_out_brcond(s, TCG_COND_LEU, args[0], args[2], const_args[2], args[5]);
513	break;
514	case TCG_COND_GTU:
515	tcg_out_brcond(s, TCG_COND_GTU, args[1], args[3], const_args[3], args[5]);
516	tcg_out_jxx(s, JCC_JNE, label_next);
517	tcg_out_brcond(s, TCG_COND_GTU, args[0], args[2], const_args[2], args[5]);
518	break;
519	case TCG_COND_GEU:
520	tcg_out_brcond(s, TCG_COND_GTU, args[1], args[3], const_args[3], args[5]);
521	tcg_out_jxx(s, JCC_JNE, label_next);
522	tcg_out_brcond(s, TCG_COND_GEU, args[0], args[2], const_args[2], args[5]);
523	break;
524	default:
525	tcg_abort();
526	}
527	tcg_out_label(s, label_next, (tcg_target_long)s->code_ptr);
528	}
529
530	#if defined(CONFIG_SOFTMMU)
531
532	#include "../../softmmu_defs.h"
533
534	static void *qemu_ld_helpers[4] = {
535	__ldb_mmu,
536	__ldw_mmu,
537	__ldl_mmu,
538	__ldq_mmu,
539	};
540
541	static void *qemu_st_helpers[4] = {
542	__stb_mmu,
543	__stw_mmu,
544	__stl_mmu,
545	__stq_mmu,
546	};
547	#endif
548
549	#if defined(VBOX) && defined(REM_PHYS_ADDR_IN_TLB)
550	static void *vbox_ld_helpers[] = {
551	remR3PhysReadU8,
552	remR3PhysReadU16,
553	remR3PhysReadU32,
554	remR3PhysReadU64,
555	remR3PhysReadS8,
556	remR3PhysReadS16,
557	remR3PhysReadS32,
558	remR3PhysReadS64,
559	};
560
561	static void *vbox_st_helpers[] = {
562	remR3PhysWriteU8,
563	remR3PhysWriteU16,
564	remR3PhysWriteU32,
565	remR3PhysWriteU64
566	};
567
568	static void tcg_out_vbox_phys_read(TCGContext *s, int index,
569	int addr_reg,
570	int data_reg, int data_reg2)
571	{
572	int useReg2 = ((index & 3) == 3);
573
574	/** @todo: should we make phys addess accessors fastcalls - probably not a big deal */
575	/* out parameter (address), note that phys address is always 64-bit */
576	AssertMsg(sizeof(RTGCPHYS) == 8, ("Physical address must be 64-bits, update caller\n"));
577	# ifdef RT_OS_DARWIN
578	tgen_arithi(s, ARITH_SUB, TCG_REG_ESP, 8);
579	# endif
580	tcg_out8(s, 0x6a); tcg_out8(s, 0x00); /* push $0 */
581	tcg_out_push(s, addr_reg);
582
583	tcg_out_long_call(s, vbox_ld_helpers[index]);
584
585	/* mov %eax, data_reg */
586	tcg_out_mov(s, data_reg, TCG_REG_EAX);
587
588	/* returned 64-bit value */
589	if (useReg2)
590	tcg_out_mov(s, data_reg2, TCG_REG_EDX);
591
592	/* clean stack after us */
593	# ifdef RT_OS_DARWIN
594	tcg_out_addi(s, TCG_REG_ESP, 16);
595	# else
596	tcg_out_addi(s, TCG_REG_ESP, 8);
597	# endif
598	}
599
600	static void tcg_out_vbox_phys_write(TCGContext *s, int index,
601	int addr_reg,
602	int val_reg, int val_reg2) {
603	int useReg2 = ((index & 3) == 3);
604
605	/** @todo: should we make phys addess accessors fastcalls - probably not a big deal */
606	# ifdef RT_OS_DARWIN
607	if (!useReg2)
608	tgen_arithi(s, ARITH_SUB, TCG_REG_ESP, 4);
609	# endif
610	/* out parameter (value2) */
611	if (useReg2)
612	tcg_out_push(s, val_reg2);
613	/* out parameter (value) */
614	tcg_out_push(s, val_reg);
615	/* out parameter (address), note that phys address is always 64-bit */
616	AssertMsg(sizeof(RTGCPHYS) == 8, ("Physical address must be 64-bits, update caller\n"));
617	tcg_out8(s, 0x6a); tcg_out8(s, 0x00); /* push $0 */
618	tcg_out_push(s, addr_reg);
619
620	/* call it */
621	tcg_out_long_call(s, vbox_st_helpers[index]);
622
623	/* clean stack after us */
624	# ifdef RT_OS_DARWIN
625	tcg_out_addi(s, TCG_REG_ESP, 16);
626	# else
627	tcg_out_addi(s, TCG_REG_ESP, 8 + (useReg2 ? 8 : 4));
628	# endif
629	}
630
631	#endif /* defined(VBOX) && defined(REM_PHYS_ADDR_IN_TLB) */
632
633	/* XXX: qemu_ld and qemu_st could be modified to clobber only EDX and
634	EAX. It will be useful once fixed registers globals are less
635	common. */
636	static void tcg_out_qemu_ld(TCGContext s, const TCGArg args,
637	int opc)
638	{
639	int addr_reg, data_reg, data_reg2, r0, r1, mem_index, s_bits, bswap;
640	#if defined(CONFIG_SOFTMMU)
641	uint8_t label1_ptr, label2_ptr;
642	#endif
643	#if TARGET_LONG_BITS == 64
644	#if defined(CONFIG_SOFTMMU)
645	uint8_t *label3_ptr;
646	#endif
647	int addr_reg2;
648	#endif
649
650	data_reg = *args++;
651	if (opc == 3)
652	data_reg2 = *args++;
653	else
654	data_reg2 = 0;
655	addr_reg = *args++;
656	#if TARGET_LONG_BITS == 64
657	addr_reg2 = *args++;
658	#endif
659	mem_index = *args;
660	s_bits = opc & 3;
661
662	r0 = TCG_REG_EAX;
663	r1 = TCG_REG_EDX;
664
665	#if defined(CONFIG_SOFTMMU)
666	tcg_out_mov(s, r1, addr_reg);
667
668	tcg_out_mov(s, r0, addr_reg);
669
670	tcg_out_modrm(s, 0xc1, 5, r1); /* shr $x, r1 */
671	tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
672
673	tcg_out_modrm(s, 0x81, 4, r0); /* andl $x, r0 */
674	tcg_out32(s, TARGET_PAGE_MASK \| ((1 << s_bits) - 1));
675
676	tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
677	tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
678
679	#ifndef VBOX
680	tcg_out_opc(s, 0x8d); /* lea offset(r1, %ebp), r1 */
681	tcg_out8(s, 0x80 \| (r1 << 3) \| 0x04);
682	tcg_out8(s, (5 << 3) \| r1);
683	tcg_out32(s, offsetof(CPUState, tlb_table[mem_index][0].addr_read));
684	#else
685	tcg_out_opc(s, 0x8d); /* lea offset(r1, env), r1 */
686	tcg_out8(s, 0x80 \| (r1 << 3) \| 0x04);
687	tcg_out8(s, (TCG_AREG0 << 3) \| r1);
688	tcg_out32(s, offsetof(CPUState, tlb_table[mem_index][0].addr_read));
689	#endif
690
691	/* cmp 0(r1), r0 */
692	tcg_out_modrm_offset(s, 0x3b, r0, r1, 0);
693
694	tcg_out_mov(s, r0, addr_reg);
695
696	#if TARGET_LONG_BITS == 32
697	/* je label1 */
698	tcg_out8(s, 0x70 + JCC_JE);
699	label1_ptr = s->code_ptr;
700	s->code_ptr++;
701	#else
702	/* jne label3 */
703	tcg_out8(s, 0x70 + JCC_JNE);
704	label3_ptr = s->code_ptr;
705	s->code_ptr++;
706
707	/* cmp 4(r1), addr_reg2 */
708	tcg_out_modrm_offset(s, 0x3b, addr_reg2, r1, 4);
709
710	/* je label1 */
711	tcg_out8(s, 0x70 + JCC_JE);
712	label1_ptr = s->code_ptr;
713	s->code_ptr++;
714
715	/* label3: */
716	*label3_ptr = s->code_ptr - label3_ptr - 1;
717	#endif
718
719	/* XXX: move that code at the end of the TB */
720	#if TARGET_LONG_BITS == 32
721	tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_EDX, mem_index);
722	#else
723	tcg_out_mov(s, TCG_REG_EDX, addr_reg2);
724	tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_ECX, mem_index);
725	#endif
726	#ifdef VBOX
727	tcg_gen_stack_alignment_check(s);
728	#endif
729	tcg_out8(s, 0xe8);
730	tcg_out32(s, (tcg_target_long)qemu_ld_helpers[s_bits] -
731	(tcg_target_long)s->code_ptr - 4);
732
733	switch(opc) {
734	case 0 \| 4:
735	/* movsbl */
736	tcg_out_modrm(s, 0xbe \| P_EXT, data_reg, TCG_REG_EAX);
737	break;
738	case 1 \| 4:
739	/* movswl */
740	tcg_out_modrm(s, 0xbf \| P_EXT, data_reg, TCG_REG_EAX);
741	break;
742	case 0:
743	case 1:
744	case 2:
745	default:
746	tcg_out_mov(s, data_reg, TCG_REG_EAX);
747	break;
748	case 3:
749	if (data_reg == TCG_REG_EDX) {
750	tcg_out_opc(s, 0x90 + TCG_REG_EDX); /* xchg %edx, %eax */
751	tcg_out_mov(s, data_reg2, TCG_REG_EAX);
752	} else {
753	tcg_out_mov(s, data_reg, TCG_REG_EAX);
754	tcg_out_mov(s, data_reg2, TCG_REG_EDX);
755	}
756	break;
757	}
758
759	/* jmp label2 */
760	tcg_out8(s, 0xeb);
761	label2_ptr = s->code_ptr;
762	s->code_ptr++;
763
764	/* label1: */
765	*label1_ptr = s->code_ptr - label1_ptr - 1;
766
767	/* add x(r1), r0 */
768	tcg_out_modrm_offset(s, 0x03, r0, r1, offsetof(CPUTLBEntry, addend) -
769	offsetof(CPUTLBEntry, addr_read));
770	#else
771	r0 = addr_reg;
772	#endif
773
774	#if !defined(VBOX) \|\| !defined(REM_PHYS_ADDR_IN_TLB)
775	#ifdef TARGET_WORDS_BIGENDIAN
776	bswap = 1;
777	#else
778	bswap = 0;
779	#endif
780	switch(opc) {
781	case 0:
782	/* movzbl */
783	tcg_out_modrm_offset(s, 0xb6 \| P_EXT, data_reg, r0, 0);
784	break;
785	case 0 \| 4:
786	/* movsbl */
787	tcg_out_modrm_offset(s, 0xbe \| P_EXT, data_reg, r0, 0);
788	break;
789	case 1:
790	/* movzwl */
791	tcg_out_modrm_offset(s, 0xb7 \| P_EXT, data_reg, r0, 0);
792	if (bswap) {
793	/* rolw $8, data_reg */
794	tcg_out8(s, 0x66);
795	tcg_out_modrm(s, 0xc1, 0, data_reg);
796	tcg_out8(s, 8);
797	}
798	break;
799	case 1 \| 4:
800	/* movswl */
801	tcg_out_modrm_offset(s, 0xbf \| P_EXT, data_reg, r0, 0);
802	if (bswap) {
803	/* rolw $8, data_reg */
804	tcg_out8(s, 0x66);
805	tcg_out_modrm(s, 0xc1, 0, data_reg);
806	tcg_out8(s, 8);
807
808	/* movswl data_reg, data_reg */
809	tcg_out_modrm(s, 0xbf \| P_EXT, data_reg, data_reg);
810	}
811	break;
812	case 2:
813	/* movl (r0), data_reg */
814	tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 0);
815	if (bswap) {
816	/* bswap */
817	tcg_out_opc(s, (0xc8 + data_reg) \| P_EXT);
818	}
819	break;
820	case 3:
821	/* XXX: could be nicer */
822	if (r0 == data_reg) {
823	r1 = TCG_REG_EDX;
824	if (r1 == data_reg)
825	r1 = TCG_REG_EAX;
826	tcg_out_mov(s, r1, r0);
827	r0 = r1;
828	}
829	if (!bswap) {
830	tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 0);
831	tcg_out_modrm_offset(s, 0x8b, data_reg2, r0, 4);
832	} else {
833	tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 4);
834	tcg_out_opc(s, (0xc8 + data_reg) \| P_EXT);
835
836	tcg_out_modrm_offset(s, 0x8b, data_reg2, r0, 0);
837	/* bswap */
838	tcg_out_opc(s, (0xc8 + data_reg2) \| P_EXT);
839	}
840	break;
841	default:
842	tcg_abort();
843	}
844	#else /* VBOX */
845	tcg_out_vbox_phys_read(s, opc, r0, data_reg, data_reg2);
846	#endif
847
848
849	#if defined(CONFIG_SOFTMMU)
850	/* label2: */
851	*label2_ptr = s->code_ptr - label2_ptr - 1;
852	# ifdef VBOX
853	Assert((unsigned)(s->code_ptr - label2_ptr - 1) <= 127);
854	# endif
855	#endif
856	}
857
858
859	static void tcg_out_qemu_st(TCGContext s, const TCGArg args,
860	int opc)
861	{
862	int addr_reg, data_reg, data_reg2, r0, r1, mem_index, s_bits, bswap;
863	#if defined(CONFIG_SOFTMMU)
864	uint8_t label1_ptr, label2_ptr;
865	#endif
866	#if TARGET_LONG_BITS == 64
867	#if defined(CONFIG_SOFTMMU)
868	uint8_t *label3_ptr;
869	#endif
870	int addr_reg2;
871	#endif
872
873	data_reg = *args++;
874	if (opc == 3)
875	data_reg2 = *args++;
876	else
877	data_reg2 = 0;
878	addr_reg = *args++;
879	#if TARGET_LONG_BITS == 64
880	addr_reg2 = *args++;
881	#endif
882	mem_index = *args;
883
884	s_bits = opc;
885
886	r0 = TCG_REG_EAX;
887	r1 = TCG_REG_EDX;
888
889	#if defined(CONFIG_SOFTMMU)
890	tcg_out_mov(s, r1, addr_reg);
891
892	tcg_out_mov(s, r0, addr_reg);
893
894	tcg_out_modrm(s, 0xc1, 5, r1); /* shr $x, r1 */
895	tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
896
897	tcg_out_modrm(s, 0x81, 4, r0); /* andl $x, r0 */
898	tcg_out32(s, TARGET_PAGE_MASK \| ((1 << s_bits) - 1));
899
900	tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
901	tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
902
903	#ifndef VBOX
904	tcg_out_opc(s, 0x8d); /* lea offset(r1, %ebp), r1 */
905	tcg_out8(s, 0x80 \| (r1 << 3) \| 0x04);
906	tcg_out8(s, (5 << 3) \| r1);
907	tcg_out32(s, offsetof(CPUState, tlb_table[mem_index][0].addr_write));
908	#else
909	tcg_out_opc(s, 0x8d); /* lea offset(r1, env), r1 */
910	tcg_out8(s, 0x80 \| (r1 << 3) \| 0x04);
911	tcg_out8(s, (TCG_AREG0 << 3) \| r1);
912	tcg_out32(s, offsetof(CPUState, tlb_table[mem_index][0].addr_write));
913	#endif
914
915	/* cmp 0(r1), r0 */
916	tcg_out_modrm_offset(s, 0x3b, r0, r1, 0);
917
918	tcg_out_mov(s, r0, addr_reg);
919
920	#if TARGET_LONG_BITS == 32
921	/* je label1 */
922	tcg_out8(s, 0x70 + JCC_JE);
923	label1_ptr = s->code_ptr;
924	s->code_ptr++;
925	#else
926	/* jne label3 */
927	tcg_out8(s, 0x70 + JCC_JNE);
928	label3_ptr = s->code_ptr;
929	s->code_ptr++;
930
931	/* cmp 4(r1), addr_reg2 */
932	tcg_out_modrm_offset(s, 0x3b, addr_reg2, r1, 4);
933
934	/* je label1 */
935	tcg_out8(s, 0x70 + JCC_JE);
936	label1_ptr = s->code_ptr;
937	s->code_ptr++;
938
939	/* label3: */
940	*label3_ptr = s->code_ptr - label3_ptr - 1;
941	#endif
942
943	/* XXX: move that code at the end of the TB */
944	#if TARGET_LONG_BITS == 32
945	if (opc == 3) {
946	tcg_out_mov(s, TCG_REG_EDX, data_reg);
947	tcg_out_mov(s, TCG_REG_ECX, data_reg2);
948	tcg_out8(s, 0x6a); /* push Ib */
949	tcg_out8(s, mem_index);
950	# ifdef VBOX
951	tcg_gen_stack_alignment_check(s);
952	# endif
953	tcg_out8(s, 0xe8);
954	tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] -
955	(tcg_target_long)s->code_ptr - 4);
956	tcg_out_addi(s, TCG_REG_ESP, 4);
957	} else {
958	switch(opc) {
959	case 0:
960	/* movzbl */
961	tcg_out_modrm(s, 0xb6 \| P_EXT, TCG_REG_EDX, data_reg);
962	break;
963	case 1:
964	/* movzwl */
965	tcg_out_modrm(s, 0xb7 \| P_EXT, TCG_REG_EDX, data_reg);
966	break;
967	case 2:
968	tcg_out_mov(s, TCG_REG_EDX, data_reg);
969	break;
970	}
971	tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_ECX, mem_index);
972	# ifdef VBOX
973	tcg_gen_stack_alignment_check(s);
974	# endif
975	tcg_out8(s, 0xe8);
976	tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] -
977	(tcg_target_long)s->code_ptr - 4);
978	}
979	#else
980	if (opc == 3) {
981	tcg_out_mov(s, TCG_REG_EDX, addr_reg2);
982	tcg_out8(s, 0x6a); /* push Ib */
983	tcg_out8(s, mem_index);
984	tcg_out_opc(s, 0x50 + data_reg2); /* push */
985	tcg_out_opc(s, 0x50 + data_reg); /* push */
986	# ifdef VBOX
987	tcg_gen_stack_alignment_check(s);
988	# endif
989	tcg_out8(s, 0xe8);
990	tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] -
991	(tcg_target_long)s->code_ptr - 4);
992	tcg_out_addi(s, TCG_REG_ESP, 12);
993	} else {
994	tcg_out_mov(s, TCG_REG_EDX, addr_reg2);
995	switch(opc) {
996	case 0:
997	/* movzbl */
998	tcg_out_modrm(s, 0xb6 \| P_EXT, TCG_REG_ECX, data_reg);
999	break;
1000	case 1:
1001	/* movzwl */
1002	tcg_out_modrm(s, 0xb7 \| P_EXT, TCG_REG_ECX, data_reg);
1003	break;
1004	case 2:
1005	tcg_out_mov(s, TCG_REG_ECX, data_reg);
1006	break;
1007	}
1008	# if defined(VBOX) && defined(RT_OS_DARWIN)
1009	tgen_arithi(s, ARITH_SUB, TCG_REG_ESP, 12); /** @todo FIXME: This is not 100% correct (assumes a bunch of things), but it works around the current issue it seems... */
1010	# endif
1011	tcg_out8(s, 0x6a); /* push Ib */
1012	tcg_out8(s, mem_index);
1013	# ifdef VBOX
1014	tcg_gen_stack_alignment_check(s);
1015	# endif
1016
1017	tcg_out8(s, 0xe8);
1018	tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] -
1019	(tcg_target_long)s->code_ptr - 4);
1020	# if defined(VBOX) && defined(RT_OS_DARWIN)
1021	tcg_out_addi(s, TCG_REG_ESP, 12+4);
1022	# else
1023	tcg_out_addi(s, TCG_REG_ESP, 4);
1024	# endif
1025	}
1026	#endif
1027
1028	/* jmp label2 */
1029	tcg_out8(s, 0xeb);
1030	label2_ptr = s->code_ptr;
1031	s->code_ptr++;
1032
1033	/* label1: */
1034	*label1_ptr = s->code_ptr - label1_ptr - 1;
1035
1036	/* add x(r1), r0 */
1037	tcg_out_modrm_offset(s, 0x03, r0, r1, offsetof(CPUTLBEntry, addend) -
1038	offsetof(CPUTLBEntry, addr_write));
1039	#else
1040	r0 = addr_reg;
1041	#endif
1042
1043	#if !defined(VBOX) \|\| !defined(REM_PHYS_ADDR_IN_TLB)
1044	#ifdef TARGET_WORDS_BIGENDIAN
1045	bswap = 1;
1046	#else
1047	bswap = 0;
1048	#endif
1049	switch(opc) {
1050	case 0:
1051	/* movb */
1052	tcg_out_modrm_offset(s, 0x88, data_reg, r0, 0);
1053	break;
1054	case 1:
1055	if (bswap) {
1056	tcg_out_mov(s, r1, data_reg);
1057	tcg_out8(s, 0x66); /* rolw $8, %ecx */
1058	tcg_out_modrm(s, 0xc1, 0, r1);
1059	tcg_out8(s, 8);
1060	data_reg = r1;
1061	}
1062	/* movw */
1063	tcg_out8(s, 0x66);
1064	tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
1065	break;
1066	case 2:
1067	if (bswap) {
1068	tcg_out_mov(s, r1, data_reg);
1069	/* bswap data_reg */
1070	tcg_out_opc(s, (0xc8 + r1) \| P_EXT);
1071	data_reg = r1;
1072	}
1073	/* movl */
1074	tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
1075	break;
1076	case 3:
1077	if (bswap) {
1078	tcg_out_mov(s, r1, data_reg2);
1079	/* bswap data_reg */
1080	tcg_out_opc(s, (0xc8 + r1) \| P_EXT);
1081	tcg_out_modrm_offset(s, 0x89, r1, r0, 0);
1082	tcg_out_mov(s, r1, data_reg);
1083	/* bswap data_reg */
1084	tcg_out_opc(s, (0xc8 + r1) \| P_EXT);
1085	tcg_out_modrm_offset(s, 0x89, r1, r0, 4);
1086	} else {
1087	tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
1088	tcg_out_modrm_offset(s, 0x89, data_reg2, r0, 4);
1089	}
1090	break;
1091	default:
1092	tcg_abort();
1093	}
1094	#else
1095	tcg_out_vbox_phys_write(s, opc, r0, data_reg, data_reg2);
1096	#endif
1097
1098	#if defined(CONFIG_SOFTMMU)
1099	/* label2: */
1100	*label2_ptr = s->code_ptr - label2_ptr - 1;
1101	# ifdef VBOX
1102	Assert((unsigned)(s->code_ptr - label2_ptr - 1) <= 127);
1103	# endif
1104	#endif
1105	}
1106
1107	#ifndef VBOX
1108	static inline void tcg_out_op(TCGContext *s, int opc,
1109	#else /* VBOX */
1110	DECLINLINE(void) tcg_out_op(TCGContext *s, int opc,
1111	#endif /* VBOX */
1112	const TCGArg args, const int const_args)
1113	{
1114	int c;
1115
1116	switch(opc) {
1117	case INDEX_op_exit_tb:
1118	tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_EAX, args[0]);
1119	tcg_out8(s, 0xe9); /* jmp tb_ret_addr */
1120	tcg_out32(s, tb_ret_addr - s->code_ptr - 4);
1121	break;
1122	case INDEX_op_goto_tb:
1123	if (s->tb_jmp_offset) {
1124	/* direct jump method */
1125	tcg_out8(s, 0xe9); /* jmp im */
1126	s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1127	tcg_out32(s, 0);
1128	} else {
1129	/* indirect jump method */
1130	/* jmp Ev */
1131	tcg_out_modrm_offset(s, 0xff, 4, -1,
1132	(tcg_target_long)(s->tb_next + args[0]));
1133	}
1134	s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1135	break;
1136	case INDEX_op_call:
1137	#ifdef VBOX
1138	tcg_gen_stack_alignment_check(s);
1139	#endif
1140	if (const_args[0]) {
1141	tcg_out8(s, 0xe8);
1142	tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4);
1143	} else {
1144	tcg_out_modrm(s, 0xff, 2, args[0]);
1145	}
1146	break;
1147	case INDEX_op_jmp:
1148	if (const_args[0]) {
1149	tcg_out8(s, 0xe9);
1150	tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4);
1151	} else {
1152	tcg_out_modrm(s, 0xff, 4, args[0]);
1153	}
1154	break;
1155	case INDEX_op_br:
1156	tcg_out_jxx(s, JCC_JMP, args[0]);
1157	break;
1158	case INDEX_op_movi_i32:
1159	tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
1160	break;
1161	case INDEX_op_ld8u_i32:
1162	/* movzbl */
1163	tcg_out_modrm_offset(s, 0xb6 \| P_EXT, args[0], args[1], args[2]);
1164	break;
1165	case INDEX_op_ld8s_i32:
1166	/* movsbl */
1167	tcg_out_modrm_offset(s, 0xbe \| P_EXT, args[0], args[1], args[2]);
1168	break;
1169	case INDEX_op_ld16u_i32:
1170	/* movzwl */
1171	tcg_out_modrm_offset(s, 0xb7 \| P_EXT, args[0], args[1], args[2]);
1172	break;
1173	case INDEX_op_ld16s_i32:
1174	/* movswl */
1175	tcg_out_modrm_offset(s, 0xbf \| P_EXT, args[0], args[1], args[2]);
1176	break;
1177	case INDEX_op_ld_i32:
1178	/* movl */
1179	tcg_out_modrm_offset(s, 0x8b, args[0], args[1], args[2]);
1180	break;
1181	case INDEX_op_st8_i32:
1182	/* movb */
1183	tcg_out_modrm_offset(s, 0x88, args[0], args[1], args[2]);
1184	break;
1185	case INDEX_op_st16_i32:
1186	/* movw */
1187	tcg_out8(s, 0x66);
1188	tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
1189	break;
1190	case INDEX_op_st_i32:
1191	/* movl */
1192	tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
1193	break;
1194	case INDEX_op_sub_i32:
1195	c = ARITH_SUB;
1196	goto gen_arith;
1197	case INDEX_op_and_i32:
1198	c = ARITH_AND;
1199	goto gen_arith;
1200	case INDEX_op_or_i32:
1201	c = ARITH_OR;
1202	goto gen_arith;
1203	case INDEX_op_xor_i32:
1204	c = ARITH_XOR;
1205	goto gen_arith;
1206	case INDEX_op_add_i32:
1207	c = ARITH_ADD;
1208	gen_arith:
1209	if (const_args[2]) {
1210	tgen_arithi(s, c, args[0], args[2]);
1211	} else {
1212	tcg_out_modrm(s, 0x01 \| (c << 3), args[2], args[0]);
1213	}
1214	break;
1215	case INDEX_op_mul_i32:
1216	if (const_args[2]) {
1217	int32_t val;
1218	val = args[2];
1219	if (val == (int8_t)val) {
1220	tcg_out_modrm(s, 0x6b, args[0], args[0]);
1221	tcg_out8(s, val);
1222	} else {
1223	tcg_out_modrm(s, 0x69, args[0], args[0]);
1224	tcg_out32(s, val);
1225	}
1226	} else {
1227	tcg_out_modrm(s, 0xaf \| P_EXT, args[0], args[2]);
1228	}
1229	break;
1230	case INDEX_op_mulu2_i32:
1231	tcg_out_modrm(s, 0xf7, 4, args[3]);
1232	break;
1233	case INDEX_op_div2_i32:
1234	tcg_out_modrm(s, 0xf7, 7, args[4]);
1235	break;
1236	case INDEX_op_divu2_i32:
1237	tcg_out_modrm(s, 0xf7, 6, args[4]);
1238	break;
1239	case INDEX_op_shl_i32:
1240	c = SHIFT_SHL;
1241	gen_shift32:
1242	if (const_args[2]) {
1243	if (args[2] == 1) {
1244	tcg_out_modrm(s, 0xd1, c, args[0]);
1245	} else {
1246	tcg_out_modrm(s, 0xc1, c, args[0]);
1247	tcg_out8(s, args[2]);
1248	}
1249	} else {
1250	tcg_out_modrm(s, 0xd3, c, args[0]);
1251	}
1252	break;
1253	case INDEX_op_shr_i32:
1254	c = SHIFT_SHR;
1255	goto gen_shift32;
1256	case INDEX_op_sar_i32:
1257	c = SHIFT_SAR;
1258	goto gen_shift32;
1259
1260	case INDEX_op_add2_i32:
1261	if (const_args[4])
1262	tgen_arithi(s, ARITH_ADD, args[0], args[4]);
1263	else
1264	tcg_out_modrm(s, 0x01 \| (ARITH_ADD << 3), args[4], args[0]);
1265	if (const_args[5])
1266	tgen_arithi(s, ARITH_ADC, args[1], args[5]);
1267	else
1268	tcg_out_modrm(s, 0x01 \| (ARITH_ADC << 3), args[5], args[1]);
1269	break;
1270	case INDEX_op_sub2_i32:
1271	if (const_args[4])
1272	tgen_arithi(s, ARITH_SUB, args[0], args[4]);
1273	else
1274	tcg_out_modrm(s, 0x01 \| (ARITH_SUB << 3), args[4], args[0]);
1275	if (const_args[5])
1276	tgen_arithi(s, ARITH_SBB, args[1], args[5]);
1277	else
1278	tcg_out_modrm(s, 0x01 \| (ARITH_SBB << 3), args[5], args[1]);
1279	break;
1280	case INDEX_op_brcond_i32:
1281	tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], args[3]);
1282	break;
1283	case INDEX_op_brcond2_i32:
1284	tcg_out_brcond2(s, args, const_args);
1285	break;
1286
1287	case INDEX_op_qemu_ld8u:
1288	tcg_out_qemu_ld(s, args, 0);
1289	break;
1290	case INDEX_op_qemu_ld8s:
1291	tcg_out_qemu_ld(s, args, 0 \| 4);
1292	break;
1293	case INDEX_op_qemu_ld16u:
1294	tcg_out_qemu_ld(s, args, 1);
1295	break;
1296	case INDEX_op_qemu_ld16s:
1297	tcg_out_qemu_ld(s, args, 1 \| 4);
1298	break;
1299	case INDEX_op_qemu_ld32u:
1300	tcg_out_qemu_ld(s, args, 2);
1301	break;
1302	case INDEX_op_qemu_ld64:
1303	tcg_out_qemu_ld(s, args, 3);
1304	break;
1305
1306	case INDEX_op_qemu_st8:
1307	tcg_out_qemu_st(s, args, 0);
1308	break;
1309	case INDEX_op_qemu_st16:
1310	tcg_out_qemu_st(s, args, 1);
1311	break;
1312	case INDEX_op_qemu_st32:
1313	tcg_out_qemu_st(s, args, 2);
1314	break;
1315	case INDEX_op_qemu_st64:
1316	tcg_out_qemu_st(s, args, 3);
1317	break;
1318
1319	default:
1320	tcg_abort();
1321	}
1322	}
1323
1324	static const TCGTargetOpDef x86_op_defs[] = {
1325	{ INDEX_op_exit_tb, {"", "" } },
1326	{ INDEX_op_goto_tb, {"", "" } },
1327	{ INDEX_op_call, { "ri", "", } },
1328	{ INDEX_op_jmp, { "ri", ""} },
1329	{ INDEX_op_br, {"", "" } },
1330	{ INDEX_op_mov_i32, { "r", "r" } },
1331	{ INDEX_op_movi_i32, { "r" } },
1332	{ INDEX_op_ld8u_i32, { "r", "r" } },
1333	{ INDEX_op_ld8s_i32, { "r", "r" } },
1334	{ INDEX_op_ld16u_i32, { "r", "r" } },
1335	{ INDEX_op_ld16s_i32, { "r", "r" } },
1336	{ INDEX_op_ld_i32, { "r", "r" } },
1337	{ INDEX_op_st8_i32, { "q", "r" } },
1338	{ INDEX_op_st16_i32, { "r", "r" } },
1339	{ INDEX_op_st_i32, { "r", "r" } },
1340
1341	{ INDEX_op_add_i32, { "r", "0", "ri" } },
1342	{ INDEX_op_sub_i32, { "r", "0", "ri" } },
1343	{ INDEX_op_mul_i32, { "r", "0", "ri" } },
1344	{ INDEX_op_mulu2_i32, { "a", "d", "a", "r" } },
1345	{ INDEX_op_div2_i32, { "a", "d", "0", "1", "r" } },
1346	{ INDEX_op_divu2_i32, { "a", "d", "0", "1", "r" } },
1347	{ INDEX_op_and_i32, { "r", "0", "ri" } },
1348	{ INDEX_op_or_i32, { "r", "0", "ri" } },
1349	{ INDEX_op_xor_i32, { "r", "0", "ri" } },
1350
1351	{ INDEX_op_shl_i32, { "r", "0", "ci" } },
1352	{ INDEX_op_shr_i32, { "r", "0", "ci" } },
1353	{ INDEX_op_sar_i32, { "r", "0", "ci" } },
1354
1355	{ INDEX_op_brcond_i32, { "r", "ri" } },
1356
1357	{ INDEX_op_add2_i32, { "r", "r", "0", "1", "ri", "ri" } },
1358	{ INDEX_op_sub2_i32, { "r", "r", "0", "1", "ri", "ri" } },
1359	{ INDEX_op_brcond2_i32, { "r", "r", "ri", "ri" } },
1360
1361	#if TARGET_LONG_BITS == 32
1362	{ INDEX_op_qemu_ld8u, { "r", "L" } },
1363	{ INDEX_op_qemu_ld8s, { "r", "L" } },
1364	{ INDEX_op_qemu_ld16u, { "r", "L" } },
1365	{ INDEX_op_qemu_ld16s, { "r", "L" } },
1366	{ INDEX_op_qemu_ld32u, { "r", "L" } },
1367	{ INDEX_op_qemu_ld64, { "r", "r", "L" } },
1368
1369	{ INDEX_op_qemu_st8, { "cb", "L" } },
1370	{ INDEX_op_qemu_st16, { "L", "L" } },
1371	{ INDEX_op_qemu_st32, { "L", "L" } },
1372	{ INDEX_op_qemu_st64, { "L", "L", "L" } },
1373	#else
1374	{ INDEX_op_qemu_ld8u, { "r", "L", "L" } },
1375	{ INDEX_op_qemu_ld8s, { "r", "L", "L" } },
1376	{ INDEX_op_qemu_ld16u, { "r", "L", "L" } },
1377	{ INDEX_op_qemu_ld16s, { "r", "L", "L" } },
1378	{ INDEX_op_qemu_ld32u, { "r", "L", "L" } },
1379	{ INDEX_op_qemu_ld64, { "r", "r", "L", "L" } },
1380
1381	{ INDEX_op_qemu_st8, { "cb", "L", "L" } },
1382	{ INDEX_op_qemu_st16, { "L", "L", "L" } },
1383	{ INDEX_op_qemu_st32, { "L", "L", "L" } },
1384	{ INDEX_op_qemu_st64, { "L", "L", "L", "L" } },
1385	#endif
1386	#ifndef VBOX
1387	{ -1 },
1388	#else
1389	{ -1, {"", "", "", ""} },
1390	#endif
1391	};
1392
1393	static int tcg_target_callee_save_regs[] = {
1394	#ifndef VBOX
1395	/* TCG_REG_EBP, / / currently used for the global env, so no
1396	need to save */
1397	TCG_REG_EBX,
1398	TCG_REG_ESI,
1399	TCG_REG_EDI,
1400	#else
1401	TCG_REG_EBP,
1402	TCG_REG_EBX,
1403	/* TCG_REG_ESI, / / currently used for the global env, so no
1404	need to save */
1405	TCG_REG_EDI,
1406	#endif
1407	};
1408
1409	/* Generate global QEMU prologue and epilogue code */
1410	void tcg_target_qemu_prologue(TCGContext *s)
1411	{
1412	int i, frame_size, push_size, stack_addend;
1413
1414	/* TB prologue */
1415	/* save all callee saved registers */
1416	for(i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
1417	tcg_out_push(s, tcg_target_callee_save_regs[i]);
1418	}
1419	/* reserve some stack space */
1420	push_size = 4 + ARRAY_SIZE(tcg_target_callee_save_regs) * 4;
1421	frame_size = push_size + TCG_STATIC_CALL_ARGS_SIZE;
1422	frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
1423	~(TCG_TARGET_STACK_ALIGN - 1);
1424	stack_addend = frame_size - push_size;
1425	tcg_out_addi(s, TCG_REG_ESP, -stack_addend);
1426	# ifdef VBOX
1427	tcg_gen_stack_alignment_check(s);
1428	# endif
1429
1430	tcg_out_modrm(s, 0xff, 4, TCG_REG_EAX); /* jmp %eax /
1431
1432	/* TB epilogue */
1433	tb_ret_addr = s->code_ptr;
1434	tcg_out_addi(s, TCG_REG_ESP, stack_addend);
1435	for(i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) {
1436	tcg_out_pop(s, tcg_target_callee_save_regs[i]);
1437	}
1438	tcg_out8(s, 0xc3); /* ret */
1439	}
1440
1441	void tcg_target_init(TCGContext *s)
1442	{
1443	/* fail safe */
1444	if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
1445	tcg_abort();
1446
1447	tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xff);
1448	tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1449	(1 << TCG_REG_EAX) \|
1450	(1 << TCG_REG_EDX) \|
1451	(1 << TCG_REG_ECX));
1452
1453	tcg_regset_clear(s->reserved_regs);
1454	tcg_regset_set_reg(s->reserved_regs, TCG_REG_ESP);
1455
1456	tcg_add_target_add_op_defs(x86_op_defs);
1457	}

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source: vbox/trunk/src/recompiler_new/tcg/i386/tcg-target.c@ 15135

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