test-i386.c@ 36170

最後變更在這個檔案從36170是 36170,由 vboxsync 提交於 14 年前
rem: synced up to svn://svn.savannah.nongnu.org/qemu/trunk@6686 (repo UUID c046a42c-6fe2-441c-8c8c-71466251a162).
屬性 svn:eol-style 設為 `native`
檔案大小: 70.6 KB

行
1	/*
2	* x86 CPU test
3	*
4	* Copyright (c) 2003 Fabrice Bellard
5	*
6	* This program is free software; you can redistribute it and/or modify
7	* it under the terms of the GNU General Public License as published by
8	* the Free Software Foundation; either version 2 of the License, or
9	* (at your option) any later version.
10	*
11	* This program is distributed in the hope that it will be useful,
12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14	* GNU General Public License for more details.
15	*
16	* You should have received a copy of the GNU General Public License
17	* along with this program; if not, write to the Free Software
18	* Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19	* MA 02110-1301, USA.
20	*/
21
22	/*
23	* Oracle GPL Disclaimer: For the avoidance of doubt, except that if any license choice
24	* other than GPL or LGPL is available it will apply instead, Oracle elects to use only
25	* the General Public License version 2 (GPLv2) at this time for any software where
26	* a choice of GPL license versions is made available with the language indicating
27	* that GPLv2 or any later version may be used, or where a choice of which version
28	* of the GPL is applied is otherwise unspecified.
29	*/
30
31	#define _GNU_SOURCE
32	#include <stdlib.h>
33	#include <stdio.h>
34	#include <string.h>
35	#include <inttypes.h>
36	#include <math.h>
37	#include <signal.h>
38	#include <setjmp.h>
39	#include <errno.h>
40	#include <sys/ucontext.h>
41	#include <sys/mman.h>
42
43	#if !defined(__x86_64__)
44	//#define TEST_VM86
45	#define TEST_SEGS
46	#endif
47	//#define LINUX_VM86_IOPL_FIX
48	//#define TEST_P4_FLAGS
49	#ifdef __SSE__
50	#define TEST_SSE
51	#define TEST_CMOV 1
52	#define TEST_FCOMI 1
53	#else
54	#undef TEST_SSE
55	#define TEST_CMOV 1
56	#define TEST_FCOMI 1
57	#endif
58
59	#if defined(__x86_64__)
60	#define FMT64X "%016lx"
61	#define FMTLX "%016lx"
62	#define X86_64_ONLY(x) x
63	#else
64	#define FMT64X "%016" PRIx64
65	#define FMTLX "%08lx"
66	#define X86_64_ONLY(x)
67	#endif
68
69	#ifdef TEST_VM86
70	#include <asm/vm86.h>
71	#endif
72
73	#define xglue(x, y) x ## y
74	#define glue(x, y) xglue(x, y)
75	#define stringify(s) tostring(s)
76	#define tostring(s) #s
77
78	#define CC_C 0x0001
79	#define CC_P 0x0004
80	#define CC_A 0x0010
81	#define CC_Z 0x0040
82	#define CC_S 0x0080
83	#define CC_O 0x0800
84
85	#define __init_call __attribute__ ((unused,__section__ ("initcall")))
86
87	#define CC_MASK (CC_C \| CC_P \| CC_Z \| CC_S \| CC_O \| CC_A)
88
89	#if defined(__x86_64__)
90	static inline long i2l(long v)
91	{
92	return v \| ((v ^ 0xabcd) << 32);
93	}
94	#else
95	static inline long i2l(long v)
96	{
97	return v;
98	}
99	#endif
100
101	#define OP add
102	#include "test-i386.h"
103
104	#define OP sub
105	#include "test-i386.h"
106
107	#define OP xor
108	#include "test-i386.h"
109
110	#define OP and
111	#include "test-i386.h"
112
113	#define OP or
114	#include "test-i386.h"
115
116	#define OP cmp
117	#include "test-i386.h"
118
119	#define OP adc
120	#define OP_CC
121	#include "test-i386.h"
122
123	#define OP sbb
124	#define OP_CC
125	#include "test-i386.h"
126
127	#define OP inc
128	#define OP_CC
129	#define OP1
130	#include "test-i386.h"
131
132	#define OP dec
133	#define OP_CC
134	#define OP1
135	#include "test-i386.h"
136
137	#define OP neg
138	#define OP_CC
139	#define OP1
140	#include "test-i386.h"
141
142	#define OP not
143	#define OP_CC
144	#define OP1
145	#include "test-i386.h"
146
147	#undef CC_MASK
148	#define CC_MASK (CC_C \| CC_P \| CC_Z \| CC_S \| CC_O)
149
150	#define OP shl
151	#include "test-i386-shift.h"
152
153	#define OP shr
154	#include "test-i386-shift.h"
155
156	#define OP sar
157	#include "test-i386-shift.h"
158
159	#define OP rol
160	#include "test-i386-shift.h"
161
162	#define OP ror
163	#include "test-i386-shift.h"
164
165	#define OP rcr
166	#define OP_CC
167	#include "test-i386-shift.h"
168
169	#define OP rcl
170	#define OP_CC
171	#include "test-i386-shift.h"
172
173	#define OP shld
174	#define OP_SHIFTD
175	#define OP_NOBYTE
176	#include "test-i386-shift.h"
177
178	#define OP shrd
179	#define OP_SHIFTD
180	#define OP_NOBYTE
181	#include "test-i386-shift.h"
182
183	/* XXX: should be more precise ? */
184	#undef CC_MASK
185	#define CC_MASK (CC_C)
186
187	#define OP bt
188	#define OP_NOBYTE
189	#include "test-i386-shift.h"
190
191	#define OP bts
192	#define OP_NOBYTE
193	#include "test-i386-shift.h"
194
195	#define OP btr
196	#define OP_NOBYTE
197	#include "test-i386-shift.h"
198
199	#define OP btc
200	#define OP_NOBYTE
201	#include "test-i386-shift.h"
202
203	/* lea test (modrm support) */
204	#define TEST_LEAQ(STR)\
205	{\
206	asm("lea " STR ", %0"\
207	: "=r" (res)\
208	: "a" (eax), "b" (ebx), "c" (ecx), "d" (edx), "S" (esi), "D" (edi));\
209	printf("lea %s = " FMTLX "\n", STR, res);\
210	}
211
212	#define TEST_LEA(STR)\
213	{\
214	asm("lea " STR ", %0"\
215	: "=r" (res)\
216	: "a" (eax), "b" (ebx), "c" (ecx), "d" (edx), "S" (esi), "D" (edi));\
217	printf("lea %s = " FMTLX "\n", STR, res);\
218	}
219
220	#define TEST_LEA16(STR)\
221	{\
222	asm(".code16 ; .byte 0x67 ; leal " STR ", %0 ; .code32"\
223	: "=wq" (res)\
224	: "a" (eax), "b" (ebx), "c" (ecx), "d" (edx), "S" (esi), "D" (edi));\
225	printf("lea %s = %08lx\n", STR, res);\
226	}
227
228
229	void test_lea(void)
230	{
231	long eax, ebx, ecx, edx, esi, edi, res;
232	eax = i2l(0x0001);
233	ebx = i2l(0x0002);
234	ecx = i2l(0x0004);
235	edx = i2l(0x0008);
236	esi = i2l(0x0010);
237	edi = i2l(0x0020);
238
239	TEST_LEA("0x4000");
240
241	TEST_LEA("(%%eax)");
242	TEST_LEA("(%%ebx)");
243	TEST_LEA("(%%ecx)");
244	TEST_LEA("(%%edx)");
245	TEST_LEA("(%%esi)");
246	TEST_LEA("(%%edi)");
247
248	TEST_LEA("0x40(%%eax)");
249	TEST_LEA("0x40(%%ebx)");
250	TEST_LEA("0x40(%%ecx)");
251	TEST_LEA("0x40(%%edx)");
252	TEST_LEA("0x40(%%esi)");
253	TEST_LEA("0x40(%%edi)");
254
255	TEST_LEA("0x4000(%%eax)");
256	TEST_LEA("0x4000(%%ebx)");
257	TEST_LEA("0x4000(%%ecx)");
258	TEST_LEA("0x4000(%%edx)");
259	TEST_LEA("0x4000(%%esi)");
260	TEST_LEA("0x4000(%%edi)");
261
262	TEST_LEA("(%%eax, %%ecx)");
263	TEST_LEA("(%%ebx, %%edx)");
264	TEST_LEA("(%%ecx, %%ecx)");
265	TEST_LEA("(%%edx, %%ecx)");
266	TEST_LEA("(%%esi, %%ecx)");
267	TEST_LEA("(%%edi, %%ecx)");
268
269	TEST_LEA("0x40(%%eax, %%ecx)");
270	TEST_LEA("0x4000(%%ebx, %%edx)");
271
272	TEST_LEA("(%%ecx, %%ecx, 2)");
273	TEST_LEA("(%%edx, %%ecx, 4)");
274	TEST_LEA("(%%esi, %%ecx, 8)");
275
276	TEST_LEA("(,%%eax, 2)");
277	TEST_LEA("(,%%ebx, 4)");
278	TEST_LEA("(,%%ecx, 8)");
279
280	TEST_LEA("0x40(,%%eax, 2)");
281	TEST_LEA("0x40(,%%ebx, 4)");
282	TEST_LEA("0x40(,%%ecx, 8)");
283
284
285	TEST_LEA("-10(%%ecx, %%ecx, 2)");
286	TEST_LEA("-10(%%edx, %%ecx, 4)");
287	TEST_LEA("-10(%%esi, %%ecx, 8)");
288
289	TEST_LEA("0x4000(%%ecx, %%ecx, 2)");
290	TEST_LEA("0x4000(%%edx, %%ecx, 4)");
291	TEST_LEA("0x4000(%%esi, %%ecx, 8)");
292
293	#if defined(__x86_64__)
294	TEST_LEAQ("0x4000");
295	TEST_LEAQ("0x4000(%%rip)");
296
297	TEST_LEAQ("(%%rax)");
298	TEST_LEAQ("(%%rbx)");
299	TEST_LEAQ("(%%rcx)");
300	TEST_LEAQ("(%%rdx)");
301	TEST_LEAQ("(%%rsi)");
302	TEST_LEAQ("(%%rdi)");
303
304	TEST_LEAQ("0x40(%%rax)");
305	TEST_LEAQ("0x40(%%rbx)");
306	TEST_LEAQ("0x40(%%rcx)");
307	TEST_LEAQ("0x40(%%rdx)");
308	TEST_LEAQ("0x40(%%rsi)");
309	TEST_LEAQ("0x40(%%rdi)");
310
311	TEST_LEAQ("0x4000(%%rax)");
312	TEST_LEAQ("0x4000(%%rbx)");
313	TEST_LEAQ("0x4000(%%rcx)");
314	TEST_LEAQ("0x4000(%%rdx)");
315	TEST_LEAQ("0x4000(%%rsi)");
316	TEST_LEAQ("0x4000(%%rdi)");
317
318	TEST_LEAQ("(%%rax, %%rcx)");
319	TEST_LEAQ("(%%rbx, %%rdx)");
320	TEST_LEAQ("(%%rcx, %%rcx)");
321	TEST_LEAQ("(%%rdx, %%rcx)");
322	TEST_LEAQ("(%%rsi, %%rcx)");
323	TEST_LEAQ("(%%rdi, %%rcx)");
324
325	TEST_LEAQ("0x40(%%rax, %%rcx)");
326	TEST_LEAQ("0x4000(%%rbx, %%rdx)");
327
328	TEST_LEAQ("(%%rcx, %%rcx, 2)");
329	TEST_LEAQ("(%%rdx, %%rcx, 4)");
330	TEST_LEAQ("(%%rsi, %%rcx, 8)");
331
332	TEST_LEAQ("(,%%rax, 2)");
333	TEST_LEAQ("(,%%rbx, 4)");
334	TEST_LEAQ("(,%%rcx, 8)");
335
336	TEST_LEAQ("0x40(,%%rax, 2)");
337	TEST_LEAQ("0x40(,%%rbx, 4)");
338	TEST_LEAQ("0x40(,%%rcx, 8)");
339
340
341	TEST_LEAQ("-10(%%rcx, %%rcx, 2)");
342	TEST_LEAQ("-10(%%rdx, %%rcx, 4)");
343	TEST_LEAQ("-10(%%rsi, %%rcx, 8)");
344
345	TEST_LEAQ("0x4000(%%rcx, %%rcx, 2)");
346	TEST_LEAQ("0x4000(%%rdx, %%rcx, 4)");
347	TEST_LEAQ("0x4000(%%rsi, %%rcx, 8)");
348	#else
349	/* limited 16 bit addressing test */
350	TEST_LEA16("0x4000");
351	TEST_LEA16("(%%bx)");
352	TEST_LEA16("(%%si)");
353	TEST_LEA16("(%%di)");
354	TEST_LEA16("0x40(%%bx)");
355	TEST_LEA16("0x40(%%si)");
356	TEST_LEA16("0x40(%%di)");
357	TEST_LEA16("0x4000(%%bx)");
358	TEST_LEA16("0x4000(%%si)");
359	TEST_LEA16("(%%bx,%%si)");
360	TEST_LEA16("(%%bx,%%di)");
361	TEST_LEA16("0x40(%%bx,%%si)");
362	TEST_LEA16("0x40(%%bx,%%di)");
363	TEST_LEA16("0x4000(%%bx,%%si)");
364	TEST_LEA16("0x4000(%%bx,%%di)");
365	#endif
366	}
367
368	#define TEST_JCC(JCC, v1, v2)\
369	{\
370	int res;\
371	asm("movl $1, %0\n\t"\
372	"cmpl %2, %1\n\t"\
373	"j" JCC " 1f\n\t"\
374	"movl $0, %0\n\t"\
375	"1:\n\t"\
376	: "=r" (res)\
377	: "r" (v1), "r" (v2));\
378	printf("%-10s %d\n", "j" JCC, res);\
379	\
380	asm("movl $0, %0\n\t"\
381	"cmpl %2, %1\n\t"\
382	"set" JCC " %b0\n\t"\
383	: "=r" (res)\
384	: "r" (v1), "r" (v2));\
385	printf("%-10s %d\n", "set" JCC, res);\
386	if (TEST_CMOV) {\
387	long val = i2l(1);\
388	long res = i2l(0x12345678);\
389	X86_64_ONLY(\
390	asm("cmpl %2, %1\n\t"\
391	"cmov" JCC "q %3, %0\n\t"\
392	: "=r" (res)\
393	: "r" (v1), "r" (v2), "m" (val), "0" (res));\
394	printf("%-10s R=" FMTLX "\n", "cmov" JCC "q", res);)\
395	asm("cmpl %2, %1\n\t"\
396	"cmov" JCC "l %k3, %k0\n\t"\
397	: "=r" (res)\
398	: "r" (v1), "r" (v2), "m" (val), "0" (res));\
399	printf("%-10s R=" FMTLX "\n", "cmov" JCC "l", res);\
400	asm("cmpl %2, %1\n\t"\
401	"cmov" JCC "w %w3, %w0\n\t"\
402	: "=r" (res)\
403	: "r" (v1), "r" (v2), "r" (1), "0" (res));\
404	printf("%-10s R=" FMTLX "\n", "cmov" JCC "w", res);\
405	} \
406	}
407
408	/* various jump tests */
409	void test_jcc(void)
410	{
411	TEST_JCC("ne", 1, 1);
412	TEST_JCC("ne", 1, 0);
413
414	TEST_JCC("e", 1, 1);
415	TEST_JCC("e", 1, 0);
416
417	TEST_JCC("l", 1, 1);
418	TEST_JCC("l", 1, 0);
419	TEST_JCC("l", 1, -1);
420
421	TEST_JCC("le", 1, 1);
422	TEST_JCC("le", 1, 0);
423	TEST_JCC("le", 1, -1);
424
425	TEST_JCC("ge", 1, 1);
426	TEST_JCC("ge", 1, 0);
427	TEST_JCC("ge", -1, 1);
428
429	TEST_JCC("g", 1, 1);
430	TEST_JCC("g", 1, 0);
431	TEST_JCC("g", 1, -1);
432
433	TEST_JCC("b", 1, 1);
434	TEST_JCC("b", 1, 0);
435	TEST_JCC("b", 1, -1);
436
437	TEST_JCC("be", 1, 1);
438	TEST_JCC("be", 1, 0);
439	TEST_JCC("be", 1, -1);
440
441	TEST_JCC("ae", 1, 1);
442	TEST_JCC("ae", 1, 0);
443	TEST_JCC("ae", 1, -1);
444
445	TEST_JCC("a", 1, 1);
446	TEST_JCC("a", 1, 0);
447	TEST_JCC("a", 1, -1);
448
449
450	TEST_JCC("p", 1, 1);
451	TEST_JCC("p", 1, 0);
452
453	TEST_JCC("np", 1, 1);
454	TEST_JCC("np", 1, 0);
455
456	TEST_JCC("o", 0x7fffffff, 0);
457	TEST_JCC("o", 0x7fffffff, -1);
458
459	TEST_JCC("no", 0x7fffffff, 0);
460	TEST_JCC("no", 0x7fffffff, -1);
461
462	TEST_JCC("s", 0, 1);
463	TEST_JCC("s", 0, -1);
464	TEST_JCC("s", 0, 0);
465
466	TEST_JCC("ns", 0, 1);
467	TEST_JCC("ns", 0, -1);
468	TEST_JCC("ns", 0, 0);
469	}
470
471	#define TEST_LOOP(insn) \
472	{\
473	for(i = 0; i < sizeof(ecx_vals) / sizeof(long); i++) {\
474	ecx = ecx_vals[i];\
475	for(zf = 0; zf < 2; zf++) {\
476	asm("test %2, %2\n\t"\
477	"movl $1, %0\n\t"\
478	insn " 1f\n\t" \
479	"movl $0, %0\n\t"\
480	"1:\n\t"\
481	: "=a" (res)\
482	: "c" (ecx), "b" (!zf)); \
483	printf("%-10s ECX=" FMTLX " ZF=%ld r=%d\n", insn, ecx, zf, res); \
484	}\
485	}\
486	}
487
488	void test_loop(void)
489	{
490	long ecx, zf;
491	const long ecx_vals[] = {
492	0,
493	1,
494	0x10000,
495	0x10001,
496	#if defined(__x86_64__)
497	0x100000000L,
498	0x100000001L,
499	#endif
500	};
501	int i, res;
502
503	#if !defined(__x86_64__)
504	TEST_LOOP("jcxz");
505	TEST_LOOP("loopw");
506	TEST_LOOP("loopzw");
507	TEST_LOOP("loopnzw");
508	#endif
509
510	TEST_LOOP("jecxz");
511	TEST_LOOP("loopl");
512	TEST_LOOP("loopzl");
513	TEST_LOOP("loopnzl");
514	}
515
516	#undef CC_MASK
517	#ifdef TEST_P4_FLAGS
518	#define CC_MASK (CC_C \| CC_P \| CC_Z \| CC_S \| CC_O \| CC_A)
519	#else
520	#define CC_MASK (CC_O \| CC_C)
521	#endif
522
523	#define OP mul
524	#include "test-i386-muldiv.h"
525
526	#define OP imul
527	#include "test-i386-muldiv.h"
528
529	void test_imulw2(long op0, long op1)
530	{
531	long res, s1, s0, flags;
532	s0 = op0;
533	s1 = op1;
534	res = s0;
535	flags = 0;
536	asm volatile ("push %4\n\t"
537	"popf\n\t"
538	"imulw %w2, %w0\n\t"
539	"pushf\n\t"
540	"pop %1\n\t"
541	: "=q" (res), "=g" (flags)
542	: "q" (s1), "0" (res), "1" (flags));
543	printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CC=%04lx\n",
544	"imulw", s0, s1, res, flags & CC_MASK);
545	}
546
547	void test_imull2(long op0, long op1)
548	{
549	long res, s1, s0, flags;
550	s0 = op0;
551	s1 = op1;
552	res = s0;
553	flags = 0;
554	asm volatile ("push %4\n\t"
555	"popf\n\t"
556	"imull %k2, %k0\n\t"
557	"pushf\n\t"
558	"pop %1\n\t"
559	: "=q" (res), "=g" (flags)
560	: "q" (s1), "0" (res), "1" (flags));
561	printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CC=%04lx\n",
562	"imull", s0, s1, res, flags & CC_MASK);
563	}
564
565	#if defined(__x86_64__)
566	void test_imulq2(long op0, long op1)
567	{
568	long res, s1, s0, flags;
569	s0 = op0;
570	s1 = op1;
571	res = s0;
572	flags = 0;
573	asm volatile ("push %4\n\t"
574	"popf\n\t"
575	"imulq %2, %0\n\t"
576	"pushf\n\t"
577	"pop %1\n\t"
578	: "=q" (res), "=g" (flags)
579	: "q" (s1), "0" (res), "1" (flags));
580	printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CC=%04lx\n",
581	"imulq", s0, s1, res, flags & CC_MASK);
582	}
583	#endif
584
585	#define TEST_IMUL_IM(size, rsize, op0, op1)\
586	{\
587	long res, flags, s1;\
588	flags = 0;\
589	res = 0;\
590	s1 = op1;\
591	asm volatile ("push %3\n\t"\
592	"popf\n\t"\
593	"imul" size " $" #op0 ", %" rsize "2, %" rsize "0\n\t" \
594	"pushf\n\t"\
595	"pop %1\n\t"\
596	: "=r" (res), "=g" (flags)\
597	: "r" (s1), "1" (flags), "0" (res));\
598	printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CC=%04lx\n",\
599	"imul" size " im", (long)op0, (long)op1, res, flags & CC_MASK);\
600	}
601
602
603	#undef CC_MASK
604	#define CC_MASK (0)
605
606	#define OP div
607	#include "test-i386-muldiv.h"
608
609	#define OP idiv
610	#include "test-i386-muldiv.h"
611
612	void test_mul(void)
613	{
614	test_imulb(0x1234561d, 4);
615	test_imulb(3, -4);
616	test_imulb(0x80, 0x80);
617	test_imulb(0x10, 0x10);
618
619	test_imulw(0, 0x1234001d, 45);
620	test_imulw(0, 23, -45);
621	test_imulw(0, 0x8000, 0x8000);
622	test_imulw(0, 0x100, 0x100);
623
624	test_imull(0, 0x1234001d, 45);
625	test_imull(0, 23, -45);
626	test_imull(0, 0x80000000, 0x80000000);
627	test_imull(0, 0x10000, 0x10000);
628
629	test_mulb(0x1234561d, 4);
630	test_mulb(3, -4);
631	test_mulb(0x80, 0x80);
632	test_mulb(0x10, 0x10);
633
634	test_mulw(0, 0x1234001d, 45);
635	test_mulw(0, 23, -45);
636	test_mulw(0, 0x8000, 0x8000);
637	test_mulw(0, 0x100, 0x100);
638
639	test_mull(0, 0x1234001d, 45);
640	test_mull(0, 23, -45);
641	test_mull(0, 0x80000000, 0x80000000);
642	test_mull(0, 0x10000, 0x10000);
643
644	test_imulw2(0x1234001d, 45);
645	test_imulw2(23, -45);
646	test_imulw2(0x8000, 0x8000);
647	test_imulw2(0x100, 0x100);
648
649	test_imull2(0x1234001d, 45);
650	test_imull2(23, -45);
651	test_imull2(0x80000000, 0x80000000);
652	test_imull2(0x10000, 0x10000);
653
654	TEST_IMUL_IM("w", "w", 45, 0x1234);
655	TEST_IMUL_IM("w", "w", -45, 23);
656	TEST_IMUL_IM("w", "w", 0x8000, 0x80000000);
657	TEST_IMUL_IM("w", "w", 0x7fff, 0x1000);
658
659	TEST_IMUL_IM("l", "k", 45, 0x1234);
660	TEST_IMUL_IM("l", "k", -45, 23);
661	TEST_IMUL_IM("l", "k", 0x8000, 0x80000000);
662	TEST_IMUL_IM("l", "k", 0x7fff, 0x1000);
663
664	test_idivb(0x12341678, 0x127e);
665	test_idivb(0x43210123, -5);
666	test_idivb(0x12340004, -1);
667
668	test_idivw(0, 0x12345678, 12347);
669	test_idivw(0, -23223, -45);
670	test_idivw(0, 0x12348000, -1);
671	test_idivw(0x12343, 0x12345678, 0x81238567);
672
673	test_idivl(0, 0x12345678, 12347);
674	test_idivl(0, -233223, -45);
675	test_idivl(0, 0x80000000, -1);
676	test_idivl(0x12343, 0x12345678, 0x81234567);
677
678	test_divb(0x12341678, 0x127e);
679	test_divb(0x43210123, -5);
680	test_divb(0x12340004, -1);
681
682	test_divw(0, 0x12345678, 12347);
683	test_divw(0, -23223, -45);
684	test_divw(0, 0x12348000, -1);
685	test_divw(0x12343, 0x12345678, 0x81238567);
686
687	test_divl(0, 0x12345678, 12347);
688	test_divl(0, -233223, -45);
689	test_divl(0, 0x80000000, -1);
690	test_divl(0x12343, 0x12345678, 0x81234567);
691
692	#if defined(__x86_64__)
693	test_imulq(0, 0x1234001d1234001d, 45);
694	test_imulq(0, 23, -45);
695	test_imulq(0, 0x8000000000000000, 0x8000000000000000);
696	test_imulq(0, 0x100000000, 0x100000000);
697
698	test_mulq(0, 0x1234001d1234001d, 45);
699	test_mulq(0, 23, -45);
700	test_mulq(0, 0x8000000000000000, 0x8000000000000000);
701	test_mulq(0, 0x100000000, 0x100000000);
702
703	test_imulq2(0x1234001d1234001d, 45);
704	test_imulq2(23, -45);
705	test_imulq2(0x8000000000000000, 0x8000000000000000);
706	test_imulq2(0x100000000, 0x100000000);
707
708	TEST_IMUL_IM("q", "", 45, 0x12341234);
709	TEST_IMUL_IM("q", "", -45, 23);
710	TEST_IMUL_IM("q", "", 0x8000, 0x8000000000000000);
711	TEST_IMUL_IM("q", "", 0x7fff, 0x10000000);
712
713	test_idivq(0, 0x12345678abcdef, 12347);
714	test_idivq(0, -233223, -45);
715	test_idivq(0, 0x8000000000000000, -1);
716	test_idivq(0x12343, 0x12345678, 0x81234567);
717
718	test_divq(0, 0x12345678abcdef, 12347);
719	test_divq(0, -233223, -45);
720	test_divq(0, 0x8000000000000000, -1);
721	test_divq(0x12343, 0x12345678, 0x81234567);
722	#endif
723	}
724
725	#define TEST_BSX(op, size, op0)\
726	{\
727	long res, val, resz;\
728	val = op0;\
729	asm("xor %1, %1\n"\
730	"mov $0x12345678, %0\n"\
731	#op " %" size "2, %" size "0 ; setz %b1" \
732	: "=&r" (res), "=&q" (resz)\
733	: "r" (val));\
734	printf("%-10s A=" FMTLX " R=" FMTLX " %ld\n", #op, val, res, resz);\
735	}
736
737	void test_bsx(void)
738	{
739	TEST_BSX(bsrw, "w", 0);
740	TEST_BSX(bsrw, "w", 0x12340128);
741	TEST_BSX(bsfw, "w", 0);
742	TEST_BSX(bsfw, "w", 0x12340128);
743	TEST_BSX(bsrl, "k", 0);
744	TEST_BSX(bsrl, "k", 0x00340128);
745	TEST_BSX(bsfl, "k", 0);
746	TEST_BSX(bsfl, "k", 0x00340128);
747	#if defined(__x86_64__)
748	TEST_BSX(bsrq, "", 0);
749	TEST_BSX(bsrq, "", 0x003401281234);
750	TEST_BSX(bsfq, "", 0);
751	TEST_BSX(bsfq, "", 0x003401281234);
752	#endif
753	}
754
755	/**********************************************/
756
757	union float64u {
758	double d;
759	uint64_t l;
760	};
761
762	union float64u q_nan = { .l = 0xFFF8000000000000LL };
763	union float64u s_nan = { .l = 0xFFF0000000000000LL };
764
765	void test_fops(double a, double b)
766	{
767	printf("a=%f b=%f a+b=%f\n", a, b, a + b);
768	printf("a=%f b=%f a-b=%f\n", a, b, a - b);
769	printf("a=%f b=%f ab=%f\n", a, b, a b);
770	printf("a=%f b=%f a/b=%f\n", a, b, a / b);
771	printf("a=%f b=%f fmod(a, b)=%f\n", a, b, fmod(a, b));
772	printf("a=%f sqrt(a)=%f\n", a, sqrt(a));
773	printf("a=%f sin(a)=%f\n", a, sin(a));
774	printf("a=%f cos(a)=%f\n", a, cos(a));
775	printf("a=%f tan(a)=%f\n", a, tan(a));
776	printf("a=%f log(a)=%f\n", a, log(a));
777	printf("a=%f exp(a)=%f\n", a, exp(a));
778	printf("a=%f b=%f atan2(a, b)=%f\n", a, b, atan2(a, b));
779	/* just to test some op combining */
780	printf("a=%f asin(sin(a))=%f\n", a, asin(sin(a)));
781	printf("a=%f acos(cos(a))=%f\n", a, acos(cos(a)));
782	printf("a=%f atan(tan(a))=%f\n", a, atan(tan(a)));
783
784	}
785
786	void fpu_clear_exceptions(void)
787	{
788	struct __attribute__((packed)) {
789	uint16_t fpuc;
790	uint16_t dummy1;
791	uint16_t fpus;
792	uint16_t dummy2;
793	uint16_t fptag;
794	uint16_t dummy3;
795	uint32_t ignored[4];
796	long double fpregs[8];
797	} float_env32;
798
799	asm volatile ("fnstenv %0\n" : : "m" (float_env32));
800	float_env32.fpus &= ~0x7f;
801	asm volatile ("fldenv %0\n" : : "m" (float_env32));
802	}
803
804	/* XXX: display exception bits when supported */
805	#define FPUS_EMASK 0x0000
806	//#define FPUS_EMASK 0x007f
807
808	void test_fcmp(double a, double b)
809	{
810	long eflags, fpus;
811
812	fpu_clear_exceptions();
813	asm("fcom %2\n"
814	"fstsw %%ax\n"
815	: "=a" (fpus)
816	: "t" (a), "u" (b));
817	printf("fcom(%f %f)=%04lx \n",
818	a, b, fpus & (0x4500 \| FPUS_EMASK));
819	fpu_clear_exceptions();
820	asm("fucom %2\n"
821	"fstsw %%ax\n"
822	: "=a" (fpus)
823	: "t" (a), "u" (b));
824	printf("fucom(%f %f)=%04lx\n",
825	a, b, fpus & (0x4500 \| FPUS_EMASK));
826	if (TEST_FCOMI) {
827	/* test f(u)comi instruction */
828	fpu_clear_exceptions();
829	asm("fcomi %3, %2\n"
830	"fstsw %%ax\n"
831	"pushf\n"
832	"pop %0\n"
833	: "=r" (eflags), "=a" (fpus)
834	: "t" (a), "u" (b));
835	printf("fcomi(%f %f)=%04lx %02lx\n",
836	a, b, fpus & FPUS_EMASK, eflags & (CC_Z \| CC_P \| CC_C));
837	fpu_clear_exceptions();
838	asm("fucomi %3, %2\n"
839	"fstsw %%ax\n"
840	"pushf\n"
841	"pop %0\n"
842	: "=r" (eflags), "=a" (fpus)
843	: "t" (a), "u" (b));
844	printf("fucomi(%f %f)=%04lx %02lx\n",
845	a, b, fpus & FPUS_EMASK, eflags & (CC_Z \| CC_P \| CC_C));
846	}
847	fpu_clear_exceptions();
848	asm volatile("fxam\n"
849	"fstsw %%ax\n"
850	: "=a" (fpus)
851	: "t" (a));
852	printf("fxam(%f)=%04lx\n", a, fpus & 0x4700);
853	fpu_clear_exceptions();
854	}
855
856	void test_fcvt(double a)
857	{
858	float fa;
859	long double la;
860	int16_t fpuc;
861	int i;
862	int64_t lla;
863	int ia;
864	int16_t wa;
865	double ra;
866
867	fa = a;
868	la = a;
869	printf("(float)%f = %f\n", a, fa);
870	printf("(long double)%f = %Lf\n", a, la);
871	printf("a=" FMT64X "\n", (uint64_t )&a);
872	printf("la=" FMT64X " %04x\n", (uint64_t )&la,
873	(unsigned short )((char *)(&la) + 8));
874
875	/* test all roundings */
876	asm volatile ("fstcw %0" : "=m" (fpuc));
877	for(i=0;i<4;i++) {
878	uint16_t val16;
879	val16 = (fpuc & ~0x0c00) \| (i << 10);
880	asm volatile ("fldcw %0" : : "m" (val16));
881	asm volatile ("fist %0" : "=m" (wa) : "t" (a));
882	asm volatile ("fistl %0" : "=m" (ia) : "t" (a));
883	asm volatile ("fistpll %0" : "=m" (lla) : "t" (a) : "st");
884	asm volatile ("frndint ; fstl %0" : "=m" (ra) : "t" (a));
885	asm volatile ("fldcw %0" : : "m" (fpuc));
886	printf("(short)a = %d\n", wa);
887	printf("(int)a = %d\n", ia);
888	printf("(int64_t)a = " FMT64X "\n", lla);
889	printf("rint(a) = %f\n", ra);
890	}
891	}
892
893	#define TEST(N) \
894	asm("fld" #N : "=t" (a)); \
895	printf("fld" #N "= %f\n", a);
896
897	void test_fconst(void)
898	{
899	double a;
900	TEST(1);
901	TEST(l2t);
902	TEST(l2e);
903	TEST(pi);
904	TEST(lg2);
905	TEST(ln2);
906	TEST(z);
907	}
908
909	void test_fbcd(double a)
910	{
911	unsigned short bcd[5];
912	double b;
913
914	asm("fbstp %0" : "=m" (bcd[0]) : "t" (a) : "st");
915	asm("fbld %1" : "=t" (b) : "m" (bcd[0]));
916	printf("a=%f bcd=%04x%04x%04x%04x%04x b=%f\n",
917	a, bcd[4], bcd[3], bcd[2], bcd[1], bcd[0], b);
918	}
919
920	#define TEST_ENV(env, save, restore)\
921	{\
922	memset((env), 0xaa, sizeof(*(env)));\
923	for(i=0;i<5;i++)\
924	asm volatile ("fldl %0" : : "m" (dtab[i]));\
925	asm volatile (save " %0\n" : : "m" (*(env)));\
926	asm volatile (restore " %0\n": : "m" (*(env)));\
927	for(i=0;i<5;i++)\
928	asm volatile ("fstpl %0" : "=m" (rtab[i]));\
929	for(i=0;i<5;i++)\
930	printf("res[%d]=%f\n", i, rtab[i]);\
931	printf("fpuc=%04x fpus=%04x fptag=%04x\n",\
932	(env)->fpuc,\
933	(env)->fpus & 0xff00,\
934	(env)->fptag);\
935	}
936
937	void test_fenv(void)
938	{
939	struct __attribute__((packed)) {
940	uint16_t fpuc;
941	uint16_t dummy1;
942	uint16_t fpus;
943	uint16_t dummy2;
944	uint16_t fptag;
945	uint16_t dummy3;
946	uint32_t ignored[4];
947	long double fpregs[8];
948	} float_env32;
949	struct __attribute__((packed)) {
950	uint16_t fpuc;
951	uint16_t fpus;
952	uint16_t fptag;
953	uint16_t ignored[4];
954	long double fpregs[8];
955	} float_env16;
956	double dtab[8];
957	double rtab[8];
958	int i;
959
960	for(i=0;i<8;i++)
961	dtab[i] = i + 1;
962
963	TEST_ENV(&float_env16, "data16 fnstenv", "data16 fldenv");
964	TEST_ENV(&float_env16, "data16 fnsave", "data16 frstor");
965	TEST_ENV(&float_env32, "fnstenv", "fldenv");
966	TEST_ENV(&float_env32, "fnsave", "frstor");
967
968	/* test for ffree */
969	for(i=0;i<5;i++)
970	asm volatile ("fldl %0" : : "m" (dtab[i]));
971	asm volatile("ffree %st(2)");
972	asm volatile ("fnstenv %0\n" : : "m" (float_env32));
973	asm volatile ("fninit");
974	printf("fptag=%04x\n", float_env32.fptag);
975	}
976
977
978	#define TEST_FCMOV(a, b, eflags, CC)\
979	{\
980	double res;\
981	asm("push %3\n"\
982	"popf\n"\
983	"fcmov" CC " %2, %0\n"\
984	: "=t" (res)\
985	: "0" (a), "u" (b), "g" (eflags));\
986	printf("fcmov%s eflags=0x%04lx-> %f\n", \
987	CC, (long)eflags, res);\
988	}
989
990	void test_fcmov(void)
991	{
992	double a, b;
993	long eflags, i;
994
995	a = 1.0;
996	b = 2.0;
997	for(i = 0; i < 4; i++) {
998	eflags = 0;
999	if (i & 1)
1000	eflags \|= CC_C;
1001	if (i & 2)
1002	eflags \|= CC_Z;
1003	TEST_FCMOV(a, b, eflags, "b");
1004	TEST_FCMOV(a, b, eflags, "e");
1005	TEST_FCMOV(a, b, eflags, "be");
1006	TEST_FCMOV(a, b, eflags, "nb");
1007	TEST_FCMOV(a, b, eflags, "ne");
1008	TEST_FCMOV(a, b, eflags, "nbe");
1009	}
1010	TEST_FCMOV(a, b, 0, "u");
1011	TEST_FCMOV(a, b, CC_P, "u");
1012	TEST_FCMOV(a, b, 0, "nu");
1013	TEST_FCMOV(a, b, CC_P, "nu");
1014	}
1015
1016	void test_floats(void)
1017	{
1018	test_fops(2, 3);
1019	test_fops(1.4, -5);
1020	test_fcmp(2, -1);
1021	test_fcmp(2, 2);
1022	test_fcmp(2, 3);
1023	test_fcmp(2, q_nan.d);
1024	test_fcmp(q_nan.d, -1);
1025	test_fcmp(-1.0/0.0, -1);
1026	test_fcmp(1.0/0.0, -1);
1027	test_fcvt(0.5);
1028	test_fcvt(-0.5);
1029	test_fcvt(1.0/7.0);
1030	test_fcvt(-1.0/9.0);
1031	test_fcvt(32768);
1032	test_fcvt(-1e20);
1033	test_fcvt(-1.0/0.0);
1034	test_fcvt(1.0/0.0);
1035	test_fcvt(q_nan.d);
1036	test_fconst();
1037	test_fbcd(1234567890123456.0);
1038	test_fbcd(-123451234567890.0);
1039	test_fenv();
1040	if (TEST_CMOV) {
1041	test_fcmov();
1042	}
1043	}
1044
1045	/**********************************************/
1046	#if !defined(__x86_64__)
1047
1048	#define TEST_BCD(op, op0, cc_in, cc_mask)\
1049	{\
1050	int res, flags;\
1051	res = op0;\
1052	flags = cc_in;\
1053	asm ("push %3\n\t"\
1054	"popf\n\t"\
1055	#op "\n\t"\
1056	"pushf\n\t"\
1057	"pop %1\n\t"\
1058	: "=a" (res), "=g" (flags)\
1059	: "0" (res), "1" (flags));\
1060	printf("%-10s A=%08x R=%08x CCIN=%04x CC=%04x\n",\
1061	#op, op0, res, cc_in, flags & cc_mask);\
1062	}
1063
1064	void test_bcd(void)
1065	{
1066	TEST_BCD(daa, 0x12340503, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1067	TEST_BCD(daa, 0x12340506, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1068	TEST_BCD(daa, 0x12340507, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1069	TEST_BCD(daa, 0x12340559, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1070	TEST_BCD(daa, 0x12340560, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1071	TEST_BCD(daa, 0x1234059f, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1072	TEST_BCD(daa, 0x123405a0, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1073	TEST_BCD(daa, 0x12340503, 0, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1074	TEST_BCD(daa, 0x12340506, 0, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1075	TEST_BCD(daa, 0x12340503, CC_C, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1076	TEST_BCD(daa, 0x12340506, CC_C, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1077	TEST_BCD(daa, 0x12340503, CC_C \| CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1078	TEST_BCD(daa, 0x12340506, CC_C \| CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1079
1080	TEST_BCD(das, 0x12340503, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1081	TEST_BCD(das, 0x12340506, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1082	TEST_BCD(das, 0x12340507, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1083	TEST_BCD(das, 0x12340559, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1084	TEST_BCD(das, 0x12340560, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1085	TEST_BCD(das, 0x1234059f, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1086	TEST_BCD(das, 0x123405a0, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1087	TEST_BCD(das, 0x12340503, 0, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1088	TEST_BCD(das, 0x12340506, 0, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1089	TEST_BCD(das, 0x12340503, CC_C, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1090	TEST_BCD(das, 0x12340506, CC_C, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1091	TEST_BCD(das, 0x12340503, CC_C \| CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1092	TEST_BCD(das, 0x12340506, CC_C \| CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_A));
1093
1094	TEST_BCD(aaa, 0x12340205, CC_A, (CC_C \| CC_A));
1095	TEST_BCD(aaa, 0x12340306, CC_A, (CC_C \| CC_A));
1096	TEST_BCD(aaa, 0x1234040a, CC_A, (CC_C \| CC_A));
1097	TEST_BCD(aaa, 0x123405fa, CC_A, (CC_C \| CC_A));
1098	TEST_BCD(aaa, 0x12340205, 0, (CC_C \| CC_A));
1099	TEST_BCD(aaa, 0x12340306, 0, (CC_C \| CC_A));
1100	TEST_BCD(aaa, 0x1234040a, 0, (CC_C \| CC_A));
1101	TEST_BCD(aaa, 0x123405fa, 0, (CC_C \| CC_A));
1102
1103	TEST_BCD(aas, 0x12340205, CC_A, (CC_C \| CC_A));
1104	TEST_BCD(aas, 0x12340306, CC_A, (CC_C \| CC_A));
1105	TEST_BCD(aas, 0x1234040a, CC_A, (CC_C \| CC_A));
1106	TEST_BCD(aas, 0x123405fa, CC_A, (CC_C \| CC_A));
1107	TEST_BCD(aas, 0x12340205, 0, (CC_C \| CC_A));
1108	TEST_BCD(aas, 0x12340306, 0, (CC_C \| CC_A));
1109	TEST_BCD(aas, 0x1234040a, 0, (CC_C \| CC_A));
1110	TEST_BCD(aas, 0x123405fa, 0, (CC_C \| CC_A));
1111
1112	TEST_BCD(aam, 0x12340547, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_O \| CC_A));
1113	TEST_BCD(aad, 0x12340407, CC_A, (CC_C \| CC_P \| CC_Z \| CC_S \| CC_O \| CC_A));
1114	}
1115	#endif
1116
1117	#define TEST_XCHG(op, size, opconst)\
1118	{\
1119	long op0, op1;\
1120	op0 = i2l(0x12345678);\
1121	op1 = i2l(0xfbca7654);\
1122	asm(#op " %" size "0, %" size "1" \
1123	: "=q" (op0), opconst (op1) \
1124	: "0" (op0));\
1125	printf("%-10s A=" FMTLX " B=" FMTLX "\n",\
1126	#op, op0, op1);\
1127	}
1128
1129	#define TEST_CMPXCHG(op, size, opconst, eax)\
1130	{\
1131	long op0, op1, op2;\
1132	op0 = i2l(0x12345678);\
1133	op1 = i2l(0xfbca7654);\
1134	op2 = i2l(eax);\
1135	asm(#op " %" size "0, %" size "1" \
1136	: "=q" (op0), opconst (op1) \
1137	: "0" (op0), "a" (op2));\
1138	printf("%-10s EAX=" FMTLX " A=" FMTLX " C=" FMTLX "\n",\
1139	#op, op2, op0, op1);\
1140	}
1141
1142	void test_xchg(void)
1143	{
1144	#if defined(__x86_64__)
1145	TEST_XCHG(xchgq, "", "+q");
1146	#endif
1147	TEST_XCHG(xchgl, "k", "+q");
1148	TEST_XCHG(xchgw, "w", "+q");
1149	TEST_XCHG(xchgb, "b", "+q");
1150
1151	#if defined(__x86_64__)
1152	TEST_XCHG(xchgq, "", "=m");
1153	#endif
1154	TEST_XCHG(xchgl, "k", "+m");
1155	TEST_XCHG(xchgw, "w", "+m");
1156	TEST_XCHG(xchgb, "b", "+m");
1157
1158	#if defined(__x86_64__)
1159	TEST_XCHG(xaddq, "", "+q");
1160	#endif
1161	TEST_XCHG(xaddl, "k", "+q");
1162	TEST_XCHG(xaddw, "w", "+q");
1163	TEST_XCHG(xaddb, "b", "+q");
1164
1165	{
1166	int res;
1167	res = 0x12345678;
1168	asm("xaddl %1, %0" : "=r" (res) : "0" (res));
1169	printf("xaddl same res=%08x\n", res);
1170	}
1171
1172	#if defined(__x86_64__)
1173	TEST_XCHG(xaddq, "", "+m");
1174	#endif
1175	TEST_XCHG(xaddl, "k", "+m");
1176	TEST_XCHG(xaddw, "w", "+m");
1177	TEST_XCHG(xaddb, "b", "+m");
1178
1179	#if defined(__x86_64__)
1180	TEST_CMPXCHG(cmpxchgq, "", "+q", 0xfbca7654);
1181	#endif
1182	TEST_CMPXCHG(cmpxchgl, "k", "+q", 0xfbca7654);
1183	TEST_CMPXCHG(cmpxchgw, "w", "+q", 0xfbca7654);
1184	TEST_CMPXCHG(cmpxchgb, "b", "+q", 0xfbca7654);
1185
1186	#if defined(__x86_64__)
1187	TEST_CMPXCHG(cmpxchgq, "", "+q", 0xfffefdfc);
1188	#endif
1189	TEST_CMPXCHG(cmpxchgl, "k", "+q", 0xfffefdfc);
1190	TEST_CMPXCHG(cmpxchgw, "w", "+q", 0xfffefdfc);
1191	TEST_CMPXCHG(cmpxchgb, "b", "+q", 0xfffefdfc);
1192
1193	#if defined(__x86_64__)
1194	TEST_CMPXCHG(cmpxchgq, "", "+m", 0xfbca7654);
1195	#endif
1196	TEST_CMPXCHG(cmpxchgl, "k", "+m", 0xfbca7654);
1197	TEST_CMPXCHG(cmpxchgw, "w", "+m", 0xfbca7654);
1198	TEST_CMPXCHG(cmpxchgb, "b", "+m", 0xfbca7654);
1199
1200	#if defined(__x86_64__)
1201	TEST_CMPXCHG(cmpxchgq, "", "+m", 0xfffefdfc);
1202	#endif
1203	TEST_CMPXCHG(cmpxchgl, "k", "+m", 0xfffefdfc);
1204	TEST_CMPXCHG(cmpxchgw, "w", "+m", 0xfffefdfc);
1205	TEST_CMPXCHG(cmpxchgb, "b", "+m", 0xfffefdfc);
1206
1207	{
1208	uint64_t op0, op1, op2;
1209	long eax, edx;
1210	long i, eflags;
1211
1212	for(i = 0; i < 2; i++) {
1213	op0 = 0x123456789abcdLL;
1214	eax = i2l(op0 & 0xffffffff);
1215	edx = i2l(op0 >> 32);
1216	if (i == 0)
1217	op1 = 0xfbca765423456LL;
1218	else
1219	op1 = op0;
1220	op2 = 0x6532432432434LL;
1221	asm("cmpxchg8b %2\n"
1222	"pushf\n"
1223	"pop %3\n"
1224	: "=a" (eax), "=d" (edx), "=m" (op1), "=g" (eflags)
1225	: "0" (eax), "1" (edx), "m" (op1), "b" ((int)op2), "c" ((int)(op2 >> 32)));
1226	printf("cmpxchg8b: eax=" FMTLX " edx=" FMTLX " op1=" FMT64X " CC=%02lx\n",
1227	eax, edx, op1, eflags & CC_Z);
1228	}
1229	}
1230	}
1231
1232	#ifdef TEST_SEGS
1233	/**********************************************/
1234	/* segmentation tests */
1235
1236	#include <sys/syscall.h>
1237	#include <unistd.h>
1238	#include <asm/ldt.h>
1239	#include <linux/version.h>
1240
1241	static inline int modify_ldt(int func, void * ptr, unsigned long bytecount)
1242	{
1243	return syscall(__NR_modify_ldt, func, ptr, bytecount);
1244	}
1245
1246	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 5, 66)
1247	#define modify_ldt_ldt_s user_desc
1248	#endif
1249
1250	#define MK_SEL(n) (((n) << 3) \| 7)
1251
1252	uint8_t seg_data1[4096];
1253	uint8_t seg_data2[4096];
1254
1255	#define TEST_LR(op, size, seg, mask)\
1256	{\
1257	int res, res2;\
1258	uint16_t mseg = seg;\
1259	res = 0x12345678;\
1260	asm (op " %" size "2, %" size "0\n" \
1261	"movl $0, %1\n"\
1262	"jnz 1f\n"\
1263	"movl $1, %1\n"\
1264	"1:\n"\
1265	: "=r" (res), "=r" (res2) : "m" (mseg), "0" (res));\
1266	printf(op ": Z=%d %08x\n", res2, res & ~(mask));\
1267	}
1268
1269	#define TEST_ARPL(op, size, op1, op2)\
1270	{\
1271	long a, b, c; \
1272	a = (op1); \
1273	b = (op2); \
1274	asm volatile(op " %" size "3, %" size "0\n"\
1275	"movl $0,%1\n"\
1276	"jnz 1f\n"\
1277	"movl $1,%1\n"\
1278	"1:\n"\
1279	: "=r" (a), "=r" (c) : "0" (a), "r" (b)); \
1280	printf(op size " A=" FMTLX " B=" FMTLX " R=" FMTLX " z=%ld\n",\
1281	(long)(op1), (long)(op2), a, c);\
1282	}
1283
1284	/* NOTE: we use Linux modify_ldt syscall */
1285	void test_segs(void)
1286	{
1287	struct modify_ldt_ldt_s ldt;
1288	long long ldt_table[3];
1289	int res, res2;
1290	char tmp;
1291	struct {
1292	uint32_t offset;
1293	uint16_t seg;
1294	} __attribute__((packed)) segoff;
1295
1296	ldt.entry_number = 1;
1297	ldt.base_addr = (unsigned long)&seg_data1;
1298	ldt.limit = (sizeof(seg_data1) + 0xfff) >> 12;
1299	ldt.seg_32bit = 1;
1300	ldt.contents = MODIFY_LDT_CONTENTS_DATA;
1301	ldt.read_exec_only = 0;
1302	ldt.limit_in_pages = 1;
1303	ldt.seg_not_present = 0;
1304	ldt.useable = 1;
1305	modify_ldt(1, &ldt, sizeof(ldt)); /* write ldt entry */
1306
1307	ldt.entry_number = 2;
1308	ldt.base_addr = (unsigned long)&seg_data2;
1309	ldt.limit = (sizeof(seg_data2) + 0xfff) >> 12;
1310	ldt.seg_32bit = 1;
1311	ldt.contents = MODIFY_LDT_CONTENTS_DATA;
1312	ldt.read_exec_only = 0;
1313	ldt.limit_in_pages = 1;
1314	ldt.seg_not_present = 0;
1315	ldt.useable = 1;
1316	modify_ldt(1, &ldt, sizeof(ldt)); /* write ldt entry */
1317
1318	modify_ldt(0, &ldt_table, sizeof(ldt_table)); /* read ldt entries */
1319	#if 0
1320	{
1321	int i;
1322	for(i=0;i<3;i++)
1323	printf("%d: %016Lx\n", i, ldt_table[i]);
1324	}
1325	#endif
1326	/* do some tests with fs or gs */
1327	asm volatile ("movl %0, %%fs" : : "r" (MK_SEL(1)));
1328
1329	seg_data1[1] = 0xaa;
1330	seg_data2[1] = 0x55;
1331
1332	asm volatile ("fs movzbl 0x1, %0" : "=r" (res));
1333	printf("FS[1] = %02x\n", res);
1334
1335	asm volatile ("pushl %%gs\n"
1336	"movl %1, %%gs\n"
1337	"gs movzbl 0x1, %0\n"
1338	"popl %%gs\n"
1339	: "=r" (res)
1340	: "r" (MK_SEL(2)));
1341	printf("GS[1] = %02x\n", res);
1342
1343	/* tests with ds/ss (implicit segment case) */
1344	tmp = 0xa5;
1345	asm volatile ("pushl %%ebp\n\t"
1346	"pushl %%ds\n\t"
1347	"movl %2, %%ds\n\t"
1348	"movl %3, %%ebp\n\t"
1349	"movzbl 0x1, %0\n\t"
1350	"movzbl (%%ebp), %1\n\t"
1351	"popl %%ds\n\t"
1352	"popl %%ebp\n\t"
1353	: "=r" (res), "=r" (res2)
1354	: "r" (MK_SEL(1)), "r" (&tmp));
1355	printf("DS[1] = %02x\n", res);
1356	printf("SS[tmp] = %02x\n", res2);
1357
1358	segoff.seg = MK_SEL(2);
1359	segoff.offset = 0xabcdef12;
1360	asm volatile("lfs %2, %0\n\t"
1361	"movl %%fs, %1\n\t"
1362	: "=r" (res), "=g" (res2)
1363	: "m" (segoff));
1364	printf("FS:reg = %04x:%08x\n", res2, res);
1365
1366	TEST_LR("larw", "w", MK_SEL(2), 0x0100);
1367	TEST_LR("larl", "", MK_SEL(2), 0x0100);
1368	TEST_LR("lslw", "w", MK_SEL(2), 0);
1369	TEST_LR("lsll", "", MK_SEL(2), 0);
1370
1371	TEST_LR("larw", "w", 0xfff8, 0);
1372	TEST_LR("larl", "", 0xfff8, 0);
1373	TEST_LR("lslw", "w", 0xfff8, 0);
1374	TEST_LR("lsll", "", 0xfff8, 0);
1375
1376	TEST_ARPL("arpl", "w", 0x12345678 \| 3, 0x762123c \| 1);
1377	TEST_ARPL("arpl", "w", 0x12345678 \| 1, 0x762123c \| 3);
1378	TEST_ARPL("arpl", "w", 0x12345678 \| 1, 0x762123c \| 1);
1379	}
1380
1381	/* 16 bit code test */
1382	extern char code16_start, code16_end;
1383	extern char code16_func1;
1384	extern char code16_func2;
1385	extern char code16_func3;
1386
1387	void test_code16(void)
1388	{
1389	struct modify_ldt_ldt_s ldt;
1390	int res, res2;
1391
1392	/* build a code segment */
1393	ldt.entry_number = 1;
1394	ldt.base_addr = (unsigned long)&code16_start;
1395	ldt.limit = &code16_end - &code16_start;
1396	ldt.seg_32bit = 0;
1397	ldt.contents = MODIFY_LDT_CONTENTS_CODE;
1398	ldt.read_exec_only = 0;
1399	ldt.limit_in_pages = 0;
1400	ldt.seg_not_present = 0;
1401	ldt.useable = 1;
1402	modify_ldt(1, &ldt, sizeof(ldt)); /* write ldt entry */
1403
1404	/* call the first function */
1405	asm volatile ("lcall %1, %2"
1406	: "=a" (res)
1407	: "i" (MK_SEL(1)), "i" (&code16_func1): "memory", "cc");
1408	printf("func1() = 0x%08x\n", res);
1409	asm volatile ("lcall %2, %3"
1410	: "=a" (res), "=c" (res2)
1411	: "i" (MK_SEL(1)), "i" (&code16_func2): "memory", "cc");
1412	printf("func2() = 0x%08x spdec=%d\n", res, res2);
1413	asm volatile ("lcall %1, %2"
1414	: "=a" (res)
1415	: "i" (MK_SEL(1)), "i" (&code16_func3): "memory", "cc");
1416	printf("func3() = 0x%08x\n", res);
1417	}
1418	#endif
1419
1420	#if defined(__x86_64__)
1421	asm(".globl func_lret\n"
1422	"func_lret:\n"
1423	"movl $0x87654641, %eax\n"
1424	"lretq\n");
1425	#else
1426	asm(".globl func_lret\n"
1427	"func_lret:\n"
1428	"movl $0x87654321, %eax\n"
1429	"lret\n"
1430
1431	".globl func_iret\n"
1432	"func_iret:\n"
1433	"movl $0xabcd4321, %eax\n"
1434	"iret\n");
1435	#endif
1436
1437	extern char func_lret;
1438	extern char func_iret;
1439
1440	void test_misc(void)
1441	{
1442	char table[256];
1443	long res, i;
1444
1445	for(i=0;i<256;i++) table[i] = 256 - i;
1446	res = 0x12345678;
1447	asm ("xlat" : "=a" (res) : "b" (table), "0" (res));
1448	printf("xlat: EAX=" FMTLX "\n", res);
1449
1450	#if defined(__x86_64__)
1451	#if 0
1452	{
1453	/* XXX: see if Intel Core2 and AMD64 behavior really
1454	differ. Here we implemented the Intel way which is not
1455	compatible yet with QEMU. */
1456	static struct __attribute__((packed)) {
1457	uint64_t offset;
1458	uint16_t seg;
1459	} desc;
1460	long cs_sel;
1461
1462	asm volatile ("mov %%cs, %0" : "=r" (cs_sel));
1463
1464	asm volatile ("push %1\n"
1465	"call func_lret\n"
1466	: "=a" (res)
1467	: "r" (cs_sel) : "memory", "cc");
1468	printf("func_lret=" FMTLX "\n", res);
1469
1470	desc.offset = (long)&func_lret;
1471	desc.seg = cs_sel;
1472
1473	asm volatile ("xor %%rax, %%rax\n"
1474	"rex64 lcall *(%%rcx)\n"
1475	: "=a" (res)
1476	: "c" (&desc)
1477	: "memory", "cc");
1478	printf("func_lret2=" FMTLX "\n", res);
1479
1480	asm volatile ("push %2\n"
1481	"mov $ 1f, %%rax\n"
1482	"push %%rax\n"
1483	"rex64 ljmp *(%%rcx)\n"
1484	"1:\n"
1485	: "=a" (res)
1486	: "c" (&desc), "b" (cs_sel)
1487	: "memory", "cc");
1488	printf("func_lret3=" FMTLX "\n", res);
1489	}
1490	#endif
1491	#else
1492	asm volatile ("push %%cs ; call %1"
1493	: "=a" (res)
1494	: "m" (func_lret): "memory", "cc");
1495	printf("func_lret=" FMTLX "\n", res);
1496
1497	asm volatile ("pushf ; push %%cs ; call %1"
1498	: "=a" (res)
1499	: "m" (func_iret): "memory", "cc");
1500	printf("func_iret=" FMTLX "\n", res);
1501	#endif
1502
1503	#if defined(__x86_64__)
1504	/* specific popl test */
1505	asm volatile ("push $12345432 ; push $0x9abcdef ; pop (%%rsp) ; pop %0"
1506	: "=g" (res));
1507	printf("popl esp=" FMTLX "\n", res);
1508	#else
1509	/* specific popl test */
1510	asm volatile ("pushl $12345432 ; pushl $0x9abcdef ; popl (%%esp) ; popl %0"
1511	: "=g" (res));
1512	printf("popl esp=" FMTLX "\n", res);
1513
1514	/* specific popw test */
1515	asm volatile ("pushl $12345432 ; pushl $0x9abcdef ; popw (%%esp) ; addl $2, %%esp ; popl %0"
1516	: "=g" (res));
1517	printf("popw esp=" FMTLX "\n", res);
1518	#endif
1519	}
1520
1521	uint8_t str_buffer[4096];
1522
1523	#define TEST_STRING1(OP, size, DF, REP)\
1524	{\
1525	long esi, edi, eax, ecx, eflags;\
1526	\
1527	esi = (long)(str_buffer + sizeof(str_buffer) / 2);\
1528	edi = (long)(str_buffer + sizeof(str_buffer) / 2) + 16;\
1529	eax = i2l(0x12345678);\
1530	ecx = 17;\
1531	\
1532	asm volatile ("push $0\n\t"\
1533	"popf\n\t"\
1534	DF "\n\t"\
1535	REP #OP size "\n\t"\
1536	"cld\n\t"\
1537	"pushf\n\t"\
1538	"pop %4\n\t"\
1539	: "=S" (esi), "=D" (edi), "=a" (eax), "=c" (ecx), "=g" (eflags)\
1540	: "0" (esi), "1" (edi), "2" (eax), "3" (ecx));\
1541	printf("%-10s ESI=" FMTLX " EDI=" FMTLX " EAX=" FMTLX " ECX=" FMTLX " EFL=%04x\n",\
1542	REP #OP size, esi, edi, eax, ecx,\
1543	(int)(eflags & (CC_C \| CC_P \| CC_Z \| CC_S \| CC_O \| CC_A)));\
1544	}
1545
1546	#define TEST_STRING(OP, REP)\
1547	TEST_STRING1(OP, "b", "", REP);\
1548	TEST_STRING1(OP, "w", "", REP);\
1549	TEST_STRING1(OP, "l", "", REP);\
1550	X86_64_ONLY(TEST_STRING1(OP, "q", "", REP));\
1551	TEST_STRING1(OP, "b", "std", REP);\
1552	TEST_STRING1(OP, "w", "std", REP);\
1553	TEST_STRING1(OP, "l", "std", REP);\
1554	X86_64_ONLY(TEST_STRING1(OP, "q", "std", REP))
1555
1556	void test_string(void)
1557	{
1558	int i;
1559	for(i = 0;i < sizeof(str_buffer); i++)
1560	str_buffer[i] = i + 0x56;
1561	TEST_STRING(stos, "");
1562	TEST_STRING(stos, "rep ");
1563	TEST_STRING(lods, ""); /* to verify stos */
1564	TEST_STRING(lods, "rep ");
1565	TEST_STRING(movs, "");
1566	TEST_STRING(movs, "rep ");
1567	TEST_STRING(lods, ""); /* to verify stos */
1568
1569	/* XXX: better tests */
1570	TEST_STRING(scas, "");
1571	TEST_STRING(scas, "repz ");
1572	TEST_STRING(scas, "repnz ");
1573	TEST_STRING(cmps, "");
1574	TEST_STRING(cmps, "repz ");
1575	TEST_STRING(cmps, "repnz ");
1576	}
1577
1578	#ifdef TEST_VM86
1579	/* VM86 test */
1580
1581	static inline void set_bit(uint8_t *a, unsigned int bit)
1582	{
1583	a[bit / 8] \|= (1 << (bit % 8));
1584	}
1585
1586	static inline uint8_t *seg_to_linear(unsigned int seg, unsigned int reg)
1587	{
1588	return (uint8_t *)((seg << 4) + (reg & 0xffff));
1589	}
1590
1591	static inline void pushw(struct vm86_regs *r, int val)
1592	{
1593	r->esp = (r->esp & ~0xffff) \| ((r->esp - 2) & 0xffff);
1594	(uint16_t )seg_to_linear(r->ss, r->esp) = val;
1595	}
1596
1597	static inline int vm86(int func, struct vm86plus_struct *v86)
1598	{
1599	return syscall(__NR_vm86, func, v86);
1600	}
1601
1602	extern char vm86_code_start;
1603	extern char vm86_code_end;
1604
1605	#define VM86_CODE_CS 0x100
1606	#define VM86_CODE_IP 0x100
1607
1608	void test_vm86(void)
1609	{
1610	struct vm86plus_struct ctx;
1611	struct vm86_regs *r;
1612	uint8_t *vm86_mem;
1613	int seg, ret;
1614
1615	vm86_mem = mmap((void *)0x00000000, 0x110000,
1616	PROT_WRITE \| PROT_READ \| PROT_EXEC,
1617	MAP_FIXED \| MAP_ANON \| MAP_PRIVATE, -1, 0);
1618	if (vm86_mem == MAP_FAILED) {
1619	printf("ERROR: could not map vm86 memory");
1620	return;
1621	}
1622	memset(&ctx, 0, sizeof(ctx));
1623
1624	/* init basic registers */
1625	r = &ctx.regs;
1626	r->eip = VM86_CODE_IP;
1627	r->esp = 0xfffe;
1628	seg = VM86_CODE_CS;
1629	r->cs = seg;
1630	r->ss = seg;
1631	r->ds = seg;
1632	r->es = seg;
1633	r->fs = seg;
1634	r->gs = seg;
1635	r->eflags = VIF_MASK;
1636
1637	/* move code to proper address. We use the same layout as a .com
1638	dos program. */
1639	memcpy(vm86_mem + (VM86_CODE_CS << 4) + VM86_CODE_IP,
1640	&vm86_code_start, &vm86_code_end - &vm86_code_start);
1641
1642	/* mark int 0x21 as being emulated */
1643	set_bit((uint8_t *)&ctx.int_revectored, 0x21);
1644
1645	for(;;) {
1646	ret = vm86(VM86_ENTER, &ctx);
1647	switch(VM86_TYPE(ret)) {
1648	case VM86_INTx:
1649	{
1650	int int_num, ah, v;
1651
1652	int_num = VM86_ARG(ret);
1653	if (int_num != 0x21)
1654	goto unknown_int;
1655	ah = (r->eax >> 8) & 0xff;
1656	switch(ah) {
1657	case 0x00: /* exit */
1658	goto the_end;
1659	case 0x02: /* write char */
1660	{
1661	uint8_t c = r->edx;
1662	putchar(c);
1663	}
1664	break;
1665	case 0x09: /* write string */
1666	{
1667	uint8_t c, *ptr;
1668	ptr = seg_to_linear(r->ds, r->edx);
1669	for(;;) {
1670	c = *ptr++;
1671	if (c == '$')
1672	break;
1673	putchar(c);
1674	}
1675	r->eax = (r->eax & ~0xff) \| '$';
1676	}
1677	break;
1678	case 0xff: /* extension: write eflags number in edx */
1679	v = (int)r->edx;
1680	#ifndef LINUX_VM86_IOPL_FIX
1681	v &= ~0x3000;
1682	#endif
1683	printf("%08x\n", v);
1684	break;
1685	default:
1686	unknown_int:
1687	printf("unsupported int 0x%02x\n", int_num);
1688	goto the_end;
1689	}
1690	}
1691	break;
1692	case VM86_SIGNAL:
1693	/* a signal came, we just ignore that */
1694	break;
1695	case VM86_STI:
1696	break;
1697	default:
1698	printf("ERROR: unhandled vm86 return code (0x%x)\n", ret);
1699	goto the_end;
1700	}
1701	}
1702	the_end:
1703	printf("VM86 end\n");
1704	munmap(vm86_mem, 0x110000);
1705	}
1706	#endif
1707
1708	/* exception tests */
1709	#if defined(__i386__) && !defined(REG_EAX)
1710	#define REG_EAX EAX
1711	#define REG_EBX EBX
1712	#define REG_ECX ECX
1713	#define REG_EDX EDX
1714	#define REG_ESI ESI
1715	#define REG_EDI EDI
1716	#define REG_EBP EBP
1717	#define REG_ESP ESP
1718	#define REG_EIP EIP
1719	#define REG_EFL EFL
1720	#define REG_TRAPNO TRAPNO
1721	#define REG_ERR ERR
1722	#endif
1723
1724	#if defined(__x86_64__)
1725	#define REG_EIP REG_RIP
1726	#endif
1727
1728	jmp_buf jmp_env;
1729	int v1;
1730	int tab[2];
1731
1732	void sig_handler(int sig, siginfo_t info, void puc)
1733	{
1734	struct ucontext *uc = puc;
1735
1736	printf("si_signo=%d si_errno=%d si_code=%d",
1737	info->si_signo, info->si_errno, info->si_code);
1738	printf(" si_addr=0x%08lx",
1739	(unsigned long)info->si_addr);
1740	printf("\n");
1741
1742	printf("trapno=" FMTLX " err=" FMTLX,
1743	(long)uc->uc_mcontext.gregs[REG_TRAPNO],
1744	(long)uc->uc_mcontext.gregs[REG_ERR]);
1745	printf(" EIP=" FMTLX, (long)uc->uc_mcontext.gregs[REG_EIP]);
1746	printf("\n");
1747	longjmp(jmp_env, 1);
1748	}
1749
1750	void test_exceptions(void)
1751	{
1752	struct sigaction act;
1753	volatile int val;
1754
1755	act.sa_sigaction = sig_handler;
1756	sigemptyset(&act.sa_mask);
1757	act.sa_flags = SA_SIGINFO \| SA_NODEFER;
1758	sigaction(SIGFPE, &act, NULL);
1759	sigaction(SIGILL, &act, NULL);
1760	sigaction(SIGSEGV, &act, NULL);
1761	sigaction(SIGBUS, &act, NULL);
1762	sigaction(SIGTRAP, &act, NULL);
1763
1764	/* test division by zero reporting */
1765	printf("DIVZ exception:\n");
1766	if (setjmp(jmp_env) == 0) {
1767	/* now divide by zero */
1768	v1 = 0;
1769	v1 = 2 / v1;
1770	}
1771
1772	#if !defined(__x86_64__)
1773	printf("BOUND exception:\n");
1774	if (setjmp(jmp_env) == 0) {
1775	/* bound exception */
1776	tab[0] = 1;
1777	tab[1] = 10;
1778	asm volatile ("bound %0, %1" : : "r" (11), "m" (tab[0]));
1779	}
1780	#endif
1781
1782	#ifdef TEST_SEGS
1783	printf("segment exceptions:\n");
1784	if (setjmp(jmp_env) == 0) {
1785	/* load an invalid segment */
1786	asm volatile ("movl %0, %%fs" : : "r" ((0x1234 << 3) \| 1));
1787	}
1788	if (setjmp(jmp_env) == 0) {
1789	/* null data segment is valid */
1790	asm volatile ("movl %0, %%fs" : : "r" (3));
1791	/* null stack segment */
1792	asm volatile ("movl %0, %%ss" : : "r" (3));
1793	}
1794
1795	{
1796	struct modify_ldt_ldt_s ldt;
1797	ldt.entry_number = 1;
1798	ldt.base_addr = (unsigned long)&seg_data1;
1799	ldt.limit = (sizeof(seg_data1) + 0xfff) >> 12;
1800	ldt.seg_32bit = 1;
1801	ldt.contents = MODIFY_LDT_CONTENTS_DATA;
1802	ldt.read_exec_only = 0;
1803	ldt.limit_in_pages = 1;
1804	ldt.seg_not_present = 1;
1805	ldt.useable = 1;
1806	modify_ldt(1, &ldt, sizeof(ldt)); /* write ldt entry */
1807
1808	if (setjmp(jmp_env) == 0) {
1809	/* segment not present */
1810	asm volatile ("movl %0, %%fs" : : "r" (MK_SEL(1)));
1811	}
1812	}
1813	#endif
1814
1815	/* test SEGV reporting */
1816	printf("PF exception:\n");
1817	if (setjmp(jmp_env) == 0) {
1818	val = 1;
1819	/* we add a nop to test a weird PC retrieval case */
1820	asm volatile ("nop");
1821	/* now store in an invalid address */
1822	(char )0x1234 = 1;
1823	}
1824
1825	/* test SEGV reporting */
1826	printf("PF exception:\n");
1827	if (setjmp(jmp_env) == 0) {
1828	val = 1;
1829	/* read from an invalid address */
1830	v1 = (char )0x1234;
1831	}
1832
1833	/* test illegal instruction reporting */
1834	printf("UD2 exception:\n");
1835	if (setjmp(jmp_env) == 0) {
1836	/* now execute an invalid instruction */
1837	asm volatile("ud2");
1838	}
1839	printf("lock nop exception:\n");
1840	if (setjmp(jmp_env) == 0) {
1841	/* now execute an invalid instruction */
1842	asm volatile("lock nop");
1843	}
1844
1845	printf("INT exception:\n");
1846	if (setjmp(jmp_env) == 0) {
1847	asm volatile ("int $0xfd");
1848	}
1849	if (setjmp(jmp_env) == 0) {
1850	asm volatile ("int $0x01");
1851	}
1852	if (setjmp(jmp_env) == 0) {
1853	asm volatile (".byte 0xcd, 0x03");
1854	}
1855	if (setjmp(jmp_env) == 0) {
1856	asm volatile ("int $0x04");
1857	}
1858	if (setjmp(jmp_env) == 0) {
1859	asm volatile ("int $0x05");
1860	}
1861
1862	printf("INT3 exception:\n");
1863	if (setjmp(jmp_env) == 0) {
1864	asm volatile ("int3");
1865	}
1866
1867	printf("CLI exception:\n");
1868	if (setjmp(jmp_env) == 0) {
1869	asm volatile ("cli");
1870	}
1871
1872	printf("STI exception:\n");
1873	if (setjmp(jmp_env) == 0) {
1874	asm volatile ("cli");
1875	}
1876
1877	#if !defined(__x86_64__)
1878	printf("INTO exception:\n");
1879	if (setjmp(jmp_env) == 0) {
1880	/* overflow exception */
1881	asm volatile ("addl $1, %0 ; into" : : "r" (0x7fffffff));
1882	}
1883	#endif
1884
1885	printf("OUTB exception:\n");
1886	if (setjmp(jmp_env) == 0) {
1887	asm volatile ("outb %%al, %%dx" : : "d" (0x4321), "a" (0));
1888	}
1889
1890	printf("INB exception:\n");
1891	if (setjmp(jmp_env) == 0) {
1892	asm volatile ("inb %%dx, %%al" : "=a" (val) : "d" (0x4321));
1893	}
1894
1895	printf("REP OUTSB exception:\n");
1896	if (setjmp(jmp_env) == 0) {
1897	asm volatile ("rep outsb" : : "d" (0x4321), "S" (tab), "c" (1));
1898	}
1899
1900	printf("REP INSB exception:\n");
1901	if (setjmp(jmp_env) == 0) {
1902	asm volatile ("rep insb" : : "d" (0x4321), "D" (tab), "c" (1));
1903	}
1904
1905	printf("HLT exception:\n");
1906	if (setjmp(jmp_env) == 0) {
1907	asm volatile ("hlt");
1908	}
1909
1910	printf("single step exception:\n");
1911	val = 0;
1912	if (setjmp(jmp_env) == 0) {
1913	asm volatile ("pushf\n"
1914	"orl $0x00100, (%%esp)\n"
1915	"popf\n"
1916	"movl $0xabcd, %0\n"
1917	"movl $0x0, %0\n" : "=m" (val) : : "cc", "memory");
1918	}
1919	printf("val=0x%x\n", val);
1920	}
1921
1922	#if !defined(__x86_64__)
1923	/* specific precise single step test */
1924	void sig_trap_handler(int sig, siginfo_t info, void puc)
1925	{
1926	struct ucontext *uc = puc;
1927	printf("EIP=" FMTLX "\n", (long)uc->uc_mcontext.gregs[REG_EIP]);
1928	}
1929
1930	const uint8_t sstep_buf1[4] = { 1, 2, 3, 4};
1931	uint8_t sstep_buf2[4];
1932
1933	void test_single_step(void)
1934	{
1935	struct sigaction act;
1936	volatile int val;
1937	int i;
1938
1939	val = 0;
1940	act.sa_sigaction = sig_trap_handler;
1941	sigemptyset(&act.sa_mask);
1942	act.sa_flags = SA_SIGINFO;
1943	sigaction(SIGTRAP, &act, NULL);
1944	asm volatile ("pushf\n"
1945	"orl $0x00100, (%%esp)\n"
1946	"popf\n"
1947	"movl $0xabcd, %0\n"
1948
1949	/* jmp test */
1950	"movl $3, %%ecx\n"
1951	"1:\n"
1952	"addl $1, %0\n"
1953	"decl %%ecx\n"
1954	"jnz 1b\n"
1955
1956	/* movsb: the single step should stop at each movsb iteration */
1957	"movl $sstep_buf1, %%esi\n"
1958	"movl $sstep_buf2, %%edi\n"
1959	"movl $0, %%ecx\n"
1960	"rep movsb\n"
1961	"movl $3, %%ecx\n"
1962	"rep movsb\n"
1963	"movl $1, %%ecx\n"
1964	"rep movsb\n"
1965
1966	/* cmpsb: the single step should stop at each cmpsb iteration */
1967	"movl $sstep_buf1, %%esi\n"
1968	"movl $sstep_buf2, %%edi\n"
1969	"movl $0, %%ecx\n"
1970	"rep cmpsb\n"
1971	"movl $4, %%ecx\n"
1972	"rep cmpsb\n"
1973
1974	/* getpid() syscall: single step should skip one
1975	instruction */
1976	"movl $20, %%eax\n"
1977	"int $0x80\n"
1978	"movl $0, %%eax\n"
1979
1980	/* when modifying SS, trace is not done on the next
1981	instruction */
1982	"movl %%ss, %%ecx\n"
1983	"movl %%ecx, %%ss\n"
1984	"addl $1, %0\n"
1985	"movl $1, %%eax\n"
1986	"movl %%ecx, %%ss\n"
1987	"jmp 1f\n"
1988	"addl $1, %0\n"
1989	"1:\n"
1990	"movl $1, %%eax\n"
1991	"pushl %%ecx\n"
1992	"popl %%ss\n"
1993	"addl $1, %0\n"
1994	"movl $1, %%eax\n"
1995
1996	"pushf\n"
1997	"andl $~0x00100, (%%esp)\n"
1998	"popf\n"
1999	: "=m" (val)
2000	:
2001	: "cc", "memory", "eax", "ecx", "esi", "edi");
2002	printf("val=%d\n", val);
2003	for(i = 0; i < 4; i++)
2004	printf("sstep_buf2[%d] = %d\n", i, sstep_buf2[i]);
2005	}
2006
2007	/* self modifying code test */
2008	uint8_t code[] = {
2009	0xb8, 0x1, 0x00, 0x00, 0x00, /* movl $1, %eax */
2010	0xc3, /* ret */
2011	};
2012
2013	asm(".section \".data\"\n"
2014	"smc_code2:\n"
2015	"movl 4(%esp), %eax\n"
2016	"movl %eax, smc_patch_addr2 + 1\n"
2017	"nop\n"
2018	"nop\n"
2019	"nop\n"
2020	"nop\n"
2021	"nop\n"
2022	"nop\n"
2023	"nop\n"
2024	"nop\n"
2025	"smc_patch_addr2:\n"
2026	"movl $1, %eax\n"
2027	"ret\n"
2028	".previous\n"
2029	);
2030
2031	typedef int FuncType(void);
2032	extern int smc_code2(int);
2033	void test_self_modifying_code(void)
2034	{
2035	int i;
2036	printf("self modifying code:\n");
2037	printf("func1 = 0x%x\n", ((FuncType *)code)());
2038	for(i = 2; i <= 4; i++) {
2039	code[1] = i;
2040	printf("func%d = 0x%x\n", i, ((FuncType *)code)());
2041	}
2042
2043	/* more difficult test : the modified code is just after the
2044	modifying instruction. It is forbidden in Intel specs, but it
2045	is used by old DOS programs */
2046	for(i = 2; i <= 4; i++) {
2047	printf("smc_code2(%d) = %d\n", i, smc_code2(i));
2048	}
2049	}
2050	#endif
2051
2052	long enter_stack[4096];
2053
2054	#if defined(__x86_64__)
2055	#define RSP "%%rsp"
2056	#define RBP "%%rbp"
2057	#else
2058	#define RSP "%%esp"
2059	#define RBP "%%ebp"
2060	#endif
2061
2062	#define TEST_ENTER(size, stack_type, level)\
2063	{\
2064	long esp_save, esp_val, ebp_val, ebp_save, i;\
2065	stack_type ptr, stack_end, *stack_ptr;\
2066	memset(enter_stack, 0, sizeof(enter_stack));\
2067	stack_end = stack_ptr = (stack_type *)(enter_stack + 4096);\
2068	ebp_val = (long)stack_ptr;\
2069	for(i=1;i<=32;i++)\
2070	*--stack_ptr = i;\
2071	esp_val = (long)stack_ptr;\
2072	asm("mov " RSP ", %[esp_save]\n"\
2073	"mov " RBP ", %[ebp_save]\n"\
2074	"mov %[esp_val], " RSP "\n"\
2075	"mov %[ebp_val], " RBP "\n"\
2076	"enter" size " $8, $" #level "\n"\
2077	"mov " RSP ", %[esp_val]\n"\
2078	"mov " RBP ", %[ebp_val]\n"\
2079	"mov %[esp_save], " RSP "\n"\
2080	"mov %[ebp_save], " RBP "\n"\
2081	: [esp_save] "=r" (esp_save),\
2082	[ebp_save] "=r" (ebp_save),\
2083	[esp_val] "=r" (esp_val),\
2084	[ebp_val] "=r" (ebp_val)\
2085	: "[esp_val]" (esp_val),\
2086	"[ebp_val]" (ebp_val));\
2087	printf("level=%d:\n", level);\
2088	printf("esp_val=" FMTLX "\n", esp_val - (long)stack_end);\
2089	printf("ebp_val=" FMTLX "\n", ebp_val - (long)stack_end);\
2090	for(ptr = (stack_type *)esp_val; ptr < stack_end; ptr++)\
2091	printf(FMTLX "\n", (long)ptr[0]);\
2092	}
2093
2094	static void test_enter(void)
2095	{
2096	#if defined(__x86_64__)
2097	TEST_ENTER("q", uint64_t, 0);
2098	TEST_ENTER("q", uint64_t, 1);
2099	TEST_ENTER("q", uint64_t, 2);
2100	TEST_ENTER("q", uint64_t, 31);
2101	#else
2102	TEST_ENTER("l", uint32_t, 0);
2103	TEST_ENTER("l", uint32_t, 1);
2104	TEST_ENTER("l", uint32_t, 2);
2105	TEST_ENTER("l", uint32_t, 31);
2106	#endif
2107
2108	TEST_ENTER("w", uint16_t, 0);
2109	TEST_ENTER("w", uint16_t, 1);
2110	TEST_ENTER("w", uint16_t, 2);
2111	TEST_ENTER("w", uint16_t, 31);
2112	}
2113
2114	#ifdef TEST_SSE
2115
2116	typedef int __m64 __attribute__ ((__mode__ (__V2SI__)));
2117	typedef float __m128 __attribute__ ((__mode__(__V4SF__)));
2118
2119	typedef union {
2120	double d[2];
2121	float s[4];
2122	uint32_t l[4];
2123	uint64_t q[2];
2124	__m128 dq;
2125	} XMMReg;
2126
2127	static uint64_t __attribute__((aligned(16))) test_values[4][2] = {
2128	{ 0x456723c698694873, 0xdc515cff944a58ec },
2129	{ 0x1f297ccd58bad7ab, 0x41f21efba9e3e146 },
2130	{ 0x007c62c2085427f8, 0x231be9e8cde7438d },
2131	{ 0x0f76255a085427f8, 0xc233e9e8c4c9439a },
2132	};
2133
2134	#define SSE_OP(op)\
2135	{\
2136	asm volatile (#op " %2, %0" : "=x" (r.dq) : "0" (a.dq), "x" (b.dq));\
2137	printf("%-9s: a=" FMT64X "" FMT64X " b=" FMT64X "" FMT64X " r=" FMT64X "" FMT64X "\n",\
2138	#op,\
2139	a.q[1], a.q[0],\
2140	b.q[1], b.q[0],\
2141	r.q[1], r.q[0]);\
2142	}
2143
2144	#define SSE_OP2(op)\
2145	{\
2146	int i;\
2147	for(i=0;i<2;i++) {\
2148	a.q[0] = test_values[2*i][0];\
2149	a.q[1] = test_values[2*i][1];\
2150	b.q[0] = test_values[2*i+1][0];\
2151	b.q[1] = test_values[2*i+1][1];\
2152	SSE_OP(op);\
2153	}\
2154	}
2155
2156	#define MMX_OP2(op)\
2157	{\
2158	int i;\
2159	for(i=0;i<2;i++) {\
2160	a.q[0] = test_values[2*i][0];\
2161	b.q[0] = test_values[2*i+1][0];\
2162	asm volatile (#op " %2, %0" : "=y" (r.q[0]) : "0" (a.q[0]), "y" (b.q[0]));\
2163	printf("%-9s: a=" FMT64X " b=" FMT64X " r=" FMT64X "\n",\
2164	#op,\
2165	a.q[0],\
2166	b.q[0],\
2167	r.q[0]);\
2168	}\
2169	SSE_OP2(op);\
2170	}
2171
2172	#define SHUF_OP(op, ib)\
2173	{\
2174	a.q[0] = test_values[0][0];\
2175	a.q[1] = test_values[0][1];\
2176	b.q[0] = test_values[1][0];\
2177	b.q[1] = test_values[1][1];\
2178	asm volatile (#op " $" #ib ", %2, %0" : "=x" (r.dq) : "0" (a.dq), "x" (b.dq));\
2179	printf("%-9s: a=" FMT64X "" FMT64X " b=" FMT64X "" FMT64X " ib=%02x r=" FMT64X "" FMT64X "\n",\
2180	#op,\
2181	a.q[1], a.q[0],\
2182	b.q[1], b.q[0],\
2183	ib,\
2184	r.q[1], r.q[0]);\
2185	}
2186
2187	#define PSHUF_OP(op, ib)\
2188	{\
2189	int i;\
2190	for(i=0;i<2;i++) {\
2191	a.q[0] = test_values[2*i][0];\
2192	a.q[1] = test_values[2*i][1];\
2193	asm volatile (#op " $" #ib ", %1, %0" : "=x" (r.dq) : "x" (a.dq));\
2194	printf("%-9s: a=" FMT64X "" FMT64X " ib=%02x r=" FMT64X "" FMT64X "\n",\
2195	#op,\
2196	a.q[1], a.q[0],\
2197	ib,\
2198	r.q[1], r.q[0]);\
2199	}\
2200	}
2201
2202	#define SHIFT_IM(op, ib)\
2203	{\
2204	int i;\
2205	for(i=0;i<2;i++) {\
2206	a.q[0] = test_values[2*i][0];\
2207	a.q[1] = test_values[2*i][1];\
2208	asm volatile (#op " $" #ib ", %0" : "=x" (r.dq) : "0" (a.dq));\
2209	printf("%-9s: a=" FMT64X "" FMT64X " ib=%02x r=" FMT64X "" FMT64X "\n",\
2210	#op,\
2211	a.q[1], a.q[0],\
2212	ib,\
2213	r.q[1], r.q[0]);\
2214	}\
2215	}
2216
2217	#define SHIFT_OP(op, ib)\
2218	{\
2219	int i;\
2220	SHIFT_IM(op, ib);\
2221	for(i=0;i<2;i++) {\
2222	a.q[0] = test_values[2*i][0];\
2223	a.q[1] = test_values[2*i][1];\
2224	b.q[0] = ib;\
2225	b.q[1] = 0;\
2226	asm volatile (#op " %2, %0" : "=x" (r.dq) : "0" (a.dq), "x" (b.dq));\
2227	printf("%-9s: a=" FMT64X "" FMT64X " b=" FMT64X "" FMT64X " r=" FMT64X "" FMT64X "\n",\
2228	#op,\
2229	a.q[1], a.q[0],\
2230	b.q[1], b.q[0],\
2231	r.q[1], r.q[0]);\
2232	}\
2233	}
2234
2235	#define MOVMSK(op)\
2236	{\
2237	int i, reg;\
2238	for(i=0;i<2;i++) {\
2239	a.q[0] = test_values[2*i][0];\
2240	a.q[1] = test_values[2*i][1];\
2241	asm volatile (#op " %1, %0" : "=r" (reg) : "x" (a.dq));\
2242	printf("%-9s: a=" FMT64X "" FMT64X " r=%08x\n",\
2243	#op,\
2244	a.q[1], a.q[0],\
2245	reg);\
2246	}\
2247	}
2248
2249	#define SSE_OPS(a) \
2250	SSE_OP(a ## ps);\
2251	SSE_OP(a ## ss);
2252
2253	#define SSE_OPD(a) \
2254	SSE_OP(a ## pd);\
2255	SSE_OP(a ## sd);
2256
2257	#define SSE_COMI(op, field)\
2258	{\
2259	unsigned int eflags;\
2260	XMMReg a, b;\
2261	a.field[0] = a1;\
2262	b.field[0] = b1;\
2263	asm volatile (#op " %2, %1\n"\
2264	"pushf\n"\
2265	"pop %0\n"\
2266	: "=m" (eflags)\
2267	: "x" (a.dq), "x" (b.dq));\
2268	printf("%-9s: a=%f b=%f cc=%04x\n",\
2269	#op, a1, b1,\
2270	eflags & (CC_C \| CC_P \| CC_Z \| CC_S \| CC_O \| CC_A));\
2271	}
2272
2273	void test_sse_comi(double a1, double b1)
2274	{
2275	SSE_COMI(ucomiss, s);
2276	SSE_COMI(ucomisd, d);
2277	SSE_COMI(comiss, s);
2278	SSE_COMI(comisd, d);
2279	}
2280
2281	#define CVT_OP_XMM(op)\
2282	{\
2283	asm volatile (#op " %1, %0" : "=x" (r.dq) : "x" (a.dq));\
2284	printf("%-9s: a=" FMT64X "" FMT64X " r=" FMT64X "" FMT64X "\n",\
2285	#op,\
2286	a.q[1], a.q[0],\
2287	r.q[1], r.q[0]);\
2288	}
2289
2290	/* Force %xmm0 usage to avoid the case where both register index are 0
2291	to test intruction decoding more extensively */
2292	#define CVT_OP_XMM2MMX(op)\
2293	{\
2294	asm volatile (#op " %1, %0" : "=y" (r.q[0]) : "x" (a.dq) \
2295	: "%xmm0"); \
2296	asm volatile("emms\n"); \
2297	printf("%-9s: a=" FMT64X "" FMT64X " r=" FMT64X "\n",\
2298	#op,\
2299	a.q[1], a.q[0],\
2300	r.q[0]);\
2301	}
2302
2303	#define CVT_OP_MMX2XMM(op)\
2304	{\
2305	asm volatile (#op " %1, %0" : "=x" (r.dq) : "y" (a.q[0]));\
2306	asm volatile("emms\n"); \
2307	printf("%-9s: a=" FMT64X " r=" FMT64X "" FMT64X "\n",\
2308	#op,\
2309	a.q[0],\
2310	r.q[1], r.q[0]);\
2311	}
2312
2313	#define CVT_OP_REG2XMM(op)\
2314	{\
2315	asm volatile (#op " %1, %0" : "=x" (r.dq) : "r" (a.l[0]));\
2316	printf("%-9s: a=%08x r=" FMT64X "" FMT64X "\n",\
2317	#op,\
2318	a.l[0],\
2319	r.q[1], r.q[0]);\
2320	}
2321
2322	#define CVT_OP_XMM2REG(op)\
2323	{\
2324	asm volatile (#op " %1, %0" : "=r" (r.l[0]) : "x" (a.dq));\
2325	printf("%-9s: a=" FMT64X "" FMT64X " r=%08x\n",\
2326	#op,\
2327	a.q[1], a.q[0],\
2328	r.l[0]);\
2329	}
2330
2331	struct fpxstate {
2332	uint16_t fpuc;
2333	uint16_t fpus;
2334	uint16_t fptag;
2335	uint16_t fop;
2336	uint32_t fpuip;
2337	uint16_t cs_sel;
2338	uint16_t dummy0;
2339	uint32_t fpudp;
2340	uint16_t ds_sel;
2341	uint16_t dummy1;
2342	uint32_t mxcsr;
2343	uint32_t mxcsr_mask;
2344	uint8_t fpregs1[8 * 16];
2345	uint8_t xmm_regs[8 * 16];
2346	uint8_t dummy2[224];
2347	};
2348
2349	static struct fpxstate fpx_state __attribute__((aligned(16)));
2350	static struct fpxstate fpx_state2 __attribute__((aligned(16)));
2351
2352	void test_fxsave(void)
2353	{
2354	struct fpxstate *fp = &fpx_state;
2355	struct fpxstate *fp2 = &fpx_state2;
2356	int i, nb_xmm;
2357	XMMReg a, b;
2358	a.q[0] = test_values[0][0];
2359	a.q[1] = test_values[0][1];
2360	b.q[0] = test_values[1][0];
2361	b.q[1] = test_values[1][1];
2362
2363	asm("movdqa %2, %%xmm0\n"
2364	"movdqa %3, %%xmm7\n"
2365	#if defined(__x86_64__)
2366	"movdqa %2, %%xmm15\n"
2367	#endif
2368	" fld1\n"
2369	" fldpi\n"
2370	" fldln2\n"
2371	" fxsave %0\n"
2372	" fxrstor %0\n"
2373	" fxsave %1\n"
2374	" fninit\n"
2375	: "=m" ((uint32_t )fp2), "=m" ((uint32_t )fp)
2376	: "m" (a), "m" (b));
2377	printf("fpuc=%04x\n", fp->fpuc);
2378	printf("fpus=%04x\n", fp->fpus);
2379	printf("fptag=%04x\n", fp->fptag);
2380	for(i = 0; i < 3; i++) {
2381	printf("ST%d: " FMT64X " %04x\n",
2382	i,
2383	(uint64_t )&fp->fpregs1[i * 16],
2384	(uint16_t )&fp->fpregs1[i * 16 + 8]);
2385	}
2386	printf("mxcsr=%08x\n", fp->mxcsr & 0x1f80);
2387	#if defined(__x86_64__)
2388	nb_xmm = 16;
2389	#else
2390	nb_xmm = 8;
2391	#endif
2392	for(i = 0; i < nb_xmm; i++) {
2393	printf("xmm%d: " FMT64X "" FMT64X "\n",
2394	i,
2395	(uint64_t )&fp->xmm_regs[i * 16],
2396	(uint64_t )&fp->xmm_regs[i * 16 + 8]);
2397	}
2398	}
2399
2400	void test_sse(void)
2401	{
2402	XMMReg r, a, b;
2403	int i;
2404
2405	MMX_OP2(punpcklbw);
2406	MMX_OP2(punpcklwd);
2407	MMX_OP2(punpckldq);
2408	MMX_OP2(packsswb);
2409	MMX_OP2(pcmpgtb);
2410	MMX_OP2(pcmpgtw);
2411	MMX_OP2(pcmpgtd);
2412	MMX_OP2(packuswb);
2413	MMX_OP2(punpckhbw);
2414	MMX_OP2(punpckhwd);
2415	MMX_OP2(punpckhdq);
2416	MMX_OP2(packssdw);
2417	MMX_OP2(pcmpeqb);
2418	MMX_OP2(pcmpeqw);
2419	MMX_OP2(pcmpeqd);
2420
2421	MMX_OP2(paddq);
2422	MMX_OP2(pmullw);
2423	MMX_OP2(psubusb);
2424	MMX_OP2(psubusw);
2425	MMX_OP2(pminub);
2426	MMX_OP2(pand);
2427	MMX_OP2(paddusb);
2428	MMX_OP2(paddusw);
2429	MMX_OP2(pmaxub);
2430	MMX_OP2(pandn);
2431
2432	MMX_OP2(pmulhuw);
2433	MMX_OP2(pmulhw);
2434
2435	MMX_OP2(psubsb);
2436	MMX_OP2(psubsw);
2437	MMX_OP2(pminsw);
2438	MMX_OP2(por);
2439	MMX_OP2(paddsb);
2440	MMX_OP2(paddsw);
2441	MMX_OP2(pmaxsw);
2442	MMX_OP2(pxor);
2443	MMX_OP2(pmuludq);
2444	MMX_OP2(pmaddwd);
2445	MMX_OP2(psadbw);
2446	MMX_OP2(psubb);
2447	MMX_OP2(psubw);
2448	MMX_OP2(psubd);
2449	MMX_OP2(psubq);
2450	MMX_OP2(paddb);
2451	MMX_OP2(paddw);
2452	MMX_OP2(paddd);
2453
2454	MMX_OP2(pavgb);
2455	MMX_OP2(pavgw);
2456
2457	asm volatile ("pinsrw $1, %1, %0" : "=y" (r.q[0]) : "r" (0x12345678));
2458	printf("%-9s: r=" FMT64X "\n", "pinsrw", r.q[0]);
2459
2460	asm volatile ("pinsrw $5, %1, %0" : "=x" (r.dq) : "r" (0x12345678));
2461	printf("%-9s: r=" FMT64X "" FMT64X "\n", "pinsrw", r.q[1], r.q[0]);
2462
2463	a.q[0] = test_values[0][0];
2464	a.q[1] = test_values[0][1];
2465	asm volatile ("pextrw $1, %1, %0" : "=r" (r.l[0]) : "y" (a.q[0]));
2466	printf("%-9s: r=%08x\n", "pextrw", r.l[0]);
2467
2468	asm volatile ("pextrw $5, %1, %0" : "=r" (r.l[0]) : "x" (a.dq));
2469	printf("%-9s: r=%08x\n", "pextrw", r.l[0]);
2470
2471	asm volatile ("pmovmskb %1, %0" : "=r" (r.l[0]) : "y" (a.q[0]));
2472	printf("%-9s: r=%08x\n", "pmovmskb", r.l[0]);
2473
2474	asm volatile ("pmovmskb %1, %0" : "=r" (r.l[0]) : "x" (a.dq));
2475	printf("%-9s: r=%08x\n", "pmovmskb", r.l[0]);
2476
2477	{
2478	r.q[0] = -1;
2479	r.q[1] = -1;
2480
2481	a.q[0] = test_values[0][0];
2482	a.q[1] = test_values[0][1];
2483	b.q[0] = test_values[1][0];
2484	b.q[1] = test_values[1][1];
2485	asm volatile("maskmovq %1, %0" :
2486	: "y" (a.q[0]), "y" (b.q[0]), "D" (&r)
2487	: "memory");
2488	printf("%-9s: r=" FMT64X " a=" FMT64X " b=" FMT64X "\n",
2489	"maskmov",
2490	r.q[0],
2491	a.q[0],
2492	b.q[0]);
2493	asm volatile("maskmovdqu %1, %0" :
2494	: "x" (a.dq), "x" (b.dq), "D" (&r)
2495	: "memory");
2496	printf("%-9s: r=" FMT64X "" FMT64X " a=" FMT64X "" FMT64X " b=" FMT64X "" FMT64X "\n",
2497	"maskmov",
2498	r.q[1], r.q[0],
2499	a.q[1], a.q[0],
2500	b.q[1], b.q[0]);
2501	}
2502
2503	asm volatile ("emms");
2504
2505	SSE_OP2(punpcklqdq);
2506	SSE_OP2(punpckhqdq);
2507	SSE_OP2(andps);
2508	SSE_OP2(andpd);
2509	SSE_OP2(andnps);
2510	SSE_OP2(andnpd);
2511	SSE_OP2(orps);
2512	SSE_OP2(orpd);
2513	SSE_OP2(xorps);
2514	SSE_OP2(xorpd);
2515
2516	SSE_OP2(unpcklps);
2517	SSE_OP2(unpcklpd);
2518	SSE_OP2(unpckhps);
2519	SSE_OP2(unpckhpd);
2520
2521	SHUF_OP(shufps, 0x78);
2522	SHUF_OP(shufpd, 0x02);
2523
2524	PSHUF_OP(pshufd, 0x78);
2525	PSHUF_OP(pshuflw, 0x78);
2526	PSHUF_OP(pshufhw, 0x78);
2527
2528	SHIFT_OP(psrlw, 7);
2529	SHIFT_OP(psrlw, 16);
2530	SHIFT_OP(psraw, 7);
2531	SHIFT_OP(psraw, 16);
2532	SHIFT_OP(psllw, 7);
2533	SHIFT_OP(psllw, 16);
2534
2535	SHIFT_OP(psrld, 7);
2536	SHIFT_OP(psrld, 32);
2537	SHIFT_OP(psrad, 7);
2538	SHIFT_OP(psrad, 32);
2539	SHIFT_OP(pslld, 7);
2540	SHIFT_OP(pslld, 32);
2541
2542	SHIFT_OP(psrlq, 7);
2543	SHIFT_OP(psrlq, 32);
2544	SHIFT_OP(psllq, 7);
2545	SHIFT_OP(psllq, 32);
2546
2547	SHIFT_IM(psrldq, 16);
2548	SHIFT_IM(psrldq, 7);
2549	SHIFT_IM(pslldq, 16);
2550	SHIFT_IM(pslldq, 7);
2551
2552	MOVMSK(movmskps);
2553	MOVMSK(movmskpd);
2554
2555	/* FPU specific ops */
2556
2557	{
2558	uint32_t mxcsr;
2559	asm volatile("stmxcsr %0" : "=m" (mxcsr));
2560	printf("mxcsr=%08x\n", mxcsr & 0x1f80);
2561	asm volatile("ldmxcsr %0" : : "m" (mxcsr));
2562	}
2563
2564	test_sse_comi(2, -1);
2565	test_sse_comi(2, 2);
2566	test_sse_comi(2, 3);
2567	test_sse_comi(2, q_nan.d);
2568	test_sse_comi(q_nan.d, -1);
2569
2570	for(i = 0; i < 2; i++) {
2571	a.s[0] = 2.7;
2572	a.s[1] = 3.4;
2573	a.s[2] = 4;
2574	a.s[3] = -6.3;
2575	b.s[0] = 45.7;
2576	b.s[1] = 353.4;
2577	b.s[2] = 4;
2578	b.s[3] = 56.3;
2579	if (i == 1) {
2580	a.s[0] = q_nan.d;
2581	b.s[3] = q_nan.d;
2582	}
2583
2584	SSE_OPS(add);
2585	SSE_OPS(mul);
2586	SSE_OPS(sub);
2587	SSE_OPS(min);
2588	SSE_OPS(div);
2589	SSE_OPS(max);
2590	SSE_OPS(sqrt);
2591	SSE_OPS(cmpeq);
2592	SSE_OPS(cmplt);
2593	SSE_OPS(cmple);
2594	SSE_OPS(cmpunord);
2595	SSE_OPS(cmpneq);
2596	SSE_OPS(cmpnlt);
2597	SSE_OPS(cmpnle);
2598	SSE_OPS(cmpord);
2599
2600
2601	a.d[0] = 2.7;
2602	a.d[1] = -3.4;
2603	b.d[0] = 45.7;
2604	b.d[1] = -53.4;
2605	if (i == 1) {
2606	a.d[0] = q_nan.d;
2607	b.d[1] = q_nan.d;
2608	}
2609	SSE_OPD(add);
2610	SSE_OPD(mul);
2611	SSE_OPD(sub);
2612	SSE_OPD(min);
2613	SSE_OPD(div);
2614	SSE_OPD(max);
2615	SSE_OPD(sqrt);
2616	SSE_OPD(cmpeq);
2617	SSE_OPD(cmplt);
2618	SSE_OPD(cmple);
2619	SSE_OPD(cmpunord);
2620	SSE_OPD(cmpneq);
2621	SSE_OPD(cmpnlt);
2622	SSE_OPD(cmpnle);
2623	SSE_OPD(cmpord);
2624	}
2625
2626	/* float to float/int */
2627	a.s[0] = 2.7;
2628	a.s[1] = 3.4;
2629	a.s[2] = 4;
2630	a.s[3] = -6.3;
2631	CVT_OP_XMM(cvtps2pd);
2632	CVT_OP_XMM(cvtss2sd);
2633	CVT_OP_XMM2MMX(cvtps2pi);
2634	CVT_OP_XMM2MMX(cvttps2pi);
2635	CVT_OP_XMM2REG(cvtss2si);
2636	CVT_OP_XMM2REG(cvttss2si);
2637	CVT_OP_XMM(cvtps2dq);
2638	CVT_OP_XMM(cvttps2dq);
2639
2640	a.d[0] = 2.6;
2641	a.d[1] = -3.4;
2642	CVT_OP_XMM(cvtpd2ps);
2643	CVT_OP_XMM(cvtsd2ss);
2644	CVT_OP_XMM2MMX(cvtpd2pi);
2645	CVT_OP_XMM2MMX(cvttpd2pi);
2646	CVT_OP_XMM2REG(cvtsd2si);
2647	CVT_OP_XMM2REG(cvttsd2si);
2648	CVT_OP_XMM(cvtpd2dq);
2649	CVT_OP_XMM(cvttpd2dq);
2650
2651	/* sse/mmx moves */
2652	CVT_OP_XMM2MMX(movdq2q);
2653	CVT_OP_MMX2XMM(movq2dq);
2654
2655	/* int to float */
2656	a.l[0] = -6;
2657	a.l[1] = 2;
2658	a.l[2] = 100;
2659	a.l[3] = -60000;
2660	CVT_OP_MMX2XMM(cvtpi2ps);
2661	CVT_OP_MMX2XMM(cvtpi2pd);
2662	CVT_OP_REG2XMM(cvtsi2ss);
2663	CVT_OP_REG2XMM(cvtsi2sd);
2664	CVT_OP_XMM(cvtdq2ps);
2665	CVT_OP_XMM(cvtdq2pd);
2666
2667	/* XXX: test PNI insns */
2668	#if 0
2669	SSE_OP2(movshdup);
2670	#endif
2671	asm volatile ("emms");
2672	}
2673
2674	#endif
2675
2676	#define TEST_CONV_RAX(op)\
2677	{\
2678	unsigned long a, r;\
2679	a = i2l(0x8234a6f8);\
2680	r = a;\
2681	asm volatile(#op : "=a" (r) : "0" (r));\
2682	printf("%-10s A=" FMTLX " R=" FMTLX "\n", #op, a, r);\
2683	}
2684
2685	#define TEST_CONV_RAX_RDX(op)\
2686	{\
2687	unsigned long a, d, r, rh; \
2688	a = i2l(0x8234a6f8);\
2689	d = i2l(0x8345a1f2);\
2690	r = a;\
2691	rh = d;\
2692	asm volatile(#op : "=a" (r), "=d" (rh) : "0" (r), "1" (rh)); \
2693	printf("%-10s A=" FMTLX " R=" FMTLX ":" FMTLX "\n", #op, a, r, rh); \
2694	}
2695
2696	void test_conv(void)
2697	{
2698	TEST_CONV_RAX(cbw);
2699	TEST_CONV_RAX(cwde);
2700	#if defined(__x86_64__)
2701	TEST_CONV_RAX(cdqe);
2702	#endif
2703
2704	TEST_CONV_RAX_RDX(cwd);
2705	TEST_CONV_RAX_RDX(cdq);
2706	#if defined(__x86_64__)
2707	TEST_CONV_RAX_RDX(cqo);
2708	#endif
2709
2710	{
2711	unsigned long a, r;
2712	a = i2l(0x12345678);
2713	asm volatile("bswapl %k0" : "=r" (r) : "0" (a));
2714	printf("%-10s: A=" FMTLX " R=" FMTLX "\n", "bswapl", a, r);
2715	}
2716	#if defined(__x86_64__)
2717	{
2718	unsigned long a, r;
2719	a = i2l(0x12345678);
2720	asm volatile("bswapq %0" : "=r" (r) : "0" (a));
2721	printf("%-10s: A=" FMTLX " R=" FMTLX "\n", "bswapq", a, r);
2722	}
2723	#endif
2724	}
2725
2726	extern void *__start_initcall;
2727	extern void *__stop_initcall;
2728
2729
2730	int main(int argc, char **argv)
2731	{
2732	void **ptr;
2733	void (*func)(void);
2734
2735	ptr = &__start_initcall;
2736	while (ptr != &__stop_initcall) {
2737	func = *ptr++;
2738	func();
2739	}
2740	test_bsx();
2741	test_mul();
2742	test_jcc();
2743	test_loop();
2744	test_floats();
2745	#if !defined(__x86_64__)
2746	test_bcd();
2747	#endif
2748	test_xchg();
2749	test_string();
2750	test_misc();
2751	test_lea();
2752	#ifdef TEST_SEGS
2753	test_segs();
2754	test_code16();
2755	#endif
2756	#ifdef TEST_VM86
2757	test_vm86();
2758	#endif
2759	#if !defined(__x86_64__)
2760	test_exceptions();
2761	test_self_modifying_code();
2762	test_single_step();
2763	#endif
2764	test_enter();
2765	test_conv();
2766	#ifdef TEST_SSE
2767	test_sse();
2768	test_fxsave();
2769	#endif
2770	return 0;
2771	}

注意: 瀏覽 TracBrowser 來幫助您使用儲存庫瀏覽器

source: vbox/trunk/src/recompiler/tests/test-i386.c@ 36170

以其他格式下載: