| 1 | /* $Id: bs3-cpu-instr-x-regs.c32 106620 2024-10-23 12:10:42Z vboxsync $ */
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| 2 | /** @file
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| 3 | * BS3Kit - bs3-cpu-instr-x - register reference constants & functions.
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| 4 | */
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| 5 |
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| 6 | /*
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| 7 | * Copyright (C) 2024 Oracle and/or its affiliates.
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| 8 | *
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| 9 | * This file is part of VirtualBox base platform packages, as
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| 10 | * available from https://www.alldomusa.eu.org.
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| 11 | *
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| 12 | * This program is free software; you can redistribute it and/or
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| 13 | * modify it under the terms of the GNU General Public License
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| 14 | * as published by the Free Software Foundation, in version 3 of the
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| 15 | * License.
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| 16 | *
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| 17 | * This program is distributed in the hope that it will be useful, but
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| 18 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 20 | * General Public License for more details.
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| 21 | *
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| 22 | * You should have received a copy of the GNU General Public License
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| 23 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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| 24 | *
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| 25 | * The contents of this file may alternatively be used under the terms
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| 26 | * of the Common Development and Distribution License Version 1.0
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| 27 | * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
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| 28 | * in the VirtualBox distribution, in which case the provisions of the
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| 29 | * CDDL are applicable instead of those of the GPL.
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| 30 | *
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| 31 | * You may elect to license modified versions of this file under the
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| 32 | * terms and conditions of either the GPL or the CDDL or both.
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| 33 | *
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| 34 | * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
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| 35 | */
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| 36 |
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| 37 | /** Simple unadorned x86 family register names to be used in instruction test value tables. */
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| 38 |
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| 39 | /**
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| 40 | * Includes preliminary / placeholder support (in terms of knowing their
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| 41 | * names and having space set aside) for AVX-512 registers ([XY]MM16..31,
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| 42 | * ZMM, and k0..7), which VirtualBox does not yet support; and Intel APX
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| 43 | * (R16..31) extended x86 general purpose registers -- which VirtualBox
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| 44 | * does not yet support and Intel are not yet shipping.
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| 45 | */
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| 46 |
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| 47 | /** x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE xF
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| 48 | * /====== ===== ===== ===== ===== ===== ===== ===== ===== ===== ===== ===== ===== ===== ===== ======\
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| 49 | * 8-bit-L | 0y | AL CL DL BL SPL BPL SIL DIL R8B R9B R10B R11B R12B R13B R14B R15B |
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| 50 | * 8-bit-L-APX | 1y | R16B R17B R18B R19B R20B R21B R22B R23B R24B R25B R26B R27B R28B R29B R30B R31B |
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| 51 | * 16-bit | 2y | AX CX DX BX SP BP SI DI R8W R9W R10W R11W R12W R13W R14W R15W |
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| 52 | * 16-bit-APX | 3y | R16W R17W R18W R19W R20W R21W R22W R23W R24W R25W R26W R27W R28W R29W R30W R31W |
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| 53 | * 32-bit | 4y | EAX ECX EDX EBX ESP EBP ESI EDI R8D R9D R10D R11D R12D R13D R14D R15D |
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| 54 | * 32-bit-APX | 5y | R16D R17D R18D R19D R20D R21D R22D R23D R24D R25D R26D R27D R28D R29D R30D R31D |
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| 55 | * 64-bit | 6y | RAX RCX RDX RBX RSP RBP RSI RDI R8 R9 R10 R11 R12 R13 R14 R15 |
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| 56 | * 64-bit-APX | 7y | R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 |
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| 57 | * XMM | 8y | XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 XMM9 XMM10 XMM11 XMM12 XMM13 XMM14 XMM15 |
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| 58 | * XMM-AVX512 | 9y | XMM16 XMM17 XMM18 XMM19 XMM20 XMM21 XMM22 XMM23 XMM24 XMM25 XMM26 XMM27 XMM28 XMM29 XMM30 XMM31 |
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| 59 | * YMM | Ay | YMM0 YMM1 YMM2 YMM3 YMM4 YMM5 YMM6 YMM7 YMM8 YMM9 YMM10 YMM11 YMM12 YMM13 YMM14 YMM15 |
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| 60 | * YMM-AVX512 | By | YMM16 YMM17 YMM18 YMM19 YMM20 YMM21 YMM22 YMM23 YMM24 YMM25 YMM26 YMM27 YMM28 YMM29 YMM30 YMM31 |
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| 61 | * ZMM | Cy | ZMM0 ZMM1 ZMM2 ZMM3 ZMM4 ZMM5 ZMM6 ZMM7 ZMM8 ZMM9 ZMM10 ZMM11 ZMM12 ZMM13 ZMM14 ZMM15 |
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| 62 | * ZMM-AVX512 | Dy | ZMM16 ZMM17 ZMM18 ZMM19 ZMM20 ZMM21 ZMM22 ZMM23 ZMM24 ZMM25 ZMM26 ZMM27 ZMM28 ZMM29 ZMM30 ZMM31 |
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| 63 | * MMX / STn | Ey/| MM0 MM1 MM2 MM3 MM4 MM5 MM6 MM7 --- --- --- --- --- --- --- --- |
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| 64 | * OpMask-kx | Ey\| --- --- --- --- --- --- --- --- k0 k1 k2 k3 k4 k5 k6 k7 |
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| 65 | * SEGREG | Fy/| CS DS ES FS GS SS --- --- --- --- --- --- --- --- --- --- |
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| 66 | * 8-bit-H | Fy|| --- --- --- --- --- --- --- --- AH CH DH BH --- --- --- --- |
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| 67 | * Other/MEMREF | Fy\| --- --- --- --- --- --- xIP xFL --- --- --- --- NOREG (avail) FSxDI FSxBX |
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| 68 | * \====== ===== ===== ===== ===== ===== ===== ===== ===== ===== ===== ===== ===== ===== ===== =====*/
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| 69 |
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| 70 | /** These values are used in uint8_t fields; the TODO values are *intended* to break compilation. */
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| 71 |
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| 72 | #define BS3_REGISTER_FAMILY_AVX512_TODO 0x1000
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| 73 | #define BS3_REGISTER_FAMILY_APX_TODO 0x2000
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| 74 | #define BS3_REGISTER_FAMILY_OTHER_TODO 0x3000
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| 75 |
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| 76 | #define BS3_REGISTER_FAMILY_MASK 0xE0
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| 77 | #define BS3_REGISTER_REGISTER_MASK 0x1F
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| 78 |
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| 79 | #define BS3_REGISTER_FAMILY_8BIT_L 0x00
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| 80 | #define BS3_REGISTER_FAMILY_8BIT_L_LOW (0x00 | BS3_REGISTER_FAMILY_OTHER_TODO)
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| 81 | #define AL (BS3_REGISTER_FAMILY_8BIT_L_LOW | 0)
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| 82 | #define CL (BS3_REGISTER_FAMILY_8BIT_L_LOW | 1)
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| 83 | #define DL (BS3_REGISTER_FAMILY_8BIT_L_LOW | 2)
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| 84 | #define BL (BS3_REGISTER_FAMILY_8BIT_L_LOW | 3)
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| 85 | #define SPL (BS3_REGISTER_FAMILY_8BIT_L_LOW | 4)
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| 86 | #define BPL (BS3_REGISTER_FAMILY_8BIT_L_LOW | 5)
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| 87 | #define SIL (BS3_REGISTER_FAMILY_8BIT_L_LOW | 6)
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| 88 | #define DIL (BS3_REGISTER_FAMILY_8BIT_L_LOW | 7)
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| 89 | #define R8B (BS3_REGISTER_FAMILY_8BIT_L_LOW | 8)
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| 90 | #define R9B (BS3_REGISTER_FAMILY_8BIT_L_LOW | 9)
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| 91 | #define R10B (BS3_REGISTER_FAMILY_8BIT_L_LOW | 10)
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| 92 | #define R11B (BS3_REGISTER_FAMILY_8BIT_L_LOW | 11)
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| 93 | #define R12B (BS3_REGISTER_FAMILY_8BIT_L_LOW | 12)
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| 94 | #define R13B (BS3_REGISTER_FAMILY_8BIT_L_LOW | 13)
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| 95 | #define R14B (BS3_REGISTER_FAMILY_8BIT_L_LOW | 14)
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| 96 | #define R15B (BS3_REGISTER_FAMILY_8BIT_L_LOW | 15)
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| 97 | #define BS3_REGISTER_FAMILY_8BIT_L_APX (0x10 | BS3_REGISTER_FAMILY_APX_TODO)
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| 98 | #define R16B (BS3_REGISTER_FAMILY_8BIT_L_APX | 16)
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| 99 | #define R17B (BS3_REGISTER_FAMILY_8BIT_L_APX | 17)
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| 100 | #define R18B (BS3_REGISTER_FAMILY_8BIT_L_APX | 18)
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| 101 | #define R19B (BS3_REGISTER_FAMILY_8BIT_L_APX | 19)
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| 102 | #define R20B (BS3_REGISTER_FAMILY_8BIT_L_APX | 20)
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| 103 | #define R21B (BS3_REGISTER_FAMILY_8BIT_L_APX | 21)
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| 104 | #define R22B (BS3_REGISTER_FAMILY_8BIT_L_APX | 22)
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| 105 | #define R23B (BS3_REGISTER_FAMILY_8BIT_L_APX | 23)
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| 106 | #define R24B (BS3_REGISTER_FAMILY_8BIT_L_APX | 24)
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| 107 | #define R25B (BS3_REGISTER_FAMILY_8BIT_L_APX | 25)
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| 108 | #define R26B (BS3_REGISTER_FAMILY_8BIT_L_APX | 26)
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| 109 | #define R27B (BS3_REGISTER_FAMILY_8BIT_L_APX | 27)
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| 110 | #define R28B (BS3_REGISTER_FAMILY_8BIT_L_APX | 28)
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| 111 | #define R29B (BS3_REGISTER_FAMILY_8BIT_L_APX | 29)
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| 112 | #define R30B (BS3_REGISTER_FAMILY_8BIT_L_APX | 30)
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| 113 | #define R31B (BS3_REGISTER_FAMILY_8BIT_L_APX | 31)
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| 114 |
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| 115 | #define BS3_REGISTER_FAMILY_16BIT 0x20
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| 116 | #define AX (BS3_REGISTER_FAMILY_16BIT | 0)
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| 117 | #define CX (BS3_REGISTER_FAMILY_16BIT | 1)
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| 118 | #define DX (BS3_REGISTER_FAMILY_16BIT | 2)
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| 119 | #define BX (BS3_REGISTER_FAMILY_16BIT | 3)
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| 120 | #define SP (BS3_REGISTER_FAMILY_16BIT | 4)
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| 121 | #define BP (BS3_REGISTER_FAMILY_16BIT | 5)
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| 122 | #define SI (BS3_REGISTER_FAMILY_16BIT | 6)
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| 123 | #define DI (BS3_REGISTER_FAMILY_16BIT | 7)
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| 124 | #define R8W (BS3_REGISTER_FAMILY_16BIT | 8)
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| 125 | #define R9W (BS3_REGISTER_FAMILY_16BIT | 9)
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| 126 | #define R10W (BS3_REGISTER_FAMILY_16BIT | 10)
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| 127 | #define R11W (BS3_REGISTER_FAMILY_16BIT | 11)
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| 128 | #define R12W (BS3_REGISTER_FAMILY_16BIT | 12)
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| 129 | #define R13W (BS3_REGISTER_FAMILY_16BIT | 13)
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| 130 | #define R14W (BS3_REGISTER_FAMILY_16BIT | 14)
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| 131 | #define R15W (BS3_REGISTER_FAMILY_16BIT | 15)
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| 132 | #define BS3_REGISTER_FAMILY_16BIT_APX (0x30 | BS3_REGISTER_FAMILY_APX_TODO)
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| 133 | #define R16W (BS3_REGISTER_FAMILY_16BIT_APX | 16)
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| 134 | #define R17W (BS3_REGISTER_FAMILY_16BIT_APX | 17)
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| 135 | #define R18W (BS3_REGISTER_FAMILY_16BIT_APX | 18)
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| 136 | #define R19W (BS3_REGISTER_FAMILY_16BIT_APX | 19)
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| 137 | #define R20W (BS3_REGISTER_FAMILY_16BIT_APX | 20)
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| 138 | #define R21W (BS3_REGISTER_FAMILY_16BIT_APX | 21)
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| 139 | #define R22W (BS3_REGISTER_FAMILY_16BIT_APX | 22)
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| 140 | #define R23W (BS3_REGISTER_FAMILY_16BIT_APX | 23)
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| 141 | #define R24W (BS3_REGISTER_FAMILY_16BIT_APX | 24)
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| 142 | #define R25W (BS3_REGISTER_FAMILY_16BIT_APX | 25)
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| 143 | #define R26W (BS3_REGISTER_FAMILY_16BIT_APX | 26)
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| 144 | #define R27W (BS3_REGISTER_FAMILY_16BIT_APX | 27)
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| 145 | #define R28W (BS3_REGISTER_FAMILY_16BIT_APX | 28)
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| 146 | #define R29W (BS3_REGISTER_FAMILY_16BIT_APX | 29)
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| 147 | #define R30W (BS3_REGISTER_FAMILY_16BIT_APX | 30)
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| 148 | #define R31W (BS3_REGISTER_FAMILY_16BIT_APX | 31)
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| 149 |
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| 150 | #define BS3_REGISTER_FAMILY_32BIT 0x40
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| 151 | #define EAX (BS3_REGISTER_FAMILY_32BIT | 0)
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| 152 | #define ECX (BS3_REGISTER_FAMILY_32BIT | 1)
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| 153 | #define EDX (BS3_REGISTER_FAMILY_32BIT | 2)
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| 154 | #define EBX (BS3_REGISTER_FAMILY_32BIT | 3)
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| 155 | #define ESP (BS3_REGISTER_FAMILY_32BIT | 4)
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| 156 | #define EBP (BS3_REGISTER_FAMILY_32BIT | 5)
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| 157 | #define ESI (BS3_REGISTER_FAMILY_32BIT | 6)
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| 158 | #define EDI (BS3_REGISTER_FAMILY_32BIT | 7)
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| 159 | #define R8D (BS3_REGISTER_FAMILY_32BIT | 8)
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| 160 | #define R9D (BS3_REGISTER_FAMILY_32BIT | 9)
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| 161 | #define R10D (BS3_REGISTER_FAMILY_32BIT | 10)
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| 162 | #define R11D (BS3_REGISTER_FAMILY_32BIT | 11)
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| 163 | #define R12D (BS3_REGISTER_FAMILY_32BIT | 12)
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| 164 | #define R13D (BS3_REGISTER_FAMILY_32BIT | 13)
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| 165 | #define R14D (BS3_REGISTER_FAMILY_32BIT | 14)
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| 166 | #define R15D (BS3_REGISTER_FAMILY_32BIT | 15)
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| 167 | #define BS3_REGISTER_FAMILY_32BIT_APX (0x50 | BS3_REGISTER_FAMILY_APX_TODO)
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| 168 | #define R16D (BS3_REGISTER_FAMILY_32BIT_APX | 16)
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| 169 | #define R17D (BS3_REGISTER_FAMILY_32BIT_APX | 17)
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| 170 | #define R18D (BS3_REGISTER_FAMILY_32BIT_APX | 18)
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| 171 | #define R19D (BS3_REGISTER_FAMILY_32BIT_APX | 19)
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| 172 | #define R20D (BS3_REGISTER_FAMILY_32BIT_APX | 20)
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| 173 | #define R21D (BS3_REGISTER_FAMILY_32BIT_APX | 21)
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| 174 | #define R22D (BS3_REGISTER_FAMILY_32BIT_APX | 22)
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| 175 | #define R23D (BS3_REGISTER_FAMILY_32BIT_APX | 23)
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| 176 | #define R24D (BS3_REGISTER_FAMILY_32BIT_APX | 24)
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| 177 | #define R25D (BS3_REGISTER_FAMILY_32BIT_APX | 25)
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| 178 | #define R26D (BS3_REGISTER_FAMILY_32BIT_APX | 26)
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| 179 | #define R27D (BS3_REGISTER_FAMILY_32BIT_APX | 27)
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| 180 | #define R28D (BS3_REGISTER_FAMILY_32BIT_APX | 28)
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| 181 | #define R29D (BS3_REGISTER_FAMILY_32BIT_APX | 29)
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| 182 | #define R30D (BS3_REGISTER_FAMILY_32BIT_APX | 30)
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| 183 | #define R31D (BS3_REGISTER_FAMILY_32BIT_APX | 31)
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| 184 |
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| 185 | #define BS3_REGISTER_FAMILY_64BIT 0x60
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| 186 | #define RAX (BS3_REGISTER_FAMILY_64BIT | 0)
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| 187 | #define RCX (BS3_REGISTER_FAMILY_64BIT | 1)
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| 188 | #define RDX (BS3_REGISTER_FAMILY_64BIT | 2)
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| 189 | #define RBX (BS3_REGISTER_FAMILY_64BIT | 3)
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| 190 | #define RSP (BS3_REGISTER_FAMILY_64BIT | 4)
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| 191 | #define RBP (BS3_REGISTER_FAMILY_64BIT | 5)
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| 192 | #define RSI (BS3_REGISTER_FAMILY_64BIT | 6)
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| 193 | #define RDI (BS3_REGISTER_FAMILY_64BIT | 7)
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| 194 | #define R8 (BS3_REGISTER_FAMILY_64BIT | 8)
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| 195 | #define R9 (BS3_REGISTER_FAMILY_64BIT | 9)
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| 196 | #define R10 (BS3_REGISTER_FAMILY_64BIT | 10)
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| 197 | #define R11 (BS3_REGISTER_FAMILY_64BIT | 11)
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| 198 | #define R12 (BS3_REGISTER_FAMILY_64BIT | 12)
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| 199 | #define R13 (BS3_REGISTER_FAMILY_64BIT | 13)
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| 200 | #define R14 (BS3_REGISTER_FAMILY_64BIT | 14)
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| 201 | #define R15 (BS3_REGISTER_FAMILY_64BIT | 15)
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| 202 | #define BS3_REGISTER_FAMILY_64BIT_APX (0x70 | BS3_REGISTER_FAMILY_APX_TODO)
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| 203 | #define R16 (BS3_REGISTER_FAMILY_64BIT_APX | 16)
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| 204 | #define R17 (BS3_REGISTER_FAMILY_64BIT_APX | 17)
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| 205 | #define R18 (BS3_REGISTER_FAMILY_64BIT_APX | 18)
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| 206 | #define R19 (BS3_REGISTER_FAMILY_64BIT_APX | 19)
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| 207 | #define R20 (BS3_REGISTER_FAMILY_64BIT_APX | 20)
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| 208 | #define R21 (BS3_REGISTER_FAMILY_64BIT_APX | 21)
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| 209 | #define R22 (BS3_REGISTER_FAMILY_64BIT_APX | 22)
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| 210 | #define R23 (BS3_REGISTER_FAMILY_64BIT_APX | 23)
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| 211 | #define R24 (BS3_REGISTER_FAMILY_64BIT_APX | 24)
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| 212 | #define R25 (BS3_REGISTER_FAMILY_64BIT_APX | 25)
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| 213 | #define R26 (BS3_REGISTER_FAMILY_64BIT_APX | 26)
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| 214 | #define R27 (BS3_REGISTER_FAMILY_64BIT_APX | 27)
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| 215 | #define R28 (BS3_REGISTER_FAMILY_64BIT_APX | 28)
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| 216 | #define R29 (BS3_REGISTER_FAMILY_64BIT_APX | 29)
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| 217 | #define R30 (BS3_REGISTER_FAMILY_64BIT_APX | 30)
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| 218 | #define R31 (BS3_REGISTER_FAMILY_64BIT_APX | 31)
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| 219 |
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| 220 | #define BS3_REGISTER_FAMILY_XMM 0x80
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| 221 | #define XMM0 (BS3_REGISTER_FAMILY_XMM | 0)
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| 222 | #define XMM1 (BS3_REGISTER_FAMILY_XMM | 1)
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| 223 | #define XMM2 (BS3_REGISTER_FAMILY_XMM | 2)
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| 224 | #define XMM3 (BS3_REGISTER_FAMILY_XMM | 3)
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| 225 | #define XMM4 (BS3_REGISTER_FAMILY_XMM | 4)
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| 226 | #define XMM5 (BS3_REGISTER_FAMILY_XMM | 5)
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| 227 | #define XMM6 (BS3_REGISTER_FAMILY_XMM | 6)
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| 228 | #define XMM7 (BS3_REGISTER_FAMILY_XMM | 7)
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| 229 | #define XMM8 (BS3_REGISTER_FAMILY_XMM | 8)
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| 230 | #define XMM9 (BS3_REGISTER_FAMILY_XMM | 9)
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| 231 | #define XMM10 (BS3_REGISTER_FAMILY_XMM | 10)
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| 232 | #define XMM11 (BS3_REGISTER_FAMILY_XMM | 11)
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| 233 | #define XMM12 (BS3_REGISTER_FAMILY_XMM | 12)
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| 234 | #define XMM13 (BS3_REGISTER_FAMILY_XMM | 13)
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| 235 | #define XMM14 (BS3_REGISTER_FAMILY_XMM | 14)
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| 236 | #define XMM15 (BS3_REGISTER_FAMILY_XMM | 15)
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| 237 | #define BS3_REGISTER_FAMILY_XMM_512 (0x90 | BS3_REGISTER_FAMILY_AVX512_TODO)
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| 238 | #define XMM16 (BS3_REGISTER_FAMILY_XMM_512 | 16)
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| 239 | #define XMM17 (BS3_REGISTER_FAMILY_XMM_512 | 17)
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| 240 | #define XMM18 (BS3_REGISTER_FAMILY_XMM_512 | 18)
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| 241 | #define XMM19 (BS3_REGISTER_FAMILY_XMM_512 | 19)
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| 242 | #define XMM20 (BS3_REGISTER_FAMILY_XMM_512 | 20)
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| 243 | #define XMM21 (BS3_REGISTER_FAMILY_XMM_512 | 21)
|
|---|
| 244 | #define XMM22 (BS3_REGISTER_FAMILY_XMM_512 | 22)
|
|---|
| 245 | #define XMM23 (BS3_REGISTER_FAMILY_XMM_512 | 23)
|
|---|
| 246 | #define XMM24 (BS3_REGISTER_FAMILY_XMM_512 | 24)
|
|---|
| 247 | #define XMM25 (BS3_REGISTER_FAMILY_XMM_512 | 25)
|
|---|
| 248 | #define XMM26 (BS3_REGISTER_FAMILY_XMM_512 | 26)
|
|---|
| 249 | #define XMM27 (BS3_REGISTER_FAMILY_XMM_512 | 27)
|
|---|
| 250 | #define XMM28 (BS3_REGISTER_FAMILY_XMM_512 | 28)
|
|---|
| 251 | #define XMM29 (BS3_REGISTER_FAMILY_XMM_512 | 29)
|
|---|
| 252 | #define XMM30 (BS3_REGISTER_FAMILY_XMM_512 | 30)
|
|---|
| 253 | #define XMM31 (BS3_REGISTER_FAMILY_XMM_512 | 31)
|
|---|
| 254 |
|
|---|
| 255 | #define BS3_REGISTER_FAMILY_YMM 0xA0
|
|---|
| 256 | #define YMM0 (BS3_REGISTER_FAMILY_YMM | 0)
|
|---|
| 257 | #define YMM1 (BS3_REGISTER_FAMILY_YMM | 1)
|
|---|
| 258 | #define YMM2 (BS3_REGISTER_FAMILY_YMM | 2)
|
|---|
| 259 | #define YMM3 (BS3_REGISTER_FAMILY_YMM | 3)
|
|---|
| 260 | #define YMM4 (BS3_REGISTER_FAMILY_YMM | 4)
|
|---|
| 261 | #define YMM5 (BS3_REGISTER_FAMILY_YMM | 5)
|
|---|
| 262 | #define YMM6 (BS3_REGISTER_FAMILY_YMM | 6)
|
|---|
| 263 | #define YMM7 (BS3_REGISTER_FAMILY_YMM | 7)
|
|---|
| 264 | #define YMM8 (BS3_REGISTER_FAMILY_YMM | 8)
|
|---|
| 265 | #define YMM9 (BS3_REGISTER_FAMILY_YMM | 9)
|
|---|
| 266 | #define YMM10 (BS3_REGISTER_FAMILY_YMM | 10)
|
|---|
| 267 | #define YMM11 (BS3_REGISTER_FAMILY_YMM | 11)
|
|---|
| 268 | #define YMM12 (BS3_REGISTER_FAMILY_YMM | 12)
|
|---|
| 269 | #define YMM13 (BS3_REGISTER_FAMILY_YMM | 13)
|
|---|
| 270 | #define YMM14 (BS3_REGISTER_FAMILY_YMM | 14)
|
|---|
| 271 | #define YMM15 (BS3_REGISTER_FAMILY_YMM | 15)
|
|---|
| 272 | #define BS3_REGISTER_FAMILY_YMM_512 (0xB0 | BS3_REGISTER_FAMILY_AVX512_TODO)
|
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| 273 | #define YMM16 (BS3_REGISTER_FAMILY_YMM_512 | 16)
|
|---|
| 274 | #define YMM17 (BS3_REGISTER_FAMILY_YMM_512 | 17)
|
|---|
| 275 | #define YMM18 (BS3_REGISTER_FAMILY_YMM_512 | 18)
|
|---|
| 276 | #define YMM19 (BS3_REGISTER_FAMILY_YMM_512 | 19)
|
|---|
| 277 | #define YMM20 (BS3_REGISTER_FAMILY_YMM_512 | 20)
|
|---|
| 278 | #define YMM21 (BS3_REGISTER_FAMILY_YMM_512 | 21)
|
|---|
| 279 | #define YMM22 (BS3_REGISTER_FAMILY_YMM_512 | 22)
|
|---|
| 280 | #define YMM23 (BS3_REGISTER_FAMILY_YMM_512 | 23)
|
|---|
| 281 | #define YMM24 (BS3_REGISTER_FAMILY_YMM_512 | 24)
|
|---|
| 282 | #define YMM25 (BS3_REGISTER_FAMILY_YMM_512 | 25)
|
|---|
| 283 | #define YMM26 (BS3_REGISTER_FAMILY_YMM_512 | 26)
|
|---|
| 284 | #define YMM27 (BS3_REGISTER_FAMILY_YMM_512 | 27)
|
|---|
| 285 | #define YMM28 (BS3_REGISTER_FAMILY_YMM_512 | 28)
|
|---|
| 286 | #define YMM29 (BS3_REGISTER_FAMILY_YMM_512 | 29)
|
|---|
| 287 | #define YMM30 (BS3_REGISTER_FAMILY_YMM_512 | 30)
|
|---|
| 288 | #define YMM31 (BS3_REGISTER_FAMILY_YMM_512 | 31)
|
|---|
| 289 |
|
|---|
| 290 | #define BS3_REGISTER_FAMILY_ZMM 0xC0
|
|---|
| 291 | #define BS3_REGISTER_FAMILY_ZMM_LOW (0xC0 | BS3_REGISTER_FAMILY_AVX512_TODO)
|
|---|
| 292 | #define ZMM0 (BS3_REGISTER_FAMILY_ZMM_LOW | 0)
|
|---|
| 293 | #define ZMM1 (BS3_REGISTER_FAMILY_ZMM_LOW | 1)
|
|---|
| 294 | #define ZMM2 (BS3_REGISTER_FAMILY_ZMM_LOW | 2)
|
|---|
| 295 | #define ZMM3 (BS3_REGISTER_FAMILY_ZMM_LOW | 3)
|
|---|
| 296 | #define ZMM4 (BS3_REGISTER_FAMILY_ZMM_LOW | 4)
|
|---|
| 297 | #define ZMM5 (BS3_REGISTER_FAMILY_ZMM_LOW | 5)
|
|---|
| 298 | #define ZMM6 (BS3_REGISTER_FAMILY_ZMM_LOW | 6)
|
|---|
| 299 | #define ZMM7 (BS3_REGISTER_FAMILY_ZMM_LOW | 7)
|
|---|
| 300 | #define ZMM8 (BS3_REGISTER_FAMILY_ZMM_LOW | 8)
|
|---|
| 301 | #define ZMM9 (BS3_REGISTER_FAMILY_ZMM_LOW | 9)
|
|---|
| 302 | #define ZMM10 (BS3_REGISTER_FAMILY_ZMM_LOW | 10)
|
|---|
| 303 | #define ZMM11 (BS3_REGISTER_FAMILY_ZMM_LOW | 11)
|
|---|
| 304 | #define ZMM12 (BS3_REGISTER_FAMILY_ZMM_LOW | 12)
|
|---|
| 305 | #define ZMM13 (BS3_REGISTER_FAMILY_ZMM_LOW | 13)
|
|---|
| 306 | #define ZMM14 (BS3_REGISTER_FAMILY_ZMM_LOW | 14)
|
|---|
| 307 | #define ZMM15 (BS3_REGISTER_FAMILY_ZMM_LOW | 15)
|
|---|
| 308 | #define BS3_REGISTER_FAMILY_ZMM_512 (0xD0 | BS3_REGISTER_FAMILY_AVX512_TODO)
|
|---|
| 309 | #define ZMM16 (BS3_REGISTER_FAMILY_ZMM_512 | 16)
|
|---|
| 310 | #define ZMM17 (BS3_REGISTER_FAMILY_ZMM_512 | 17)
|
|---|
| 311 | #define ZMM18 (BS3_REGISTER_FAMILY_ZMM_512 | 18)
|
|---|
| 312 | #define ZMM19 (BS3_REGISTER_FAMILY_ZMM_512 | 19)
|
|---|
| 313 | #define ZMM20 (BS3_REGISTER_FAMILY_ZMM_512 | 20)
|
|---|
| 314 | #define ZMM21 (BS3_REGISTER_FAMILY_ZMM_512 | 21)
|
|---|
| 315 | #define ZMM22 (BS3_REGISTER_FAMILY_ZMM_512 | 22)
|
|---|
| 316 | #define ZMM23 (BS3_REGISTER_FAMILY_ZMM_512 | 23)
|
|---|
| 317 | #define ZMM24 (BS3_REGISTER_FAMILY_ZMM_512 | 24)
|
|---|
| 318 | #define ZMM25 (BS3_REGISTER_FAMILY_ZMM_512 | 25)
|
|---|
| 319 | #define ZMM26 (BS3_REGISTER_FAMILY_ZMM_512 | 26)
|
|---|
| 320 | #define ZMM27 (BS3_REGISTER_FAMILY_ZMM_512 | 27)
|
|---|
| 321 | #define ZMM28 (BS3_REGISTER_FAMILY_ZMM_512 | 28)
|
|---|
| 322 | #define ZMM29 (BS3_REGISTER_FAMILY_ZMM_512 | 29)
|
|---|
| 323 | #define ZMM30 (BS3_REGISTER_FAMILY_ZMM_512 | 30)
|
|---|
| 324 | #define ZMM31 (BS3_REGISTER_FAMILY_ZMM_512 | 31)
|
|---|
| 325 |
|
|---|
| 326 | #define BS3_REGISTER_FAMILY_OTHER 0xE0
|
|---|
| 327 | #define BS3_REGISTER_FAMILY_MMX 0xE0
|
|---|
| 328 | #define MM0 (BS3_REGISTER_FAMILY_MMX | 0)
|
|---|
| 329 | #define MM1 (BS3_REGISTER_FAMILY_MMX | 1)
|
|---|
| 330 | #define MM2 (BS3_REGISTER_FAMILY_MMX | 2)
|
|---|
| 331 | #define MM3 (BS3_REGISTER_FAMILY_MMX | 3)
|
|---|
| 332 | #define MM4 (BS3_REGISTER_FAMILY_MMX | 4)
|
|---|
| 333 | #define MM5 (BS3_REGISTER_FAMILY_MMX | 5)
|
|---|
| 334 | #define MM6 (BS3_REGISTER_FAMILY_MMX | 6)
|
|---|
| 335 | #define MM7 (BS3_REGISTER_FAMILY_MMX | 7)
|
|---|
| 336 |
|
|---|
| 337 | #define BS3_REGISTER_FAMILY_OPMASK (0xE8 | BS3_REGISTER_FAMILY_AVX512_TODO)
|
|---|
| 338 | #define k0 (BS3_REGISTER_FAMILY_OPMASK | 0)
|
|---|
| 339 | #define k1 (BS3_REGISTER_FAMILY_OPMASK | 1)
|
|---|
| 340 | #define k2 (BS3_REGISTER_FAMILY_OPMASK | 2)
|
|---|
| 341 | #define k3 (BS3_REGISTER_FAMILY_OPMASK | 3)
|
|---|
| 342 | #define k4 (BS3_REGISTER_FAMILY_OPMASK | 4)
|
|---|
| 343 | #define k5 (BS3_REGISTER_FAMILY_OPMASK | 5)
|
|---|
| 344 | #define k6 (BS3_REGISTER_FAMILY_OPMASK | 6)
|
|---|
| 345 | #define k7 (BS3_REGISTER_FAMILY_OPMASK | 7)
|
|---|
| 346 |
|
|---|
| 347 | #define BS3_REGISTER_FAMILY_SEGREG (0xF0 | BS3_REGISTER_FAMILY_OTHER_TODO)
|
|---|
| 348 | #define ES (BS3_REGISTER_FAMILY_SEGREG | 0)
|
|---|
| 349 | #define CS (BS3_REGISTER_FAMILY_SEGREG | 1)
|
|---|
| 350 | #define SS (BS3_REGISTER_FAMILY_SEGREG | 2)
|
|---|
| 351 | #define DS (BS3_REGISTER_FAMILY_SEGREG | 3)
|
|---|
| 352 | #define FS (BS3_REGISTER_FAMILY_SEGREG | 4)
|
|---|
| 353 | #define GS (BS3_REGISTER_FAMILY_SEGREG | 5)
|
|---|
| 354 |
|
|---|
| 355 | #define BS3_REGISTER_FAMILY_IP (0xF5 | BS3_REGISTER_FAMILY_OTHER_TODO)
|
|---|
| 356 | #define IP BS3_REGISTER_FAMILY_IP
|
|---|
| 357 | #define EIP BS3_REGISTER_FAMILY_IP
|
|---|
| 358 | #define RIP BS3_REGISTER_FAMILY_IP
|
|---|
| 359 | #define xIP BS3_REGISTER_FAMILY_IP
|
|---|
| 360 |
|
|---|
| 361 | #define BS3_REGISTER_FAMILY_FL (0xF6 | BS3_REGISTER_FAMILY_OTHER_TODO)
|
|---|
| 362 | #define FL BS3_REGISTER_FAMILY_FL
|
|---|
| 363 | #define EFL BS3_REGISTER_FAMILY_FL
|
|---|
| 364 | #define RFL BS3_REGISTER_FAMILY_FL
|
|---|
| 365 | #define xFL BS3_REGISTER_FAMILY_FL
|
|---|
| 366 |
|
|---|
| 367 | #define BS3_REGISTER_FAMILY_8BIT_H (0xE8 | BS3_REGISTER_FAMILY_OTHER_TODO)
|
|---|
| 368 | #define AH (BS3_REGISTER_FAMILY_8BIT_H | 0)
|
|---|
| 369 | #define CH (BS3_REGISTER_FAMILY_8BIT_H | 1)
|
|---|
| 370 | #define DH (BS3_REGISTER_FAMILY_8BIT_H | 2)
|
|---|
| 371 | #define BH (BS3_REGISTER_FAMILY_8BIT_H | 3)
|
|---|
| 372 |
|
|---|
| 373 | #define NOREG 0xFC
|
|---|
| 374 |
|
|---|
| 375 | #define BS3_REGISTER_FAMILY_MEMREF 0xFE
|
|---|
| 376 | #define FSxDI (BS3_REGISTER_FAMILY_MEMREF | 0)
|
|---|
| 377 | #define FSxBX (BS3_REGISTER_FAMILY_MEMREF | 1)
|
|---|
| 378 |
|
|---|
| 379 | #define BS3_REGISTER_FLAG_MEMREF 0x100
|
|---|
| 380 | #define BS3_FSxREG(reg) (((reg) == FSxBX || (reg) == FSxDI) ? reg : ((reg) & BS3_REGISTER_REGISTER_MASK) | BS3_REGISTER_FLAG_MEMREF)
|
|---|
| 381 |
|
|---|
| 382 | #define BS3_REGISTER_NAME_MAXSIZE sizeof("(avail)")
|
|---|
| 383 |
|
|---|
| 384 | /**
|
|---|
| 385 | * Get the name of a register from its identity value used in instruction test value tables.
|
|---|
| 386 | *
|
|---|
| 387 | * @returns Name of register.
|
|---|
| 388 | * @param pszBuf Where to store the name.
|
|---|
| 389 | * @param cchBuf The size of the buffer.
|
|---|
| 390 | * @param uReg The register identity value.
|
|---|
| 391 | */
|
|---|
| 392 | static size_t bs3CpuInstrXGetRegisterName(char BS3_FAR *pszBuf, size_t cchBuf, uint8_t uReg)
|
|---|
| 393 | {
|
|---|
| 394 | const uint8_t uRegNum = uReg & BS3_REGISTER_REGISTER_MASK;
|
|---|
| 395 | const uint8_t uRegSet = uReg & BS3_REGISTER_FAMILY_MASK;
|
|---|
| 396 | static const char * const s_apsz8bitLNames[] = { "AL", "CL", "DL", "BL", "SPL", "BPL", "SIL", "DIL" };
|
|---|
| 397 | static const char * const s_apsz16bitNames[] = { "AX", "CX", "DX", "BX", "SP", "BP", "SI", "DI" };
|
|---|
| 398 | static const char * const s_apszOtherNames[] = { "MM0", "MM1", "MM2", "MM3", "MM4", "MM5", "MM6", "MM7",
|
|---|
| 399 | "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7",
|
|---|
| 400 | "CS", "DS", "ES", "FS", "GS", "SS",
|
|---|
| 401 | "xIP", "xFL",
|
|---|
| 402 | "AH", "CH", "DH", "BH",
|
|---|
| 403 | "NOREG", "(avail)", "FSxDI", "FSxBX" };
|
|---|
| 404 | BS3_ASSERT(cchBuf >= BS3_REGISTER_NAME_MAXSIZE);
|
|---|
| 405 |
|
|---|
| 406 | switch (uRegSet) {
|
|---|
| 407 | case BS3_REGISTER_FAMILY_8BIT_L:
|
|---|
| 408 | if (uRegNum < RT_ELEMENTS(s_apsz8bitLNames))
|
|---|
| 409 | return Bs3StrPrintf(pszBuf, cchBuf, "%s", s_apsz8bitLNames[uRegNum]);
|
|---|
| 410 | else
|
|---|
| 411 | return Bs3StrPrintf(pszBuf, cchBuf, "R%dB", uRegNum);
|
|---|
| 412 | case BS3_REGISTER_FAMILY_16BIT:
|
|---|
| 413 | if (uRegNum < RT_ELEMENTS(s_apsz16bitNames))
|
|---|
| 414 | return Bs3StrPrintf(pszBuf, cchBuf, "%s", s_apsz16bitNames[uRegNum]);
|
|---|
| 415 | else
|
|---|
| 416 | return Bs3StrPrintf(pszBuf, cchBuf, "R%dW", uRegNum);
|
|---|
| 417 | case BS3_REGISTER_FAMILY_32BIT:
|
|---|
| 418 | if (uRegNum < RT_ELEMENTS(s_apsz16bitNames))
|
|---|
| 419 | return Bs3StrPrintf(pszBuf, cchBuf, "E%s", s_apsz16bitNames[uRegNum]);
|
|---|
| 420 | else
|
|---|
| 421 | return Bs3StrPrintf(pszBuf, cchBuf, "R%dD", uRegNum);
|
|---|
| 422 | case BS3_REGISTER_FAMILY_64BIT:
|
|---|
| 423 | if (uRegNum < RT_ELEMENTS(s_apsz16bitNames))
|
|---|
| 424 | return Bs3StrPrintf(pszBuf, cchBuf, "R%s", s_apsz16bitNames[uRegNum]);
|
|---|
| 425 | else
|
|---|
| 426 | return Bs3StrPrintf(pszBuf, cchBuf, "R%d", uRegNum);
|
|---|
| 427 | case BS3_REGISTER_FAMILY_XMM:
|
|---|
| 428 | return Bs3StrPrintf(pszBuf, cchBuf, "XMM%d", uRegNum);
|
|---|
| 429 | case BS3_REGISTER_FAMILY_YMM:
|
|---|
| 430 | return Bs3StrPrintf(pszBuf, cchBuf, "YMM%d", uRegNum);
|
|---|
| 431 | case BS3_REGISTER_FAMILY_ZMM:
|
|---|
| 432 | return Bs3StrPrintf(pszBuf, cchBuf, "ZMM%d", uRegNum);
|
|---|
| 433 | case BS3_REGISTER_FAMILY_OTHER:
|
|---|
| 434 | return Bs3StrPrintf(pszBuf, cchBuf, "%s", s_apszOtherNames[uRegNum]);
|
|---|
| 435 | }
|
|---|
| 436 | return Bs3StrPrintf(pszBuf, cchBuf, "(?%02X?)", uReg);
|
|---|
| 437 | }
|
|---|
| 438 |
|
|---|
| 439 | /**
|
|---|
| 440 | * Set a register within a testing context. Intended to support a broad
|
|---|
| 441 | * range of register types; this prototype so far only supports MMX, XMM,
|
|---|
| 442 | * YMM, and hypothetically-but-not-yet-linked, general purpose registers
|
|---|
| 443 | * other than their 8-bit sub-aliases.
|
|---|
| 444 | *
|
|---|
| 445 | * @returns Nothing much of any interest (so far).
|
|---|
| 446 | * @param pExtCtx The testing context to modify.
|
|---|
| 447 | * @param uReg The register identity value to modify within that context.
|
|---|
| 448 | * @param pValue Pointer to the data to store there.
|
|---|
| 449 | * @param pExtra For BS3_REGISTER_FAMILY_XMM: flag whether to zero YMM-hi.
|
|---|
| 450 | * For GPR references: pointer to general purpose register context.
|
|---|
| 451 | */
|
|---|
| 452 | #define CLR_YmmHi (void *)true
|
|---|
| 453 | #define SET_YmmHi (void *)false
|
|---|
| 454 |
|
|---|
| 455 | static bool Bs3ExtCtxSetReg(PBS3EXTCTX pExtCtx, uint16_t uReg, void * pValue, void * pExtra)
|
|---|
| 456 | {
|
|---|
| 457 | uint8_t uRegNum = uReg & BS3_REGISTER_REGISTER_MASK;
|
|---|
| 458 | uint8_t uRegSet = uReg & BS3_REGISTER_FAMILY_MASK;
|
|---|
| 459 | char pszRegName[BS3_REGISTER_NAME_MAXSIZE];
|
|---|
| 460 | PBS3REGCTX pCtx = (PBS3REGCTX)pExtra; /* for BS3_REGISTER_FAMILY_MEMREF, all GPR families */
|
|---|
| 461 | bool fZeroYMMHi = (bool)pExtra; /* for BS3_REGISTER_FAMILY_XMM */
|
|---|
| 462 |
|
|---|
| 463 | if (uReg & BS3_REGISTER_FLAG_MEMREF || uReg == FSxBX || uReg == FSxDI)
|
|---|
| 464 | {
|
|---|
| 465 | uRegSet = BS3_REGISTER_FAMILY_MEMREF;
|
|---|
| 466 | if (uReg == FSxBX) uRegNum = BX;
|
|---|
| 467 | if (uReg == FSxDI) uRegNum = DI;
|
|---|
| 468 | uRegNum &= BS3_REGISTER_REGISTER_MASK;
|
|---|
| 469 | }
|
|---|
| 470 |
|
|---|
| 471 | if (uRegNum < 16)
|
|---|
| 472 | {
|
|---|
| 473 | switch (uRegSet)
|
|---|
| 474 | {
|
|---|
| 475 | case BS3_REGISTER_FAMILY_16BIT:
|
|---|
| 476 | return Bs3RegCtxSetGpr(pCtx, uRegNum, *((uint16_t *)pValue), 2);
|
|---|
| 477 | case BS3_REGISTER_FAMILY_32BIT:
|
|---|
| 478 | return Bs3RegCtxSetGpr(pCtx, uRegNum, *((uint32_t *)pValue), 4);
|
|---|
| 479 | case BS3_REGISTER_FAMILY_64BIT:
|
|---|
| 480 | return Bs3RegCtxSetGpr(pCtx, uRegNum, *((uint64_t *)pValue), 8);
|
|---|
| 481 | case BS3_REGISTER_FAMILY_XMM:
|
|---|
| 482 | if (fZeroYMMHi)
|
|---|
| 483 | return Bs3ExtCtxSetXmm(pExtCtx, uRegNum, pValue);
|
|---|
| 484 | else
|
|---|
| 485 | return Bs3ExtCtxSetYmm(pExtCtx, uRegNum, pValue, 16);
|
|---|
| 486 | case BS3_REGISTER_FAMILY_YMM:
|
|---|
| 487 | return Bs3ExtCtxSetYmm(pExtCtx, uRegNum, pValue, 32);
|
|---|
| 488 | case BS3_REGISTER_FAMILY_MEMREF:
|
|---|
| 489 | Bs3RegCtxSetGrpSegFromCurPtr(pCtx, (&pCtx->rax) + uRegNum, &pCtx->fs, pValue);
|
|---|
| 490 | return true;
|
|---|
| 491 | case BS3_REGISTER_FAMILY_OTHER:
|
|---|
| 492 | if (uReg >= MM0 && uReg <= MM7)
|
|---|
| 493 | return Bs3ExtCtxSetMm(pExtCtx, uRegNum, (uint64_t)pValue, BS3EXTCTXTOPMM_SET);
|
|---|
| 494 | case BS3_REGISTER_FAMILY_8BIT_L:
|
|---|
| 495 | case BS3_REGISTER_FAMILY_ZMM:
|
|---|
| 496 | default:
|
|---|
| 497 | break;
|
|---|
| 498 |
|
|---|
| 499 | }
|
|---|
| 500 | }
|
|---|
| 501 | if (uReg == NOREG)
|
|---|
| 502 | return true;
|
|---|
| 503 | /* FSxDI, FSxBX presumed handled by the callers, though that may change */
|
|---|
| 504 |
|
|---|
| 505 | bs3CpuInstrXGetRegisterName(pszRegName, BS3_REGISTER_NAME_MAXSIZE, uReg);
|
|---|
| 506 | return Bs3TestFailedF("Bs3ExtCtxSetReg() todo: handle register '%s' (%02X)", pszRegName, uReg);
|
|---|
| 507 | }
|
|---|
