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source: vbox/trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-2-template.mac@ 95296

最後變更 在這個檔案從95296是 95296,由 vboxsync 提交於 3 年 前

ValKit/bs3-cpu-instr-2: Simple RORX test to establing whether V<>0 triggers #UD or not (it does). bugref:9898
  • 屬性 svn:eol-style 設為 native
  • 屬性 svn:keywords 設為 Author Date Id Revision
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1; $Id: bs3-cpu-instr-2-template.mac 95296 2022-06-15 22:06:20Z vboxsync $
2;; @file
3; BS3Kit - bs3-cpu-instr-2 assembly template.
4;
5
6;
7; Copyright (C) 2007-2022 Oracle Corporation
8;
9; This file is part of VirtualBox Open Source Edition (OSE), as
10; available from http://www.alldomusa.eu.org. This file is free software;
11; you can redistribute it and/or modify it under the terms of the GNU
12; General Public License (GPL) as published by the Free Software
13; Foundation, in version 2 as it comes in the "COPYING" file of the
14; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16;
17; The contents of this file may alternatively be used under the terms
18; of the Common Development and Distribution License Version 1.0
19; (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20; VirtualBox OSE distribution, in which case the provisions of the
21; CDDL are applicable instead of those of the GPL.
22;
23; You may elect to license modified versions of this file under the
24; terms and conditions of either the GPL or the CDDL or both.
25;
26
27
28;*********************************************************************************************************************************
29;* Header Files *
30;*********************************************************************************************************************************
31%include "bs3kit-template-header.mac" ; setup environment
32
33
34;*********************************************************************************************************************************
35;* External Symbols *
36;*********************************************************************************************************************************
37TMPL_BEGIN_TEXT
38
39
40;
41; Test code snippets containing code which differs between 16-bit, 32-bit
42; and 64-bit CPUs modes.
43;
44%ifdef BS3_INSTANTIATING_CMN
45
46BS3_PROC_BEGIN_CMN bs3CpuInstr2_mul_xBX_ud2, BS3_PBC_NEAR
47 mul xBX
48.again:
49 ud2
50 jmp .again
51BS3_PROC_END_CMN bs3CpuInstr2_mul_xBX_ud2
52
53
54BS3_PROC_BEGIN_CMN bs3CpuInstr2_imul_xBX_ud2, BS3_PBC_NEAR
55 imul xBX
56.again:
57 ud2
58 jmp .again
59BS3_PROC_END_CMN bs3CpuInstr2_imul_xBX_ud2
60
61
62BS3_PROC_BEGIN_CMN bs3CpuInstr2_imul_xCX_xBX_ud2, BS3_PBC_NEAR
63 imul xCX, xBX
64.again:
65 ud2
66 jmp .again
67BS3_PROC_END_CMN bs3CpuInstr2_imul_xCX_xBX_ud2
68
69
70BS3_PROC_BEGIN_CMN bs3CpuInstr2_div_xBX_ud2, BS3_PBC_NEAR
71 div xBX
72.again:
73 ud2
74 jmp .again
75BS3_PROC_END_CMN bs3CpuInstr2_div_xBX_ud2
76
77
78BS3_PROC_BEGIN_CMN bs3CpuInstr2_idiv_xBX_ud2, BS3_PBC_NEAR
79 idiv xBX
80.again:
81 ud2
82 jmp .again
83BS3_PROC_END_CMN bs3CpuInstr2_idiv_xBX_ud2
84
85;
86; RORX - VEX instruction with a couple of questions about non-standard encodings.
87;
88%define icebp ud2
89BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp, BS3_PBC_NEAR
90%if TMPL_BITS != 16
91 rorx ebx, edx, 2
92%else
93 db 0C4h,0E3h,07Bh,0F0h,0DAh,002h ; wrong nasm mode, whatever
94%endif
95.again:
96 icebp
97 jmp .again
98BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp
99
100BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_RBX_RDX_2_icebp, BS3_PBC_NEAR
101%if TMPL_BITS == 64
102 rorx rbx, rdx, 2
103%else
104 db 0C4h,0E3h,0FBh,0F0h,0DAh,002h ; 32-bit ignores VEX.W=1 (10980xe)
105%endif
106.again:
107 icebp
108 jmp .again
109BS3_PROC_END_CMN bs3CpuInstr2_rorx_RBX_RDX_2_icebp
110
111BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_L1, BS3_PBC_NEAR
112 db 0C4h, 0E3h, 07Bh | 4h, 0F0h, 0DAh, 002h ; VEX.L=1 should #UD according to the docs
113.again:
114 icebp
115 jmp .again
116BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_L1
117
118BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_V1, BS3_PBC_NEAR
119 db 0C4h, 0E3h, 003h | ~(1 << 3), 0F0h, 0DAh, 002h ; VEX.VVVV=1 - behaviour is undocumented - 10980xe #UD
120.again:
121 icebp
122 jmp .again
123BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_V1
124
125BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_V15, BS3_PBC_NEAR
126 db 0C4h, 0E3h, 003h | ~(15 << 3), 0F0h, 0DAh, 002h ; VEX.VVVV=15 - behaviour is not documented - 10980xe #UD
127.again:
128 icebp
129 jmp .again
130BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_V15
131
132 %if TMPL_BITS == 64
133BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_X1, BS3_PBC_NEAR
134 db 0C4h, 0E3h & ~40h, 07Bh, 0F0h, 0DAh, 002h ; VEX.X=0 - behaviour is not documented - ignored by 10980xe
135.again:
136 icebp
137 jmp .again
138BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_X1
139 %endif
140
141
142;
143;
144;
145 %if TMPL_BITS == 64
146BS3_PROC_BEGIN_CMN bs3CpuInstr2_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
147 cmpxchg16b [rdi]
148.again:
149 ud2
150 jmp .again
151AssertCompile(.again - BS3_LAST_LABEL == 4)
152BS3_PROC_END_CMN bs3CpuInstr2_cmpxchg16b_rdi_ud2
153
154
155BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
156 lock cmpxchg16b [rdi]
157.again:
158 ud2
159 jmp .again
160AssertCompile(.again - BS3_LAST_LABEL == 5)
161BS3_PROC_END_CMN bs3CpuInstr2_lock_cmpxchg16b_rdi_ud2
162
163
164BS3_PROC_BEGIN_CMN bs3CpuInstr2_o16_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
165 o16 cmpxchg16b [rdi]
166.again:
167 ud2
168 jmp .again
169AssertCompile(.again - BS3_LAST_LABEL == 5)
170BS3_PROC_END_CMN bs3CpuInstr2_o16_cmpxchg16b_rdi_ud2
171
172
173BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_o16_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
174 db 0f0h, 066h
175 cmpxchg16b [rdi]
176.again:
177 ud2
178 jmp .again
179AssertCompile(.again - BS3_LAST_LABEL == 6)
180BS3_PROC_END_CMN bs3CpuInstr2_lock_o16_cmpxchg16b_rdi_ud2
181
182
183BS3_PROC_BEGIN_CMN bs3CpuInstr2_repz_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
184 repz cmpxchg16b [rdi]
185.again:
186 ud2
187 jmp .again
188AssertCompile(.again - BS3_LAST_LABEL == 5)
189BS3_PROC_END_CMN bs3CpuInstr2_repz_cmpxchg16b_rdi_ud2
190
191
192BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_repz_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
193 db 0f0h, 0f3h
194 cmpxchg16b [rdi]
195.again:
196 ud2
197 jmp .again
198AssertCompile(.again - BS3_LAST_LABEL == 6)
199BS3_PROC_END_CMN bs3CpuInstr2_lock_repz_cmpxchg16b_rdi_ud2
200
201BS3_PROC_BEGIN_CMN bs3CpuInstr2_repnz_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
202 repnz cmpxchg16b [rdi]
203.again:
204 ud2
205 jmp .again
206AssertCompile(.again - BS3_LAST_LABEL == 5)
207BS3_PROC_END_CMN bs3CpuInstr2_repnz_cmpxchg16b_rdi_ud2
208
209
210BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_repnz_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
211 db 0f0h, 0f2h
212 cmpxchg16b [rdi]
213.again:
214 ud2
215 jmp .again
216AssertCompile(.again - BS3_LAST_LABEL == 6)
217BS3_PROC_END_CMN bs3CpuInstr2_lock_repnz_cmpxchg16b_rdi_ud2
218
219
220BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrfsbase_rbx_ud2, BS3_PBC_NEAR
221 wrfsbase rbx
222.again:
223 ud2
224 jmp .again
225AssertCompile(.again - BS3_LAST_LABEL == 5)
226BS3_PROC_END_CMN bs3CpuInstr2_wrfsbase_rbx_ud2
227
228
229BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrfsbase_ebx_ud2, BS3_PBC_NEAR
230 wrfsbase ebx
231.again:
232 ud2
233 jmp .again
234AssertCompile(.again - BS3_LAST_LABEL == 4)
235BS3_PROC_END_CMN bs3CpuInstr2_wrfsbase_ebx_ud2
236
237
238BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrgsbase_rbx_ud2, BS3_PBC_NEAR
239 wrgsbase rbx
240.again:
241 ud2
242 jmp .again
243AssertCompile(.again - BS3_LAST_LABEL == 5)
244BS3_PROC_END_CMN bs3CpuInstr2_wrgsbase_rbx_ud2
245
246
247BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrgsbase_ebx_ud2, BS3_PBC_NEAR
248 wrgsbase ebx
249.again:
250 ud2
251 jmp .again
252AssertCompile(.again - BS3_LAST_LABEL == 4)
253BS3_PROC_END_CMN bs3CpuInstr2_wrgsbase_ebx_ud2
254
255
256BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrfsbase_rbx_rdfsbase_rcx_ud2, BS3_PBC_NEAR
257 wrfsbase rbx
258 xor rbx, rbx
259 rdfsbase rcx
260.again:
261 ud2
262 jmp .again
263AssertCompile(.again - BS3_LAST_LABEL == 13)
264BS3_PROC_END_CMN bs3CpuInstr2_wrfsbase_rbx_rdfsbase_rcx_ud2
265
266
267BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrfsbase_ebx_rdfsbase_ecx_ud2, BS3_PBC_NEAR
268 wrfsbase ebx
269 xor ebx, ebx
270 rdfsbase ecx
271.again:
272 ud2
273 jmp .again
274AssertCompile(.again - BS3_LAST_LABEL == 10)
275BS3_PROC_END_CMN bs3CpuInstr2_wrfsbase_ebx_rdfsbase_ecx_ud2
276
277
278BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrgsbase_rbx_rdgsbase_rcx_ud2, BS3_PBC_NEAR
279 wrgsbase rbx
280 xor rbx, rbx
281 rdgsbase rcx
282.again:
283 ud2
284 jmp .again
285AssertCompile(.again - BS3_LAST_LABEL == 13)
286BS3_PROC_END_CMN bs3CpuInstr2_wrgsbase_rbx_rdgsbase_rcx_ud2
287
288
289BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrgsbase_ebx_rdgsbase_ecx_ud2, BS3_PBC_NEAR
290 wrgsbase ebx
291 xor ebx, ebx
292 rdgsbase ecx
293.again:
294 ud2
295 jmp .again
296AssertCompile(.again - BS3_LAST_LABEL == 10)
297BS3_PROC_END_CMN bs3CpuInstr2_wrfgbase_ebx_rdgsbase_ecx_ud2
298
299
300BS3_PROC_BEGIN_CMN bs3CpuInstr2_rdfsbase_rbx_ud2, BS3_PBC_NEAR
301 rdfsbase rbx
302.again:
303 ud2
304 jmp .again
305AssertCompile(.again - BS3_LAST_LABEL == 5)
306BS3_PROC_END_CMN bs3CpuInstr2_rdfsbase_rbx_ud2
307
308
309BS3_PROC_BEGIN_CMN bs3CpuInstr2_rdfsbase_ebx_ud2, BS3_PBC_NEAR
310 rdfsbase ebx
311.again:
312 ud2
313 jmp .again
314AssertCompile(.again - BS3_LAST_LABEL == 4)
315BS3_PROC_END_CMN bs3CpuInstr2_rdfsbase_ebx_ud2
316
317
318BS3_PROC_BEGIN_CMN bs3CpuInstr2_rdgsbase_rbx_ud2, BS3_PBC_NEAR
319 rdgsbase rbx
320.again:
321 ud2
322 jmp .again
323AssertCompile(.again - BS3_LAST_LABEL == 5)
324BS3_PROC_END_CMN bs3CpuInstr2_rdgsbase_rbx_ud2
325
326
327BS3_PROC_BEGIN_CMN bs3CpuInstr2_rdgsbase_ebx_ud2, BS3_PBC_NEAR
328 rdgsbase ebx
329.again:
330 ud2
331 jmp .again
332AssertCompile(.again - BS3_LAST_LABEL == 4)
333BS3_PROC_END_CMN bs3CpuInstr2_rdgsbase_ebx_ud2
334
335
336;; @todo figure out this fudge. sigh.
337times (348) db 0cch ; fudge to avoid 'rderr' during boot.
338
339 %endif ; TMPL_BITS == 64
340
341
342%endif ; BS3_INSTANTIATING_CMN
343
344%include "bs3kit-template-footer.mac" ; reset environment
345
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