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source: vbox/trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-2-template.mac@ 103615

最後變更 在這個檔案從103615是 103611,由 vboxsync 提交於 13 月 前

ValKit/bs3-cpu-instr-2: Test the alternate reg/reg encoding of and, or, xor, add, adc, sub, sbb and cmp. Extended x86extra.mac with macros for manually encoding reg/reg instructions like this. bugref:10376
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1; $Id: bs3-cpu-instr-2-template.mac 103611 2024-02-29 11:26:29Z vboxsync $
2;; @file
3; BS3Kit - bs3-cpu-instr-2 assembly template.
4;
5
6;
7; Copyright (C) 2007-2023 Oracle and/or its affiliates.
8;
9; This file is part of VirtualBox base platform packages, as
10; available from https://www.alldomusa.eu.org.
11;
12; This program is free software; you can redistribute it and/or
13; modify it under the terms of the GNU General Public License
14; as published by the Free Software Foundation, in version 3 of the
15; License.
16;
17; This program is distributed in the hope that it will be useful, but
18; WITHOUT ANY WARRANTY; without even the implied warranty of
19; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20; General Public License for more details.
21;
22; You should have received a copy of the GNU General Public License
23; along with this program; if not, see <https://www.gnu.org/licenses>.
24;
25; The contents of this file may alternatively be used under the terms
26; of the Common Development and Distribution License Version 1.0
27; (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
28; in the VirtualBox distribution, in which case the provisions of the
29; CDDL are applicable instead of those of the GPL.
30;
31; You may elect to license modified versions of this file under the
32; terms and conditions of either the GPL or the CDDL or both.
33;
34; SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
35;
36
37
38;*********************************************************************************************************************************
39;* Header Files *
40;*********************************************************************************************************************************
41%include "bs3kit-template-header.mac" ; setup environment
42
43
44;*********************************************************************************************************************************
45;* Defined Constants And Macros *
46;*********************************************************************************************************************************
47;;
48; Variant on BS3_PROC_BEGIN_CMN w/ BS3_PBC_NEAR that prefixes the function
49; with an instruction length byte.
50;
51; ASSUMES the length is between the start of the function and the .again label.
52;
53%ifndef BS3CPUINSTR2_PROC_BEGIN_CMN_DEFINED
54 %define BS3CPUINSTR2_PROC_BEGIN_CMN_DEFINED
55 %macro BS3CPUINSTR2_PROC_BEGIN_CMN 1
56 align 8, db 0cch
57 db BS3_CMN_NM(%1).again - BS3_CMN_NM(%1)
58BS3_PROC_BEGIN_CMN %1, BS3_PBC_NEAR
59 %endmacro
60%endif
61
62
63;;
64; For defining simple instruction test.
65%ifndef BS3CPUINSTR2_EMIT_INSTR_UD2_DEFINED
66 %define BS3CPUINSTR2_EMIT_INSTR_UD2_DEFINED
67 %macro BS3CPUINSTR2_EMIT_INSTR_UD2 2+
68BS3CPUINSTR2_PROC_BEGIN_CMN %1
69 %2
70.again:
71 ud2
72 jmp .again
73BS3_PROC_END_CMN %1
74 %endmacro
75%endif
76
77;;
78; @param 1 The instruction menmonic.
79; @param 2 Whether there is an 8-bit form of the instruction (1) or not 0.
80; @param 3 Whether there are alternative forms of the instruction.
81%ifndef BS3CPUINSTR2_BINARY_OP_DEFINED
82 %define BS3CPUINSTR2_BINARY_OP_DEFINED
83 %macro BS3CPUINSTR2_BINARY_OP 3
84 %if %2 != 0
85 ; 8-bit
86 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _al %+ _dl, %1 al, dl
87 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _ch %+ _bh, %1 ch, bh
88 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _dl %+ _ah, %1 dl, ah
89 %if %3 != 0
90 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _dh %+ _cl, ALT_INSTRUCTION8_ %+ %1 dh, cl
91 %endif
92 %ifdef TMPL_64BIT
93 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _sil %+ _dil, %1 sil, dil
94 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r9b %+ _r8b, %1 r9b, r8b
95 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _al %+ _r13b, %1 al, r13b
96 %if %3 != 0
97 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _dl %+ _r14b, ALT_INSTRUCTION8_ %+ %1 dl, r14b
98 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _r8b %+ _bl, ALT_INSTRUCTION8_ %+ %1 r8b, bl
99 %endif
100 %endif
101 %endif
102 ; 16-bit
103 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _di %+ _si, %1 di, si
104 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _cx %+ _bp, %1 cx, bp
105 %if %3 != 0
106 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _bp %+ _bx, ALT_INSTRUCTION16_ %+ %1 bp, bx
107 %endif
108 %ifdef TMPL_64BIT
109 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r8w %+ _cx, %1 r8w, cx
110 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r15w %+ _r10w, %1 r15w, r10w
111 %if %3 != 0
112 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _r13w %+ _ax, ALT_INSTRUCTION16_ %+ %1 r13w, ax
113 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _si %+ _r9w, ALT_INSTRUCTION16_ %+ %1 si, r9w
114 %endif
115 %endif
116 ; 32-bit
117 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _eax %+ _ebx, %1 eax, ebx
118 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _ecx %+ _ebp, %1 ecx, ebp
119 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _edx %+ _edi, %1 edx, edi
120 %if %3 != 0
121 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _edi %+ _esi, ALT_INSTRUCTION32_ %+ %1 edi, esi
122 %endif
123 %ifdef TMPL_64BIT
124 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _eax %+ _r8d, %1 eax, r8d
125 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r9d %+ _ecx, %1 r9d, ecx
126 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r13d %+ _r14d, %1 r13d, r14d
127 %if %3 != 0
128 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _r15d %+ _esi, ALT_INSTRUCTION32_ %+ %1 r15d, esi
129 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _eax %+ _r10d, ALT_INSTRUCTION32_ %+ %1 eax, r10d
130 %endif
131 %endif
132 ; 64-bit
133 %ifdef TMPL_64BIT
134 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _rax %+ _rbx, %1 rax, rbx
135 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r8 %+ _rax, %1 r8, rax
136 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _rdx %+ _r10, %1 rdx, r10
137 %if %3 != 0
138 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _r15 %+ _rsi, ALT_INSTRUCTION64_ %+ %1 r15, rsi
139 BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _rbx %+ _r14, ALT_INSTRUCTION64_ %+ %1 rbx, r14
140 %endif
141 %endif
142 %endmacro
143%endif
144
145
146;*********************************************************************************************************************************
147;* External Symbols *
148;*********************************************************************************************************************************
149TMPL_BEGIN_TEXT
150
151
152;
153; Test code snippets containing code which differs between 16-bit, 32-bit
154; and 64-bit CPUs modes.
155;
156%ifdef BS3_INSTANTIATING_CMN
157
158%ifndef ALT_INSTRUCTION_MACROS_DEFINED
159 %define ALT_INSTRUCTION_MACROS_DEFINED
160 %macro ALT_INSTRUCTION8_REG_RM 3+
161 X86_MKOP_REX8 %1, %2
162 db %3
163 X86_MKOP_MODRM8 X86_MOD_REG, %1, %2
164 %endmacro
165
166 %macro ALT_INSTRUCTION16_REG_RM 3+
167 %if TMPL_BITS != 16
168 db X86_OP_PRF_SIZE_OP
169 %endif
170 X86_MKOP_REX16 %1, %2
171 db %3
172 X86_MKOP_MODRM16 X86_MOD_REG, %1, %2
173 %endmacro
174
175 %macro ALT_INSTRUCTION32_REG_RM 3+
176 %if TMPL_BITS == 16
177 db X86_OP_PRF_SIZE_OP
178 %endif
179 X86_MKOP_REX32 %1, %2
180 db %3
181 X86_MKOP_MODRM32 X86_MOD_REG, %1, %2
182 %endmacro
183
184 %macro ALT_INSTRUCTION64_REG_RM 3+
185 X86_MKOP_REX64 %1, %2
186 db %3
187 X86_MKOP_MODRM64 X86_MOD_REG, %1, %2
188 %endmacro
189
190 ; nasm v2.16.02rc1 encodes the 20h and 21h variants (AND rm,reg)
191 %macro ALT_INSTRUCTION8_and 2
192 ALT_INSTRUCTION8_REG_RM %1, %2, 22h
193 %endmacro
194 %macro ALT_INSTRUCTION16_and 2
195 ALT_INSTRUCTION16_REG_RM %1, %2, 23h
196 %endmacro
197 %macro ALT_INSTRUCTION32_and 2
198 ALT_INSTRUCTION32_REG_RM %1, %2, 23h
199 %endmacro
200 %macro ALT_INSTRUCTION64_and 2
201 ALT_INSTRUCTION64_REG_RM %1, %2, 23h
202 %endmacro
203
204 ; nasm v2.16.02rc1 encodes the 08h and 09h variants (OR rm,reg)
205 %macro ALT_INSTRUCTION8_or 2
206 ALT_INSTRUCTION8_REG_RM %1, %2, 0ah
207 %endmacro
208 %macro ALT_INSTRUCTION16_or 2
209 ALT_INSTRUCTION16_REG_RM %1, %2, 0bh
210 %endmacro
211 %macro ALT_INSTRUCTION32_or 2
212 ALT_INSTRUCTION32_REG_RM %1, %2, 0bh
213 %endmacro
214 %macro ALT_INSTRUCTION64_or 2
215 ALT_INSTRUCTION64_REG_RM %1, %2, 0bh
216 %endmacro
217
218 ; nasm v2.16.02rc1 encodes the 30h and 31h variants (XOR rm,reg)
219 %macro ALT_INSTRUCTION8_xor 2
220 ALT_INSTRUCTION8_REG_RM %1, %2, 32h
221 %endmacro
222 %macro ALT_INSTRUCTION16_xor 2
223 ALT_INSTRUCTION16_REG_RM %1, %2, 33h
224 %endmacro
225 %macro ALT_INSTRUCTION32_xor 2
226 ALT_INSTRUCTION32_REG_RM %1, %2, 33h
227 %endmacro
228 %macro ALT_INSTRUCTION64_xor 2
229 ALT_INSTRUCTION64_REG_RM %1, %2, 33h
230 %endmacro
231
232 ; nasm v2.16.02rc1 encodes the 00h and 01h variants (ADD rm,reg)
233 %macro ALT_INSTRUCTION8_add 2
234 ALT_INSTRUCTION8_REG_RM %1, %2, 02h
235 %endmacro
236 %macro ALT_INSTRUCTION16_add 2
237 ALT_INSTRUCTION16_REG_RM %1, %2, 03h
238 %endmacro
239 %macro ALT_INSTRUCTION32_add 2
240 ALT_INSTRUCTION32_REG_RM %1, %2, 03h
241 %endmacro
242 %macro ALT_INSTRUCTION64_add 2
243 ALT_INSTRUCTION64_REG_RM %1, %2, 03h
244 %endmacro
245
246 ; nasm v2.16.02rc1 encodes the 10h and 11h variants (ADC rm,reg)
247 %macro ALT_INSTRUCTION8_adc 2
248 ALT_INSTRUCTION8_REG_RM %1, %2, 12h
249 %endmacro
250 %macro ALT_INSTRUCTION16_adc 2
251 ALT_INSTRUCTION16_REG_RM %1, %2, 13h
252 %endmacro
253 %macro ALT_INSTRUCTION32_adc 2
254 ALT_INSTRUCTION32_REG_RM %1, %2, 13h
255 %endmacro
256 %macro ALT_INSTRUCTION64_adc 2
257 ALT_INSTRUCTION64_REG_RM %1, %2, 13h
258 %endmacro
259
260 ; nasm v2.16.02rc1 encodes the 28h and 29h variants (SUB rm,reg)
261 %macro ALT_INSTRUCTION8_sub 2
262 ALT_INSTRUCTION8_REG_RM %1, %2, 2ah
263 %endmacro
264 %macro ALT_INSTRUCTION16_sub 2
265 ALT_INSTRUCTION16_REG_RM %1, %2, 2bh
266 %endmacro
267 %macro ALT_INSTRUCTION32_sub 2
268 ALT_INSTRUCTION32_REG_RM %1, %2, 2bh
269 %endmacro
270 %macro ALT_INSTRUCTION64_sub 2
271 ALT_INSTRUCTION64_REG_RM %1, %2, 2bh
272 %endmacro
273
274 ; nasm v2.16.02rc1 encodes the 18h and 19h variants (SBB rm,reg)
275 %macro ALT_INSTRUCTION8_sbb 2
276 ALT_INSTRUCTION8_REG_RM %1, %2, 1ah
277 %endmacro
278 %macro ALT_INSTRUCTION16_sbb 2
279 ALT_INSTRUCTION16_REG_RM %1, %2, 1bh
280 %endmacro
281 %macro ALT_INSTRUCTION32_sbb 2
282 ALT_INSTRUCTION32_REG_RM %1, %2, 1bh
283 %endmacro
284 %macro ALT_INSTRUCTION64_sbb 2
285 ALT_INSTRUCTION64_REG_RM %1, %2, 1bh
286 %endmacro
287
288 ; nasm v2.16.02rc1 encodes the 38h and 39h variants (CMP rm,reg)
289 %macro ALT_INSTRUCTION8_cmp 2
290 ALT_INSTRUCTION8_REG_RM %1, %2, 3ah
291 %endmacro
292 %macro ALT_INSTRUCTION16_cmp 2
293 ALT_INSTRUCTION16_REG_RM %1, %2, 3bh
294 %endmacro
295 %macro ALT_INSTRUCTION32_cmp 2
296 ALT_INSTRUCTION32_REG_RM %1, %2, 3bh
297 %endmacro
298 %macro ALT_INSTRUCTION64_cmp 2
299 ALT_INSTRUCTION64_REG_RM %1, %2, 3bh
300 %endmacro
301
302%endif ; !ALT_INSTRUCTION_MACROS_DEFINED
303
304BS3CPUINSTR2_BINARY_OP and, 1, 1
305BS3CPUINSTR2_BINARY_OP or, 1, 1
306BS3CPUINSTR2_BINARY_OP xor, 1, 1
307BS3CPUINSTR2_BINARY_OP test, 1, 0
308
309BS3CPUINSTR2_BINARY_OP add, 1, 1
310BS3CPUINSTR2_BINARY_OP adc, 1, 1
311BS3CPUINSTR2_BINARY_OP sub, 1, 1
312BS3CPUINSTR2_BINARY_OP sbb, 1, 1
313BS3CPUINSTR2_BINARY_OP cmp, 1, 1
314
315BS3CPUINSTR2_BINARY_OP bt, 0, 0
316BS3CPUINSTR2_BINARY_OP btc, 0, 0
317BS3CPUINSTR2_BINARY_OP btr, 0, 0
318BS3CPUINSTR2_BINARY_OP bts, 0, 0
319
320
321BS3_PROC_BEGIN_CMN bs3CpuInstr2_mul_xBX_ud2, BS3_PBC_NEAR
322 mul xBX
323.again:
324 ud2
325 jmp .again
326BS3_PROC_END_CMN bs3CpuInstr2_mul_xBX_ud2
327
328
329BS3_PROC_BEGIN_CMN bs3CpuInstr2_imul_xBX_ud2, BS3_PBC_NEAR
330 imul xBX
331.again:
332 ud2
333 jmp .again
334BS3_PROC_END_CMN bs3CpuInstr2_imul_xBX_ud2
335
336
337BS3_PROC_BEGIN_CMN bs3CpuInstr2_imul_xCX_xBX_ud2, BS3_PBC_NEAR
338 imul xCX, xBX
339.again:
340 ud2
341 jmp .again
342BS3_PROC_END_CMN bs3CpuInstr2_imul_xCX_xBX_ud2
343
344
345BS3_PROC_BEGIN_CMN bs3CpuInstr2_div_xBX_ud2, BS3_PBC_NEAR
346 div xBX
347.again:
348 ud2
349 jmp .again
350BS3_PROC_END_CMN bs3CpuInstr2_div_xBX_ud2
351
352
353BS3_PROC_BEGIN_CMN bs3CpuInstr2_idiv_xBX_ud2, BS3_PBC_NEAR
354 idiv xBX
355.again:
356 ud2
357 jmp .again
358BS3_PROC_END_CMN bs3CpuInstr2_idiv_xBX_ud2
359
360
361;
362; BSF / BSR / TZCNT / LZCNT
363;
364%ifndef EMIT_BITSCAN_DEFINED
365%define EMIT_BITSCAN_DEFINED
366%macro EMIT_BITSCAN 3
367BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %3 %+ _AX_BX_ud2, BS3_PBC_NEAR
368 %2
369 %1 ax, bx
370.again:
371 ud2
372 jmp .again
373BS3_PROC_END_CMN bs3CpuInstr2_ %+ %3 %+ _AX_BX_ud2
374
375BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %3 %+ _AX_FSxBX_ud2, BS3_PBC_NEAR
376 %2
377 %1 ax, [fs:xBX]
378.again:
379 ud2
380 jmp .again
381BS3_PROC_END_CMN bs3CpuInstr2_ %+ %3 %+ _AX_FSxBX_ud2
382
383BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %3 %+ _EAX_EBX_ud2, BS3_PBC_NEAR
384 %2
385 %1 eax, ebx
386.again:
387 ud2
388 jmp .again
389BS3_PROC_END_CMN bs3CpuInstr2_ %+ %3 %+ _EAX_EBX_ud2
390
391BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %3 %+ _EAX_FSxBX_ud2, BS3_PBC_NEAR
392 %2
393 %1 eax, [fs:xBX]
394.again:
395 ud2
396 jmp .again
397BS3_PROC_END_CMN bs3CpuInstr2_ %+ %3 %+ _EAX_FSxBX_ud2
398
399 %if TMPL_BITS == 64
400BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %3 %+ _RAX_RBX_ud2, BS3_PBC_NEAR
401 %2
402 %1 rax, rbx
403.again:
404 ud2
405 jmp .again
406BS3_PROC_END_CMN bs3CpuInstr2_ %+ %3 %+ _RAX_RBX_ud2
407
408BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %3 %+ _RAX_FSxBX_ud2, BS3_PBC_NEAR
409 %2
410 %1 rax, [fs:xBX]
411.again:
412 ud2
413 jmp .again
414BS3_PROC_END_CMN bs3CpuInstr2_ %+ %3 %+ _RAX_FSxBX_ud2
415 %endif
416%endmacro
417%endif
418
419EMIT_BITSCAN bsf, .ignored:, bsf
420EMIT_BITSCAN bsr, .ignored:, bsr
421EMIT_BITSCAN tzcnt, .ignored:, tzcnt
422EMIT_BITSCAN lzcnt, .ignored:, lzcnt
423EMIT_BITSCAN bsf, db 0f2h, f2_bsf
424EMIT_BITSCAN bsr, db 0f2h, f2_bsr
425EMIT_BITSCAN tzcnt, db 0f2h, f2_tzcnt
426EMIT_BITSCAN lzcnt, db 0f2h, f2_lzcnt
427
428
429;
430; RORX - VEX instruction with a couple of questions about non-standard encodings.
431;
432;;%define icebp ud2
433BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp, BS3_PBC_NEAR
434 rorx ebx, edx, 2
435.again:
436 icebp
437 jmp .again
438BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp
439
440BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_RBX_RDX_2_icebp, BS3_PBC_NEAR
441%if TMPL_BITS == 64
442 rorx rbx, rdx, 2
443%else
444 db 0C4h,0E3h,0FBh,0F0h,0DAh,002h ; 32-bit ignores VEX.W=1 (10980xe)
445%endif
446.again:
447 icebp
448 jmp .again
449BS3_PROC_END_CMN bs3CpuInstr2_rorx_RBX_RDX_2_icebp
450
451BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_L1, BS3_PBC_NEAR
452 db 0C4h, 0E3h, 07Bh | 4h, 0F0h, 0DAh, 002h ; VEX.L=1 should #UD according to the docs
453.again:
454 icebp
455 jmp .again
456BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_L1
457
458BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_V1, BS3_PBC_NEAR
459 db 0C4h, 0E3h, 003h | ~(1 << 3), 0F0h, 0DAh, 002h ; VEX.VVVV=1 - behaviour is undocumented - 10980xe #UD
460.again:
461 icebp
462 jmp .again
463BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_V1
464
465BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_V15, BS3_PBC_NEAR
466 db 0C4h, 0E3h, 003h | ~(15 << 3), 0F0h, 0DAh, 002h ; VEX.VVVV=15 - behaviour is not documented - 10980xe #UD
467.again:
468 icebp
469 jmp .again
470BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_V15
471
472 %if TMPL_BITS == 64
473BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_X1, BS3_PBC_NEAR
474 db 0C4h, 0E3h & ~40h, 07Bh, 0F0h, 0DAh, 002h ; VEX.X=0 - behaviour is not documented - ignored by 10980xe
475.again:
476 icebp
477 jmp .again
478BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_X1
479 %endif
480
481; A couple of memory variants
482BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_DSxDI_36_icebp, BS3_PBC_NEAR
483 rorx ebx, [xDI], 36
484.again:
485 icebp
486 jmp .again
487BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_DSxDI_36_icebp
488
489BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_RBX_DSxDI_68_icebp, BS3_PBC_NEAR
490 %if TMPL_BITS == 64
491 rorx rbx, [xDI], 68
492 %elif TMPL_BITS == 32
493 db 0C4h,0E3h,07Bh,0F0h,01Fh,044h ; 16-bit ignores VEX.W=1 (10980xe)
494 %else
495 db 0C4h,0E3h,0FBh,0F0h,01Dh,044h ; 16-bit ignores VEX.W=1 (10980xe)
496 %endif
497.again:
498 icebp
499 jmp .again
500BS3_PROC_END_CMN bs3CpuInstr2_rorx_RBX_DSxDI_68_icebp
501
502;
503; ANDN (BMI1)
504;
505BS3_PROC_BEGIN_CMN bs3CpuInstr2_andn_RAX_RCX_RBX_icebp, BS3_PBC_NEAR
506%if TMPL_BITS == 64
507 andn rax, rcx, rbx
508%else
509 db 0C4h,0E2h,0F0h,0F2h,0C3h ; 32-bit & 16-bit ignores VEX.W=1 (10980xe)
510%endif
511.again:
512 icebp
513 jmp .again
514BS3_PROC_END_CMN bs3CpuInstr2_andn_RAX_RCX_RBX_icebp
515
516BS3_PROC_BEGIN_CMN bs3CpuInstr2_andn_EAX_ECX_EBX_icebp, BS3_PBC_NEAR
517 andn eax, ecx, ebx
518.again:
519 icebp
520 jmp .again
521BS3_PROC_END_CMN bs3CpuInstr2_andn_EAX_ECX_EBX_icebp
522
523
524BS3_PROC_BEGIN_CMN bs3CpuInstr2_andn_RAX_RCX_FSxBX_icebp, BS3_PBC_NEAR
525%if TMPL_BITS == 64
526 andn rax, rcx, [fs:rbx]
527%elif TMPL_BITS == 32
528 db 064h,0C4h,0E2h,0F0h,0F2h,003h ; andn rax, rcx, [fs:ebx]
529%else
530 db 064h,0C4h,0E2h,0F0h,0F2h,007h ; andn rax, rcx, [fs:bx]
531%endif
532.again:
533 icebp
534 jmp .again
535BS3_PROC_END_CMN bs3CpuInstr2_andn_RAX_RCX_FSxBX_icebp
536
537BS3_PROC_BEGIN_CMN bs3CpuInstr2_andn_EAX_ECX_FSxBX_icebp, BS3_PBC_NEAR
538 andn eax, ecx, [fs:xBX]
539.again:
540 icebp
541 jmp .again
542BS3_PROC_END_CMN bs3CpuInstr2_andn_EAX_ECX_FSxBX_icebp
543
544
545;
546; BEXTR / SHLX / SARX / SHRX - BMI1 (opcode f7h)
547; BZHI - BMI2 (opcode f5h)
548;
549; @param %1 instruction
550; @param %2 opcode
551; @param %3 prefix
552;
553%ifndef SHLX_SARX_SHRX_DEFINED
554%define SHLX_SARX_SHRX_DEFINED
555%macro SHLX_SARX_SHRX 3
556
557BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RBX_RCX_icebp, BS3_PBC_NEAR
558 %if TMPL_BITS == 64
559 %1 rax, rbx, rcx ; SHLX=C4E2F1F7C3
560 %else
561 db 0C4h,0E2h,0F0h|%3,%2,0C3h ; 32-bit & 16-bit ignores VEX.W=1 (10980xe)
562 %endif
563.again:
564 icebp
565 jmp .again
566BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RBX_RCX_icebp
567
568BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_EBX_ECX_icebp, BS3_PBC_NEAR
569 %1 eax, ebx, ecx
570.again:
571 icebp
572 jmp .again
573BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_EBX_ECX_icebp
574
575BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_FSxBX_RCX_icebp, BS3_PBC_NEAR
576 %if TMPL_BITS == 64
577 %1 rax, [fs:rbx], rcx ; SHLX=64C4E2F1F703
578 %elif TMPL_BITS == 32
579 db 064h,0C4h,0E2h,0F0h|%3,%2,003h
580 %else
581 db 064h,0C4h,0E2h,0F0h|%3,%2,007h
582 %endif
583.again:
584 icebp
585 jmp .again
586BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_FSxBX_RCX_icebp
587
588BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_FSxBX_ECX_icebp, BS3_PBC_NEAR
589 %1 eax, [fs:xBX], ecx
590.again:
591 icebp
592 jmp .again
593BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_FSxBX_ECX_icebp
594
595%endmacro
596%endif
597
598SHLX_SARX_SHRX bextr, 0f7h, 0 ; none
599SHLX_SARX_SHRX shlx, 0f7h, 1 ; 66h
600SHLX_SARX_SHRX sarx, 0f7h, 2 ; f3h
601SHLX_SARX_SHRX shrx, 0f7h, 3 ; f2h
602SHLX_SARX_SHRX bzhi, 0f5h, 0 ; none
603
604;
605; PPEP / PEXT - BMI2 (opcode f5h)
606;
607; @param %1 instruction
608; @param %2 opcode
609; @param %3 prefix
610;
611%ifndef PDEP_PEXT_DEFINED
612%define PDEP_PEXT_DEFINED
613%macro PDEP_PEXT_ 3
614
615BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RCX_RBX_icebp, BS3_PBC_NEAR
616 %if TMPL_BITS == 64
617 %1 rax, rcx, rbx
618 %else
619 db 0C4h,0E2h,0F0h|%3,%2,0C3h ; 32-bit & 16-bit ignores VEX.W=1 (10980xe)
620 %endif
621.again:
622 icebp
623 jmp .again
624BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RCX_RBX_icebp
625
626BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_ECX_EBX_icebp, BS3_PBC_NEAR
627 %1 eax, ecx, ebx
628.again:
629 icebp
630 jmp .again
631BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_ECX_EBX_icebp
632
633BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RCX_FSxBX_icebp, BS3_PBC_NEAR
634 %if TMPL_BITS == 64
635 %1 rax, rcx, [fs:rbx]
636 %elif TMPL_BITS == 32
637 db 064h,0C4h,0E2h,0F0h|%3,%2,003h
638 %else
639 db 064h,0C4h,0E2h,0F0h|%3,%2,007h
640 %endif
641.again:
642 icebp
643 jmp .again
644BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RCX_FSxBX_icebp
645
646BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_ECX_FSxBX_icebp, BS3_PBC_NEAR
647 %1 eax, ecx, [fs:xBX]
648.again:
649 icebp
650 jmp .again
651BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_ECX_FSxBX_icebp
652
653%endmacro
654%endif
655
656PDEP_PEXT_ pext, 0f5h, 2 ; f3h
657PDEP_PEXT_ pdep, 0f5h, 3 ; f2h
658
659;
660; BLSR / BLSMSK / BLSI
661; These are encoded in the exact same way, only the /r differs (%2).
662;
663%ifndef BLSR_BLSMSK_BLSI_DEFINED
664%define BLSR_BLSMSK_BLSI_DEFINED
665%macro BLSR_BLSMSK_BLSI 2
666
667BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RBX_icebp, BS3_PBC_NEAR
668 %if TMPL_BITS == 64
669 %1 rax, rbx ; BLSR=C4E2F8F3CB
670 %else
671 db 0C4h,0E2h,0F8h,0F3h,0C3h | (%2 << 3) ; 32-bit & 16-bit ignores VEX.W=1 (10980xe)
672 %endif
673.again:
674 icebp
675 jmp .again
676BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RBX_icebp
677
678BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_EBX_icebp, BS3_PBC_NEAR
679 %1 eax, ebx
680.again:
681 icebp
682 jmp .again
683BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_EBX_icebp
684
685BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_FSxBX_icebp, BS3_PBC_NEAR
686 %if TMPL_BITS == 64
687 %1 rax, [fs:rbx] ; BSLR=64C4E2F8F30B
688 %elif TMPL_BITS == 32
689 db 064h,0C4h,0E2h,0F8h,0F3h,003h | (%2 << 3)
690 %else
691 db 064h,0C4h,0E2h,0F8h,0F3h,007h | (%2 << 3)
692 %endif
693.again:
694 icebp
695 jmp .again
696BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_FSxBX_icebp
697
698BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_FSxBX_icebp, BS3_PBC_NEAR
699 %1 eax, [fs:xBX]
700.again:
701 icebp
702 jmp .again
703BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_FSxBX_icebp
704
705%endmacro
706%endif
707
708BLSR_BLSMSK_BLSI blsr, 1
709BLSR_BLSMSK_BLSI blsmsk, 2
710BLSR_BLSMSK_BLSI blsi, 3
711
712;
713; MULX
714;
715BS3_PROC_BEGIN_CMN bs3CpuInstr2_mulx_RAX_RCX_RBX_RDX_icebp, BS3_PBC_NEAR
716 %if TMPL_BITS == 64
717 mulx rax, rcx, rbx ; C4E2F3F6C3
718 %else
719 db 0C4h,0E2h,0F3h,0F6h,0C3h ; 32-bit & 16-bit ignores VEX.W=1 (10980xe)
720 %endif
721.again:
722 icebp
723 jmp .again
724BS3_PROC_END_CMN bs3CpuInstr2_mulx_RAX_RCX_RBX_RDX_icebp
725
726BS3_PROC_BEGIN_CMN bs3CpuInstr2_mulx_RCX_RCX_RBX_RDX_icebp, BS3_PBC_NEAR
727 %if TMPL_BITS == 64
728 mulx rcx, rcx, rbx ; C4E2F3F6CB
729 %else
730 db 0C4h,0E2h,0F3h,0F6h,0CBh ; 32-bit & 16-bit ignores VEX.W=1 (10980xe)
731 %endif
732.again:
733 icebp
734 jmp .again
735BS3_PROC_END_CMN bs3CpuInstr2_mulx_RCX_RCX_RBX_RDX_icebp
736
737BS3_PROC_BEGIN_CMN bs3CpuInstr2_mulx_RAX_RCX_FSxBX_RDX_icebp, BS3_PBC_NEAR
738 %if TMPL_BITS == 64
739 mulx rax, rcx, [fs:rbx] ; 64C4E2F3F603
740 %elif TMPL_BITS == 32
741 db 064h,0C4h,0E2h,0F3h,0F6h,003h ; 32-bit & 16-bit ignores VEX.W=1 (10980xe)
742 %else
743 db 064h,0C4h,0E2h,0F3h,0F6h,007h ; 32-bit & 16-bit ignores VEX.W=1 (10980xe)
744 %endif
745.again:
746 icebp
747 jmp .again
748BS3_PROC_END_CMN bs3CpuInstr2_mulx_RAX_RCX_FSxBX_RDX_icebp
749
750BS3_PROC_BEGIN_CMN bs3CpuInstr2_mulx_EAX_ECX_EBX_EDX_icebp, BS3_PBC_NEAR
751 mulx eax, ecx, ebx
752.again:
753 icebp
754 jmp .again
755BS3_PROC_END_CMN bs3CpuInstr2_mulx_EAX_ECX_EBX_EDX_icebp
756
757BS3_PROC_BEGIN_CMN bs3CpuInstr2_mulx_ECX_ECX_EBX_EDX_icebp, BS3_PBC_NEAR
758 mulx ecx, ecx, ebx
759.again:
760 icebp
761 jmp .again
762BS3_PROC_END_CMN bs3CpuInstr2_mulx_ECX_ECX_EBX_EDX_icebp
763
764BS3_PROC_BEGIN_CMN bs3CpuInstr2_mulx_EAX_ECX_FSxBX_EDX_icebp, BS3_PBC_NEAR
765 mulx eax, ecx, [fs:xBX]
766.again:
767 icebp
768 jmp .again
769BS3_PROC_END_CMN bs3CpuInstr2_mulx_EAX_ECX_FSxBX_EDX_icebp
770
771
772;
773; POPCNT
774;
775BS3_PROC_BEGIN_CMN bs3CpuInstr2_popcnt_AX_BX_icebp, BS3_PBC_NEAR
776 popcnt ax, bx
777.again:
778 icebp
779 jmp .again
780BS3_PROC_END_CMN bs3CpuInstr2_popcnt_AX_BX_icebp
781
782BS3_PROC_BEGIN_CMN bs3CpuInstr2_popcnt_EAX_EBX_icebp, BS3_PBC_NEAR
783 popcnt eax, ebx
784.again:
785 icebp
786 jmp .again
787BS3_PROC_END_CMN bs3CpuInstr2_popcnt_EAX_EBX_icebp
788
789 %if TMPL_BITS == 64
790BS3_PROC_BEGIN_CMN bs3CpuInstr2_popcnt_RAX_RBX_icebp, BS3_PBC_NEAR
791 popcnt rax, rbx
792.again:
793 icebp
794 jmp .again
795BS3_PROC_END_CMN bs3CpuInstr2_popcnt_RAX_RBX_icebp
796 %endif
797
798
799BS3_PROC_BEGIN_CMN bs3CpuInstr2_popcnt_AX_FSxBX_icebp, BS3_PBC_NEAR
800 popcnt ax, [fs:xBX]
801.again:
802 icebp
803 jmp .again
804BS3_PROC_END_CMN bs3CpuInstr2_popcnt_AX_FSxBX_icebp
805
806BS3_PROC_BEGIN_CMN bs3CpuInstr2_popcnt_EAX_FSxBX_icebp, BS3_PBC_NEAR
807 popcnt eax, [fs:xBX]
808.again:
809 icebp
810 jmp .again
811BS3_PROC_END_CMN bs3CpuInstr2_popcnt_EAX_FSxBX_icebp
812
813 %if TMPL_BITS == 64
814BS3_PROC_BEGIN_CMN bs3CpuInstr2_popcnt_RAX_FSxBX_icebp, BS3_PBC_NEAR
815 popcnt rax, [fs:xBX]
816.again:
817 icebp
818 jmp .again
819BS3_PROC_END_CMN bs3CpuInstr2_popcnt_RAX_FSxBX_icebp
820 %endif
821
822
823;
824; CRC32
825;
826BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_BL_icebp
827 crc32 eax, bl
828.again:
829 icebp
830 jmp .again
831BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_BL_icebp
832
833BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_BX_icebp
834 crc32 eax, bx
835.again:
836 icebp
837 jmp .again
838BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_BX_icebp
839
840BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_EBX_icebp
841 crc32 eax, ebx
842.again:
843 icebp
844 jmp .again
845BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_EBX_icebp
846
847 %if TMPL_BITS == 64
848BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_RBX_icebp
849 crc32 rax, rbx
850.again:
851 icebp
852 jmp .again
853BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_RBX_icebp
854 %endif
855
856
857BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_byte_FSxBX_icebp
858 crc32 eax, byte [fs:xBX]
859.again:
860 icebp
861 jmp .again
862BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_byte_FSxBX_icebp
863
864BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_word_FSxBX_icebp
865 crc32 eax, word [fs:xBX]
866.again:
867 icebp
868 jmp .again
869BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_word_FSxBX_icebp
870
871BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_dword_FSxBX_icebp
872 crc32 eax, dword [fs:xBX]
873.again:
874 icebp
875 jmp .again
876BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_dword_FSxBX_icebp
877
878 %if TMPL_BITS == 64
879BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_crc32_EAX_qword_FSxBX_icebp
880 crc32 rax, qword [fs:xBX]
881.again:
882 icebp
883 jmp .again
884BS3_PROC_END_CMN bs3CpuInstr2_crc32_EAX_qword_FSxBX_icebp
885 %endif
886
887
888;
889; ADCX
890;
891BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_adcx_EAX_EBX_icebp
892 adcx eax, ebx
893.again:
894 icebp
895 jmp .again
896BS3_PROC_END_CMN bs3CpuInstr2_adcx_EAX_EBX_icebp
897
898 %if TMPL_BITS == 64
899BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_adcx_RAX_RBX_icebp
900 adcx rax, rbx
901.again:
902 icebp
903 jmp .again
904BS3_PROC_END_CMN bs3CpuInstr2_adcx_RAX_RBX_icebp
905 %endif
906
907BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_adcx_EAX_dword_FSxBX_icebp
908 adcx eax, dword [fs:xBX]
909.again:
910 icebp
911 jmp .again
912BS3_PROC_END_CMN bs3CpuInstr2_adcx_EAX_dword_FSxBX_icebp
913
914 %if TMPL_BITS == 64
915BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_adcx_RAX_qword_FSxBX_icebp
916 adcx rax, qword [fs:xBX]
917.again:
918 icebp
919 jmp .again
920BS3_PROC_END_CMN bs3CpuInstr2_adcx_RAX_qword_FSxBX_icebp
921 %endif
922
923
924;
925; ADOX
926;
927BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_adox_EAX_EBX_icebp
928 adox eax, ebx
929.again:
930 icebp
931 jmp .again
932BS3_PROC_END_CMN bs3CpuInstr2_adox_EAX_EBX_icebp
933
934 %if TMPL_BITS == 64
935BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_adox_RAX_RBX_icebp
936 adox rax, rbx
937.again:
938 icebp
939 jmp .again
940BS3_PROC_END_CMN bs3CpuInstr2_adox_RAX_RBX_icebp
941 %endif
942
943BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_adox_EAX_dword_FSxBX_icebp
944 adox eax, dword [fs:xBX]
945.again:
946 icebp
947 jmp .again
948BS3_PROC_END_CMN bs3CpuInstr2_adox_EAX_dword_FSxBX_icebp
949
950 %if TMPL_BITS == 64
951BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_adox_RAX_qword_FSxBX_icebp
952 adox rax, qword [fs:xBX]
953.again:
954 icebp
955 jmp .again
956BS3_PROC_END_CMN bs3CpuInstr2_adox_RAX_qword_FSxBX_icebp
957 %endif
958
959
960;
961; MOVBE
962;
963BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_movbe_AX_word_FSxBX_icebp
964 movbe ax, word [fs:xBX]
965.again:
966 icebp
967 jmp .again
968BS3_PROC_END_CMN bs3CpuInstr2_movbe_AX_word_FSxBX_icebp
969
970BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_movbe_word_FSxBX_AX_icebp
971 movbe word [fs:xBX], ax
972.again:
973 icebp
974 jmp .again
975BS3_PROC_END_CMN bs3CpuInstr2_movbe_word_FSxBX_AX_icebp
976
977BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_movbe_EAX_dword_FSxBX_icebp
978 movbe eax, dword [fs:xBX]
979.again:
980 icebp
981 jmp .again
982BS3_PROC_END_CMN bs3CpuInstr2_movbe_EAX_dword_FSxBX_icebp
983
984BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_movbe_dword_FSxBX_EAX_icebp
985 movbe dword [fs:xBX], eax
986.again:
987 icebp
988 jmp .again
989BS3_PROC_END_CMN bs3CpuInstr2_movbe_dword_FSxBX_EAX_icebp
990
991 %if TMPL_BITS == 64
992BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_movbe_RAX_qword_FSxBX_icebp
993 movbe rax, qword [fs:xBX]
994.again:
995 icebp
996 jmp .again
997BS3_PROC_END_CMN bs3CpuInstr2_movbe_RAX_qword_FSxBX_icebp
998
999BS3CPUINSTR2_PROC_BEGIN_CMN bs3CpuInstr2_movbe_qword_FSxBX_RAX_icebp
1000 movbe qword [fs:xBX], rax
1001.again:
1002 icebp
1003 jmp .again
1004BS3_PROC_END_CMN bs3CpuInstr2_movbe_qword_FSxBX_RAX_icebp
1005 %endif
1006
1007
1008;
1009; CMPXCHG8B
1010;
1011BS3_PROC_BEGIN_CMN bs3CpuInstr2_cmpxchg8b_FSxDI_icebp, BS3_PBC_NEAR
1012 cmpxchg8b [fs:xDI]
1013.again:
1014 icebp
1015 jmp .again
1016BS3_PROC_END_CMN bs3CpuInstr2_cmpxchg8b_FSxDI_icebp
1017
1018BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_cmpxchg8b_FSxDI_icebp, BS3_PBC_NEAR
1019 lock cmpxchg8b [fs:xDI]
1020.again:
1021 icebp
1022 jmp .again
1023BS3_PROC_END_CMN bs3CpuInstr2_lock_cmpxchg8b_FSxDI_icebp
1024
1025BS3_PROC_BEGIN_CMN bs3CpuInstr2_o16_cmpxchg8b_FSxDI_icebp, BS3_PBC_NEAR
1026 o16 cmpxchg8b [fs:xDI]
1027.again:
1028 icebp
1029 jmp .again
1030BS3_PROC_END_CMN bs3CpuInstr2_o16_cmpxchg8b_FSxDI_icebp
1031
1032BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_o16_cmpxchg8b_FSxDI_icebp, BS3_PBC_NEAR
1033 db 0f0h, 066h
1034 cmpxchg8b [fs:xDI]
1035.again:
1036 icebp
1037 jmp .again
1038BS3_PROC_END_CMN bs3CpuInstr2_lock_o16_cmpxchg8b_FSxDI_icebp
1039
1040BS3_PROC_BEGIN_CMN bs3CpuInstr2_repz_cmpxchg8b_FSxDI_icebp, BS3_PBC_NEAR
1041 repz cmpxchg8b [fs:xDI]
1042.again:
1043 icebp
1044 jmp .again
1045BS3_PROC_END_CMN bs3CpuInstr2_repz_cmpxchg8b_FSxDI_icebp
1046
1047BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_repz_cmpxchg8b_FSxDI_icebp, BS3_PBC_NEAR
1048 db 0f0h, 0f3h
1049 cmpxchg8b [fs:xDI]
1050.again:
1051 icebp
1052 jmp .again
1053BS3_PROC_END_CMN bs3CpuInstr2_lock_repz_cmpxchg8b_FSxDI_icebp
1054
1055BS3_PROC_BEGIN_CMN bs3CpuInstr2_repnz_cmpxchg8b_FSxDI_icebp, BS3_PBC_NEAR
1056 repnz cmpxchg8b [fs:xDI]
1057.again:
1058 icebp
1059 jmp .again
1060BS3_PROC_END_CMN bs3CpuInstr2_repnz_cmpxchg8b_FSxDI_icebp
1061
1062BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_repnz_cmpxchg8b_FSxDI_icebp, BS3_PBC_NEAR
1063 db 0f0h, 0f2h
1064 cmpxchg8b [fs:xDI]
1065.again:
1066 icebp
1067 jmp .again
1068BS3_PROC_END_CMN bs3CpuInstr2_lock_repnz_cmpxchg8b_FSxDI_icebp
1069
1070
1071;
1072; CMPXCHG16B
1073;
1074 %if TMPL_BITS == 64
1075BS3_PROC_BEGIN_CMN bs3CpuInstr2_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
1076 cmpxchg16b [rdi]
1077.again:
1078 ud2
1079 jmp .again
1080AssertCompile(.again - BS3_LAST_LABEL == 4)
1081BS3_PROC_END_CMN bs3CpuInstr2_cmpxchg16b_rdi_ud2
1082
1083
1084BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
1085 lock cmpxchg16b [rdi]
1086.again:
1087 ud2
1088 jmp .again
1089AssertCompile(.again - BS3_LAST_LABEL == 5)
1090BS3_PROC_END_CMN bs3CpuInstr2_lock_cmpxchg16b_rdi_ud2
1091
1092
1093BS3_PROC_BEGIN_CMN bs3CpuInstr2_o16_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
1094 o16 cmpxchg16b [rdi]
1095.again:
1096 ud2
1097 jmp .again
1098AssertCompile(.again - BS3_LAST_LABEL == 5)
1099BS3_PROC_END_CMN bs3CpuInstr2_o16_cmpxchg16b_rdi_ud2
1100
1101
1102BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_o16_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
1103 db 0f0h, 066h
1104 cmpxchg16b [rdi]
1105.again:
1106 ud2
1107 jmp .again
1108AssertCompile(.again - BS3_LAST_LABEL == 6)
1109BS3_PROC_END_CMN bs3CpuInstr2_lock_o16_cmpxchg16b_rdi_ud2
1110
1111
1112BS3_PROC_BEGIN_CMN bs3CpuInstr2_repz_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
1113 repz cmpxchg16b [rdi]
1114.again:
1115 ud2
1116 jmp .again
1117AssertCompile(.again - BS3_LAST_LABEL == 5)
1118BS3_PROC_END_CMN bs3CpuInstr2_repz_cmpxchg16b_rdi_ud2
1119
1120
1121BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_repz_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
1122 db 0f0h, 0f3h
1123 cmpxchg16b [rdi]
1124.again:
1125 ud2
1126 jmp .again
1127AssertCompile(.again - BS3_LAST_LABEL == 6)
1128BS3_PROC_END_CMN bs3CpuInstr2_lock_repz_cmpxchg16b_rdi_ud2
1129
1130BS3_PROC_BEGIN_CMN bs3CpuInstr2_repnz_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
1131 repnz cmpxchg16b [rdi]
1132.again:
1133 ud2
1134 jmp .again
1135AssertCompile(.again - BS3_LAST_LABEL == 5)
1136BS3_PROC_END_CMN bs3CpuInstr2_repnz_cmpxchg16b_rdi_ud2
1137
1138
1139BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_repnz_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
1140 db 0f0h, 0f2h
1141 cmpxchg16b [rdi]
1142.again:
1143 ud2
1144 jmp .again
1145AssertCompile(.again - BS3_LAST_LABEL == 6)
1146BS3_PROC_END_CMN bs3CpuInstr2_lock_repnz_cmpxchg16b_rdi_ud2
1147
1148
1149BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrfsbase_rbx_ud2, BS3_PBC_NEAR
1150 wrfsbase rbx
1151.again:
1152 ud2
1153 jmp .again
1154AssertCompile(.again - BS3_LAST_LABEL == 5)
1155BS3_PROC_END_CMN bs3CpuInstr2_wrfsbase_rbx_ud2
1156
1157
1158BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrfsbase_ebx_ud2, BS3_PBC_NEAR
1159 wrfsbase ebx
1160.again:
1161 ud2
1162 jmp .again
1163AssertCompile(.again - BS3_LAST_LABEL == 4)
1164BS3_PROC_END_CMN bs3CpuInstr2_wrfsbase_ebx_ud2
1165
1166
1167BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrgsbase_rbx_ud2, BS3_PBC_NEAR
1168 wrgsbase rbx
1169.again:
1170 ud2
1171 jmp .again
1172AssertCompile(.again - BS3_LAST_LABEL == 5)
1173BS3_PROC_END_CMN bs3CpuInstr2_wrgsbase_rbx_ud2
1174
1175
1176BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrgsbase_ebx_ud2, BS3_PBC_NEAR
1177 wrgsbase ebx
1178.again:
1179 ud2
1180 jmp .again
1181AssertCompile(.again - BS3_LAST_LABEL == 4)
1182BS3_PROC_END_CMN bs3CpuInstr2_wrgsbase_ebx_ud2
1183
1184
1185BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrfsbase_rbx_rdfsbase_rcx_ud2, BS3_PBC_NEAR
1186 wrfsbase rbx
1187 mov ebx, 0
1188 rdfsbase rcx
1189.again:
1190 ud2
1191 jmp .again
1192AssertCompile(.again - BS3_LAST_LABEL == 15)
1193BS3_PROC_END_CMN bs3CpuInstr2_wrfsbase_rbx_rdfsbase_rcx_ud2
1194
1195
1196BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrfsbase_ebx_rdfsbase_ecx_ud2, BS3_PBC_NEAR
1197 wrfsbase ebx
1198 mov ebx, 0
1199 rdfsbase ecx
1200.again:
1201 ud2
1202 jmp .again
1203AssertCompile(.again - BS3_LAST_LABEL == 13)
1204BS3_PROC_END_CMN bs3CpuInstr2_wrfsbase_ebx_rdfsbase_ecx_ud2
1205
1206
1207BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrgsbase_rbx_rdgsbase_rcx_ud2, BS3_PBC_NEAR
1208 wrgsbase rbx
1209 mov ebx, 0
1210 rdgsbase rcx
1211.again:
1212 ud2
1213 jmp .again
1214AssertCompile(.again - BS3_LAST_LABEL == 15)
1215BS3_PROC_END_CMN bs3CpuInstr2_wrgsbase_rbx_rdgsbase_rcx_ud2
1216
1217
1218BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrgsbase_ebx_rdgsbase_ecx_ud2, BS3_PBC_NEAR
1219 wrgsbase ebx
1220 mov ebx, 0
1221 rdgsbase ecx
1222.again:
1223 ud2
1224 jmp .again
1225AssertCompile(.again - BS3_LAST_LABEL == 13)
1226BS3_PROC_END_CMN bs3CpuInstr2_wrfgbase_ebx_rdgsbase_ecx_ud2
1227
1228
1229BS3_PROC_BEGIN_CMN bs3CpuInstr2_rdfsbase_rbx_ud2, BS3_PBC_NEAR
1230 rdfsbase rbx
1231.again:
1232 ud2
1233 jmp .again
1234AssertCompile(.again - BS3_LAST_LABEL == 5)
1235BS3_PROC_END_CMN bs3CpuInstr2_rdfsbase_rbx_ud2
1236
1237
1238BS3_PROC_BEGIN_CMN bs3CpuInstr2_rdfsbase_ebx_ud2, BS3_PBC_NEAR
1239 rdfsbase ebx
1240.again:
1241 ud2
1242 jmp .again
1243AssertCompile(.again - BS3_LAST_LABEL == 4)
1244BS3_PROC_END_CMN bs3CpuInstr2_rdfsbase_ebx_ud2
1245
1246
1247BS3_PROC_BEGIN_CMN bs3CpuInstr2_rdgsbase_rbx_ud2, BS3_PBC_NEAR
1248 rdgsbase rbx
1249.again:
1250 ud2
1251 jmp .again
1252AssertCompile(.again - BS3_LAST_LABEL == 5)
1253BS3_PROC_END_CMN bs3CpuInstr2_rdgsbase_rbx_ud2
1254
1255
1256BS3_PROC_BEGIN_CMN bs3CpuInstr2_rdgsbase_ebx_ud2, BS3_PBC_NEAR
1257 rdgsbase ebx
1258.again:
1259 ud2
1260 jmp .again
1261AssertCompile(.again - BS3_LAST_LABEL == 4)
1262BS3_PROC_END_CMN bs3CpuInstr2_rdgsbase_ebx_ud2
1263
1264
1265;; @todo figure out this fudge. sigh.
1266times (348) db 0cch ; fudge to avoid 'rderr' during boot.
1267
1268 %endif ; TMPL_BITS == 64
1269
1270
1271%endif ; BS3_INSTANTIATING_CMN
1272
1273%include "bs3kit-template-footer.mac" ; reset environment
1274
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