bs3-cpu-basic-2-template.mac@ 97576

最後變更在這個檔案從97576是 97518,由 vboxsync 提交於 2 年前
ValKit/bs3-cpu-basic-2: Some assembly cleanups. bugref:9898
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1	; $Id: bs3-cpu-basic-2-template.mac 97518 2022-11-11 23:23:43Z vboxsync $
2	;; @file
3	; BS3Kit - bs3-cpu-basic-2 assembly template.
4	;
5
6	;
7	; Copyright (C) 2007-2022 Oracle and/or its affiliates.
8	;
9	; This file is part of VirtualBox base platform packages, as
10	; available from https://www.alldomusa.eu.org.
11	;
12	; This program is free software; you can redistribute it and/or
13	; modify it under the terms of the GNU General Public License
14	; as published by the Free Software Foundation, in version 3 of the
15	; License.
16	;
17	; This program is distributed in the hope that it will be useful, but
18	; WITHOUT ANY WARRANTY; without even the implied warranty of
19	; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	; General Public License for more details.
21	;
22	; You should have received a copy of the GNU General Public License
23	; along with this program; if not, see <https://www.gnu.org/licenses>.
24	;
25	; The contents of this file may alternatively be used under the terms
26	; of the Common Development and Distribution License Version 1.0
27	; (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
28	; in the VirtualBox distribution, in which case the provisions of the
29	; CDDL are applicable instead of those of the GPL.
30	;
31	; You may elect to license modified versions of this file under the
32	; terms and conditions of either the GPL or the CDDL or both.
33	;
34	; SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
35	;
36
37
38	;*********************************************************************************************************************************
39	;* Header Files *
40	;*********************************************************************************************************************************
41	%include "bs3kit-template-header.mac" ; setup environment
42
43
44	;*********************************************************************************************************************************
45	;* Defined Constants And Macros *
46	;*********************************************************************************************************************************
47	%ifnmacro BS3_CPUBAS2_UD_OFF
48	%macro BS3_CPUBAS2_UD_OFF 1
49	BS3_GLOBAL_NAME_EX BS3_CMN_NM(%1) %+ _offUD, , 1
50	db BS3_CMN_NM(%1).again - BS3_CMN_NM(%1)
51	%endmacro
52	%endif
53
54	%undef BS3_CPUBAS2_REF_LABEL_VIA_CS
55	%if TMPL_BITS == 16
56	%define BS3_CPUBAS2_REF_LABEL_VIA_CS(a_Label) cs:a_Label
57	%elif TMPL_BITS == 32
58	%define BS3_CPUBAS2_REF_LABEL_VIA_CS(a_Label) cs:a_Label wrt FLAT
59	%elif TMPL_BITS == 64
60	%define BS3_CPUBAS2_REF_LABEL_VIA_CS(a_Label) a_Label wrt FLAT
61	%else
62	%error TMPL_BITS
63	%endif
64
65	;;
66	; Macro for generating far jmp instruction w/o nasm adding REX.W prefixes.
67	;
68	; @param 1 The label of the memory pointer.
69	; @param 2 Prefix: 0: none, 1: 066h, 2: REX.W, 3: 066h REX.W
70	%ifnmacro BS3_CPUBAS2_JMP_FAR_MEM_LABEL
71	%macro BS3_CPUBAS2_JMP_FAR_MEM_LABEL 2
72	%if (%2) == 1 \|\| (%2) == 3
73	db 066h ; o16/o32
74	%endif
75	%if TMPL_BITS != 64
76	jmp far [BS3_CPUBAS2_REF_LABEL_VIA_CS(%1)]
77	%elif TMPL_BITS == 64
78	; 48FF2C25[040C0000] <3> jmp far [BS3_CPUBAS2_REF_LABLE_VIA_CS(.fpfn)]
79	%if (%2) == 2 \|\| (%2) == 3
80	db 048h ; REX.W
81	%endif
82	db 0ffh, 02ch, 025h
83	dd %1 wrt FLAT
84	%else
85	%error TMPL_BITS
86	%endif
87	%endmacro
88	%endif
89
90	;;
91	; Macro for generating far call instruction w/o nasm adding REX.W prefixes.
92	;
93	; @param 1 The label of the memory pointer.
94	; @param 2 Prefix: 0: none, 1: 066h, 2: REX.W, 3: 066h REX.W
95	%ifnmacro BS3_CPUBAS2_CALL_FAR_MEM_LABEL
96	%macro BS3_CPUBAS2_CALL_FAR_MEM_LABEL 2
97	%if (%2) == 1 \|\| (%2) == 3
98	db 066h ; o16/o32
99	%endif
100	%if TMPL_BITS != 64
101	call far [BS3_CPUBAS2_REF_LABEL_VIA_CS(%1)]
102	%elif TMPL_BITS == 64
103	%if (%2) == 2 \|\| (%2) == 3
104	db 048h ; REX.W
105	%endif
106	db 0ffh, 01ch, 025h ; call far [mem]
107	dd %1 wrt FLAT
108	%else
109	%error TMPL_BITS
110	%endif
111	%endmacro
112	%endif
113
114
115	;*********************************************************************************************************************************
116	;* External Symbols *
117	;*********************************************************************************************************************************
118	TMPL_BEGIN_TEXT
119
120
121
122	;
123	; Test code snippets containing code which differs between 16-bit, 32-bit
124	; and 64-bit CPUs modes.
125	;
126	%ifdef BS3_INSTANTIATING_CMN
127
128	;
129	; SIDT
130	;
131	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_sidt_bx_ud2
132	BS3_PROC_BEGIN_CMN bs3CpuBasic2_sidt_bx_ud2, BS3_PBC_NEAR
133	sidt [xBX]
134	.again: ud2
135	jmp .again
136	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_sidt_bx_ud2) == 3)
137	BS3_PROC_END_CMN bs3CpuBasic2_sidt_bx_ud2
138
139	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_sidt_opsize_bx_ud2
140	BS3_PROC_BEGIN_CMN bs3CpuBasic2_sidt_opsize_bx_ud2, BS3_PBC_NEAR
141	db X86_OP_PRF_SIZE_OP
142	sidt [xBX]
143	.again: ud2
144	jmp .again
145	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_sidt_opsize_bx_ud2) == 4)
146	BS3_PROC_END_CMN bs3CpuBasic2_sidt_opsize_bx_ud2
147
148	%if TMPL_BITS == 64
149	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_sidt_rexw_bx_ud2
150	BS3_PROC_BEGIN_CMN bs3CpuBasic2_sidt_rexw_bx_ud2, BS3_PBC_NEAR
151	db X86_OP_REX_W
152	sidt [xBX]
153	.again: ud2
154	jmp .again
155	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_sidt_rexw_bx_ud2) == 4)
156	BS3_PROC_END_CMN bs3CpuBasic2_sidt_rexw_bx_ud2
157
158	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_sidt_opsize_rexw_bx_ud2
159	BS3_PROC_BEGIN_CMN bs3CpuBasic2_sidt_opsize_rexw_bx_ud2, BS3_PBC_NEAR
160	db X86_OP_PRF_SIZE_OP
161	db X86_OP_REX_W
162	sidt [xBX]
163	.again: ud2
164	jmp .again
165	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_sidt_opsize_rexw_bx_ud2) == 5)
166	BS3_PROC_END_CMN bs3CpuBasic2_sidt_opsize_rexw_bx_ud2
167	%endif
168
169	%if TMPL_BITS != 64
170	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_sidt_ss_bx_ud2
171	BS3_PROC_BEGIN_CMN bs3CpuBasic2_sidt_ss_bx_ud2, BS3_PBC_NEAR
172	sidt [ss:xBX]
173	.again: ud2
174	jmp .again
175	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_sidt_ss_bx_ud2) == 4)
176	BS3_PROC_END_CMN bs3CpuBasic2_sidt_ss_bx_ud2
177
178	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_sidt_opsize_ss_bx_ud2
179	BS3_PROC_BEGIN_CMN bs3CpuBasic2_sidt_opsize_ss_bx_ud2, BS3_PBC_NEAR
180	db X86_OP_PRF_SIZE_OP
181	sidt [ss:xBX]
182	.again: ud2
183	jmp .again
184	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_sidt_opsize_ss_bx_ud2) == 5)
185	BS3_PROC_END_CMN bs3CpuBasic2_sidt_opsize_ss_bx_ud2
186	%endif
187
188
189	;
190	; SGDT
191	;
192	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_sgdt_bx_ud2
193	BS3_PROC_BEGIN_CMN bs3CpuBasic2_sgdt_bx_ud2, BS3_PBC_NEAR
194	sgdt [xBX]
195	.again: ud2
196	jmp .again
197	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_sgdt_bx_ud2) == 3)
198	BS3_PROC_END_CMN bs3CpuBasic2_sgdt_bx_ud2
199
200	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_sgdt_opsize_bx_ud2
201	BS3_PROC_BEGIN_CMN bs3CpuBasic2_sgdt_opsize_bx_ud2, BS3_PBC_NEAR
202	db X86_OP_PRF_SIZE_OP
203	sgdt [xBX]
204	.again: ud2
205	jmp .again
206	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_sgdt_opsize_bx_ud2) == 4)
207	BS3_PROC_END_CMN bs3CpuBasic2_sgdt_opsize_bx_ud2
208
209	%if TMPL_BITS == 64
210	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_sgdt_rexw_bx_ud2
211	BS3_PROC_BEGIN_CMN bs3CpuBasic2_sgdt_rexw_bx_ud2, BS3_PBC_NEAR
212	db X86_OP_REX_W
213	sgdt [xBX]
214	.again: ud2
215	jmp .again
216	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_sgdt_rexw_bx_ud2) == 4)
217	BS3_PROC_END_CMN bs3CpuBasic2_sgdt_rexw_bx_ud2
218
219	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_sgdt_opsize_rexw_bx_ud2
220	BS3_PROC_BEGIN_CMN bs3CpuBasic2_sgdt_opsize_rexw_bx_ud2, BS3_PBC_NEAR
221	db X86_OP_PRF_SIZE_OP
222	db X86_OP_REX_W
223	sgdt [xBX]
224	.again: ud2
225	jmp .again
226	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_sgdt_opsize_rexw_bx_ud2) == 5)
227	BS3_PROC_END_CMN bs3CpuBasic2_sgdt_opsize_rexw_bx_ud2
228	%endif
229
230	%if TMPL_BITS != 64
231	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_sgdt_ss_bx_ud2
232	BS3_PROC_BEGIN_CMN bs3CpuBasic2_sgdt_ss_bx_ud2, BS3_PBC_NEAR
233	sgdt [ss:xBX]
234	.again: ud2
235	jmp .again
236	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_sgdt_ss_bx_ud2) == 4)
237	BS3_PROC_END_CMN bs3CpuBasic2_sgdt_ss_bx_ud2
238
239	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_sgdt_opsize_ss_bx_ud2
240	BS3_PROC_BEGIN_CMN bs3CpuBasic2_sgdt_opsize_ss_bx_ud2, BS3_PBC_NEAR
241	db X86_OP_PRF_SIZE_OP
242	sgdt [ss:xBX]
243	.again: ud2
244	jmp .again
245	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_sgdt_opsize_ss_bx_ud2) == 5)
246	BS3_PROC_END_CMN bs3CpuBasic2_sgdt_opsize_ss_bx_ud2
247	%endif
248
249
250	;
251	; LIDT
252	;
253	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_lidt_bx__sidt_es_di__lidt_es_si__ud2
254	BS3_PROC_BEGIN_CMN bs3CpuBasic2_lidt_bx__sidt_es_di__lidt_es_si__ud2, BS3_PBC_NEAR
255	lidt [xBX]
256	sidt [BS3_NOT_64BIT(es:) xDI]
257	lidt [BS3_NOT_64BIT(es:) xSI]
258	.again:
259	ud2
260	jmp .again
261	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_lidt_bx__sidt_es_di__lidt_es_si__ud2) == BS3_IF_64BIT_OTHERWISE(9,11))
262	BS3_PROC_END_CMN bs3CpuBasic2_lidt_bx__sidt_es_di__lidt_es_si__ud2
263
264	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_lidt_opsize_bx__sidt_es_di__lidt_es_si__ud2
265	BS3_PROC_BEGIN_CMN bs3CpuBasic2_lidt_opsize_bx__sidt_es_di__lidt_es_si__ud2, BS3_PBC_NEAR
266	db X86_OP_PRF_SIZE_OP
267	lidt [xBX]
268	sidt [BS3_NOT_64BIT(es:) xDI]
269	lidt [BS3_NOT_64BIT(es:) xSI]
270	.again:
271	ud2
272	jmp .again
273	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_lidt_opsize_bx__sidt_es_di__lidt_es_si__ud2) == BS3_IF_64BIT_OTHERWISE(10,12))
274	BS3_PROC_END_CMN bs3CpuBasic2_lidt_opsize_bx__sidt_es_di__lidt_es_si__ud2
275
276	%if TMPL_BITS == 16
277	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_lidt_opsize_bx__sidt32_es_di__lidt_es_si__ud2
278	BS3_PROC_BEGIN_CMN bs3CpuBasic2_lidt_opsize_bx__sidt32_es_di__lidt_es_si__ud2, BS3_PBC_NEAR
279	db X86_OP_PRF_SIZE_OP
280	lidt [xBX]
281	jmp dword BS3_SEL_R0_CS32:.in_32bit wrt FLAT
282	BS3_SET_BITS 32
283	.in_32bit:
284	sidt [es:edi]
285	lidt [es:esi]
286	jmp dword BS3_SEL_R0_CS16:.again wrt CGROUP16
287	BS3_SET_BITS 16
288	.again:
289	ud2
290	jmp .again
291	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_lidt_opsize_bx__sidt32_es_di__lidt_es_si__ud2) == 27)
292	BS3_PROC_END_CMN bs3CpuBasic2_lidt_opsize_bx__sidt32_es_di__lidt_es_si__ud2
293	%endif
294
295	%if TMPL_BITS == 64
296	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_lidt_rexw_bx__sidt_es_di__lidt_es_si__ud2
297	BS3_PROC_BEGIN_CMN bs3CpuBasic2_lidt_rexw_bx__sidt_es_di__lidt_es_si__ud2, BS3_PBC_NEAR
298	db X86_OP_REX_W
299	lidt [xBX]
300	sidt [xDI]
301	lidt [xSI]
302	.again:
303	ud2
304	jmp .again
305	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_lidt_rexw_bx__sidt_es_di__lidt_es_si__ud2) == 10)
306	BS3_PROC_END_CMN bs3CpuBasic2_lidt_rexw_bx__sidt_es_di__lidt_es_si__ud2
307
308	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_lidt_opsize_rexw_bx__sidt_es_di__lidt_es_si__ud2
309	BS3_PROC_BEGIN_CMN bs3CpuBasic2_lidt_opsize_rexw_bx__sidt_es_di__lidt_es_si__ud2, BS3_PBC_NEAR
310	db X86_OP_PRF_SIZE_OP
311	db X86_OP_REX_W
312	lidt [xBX]
313	sidt [xDI]
314	lidt [xSI]
315	.again:
316	ud2
317	jmp .again
318	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_lidt_opsize_rexw_bx__sidt_es_di__lidt_es_si__ud2) == 11)
319	BS3_PROC_END_CMN bs3CpuBasic2_lidt_opsize_rexw_bx__sidt_es_di__lidt_es_si__ud2
320	%endif
321
322	%if TMPL_BITS != 64
323	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_lidt_ss_bx__sidt_es_di__lidt_es_si__ud2
324	BS3_PROC_BEGIN_CMN bs3CpuBasic2_lidt_ss_bx__sidt_es_di__lidt_es_si__ud2, BS3_PBC_NEAR
325	lidt [ss:xBX]
326	sidt [BS3_NOT_64BIT(es:) xDI]
327	lidt [BS3_NOT_64BIT(es:) xSI]
328	.again:
329	ud2
330	jmp .again
331	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_lidt_ss_bx__sidt_es_di__lidt_es_si__ud2) == 12)
332	BS3_PROC_END_CMN bs3CpuBasic2_lidt_ss_bx__sidt_es_di__lidt_es_si__ud2
333
334	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_lidt_opsize_ss_bx__sidt_es_di__lidt_es_si__ud2
335	BS3_PROC_BEGIN_CMN bs3CpuBasic2_lidt_opsize_ss_bx__sidt_es_di__lidt_es_si__ud2, BS3_PBC_NEAR
336	db X86_OP_PRF_SIZE_OP
337	lidt [ss:xBX]
338	sidt [BS3_NOT_64BIT(es:) xDI]
339	lidt [BS3_NOT_64BIT(es:) xSI]
340	.again:
341	ud2
342	jmp .again
343	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_lidt_opsize_ss_bx__sidt_es_di__lidt_es_si__ud2) == 13)
344	BS3_PROC_END_CMN bs3CpuBasic2_lidt_opsize_ss_bx__sidt_es_di__lidt_es_si__ud2
345	%endif
346
347
348	;
349	; LGDT
350	;
351	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_lgdt_bx__sgdt_es_di__lgdt_es_si__ud2
352	BS3_PROC_BEGIN_CMN bs3CpuBasic2_lgdt_bx__sgdt_es_di__lgdt_es_si__ud2, BS3_PBC_NEAR
353	lgdt [xBX]
354	sgdt [BS3_NOT_64BIT(es:) xDI]
355	lgdt [BS3_NOT_64BIT(es:) xSI]
356	.again:
357	ud2
358	jmp .again
359	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_lgdt_bx__sgdt_es_di__lgdt_es_si__ud2) == BS3_IF_64BIT_OTHERWISE(9,11))
360	BS3_PROC_END_CMN bs3CpuBasic2_lgdt_bx__sgdt_es_di__lgdt_es_si__ud2
361
362	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_lgdt_opsize_bx__sgdt_es_di__lgdt_es_si__ud2
363	BS3_PROC_BEGIN_CMN bs3CpuBasic2_lgdt_opsize_bx__sgdt_es_di__lgdt_es_si__ud2, BS3_PBC_NEAR
364	db X86_OP_PRF_SIZE_OP
365	lgdt [xBX]
366	sgdt [BS3_NOT_64BIT(es:) xDI]
367	lgdt [BS3_NOT_64BIT(es:) xSI]
368	.again:
369	ud2
370	jmp .again
371	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_lgdt_opsize_bx__sgdt_es_di__lgdt_es_si__ud2) == BS3_IF_64BIT_OTHERWISE(10,12))
372	BS3_PROC_END_CMN bs3CpuBasic2_lgdt_opsize_bx__sgdt_es_di__lgdt_es_si__ud2
373
374	%if TMPL_BITS == 64
375	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_lgdt_rexw_bx__sgdt_es_di__lgdt_es_si__ud2
376	BS3_PROC_BEGIN_CMN bs3CpuBasic2_lgdt_rexw_bx__sgdt_es_di__lgdt_es_si__ud2, BS3_PBC_NEAR
377	db X86_OP_REX_W
378	lgdt [xBX]
379	sgdt [xDI]
380	lgdt [xSI]
381	.again:
382	ud2
383	jmp .again
384	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_lgdt_rexw_bx__sgdt_es_di__lgdt_es_si__ud2) == 10)
385	BS3_PROC_END_CMN bs3CpuBasic2_lgdt_rexw_bx__sgdt_es_di__lgdt_es_si__ud2
386
387	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_lgdt_opsize_rexw_bx__sgdt_es_di__lgdt_es_si__ud2
388	BS3_PROC_BEGIN_CMN bs3CpuBasic2_lgdt_opsize_rexw_bx__sgdt_es_di__lgdt_es_si__ud2, BS3_PBC_NEAR
389	db X86_OP_PRF_SIZE_OP
390	db X86_OP_REX_W
391	lgdt [xBX]
392	sgdt [xDI]
393	lgdt [xSI]
394	.again:
395	ud2
396	jmp .again
397	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_lgdt_opsize_rexw_bx__sgdt_es_di__lgdt_es_si__ud2) == 11)
398	BS3_PROC_END_CMN bs3CpuBasic2_lgdt_opsize_rexw_bx__sgdt_es_di__lgdt_es_si__ud2
399	%endif
400
401	%if TMPL_BITS != 64
402	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_lgdt_ss_bx__sgdt_es_di__lgdt_es_si__ud2
403	BS3_PROC_BEGIN_CMN bs3CpuBasic2_lgdt_ss_bx__sgdt_es_di__lgdt_es_si__ud2, BS3_PBC_NEAR
404	lgdt [ss:xBX]
405	sgdt [BS3_NOT_64BIT(es:) xDI]
406	lgdt [BS3_NOT_64BIT(es:) xSI]
407	.again:
408	ud2
409	jmp .again
410	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_lgdt_ss_bx__sgdt_es_di__lgdt_es_si__ud2) == 12)
411	BS3_PROC_END_CMN bs3CpuBasic2_lgdt_ss_bx__sgdt_es_di__lgdt_es_si__ud2
412
413	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_lgdt_opsize_ss_bx__sgdt_es_di__lgdt_es_si__ud2
414	BS3_PROC_BEGIN_CMN bs3CpuBasic2_lgdt_opsize_ss_bx__sgdt_es_di__lgdt_es_si__ud2, BS3_PBC_NEAR
415	db X86_OP_PRF_SIZE_OP
416	lgdt [ss:xBX]
417	sgdt [BS3_NOT_64BIT(es:) xDI]
418	lgdt [BS3_NOT_64BIT(es:) xSI]
419	.again:
420	ud2
421	jmp .again
422	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_lgdt_opsize_ss_bx__sgdt_es_di__lgdt_es_si__ud2) == 13)
423	BS3_PROC_END_CMN bs3CpuBasic2_lgdt_opsize_ss_bx__sgdt_es_di__lgdt_es_si__ud2
424	%endif ; TMPL_BITS != 64
425
426	;
427	; #PF & #AC
428	;
429
430	; For testing read access.
431	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_mov_ax_ds_bx__ud2
432	BS3_PROC_BEGIN_CMN bs3CpuBasic2_mov_ax_ds_bx__ud2, BS3_PBC_NEAR
433	mov xAX, [xBX]
434	.again: ud2
435	jmp .again
436	AssertCompile(.again - BS3_LAST_LABEL == 2 + (TMPL_BITS == 64))
437	BS3_PROC_END_CMN bs3CpuBasic2_mov_ax_ds_bx__ud2
438
439
440	; For testing write access.
441	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_mov_ds_bx_ax__ud2
442	BS3_PROC_BEGIN_CMN bs3CpuBasic2_mov_ds_bx_ax__ud2, BS3_PBC_NEAR
443	mov [xBX], xAX
444	.again: ud2
445	jmp .again
446	AssertCompile(.again - BS3_LAST_LABEL == 2 + (TMPL_BITS == 64))
447	BS3_PROC_END_CMN bs3CpuBasic2_mov_ds_bx_ax__ud2
448
449
450	; For testing read+write access.
451	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_xchg_ds_bx_ax__ud2
452	BS3_PROC_BEGIN_CMN bs3CpuBasic2_xchg_ds_bx_ax__ud2, BS3_PBC_NEAR
453	xchg [xBX], xAX
454	.again: ud2
455	jmp .again
456	AssertCompile(.again - BS3_LAST_LABEL == 2 + (TMPL_BITS == 64))
457	BS3_PROC_END_CMN bs3CpuBasic2_xchg_ds_bx_ax__ud2
458
459
460	; Another read+write access test.
461	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_cmpxchg_ds_bx_cx__ud2
462	BS3_PROC_BEGIN_CMN bs3CpuBasic2_cmpxchg_ds_bx_cx__ud2, BS3_PBC_NEAR
463	cmpxchg [xBX], xCX
464	.again: ud2
465	jmp .again
466	AssertCompile(.again - BS3_LAST_LABEL == 3 + (TMPL_BITS == 64))
467	BS3_PROC_END_CMN bs3CpuBasic2_cmpxchg_ds_bx_cx__ud2
468
469
470	; For testing read access from an aborted instruction: DIV by zero
471	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_div_ds_bx__ud2
472	BS3_PROC_BEGIN_CMN bs3CpuBasic2_div_ds_bx__ud2, BS3_PBC_NEAR
473	div xPRE [xBX]
474	.again: ud2
475	jmp .again
476	AssertCompile(.again - BS3_LAST_LABEL == 2 + (TMPL_BITS == 64))
477	BS3_PROC_END_CMN bs3CpuBasic2_div_ds_bx__ud2
478
479	; For testing FLD m80 alignment (#AC).
480	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_fninit_fld_ds_bx__ud2
481	BS3_PROC_BEGIN_CMN bs3CpuBasic2_fninit_fld_ds_bx__ud2, BS3_PBC_NEAR
482	fninit ; make sure to not trigger a stack overflow.
483	.actual_test_instruction:
484	fld tword [xBX]
485	.again: ud2
486	jmp .again
487	AssertCompile(.actual_test_instruction - BS3_LAST_LABEL == 2)
488	BS3_PROC_END_CMN bs3CpuBasic2_fninit_fld_ds_bx__ud2
489
490	; For testing FBLD m80 alignment (#AC).
491	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_fninit_fbld_ds_bx__ud2
492	BS3_PROC_BEGIN_CMN bs3CpuBasic2_fninit_fbld_ds_bx__ud2, BS3_PBC_NEAR
493	fninit ; make sure to not trigger a stack overflow.
494	.actual_test_instruction:
495	fbld tword [xBX]
496	.again: ud2
497	jmp .again
498	AssertCompile(.actual_test_instruction - BS3_LAST_LABEL == 2)
499	BS3_PROC_END_CMN bs3CpuBasic2_fninit_fbld_ds_bx__ud2
500
501	; For testing FST m80 alignment (#AC).
502	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_fninit_fldz_fstp_ds_bx__ud2
503	BS3_PROC_BEGIN_CMN bs3CpuBasic2_fninit_fldz_fstp_ds_bx__ud2, BS3_PBC_NEAR
504	fninit ; make sure to not trigger a stack overflow.
505	fldz ; make sure we've got something to store
506	.actual_test_instruction:
507	fstp tword [xBX]
508	.again: ud2
509	jmp .again
510	AssertCompile(.actual_test_instruction - BS3_LAST_LABEL == 4)
511	BS3_PROC_END_CMN bs3CpuBasic2_fninit_fldz_fstp_ds_bx__ud2
512
513	; For testing FXSAVE alignment (#AC/#GP).
514	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_fxsave_ds_bx__ud2
515	BS3_PROC_BEGIN_CMN bs3CpuBasic2_fxsave_ds_bx__ud2, BS3_PBC_NEAR
516	fxsave [xBX]
517	.again: ud2
518	jmp .again
519	BS3_PROC_END_CMN bs3CpuBasic2_fxsave_ds_bx__ud2
520
521
522	; Two memory operands: push [mem]
523	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_push_ds_bx__ud2
524	BS3_PROC_BEGIN_CMN bs3CpuBasic2_push_ds_bx__ud2, BS3_PBC_NEAR
525	push xPRE [xBX]
526	.again: ud2
527	jmp .again
528	AssertCompile(.again - BS3_LAST_LABEL == 2)
529	BS3_PROC_END_CMN bs3CpuBasic2_push_ds_bx__ud2
530
531	; Two memory operands: pop [mem]
532	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_push_ax__pop_ds_bx__ud2
533	BS3_PROC_BEGIN_CMN bs3CpuBasic2_push_ax__pop_ds_bx__ud2, BS3_PBC_NEAR
534	push xAX
535	pop xPRE [xBX]
536	.again: ud2
537	jmp .again
538	AssertCompile(.again - BS3_LAST_LABEL == 3)
539	BS3_PROC_END_CMN bs3CpuBasic2_push_ax__pop_ds_bx__ud2
540
541	; Two memory operands: call [mem]
542	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_call_ds_bx__ud2
543	BS3_PROC_BEGIN_CMN bs3CpuBasic2_call_ds_bx__ud2, BS3_PBC_NEAR
544	call xPRE [xBX]
545	.again: ud2
546	jmp .again
547	AssertCompile(.again - BS3_LAST_LABEL == 2)
548	BS3_PROC_END_CMN bs3CpuBasic2_call_ds_bx__ud2
549
550	; For testing #GP vs #PF write
551	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_insb__ud2
552	BS3_PROC_BEGIN_CMN bs3CpuBasic2_insb__ud2, BS3_PBC_NEAR
553	insb
554	.again: ud2
555	jmp .again
556	AssertCompile(.again - BS3_LAST_LABEL == 1)
557	BS3_PROC_END_CMN bs3CpuBasic2_insb__ud2
558
559
560	;*********************************************************************************************************************************
561	;* Non-far JMP & CALL Tests (simple ones). *
562	;*********************************************************************************************************************************
563
564	; jmp rel8 (forwards)
565	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmp_jb__ud2
566	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmp_jb__ud2, BS3_PBC_NEAR
567	jmp short .again
568	.post_jmp:
569	times 7 int3
570	.again: ud2
571	int3
572	jmp .again
573	AssertCompile(.post_jmp - BS3_LAST_LABEL == 2)
574	BS3_PROC_END_CMN bs3CpuBasic2_jmp_jb__ud2
575
576
577	; jmp rel8 (backwards)
578	BS3_GLOBAL_NAME_EX RT_CONCAT(BS3_CMN_NM(bs3CpuBasic2_jmp_jb_back__ud2),.again), function, 2
579	ud2
580	times 7 int3
581	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmp_jb_back__ud2
582	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmp_jb_back__ud2, BS3_PBC_NEAR
583	jmp short .again
584	.post_jmp:
585	int3
586	AssertCompile(.post_jmp - BS3_LAST_LABEL == 2)
587	BS3_PROC_END_CMN bs3CpuBasic2_jmp_jb_back__ud2
588
589
590	; jmp rel16 (forwards)
591	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmp_jv__ud2
592	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmp_jv__ud2, BS3_PBC_NEAR
593	jmp near .again
594	.post_jmp:
595	times 9 int3
596	.again: ud2
597	int3
598	jmp .again
599	%if TMPL_BITS == 16
600	AssertCompile(.post_jmp - BS3_LAST_LABEL == 3)
601	%else
602	AssertCompile(.post_jmp - BS3_LAST_LABEL == 5)
603	%endif
604	BS3_PROC_END_CMN bs3CpuBasic2_jmp_jv__ud2
605
606
607	; jmp rel16 (backwards)
608	BS3_GLOBAL_NAME_EX RT_CONCAT(BS3_CMN_NM(bs3CpuBasic2_jmp_jv_back__ud2),.again), function, 2
609	ud2
610	times 6 int3
611	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmp_jv_back__ud2
612	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmp_jv_back__ud2, BS3_PBC_NEAR
613	jmp near .again
614	.post_jmp:
615	int3
616	%if TMPL_BITS == 16
617	AssertCompile(.post_jmp - BS3_LAST_LABEL == 3)
618	%else
619	AssertCompile(.post_jmp - BS3_LAST_LABEL == 5)
620	%endif
621	BS3_PROC_END_CMN bs3CpuBasic2_jmp_jv_back__ud2
622
623
624	; jmp [indirect]
625	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmp_ind_mem__ud2
626	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmp_ind_mem__ud2, BS3_PBC_NEAR
627	%if TMPL_BITS == 16
628	jmp [word cs:.npAgain]
629	%elif TMPL_BITS == 32
630	jmp [dword cs:.npAgain]
631	%else
632	jmp [.npAgain]
633	%endif
634	.post_jmp:
635	times 9 int3
636	.npAgain:
637	%if TMPL_BITS == 16
638	dw BS3_TEXT16_WRT(.again)
639	%else
640	dd .again wrt FLAT
641	%if TMPL_BITS == 64
642	dd 0
643	%endif
644	%endif
645	.again: ud2
646	int3
647	jmp .again
648	BS3_PROC_END_CMN bs3CpuBasic2_jmp_ind_mem__ud2
649
650	; jmp [xAX]
651	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmp_ind_xAX__ud2
652	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmp_ind_xAX__ud2, BS3_PBC_NEAR
653	jmp xAX
654	.post_jmp:
655	times 17 int3
656	.again: ud2
657	int3
658	jmp .again
659	BS3_PROC_END_CMN bs3CpuBasic2_jmp_ind_xAX__ud2
660
661	; jmp [xDI]
662	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmp_ind_xDI__ud2
663	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmp_ind_xDI__ud2, BS3_PBC_NEAR
664	jmp xDI
665	.post_jmp:
666	times 17 int3
667	.again: ud2
668	int3
669	jmp .again
670	BS3_PROC_END_CMN bs3CpuBasic2_jmp_ind_xDI__ud2
671
672	%if TMPL_BITS == 64
673	; jmp [xAX]
674	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmp_ind_r9__ud2
675	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmp_ind_r9__ud2, BS3_PBC_NEAR
676	jmp r9
677	.post_jmp:
678	times 17 int3
679	.again: ud2
680	int3
681	jmp .again
682	BS3_PROC_END_CMN bs3CpuBasic2_jmp_ind_r9__ud2
683	%endif
684
685
686	; call rel16/32 (forwards)
687	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_call_jv__ud2
688	BS3_PROC_BEGIN_CMN bs3CpuBasic2_call_jv__ud2, BS3_PBC_NEAR
689	call near .again
690	.post_call:
691	times 9 int3
692	.again: ud2
693	int3
694	jmp .again
695	%if TMPL_BITS == 16
696	AssertCompile(.post_call - BS3_LAST_LABEL == 3)
697	%else
698	AssertCompile(.post_call - BS3_LAST_LABEL == 5)
699	%endif
700	BS3_PROC_END_CMN bs3CpuBasic2_call_jv__ud2
701
702	; call rel16/32 (backwards)
703	BS3_GLOBAL_NAME_EX RT_CONCAT(BS3_CMN_NM(bs3CpuBasic2_call_jv_back__ud2),.again), function, 2
704	ud2
705	times 6 int3
706	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_call_jv_back__ud2
707	BS3_PROC_BEGIN_CMN bs3CpuBasic2_call_jv_back__ud2, BS3_PBC_NEAR
708	call near .again
709	.post_call:
710	int3
711	%if TMPL_BITS == 16
712	AssertCompile(.post_call - BS3_LAST_LABEL == 3)
713	%else
714	AssertCompile(.post_call - BS3_LAST_LABEL == 5)
715	%endif
716	BS3_PROC_END_CMN bs3CpuBasic2_call_jv_back__ud2
717
718	; call [indirect]
719	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_call_ind_mem__ud2
720	BS3_PROC_BEGIN_CMN bs3CpuBasic2_call_ind_mem__ud2, BS3_PBC_NEAR
721	%if TMPL_BITS == 16
722	call [word cs:.npAgain]
723	%elif TMPL_BITS == 32
724	call [dword cs:.npAgain]
725	%else
726	call [.npAgain]
727	%endif
728	.post_call:
729	times 9 int3
730	.npAgain:
731	%if TMPL_BITS == 16
732	dw BS3_TEXT16_WRT(.again)
733	%else
734	dd .again wrt FLAT
735	%if TMPL_BITS == 64
736	dd 0
737	%endif
738	%endif
739	.again: ud2
740	int3
741	jmp .again
742	BS3_PROC_END_CMN bs3CpuBasic2_call_ind_mem__ud2
743
744	; call [xAX]
745	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_call_ind_xAX__ud2
746	BS3_PROC_BEGIN_CMN bs3CpuBasic2_call_ind_xAX__ud2, BS3_PBC_NEAR
747	call xAX
748	.post_call:
749	times 17 int3
750	.again: ud2
751	int3
752	jmp .again
753	BS3_PROC_END_CMN bs3CpuBasic2_call_ind_xAX__ud2
754
755	; call [xDI]
756	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_call_ind_xDI__ud2
757	BS3_PROC_BEGIN_CMN bs3CpuBasic2_call_ind_xDI__ud2, BS3_PBC_NEAR
758	call xDI
759	.post_call:
760	times 17 int3
761	.again: ud2
762	int3
763	jmp .again
764	BS3_PROC_END_CMN bs3CpuBasic2_call_ind_xDI__ud2
765
766	%if TMPL_BITS == 64
767	; call [xAX]
768	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_call_ind_r9__ud2
769	BS3_PROC_BEGIN_CMN bs3CpuBasic2_call_ind_r9__ud2, BS3_PBC_NEAR
770	call r9
771	.post_call:
772	times 17 int3
773	.again: ud2
774	int3
775	jmp .again
776	BS3_PROC_END_CMN bs3CpuBasic2_call_ind_r9__ud2
777	%endif
778
779
780	;
781	; When applying opsize, we need to put this in the 16-bit text segment to
782	; better control where we end up in 32-bit and 64-bit mode.
783	;
784	; Try keep the code out of the IVT and BIOS data area. This unfortunately
785	; requires manual padding here.
786	;
787	BS3_BEGIN_TEXT16
788	BS3_SET_BITS TMPL_BITS
789	%if TMPL_BITS == 32
790	align 0x100, int3 ; Currently takes us up to 0x400 (max align value is 0x100)
791	times 0x200 int3 ; Brings us up to 0x600.
792	%endif
793
794	BS3_GLOBAL_NAME_EX BS3_CMN_NM(bs3CpuBasic2_jmp_opsize_begin), , 1
795
796
797	; jmp rel8 (forwards) with opsize override.
798	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmp_jb_opsize__ud2
799	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmp_jb_opsize__ud2, BS3_PBC_NEAR
800	db 66h
801	jmp short .again
802	.post_jmp:
803	times 8 int3
804	.again: ud2
805	int3
806	jmp .again
807	AssertCompile(.post_jmp - BS3_LAST_LABEL == 3)
808	BS3_PROC_END_CMN bs3CpuBasic2_jmp_jb_opsize__ud2
809
810
811	; jmp rel8 (backwards) with opsize override.
812	BS3_GLOBAL_NAME_EX RT_CONCAT(BS3_CMN_NM(bs3CpuBasic2_jmp_jb_opsize_back__ud2),.again), function, 2
813	ud2
814	times 19 int3
815	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmp_jb_opsize_back__ud2
816	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmp_jb_opsize_back__ud2, BS3_PBC_NEAR
817	db 66h
818	jmp short .again
819	.post_jmp:
820	int3
821	AssertCompile(.post_jmp - BS3_LAST_LABEL == 3)
822	BS3_PROC_END_CMN bs3CpuBasic2_jmp_jb_opsize_back__ud2
823
824
825	; jmp rel16 (forwards) with opsize override.
826	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmp_jv_opsize__ud2
827	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmp_jv_opsize__ud2, BS3_PBC_NEAR
828	db 66h, 0e9h ; o32 jmp near .again
829	%if TMPL_BITS != 32
830	dd 11
831	%else
832	dw 11
833	%endif
834	.post_jmp:
835	times 11 int3
836	.again: ud2
837	int3
838	jmp .again
839	BS3_PROC_END_CMN bs3CpuBasic2_jmp_jv_opsize__ud2
840
841
842	; jmp rel16 (backwards) with opsize override.
843	BS3_GLOBAL_NAME_EX RT_CONCAT(BS3_CMN_NM(bs3CpuBasic2_jmp_jv_opsize_back__ud2),.again), function, 2
844	ud2
845	times 19 int3
846	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmp_jv_opsize_back__ud2
847	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmp_jv_opsize_back__ud2, BS3_PBC_NEAR
848	%if TMPL_BITS != 32
849	db 66h, 0e9h ; o32 jmp near .again
850	dd RT_CONCAT(BS3_CMN_NM(bs3CpuBasic2_jmp_jv_opsize_back__ud2),.again) - .post_jmp
851	%else
852	db 66h, 0e9h ; o16 jmp near .again
853	dw RT_CONCAT(BS3_CMN_NM(bs3CpuBasic2_jmp_jv_opsize_back__ud2),.again) - .post_jmp
854	%endif
855	.post_jmp:
856	int3
857	BS3_PROC_END_CMN bs3CpuBasic2_jmp_jv_opsize_back__ud2
858
859
860	BS3_GLOBAL_NAME_EX BS3_CMN_NM(bs3CpuBasic2_jmp_opsize_end), , 1
861	int3
862
863	; jmp [indirect]
864	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmp_ind_mem_opsize__ud2
865	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmp_ind_mem_opsize__ud2, BS3_PBC_NEAR
866	db 66h
867	%if TMPL_BITS == 16
868	jmp [word cs:.npAgain]
869	%elif TMPL_BITS == 32
870	jmp [dword cs:.npAgain wrt FLAT]
871	%else
872	jmp [.npAgain wrt FLAT]
873	%endif
874	.post_jmp:
875	times 9 int3
876	.npAgain:
877	%if TMPL_BITS == 16
878	dw BS3_TEXT16_WRT(.again)
879	dw 0
880	%else
881	dw .again wrt CGROUP16
882	dw 0faceh, 0f00dh, 07777h ; non-canonical address
883	%endif
884	.again: ud2
885	int3
886	jmp .again
887	BS3_PROC_END_CMN bs3CpuBasic2_jmp_ind_mem_opsize__ud2
888
889	%if TMPL_BITS == 64
890	; jmp [indirect] - 64-bit intel version
891	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmp_ind_mem_opsize__ud2__intel
892	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmp_ind_mem_opsize__ud2__intel, BS3_PBC_NEAR
893	db 66h
894	jmp [.npAgain wrt FLAT]
895	.post_jmp:
896	times 8 int3
897	.npAgain:
898	dd .again wrt FLAT
899	dd 0
900	.again: ud2
901	int3
902	jmp .again
903	BS3_PROC_END_CMN bs3CpuBasic2_jmp_ind_mem_opsize__ud2__intel
904	%endif
905
906	; jmp [xAX]
907	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmp_ind_xAX_opsize__ud2
908	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmp_ind_xAX_opsize__ud2, BS3_PBC_NEAR
909	db 66h
910	jmp xAX
911	.post_jmp:
912	times 8 int3
913	.again: ud2
914	int3
915	jmp .again
916	BS3_PROC_END_CMN bs3CpuBasic2_jmp_ind_xAX_opsize__ud2
917
918
919	; call rel16/32 (forwards) with opsize override.
920	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_call_jv_opsize__ud2
921	BS3_PROC_BEGIN_CMN bs3CpuBasic2_call_jv_opsize__ud2, BS3_PBC_NEAR
922	db 66h, 0e8h ; o32 jmp near .again
923	%if TMPL_BITS != 32
924	dd 12
925	%else
926	dw 12
927	%endif
928	.post_call:
929	times 12 int3
930	.again: ud2
931	int3
932	jmp .again
933	BS3_PROC_END_CMN bs3CpuBasic2_call_jv_opsize__ud2
934
935
936	; call rel16/32 (backwards) with opsize override.
937	BS3_GLOBAL_NAME_EX RT_CONCAT(BS3_CMN_NM(bs3CpuBasic2_call_jv_opsize_back__ud2),.again), function, 2
938	ud2
939	times 19 int3
940	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_call_jv_opsize_back__ud2
941	BS3_PROC_BEGIN_CMN bs3CpuBasic2_call_jv_opsize_back__ud2, BS3_PBC_NEAR
942	%if TMPL_BITS != 32
943	db 66h, 0e8h ; o32 call near .again
944	dd RT_CONCAT(BS3_CMN_NM(bs3CpuBasic2_call_jv_opsize_back__ud2),.again) - .post_call
945	%else
946	db 66h, 0e8h ; o16 call near .again
947	dw RT_CONCAT(BS3_CMN_NM(bs3CpuBasic2_call_jv_opsize_back__ud2),.again) - .post_call
948	%endif
949	.post_call:
950	int3
951	BS3_PROC_END_CMN bs3CpuBasic2_call_jv_opsize_back__ud2
952
953	; call [indirect]
954	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_call_ind_mem_opsize__ud2
955	BS3_PROC_BEGIN_CMN bs3CpuBasic2_call_ind_mem_opsize__ud2, BS3_PBC_NEAR
956	db 66h
957	%if TMPL_BITS == 16
958	call [word cs:.npAgain]
959	%elif TMPL_BITS == 32
960	call [dword cs:.npAgain wrt FLAT]
961	%else
962	call [.npAgain wrt FLAT]
963	%endif
964	.post_call:
965	times 9 int3
966	.npAgain:
967	%if TMPL_BITS == 16
968	dw BS3_TEXT16_WRT(.again)
969	dw 0
970	%else
971	dw .again wrt CGROUP16
972	dw 0faceh, 0f00dh, 07777h ; non-canonical address
973	%endif
974	.again: ud2
975	int3
976	jmp .again
977	BS3_PROC_END_CMN bs3CpuBasic2_call_ind_mem_opsize__ud2
978
979	%if TMPL_BITS == 64
980	; call [indirect] - 64-bit intel version
981	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_call_ind_mem_opsize__ud2__intel
982	BS3_PROC_BEGIN_CMN bs3CpuBasic2_call_ind_mem_opsize__ud2__intel, BS3_PBC_NEAR
983	db 66h
984	call [.npAgain wrt FLAT]
985	.post_call:
986	times 8 int3
987	.npAgain:
988	dd .again wrt FLAT
989	dd 0
990	.again: ud2
991	int3
992	jmp .again
993	BS3_PROC_END_CMN bs3CpuBasic2_call_ind_mem_opsize__ud2__intel
994	%endif
995
996	; call [xAX]
997	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_call_ind_xAX_opsize__ud2
998	BS3_PROC_BEGIN_CMN bs3CpuBasic2_call_ind_xAX_opsize__ud2, BS3_PBC_NEAR
999	db 66h
1000	call xAX
1001	.post_call:
1002	times 8 int3
1003	.again: ud2
1004	int3
1005	jmp .again
1006	BS3_PROC_END_CMN bs3CpuBasic2_call_ind_xAX_opsize__ud2
1007
1008
1009
1010	;*********************************************************************************************************************************
1011	;* FAR JMP ABS *
1012	;*********************************************************************************************************************************
1013
1014	%if TMPL_BITS == 16
1015	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmpf_ptr_rm__ud2
1016	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmpf_ptr_rm__ud2, BS3_PBC_NEAR
1017	db 0eah
1018	dw .again wrt CGROUP16
1019	dw BS3_SEL_TEXT16
1020	.post_jmp:
1021	times 2 int3
1022	.again: ud2
1023	int3
1024	jmp .again
1025	BS3_PROC_END_CMN bs3CpuBasic2_jmpf_ptr_rm__ud2
1026	%endif
1027
1028	%if TMPL_BITS != 64
1029
1030	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmpf_ptr_same_r0__ud2
1031	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmpf_ptr_same_r0__ud2, BS3_PBC_NEAR
1032	db 0eah
1033	%if TMPL_BITS == 16
1034	dw .again wrt CGROUP16
1035	dw BS3_SEL_R0_CS16
1036	%else
1037	dd .again wrt FLAT
1038	dw BS3_SEL_R0_CS32
1039	%endif
1040	.post_jmp:
1041	times 7 int3
1042	.again: ud2
1043	int3
1044	jmp .again
1045	BS3_PROC_END_CMN bs3CpuBasic2_jmpf_ptr_same_r0__ud2
1046
1047	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmpf_ptr_same_r1__ud2
1048	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmpf_ptr_same_r1__ud2, BS3_PBC_NEAR
1049	db 0eah ; inter privilege jmp -> #GP(dst-cs)
1050	%if TMPL_BITS == 16
1051	dw .again wrt CGROUP16
1052	dw BS3_SEL_R1_CS16 \| 1
1053	%else
1054	dd .again wrt FLAT
1055	dw BS3_SEL_R1_CS32 \| 1
1056	%endif
1057	.again: ud2
1058	jmp .again
1059	BS3_PROC_END_CMN bs3CpuBasic2_jmpf_ptr_same_r1__ud2
1060
1061	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmpf_ptr_same_r2__ud2
1062	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmpf_ptr_same_r2__ud2, BS3_PBC_NEAR
1063	db 0eah ; inter privilege jmp -> #GP(dst-cs)
1064	%if TMPL_BITS == 16
1065	dw .again wrt CGROUP16
1066	dw BS3_SEL_R2_CS16 \| 2
1067	%else
1068	dd .again wrt FLAT
1069	dw BS3_SEL_R2_CS32 \| 2
1070	%endif
1071	.again: ud2
1072	jmp .again
1073	BS3_PROC_END_CMN bs3CpuBasic2_jmpf_ptr_same_r2__ud2
1074
1075	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmpf_ptr_same_r3__ud2
1076	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmpf_ptr_same_r3__ud2, BS3_PBC_NEAR
1077	db 0eah ; inter privilege jmp -> #GP(dst-cs)
1078	%if TMPL_BITS == 16
1079	dw .again wrt CGROUP16
1080	dw BS3_SEL_R3_CS16 \| 3
1081	%else
1082	dd .again wrt FLAT
1083	dw BS3_SEL_R3_CS32 \| 3
1084	%endif
1085	.again: ud2
1086	jmp .again
1087	BS3_PROC_END_CMN bs3CpuBasic2_jmpf_ptr_same_r3__ud2
1088
1089	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmpf_ptr_opsize_flipbit_r0__ud2
1090	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmpf_ptr_opsize_flipbit_r0__ud2, BS3_PBC_NEAR
1091	db 066h, 0eah
1092	%if TMPL_BITS == 32
1093	dw .again wrt CGROUP16
1094	dw BS3_SEL_R0_CS16
1095	%else
1096	dd .again wrt FLAT
1097	dw BS3_SEL_R0_CS32
1098	%endif
1099	times 4 int3
1100	.again: ud2
1101	jmp .again
1102	BS3_PROC_END_CMN bs3CpuBasic2_jmpf_ptr_opsize_flipbit_r0__ud2
1103
1104	; Do a jmp to BS3_SEL_R0_CS64. Except for when we're in long mode, this will
1105	; result in a 16-bit CS with zero base and 4G limit.
1106	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmpf_ptr_r0_cs64__ud2
1107	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmpf_ptr_r0_cs64__ud2, BS3_PBC_NEAR
1108	%if TMPL_BITS == 16
1109	db 066h
1110	%endif
1111	db 0eah
1112	dd .jmp_target wrt FLAT
1113	dw BS3_SEL_R0_CS64
1114	times 8 int3
1115	.jmp_target:
1116	salc ; #UD in 64-bit mode
1117	.again: ud2
1118	jmp .again
1119	BS3_PROC_END_CMN bs3CpuBasic2_jmpf_ptr_r0_cs64__ud2
1120
1121	; Variation of the previous with a CS16 copy that has the L bit set, emulating
1122	; pre-AMD64 software using the L bit for other stuff. (Don't run in long mode
1123	; w/o copying the 3 bytes to the 0xxxxh memory range.)
1124	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmpf_ptr_r0_cs16l__ud2
1125	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmpf_ptr_r0_cs16l__ud2, BS3_PBC_NEAR
1126	%if TMPL_BITS != 16
1127	db 066h
1128	%endif
1129	db 0eah
1130	dw .jmp_target wrt CGROUP16
1131	dw BS3_SEL_SPARE_00 ; ASSUMES this is set up as CGROUP16 but with L=1.
1132	times 3 int3
1133	.jmp_target:
1134	salc ; #UD in 64-bit mode
1135	.again: ud2
1136	jmp .again
1137	BS3_PROC_END_CMN bs3CpuBasic2_jmpf_ptr_r0_cs16l__ud2
1138
1139	%endif ; TMPL_BITS != 64
1140
1141
1142
1143	;*********************************************************************************************************************************
1144	;* FAR CALL ABS *
1145	;*********************************************************************************************************************************
1146
1147	%if TMPL_BITS == 16
1148	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_callf_ptr_rm__ud2
1149	BS3_PROC_BEGIN_CMN bs3CpuBasic2_callf_ptr_rm__ud2, BS3_PBC_NEAR
1150	db 09ah
1151	dw .again wrt CGROUP16
1152	dw BS3_SEL_TEXT16
1153	.post_call:
1154	times 2 int3
1155	.again: ud2
1156	int3
1157	jmp .again
1158	BS3_PROC_END_CMN bs3CpuBasic2_callf_ptr_rm__ud2
1159	%endif
1160
1161	%if TMPL_BITS != 64
1162
1163	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_callf_ptr_same_r0__ud2
1164	BS3_PROC_BEGIN_CMN bs3CpuBasic2_callf_ptr_same_r0__ud2, BS3_PBC_NEAR
1165	db 09ah
1166	%if TMPL_BITS == 16
1167	dw .again wrt CGROUP16
1168	dw BS3_SEL_R0_CS16
1169	%else
1170	dd .again wrt FLAT
1171	dw BS3_SEL_R0_CS32
1172	%endif
1173	.post_call:
1174	times 7 int3
1175	.again: ud2
1176	int3
1177	jmp .again
1178	BS3_PROC_END_CMN bs3CpuBasic2_callf_ptr_same_r0__ud2
1179
1180	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_callf_ptr_same_r1__ud2
1181	BS3_PROC_BEGIN_CMN bs3CpuBasic2_callf_ptr_same_r1__ud2, BS3_PBC_NEAR
1182	db 09ah
1183	%if TMPL_BITS == 16
1184	dw .again wrt CGROUP16
1185	dw BS3_SEL_R1_CS16 \| 1
1186	%else
1187	dd .again wrt FLAT
1188	dw BS3_SEL_R1_CS32 \| 1
1189	%endif
1190	.again: ud2
1191	jmp .again
1192	BS3_PROC_END_CMN bs3CpuBasic2_callf_ptr_same_r1__ud2
1193
1194	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_callf_ptr_same_r2__ud2
1195	BS3_PROC_BEGIN_CMN bs3CpuBasic2_callf_ptr_same_r2__ud2, BS3_PBC_NEAR
1196	db 09ah
1197	%if TMPL_BITS == 16
1198	dw .again wrt CGROUP16
1199	dw BS3_SEL_R2_CS16 \| 2
1200	%else
1201	dd .again wrt FLAT
1202	dw BS3_SEL_R2_CS32 \| 2
1203	%endif
1204	.again: ud2
1205	jmp .again
1206	BS3_PROC_END_CMN bs3CpuBasic2_callf_ptr_same_r2__ud2
1207
1208	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_callf_ptr_same_r3__ud2
1209	BS3_PROC_BEGIN_CMN bs3CpuBasic2_callf_ptr_same_r3__ud2, BS3_PBC_NEAR
1210	db 09ah
1211	%if TMPL_BITS == 16
1212	dw .again wrt CGROUP16
1213	dw BS3_SEL_R3_CS16 \| 3
1214	%else
1215	dd .again wrt FLAT
1216	dw BS3_SEL_R3_CS32 \| 3
1217	%endif
1218	.again: ud2
1219	jmp .again
1220	BS3_PROC_END_CMN bs3CpuBasic2_callf_ptr_same_r3__ud2
1221
1222	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_callf_ptr_opsize_flipbit_r0__ud2
1223	BS3_PROC_BEGIN_CMN bs3CpuBasic2_callf_ptr_opsize_flipbit_r0__ud2, BS3_PBC_NEAR
1224	db 066h, 09ah
1225	%if TMPL_BITS == 32
1226	dw .again wrt CGROUP16
1227	dw BS3_SEL_R0_CS16
1228	%else
1229	dd .again wrt FLAT
1230	dw BS3_SEL_R0_CS32
1231	%endif
1232	times 4 int3
1233	.again: ud2
1234	jmp .again
1235	BS3_PROC_END_CMN bs3CpuBasic2_callf_ptr_opsize_flipbit_r0__ud2
1236
1237	; Do a call to BS3_SEL_R0_CS64. Except for when we're in long mode, this will
1238	; result in a 16-bit CS with zero base and 4G limit.
1239	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_callf_ptr_r0_cs64__ud2
1240	BS3_PROC_BEGIN_CMN bs3CpuBasic2_callf_ptr_r0_cs64__ud2, BS3_PBC_NEAR
1241	%if TMPL_BITS == 16
1242	db 066h
1243	%endif
1244	db 09ah
1245	dd .call_target wrt FLAT
1246	dw BS3_SEL_R0_CS64
1247	times 8 int3
1248	.call_target:
1249	salc ; #UD in 64-bit mode
1250	.again: ud2
1251	jmp .again
1252	BS3_PROC_END_CMN bs3CpuBasic2_callf_ptr_r0_cs64__ud2
1253
1254	; Variation of the previous with a CS16 copy that has the L bit set, emulating
1255	; pre-AMD64 software using the L bit for other stuff. (Don't run in long mode
1256	; w/o copying the 3 bytes to the 0xxxxh memory range.)
1257	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_callf_ptr_r0_cs16l__ud2
1258	BS3_PROC_BEGIN_CMN bs3CpuBasic2_callf_ptr_r0_cs16l__ud2, BS3_PBC_NEAR
1259	%if TMPL_BITS != 16
1260	db 066h
1261	%endif
1262	db 09ah
1263	dw .call_target wrt CGROUP16
1264	dw BS3_SEL_SPARE_00 ; ASSUMES this is set up as CGROUP16 but with L=1.
1265	times 3 int3
1266	.call_target:
1267	salc ; #UD in 64-bit mode
1268	.again: ud2
1269	jmp .again
1270	BS3_PROC_END_CMN bs3CpuBasic2_callf_ptr_r0_cs16l__ud2
1271
1272	%endif ; TMPL_BITS != 64
1273
1274
1275	;*********************************************************************************************************************************
1276	;* INDIRECT FAR JMP *
1277	;*********************************************************************************************************************************
1278
1279	%if TMPL_BITS == 16
1280	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmpf_mem_rm__ud2
1281	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmpf_mem_rm__ud2, BS3_PBC_NEAR
1282	jmp far [BS3_CPUBAS2_REF_LABEL_VIA_CS(.fpfn)]
1283	int3
1284	.fpfn:
1285	dw .again wrt CGROUP16
1286	dw BS3_SEL_TEXT16
1287	.post_jmp:
1288	times 2 int3
1289	.again: ud2
1290	int3
1291	jmp .again
1292	BS3_PROC_END_CMN bs3CpuBasic2_jmpf_mem_rm__ud2
1293	%endif
1294
1295	;;
1296	; Since AMD and Intel treat REX.W differently, we need two versions of the
1297	; test functions here and use a macro to accomplish that.
1298	;
1299	; @param 1 Symbol suffix
1300	; @param 2 0 for AMD, 1 for Intel.
1301	;
1302	%ifnmacro jmpf_macro
1303	%macro jmpf_macro 2
1304
1305	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmpf_mem_same_r0__ud2 %+ %1
1306	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmpf_mem_same_r0__ud2 %+ %1, BS3_PBC_NEAR
1307	BS3_CPUBAS2_JMP_FAR_MEM_LABEL .fpfn, 2
1308	.fpfn:
1309	%if TMPL_BITS == 16
1310	dw .again wrt CGROUP16
1311	dw BS3_SEL_R0_CS16
1312	%elif TMPL_BITS == 32
1313	dd .again wrt FLAT
1314	dw BS3_SEL_R0_CS32
1315	%else
1316	dd .again wrt FLAT
1317	%if %2 != 0
1318	dd 0fffff000h
1319	%endif
1320	dw BS3_SEL_R0_CS64
1321	%endif
1322	.post_jmp:
1323	times 7 int3
1324	.again: ud2
1325	int3
1326	jmp .again
1327	BS3_PROC_END_CMN bs3CpuBasic2_jmpf_mem_same_r0__ud2 %+ %1
1328
1329	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmpf_mem_same_r1__ud2 %+ %1
1330	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmpf_mem_same_r1__ud2 %+ %1, BS3_PBC_NEAR
1331	BS3_CPUBAS2_JMP_FAR_MEM_LABEL .fpfn, 2
1332	.fpfn:
1333	%if TMPL_BITS == 16
1334	dw .again wrt CGROUP16
1335	dw BS3_SEL_R1_CS16 \| 1
1336	%elif TMPL_BITS == 32
1337	dd .again wrt FLAT
1338	dw BS3_SEL_R1_CS32 \| 1
1339	%else
1340	dd .again wrt FLAT
1341	%if %2 != 0
1342	dd 0fffff000h
1343	%endif
1344	dw BS3_SEL_R1_CS64 \| 1
1345	%endif
1346	.again: ud2
1347	jmp .again
1348	BS3_PROC_END_CMN bs3CpuBasic2_jmpf_mem_same_r1__ud2 %+ %1
1349
1350	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmpf_mem_same_r2__ud2 %+ %1
1351	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmpf_mem_same_r2__ud2 %+ %1, BS3_PBC_NEAR
1352	BS3_CPUBAS2_JMP_FAR_MEM_LABEL .fpfn, 0
1353	.fpfn:
1354	%if TMPL_BITS == 16
1355	dw .again wrt CGROUP16
1356	dw BS3_SEL_R2_CS16 \| 2
1357	%elif TMPL_BITS == 32
1358	dd .again wrt FLAT
1359	dw BS3_SEL_R2_CS32 \| 2
1360	%else
1361	dd .again wrt FLAT
1362	dw BS3_SEL_R2_CS64 \| 2
1363	%endif
1364	.again: ud2
1365	jmp .again
1366	BS3_PROC_END_CMN bs3CpuBasic2_jmpf_mem_same_r2__ud2 %+ %1
1367
1368	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmpf_mem_same_r3__ud2 %+ %1
1369	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmpf_mem_same_r3__ud2 %+ %1, BS3_PBC_NEAR
1370	BS3_CPUBAS2_JMP_FAR_MEM_LABEL .fpfn, 2
1371	.fpfn:
1372	%if TMPL_BITS == 16
1373	dw .again wrt CGROUP16
1374	dw BS3_SEL_R3_CS16 \| 3
1375	%elif TMPL_BITS == 32
1376	dd .again wrt FLAT
1377	dw BS3_SEL_R3_CS32 \| 3
1378	%else
1379	dd .again wrt FLAT
1380	%if %2 != 0
1381	dd 0fffff000h
1382	%endif
1383	dw BS3_SEL_R3_CS64 \| 3
1384	%endif
1385	.again: ud2
1386	jmp .again
1387	BS3_PROC_END_CMN bs3CpuBasic2_jmpf_mem_same_r3__ud2 %+ %1
1388
1389	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmpf_mem_r0_cs16__ud2 %+ %1
1390	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmpf_mem_r0_cs16__ud2 %+ %1, BS3_PBC_NEAR
1391	BS3_CPUBAS2_JMP_FAR_MEM_LABEL .fpfn, (TMPL_BITS != 16) ; TMPL_BITS != 16 ? 1 : 0
1392	.fpfn:
1393	dw .again wrt CGROUP16
1394	dw BS3_SEL_R0_CS16
1395	times 4 int3
1396	.again: ud2
1397	jmp .again
1398	BS3_PROC_END_CMN bs3CpuBasic2_jmpf_mem_r0_cs16__ud2 %+ %1
1399
1400	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmpf_mem_r0_cs32__ud2 %+ %1
1401	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmpf_mem_r0_cs32__ud2 %+ %1, BS3_PBC_NEAR
1402	BS3_CPUBAS2_JMP_FAR_MEM_LABEL .fpfn, (TMPL_BITS == 16) ; TMPL_BITS == 16 ? 1 : 0
1403	.fpfn:
1404	dd .again wrt FLAT
1405	dw BS3_SEL_R0_CS32
1406	times 4 int3
1407	.again: ud2
1408	jmp .again
1409	BS3_PROC_END_CMN bs3CpuBasic2_jmpf_mem_r0_cs32__ud2 %+ %1
1410
1411	; Do a jmp to BS3_SEL_R0_CS64. Except for when we're in long mode, this will
1412	; result in a 16-bit CS with zero base and 4G limit.
1413	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmpf_mem_r0_cs64__ud2 %+ %1
1414	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmpf_mem_r0_cs64__ud2 %+ %1, BS3_PBC_NEAR
1415	BS3_CPUBAS2_JMP_FAR_MEM_LABEL .fpfn, (2 - (TMPL_BITS == 16)) ; TMPL_BITS == 16 ? 1 : 2
1416	.fpfn:
1417	dd .jmp_target wrt FLAT
1418	%if TMPL_BITS == 64 && %2 != 0
1419	dd 0fffff000h
1420	%endif
1421	dw BS3_SEL_R0_CS64
1422	times 8 int3
1423	.jmp_target:
1424	%if TMPL_BITS != 64
1425	salc ; #UD in 64-bit mode
1426	%endif
1427	.again: ud2
1428	jmp .again
1429	BS3_PROC_END_CMN bs3CpuBasic2_jmpf_mem_r0_cs64__ud2 %+ %1
1430
1431	; Variation of the previous with a CS16 copy that has the L bit set, emulating
1432	; pre-AMD64 software using the L bit for other stuff. (Don't run _c16/32 in
1433	; long mode w/o copying the 3 bytes to the 0xxxxh memory range.)
1434	; The _c64 version will test that the base is ignored.
1435	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmpf_mem_r0_cs16l__ud2 %+ %1
1436	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmpf_mem_r0_cs16l__ud2 %+ %1, BS3_PBC_NEAR
1437	BS3_CPUBAS2_JMP_FAR_MEM_LABEL .fpfn, (TMPL_BITS == 32) ; TMPL_BITS == 32 ? 1 : 0
1438	.fpfn:
1439	%if TMPL_BITS != 64
1440	dw .jmp_target wrt CGROUP16
1441	%else
1442	dd .jmp_target wrt FLAT
1443	%endif
1444	dw BS3_SEL_SPARE_00 ; ASSUMES this is set up as CGROUP16 but with L=1.
1445	times 3 int3
1446	.jmp_target:
1447	%if TMPL_BITS != 64
1448	salc ; #UD in 64-bit mode
1449	%endif
1450	.again: ud2
1451	jmp .again
1452	BS3_PROC_END_CMN bs3CpuBasic2_jmpf_mem_r0_cs16l__ud2 %+ %1
1453
1454	%endmacro
1455	%endif
1456
1457	; Instantiate the above code
1458	jmpf_macro , 0
1459	%if TMPL_BITS == 64
1460	jmpf_macro _intel, 1
1461	%endif
1462
1463
1464	;*********************************************************************************************************************************
1465	;* INDIRECT FAR CALL *
1466	;*********************************************************************************************************************************
1467
1468	%if TMPL_BITS == 16
1469	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_callf_mem_rm__ud2
1470	BS3_PROC_BEGIN_CMN bs3CpuBasic2_callf_mem_rm__ud2, BS3_PBC_NEAR
1471	call far [BS3_CPUBAS2_REF_LABEL_VIA_CS(.fpfn)]
1472	int3
1473	.fpfn:
1474	dw .again wrt CGROUP16
1475	dw BS3_SEL_TEXT16
1476	.post_jmp:
1477	times 2 int3
1478	.again: ud2
1479	int3
1480	jmp .again
1481	BS3_PROC_END_CMN bs3CpuBasic2_callf_mem_rm__ud2
1482	%endif
1483
1484
1485	;;
1486	; Since AMD and Intel treat REX.W differently, we need two versions of the
1487	; test functions here and use a macro to accomplish that.
1488	;
1489	; @param 1 Symbol suffix
1490	; @param 2 0 for AMD, 1 for Intel.
1491	;
1492	%ifnmacro callf_macro
1493	%macro callf_macro 2
1494
1495	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_callf_mem_same_r0__ud2 %+ %1
1496	BS3_PROC_BEGIN_CMN bs3CpuBasic2_callf_mem_same_r0__ud2 %+ %1, BS3_PBC_NEAR
1497	BS3_CPUBAS2_CALL_FAR_MEM_LABEL .fpfn, 2
1498	.fpfn:
1499	%if TMPL_BITS == 16
1500	dw .again wrt CGROUP16
1501	dw BS3_SEL_R0_CS16
1502	%elif TMPL_BITS == 32
1503	dd .again wrt FLAT
1504	dw BS3_SEL_R0_CS32
1505	%else
1506	dd .again wrt FLAT
1507	%if %2 != 0
1508	dd 0fffff000h
1509	%endif
1510	dw BS3_SEL_R0_CS64
1511	%endif
1512	.post_call:
1513	times 7 int3
1514	.again: ud2
1515	int3
1516	jmp .again
1517	BS3_PROC_END_CMN bs3CpuBasic2_callf_mem_same_r0__ud2 %+ %1
1518
1519	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_callf_mem_same_r1__ud2 %+ %1
1520	BS3_PROC_BEGIN_CMN bs3CpuBasic2_callf_mem_same_r1__ud2 %+ %1, BS3_PBC_NEAR
1521	BS3_CPUBAS2_CALL_FAR_MEM_LABEL .fpfn, 2
1522	.fpfn:
1523	%if TMPL_BITS == 16
1524	dw .again wrt CGROUP16
1525	dw BS3_SEL_R1_CS16 \| 1
1526	%elif TMPL_BITS == 32
1527	dd .again wrt FLAT
1528	dw BS3_SEL_R1_CS32 \| 1
1529	%else
1530	dd .again wrt FLAT
1531	%if %2 != 0
1532	dd 0fffff000h
1533	%endif
1534	dw BS3_SEL_R1_CS64 \| 1
1535	%endif
1536	.again: ud2
1537	jmp .again
1538	BS3_PROC_END_CMN bs3CpuBasic2_callf_mem_same_r1__ud2 %+ %1
1539
1540	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_callf_mem_same_r2__ud2 %+ %1
1541	BS3_PROC_BEGIN_CMN bs3CpuBasic2_callf_mem_same_r2__ud2 %+ %1, BS3_PBC_NEAR
1542	BS3_CPUBAS2_CALL_FAR_MEM_LABEL .fpfn, 0
1543	.fpfn:
1544	%if TMPL_BITS == 16
1545	dw .again wrt CGROUP16
1546	dw BS3_SEL_R2_CS16 \| 2
1547	%elif TMPL_BITS == 32
1548	dd .again wrt FLAT
1549	dw BS3_SEL_R2_CS32 \| 2
1550	%else
1551	dd .again wrt FLAT
1552	dw BS3_SEL_R2_CS64 \| 2
1553	%endif
1554	.again: ud2
1555	jmp .again
1556	BS3_PROC_END_CMN bs3CpuBasic2_callf_mem_same_r2__ud2 %+ %1
1557
1558	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_callf_mem_same_r3__ud2 %+ %1
1559	BS3_PROC_BEGIN_CMN bs3CpuBasic2_callf_mem_same_r3__ud2 %+ %1, BS3_PBC_NEAR
1560	BS3_CPUBAS2_CALL_FAR_MEM_LABEL .fpfn, 2
1561	.fpfn:
1562	%if TMPL_BITS == 16
1563	dw .again wrt CGROUP16
1564	dw BS3_SEL_R3_CS16 \| 3
1565	%elif TMPL_BITS == 32
1566	dd .again wrt FLAT
1567	dw BS3_SEL_R3_CS32 \| 3
1568	%else
1569	dd .again wrt FLAT
1570	%if %2 != 0
1571	dd 0fffff000h
1572	%endif
1573	dw BS3_SEL_R3_CS64 \| 3
1574	%endif
1575	.again: ud2
1576	jmp .again
1577	BS3_PROC_END_CMN bs3CpuBasic2_callf_mem_same_r3__ud2 %+ %1
1578
1579	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_callf_mem_r0_cs16__ud2 %+ %1
1580	BS3_PROC_BEGIN_CMN bs3CpuBasic2_callf_mem_r0_cs16__ud2 %+ %1, BS3_PBC_NEAR
1581	BS3_CPUBAS2_CALL_FAR_MEM_LABEL .fpfn, (TMPL_BITS != 16) ; (TMPL_BITS == 16 ? 0 : 1)
1582	.fpfn:
1583	dw .again wrt CGROUP16
1584	dw BS3_SEL_R0_CS16
1585	times 4 int3
1586	.again: ud2
1587	jmp .again
1588	BS3_PROC_END_CMN bs3CpuBasic2_callf_mem_r0_cs16__ud2 %+ %1
1589
1590	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_callf_mem_r0_cs32__ud2 %+ %1
1591	BS3_PROC_BEGIN_CMN bs3CpuBasic2_callf_mem_r0_cs32__ud2 %+ %1, BS3_PBC_NEAR
1592	BS3_CPUBAS2_CALL_FAR_MEM_LABEL .fpfn, (TMPL_BITS == 16) ; (TMPL_BITS == 16 ? 1 : 0)
1593	.fpfn:
1594	dd .again wrt FLAT
1595	dw BS3_SEL_R0_CS32
1596	times 4 int3
1597	.again: ud2
1598	jmp .again
1599	BS3_PROC_END_CMN bs3CpuBasic2_callf_mem_r0_cs32__ud2 %+ %1
1600
1601	; Do a call to BS3_SEL_R0_CS64. Except for when we're in long mode, this will
1602	; result in a 16-bit CS with zero base and 4G limit.
1603	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_callf_mem_r0_cs64__ud2 %+ %1
1604	BS3_PROC_BEGIN_CMN bs3CpuBasic2_callf_mem_r0_cs64__ud2 %+ %1, BS3_PBC_NEAR
1605	BS3_CPUBAS2_CALL_FAR_MEM_LABEL .fpfn, (2 - (TMPL_BITS == 16)) ; (TMPL_BITS == 16 ? 1 : 2)
1606	.fpfn:
1607	dd .call_target wrt FLAT
1608	%if TMPL_BITS == 64 && %2 != 0
1609	dd 0fffff000h
1610	%endif
1611	dw BS3_SEL_R0_CS64
1612	times 8 int3
1613	.call_target:
1614	%if TMPL_BITS != 64
1615	salc ; #UD in 64-bit mode
1616	%endif
1617	.again: ud2
1618	jmp .again
1619	BS3_PROC_END_CMN bs3CpuBasic2_callf_mem_r0_cs64__ud2 %+ %1
1620
1621	; Variation of the previous with a CS16 copy that has the L bit set, emulating
1622	; pre-AMD64 software using the L bit for other stuff. (Don't run _c16/32 in
1623	; long mode w/o copying the 3 bytes to the 0xxxxh memory range.)
1624	; The _c64 version will test that the base is ignored.
1625	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_callf_mem_r0_cs16l__ud2 %+ %1
1626	BS3_PROC_BEGIN_CMN bs3CpuBasic2_callf_mem_r0_cs16l__ud2 %+ %1, BS3_PBC_NEAR
1627	BS3_CPUBAS2_CALL_FAR_MEM_LABEL .fpfn, (TMPL_BITS == 32) ; (TMPL_BITS == 32 ? 1 : 0)
1628	.fpfn:
1629	%if TMPL_BITS != 64
1630	dw .call_target wrt CGROUP16
1631	%else
1632	dd .call_target wrt FLAT
1633	%endif
1634	dw BS3_SEL_SPARE_00 ; ASSUMES this is set up as CGROUP16 but with L=1.
1635	times 3 int3
1636	.call_target:
1637	%if TMPL_BITS != 64
1638	salc ; #UD in 64-bit mode
1639	%endif
1640	.again: ud2
1641	jmp .again
1642	BS3_PROC_END_CMN bs3CpuBasic2_callf_mem_r0_cs16l__ud2 %+ %1
1643
1644	%endmacro ; callf_macro
1645	%endif
1646
1647	; Instantiate the above code
1648	callf_macro , 0
1649	%if TMPL_BITS == 64
1650	callf_macro _intel, 1
1651	%endif
1652
1653
1654	%endif ; BS3_INSTANTIATING_CMN
1655
1656	%include "bs3kit-template-footer.mac" ; reset environment
1657

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