| 1 | ; $Id: bootsector2-cpu-instr-1-template.mac 97108 2022-10-12 12:19:22Z vboxsync $
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| 2 | ;; @file
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| 3 | ; Bootsector test for misc instruction - multi mode template.
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| 4 | ;
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| 5 |
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| 6 | ;
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| 7 | ; Copyright (C) 2007-2022 Oracle and/or its affiliates.
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| 8 | ;
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| 9 | ; This file is part of VirtualBox base platform packages, as
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| 10 | ; available from https://www.alldomusa.eu.org.
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| 11 | ;
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| 12 | ; This program is free software; you can redistribute it and/or
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| 13 | ; modify it under the terms of the GNU General Public License
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| 14 | ; as published by the Free Software Foundation, in version 3 of the
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| 15 | ; License.
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| 16 | ;
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| 17 | ; This program is distributed in the hope that it will be useful, but
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| 18 | ; WITHOUT ANY WARRANTY; without even the implied warranty of
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| 19 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 20 | ; General Public License for more details.
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| 21 | ;
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| 22 | ; You should have received a copy of the GNU General Public License
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| 23 | ; along with this program; if not, see <https://www.gnu.org/licenses>.
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| 24 | ;
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| 25 | ; The contents of this file may alternatively be used under the terms
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| 26 | ; of the Common Development and Distribution License Version 1.0
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| 27 | ; (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
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| 28 | ; in the VirtualBox distribution, in which case the provisions of the
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| 29 | ; CDDL are applicable instead of those of the GPL.
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| 30 | ;
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| 31 | ; You may elect to license modified versions of this file under the
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| 32 | ; terms and conditions of either the GPL or the CDDL or both.
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| 33 | ;
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| 34 | ; SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
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| 35 | ;
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| 36 |
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| 37 |
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| 38 | %include "bootsector2-template-header.mac"
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| 39 |
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| 40 |
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| 41 |
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| 42 | ;;
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| 43 | ; Memory fence instructions (SSE2).
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| 44 | ;
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| 45 | ; @uses No registers, but BS2_SEL_SPARE0 is trashed.
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| 46 | ;
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| 47 | BEGINPROC TMPL_NM(TestMemFences)
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| 48 | push xBP
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| 49 | mov xBP, xSP
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| 50 | push sAX
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| 51 | push xBX
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| 52 | push xCX
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| 53 | push xDX
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| 54 | push xDI
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| 55 | push xSI
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| 56 | sub xSP, 80h ; iret stack frame space.
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| 57 | mov xSI, xSP ; Save the stack register.
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| 58 |
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| 59 | mov xAX, .s_szSubTestName
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| 60 | call TMPL_NM_CMN(TestSub)
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| 61 |
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| 62 | ;
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| 63 | ; SSE2 supported?
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| 64 | ;
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| 65 | mov eax, 1
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| 66 | xor ecx, ecx
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| 67 | cpuid
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| 68 | test edx, X86_CPUID_FEATURE_EDX_SSE2
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| 69 | jz .skip
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| 70 |
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| 71 | ;
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| 72 | ; Check that the standard instruction encodings work.
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| 73 | ;
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| 74 | mov xBX, [xSP + 10h]
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| 75 | mov [xSP], xAX
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| 76 | mfence
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| 77 | mov [xSP], xCX
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| 78 | mov xBX, [xSP + 08h]
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| 79 | sfence
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| 80 | mov [xSP], xDX
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| 81 | mov xBX, [xSP]
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| 82 | lfence
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| 83 | mov bx, [xSP + 04h]
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| 84 |
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| 85 |
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| 86 | ;
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| 87 | ; The instruction encodings in the intel manual may open the RM as well
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| 88 | ; as prefixes open to interpretation. AMD sets RM=0 in their docs.
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| 89 | ;
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| 90 | ; lfence = 0f,ea,e8
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| 91 | ; mfence = 0f,ea,f0
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| 92 | ; sfence = 0f,ea,f8
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| 93 | ; (RM is the lower 3 bits of the last byte.)
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| 94 |
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| 95 | %assign MY_RM 0xe8
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| 96 | %rep 18h
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| 97 | db 0fh, 0aeh, MY_RM
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| 98 | db X86_OP_PRF_CS, 0fh, 0aeh, MY_RM
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| 99 | db X86_OP_PRF_DS, 0fh, 0aeh, MY_RM
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| 100 | db X86_OP_PRF_ES, 0fh, 0aeh, MY_RM
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| 101 | db X86_OP_PRF_FS, 0fh, 0aeh, MY_RM
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| 102 | db X86_OP_PRF_GS, 0fh, 0aeh, MY_RM
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| 103 | db X86_OP_PRF_SS, 0fh, 0aeh, MY_RM
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| 104 | db X86_OP_PRF_SIZE_ADDR, 0fh, 0aeh, MY_RM
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| 105 | BS2_TRAP_INSTR X86_XCPT_UD, 0, db X86_OP_PRF_SIZE_OP, 0fh, 0aeh, MY_RM ; (used in group)
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| 106 | BS2_TRAP_INSTR X86_XCPT_UD, 0, db X86_OP_PRF_LOCK, 0fh, 0aeh, MY_RM ; (used in group)
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| 107 | BS2_TRAP_INSTR X86_XCPT_UD, 0, db X86_OP_PRF_REPNZ, 0fh, 0aeh, MY_RM ; (used in group)
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| 108 | BS2_TRAP_INSTR X86_XCPT_UD, 0, db X86_OP_PRF_REPZ, 0fh, 0aeh, MY_RM ; (used in group)
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| 109 | %ifdef TMPL_64BIT
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| 110 | %assign MY_REX 0x40
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| 111 | %rep 10h
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| 112 | ; Rex prefixes doesn't change anything.
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| 113 | db MY_REX, 0fh, 0aeh, MY_RM
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| 114 | db X86_OP_PRF_CS, MY_REX, 0fh, 0aeh, MY_RM
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| 115 | db X86_OP_PRF_DS, MY_REX, 0fh, 0aeh, MY_RM
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| 116 | db X86_OP_PRF_ES, MY_REX, 0fh, 0aeh, MY_RM
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| 117 | db X86_OP_PRF_FS, MY_REX, 0fh, 0aeh, MY_RM
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| 118 | db X86_OP_PRF_GS, MY_REX, 0fh, 0aeh, MY_RM
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| 119 | db X86_OP_PRF_SS, MY_REX, 0fh, 0aeh, MY_RM
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| 120 | db X86_OP_PRF_SIZE_ADDR, MY_REX, 0fh, 0aeh, MY_RM
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| 121 | BS2_TRAP_INSTR X86_XCPT_UD, 0, db X86_OP_PRF_SIZE_OP, MY_REX, 0fh, 0aeh, MY_RM ; (used in group)
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| 122 | BS2_TRAP_INSTR X86_XCPT_UD, 0, db X86_OP_PRF_LOCK, MY_REX, 0fh, 0aeh, MY_RM ; (used in group)
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| 123 | BS2_TRAP_INSTR X86_XCPT_UD, 0, db X86_OP_PRF_REPNZ, MY_REX, 0fh, 0aeh, MY_RM ; (used in group)
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| 124 | BS2_TRAP_INSTR X86_XCPT_UD, 0, db X86_OP_PRF_REPZ, MY_REX, 0fh, 0aeh, MY_RM ; (used in group)
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| 125 | %assign MY_REX (MY_REX + 1)
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| 126 | %endrep
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| 127 | %endif
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| 128 | %assign MY_RM (MY_RM + 1)
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| 129 | %endrep
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| 130 |
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| 131 | ;
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| 132 | ; Done.
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| 133 | ;
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| 134 | call TMPL_NM_CMN(TestSubDone)
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| 135 | .done:
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| 136 | mov xSP, xSI
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| 137 | add xSP, 80h
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| 138 | pop xSI
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| 139 | pop xDI
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| 140 | pop xDX
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| 141 | pop xCX
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| 142 | pop xBX
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| 143 | pop sAX
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| 144 | leave
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| 145 | ret
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| 146 |
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| 147 | .skip:
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| 148 | mov xAX, .s_szSse2Missing
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| 149 | call TMPL_NM_CMN(TestSubDone)
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| 150 | jmp .done
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| 151 |
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| 152 | .s_szSubTestName:
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| 153 | db TMPL_MODE_STR, ', mfence et al.', 0
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| 154 | .s_szSse2Missing:
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| 155 | db 'SSE2 is missing', 0
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| 156 | ENDPROC TMPL_NM(TestMemFences)
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| 157 |
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| 158 |
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| 159 | ;;
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| 160 | ; Floating-point to integer conversion (SSE/SSE2).
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| 161 | ; Neither Intel nor AMD explicitly document what happens for the 32-bit forms
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| 162 | ; of CVTxx2SI in 64-bit mode with regard to the high dword of a 64-bit
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| 163 | ; destination register.
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| 164 | ;
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| 165 | ; @uses XMM0, and BS2_SEL_SPARE0 is trashed.
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| 166 | ;
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| 167 | BEGINPROC TMPL_NM(TestCvtSize)
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| 168 | push xBP
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| 169 | mov xBP, xSP
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| 170 | push sAX
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| 171 | push xBX
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| 172 | push xCX
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| 173 | push xDX
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| 174 | push xDI
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| 175 | push xSI
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| 176 | sub xSP, 80h ; iret stack frame space.
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| 177 | mov xSI, xSP ; Save the stack register.
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| 178 |
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| 179 | mov xAX, .s_szSubTestName
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| 180 | call TMPL_NM_CMN(TestSub)
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| 181 |
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| 182 | ;
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| 183 | ; SSE2 supported?
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| 184 | ;
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| 185 | mov eax, 1
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| 186 | xor ecx, ecx
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| 187 | cpuid
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| 188 | test edx, X86_CPUID_FEATURE_EDX_SSE2
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| 189 | jz .skip
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| 190 |
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| 191 | %ifdef TMPL_64BIT
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| 192 |
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| 193 | ;
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| 194 | ; Have to enable OSFXSR for SSE instructions to work.
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| 195 | ;
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| 196 | mov rcx,cr4
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| 197 | mov rsi,rcx
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| 198 | or rcx,200h
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| 199 | mov cr4,rcx
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| 200 |
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| 201 | ;
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| 202 | ; Load 32-bit float -2.75 into XMM0
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| 203 | ;
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| 204 | mov eax, 0C0300000h
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| 205 | movd xmm0, eax
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| 206 | mov rbx, -1 ; make sure high dword is not zero
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| 207 | cvtss2si ebx, xmm0 ; result is -3
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| 208 | mov eax, -3 ; high dword of rax zeroed
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| 209 | TEST_ASSERT_SIMPLE rbx, rax, jz, "CVTSS2SI EBX"
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| 210 |
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| 211 | mov eax, 0C0300000h
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| 212 | movd xmm0, eax
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| 213 | mov rbx, -1
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| 214 | cvttss2si ebx, xmm0 ; result is -2
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| 215 | mov eax, -2
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| 216 | TEST_ASSERT_SIMPLE rbx, rax, jz, "CVTTSS2SI EBX"
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| 217 |
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| 218 | ;
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| 219 | ; Load 64-bit double -2.75 into XMM0
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| 220 | ;
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| 221 | mov rax, 0C006000000000000h
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| 222 | movd xmm0, rax
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| 223 | mov rbx, -1
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| 224 | cvtsd2si ebx, xmm0
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| 225 | mov eax, -3
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| 226 | TEST_ASSERT_SIMPLE rbx, rax, jz, "CVTSD2SI EBX"
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| 227 |
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| 228 | mov rax, 0C006000000000000h
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| 229 | mov rbx, -1
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| 230 | movd xmm0, rax
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| 231 | cvttsd2si ebx, xmm0
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| 232 | mov eax,-2
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| 233 | TEST_ASSERT_SIMPLE rbx, rax, jz, "CVTTSD2SI EBX"
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| 234 |
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| 235 | ;
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| 236 | ; Restore prior CR4 value
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| 237 | ;
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| 238 | mov cr4,rsi
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| 239 | %endif
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| 240 |
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| 241 | ;
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| 242 | ; Done.
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| 243 | ;
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| 244 | call TMPL_NM_CMN(TestSubDone)
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| 245 | .done:
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| 246 | mov xSP, xSI
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| 247 | add xSP, 80h
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| 248 | pop xSI
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| 249 | pop xDI
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| 250 | pop xDX
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| 251 | pop xCX
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| 252 | pop xBX
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| 253 | pop sAX
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| 254 | leave
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| 255 | ret
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| 256 |
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| 257 | .skip:
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| 258 | mov xAX, .s_szSse2Missing
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| 259 | call TMPL_NM_CMN(TestSubDone)
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| 260 | jmp .done
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| 261 |
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| 262 | .s_szSubTestName:
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| 263 | db TMPL_MODE_STR, ', cvtss2si et al.', 0
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| 264 | .s_szSse2Missing:
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| 265 | db 'SSE2 is missing', 0
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| 266 | ENDPROC TMPL_NM(TestCvtSize)
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| 267 |
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| 268 |
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| 269 | ;;
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| 270 | ; Proving intel manual wrong about using REX.X for BSWAP R8-R15 on 64-bit.
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| 271 | ; Checking the 'undefined' 16-bit bswap behavior.
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| 272 | ;
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| 273 | ; @uses No registers, but BS2_SEL_SPARE0 is trashed.
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| 274 | ;
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| 275 | BEGINPROC TMPL_NM(TestBSwap)
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| 276 | push xBP
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| 277 | mov xBP, xSP
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| 278 | push sAX
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| 279 | push xBX
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| 280 | push xCX
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| 281 | push xDX
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| 282 | push xDI
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| 283 | push xSI
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| 284 | sub xSP, 80h ; iret stack frame space.
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| 285 | mov xSI, xSP ; Save the stack register.
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| 286 |
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| 287 | mov xAX, .s_szSubTestName
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| 288 | call TMPL_NM_CMN(TestSub)
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| 289 |
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| 290 | ;
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| 291 | ; Assert sanity.
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| 292 | ;
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| 293 | mov eax, 11223344h
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| 294 | bswap eax
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| 295 | TEST_ASSERT_SIMPLE eax, 44332211h, jz, "32-bit BSWAP EAX"
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| 296 |
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| 297 | ;
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| 298 | ; Buggy manual (325383-041US, December 2011).
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| 299 | ;
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| 300 | %ifdef TMPL_64BIT
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| 301 | push r8
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| 302 |
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| 303 | mov r8d, 55667788h
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| 304 | mov eax, 55667788h
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| 305 | db X86_OP_REX_X
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| 306 | bswap eax ; does it access r8 or eax?
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| 307 | TEST_ASSERT_SIMPLE eax, 88776655h, jz, "REX.X BSWAP EAX - Wrong EAX."
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| 308 | TEST_ASSERT_SIMPLE r8, 55667788h, jz, "REX.X BSWAP EAX - Wrong R8."
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| 309 |
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| 310 | mov r8d, 55667788h
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| 311 | mov eax, 55667788h
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| 312 | db X86_OP_REX_R
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| 313 | bswap eax ; does it access r8 or eax?
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| 314 | TEST_ASSERT_SIMPLE eax, 88776655h, jz, "REX.R BSWAP EAX - Wrong EAX."
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| 315 | TEST_ASSERT_SIMPLE r8, 55667788h, jz, "REX.R BSWAP EAX - Wrong R8."
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| 316 |
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| 317 | mov r8d, 55667788h
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| 318 | mov eax, 55667788h
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| 319 | db X86_OP_REX_B
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| 320 | bswap eax ; does it access r8 or eax?
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| 321 | TEST_ASSERT_SIMPLE rax, 55667788h, jz, "REX.B BSWAP R8D - Wrong RAX."
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| 322 | TEST_ASSERT_SIMPLE r8d, 88776655h, jz, "REX.B BSWAP R8D - Wrong R8D."
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| 323 |
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| 324 | pop r8
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| 325 | %endif
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| 326 |
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| 327 | ;
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| 328 | ; 'Undefined' 16-bit behavior.
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| 329 | ;
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| 330 | ; Zeroing of the lower 16-bits has been observed on:
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| 331 | ; - Intel(R) Core(TM) i7-3960X CPU @ 3.30GHz
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| 332 | ;
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| 333 | %ifndef TestBSwap16_defined
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| 334 | %define TestBSwap16_defined
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| 335 | %macro TestBSwap16 3,
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| 336 | mov %3, %2 ; save the primary register.
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| 337 | %ifdef TMPL_64BIT
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| 338 | mov %2, 0ffffffff98765432h ; Set the upper bit as well.
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| 339 | %else
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| 340 | mov %2, 98765432h
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| 341 | %endif
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| 342 | %ifndef TMPL_16BIT
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| 343 | db X86_OP_PRF_SIZE_OP
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| 344 | %endif
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| 345 | bswap %1
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| 346 | xchg %2, %3 ; Restore and save the result (xSP).
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| 347 | TEST_ASSERT_SIMPLE %3, 98760000h, jz, "Unexpected 16-bit BSWAP error."
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| 348 | %endmacro
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| 349 | %endif
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| 350 |
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| 351 | TestBSwap16 eax, sAX, sSI
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| 352 | TestBSwap16 ebx, sBX, sSI
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| 353 | TestBSwap16 ecx, sCX, sSI
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| 354 | TestBSwap16 edx, sDX, sSI
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| 355 | TestBSwap16 esp, sSP, sSI
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| 356 | TestBSwap16 ebp, sBP, sSI
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| 357 | TestBSwap16 edi, sDI, sSI
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| 358 | TestBSwap16 esi, sSI, sDI
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| 359 | %ifdef TMPL_64BIT
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| 360 | TestBSwap16 r8d, r8, rax
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| 361 | TestBSwap16 r9d, r9, rax
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| 362 | TestBSwap16 r10d, r10, rax
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| 363 | TestBSwap16 r11d, r11, rax
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| 364 | TestBSwap16 r12d, r12, rax
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| 365 | TestBSwap16 r13d, r13, rax
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| 366 | TestBSwap16 r14d, r14, rax
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| 367 | TestBSwap16 r15d, r15, rax
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| 368 | %endif
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| 369 |
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| 370 | ;
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| 371 | ; Done.
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| 372 | ;
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| 373 | call TMPL_NM_CMN(TestSubDone)
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| 374 | .done:
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| 375 | mov xSP, xSI
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| 376 | add xSP, 80h
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| 377 | pop xSI
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| 378 | pop xDI
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| 379 | pop xDX
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| 380 | pop xCX
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| 381 | pop xBX
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| 382 | pop sAX
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| 383 | leave
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| 384 | ret
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| 385 |
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| 386 | .s_szSubTestName:
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| 387 | db TMPL_MODE_STR, ', bswap', 0
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| 388 | ENDPROC TMPL_NM(TestBSwap)
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| 389 |
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| 390 |
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| 391 | ;;
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| 392 | ; Do the tests for this mode.
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| 393 | ;
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| 394 | ; @uses nothing
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| 395 | ;
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| 396 | BEGINCODELOW
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| 397 | BITS 16
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| 398 | BEGINPROC TMPL_NM(DoTestsForMode_rm)
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| 399 | push bp
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| 400 | mov bp, sp
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| 401 | push ax
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| 402 |
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| 403 | ;
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| 404 | ; Check if the mode and NX is supported, do the switch.
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| 405 | ;
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| 406 | call TMPL_NM(Bs2IsModeSupported_rm)
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| 407 | jz .done
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| 408 | call TMPL_NM(Bs2EnterMode_rm)
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| 409 | BITS TMPL_BITS
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| 410 |
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| 411 | ;
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| 412 | ; Test exception handler basics using INT3 and #BP.
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| 413 | ;
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| 414 |
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| 415 | call TMPL_NM(TestMemFences)
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| 416 | call TMPL_NM(TestBSwap)
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| 417 | %ifdef TMPL_64BIT
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| 418 | ; Specifically tests 64-bit behavior.
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| 419 | call TMPL_NM(TestCvtSize)
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| 420 | %endif
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| 421 |
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| 422 | ;
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| 423 | ; Back to real mode.
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|---|
| 424 | ;
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|---|
| 425 | call TMPL_NM(Bs2ExitMode)
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| 426 | BITS 16
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| 427 | call Bs2DisableNX_r86
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|---|
| 428 |
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| 429 | .done:
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| 430 | pop ax
|
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| 431 | leave
|
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| 432 | ret
|
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| 433 | ENDPROC TMPL_NM(DoTestsForMode_rm)
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| 434 | TMPL_BEGINCODE
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|---|
| 435 | BITS TMPL_BITS
|
|---|
| 436 |
|
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| 437 | %include "bootsector2-template-footer.mac"
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| 438 |
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