VBoxCpuReport.cpp@ 50606

最後變更在這個檔案從50606是 50590,由 vboxsync 提交於 11 年前
CPUM,VMM: More work related to bus, cpu and tsc frequency info. Should cover older core and p6 as well as p4 now.
屬性 svn:eol-style 設為 `native` 屬性 svn:keywords 設為 `Author Date Id Revision`
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1	/* $Id: VBoxCpuReport.cpp 50590 2014-02-25 18:51:23Z vboxsync $ */
2	/** @file
3	* VBoxCpuReport - Produces the basis for a CPU DB entry.
4	*/
5
6	/*
7	* Copyright (C) 2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.alldomusa.eu.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#include <iprt/asm.h>
23	#include <iprt/asm-amd64-x86.h>
24	#include <iprt/buildconfig.h>
25	#include <iprt/ctype.h>
26	#include <iprt/file.h>
27	#include <iprt/getopt.h>
28	#include <iprt/initterm.h>
29	#include <iprt/message.h>
30	#include <iprt/mem.h>
31	#include <iprt/path.h>
32	#include <iprt/string.h>
33	#include <iprt/stream.h>
34	#include <iprt/symlink.h>
35	#include <iprt/thread.h>
36	#include <iprt/time.h>
37
38	#include <VBox/err.h>
39	#include <VBox/vmm/cpum.h>
40	#include <VBox/sup.h>
41
42
43	/*******************************************************************************
44	* Structures and Typedefs *
45	*******************************************************************************/
46	/** Write only register. */
47	#define VBCPUREPMSR_F_WRITE_ONLY RT_BIT(0)
48
49	typedef struct VBCPUREPMSR
50	{
51	/** The first MSR register number. */
52	uint32_t uMsr;
53	/** Flags (MSRREPORT_F_XXX). */
54	uint32_t fFlags;
55	/** The value we read, unless write-only. */
56	uint64_t uValue;
57	} VBCPUREPMSR;
58
59
60	/*******************************************************************************
61	* Global Variables *
62	*******************************************************************************/
63	/** The CPU vendor. Used by the MSR code. */
64	static CPUMCPUVENDOR g_enmVendor = CPUMCPUVENDOR_INVALID;
65	/** The CPU microarchitecture. Used by the MSR code. */
66	static CPUMMICROARCH g_enmMicroarch = kCpumMicroarch_Invalid;
67	/** Set if g_enmMicroarch indicates an Intel NetBurst CPU. */
68	static bool g_fIntelNetBurst = false;
69	/** The alternative report stream. */
70	static PRTSTREAM g_pReportOut;
71	/** The alternative debug stream. */
72	static PRTSTREAM g_pDebugOut;
73
74	/** Snooping info storage for vbCpuRepGuessScalableBusFrequencyName. */
75	static uint64_t g_uMsrIntelP6FsbFrequency = UINT64_MAX;
76
77
78	static void vbCpuRepDebug(const char *pszMsg, ...)
79	{
80	va_list va;
81
82	/* Always print a copy of the report to standard error. */
83	va_start(va, pszMsg);
84	RTStrmPrintfV(g_pStdErr, pszMsg, va);
85	va_end(va);
86	RTStrmFlush(g_pStdErr);
87
88	/* Alternatively, also print to a log file. */
89	if (g_pDebugOut)
90	{
91	va_start(va, pszMsg);
92	RTStrmPrintfV(g_pDebugOut, pszMsg, va);
93	va_end(va);
94	RTStrmFlush(g_pDebugOut);
95	}
96
97	/* Give the output device a chance to write / display it. */
98	RTThreadSleep(1);
99	}
100
101
102	static void vbCpuRepPrintf(const char *pszMsg, ...)
103	{
104	va_list va;
105
106	/* Output to report file, if requested. */
107	if (g_pReportOut)
108	{
109	va_start(va, pszMsg);
110	RTStrmPrintfV(g_pReportOut, pszMsg, va);
111	va_end(va);
112	RTStrmFlush(g_pReportOut);
113	}
114
115	/* Always print a copy of the report to standard out. */
116	va_start(va, pszMsg);
117	RTStrmPrintfV(g_pStdOut, pszMsg, va);
118	va_end(va);
119	RTStrmFlush(g_pStdOut);
120	}
121
122
123
124	static int vbCpuRepMsrsAddOne(VBCPUREPMSR *ppaMsrs, uint32_t pcMsrs,
125	uint32_t uMsr, uint64_t uValue, uint32_t fFlags)
126	{
127	/*
128	* Grow the array?
129	*/
130	uint32_t cMsrs = *pcMsrs;
131	if ((cMsrs % 64) == 0)
132	{
133	void pvNew = RTMemRealloc(ppaMsrs, (cMsrs + 64) * sizeof(**ppaMsrs));
134	if (!pvNew)
135	{
136	RTMemFree(*ppaMsrs);
137	*ppaMsrs = NULL;
138	*pcMsrs = 0;
139	return VERR_NO_MEMORY;
140	}
141	ppaMsrs = (VBCPUREPMSR )pvNew;
142	}
143
144	/*
145	* Add it.
146	*/
147	VBCPUREPMSR pEntry = ppaMsrs + cMsrs;
148	pEntry->uMsr = uMsr;
149	pEntry->fFlags = fFlags;
150	pEntry->uValue = uValue;
151	*pcMsrs = cMsrs + 1;
152
153	return VINF_SUCCESS;
154	}
155
156
157	/**
158	* Returns the max physical address width as a number of bits.
159	*
160	* @returns Bit count.
161	*/
162	static uint8_t vbCpuRepGetPhysAddrWidth(void)
163	{
164	uint8_t cMaxWidth;
165	uint32_t cMaxExt = ASMCpuId_EAX(0x80000000);
166	if (!ASMHasCpuId())
167	cMaxWidth = 32;
168	else if (ASMIsValidExtRange(cMaxExt)&& cMaxExt >= 0x80000008)
169	cMaxWidth = ASMCpuId_EAX(0x80000008) & 0xff;
170	else if ( ASMIsValidStdRange(ASMCpuId_EAX(0))
171	&& (ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_PSE36))
172	cMaxWidth = 36;
173	else
174	cMaxWidth = 32;
175	return cMaxWidth;
176	}
177
178
179	static bool vbCpuRepSupportsPae(void)
180	{
181	return ASMHasCpuId()
182	&& ASMIsValidStdRange(ASMCpuId_EAX(0))
183	&& (ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_PAE);
184	}
185
186
187	static bool vbCpuRepSupportsLongMode(void)
188	{
189	return ASMHasCpuId()
190	&& ASMIsValidExtRange(ASMCpuId_EAX(0x80000000))
191	&& (ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
192	}
193
194
195	static bool vbCpuRepSupportsNX(void)
196	{
197	return ASMHasCpuId()
198	&& ASMIsValidExtRange(ASMCpuId_EAX(0x80000000))
199	&& (ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_NX);
200	}
201
202
203	static bool vbCpuRepSupportsX2Apic(void)
204	{
205	return ASMHasCpuId()
206	&& ASMIsValidStdRange(ASMCpuId_EAX(0))
207	&& (ASMCpuId_ECX(1) & X86_CPUID_FEATURE_ECX_X2APIC);
208	}
209
210
211
212	static bool msrProberWrite(uint32_t uMsr, uint64_t uValue)
213	{
214	bool fGp;
215	int rc = SUPR3MsrProberWrite(uMsr, NIL_RTCPUID, uValue, &fGp);
216	AssertRC(rc);
217	return RT_SUCCESS(rc) && !fGp;
218	}
219
220
221	static bool msrProberRead(uint32_t uMsr, uint64_t *puValue)
222	{
223	*puValue = 0;
224	bool fGp;
225	int rc = SUPR3MsrProberRead(uMsr, NIL_RTCPUID, puValue, &fGp);
226	AssertRC(rc);
227	return RT_SUCCESS(rc) && !fGp;
228	}
229
230
231	/** Tries to modify the register by writing the original value to it. */
232	static bool msrProberModifyNoChange(uint32_t uMsr)
233	{
234	SUPMSRPROBERMODIFYRESULT Result;
235	int rc = SUPR3MsrProberModify(uMsr, NIL_RTCPUID, UINT64_MAX, 0, &Result);
236	return RT_SUCCESS(rc)
237	&& !Result.fBeforeGp
238	&& !Result.fModifyGp
239	&& !Result.fAfterGp
240	&& !Result.fRestoreGp;
241	}
242
243
244	/** Tries to modify the register by writing zero to it. */
245	static bool msrProberModifyZero(uint32_t uMsr)
246	{
247	SUPMSRPROBERMODIFYRESULT Result;
248	int rc = SUPR3MsrProberModify(uMsr, NIL_RTCPUID, 0, 0, &Result);
249	return RT_SUCCESS(rc)
250	&& !Result.fBeforeGp
251	&& !Result.fModifyGp
252	&& !Result.fAfterGp
253	&& !Result.fRestoreGp;
254	}
255
256
257	/**
258	* Tries to modify each bit in the MSR and see if we can make it change.
259	*
260	* @returns VBox status code.
261	* @param uMsr The MSR.
262	* @param pfIgnMask The ignore mask to update.
263	* @param pfGpMask The GP mask to update.
264	* @param fSkipMask Mask of bits to skip.
265	*/
266	static int msrProberModifyBitChanges(uint32_t uMsr, uint64_t pfIgnMask, uint64_t pfGpMask, uint64_t fSkipMask)
267	{
268	for (unsigned iBit = 0; iBit < 64; iBit++)
269	{
270	uint64_t fBitMask = RT_BIT_64(iBit);
271	if (fBitMask & fSkipMask)
272	continue;
273
274	/* Set it. */
275	SUPMSRPROBERMODIFYRESULT ResultSet;
276	int rc = SUPR3MsrProberModify(uMsr, NIL_RTCPUID, ~fBitMask, fBitMask, &ResultSet);
277	if (RT_FAILURE(rc))
278	return RTMsgErrorRc(rc, "SUPR3MsrProberModify(%#x,,%#llx,%#llx,): %Rrc", uMsr, ~fBitMask, fBitMask, rc);
279
280	/* Clear it. */
281	SUPMSRPROBERMODIFYRESULT ResultClear;
282	rc = SUPR3MsrProberModify(uMsr, NIL_RTCPUID, ~fBitMask, 0, &ResultClear);
283	if (RT_FAILURE(rc))
284	return RTMsgErrorRc(rc, "SUPR3MsrProberModify(%#x,,%#llx,%#llx,): %Rrc", uMsr, ~fBitMask, 0, rc);
285
286	if (ResultSet.fModifyGp \|\| ResultClear.fModifyGp)
287	*pfGpMask \|= fBitMask;
288	else if ( ( ((ResultSet.uBefore ^ ResultSet.uAfter) & fBitMask) == 0
289	&& !ResultSet.fBeforeGp
290	&& !ResultSet.fAfterGp)
291	&& ( ((ResultClear.uBefore ^ ResultClear.uAfter) & fBitMask) == 0
292	&& !ResultClear.fBeforeGp
293	&& !ResultClear.fAfterGp) )
294	*pfIgnMask \|= fBitMask;
295	}
296
297	return VINF_SUCCESS;
298	}
299
300
301	/**
302	* Tries to modify one bit.
303	*
304	* @retval -2 on API error.
305	* @retval -1 on \#GP.
306	* @retval 0 if ignored.
307	* @retval 1 if it changed.
308	*
309	* @param uMsr The MSR.
310	* @param iBit The bit to try modify.
311	*/
312	static int msrProberModifyBit(uint32_t uMsr, unsigned iBit)
313	{
314	uint64_t fBitMask = RT_BIT_64(iBit);
315
316	/* Set it. */
317	SUPMSRPROBERMODIFYRESULT ResultSet;
318	int rc = SUPR3MsrProberModify(uMsr, NIL_RTCPUID, ~fBitMask, fBitMask, &ResultSet);
319	if (RT_FAILURE(rc))
320	return RTMsgErrorRc(-2, "SUPR3MsrProberModify(%#x,,%#llx,%#llx,): %Rrc", uMsr, ~fBitMask, fBitMask, rc);
321
322	/* Clear it. */
323	SUPMSRPROBERMODIFYRESULT ResultClear;
324	rc = SUPR3MsrProberModify(uMsr, NIL_RTCPUID, ~fBitMask, 0, &ResultClear);
325	if (RT_FAILURE(rc))
326	return RTMsgErrorRc(-2, "SUPR3MsrProberModify(%#x,,%#llx,%#llx,): %Rrc", uMsr, ~fBitMask, 0, rc);
327
328	if (ResultSet.fModifyGp \|\| ResultClear.fModifyGp)
329	return -1;
330
331	if ( ( ((ResultSet.uBefore ^ ResultSet.uAfter) & fBitMask) != 0
332	&& !ResultSet.fBeforeGp
333	&& !ResultSet.fAfterGp)
334	\|\| ( ((ResultClear.uBefore ^ ResultClear.uAfter) & fBitMask) != 0
335	&& !ResultClear.fBeforeGp
336	&& !ResultClear.fAfterGp) )
337	return 1;
338
339	return 0;
340	}
341
342
343	/**
344	* Tries to do a simple AND+OR change and see if we \#GP or not.
345	*
346	* @retval @c true if successfully modified.
347	* @retval @c false if \#GP or other error.
348	*
349	* @param uMsr The MSR.
350	* @param fAndMask The AND mask.
351	* @param fOrMask The OR mask.
352	*/
353	static bool msrProberModifySimpleGp(uint32_t uMsr, uint64_t fAndMask, uint64_t fOrMask)
354	{
355	SUPMSRPROBERMODIFYRESULT Result;
356	int rc = SUPR3MsrProberModify(uMsr, NIL_RTCPUID, fAndMask, fOrMask, &Result);
357	if (RT_FAILURE(rc))
358	{
359	RTMsgError("SUPR3MsrProberModify(%#x,,%#llx,%#llx,): %Rrc", uMsr, fAndMask, fOrMask, rc);
360	return false;
361	}
362	return !Result.fBeforeGp
363	&& !Result.fModifyGp
364	&& !Result.fAfterGp
365	&& !Result.fRestoreGp;
366	}
367
368
369
370
371	/**
372	* Combination of the basic tests.
373	*
374	* @returns VBox status code.
375	* @param uMsr The MSR.
376	* @param fSkipMask Mask of bits to skip.
377	* @param pfReadOnly Where to return read-only status.
378	* @param pfIgnMask Where to return the write ignore mask. Need not
379	* be initialized.
380	* @param pfGpMask Where to return the write GP mask. Need not
381	* be initialized.
382	*/
383	static int msrProberModifyBasicTests(uint32_t uMsr, uint64_t fSkipMask, bool pfReadOnly, uint64_t pfIgnMask, uint64_t *pfGpMask)
384	{
385	if (msrProberModifyNoChange(uMsr))
386	{
387	*pfReadOnly = false;
388	*pfIgnMask = 0;
389	*pfGpMask = 0;
390	return msrProberModifyBitChanges(uMsr, pfIgnMask, pfGpMask, fSkipMask);
391	}
392
393	*pfReadOnly = true;
394	*pfIgnMask = 0;
395	*pfGpMask = UINT64_MAX;
396	return VINF_SUCCESS;
397	}
398
399
400
401	/**
402	* Determines for the MSR AND mask.
403	*
404	* Older CPUs doesn't necessiarly implement all bits of the MSR register number.
405	* So, we have to approximate how many are used so we don't get an overly large
406	* and confusing set of MSRs when probing.
407	*
408	* @returns The mask.
409	*/
410	static uint32_t determineMsrAndMask(void)
411	{
412	#define VBCPUREP_MASK_TEST_MSRS 7
413	static uint32_t const s_aMsrs[VBCPUREP_MASK_TEST_MSRS] =
414	{
415	/* Try a bunch of mostly read only registers: */
416	MSR_P5_MC_TYPE, MSR_IA32_PLATFORM_ID, MSR_IA32_MTRR_CAP, MSR_IA32_MCG_CAP, MSR_IA32_CR_PAT,
417	/* Then some which aren't supposed to be present on any CPU: */
418	0x00000015, 0x00000019,
419	};
420
421	/* Get the base values. */
422	uint64_t auBaseValues[VBCPUREP_MASK_TEST_MSRS];
423	for (unsigned i = 0; i < RT_ELEMENTS(s_aMsrs); i++)
424	{
425	if (!msrProberRead(s_aMsrs[i], &auBaseValues[i]))
426	auBaseValues[i] = UINT64_MAX;
427	//vbCpuRepDebug("Base: %#x -> %#llx\n", s_aMsrs[i], auBaseValues[i]);
428	}
429
430	/* Do the probing. */
431	unsigned iBit;
432	for (iBit = 31; iBit > 8; iBit--)
433	{
434	uint64_t fMsrOrMask = RT_BIT_64(iBit);
435	for (unsigned iTest = 0; iTest <= 64 && fMsrOrMask < UINT32_MAX; iTest++)
436	{
437	for (unsigned i = 0; i < RT_ELEMENTS(s_aMsrs); i++)
438	{
439	uint64_t uValue;
440	if (!msrProberRead(s_aMsrs[i] \| fMsrOrMask, &uValue))
441	uValue = UINT64_MAX;
442	if (uValue != auBaseValues[i])
443	{
444	uint32_t fMsrMask = iBit >= 31 ? UINT32_MAX : RT_BIT_32(iBit + 1) - 1;
445	vbCpuRepDebug("MSR AND mask: quit on iBit=%u uMsr=%#x (%#x) %llx != %llx => fMsrMask=%#x\n",
446	iBit, s_aMsrs[i] \| (uint32_t)fMsrOrMask, s_aMsrs[i], uValue, auBaseValues[i], fMsrMask);
447	return fMsrMask;
448	}
449	}
450
451	/* Advance. */
452	if (iBit <= 6)
453	fMsrOrMask += RT_BIT_64(iBit);
454	else if (iBit <= 11)
455	fMsrOrMask += RT_BIT_64(iBit) * 33;
456	else if (iBit <= 16)
457	fMsrOrMask += RT_BIT_64(iBit) * 1025;
458	else if (iBit <= 22)
459	fMsrOrMask += RT_BIT_64(iBit) * 65537;
460	else
461	fMsrOrMask += RT_BIT_64(iBit) * 262145;
462	}
463	}
464
465	uint32_t fMsrMask = RT_BIT_32(iBit + 1) - 1;
466	vbCpuRepDebug("MSR AND mask: less that %u bits that matters?!? => fMsrMask=%#x\n", iBit + 1, fMsrMask);
467	return fMsrMask;
468	}
469
470
471	static int findMsrs(VBCPUREPMSR *ppaMsrs, uint32_t pcMsrs, uint32_t fMsrMask)
472	{
473	/*
474	* Gather them.
475	*/
476	static struct { uint32_t uFirst, cMsrs; } const s_aRanges[] =
477	{
478	{ 0x00000000, 0x00042000 },
479	{ 0x10000000, 0x00001000 },
480	{ 0x20000000, 0x00001000 },
481	{ 0x40000000, 0x00012000 },
482	{ 0x80000000, 0x00012000 },
483	{ 0xc0000000, 0x00022000 }, /* Had some trouble here on solaris with the tstVMM setup. */
484	};
485
486	*pcMsrs = 0;
487	*ppaMsrs = NULL;
488
489	for (unsigned i = 0; i < RT_ELEMENTS(s_aRanges); i++)
490	{
491	uint32_t uMsr = s_aRanges[i].uFirst;
492	if ((uMsr & fMsrMask) != uMsr)
493	continue;
494	uint32_t cLeft = s_aRanges[i].cMsrs;
495	while (cLeft-- > 0 && (uMsr & fMsrMask) == uMsr)
496	{
497	if ((uMsr & 0xfff) == 0)
498	{
499	vbCpuRepDebug("testing %#x...\n", uMsr);
500	RTThreadSleep(22);
501	}
502	#if 0
503	else if (uMsr >= 0x00003170 && uMsr <= 0xc0000090)
504	{
505	vbCpuRepDebug("testing %#x...\n", uMsr);
506	RTThreadSleep(250);
507	}
508	#endif
509	/* Skip 0xc0011012..13 as it seems to be bad for our health (Phenom II X6 1100T). */
510	if ((uMsr >= 0xc0011012 && uMsr <= 0xc0011013) && g_enmVendor == CPUMCPUVENDOR_AMD)
511	vbCpuRepDebug("Skipping %#x\n", uMsr);
512	else
513	{
514	/* Read probing normally does it. */
515	uint64_t uValue = 0;
516	bool fGp = true;
517	int rc = SUPR3MsrProberRead(uMsr, NIL_RTCPUID, &uValue, &fGp);
518	if (RT_FAILURE(rc))
519	{
520	RTMemFree(*ppaMsrs);
521	*ppaMsrs = NULL;
522	return RTMsgErrorRc(rc, "SUPR3MsrProberRead failed on %#x: %Rrc\n", uMsr, rc);
523	}
524
525	uint32_t fFlags;
526	if (!fGp)
527	fFlags = 0;
528	/* VIA HACK - writing to 0x0000317e on a quad core make the core unresponsive. */
529	else if (uMsr == 0x0000317e && g_enmVendor == CPUMCPUVENDOR_VIA)
530	{
531	uValue = 0;
532	fFlags = VBCPUREPMSR_F_WRITE_ONLY;
533	fGp = *pcMsrs == 0
534	\|\| (ppaMsrs)[pcMsrs - 1].uMsr != 0x0000317d
535	\|\| (ppaMsrs)[pcMsrs - 1].fFlags != VBCPUREPMSR_F_WRITE_ONLY;
536	}
537	else
538	{
539	/* Is it a write only register? */
540	#if 0
541	if (uMsr >= 0x00003170 && uMsr <= 0xc0000090)
542	{
543	vbCpuRepDebug("test writing %#x...\n", uMsr);
544	RTThreadSleep(250);
545	}
546	#endif
547	fGp = true;
548	rc = SUPR3MsrProberWrite(uMsr, NIL_RTCPUID, 0, &fGp);
549	if (RT_FAILURE(rc))
550	{
551	RTMemFree(*ppaMsrs);
552	*ppaMsrs = NULL;
553	return RTMsgErrorRc(rc, "SUPR3MsrProberWrite failed on %#x: %Rrc\n", uMsr, rc);
554	}
555	uValue = 0;
556	fFlags = VBCPUREPMSR_F_WRITE_ONLY;
557
558	/*
559	* Tweaks. On Intel CPUs we've got trouble detecting
560	* IA32_BIOS_UPDT_TRIG (0x00000079), so we have to add it manually here.
561	* Ditto on AMD with PATCH_LOADER (0xc0010020).
562	*/
563	if ( uMsr == 0x00000079
564	&& fGp
565	&& g_enmMicroarch >= kCpumMicroarch_Intel_P6_Core_Atom_First
566	&& g_enmMicroarch <= kCpumMicroarch_Intel_End)
567	fGp = false;
568	if ( uMsr == 0xc0010020
569	&& fGp
570	&& g_enmMicroarch >= kCpumMicroarch_AMD_K8_First
571	&& g_enmMicroarch <= kCpumMicroarch_AMD_End)
572	fGp = false;
573	}
574
575	if (!fGp)
576	{
577	/* Add it. */
578	rc = vbCpuRepMsrsAddOne(ppaMsrs, pcMsrs, uMsr, uValue, fFlags);
579	if (RT_FAILURE(rc))
580	return RTMsgErrorRc(rc, "Out of memory (uMsr=%#x).\n", uMsr);
581	if ( g_enmVendor != CPUMCPUVENDOR_VIA
582	\|\| uValue
583	\|\| fFlags)
584	vbCpuRepDebug("%#010x: uValue=%#llx fFlags=%#x\n", uMsr, uValue, fFlags);
585	}
586	}
587
588	uMsr++;
589	}
590	}
591
592	return VINF_SUCCESS;
593	}
594
595	/**
596	* Get the name of the specified MSR, if we know it and can handle it.
597	*
598	* Do _NOT_ add any new names here without ALSO at the SAME TIME making sure it
599	* is handled correctly by the PROBING CODE and REPORTED correctly!!
600	*
601	* @returns Pointer to name if handled, NULL if not yet explored.
602	* @param uMsr The MSR in question.
603	*/
604	static const char *getMsrNameHandled(uint32_t uMsr)
605	{
606	/** @todo figure out where NCU_EVENT_CORE_MASK might be... */
607	switch (uMsr)
608	{
609	case 0x00000000: return "IA32_P5_MC_ADDR";
610	case 0x00000001: return "IA32_P5_MC_TYPE";
611	case 0x00000006:
612	if (g_enmMicroarch >= kCpumMicroarch_Intel_First && g_enmMicroarch <= kCpumMicroarch_Intel_P6_Core_Atom_First)
613	return NULL; /* TR4 / cache tag on Pentium, but that's for later. */
614	return "IA32_MONITOR_FILTER_LINE_SIZE";
615	//case 0x0000000e: return "P?_TR12"; /* K6-III docs */
616	case 0x00000010: return "IA32_TIME_STAMP_COUNTER";
617	case 0x00000017: return "IA32_PLATFORM_ID";
618	case 0x00000018: return "P6_UNK_0000_0018"; /* P6_M_Dothan. */
619	case 0x0000001b: return "IA32_APIC_BASE";
620	case 0x00000021: return "C2_UNK_0000_0021"; /* Core2_Penryn */
621	case 0x0000002a: return g_fIntelNetBurst ? "P4_EBC_HARD_POWERON" : "EBL_CR_POWERON";
622	case 0x0000002b: return g_fIntelNetBurst ? "P4_EBC_SOFT_POWERON" : NULL;
623	case 0x0000002c: return g_fIntelNetBurst ? "P4_EBC_FREQUENCY_ID" : NULL;
624	case 0x0000002e: return "I7_UNK_0000_002e"; /* SandyBridge, IvyBridge. */
625	case 0x0000002f: return "P6_UNK_0000_002f"; /* P6_M_Dothan. */
626	case 0x00000032: return "P6_UNK_0000_0032"; /* P6_M_Dothan. */
627	case 0x00000033: return "TEST_CTL";
628	case 0x00000034: return "P6_UNK_0000_0034"; /* P6_M_Dothan. */
629	case 0x00000035: return "P6_UNK_0000_0035"; /* P6_M_Dothan. */
630	case 0x00000036: return "I7_UNK_0000_0036"; /* SandyBridge, IvyBridge. */
631	case 0x00000039: return "C2_UNK_0000_0039"; /* Core2_Penryn */
632	case 0x0000003a: return "IA32_FEATURE_CONTROL";
633	case 0x0000003b: return "P6_UNK_0000_003b"; /* P6_M_Dothan. */
634	case 0x0000003e: return "I7_UNK_0000_003e"; /* SandyBridge, IvyBridge. */
635	case 0x0000003f: return "P6_UNK_0000_003f"; /* P6_M_Dothan. */
636	case 0x00000040: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_0_FROM_IP" : "MSR_LASTBRANCH_0";
637	case 0x00000041: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_1_FROM_IP" : "MSR_LASTBRANCH_1";
638	case 0x00000042: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_2_FROM_IP" : "MSR_LASTBRANCH_2";
639	case 0x00000043: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_3_FROM_IP" : "MSR_LASTBRANCH_3";
640	case 0x00000044: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_4_FROM_IP" : "MSR_LASTBRANCH_4";
641	case 0x00000045: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_5_FROM_IP" : "MSR_LASTBRANCH_5";
642	case 0x00000046: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_6_FROM_IP" : "MSR_LASTBRANCH_6";
643	case 0x00000047: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_7_FROM_IP" : "MSR_LASTBRANCH_7";
644	case 0x00000048: return "MSR_LASTBRANCH_8"; /??/
645	case 0x00000049: return "MSR_LASTBRANCH_9"; /??/
646	case 0x0000004a: return "P6_UNK_0000_004a"; /* P6_M_Dothan. */
647	case 0x0000004b: return "P6_UNK_0000_004b"; /* P6_M_Dothan. */
648	case 0x0000004c: return "P6_UNK_0000_004c"; /* P6_M_Dothan. */
649	case 0x0000004d: return "P6_UNK_0000_004d"; /* P6_M_Dothan. */
650	case 0x0000004e: return "P6_UNK_0000_004e"; /* P6_M_Dothan. */
651	case 0x0000004f: return "P6_UNK_0000_004f"; /* P6_M_Dothan. */
652	case 0x00000050: return "P6_UNK_0000_0050"; /* P6_M_Dothan. */
653	case 0x00000051: return "P6_UNK_0000_0051"; /* P6_M_Dothan. */
654	case 0x00000052: return "P6_UNK_0000_0052"; /* P6_M_Dothan. */
655	case 0x00000053: return "P6_UNK_0000_0053"; /* P6_M_Dothan. */
656	case 0x00000054: return "P6_UNK_0000_0054"; /* P6_M_Dothan. */
657	case 0x00000060: return "MSR_LASTBRANCH_0_TO_IP"; /* Core2_Penryn */
658	case 0x00000061: return "MSR_LASTBRANCH_1_TO_IP"; /* Core2_Penryn */
659	case 0x00000062: return "MSR_LASTBRANCH_2_TO_IP"; /* Core2_Penryn */
660	case 0x00000063: return "MSR_LASTBRANCH_3_TO_IP"; /* Core2_Penryn */
661	case 0x00000064: return "MSR_LASTBRANCH_4_TO_IP"; /* Atom? */
662	case 0x00000065: return "MSR_LASTBRANCH_5_TO_IP";
663	case 0x00000066: return "MSR_LASTBRANCH_6_TO_IP";
664	case 0x00000067: return "MSR_LASTBRANCH_7_TO_IP";
665	case 0x0000006c: return "P6_UNK_0000_006c"; /* P6_M_Dothan. */
666	case 0x0000006d: return "P6_UNK_0000_006d"; /* P6_M_Dothan. */
667	case 0x0000006e: return "P6_UNK_0000_006e"; /* P6_M_Dothan. */
668	case 0x0000006f: return "P6_UNK_0000_006f"; /* P6_M_Dothan. */
669	case 0x00000079: return "IA32_BIOS_UPDT_TRIG";
670	case 0x00000080: return "P4_UNK_0000_0080";
671	case 0x00000088: return "BBL_CR_D0";
672	case 0x00000089: return "BBL_CR_D1";
673	case 0x0000008a: return "BBL_CR_D2";
674	case 0x0000008b: return g_enmVendor == CPUMCPUVENDOR_AMD ? "AMD_K8_PATCH_LEVEL"
675	: g_fIntelNetBurst ? "IA32_BIOS_SIGN_ID" : "BBL_CR_D3\|BIOS_SIGN";
676	case 0x0000008c: return "P6_UNK_0000_008c"; /* P6_M_Dothan. */
677	case 0x0000008d: return "P6_UNK_0000_008d"; /* P6_M_Dothan. */
678	case 0x0000008e: return "P6_UNK_0000_008e"; /* P6_M_Dothan. */
679	case 0x0000008f: return "P6_UNK_0000_008f"; /* P6_M_Dothan. */
680	case 0x00000090: return "P6_UNK_0000_0090"; /* P6_M_Dothan. */
681	case 0x0000009b: return "IA32_SMM_MONITOR_CTL";
682	case 0x000000a8: return "C2_EMTTM_CR_TABLES_0";
683	case 0x000000a9: return "C2_EMTTM_CR_TABLES_1";
684	case 0x000000aa: return "C2_EMTTM_CR_TABLES_2";
685	case 0x000000ab: return "C2_EMTTM_CR_TABLES_3";
686	case 0x000000ac: return "C2_EMTTM_CR_TABLES_4";
687	case 0x000000ad: return "C2_EMTTM_CR_TABLES_5";
688	case 0x000000ae: return "P6_UNK_0000_00ae"; /* P6_M_Dothan. */
689	case 0x000000c1: return "IA32_PMC0";
690	case 0x000000c2: return "IA32_PMC1";
691	case 0x000000c3: return "IA32_PMC2";
692	case 0x000000c4: return "IA32_PMC3";
693	/* PMC4+ first seen on SandyBridge. The earlier cut off is just to be
694	on the safe side as we must avoid P6_M_Dothan and possibly others. */
695	case 0x000000c5: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First ? "IA32_PMC4" : NULL;
696	case 0x000000c6: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First ? "IA32_PMC5" : NULL;
697	case 0x000000c7: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First ? "IA32_PMC6" : "P6_UNK_0000_00c7"; /* P6_M_Dothan. */
698	case 0x000000c8: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First ? "IA32_PMC7" : NULL;
699	case 0x000000cd: return "MSR_FSB_FREQ"; /* P6_M_Dothan. */
700	case 0x000000ce: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First ? "IA32_PLATFORM_INFO" : "P6_UNK_0000_00ce"; /* P6_M_Dothan. */
701	case 0x000000cf: return "C2_UNK_0000_00cf"; /* Core2_Penryn. */
702	case 0x000000e0: return "C2_UNK_0000_00e0"; /* Core2_Penryn. */
703	case 0x000000e1: return "C2_UNK_0000_00e1"; /* Core2_Penryn. */
704	case 0x000000e2: return "MSR_PKG_CST_CONFIG_CONTROL";
705	case 0x000000e3: return "C2_SMM_CST_MISC_INFO"; /* Core2_Penryn. */
706	case 0x000000e4: return "MSR_PMG_IO_CAPTURE_BASE";
707	case 0x000000e5: return "C2_UNK_0000_00e5"; /* Core2_Penryn. */
708	case 0x000000e7: return "IA32_MPERF";
709	case 0x000000e8: return "IA32_APERF";
710	case 0x000000ee: return "C1_EXT_CONFIG"; /* Core2_Penryn. msrtool lists it for Core1 as well. */
711	case 0x000000fe: return "IA32_MTRRCAP";
712	case 0x00000102: return "I7_IB_UNK_0000_0102"; /* IvyBridge. */
713	case 0x00000103: return "I7_IB_UNK_0000_0103"; /* IvyBridge. */
714	case 0x00000104: return "I7_IB_UNK_0000_0104"; /* IvyBridge. */
715	case 0x00000116: return "BBL_CR_ADDR";
716	case 0x00000118: return "BBL_CR_DECC";
717	case 0x00000119: return "BBL_CR_CTL";
718	case 0x0000011a: return "BBL_CR_TRIG";
719	case 0x0000011b: return "P6_UNK_0000_011b"; /* P6_M_Dothan. */
720	case 0x0000011c: return "C2_UNK_0000_011c"; /* Core2_Penryn. */
721	case 0x0000011e: return "BBL_CR_CTL3";
722	case 0x00000130: return g_enmMicroarch == kCpumMicroarch_Intel_Core7_Westmere
723	\|\| g_enmMicroarch == kCpumMicroarch_Intel_Core7_Nehalem
724	? "CPUID1_FEATURE_MASK" : NULL;
725	case 0x00000131: return g_enmMicroarch == kCpumMicroarch_Intel_Core7_Westmere
726	\|\| g_enmMicroarch == kCpumMicroarch_Intel_Core7_Nehalem
727	? "CPUID80000001_FEATURE_MASK" : "P6_UNK_0000_0131" /* P6_M_Dothan. */;
728	case 0x00000132: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
729	? "CPUID1_FEATURE_MASK" : NULL;
730	case 0x00000133: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
731	? "CPUIDD_01_FEATURE_MASK" : NULL;
732	case 0x00000134: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
733	? "CPUID80000001_FEATURE_MASK" : NULL;
734	case 0x0000013c: return "I7_SB_AES_NI_CTL"; /* SandyBridge. Bit 0 is lock bit, bit 1 disables AES-NI. */
735	case 0x00000140: return "I7_IB_UNK_0000_0140"; /* IvyBridge. */
736	case 0x00000142: return "I7_IB_UNK_0000_0142"; /* IvyBridge. */
737	case 0x0000014e: return "P6_UNK_0000_014e"; /* P6_M_Dothan. */
738	case 0x0000014f: return "P6_UNK_0000_014f"; /* P6_M_Dothan. */
739	case 0x00000150: return "P6_UNK_0000_0150"; /* P6_M_Dothan. */
740	case 0x00000151: return "P6_UNK_0000_0151"; /* P6_M_Dothan. */
741	case 0x00000154: return "P6_UNK_0000_0154"; /* P6_M_Dothan. */
742	case 0x0000015b: return "P6_UNK_0000_015b"; /* P6_M_Dothan. */
743	case 0x0000015e: return "C2_UNK_0000_015e"; /* Core2_Penryn. */
744	case 0x0000015f: return "C1_DTS_CAL_CTRL"; /* Core2_Penryn. msrtool only docs this for core1! */
745	case 0x00000174: return "IA32_SYSENTER_CS";
746	case 0x00000175: return "IA32_SYSENTER_ESP";
747	case 0x00000176: return "IA32_SYSENTER_EIP";
748	case 0x00000179: return "IA32_MCG_CAP";
749	case 0x0000017a: return "IA32_MCG_STATUS";
750	case 0x0000017b: return "IA32_MCG_CTL";
751	case 0x0000017f: return "I7_SB_ERROR_CONTROL"; /* SandyBridge. */
752	case 0x00000180: return g_fIntelNetBurst ? "MSR_MCG_RAX" : NULL;
753	case 0x00000181: return g_fIntelNetBurst ? "MSR_MCG_RBX" : NULL;
754	case 0x00000182: return g_fIntelNetBurst ? "MSR_MCG_RCX" : NULL;
755	case 0x00000183: return g_fIntelNetBurst ? "MSR_MCG_RDX" : NULL;
756	case 0x00000184: return g_fIntelNetBurst ? "MSR_MCG_RSI" : NULL;
757	case 0x00000185: return g_fIntelNetBurst ? "MSR_MCG_RDI" : NULL;
758	case 0x00000186: return g_fIntelNetBurst ? "MSR_MCG_RBP" : "IA32_PERFEVTSEL0";
759	case 0x00000187: return g_fIntelNetBurst ? "MSR_MCG_RSP" : "IA32_PERFEVTSEL1";
760	case 0x00000188: return g_fIntelNetBurst ? "MSR_MCG_RFLAGS" : "IA32_PERFEVTSEL2";
761	case 0x00000189: return g_fIntelNetBurst ? "MSR_MCG_RIP" : "IA32_PERFEVTSEL3";
762	case 0x0000018a: return g_fIntelNetBurst ? "MSR_MCG_MISC" : "IA32_PERFEVTSEL4";
763	case 0x0000018b: return g_fIntelNetBurst ? "MSR_MCG_RESERVED1" : "IA32_PERFEVTSEL5";
764	case 0x0000018c: return g_fIntelNetBurst ? "MSR_MCG_RESERVED2" : "IA32_PERFEVTSEL6";
765	case 0x0000018d: return g_fIntelNetBurst ? "MSR_MCG_RESERVED3" : "IA32_PERFEVTSEL7";
766	case 0x0000018e: return g_fIntelNetBurst ? "MSR_MCG_RESERVED4" : "IA32_PERFEVTSEL8";
767	case 0x0000018f: return g_fIntelNetBurst ? "MSR_MCG_RESERVED5" : "IA32_PERFEVTSEL9";
768	case 0x00000190: return g_fIntelNetBurst ? "MSR_MCG_R8" : NULL;
769	case 0x00000191: return g_fIntelNetBurst ? "MSR_MCG_R9" : NULL;
770	case 0x00000192: return g_fIntelNetBurst ? "MSR_MCG_R10" : NULL;
771	case 0x00000193: return g_fIntelNetBurst ? "MSR_MCG_R11" : "C2_UNK_0000_0193";
772	case 0x00000194: return g_fIntelNetBurst ? "MSR_MCG_R12" : "CLOCK_FLEX_MAX";
773	case 0x00000195: return g_fIntelNetBurst ? "MSR_MCG_R13" : NULL;
774	case 0x00000196: return g_fIntelNetBurst ? "MSR_MCG_R14" : NULL;
775	case 0x00000197: return g_fIntelNetBurst ? "MSR_MCG_R15" : NULL;
776	case 0x00000198: return "IA32_PERF_STATUS";
777	case 0x00000199: return "IA32_PERF_CTL";
778	case 0x0000019a: return "IA32_CLOCK_MODULATION";
779	case 0x0000019b: return "IA32_THERM_INTERRUPT";
780	case 0x0000019c: return "IA32_THERM_STATUS";
781	case 0x0000019d: return "IA32_THERM2_CTL";
782	case 0x0000019e: return "P6_UNK_0000_019e"; /* P6_M_Dothan. */
783	case 0x0000019f: return "P6_UNK_0000_019f"; /* P6_M_Dothan. */
784	case 0x000001a0: return "IA32_MISC_ENABLE";
785	case 0x000001a1: return g_fIntelNetBurst ? "MSR_PLATFORM_BRV" : "P6_UNK_0000_01a1" /* P6_M_Dothan. */;
786	case 0x000001a2: return g_fIntelNetBurst ? "P4_UNK_0000_01a2" : "I7_MSR_TEMPERATURE_TARGET" /* SandyBridge, IvyBridge. */;
787	case 0x000001a4: return "I7_UNK_0000_01a4"; /* SandyBridge, IvyBridge. */
788	case 0x000001a6: return "I7_MSR_OFFCORE_RSP_0";
789	case 0x000001a7: return "I7_MSR_OFFCORE_RSP_1";
790	case 0x000001a8: return "I7_UNK_0000_01a8"; /* SandyBridge, IvyBridge. */
791	case 0x000001aa: return CPUMMICROARCH_IS_INTEL_CORE7(g_enmMicroarch) ? "MSR_MISC_PWR_MGMT" : "P6_PIC_SENS_CFG" /* Pentium M. */;
792	case 0x000001ad: return "I7_MSR_TURBO_RATIO_LIMIT"; /* SandyBridge+, Silvermount+ */
793	case 0x000001ae: return "P6_UNK_0000_01ae"; /* P6_M_Dothan. */
794	case 0x000001af: return "P6_UNK_0000_01af"; /* P6_M_Dothan. */
795	case 0x000001b0: return "IA32_ENERGY_PERF_BIAS";
796	case 0x000001b1: return "IA32_PACKAGE_THERM_STATUS";
797	case 0x000001b2: return "IA32_PACKAGE_THERM_INTERRUPT";
798	case 0x000001bf: return "C2_UNK_0000_01bf"; /* Core2_Penryn. */
799	case 0x000001c6: return "I7_UNK_0000_01c6"; /* SandyBridge*/
800	case 0x000001c8: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_Nehalem ? "MSR_LBR_SELECT" : NULL;
801	case 0x000001c9: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah
802	&& g_enmMicroarch <= kCpumMicroarch_Intel_P6_Core_Atom_End
803	? "MSR_LASTBRANCH_TOS" : NULL /* Pentium M Dothan seems to have something else here. */;
804	case 0x000001d3: return "P6_UNK_0000_01d3"; /* P6_M_Dothan. */
805	case 0x000001d7: return g_fIntelNetBurst ? "MSR_LER_FROM_LIP" : NULL;
806	case 0x000001d8: return g_fIntelNetBurst ? "MSR_LER_TO_LIP" : NULL;
807	case 0x000001d9: return "IA32_DEBUGCTL";
808	case 0x000001da: return g_fIntelNetBurst ? "MSR_LASTBRANCH_TOS" : NULL;
809	case 0x000001db: return g_fIntelNetBurst ? "P6_LASTBRANCH_0" : "P6_LAST_BRANCH_FROM_IP"; /* Not exclusive to P6, also AMD. */
810	case 0x000001dc: return g_fIntelNetBurst ? "P6_LASTBRANCH_1" : "P6_LAST_BRANCH_TO_IP";
811	case 0x000001dd: return g_fIntelNetBurst ? "P6_LASTBRANCH_2" : "P6_LAST_INT_FROM_IP";
812	case 0x000001de: return g_fIntelNetBurst ? "P6_LASTBRANCH_3" : "P6_LAST_INT_TO_IP";
813	case 0x000001e0: return "MSR_ROB_CR_BKUPTMPDR6";
814	case 0x000001e1: return "I7_SB_UNK_0000_01e1";
815	case 0x000001ef: return "I7_SB_UNK_0000_01ef";
816	case 0x000001f0: return "I7_VLW_CAPABILITY"; /* SandyBridge. Bit 1 is A20M and was implemented incorrectly (AAJ49). */
817	case 0x000001f2: return "IA32_SMRR_PHYSBASE";
818	case 0x000001f3: return "IA32_SMRR_PHYSMASK";
819	case 0x000001f8: return "IA32_PLATFORM_DCA_CAP";
820	case 0x000001f9: return "IA32_CPU_DCA_CAP";
821	case 0x000001fa: return "IA32_DCA_0_CAP";
822	case 0x000001fc: return "I7_MSR_POWER_CTL";
823
824	case 0x00000200: return "IA32_MTRR_PHYS_BASE0";
825	case 0x00000202: return "IA32_MTRR_PHYS_BASE1";
826	case 0x00000204: return "IA32_MTRR_PHYS_BASE2";
827	case 0x00000206: return "IA32_MTRR_PHYS_BASE3";
828	case 0x00000208: return "IA32_MTRR_PHYS_BASE4";
829	case 0x0000020a: return "IA32_MTRR_PHYS_BASE5";
830	case 0x0000020c: return "IA32_MTRR_PHYS_BASE6";
831	case 0x0000020e: return "IA32_MTRR_PHYS_BASE7";
832	case 0x00000210: return "IA32_MTRR_PHYS_BASE8";
833	case 0x00000212: return "IA32_MTRR_PHYS_BASE9";
834	case 0x00000214: return "IA32_MTRR_PHYS_BASE10";
835	case 0x00000216: return "IA32_MTRR_PHYS_BASE11";
836	case 0x00000218: return "IA32_MTRR_PHYS_BASE12";
837	case 0x0000021a: return "IA32_MTRR_PHYS_BASE13";
838	case 0x0000021c: return "IA32_MTRR_PHYS_BASE14";
839	case 0x0000021e: return "IA32_MTRR_PHYS_BASE15";
840
841	case 0x00000201: return "IA32_MTRR_PHYS_MASK0";
842	case 0x00000203: return "IA32_MTRR_PHYS_MASK1";
843	case 0x00000205: return "IA32_MTRR_PHYS_MASK2";
844	case 0x00000207: return "IA32_MTRR_PHYS_MASK3";
845	case 0x00000209: return "IA32_MTRR_PHYS_MASK4";
846	case 0x0000020b: return "IA32_MTRR_PHYS_MASK5";
847	case 0x0000020d: return "IA32_MTRR_PHYS_MASK6";
848	case 0x0000020f: return "IA32_MTRR_PHYS_MASK7";
849	case 0x00000211: return "IA32_MTRR_PHYS_MASK8";
850	case 0x00000213: return "IA32_MTRR_PHYS_MASK9";
851	case 0x00000215: return "IA32_MTRR_PHYS_MASK10";
852	case 0x00000217: return "IA32_MTRR_PHYS_MASK11";
853	case 0x00000219: return "IA32_MTRR_PHYS_MASK12";
854	case 0x0000021b: return "IA32_MTRR_PHYS_MASK13";
855	case 0x0000021d: return "IA32_MTRR_PHYS_MASK14";
856	case 0x0000021f: return "IA32_MTRR_PHYS_MASK15";
857
858	case 0x00000250: return "IA32_MTRR_FIX64K_00000";
859	case 0x00000258: return "IA32_MTRR_FIX16K_80000";
860	case 0x00000259: return "IA32_MTRR_FIX16K_A0000";
861	case 0x00000268: return "IA32_MTRR_FIX4K_C0000";
862	case 0x00000269: return "IA32_MTRR_FIX4K_C8000";
863	case 0x0000026a: return "IA32_MTRR_FIX4K_D0000";
864	case 0x0000026b: return "IA32_MTRR_FIX4K_D8000";
865	case 0x0000026c: return "IA32_MTRR_FIX4K_E0000";
866	case 0x0000026d: return "IA32_MTRR_FIX4K_E8000";
867	case 0x0000026e: return "IA32_MTRR_FIX4K_F0000";
868	case 0x0000026f: return "IA32_MTRR_FIX4K_F8000";
869	case 0x00000277: return "IA32_PAT";
870	case 0x00000280: return "IA32_MC0_CTL2";
871	case 0x00000281: return "IA32_MC1_CTL2";
872	case 0x00000282: return "IA32_MC2_CTL2";
873	case 0x00000283: return "IA32_MC3_CTL2";
874	case 0x00000284: return "IA32_MC4_CTL2";
875	case 0x00000285: return "IA32_MC5_CTL2";
876	case 0x00000286: return "IA32_MC6_CTL2";
877	case 0x00000287: return "IA32_MC7_CTL2";
878	case 0x00000288: return "IA32_MC8_CTL2";
879	case 0x00000289: return "IA32_MC9_CTL2";
880	case 0x0000028a: return "IA32_MC10_CTL2";
881	case 0x0000028b: return "IA32_MC11_CTL2";
882	case 0x0000028c: return "IA32_MC12_CTL2";
883	case 0x0000028d: return "IA32_MC13_CTL2";
884	case 0x0000028e: return "IA32_MC14_CTL2";
885	case 0x0000028f: return "IA32_MC15_CTL2";
886	case 0x00000290: return "IA32_MC16_CTL2";
887	case 0x00000291: return "IA32_MC17_CTL2";
888	case 0x00000292: return "IA32_MC18_CTL2";
889	case 0x00000293: return "IA32_MC19_CTL2";
890	case 0x00000294: return "IA32_MC20_CTL2";
891	case 0x00000295: return "IA32_MC21_CTL2";
892	//case 0x00000296: return "IA32_MC22_CTL2";
893	//case 0x00000297: return "IA32_MC23_CTL2";
894	//case 0x00000298: return "IA32_MC24_CTL2";
895	//case 0x00000299: return "IA32_MC25_CTL2";
896	//case 0x0000029a: return "IA32_MC26_CTL2";
897	//case 0x0000029b: return "IA32_MC27_CTL2";
898	//case 0x0000029c: return "IA32_MC28_CTL2";
899	//case 0x0000029d: return "IA32_MC29_CTL2";
900	//case 0x0000029e: return "IA32_MC30_CTL2";
901	//case 0x0000029f: return "IA32_MC31_CTL2";
902	case 0x000002e0: return "I7_SB_NO_EVICT_MODE"; /* (Bits 1 & 0 are said to have something to do with no-evict cache mode used during early boot.) */
903	case 0x000002e6: return "I7_IB_UNK_0000_02e6"; /* IvyBridge */
904	case 0x000002e7: return "I7_IB_UNK_0000_02e7"; /* IvyBridge */
905	case 0x000002ff: return "IA32_MTRR_DEF_TYPE";
906	case 0x00000300: return g_fIntelNetBurst ? "P4_MSR_BPU_COUNTER0" : "I7_SB_UNK_0000_0300" /* SandyBridge */;
907	case 0x00000301: return g_fIntelNetBurst ? "P4_MSR_BPU_COUNTER1" : NULL;
908	case 0x00000302: return g_fIntelNetBurst ? "P4_MSR_BPU_COUNTER2" : NULL;
909	case 0x00000303: return g_fIntelNetBurst ? "P4_MSR_BPU_COUNTER3" : NULL;
910	case 0x00000304: return g_fIntelNetBurst ? "P4_MSR_MS_COUNTER0" : NULL;
911	case 0x00000305: return g_fIntelNetBurst ? "P4_MSR_MS_COUNTER1" : "I7_SB_UNK_0000_0305" /* SandyBridge, IvyBridge */;
912	case 0x00000306: return g_fIntelNetBurst ? "P4_MSR_MS_COUNTER2" : NULL;
913	case 0x00000307: return g_fIntelNetBurst ? "P4_MSR_MS_COUNTER3" : NULL;
914	case 0x00000308: return g_fIntelNetBurst ? "P4_MSR_FLAME_COUNTER0" : NULL;
915	case 0x00000309: return g_fIntelNetBurst ? "P4_MSR_FLAME_COUNTER1" : "IA32_FIXED_CTR0";
916	case 0x0000030a: return g_fIntelNetBurst ? "P4_MSR_FLAME_COUNTER2" : "IA32_FIXED_CTR1";
917	case 0x0000030b: return g_fIntelNetBurst ? "P4_MSR_FLAME_COUNTER3" : "IA32_FIXED_CTR2";
918	case 0x0000030c: return g_fIntelNetBurst ? "P4_MSR_IQ_COUNTER0" : NULL;
919	case 0x0000030d: return g_fIntelNetBurst ? "P4_MSR_IQ_COUNTER1" : NULL;
920	case 0x0000030e: return g_fIntelNetBurst ? "P4_MSR_IQ_COUNTER2" : NULL;
921	case 0x0000030f: return g_fIntelNetBurst ? "P4_MSR_IQ_COUNTER3" : NULL;
922	case 0x00000310: return g_fIntelNetBurst ? "P4_MSR_IQ_COUNTER4" : NULL;
923	case 0x00000311: return g_fIntelNetBurst ? "P4_MSR_IQ_COUNTER5" : NULL;
924	case 0x00000345: return "IA32_PERF_CAPABILITIES";
925	case 0x00000360: return g_fIntelNetBurst ? "P4_MSR_BPU_CCCR0" : NULL;
926	case 0x00000361: return g_fIntelNetBurst ? "P4_MSR_BPU_CCCR1" : NULL;
927	case 0x00000362: return g_fIntelNetBurst ? "P4_MSR_BPU_CCCR2" : NULL;
928	case 0x00000363: return g_fIntelNetBurst ? "P4_MSR_BPU_CCCR3" : NULL;
929	case 0x00000364: return g_fIntelNetBurst ? "P4_MSR_MS_CCCR0" : NULL;
930	case 0x00000365: return g_fIntelNetBurst ? "P4_MSR_MS_CCCR1" : NULL;
931	case 0x00000366: return g_fIntelNetBurst ? "P4_MSR_MS_CCCR2" : NULL;
932	case 0x00000367: return g_fIntelNetBurst ? "P4_MSR_MS_CCCR3" : NULL;
933	case 0x00000368: return g_fIntelNetBurst ? "P4_MSR_FLAME_CCCR0" : NULL;
934	case 0x00000369: return g_fIntelNetBurst ? "P4_MSR_FLAME_CCCR1" : NULL;
935	case 0x0000036a: return g_fIntelNetBurst ? "P4_MSR_FLAME_CCCR2" : NULL;
936	case 0x0000036b: return g_fIntelNetBurst ? "P4_MSR_FLAME_CCCR3" : NULL;
937	case 0x0000036c: return g_fIntelNetBurst ? "P4_MSR_IQ_CCCR0" : NULL;
938	case 0x0000036d: return g_fIntelNetBurst ? "P4_MSR_IQ_CCCR1" : NULL;
939	case 0x0000036e: return g_fIntelNetBurst ? "P4_MSR_IQ_CCCR2" : NULL;
940	case 0x0000036f: return g_fIntelNetBurst ? "P4_MSR_IQ_CCCR3" : NULL;
941	case 0x00000370: return g_fIntelNetBurst ? "P4_MSR_IQ_CCCR4" : NULL;
942	case 0x00000371: return g_fIntelNetBurst ? "P4_MSR_IQ_CCCR5" : NULL;
943	case 0x0000038d: return "IA32_FIXED_CTR_CTRL";
944	case 0x0000038e: return "IA32_PERF_GLOBAL_STATUS";
945	case 0x0000038f: return "IA32_PERF_GLOBAL_CTRL";
946	case 0x00000390: return "IA32_PERF_GLOBAL_OVF_CTRL";
947	case 0x00000391: return "I7_UNC_PERF_GLOBAL_CTRL"; /* S,H,X */
948	case 0x00000392: return "I7_UNC_PERF_GLOBAL_STATUS"; /* S,H,X */
949	case 0x00000393: return "I7_UNC_PERF_GLOBAL_OVF_CTRL"; /* X. ASSUMING this is the same on sandybridge and later. */
950	case 0x00000394: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PERF_FIXED_CTR" /* X / : "I7_UNC_PERF_FIXED_CTR_CTRL"; / >= S,H */
951	case 0x00000395: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PERF_FIXED_CTR_CTRL" /* X/ : "I7_UNC_PERF_FIXED_CTR"; / >= S,H */
952	case 0x00000396: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_ADDR_OPCODE_MATCH" /* X / : "I7_UNC_CBO_CONFIG"; / >= S,H */
953	case 0x00000397: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_IvyBridge ? NULL : "I7_IB_UNK_0000_0397";
954	case 0x0000039c: return "I7_SB_MSR_PEBS_NUM_ALT";
955	case 0x000003a0: return g_fIntelNetBurst ? "P4_MSR_BSU_ESCR0" : NULL;
956	case 0x000003a1: return g_fIntelNetBurst ? "P4_MSR_BSU_ESCR1" : NULL;
957	case 0x000003a2: return g_fIntelNetBurst ? "P4_MSR_FSB_ESCR0" : NULL;
958	case 0x000003a3: return g_fIntelNetBurst ? "P4_MSR_FSB_ESCR1" : NULL;
959	case 0x000003a4: return g_fIntelNetBurst ? "P4_MSR_FIRM_ESCR0" : NULL;
960	case 0x000003a5: return g_fIntelNetBurst ? "P4_MSR_FIRM_ESCR1" : NULL;
961	case 0x000003a6: return g_fIntelNetBurst ? "P4_MSR_FLAME_ESCR0" : NULL;
962	case 0x000003a7: return g_fIntelNetBurst ? "P4_MSR_FLAME_ESCR1" : NULL;
963	case 0x000003a8: return g_fIntelNetBurst ? "P4_MSR_DAC_ESCR0" : NULL;
964	case 0x000003a9: return g_fIntelNetBurst ? "P4_MSR_DAC_ESCR1" : NULL;
965	case 0x000003aa: return g_fIntelNetBurst ? "P4_MSR_MOB_ESCR0" : NULL;
966	case 0x000003ab: return g_fIntelNetBurst ? "P4_MSR_MOB_ESCR1" : NULL;
967	case 0x000003ac: return g_fIntelNetBurst ? "P4_MSR_PMH_ESCR0" : NULL;
968	case 0x000003ad: return g_fIntelNetBurst ? "P4_MSR_PMH_ESCR1" : NULL;
969	case 0x000003ae: return g_fIntelNetBurst ? "P4_MSR_SAAT_ESCR0" : NULL;
970	case 0x000003af: return g_fIntelNetBurst ? "P4_MSR_SAAT_ESCR1" : NULL;
971	case 0x000003b0: return g_fIntelNetBurst ? "P4_MSR_U2L_ESCR0" : g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PMC0" /* X / : "I7_UNC_ARB_PERF_CTR0"; / >= S,H */
972	case 0x000003b1: return g_fIntelNetBurst ? "P4_MSR_U2L_ESCR1" : g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PMC1" /* X / : "I7_UNC_ARB_PERF_CTR1"; / >= S,H */
973	case 0x000003b2: return g_fIntelNetBurst ? "P4_MSR_BPU_ESCR0" : g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PMC2" /* X / : "I7_UNC_ARB_PERF_EVT_SEL0"; / >= S,H */
974	case 0x000003b3: return g_fIntelNetBurst ? "P4_MSR_BPU_ESCR1" : g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PMC3" /* X / : "I7_UNC_ARB_PERF_EVT_SEL1"; / >= S,H */
975	case 0x000003b4: return g_fIntelNetBurst ? "P4_MSR_IS_ESCR0" : "I7_UNC_PMC4";
976	case 0x000003b5: return g_fIntelNetBurst ? "P4_MSR_IS_ESCR1" : "I7_UNC_PMC5";
977	case 0x000003b6: return g_fIntelNetBurst ? "P4_MSR_ITLB_ESCR0" : "I7_UNC_PMC6";
978	case 0x000003b7: return g_fIntelNetBurst ? "P4_MSR_ITLB_ESCR1" : "I7_UNC_PMC7";
979	case 0x000003b8: return g_fIntelNetBurst ? "P4_MSR_CRU_ESCR0" : NULL;
980	case 0x000003b9: return g_fIntelNetBurst ? "P4_MSR_CRU_ESCR1" : NULL;
981	case 0x000003ba: return g_fIntelNetBurst ? "P4_MSR_IQ_ESCR0" : NULL;
982	case 0x000003bb: return g_fIntelNetBurst ? "P4_MSR_IQ_ESCR1" : NULL;
983	case 0x000003bc: return g_fIntelNetBurst ? "P4_MSR_RAT_ESCR0" : NULL;
984	case 0x000003bd: return g_fIntelNetBurst ? "P4_MSR_RAT_ESCR1" : NULL;
985	case 0x000003be: return g_fIntelNetBurst ? "P4_MSR_SSU_ESCR0" : NULL;
986	case 0x000003c0: return g_fIntelNetBurst ? "P4_MSR_MS_ESCR0" : "I7_UNC_PERF_EVT_SEL0";
987	case 0x000003c1: return g_fIntelNetBurst ? "P4_MSR_MS_ESCR1" : "I7_UNC_PERF_EVT_SEL1";
988	case 0x000003c2: return g_fIntelNetBurst ? "P4_MSR_TBPU_ESCR0" : "I7_UNC_PERF_EVT_SEL2";
989	case 0x000003c3: return g_fIntelNetBurst ? "P4_MSR_TBPU_ESCR1" : "I7_UNC_PERF_EVT_SEL3";
990	case 0x000003c4: return g_fIntelNetBurst ? "P4_MSR_TC_ESCR0" : "I7_UNC_PERF_EVT_SEL4";
991	case 0x000003c5: return g_fIntelNetBurst ? "P4_MSR_TC_ESCR1" : "I7_UNC_PERF_EVT_SEL5";
992	case 0x000003c6: return g_fIntelNetBurst ? NULL : "I7_UNC_PERF_EVT_SEL6";
993	case 0x000003c7: return g_fIntelNetBurst ? NULL : "I7_UNC_PERF_EVT_SEL7";
994	case 0x000003c8: return g_fIntelNetBurst ? "P4_MSR_IX_ESCR0" : NULL;
995	case 0x000003c9: return g_fIntelNetBurst ? "P4_MSR_IX_ESCR0" : NULL;
996	case 0x000003ca: return g_fIntelNetBurst ? "P4_MSR_ALF_ESCR0" : NULL;
997	case 0x000003cb: return g_fIntelNetBurst ? "P4_MSR_ALF_ESCR1" : NULL;
998	case 0x000003cc: return g_fIntelNetBurst ? "P4_MSR_CRU_ESCR2" : NULL;
999	case 0x000003cd: return g_fIntelNetBurst ? "P4_MSR_CRU_ESCR3" : NULL;
1000	case 0x000003e0: return g_fIntelNetBurst ? "P4_MSR_CRU_ESCR4" : NULL;
1001	case 0x000003e1: return g_fIntelNetBurst ? "P4_MSR_CRU_ESCR5" : NULL;
1002	case 0x000003f0: return g_fIntelNetBurst ? "P4_MSR_TC_PRECISE_EVENT" : NULL;
1003	case 0x000003f1: return "IA32_PEBS_ENABLE";
1004	case 0x000003f2: return g_fIntelNetBurst ? "P4_MSR_PEBS_MATRIX_VERT" : "IA32_PEBS_ENABLE";
1005	case 0x000003f3: return g_fIntelNetBurst ? "P4_UNK_0000_03f3" : NULL;
1006	case 0x000003f4: return g_fIntelNetBurst ? "P4_UNK_0000_03f4" : NULL;
1007	case 0x000003f5: return g_fIntelNetBurst ? "P4_UNK_0000_03f5" : NULL;
1008	case 0x000003f6: return g_fIntelNetBurst ? "P4_UNK_0000_03f6" : "I7_MSR_PEBS_LD_LAT";
1009	case 0x000003f7: return g_fIntelNetBurst ? "P4_UNK_0000_03f7" : "I7_MSR_PEBS_LD_LAT";
1010	case 0x000003f8: return g_fIntelNetBurst ? "P4_UNK_0000_03f8" : "I7_MSR_PKG_C3_RESIDENCY";
1011	case 0x000003f9: return "I7_MSR_PKG_C6_RESIDENCY";
1012	case 0x000003fa: return "I7_MSR_PKG_C7_RESIDENCY";
1013	case 0x000003fc: return "I7_MSR_CORE_C3_RESIDENCY";
1014	case 0x000003fd: return "I7_MSR_CORE_C6_RESIDENCY";
1015	case 0x000003fe: return "I7_MSR_CORE_C7_RESIDENCY";
1016	case 0x00000478: return g_enmMicroarch == kCpumMicroarch_Intel_Core2_Penryn ? "CPUID1_FEATURE_MASK" : NULL;
1017	case 0x00000480: return "IA32_VMX_BASIC";
1018	case 0x00000481: return "IA32_VMX_PINBASED_CTLS";
1019	case 0x00000482: return "IA32_VMX_PROCBASED_CTLS";
1020	case 0x00000483: return "IA32_VMX_EXIT_CTLS";
1021	case 0x00000484: return "IA32_VMX_ENTRY_CTLS";
1022	case 0x00000485: return "IA32_VMX_MISC";
1023	case 0x00000486: return "IA32_VMX_CR0_FIXED0";
1024	case 0x00000487: return "IA32_VMX_CR0_FIXED1";
1025	case 0x00000488: return "IA32_VMX_CR4_FIXED0";
1026	case 0x00000489: return "IA32_VMX_CR4_FIXED1";
1027	case 0x0000048a: return "IA32_VMX_VMCS_ENUM";
1028	case 0x0000048b: return "IA32_VMX_PROCBASED_CTLS2";
1029	case 0x0000048c: return "IA32_VMX_EPT_VPID_CAP";
1030	case 0x0000048d: return "IA32_VMX_TRUE_PINBASED_CTLS";
1031	case 0x0000048e: return "IA32_VMX_TRUE_PROCBASED_CTLS";
1032	case 0x0000048f: return "IA32_VMX_TRUE_EXIT_CTLS";
1033	case 0x00000490: return "IA32_VMX_TRUE_ENTRY_CTLS";
1034	case 0x000004c1: return "IA32_A_PMC0";
1035	case 0x000004c2: return "IA32_A_PMC1";
1036	case 0x000004c3: return "IA32_A_PMC2";
1037	case 0x000004c4: return "IA32_A_PMC3";
1038	case 0x000004c5: return "IA32_A_PMC4";
1039	case 0x000004c6: return "IA32_A_PMC5";
1040	case 0x000004c7: return "IA32_A_PMC6";
1041	case 0x000004c8: return "IA32_A_PMC7";
1042	case 0x000004f8: return "C2_UNK_0000_04f8"; /* Core2_Penryn. */
1043	case 0x000004f9: return "C2_UNK_0000_04f9"; /* Core2_Penryn. */
1044	case 0x000004fa: return "C2_UNK_0000_04fa"; /* Core2_Penryn. */
1045	case 0x000004fb: return "C2_UNK_0000_04fb"; /* Core2_Penryn. */
1046	case 0x000004fc: return "C2_UNK_0000_04fc"; /* Core2_Penryn. */
1047	case 0x000004fd: return "C2_UNK_0000_04fd"; /* Core2_Penryn. */
1048	case 0x000004fe: return "C2_UNK_0000_04fe"; /* Core2_Penryn. */
1049	case 0x000004ff: return "C2_UNK_0000_04ff"; /* Core2_Penryn. */
1050	case 0x00000502: return "I7_SB_UNK_0000_0502";
1051	case 0x00000590: return "C2_UNK_0000_0590"; /* Core2_Penryn. */
1052	case 0x00000591: return "C2_UNK_0000_0591"; /* Core2_Penryn. */
1053	case 0x000005a0: return "C2_PECI_CTL"; /* Core2_Penryn. */
1054	case 0x000005a1: return "C2_UNK_0000_05a1"; /* Core2_Penryn. */
1055	case 0x00000600: return "IA32_DS_AREA";
1056	case 0x00000601: return "I7_SB_MSR_VR_CURRENT_CONFIG"; /* SandyBridge, IvyBridge. */
1057	case 0x00000602: return "I7_IB_UNK_0000_0602";
1058	case 0x00000603: return "I7_SB_MSR_VR_MISC_CONFIG"; /* SandyBridge, IvyBridge. */
1059	case 0x00000604: return "I7_IB_UNK_0000_0602";
1060	case 0x00000606: return "I7_SB_MSR_RAPL_POWER_UNIT"; /* SandyBridge, IvyBridge. */
1061	case 0x0000060a: return "I7_SB_MSR_PKGC3_IRTL"; /* SandyBridge, IvyBridge. */
1062	case 0x0000060b: return "I7_SB_MSR_PKGC6_IRTL"; /* SandyBridge, IvyBridge. */
1063	case 0x0000060c: return "I7_SB_MSR_PKGC7_IRTL"; /* SandyBridge, IvyBridge. */
1064	case 0x0000060d: return "I7_SB_MSR_PKG_C2_RESIDENCY"; /* SandyBridge, IvyBridge. */
1065	case 0x00000610: return "I7_SB_MSR_PKG_POWER_LIMIT";
1066	case 0x00000611: return "I7_SB_MSR_PKG_ENERGY_STATUS";
1067	case 0x00000613: return "I7_SB_MSR_PKG_PERF_STATUS";
1068	case 0x00000614: return "I7_SB_MSR_PKG_POWER_INFO";
1069	case 0x00000618: return "I7_SB_MSR_DRAM_POWER_LIMIT";
1070	case 0x00000619: return "I7_SB_MSR_DRAM_ENERGY_STATUS";
1071	case 0x0000061b: return "I7_SB_MSR_DRAM_PERF_STATUS";
1072	case 0x0000061c: return "I7_SB_MSR_DRAM_POWER_INFO";
1073	case 0x00000638: return "I7_SB_MSR_PP0_POWER_LIMIT";
1074	case 0x00000639: return "I7_SB_MSR_PP0_ENERGY_STATUS";
1075	case 0x0000063a: return "I7_SB_MSR_PP0_POLICY";
1076	case 0x0000063b: return "I7_SB_MSR_PP0_PERF_STATUS";
1077	case 0x00000640: return "I7_HW_MSR_PP0_POWER_LIMIT";
1078	case 0x00000641: return "I7_HW_MSR_PP0_ENERGY_STATUS";
1079	case 0x00000642: return "I7_HW_MSR_PP0_POLICY";
1080	case 0x00000648: return "I7_IB_MSR_CONFIG_TDP_NOMINAL";
1081	case 0x00000649: return "I7_IB_MSR_CONFIG_TDP_LEVEL1";
1082	case 0x0000064a: return "I7_IB_MSR_CONFIG_TDP_LEVEL2";
1083	case 0x0000064b: return "I7_IB_MSR_CONFIG_TDP_CONTROL";
1084	case 0x0000064c: return "I7_IB_MSR_TURBO_ACTIVATION_RATIO";
1085	case 0x00000680: return "MSR_LASTBRANCH_0_FROM_IP";
1086	case 0x00000681: return "MSR_LASTBRANCH_1_FROM_IP";
1087	case 0x00000682: return "MSR_LASTBRANCH_2_FROM_IP";
1088	case 0x00000683: return "MSR_LASTBRANCH_3_FROM_IP";
1089	case 0x00000684: return "MSR_LASTBRANCH_4_FROM_IP";
1090	case 0x00000685: return "MSR_LASTBRANCH_5_FROM_IP";
1091	case 0x00000686: return "MSR_LASTBRANCH_6_FROM_IP";
1092	case 0x00000687: return "MSR_LASTBRANCH_7_FROM_IP";
1093	case 0x00000688: return "MSR_LASTBRANCH_8_FROM_IP";
1094	case 0x00000689: return "MSR_LASTBRANCH_9_FROM_IP";
1095	case 0x0000068a: return "MSR_LASTBRANCH_10_FROM_IP";
1096	case 0x0000068b: return "MSR_LASTBRANCH_11_FROM_IP";
1097	case 0x0000068c: return "MSR_LASTBRANCH_12_FROM_IP";
1098	case 0x0000068d: return "MSR_LASTBRANCH_13_FROM_IP";
1099	case 0x0000068e: return "MSR_LASTBRANCH_14_FROM_IP";
1100	case 0x0000068f: return "MSR_LASTBRANCH_15_FROM_IP";
1101	case 0x000006c0: return "MSR_LASTBRANCH_0_TO_IP";
1102	case 0x000006c1: return "MSR_LASTBRANCH_1_TO_IP";
1103	case 0x000006c2: return "MSR_LASTBRANCH_2_TO_IP";
1104	case 0x000006c3: return "MSR_LASTBRANCH_3_TO_IP";
1105	case 0x000006c4: return "MSR_LASTBRANCH_4_TO_IP";
1106	case 0x000006c5: return "MSR_LASTBRANCH_5_TO_IP";
1107	case 0x000006c6: return "MSR_LASTBRANCH_6_TO_IP";
1108	case 0x000006c7: return "MSR_LASTBRANCH_7_TO_IP";
1109	case 0x000006c8: return "MSR_LASTBRANCH_8_TO_IP";
1110	case 0x000006c9: return "MSR_LASTBRANCH_9_TO_IP";
1111	case 0x000006ca: return "MSR_LASTBRANCH_10_TO_IP";
1112	case 0x000006cb: return "MSR_LASTBRANCH_11_TO_IP";
1113	case 0x000006cc: return "MSR_LASTBRANCH_12_TO_IP";
1114	case 0x000006cd: return "MSR_LASTBRANCH_13_TO_IP";
1115	case 0x000006ce: return "MSR_LASTBRANCH_14_TO_IP";
1116	case 0x000006cf: return "MSR_LASTBRANCH_15_TO_IP";
1117	case 0x000006e0: return "IA32_TSC_DEADLINE";
1118
1119	case 0x00000c80: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_IvyBridge ? "IA32_DEBUG_INTERFACE" : NULL; /* Mentioned in an intel dataskit called 4th-gen-core-family-desktop-vol-1-datasheet.pdf. */
1120	case 0x00000c81: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_IvyBridge ? "I7_IB_UNK_0000_0c81" : NULL; /* Probably related to IA32_DEBUG_INTERFACE... */
1121	case 0x00000c82: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_IvyBridge ? "I7_IB_UNK_0000_0c82" : NULL; /* Probably related to IA32_DEBUG_INTERFACE... */
1122	case 0x00000c83: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_IvyBridge ? "I7_IB_UNK_0000_0c83" : NULL; /* Probably related to IA32_DEBUG_INTERFACE... */
1123
1124	/* 0x1000..0x1004 seems to have been used by IBM 386 and 486 clones too. */
1125	case 0x00001000: return "P6_DEBUG_REGISTER_0";
1126	case 0x00001001: return "P6_DEBUG_REGISTER_1";
1127	case 0x00001002: return "P6_DEBUG_REGISTER_2";
1128	case 0x00001003: return "P6_DEBUG_REGISTER_3";
1129	case 0x00001004: return "P6_DEBUG_REGISTER_4";
1130	case 0x00001005: return "P6_DEBUG_REGISTER_5";
1131	case 0x00001006: return "P6_DEBUG_REGISTER_6";
1132	case 0x00001007: return "P6_DEBUG_REGISTER_7";
1133	case 0x0000103f: return "P6_UNK_0000_103f"; /* P6_M_Dothan. */
1134	case 0x000010cd: return "P6_UNK_0000_10cd"; /* P6_M_Dothan. */
1135
1136	case 0x00001107: return "VIA_UNK_0000_1107";
1137	case 0x0000110f: return "VIA_UNK_0000_110f";
1138	case 0x00001153: return "VIA_UNK_0000_1153";
1139	case 0x00001200: return "VIA_UNK_0000_1200";
1140	case 0x00001201: return "VIA_UNK_0000_1201";
1141	case 0x00001202: return "VIA_UNK_0000_1202";
1142	case 0x00001203: return "VIA_UNK_0000_1203";
1143	case 0x00001204: return "VIA_UNK_0000_1204";
1144	case 0x00001205: return "VIA_UNK_0000_1205";
1145	case 0x00001206: return "VIA_ALT_VENDOR_EBX";
1146	case 0x00001207: return "VIA_ALT_VENDOR_ECDX";
1147	case 0x00001208: return "VIA_UNK_0000_1208";
1148	case 0x00001209: return "VIA_UNK_0000_1209";
1149	case 0x0000120a: return "VIA_UNK_0000_120a";
1150	case 0x0000120b: return "VIA_UNK_0000_120b";
1151	case 0x0000120c: return "VIA_UNK_0000_120c";
1152	case 0x0000120d: return "VIA_UNK_0000_120d";
1153	case 0x0000120e: return "VIA_UNK_0000_120e";
1154	case 0x0000120f: return "VIA_UNK_0000_120f";
1155	case 0x00001210: return "VIA_UNK_0000_1210";
1156	case 0x00001211: return "VIA_UNK_0000_1211";
1157	case 0x00001212: return "VIA_UNK_0000_1212";
1158	case 0x00001213: return "VIA_UNK_0000_1213";
1159	case 0x00001214: return "VIA_UNK_0000_1214";
1160	case 0x00001220: return "VIA_UNK_0000_1220";
1161	case 0x00001221: return "VIA_UNK_0000_1221";
1162	case 0x00001230: return "VIA_UNK_0000_1230";
1163	case 0x00001231: return "VIA_UNK_0000_1231";
1164	case 0x00001232: return "VIA_UNK_0000_1232";
1165	case 0x00001233: return "VIA_UNK_0000_1233";
1166	case 0x00001234: return "VIA_UNK_0000_1234";
1167	case 0x00001235: return "VIA_UNK_0000_1235";
1168	case 0x00001236: return "VIA_UNK_0000_1236";
1169	case 0x00001237: return "VIA_UNK_0000_1237";
1170	case 0x00001238: return "VIA_UNK_0000_1238";
1171	case 0x00001239: return "VIA_UNK_0000_1239";
1172	case 0x00001240: return "VIA_UNK_0000_1240";
1173	case 0x00001241: return "VIA_UNK_0000_1241";
1174	case 0x00001243: return "VIA_UNK_0000_1243";
1175	case 0x00001245: return "VIA_UNK_0000_1245";
1176	case 0x00001246: return "VIA_UNK_0000_1246";
1177	case 0x00001247: return "VIA_UNK_0000_1247";
1178	case 0x00001248: return "VIA_UNK_0000_1248";
1179	case 0x00001249: return "VIA_UNK_0000_1249";
1180	case 0x0000124a: return "VIA_UNK_0000_124a";
1181
1182	case 0x00001301: return "VIA_UNK_0000_1301";
1183	case 0x00001302: return "VIA_UNK_0000_1302";
1184	case 0x00001303: return "VIA_UNK_0000_1303";
1185	case 0x00001304: return "VIA_UNK_0000_1304";
1186	case 0x00001305: return "VIA_UNK_0000_1305";
1187	case 0x00001306: return "VIA_UNK_0000_1306";
1188	case 0x00001307: return "VIA_UNK_0000_1307";
1189	case 0x00001308: return "VIA_UNK_0000_1308";
1190	case 0x00001309: return "VIA_UNK_0000_1309";
1191	case 0x0000130d: return "VIA_UNK_0000_130d";
1192	case 0x0000130e: return "VIA_UNK_0000_130e";
1193	case 0x00001312: return "VIA_UNK_0000_1312";
1194	case 0x00001315: return "VIA_UNK_0000_1315";
1195	case 0x00001317: return "VIA_UNK_0000_1317";
1196	case 0x00001318: return "VIA_UNK_0000_1318";
1197	case 0x0000131a: return "VIA_UNK_0000_131a";
1198	case 0x0000131b: return "VIA_UNK_0000_131b";
1199	case 0x00001402: return "VIA_UNK_0000_1402";
1200	case 0x00001403: return "VIA_UNK_0000_1403";
1201	case 0x00001404: return "VIA_UNK_0000_1404";
1202	case 0x00001405: return "VIA_UNK_0000_1405";
1203	case 0x00001406: return "VIA_UNK_0000_1406";
1204	case 0x00001407: return "VIA_UNK_0000_1407";
1205	case 0x00001410: return "VIA_UNK_0000_1410";
1206	case 0x00001411: return "VIA_UNK_0000_1411";
1207	case 0x00001412: return "VIA_UNK_0000_1412";
1208	case 0x00001413: return "VIA_UNK_0000_1413";
1209	case 0x00001414: return "VIA_UNK_0000_1414";
1210	case 0x00001415: return "VIA_UNK_0000_1415";
1211	case 0x00001416: return "VIA_UNK_0000_1416";
1212	case 0x00001417: return "VIA_UNK_0000_1417";
1213	case 0x00001418: return "VIA_UNK_0000_1418";
1214	case 0x00001419: return "VIA_UNK_0000_1419";
1215	case 0x0000141a: return "VIA_UNK_0000_141a";
1216	case 0x0000141b: return "VIA_UNK_0000_141b";
1217	case 0x0000141c: return "VIA_UNK_0000_141c";
1218	case 0x0000141d: return "VIA_UNK_0000_141d";
1219	case 0x0000141e: return "VIA_UNK_0000_141e";
1220	case 0x0000141f: return "VIA_UNK_0000_141f";
1221	case 0x00001420: return "VIA_UNK_0000_1420";
1222	case 0x00001421: return "VIA_UNK_0000_1421";
1223	case 0x00001422: return "VIA_UNK_0000_1422";
1224	case 0x00001423: return "VIA_UNK_0000_1423";
1225	case 0x00001424: return "VIA_UNK_0000_1424";
1226	case 0x00001425: return "VIA_UNK_0000_1425";
1227	case 0x00001426: return "VIA_UNK_0000_1426";
1228	case 0x00001427: return "VIA_UNK_0000_1427";
1229	case 0x00001428: return "VIA_UNK_0000_1428";
1230	case 0x00001429: return "VIA_UNK_0000_1429";
1231	case 0x0000142a: return "VIA_UNK_0000_142a";
1232	case 0x0000142b: return "VIA_UNK_0000_142b";
1233	case 0x0000142c: return "VIA_UNK_0000_142c";
1234	case 0x0000142d: return "VIA_UNK_0000_142d";
1235	case 0x0000142e: return "VIA_UNK_0000_142e";
1236	case 0x0000142f: return "VIA_UNK_0000_142f";
1237	case 0x00001434: return "VIA_UNK_0000_1434";
1238	case 0x00001435: return "VIA_UNK_0000_1435";
1239	case 0x00001436: return "VIA_UNK_0000_1436";
1240	case 0x00001437: return "VIA_UNK_0000_1437";
1241	case 0x00001438: return "VIA_UNK_0000_1438";
1242	case 0x0000143a: return "VIA_UNK_0000_143a";
1243	case 0x0000143c: return "VIA_UNK_0000_143c";
1244	case 0x0000143d: return "VIA_UNK_0000_143d";
1245	case 0x00001440: return "VIA_UNK_0000_1440";
1246	case 0x00001441: return "VIA_UNK_0000_1441";
1247	case 0x00001442: return "VIA_UNK_0000_1442";
1248	case 0x00001449: return "VIA_UNK_0000_1449";
1249	case 0x00001450: return "VIA_UNK_0000_1450";
1250	case 0x00001451: return "VIA_UNK_0000_1451";
1251	case 0x00001452: return "VIA_UNK_0000_1452";
1252	case 0x00001453: return "VIA_UNK_0000_1453";
1253	case 0x00001460: return "VIA_UNK_0000_1460";
1254	case 0x00001461: return "VIA_UNK_0000_1461";
1255	case 0x00001462: return "VIA_UNK_0000_1462";
1256	case 0x00001463: return "VIA_UNK_0000_1463";
1257	case 0x00001465: return "VIA_UNK_0000_1465";
1258	case 0x00001466: return "VIA_UNK_0000_1466";
1259	case 0x00001470: return "VIA_UNK_0000_1470";
1260	case 0x00001471: return "VIA_UNK_0000_1471";
1261	case 0x00001480: return "VIA_UNK_0000_1480";
1262	case 0x00001481: return "VIA_UNK_0000_1481";
1263	case 0x00001482: return "VIA_UNK_0000_1482";
1264	case 0x00001483: return "VIA_UNK_0000_1483";
1265	case 0x00001484: return "VIA_UNK_0000_1484";
1266	case 0x00001485: return "VIA_UNK_0000_1485";
1267	case 0x00001486: return "VIA_UNK_0000_1486";
1268	case 0x00001490: return "VIA_UNK_0000_1490";
1269	case 0x00001491: return "VIA_UNK_0000_1491";
1270	case 0x00001492: return "VIA_UNK_0000_1492";
1271	case 0x00001493: return "VIA_UNK_0000_1493";
1272	case 0x00001494: return "VIA_UNK_0000_1494";
1273	case 0x00001495: return "VIA_UNK_0000_1495";
1274	case 0x00001496: return "VIA_UNK_0000_1496";
1275	case 0x00001497: return "VIA_UNK_0000_1497";
1276	case 0x00001498: return "VIA_UNK_0000_1498";
1277	case 0x00001499: return "VIA_UNK_0000_1499";
1278	case 0x0000149a: return "VIA_UNK_0000_149a";
1279	case 0x0000149b: return "VIA_UNK_0000_149b";
1280	case 0x0000149c: return "VIA_UNK_0000_149c";
1281	case 0x0000149f: return "VIA_UNK_0000_149f";
1282	case 0x00001523: return "VIA_UNK_0000_1523";
1283
1284	case 0x00002000: return g_enmVendor == CPUMCPUVENDOR_INTEL ? "P6_CR0" : NULL;
1285	case 0x00002002: return g_enmVendor == CPUMCPUVENDOR_INTEL ? "P6_CR2" : NULL;
1286	case 0x00002003: return g_enmVendor == CPUMCPUVENDOR_INTEL ? "P6_CR3" : NULL;
1287	case 0x00002004: return g_enmVendor == CPUMCPUVENDOR_INTEL ? "P6_CR4" : NULL;
1288	case 0x0000203f: return g_enmVendor == CPUMCPUVENDOR_INTEL ? "P6_UNK_0000_203f" /* P6_M_Dothan. */ : NULL;
1289	case 0x000020cd: return g_enmVendor == CPUMCPUVENDOR_INTEL ? "P6_UNK_0000_20cd" /* P6_M_Dothan. */ : NULL;
1290	case 0x0000303f: return g_enmVendor == CPUMCPUVENDOR_INTEL ? "P6_UNK_0000_303f" /* P6_M_Dothan. */ : NULL;
1291	case 0x000030cd: return g_enmVendor == CPUMCPUVENDOR_INTEL ? "P6_UNK_0000_30cd" /* P6_M_Dothan. */ : NULL;
1292
1293	case 0x0000317a: return "VIA_UNK_0000_317a";
1294	case 0x0000317b: return "VIA_UNK_0000_317b";
1295	case 0x0000317d: return "VIA_UNK_0000_317d";
1296	case 0x0000317e: return "VIA_UNK_0000_317e";
1297	case 0x0000317f: return "VIA_UNK_0000_317f";
1298	case 0x80000198: return "VIA_UNK_8000_0198";
1299
1300	case 0xc0000080: return "AMD64_EFER";
1301	case 0xc0000081: return "AMD64_STAR";
1302	case 0xc0000082: return "AMD64_STAR64";
1303	case 0xc0000083: return "AMD64_STARCOMPAT";
1304	case 0xc0000084: return "AMD64_SYSCALL_FLAG_MASK";
1305	case 0xc0000100: return "AMD64_FS_BASE";
1306	case 0xc0000101: return "AMD64_GS_BASE";
1307	case 0xc0000102: return "AMD64_KERNEL_GS_BASE";
1308	case 0xc0000103: return "AMD64_TSC_AUX";
1309	case 0xc0000104: return "AMD_15H_TSC_RATE";
1310	case 0xc0000105: return "AMD_15H_LWP_CFG"; /* Only Family 15h? */
1311	case 0xc0000106: return "AMD_15H_LWP_CBADDR"; /* Only Family 15h? */
1312	case 0xc0000408: return "AMD_10H_MC4_MISC1";
1313	case 0xc0000409: return "AMD_10H_MC4_MISC2";
1314	case 0xc000040a: return "AMD_10H_MC4_MISC3";
1315	case 0xc000040b: return "AMD_10H_MC4_MISC4";
1316	case 0xc000040c: return "AMD_10H_MC4_MISC5";
1317	case 0xc000040d: return "AMD_10H_MC4_MISC6";
1318	case 0xc000040e: return "AMD_10H_MC4_MISC7";
1319	case 0xc000040f: return "AMD_10H_MC4_MISC8";
1320	case 0xc0010000: return "AMD_K8_PERF_CTL_0";
1321	case 0xc0010001: return "AMD_K8_PERF_CTL_1";
1322	case 0xc0010002: return "AMD_K8_PERF_CTL_2";
1323	case 0xc0010003: return "AMD_K8_PERF_CTL_3";
1324	case 0xc0010004: return "AMD_K8_PERF_CTR_0";
1325	case 0xc0010005: return "AMD_K8_PERF_CTR_1";
1326	case 0xc0010006: return "AMD_K8_PERF_CTR_2";
1327	case 0xc0010007: return "AMD_K8_PERF_CTR_3";
1328	case 0xc0010010: return "AMD_K8_SYS_CFG";
1329	case 0xc0010015: return "AMD_K8_HW_CFG";
1330	case 0xc0010016: return "AMD_K8_IORR_BASE_0";
1331	case 0xc0010017: return "AMD_K8_IORR_MASK_0";
1332	case 0xc0010018: return "AMD_K8_IORR_BASE_1";
1333	case 0xc0010019: return "AMD_K8_IORR_MASK_1";
1334	case 0xc001001a: return "AMD_K8_TOP_MEM";
1335	case 0xc001001d: return "AMD_K8_TOP_MEM2";
1336	case 0xc001001e: return "AMD_K8_MANID";
1337	case 0xc001001f: return "AMD_K8_NB_CFG1";
1338	case 0xc0010020: return "AMD_K8_PATCH_LOADER";
1339	case 0xc0010021: return "AMD_K8_UNK_c001_0021";
1340	case 0xc0010022: return "AMD_K8_MC_XCPT_REDIR";
1341	case 0xc0010028: return "AMD_K8_UNK_c001_0028";
1342	case 0xc0010029: return "AMD_K8_UNK_c001_0029";
1343	case 0xc001002a: return "AMD_K8_UNK_c001_002a";
1344	case 0xc001002b: return "AMD_K8_UNK_c001_002b";
1345	case 0xc001002c: return "AMD_K8_UNK_c001_002c";
1346	case 0xc001002d: return "AMD_K8_UNK_c001_002d";
1347	case 0xc0010030: return "AMD_K8_CPU_NAME_0";
1348	case 0xc0010031: return "AMD_K8_CPU_NAME_1";
1349	case 0xc0010032: return "AMD_K8_CPU_NAME_2";
1350	case 0xc0010033: return "AMD_K8_CPU_NAME_3";
1351	case 0xc0010034: return "AMD_K8_CPU_NAME_4";
1352	case 0xc0010035: return "AMD_K8_CPU_NAME_5";
1353	case 0xc001003e: return "AMD_K8_HTC";
1354	case 0xc001003f: return "AMD_K8_STC";
1355	case 0xc0010041: return "AMD_K8_FIDVID_CTL";
1356	case 0xc0010042: return "AMD_K8_FIDVID_STATUS";
1357	case 0xc0010043: return "AMD_K8_THERMTRIP_STATUS"; /* BDKG says it was removed in K8 revision C.*/
1358	case 0xc0010044: return "AMD_K8_MC_CTL_MASK_0";
1359	case 0xc0010045: return "AMD_K8_MC_CTL_MASK_1";
1360	case 0xc0010046: return "AMD_K8_MC_CTL_MASK_2";
1361	case 0xc0010047: return "AMD_K8_MC_CTL_MASK_3";
1362	case 0xc0010048: return "AMD_K8_MC_CTL_MASK_4";
1363	case 0xc0010049: return "AMD_K8_MC_CTL_MASK_5";
1364	case 0xc001004a: return "AMD_K8_MC_CTL_MASK_6";
1365	//case 0xc001004b: return "AMD_K8_MC_CTL_MASK_7";
1366	case 0xc0010050: return "AMD_K8_SMI_ON_IO_TRAP_0";
1367	case 0xc0010051: return "AMD_K8_SMI_ON_IO_TRAP_1";
1368	case 0xc0010052: return "AMD_K8_SMI_ON_IO_TRAP_2";
1369	case 0xc0010053: return "AMD_K8_SMI_ON_IO_TRAP_3";
1370	case 0xc0010054: return "AMD_K8_SMI_ON_IO_TRAP_CTL_STS";
1371	case 0xc0010055: return "AMD_K8_INT_PENDING_MSG";
1372	case 0xc0010056: return "AMD_K8_SMI_TRIGGER_IO_CYCLE";
1373	case 0xc0010057: return "AMD_10H_UNK_c001_0057";
1374	case 0xc0010058: return "AMD_10H_MMIO_CFG_BASE_ADDR";
1375	case 0xc0010059: return "AMD_10H_TRAP_CTL?"; /* Undocumented, only one google hit. */
1376	case 0xc001005a: return "AMD_10H_UNK_c001_005a";
1377	case 0xc001005b: return "AMD_10H_UNK_c001_005b";
1378	case 0xc001005c: return "AMD_10H_UNK_c001_005c";
1379	case 0xc001005d: return "AMD_10H_UNK_c001_005d";
1380	case 0xc0010060: return "AMD_K8_BIST_RESULT"; /* BDKG says it as introduced with revision F. */
1381	case 0xc0010061: return "AMD_10H_P_ST_CUR_LIM";
1382	case 0xc0010062: return "AMD_10H_P_ST_CTL";
1383	case 0xc0010063: return "AMD_10H_P_ST_STS";
1384	case 0xc0010064: return "AMD_10H_P_ST_0";
1385	case 0xc0010065: return "AMD_10H_P_ST_1";
1386	case 0xc0010066: return "AMD_10H_P_ST_2";
1387	case 0xc0010067: return "AMD_10H_P_ST_3";
1388	case 0xc0010068: return "AMD_10H_P_ST_4";
1389	case 0xc0010069: return "AMD_10H_P_ST_5";
1390	case 0xc001006a: return "AMD_10H_P_ST_6";
1391	case 0xc001006b: return "AMD_10H_P_ST_7";
1392	case 0xc0010070: return "AMD_10H_COFVID_CTL";
1393	case 0xc0010071: return "AMD_10H_COFVID_STS";
1394	case 0xc0010073: return "AMD_10H_C_ST_IO_BASE_ADDR";
1395	case 0xc0010074: return "AMD_10H_CPU_WD_TMR_CFG";
1396	// case 0xc0010075: return "AMD_15H_APML_TDP_LIM";
1397	// case 0xc0010077: return "AMD_15H_CPU_PWR_IN_TDP";
1398	// case 0xc0010078: return "AMD_15H_PWR_AVG_PERIOD";
1399	// case 0xc0010079: return "AMD_15H_DRAM_CTR_CMD_THR";
1400	// case 0xc0010080: return "AMD_16H_FSFM_ACT_CNT_0";
1401	// case 0xc0010081: return "AMD_16H_FSFM_REF_CNT_0";
1402	case 0xc0010111: return "AMD_K8_SMM_BASE";
1403	case 0xc0010112: return "AMD_K8_SMM_ADDR";
1404	case 0xc0010113: return "AMD_K8_SMM_MASK";
1405	case 0xc0010114: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm_AMDV ? "AMD_K8_VM_CR" : "AMD_K8_UNK_c001_0114";
1406	case 0xc0010115: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm ? "AMD_K8_IGNNE" : "AMD_K8_UNK_c001_0115";
1407	case 0xc0010116: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm ? "AMD_K8_SMM_CTL" : "AMD_K8_UNK_c001_0116";
1408	case 0xc0010117: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm_AMDV ? "AMD_K8_VM_HSAVE_PA" : "AMD_K8_UNK_c001_0117";
1409	case 0xc0010118: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm_AMDV ? "AMD_10H_VM_LOCK_KEY" : "AMD_K8_UNK_c001_0118";
1410	case 0xc0010119: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm ? "AMD_10H_SSM_LOCK_KEY" : "AMD_K8_UNK_c001_0119";
1411	case 0xc001011a: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm ? "AMD_10H_LOCAL_SMI_STS" : "AMD_K8_UNK_c001_011a";
1412	case 0xc001011b: return "AMD_K8_UNK_c001_011b";
1413	case 0xc001011c: return "AMD_K8_UNK_c001_011c";
1414	case 0xc0010140: return "AMD_10H_OSVW_ID_LEN";
1415	case 0xc0010141: return "AMD_10H_OSVW_STS";
1416	case 0xc0010200: return "AMD_K8_PERF_CTL_0";
1417	case 0xc0010202: return "AMD_K8_PERF_CTL_1";
1418	case 0xc0010204: return "AMD_K8_PERF_CTL_2";
1419	case 0xc0010206: return "AMD_K8_PERF_CTL_3";
1420	case 0xc0010208: return "AMD_K8_PERF_CTL_4";
1421	case 0xc001020a: return "AMD_K8_PERF_CTL_5";
1422	//case 0xc001020c: return "AMD_K8_PERF_CTL_6";
1423	//case 0xc001020e: return "AMD_K8_PERF_CTL_7";
1424	case 0xc0010201: return "AMD_K8_PERF_CTR_0";
1425	case 0xc0010203: return "AMD_K8_PERF_CTR_1";
1426	case 0xc0010205: return "AMD_K8_PERF_CTR_2";
1427	case 0xc0010207: return "AMD_K8_PERF_CTR_3";
1428	case 0xc0010209: return "AMD_K8_PERF_CTR_4";
1429	case 0xc001020b: return "AMD_K8_PERF_CTR_5";
1430	//case 0xc001020d: return "AMD_K8_PERF_CTR_6";
1431	//case 0xc001020f: return "AMD_K8_PERF_CTR_7";
1432	case 0xc0010230: return "AMD_16H_L2I_PERF_CTL_0";
1433	case 0xc0010232: return "AMD_16H_L2I_PERF_CTL_1";
1434	case 0xc0010234: return "AMD_16H_L2I_PERF_CTL_2";
1435	case 0xc0010236: return "AMD_16H_L2I_PERF_CTL_3";
1436	//case 0xc0010238: return "AMD_16H_L2I_PERF_CTL_4";
1437	//case 0xc001023a: return "AMD_16H_L2I_PERF_CTL_5";
1438	//case 0xc001030c: return "AMD_16H_L2I_PERF_CTL_6";
1439	//case 0xc001023e: return "AMD_16H_L2I_PERF_CTL_7";
1440	case 0xc0010231: return "AMD_16H_L2I_PERF_CTR_0";
1441	case 0xc0010233: return "AMD_16H_L2I_PERF_CTR_1";
1442	case 0xc0010235: return "AMD_16H_L2I_PERF_CTR_2";
1443	case 0xc0010237: return "AMD_16H_L2I_PERF_CTR_3";
1444	//case 0xc0010239: return "AMD_16H_L2I_PERF_CTR_4";
1445	//case 0xc001023b: return "AMD_16H_L2I_PERF_CTR_5";
1446	//case 0xc001023d: return "AMD_16H_L2I_PERF_CTR_6";
1447	//case 0xc001023f: return "AMD_16H_L2I_PERF_CTR_7";
1448	case 0xc0010240: return "AMD_15H_NB_PERF_CTL_0";
1449	case 0xc0010242: return "AMD_15H_NB_PERF_CTL_1";
1450	case 0xc0010244: return "AMD_15H_NB_PERF_CTL_2";
1451	case 0xc0010246: return "AMD_15H_NB_PERF_CTL_3";
1452	//case 0xc0010248: return "AMD_15H_NB_PERF_CTL_4";
1453	//case 0xc001024a: return "AMD_15H_NB_PERF_CTL_5";
1454	//case 0xc001024c: return "AMD_15H_NB_PERF_CTL_6";
1455	//case 0xc001024e: return "AMD_15H_NB_PERF_CTL_7";
1456	case 0xc0010241: return "AMD_15H_NB_PERF_CTR_0";
1457	case 0xc0010243: return "AMD_15H_NB_PERF_CTR_1";
1458	case 0xc0010245: return "AMD_15H_NB_PERF_CTR_2";
1459	case 0xc0010247: return "AMD_15H_NB_PERF_CTR_3";
1460	//case 0xc0010249: return "AMD_15H_NB_PERF_CTR_4";
1461	//case 0xc001024b: return "AMD_15H_NB_PERF_CTR_5";
1462	//case 0xc001024d: return "AMD_15H_NB_PERF_CTR_6";
1463	//case 0xc001024f: return "AMD_15H_NB_PERF_CTR_7";
1464	case 0xc0011000: return "AMD_K7_MCODE_CTL";
1465	case 0xc0011001: return "AMD_K7_APIC_CLUSTER_ID"; /* Mentioned in BKDG (r3.00) for fam16h when describing EBL_CR_POWERON. */
1466	case 0xc0011002: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_CPUID_CTL_STD07" : NULL;
1467	case 0xc0011003: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_CPUID_CTL_STD06" : NULL;
1468	case 0xc0011004: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_CPUID_CTL_STD01" : NULL;
1469	case 0xc0011005: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_CPUID_CTL_EXT01" : NULL;
1470	case 0xc0011006: return "AMD_K7_DEBUG_STS?";
1471	case 0xc0011007: return "AMD_K7_BH_TRACE_BASE?";
1472	case 0xc0011008: return "AMD_K7_BH_TRACE_PTR?";
1473	case 0xc0011009: return "AMD_K7_BH_TRACE_LIM?";
1474	case 0xc001100a: return "AMD_K7_HDT_CFG?";
1475	case 0xc001100b: return "AMD_K7_FAST_FLUSH_COUNT?";
1476	case 0xc001100c: return "AMD_K7_NODE_ID";
1477	case 0xc001100d: return "AMD_K8_LOGICAL_CPUS_NUM?";
1478	case 0xc001100e: return "AMD_K8_WRMSR_BP?";
1479	case 0xc001100f: return "AMD_K8_WRMSR_BP_MASK?";
1480	case 0xc0011010: return "AMD_K8_BH_TRACE_CTL?";
1481	case 0xc0011011: return "AMD_K8_BH_TRACE_USRD?";
1482	case 0xc0011012: return "AMD_K7_UNK_c001_1012";
1483	case 0xc0011013: return "AMD_K7_UNK_c001_1013";
1484	case 0xc0011014: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_XCPT_BP_RIP?" : "AMD_K7_MOBIL_DEBUG?";
1485	case 0xc0011015: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_XCPT_BP_RIP_MASK?" : NULL;
1486	case 0xc0011016: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_COND_HDT_VAL?" : NULL;
1487	case 0xc0011017: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_COND_HDT_VAL_MASK?" : NULL;
1488	case 0xc0011018: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_XCPT_BP_CTL?" : NULL;
1489	case 0xc0011019: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver ? "AMD_16H_DR1_ADDR_MASK" : NULL;
1490	case 0xc001101a: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver ? "AMD_16H_DR2_ADDR_MASK" : NULL;
1491	case 0xc001101b: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver ? "AMD_16H_DR3_ADDR_MASK" : NULL;
1492	case 0xc001101d: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_NB_BIST?" : NULL;
1493	case 0xc001101e: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_THERMTRIP_2?" : NULL;
1494	case 0xc001101f: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_NB_CFG?" : NULL;
1495	case 0xc0011020: return "AMD_K7_LS_CFG";
1496	case 0xc0011021: return "AMD_K7_IC_CFG";
1497	case 0xc0011022: return "AMD_K7_DC_CFG";
1498	case 0xc0011023: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AMD_15H_CU_CFG" : "AMD_K7_BU_CFG";
1499	case 0xc0011024: return "AMD_K7_DEBUG_CTL_2?";
1500	case 0xc0011025: return "AMD_K7_DR0_DATA_MATCH?";
1501	case 0xc0011026: return "AMD_K7_DR0_DATA_MATCH?";
1502	case 0xc0011027: return "AMD_K7_DR0_ADDR_MASK";
1503	case 0xc0011028: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_First ? "AMD_15H_FP_CFG"
1504	: CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch) ? "AMD_10H_UNK_c001_1028"
1505	: NULL;
1506	case 0xc0011029: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_First ? "AMD_15H_DC_CFG"
1507	: CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch) ? "AMD_10H_UNK_c001_1029"
1508	: NULL;
1509	case 0xc001102a: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AMD_15H_CU_CFG2"
1510	: CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch) \|\| g_enmMicroarch > kCpumMicroarch_AMD_15h_End
1511	? "AMD_10H_BU_CFG2" /* 10h & 16h */ : NULL;
1512	case 0xc001102b: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AMD_15H_CU_CFG3" : NULL;
1513	case 0xc001102c: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AMD_15H_EX_CFG" : NULL;
1514	case 0xc001102d: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AMD_15H_LS_CFG2" : NULL;
1515	case 0xc0011030: return "AMD_10H_IBS_FETCH_CTL";
1516	case 0xc0011031: return "AMD_10H_IBS_FETCH_LIN_ADDR";
1517	case 0xc0011032: return "AMD_10H_IBS_FETCH_PHYS_ADDR";
1518	case 0xc0011033: return "AMD_10H_IBS_OP_EXEC_CTL";
1519	case 0xc0011034: return "AMD_10H_IBS_OP_RIP";
1520	case 0xc0011035: return "AMD_10H_IBS_OP_DATA";
1521	case 0xc0011036: return "AMD_10H_IBS_OP_DATA2";
1522	case 0xc0011037: return "AMD_10H_IBS_OP_DATA3";
1523	case 0xc0011038: return "AMD_10H_IBS_DC_LIN_ADDR";
1524	case 0xc0011039: return "AMD_10H_IBS_DC_PHYS_ADDR";
1525	case 0xc001103a: return "AMD_10H_IBS_CTL";
1526	case 0xc001103b: return "AMD_14H_IBS_BR_TARGET";
1527
1528	case 0xc0011040: return "AMD_15H_UNK_c001_1040";
1529	case 0xc0011041: return "AMD_15H_UNK_c001_1041";
1530	case 0xc0011042: return "AMD_15H_UNK_c001_1042";
1531	case 0xc0011043: return "AMD_15H_UNK_c001_1043";
1532	case 0xc0011044: return "AMD_15H_UNK_c001_1044";
1533	case 0xc0011045: return "AMD_15H_UNK_c001_1045";
1534	case 0xc0011046: return "AMD_15H_UNK_c001_1046";
1535	case 0xc0011047: return "AMD_15H_UNK_c001_1047";
1536	case 0xc0011048: return "AMD_15H_UNK_c001_1048";
1537	case 0xc0011049: return "AMD_15H_UNK_c001_1049";
1538	case 0xc001104a: return "AMD_15H_UNK_c001_104a";
1539	case 0xc001104b: return "AMD_15H_UNK_c001_104b";
1540	case 0xc001104c: return "AMD_15H_UNK_c001_104c";
1541	case 0xc001104d: return "AMD_15H_UNK_c001_104d";
1542	case 0xc001104e: return "AMD_15H_UNK_c001_104e";
1543	case 0xc001104f: return "AMD_15H_UNK_c001_104f";
1544	case 0xc0011050: return "AMD_15H_UNK_c001_1050";
1545	case 0xc0011051: return "AMD_15H_UNK_c001_1051";
1546	case 0xc0011052: return "AMD_15H_UNK_c001_1052";
1547	case 0xc0011053: return "AMD_15H_UNK_c001_1053";
1548	case 0xc0011054: return "AMD_15H_UNK_c001_1054";
1549	case 0xc0011055: return "AMD_15H_UNK_c001_1055";
1550	case 0xc0011056: return "AMD_15H_UNK_c001_1056";
1551	case 0xc0011057: return "AMD_15H_UNK_c001_1057";
1552	case 0xc0011058: return "AMD_15H_UNK_c001_1058";
1553	case 0xc0011059: return "AMD_15H_UNK_c001_1059";
1554	case 0xc001105a: return "AMD_15H_UNK_c001_105a";
1555	case 0xc001105b: return "AMD_15H_UNK_c001_105b";
1556	case 0xc001105c: return "AMD_15H_UNK_c001_105c";
1557	case 0xc001105d: return "AMD_15H_UNK_c001_105d";
1558	case 0xc001105e: return "AMD_15H_UNK_c001_105e";
1559	case 0xc001105f: return "AMD_15H_UNK_c001_105f";
1560	case 0xc0011060: return "AMD_15H_UNK_c001_1060";
1561	case 0xc0011061: return "AMD_15H_UNK_c001_1061";
1562	case 0xc0011062: return "AMD_15H_UNK_c001_1062";
1563	case 0xc0011063: return "AMD_15H_UNK_c001_1063";
1564	case 0xc0011064: return "AMD_15H_UNK_c001_1064";
1565	case 0xc0011065: return "AMD_15H_UNK_c001_1065";
1566	case 0xc0011066: return "AMD_15H_UNK_c001_1066";
1567	case 0xc0011067: return "AMD_15H_UNK_c001_1067";
1568	case 0xc0011068: return "AMD_15H_UNK_c001_1068";
1569	case 0xc0011069: return "AMD_15H_UNK_c001_1069";
1570	case 0xc001106a: return "AMD_15H_UNK_c001_106a";
1571	case 0xc001106b: return "AMD_15H_UNK_c001_106b";
1572	case 0xc001106c: return "AMD_15H_UNK_c001_106c";
1573	case 0xc001106d: return "AMD_15H_UNK_c001_106d";
1574	case 0xc001106e: return "AMD_15H_UNK_c001_106e";
1575	case 0xc001106f: return "AMD_15H_UNK_c001_106f";
1576	case 0xc0011070: return "AMD_15H_UNK_c001_1070"; /* coreboot defines this, but with a numerical name. */
1577	case 0xc0011071: return "AMD_15H_UNK_c001_1071";
1578	case 0xc0011072: return "AMD_15H_UNK_c001_1072";
1579	case 0xc0011073: return "AMD_15H_UNK_c001_1073";
1580	case 0xc0011080: return "AMD_15H_UNK_c001_1080";
1581	}
1582
1583	/*
1584	* Bunch of unknown sandy bridge registers. They might seem like the
1585	* nehalem based xeon stuff, but the layout doesn't match. I bet it's the
1586	* same kind of registes though (i.e. uncore (UNC)).
1587	*
1588	* Kudos to Intel for keeping these a secret! Many thanks guys!!
1589	*/
1590	if (g_enmMicroarch == kCpumMicroarch_Intel_Core7_SandyBridge)
1591	switch (uMsr)
1592	{
1593	case 0x00000a00: return "I7_SB_UNK_0000_0a00"; case 0x00000a01: return "I7_SB_UNK_0000_0a01";
1594	case 0x00000a02: return "I7_SB_UNK_0000_0a02";
1595	case 0x00000c00: return "I7_SB_UNK_0000_0c00"; case 0x00000c01: return "I7_SB_UNK_0000_0c01";
1596	case 0x00000c06: return "I7_SB_UNK_0000_0c06"; case 0x00000c08: return "I7_SB_UNK_0000_0c08";
1597	case 0x00000c09: return "I7_SB_UNK_0000_0c09"; case 0x00000c10: return "I7_SB_UNK_0000_0c10";
1598	case 0x00000c11: return "I7_SB_UNK_0000_0c11"; case 0x00000c14: return "I7_SB_UNK_0000_0c14";
1599	case 0x00000c15: return "I7_SB_UNK_0000_0c15"; case 0x00000c16: return "I7_SB_UNK_0000_0c16";
1600	case 0x00000c17: return "I7_SB_UNK_0000_0c17"; case 0x00000c24: return "I7_SB_UNK_0000_0c24";
1601	case 0x00000c30: return "I7_SB_UNK_0000_0c30"; case 0x00000c31: return "I7_SB_UNK_0000_0c31";
1602	case 0x00000c32: return "I7_SB_UNK_0000_0c32"; case 0x00000c33: return "I7_SB_UNK_0000_0c33";
1603	case 0x00000c34: return "I7_SB_UNK_0000_0c34"; case 0x00000c35: return "I7_SB_UNK_0000_0c35";
1604	case 0x00000c36: return "I7_SB_UNK_0000_0c36"; case 0x00000c37: return "I7_SB_UNK_0000_0c37";
1605	case 0x00000c38: return "I7_SB_UNK_0000_0c38"; case 0x00000c39: return "I7_SB_UNK_0000_0c39";
1606	case 0x00000d04: return "I7_SB_UNK_0000_0d04";
1607	case 0x00000d10: return "I7_SB_UNK_0000_0d10"; case 0x00000d11: return "I7_SB_UNK_0000_0d11";
1608	case 0x00000d12: return "I7_SB_UNK_0000_0d12"; case 0x00000d13: return "I7_SB_UNK_0000_0d13";
1609	case 0x00000d14: return "I7_SB_UNK_0000_0d14"; case 0x00000d15: return "I7_SB_UNK_0000_0d15";
1610	case 0x00000d16: return "I7_SB_UNK_0000_0d16"; case 0x00000d17: return "I7_SB_UNK_0000_0d17";
1611	case 0x00000d18: return "I7_SB_UNK_0000_0d18"; case 0x00000d19: return "I7_SB_UNK_0000_0d19";
1612	case 0x00000d24: return "I7_SB_UNK_0000_0d24";
1613	case 0x00000d30: return "I7_SB_UNK_0000_0d30"; case 0x00000d31: return "I7_SB_UNK_0000_0d31";
1614	case 0x00000d32: return "I7_SB_UNK_0000_0d32"; case 0x00000d33: return "I7_SB_UNK_0000_0d33";
1615	case 0x00000d34: return "I7_SB_UNK_0000_0d34"; case 0x00000d35: return "I7_SB_UNK_0000_0d35";
1616	case 0x00000d36: return "I7_SB_UNK_0000_0d36"; case 0x00000d37: return "I7_SB_UNK_0000_0d37";
1617	case 0x00000d38: return "I7_SB_UNK_0000_0d38"; case 0x00000d39: return "I7_SB_UNK_0000_0d39";
1618	case 0x00000d44: return "I7_SB_UNK_0000_0d44";
1619	case 0x00000d50: return "I7_SB_UNK_0000_0d50"; case 0x00000d51: return "I7_SB_UNK_0000_0d51";
1620	case 0x00000d52: return "I7_SB_UNK_0000_0d52"; case 0x00000d53: return "I7_SB_UNK_0000_0d53";
1621	case 0x00000d54: return "I7_SB_UNK_0000_0d54"; case 0x00000d55: return "I7_SB_UNK_0000_0d55";
1622	case 0x00000d56: return "I7_SB_UNK_0000_0d56"; case 0x00000d57: return "I7_SB_UNK_0000_0d57";
1623	case 0x00000d58: return "I7_SB_UNK_0000_0d58"; case 0x00000d59: return "I7_SB_UNK_0000_0d59";
1624	case 0x00000d64: return "I7_SB_UNK_0000_0d64";
1625	case 0x00000d70: return "I7_SB_UNK_0000_0d70"; case 0x00000d71: return "I7_SB_UNK_0000_0d71";
1626	case 0x00000d72: return "I7_SB_UNK_0000_0d72"; case 0x00000d73: return "I7_SB_UNK_0000_0d73";
1627	case 0x00000d74: return "I7_SB_UNK_0000_0d74"; case 0x00000d75: return "I7_SB_UNK_0000_0d75";
1628	case 0x00000d76: return "I7_SB_UNK_0000_0d76"; case 0x00000d77: return "I7_SB_UNK_0000_0d77";
1629	case 0x00000d78: return "I7_SB_UNK_0000_0d78"; case 0x00000d79: return "I7_SB_UNK_0000_0d79";
1630	case 0x00000d84: return "I7_SB_UNK_0000_0d84";
1631	case 0x00000d90: return "I7_SB_UNK_0000_0d90"; case 0x00000d91: return "I7_SB_UNK_0000_0d91";
1632	case 0x00000d92: return "I7_SB_UNK_0000_0d92"; case 0x00000d93: return "I7_SB_UNK_0000_0d93";
1633	case 0x00000d94: return "I7_SB_UNK_0000_0d94"; case 0x00000d95: return "I7_SB_UNK_0000_0d95";
1634	case 0x00000d96: return "I7_SB_UNK_0000_0d96"; case 0x00000d97: return "I7_SB_UNK_0000_0d97";
1635	case 0x00000d98: return "I7_SB_UNK_0000_0d98"; case 0x00000d99: return "I7_SB_UNK_0000_0d99";
1636	case 0x00000da4: return "I7_SB_UNK_0000_0da4";
1637	case 0x00000db0: return "I7_SB_UNK_0000_0db0"; case 0x00000db1: return "I7_SB_UNK_0000_0db1";
1638	case 0x00000db2: return "I7_SB_UNK_0000_0db2"; case 0x00000db3: return "I7_SB_UNK_0000_0db3";
1639	case 0x00000db4: return "I7_SB_UNK_0000_0db4"; case 0x00000db5: return "I7_SB_UNK_0000_0db5";
1640	case 0x00000db6: return "I7_SB_UNK_0000_0db6"; case 0x00000db7: return "I7_SB_UNK_0000_0db7";
1641	case 0x00000db8: return "I7_SB_UNK_0000_0db8"; case 0x00000db9: return "I7_SB_UNK_0000_0db9";
1642	}
1643
1644	/*
1645	* Ditto for ivy bridge (observed on the i5-3570). There are some haswell
1646	* and sandybridge related docs on registers in this ares, but either
1647	* things are different for ivy or they're very incomplete. Again, kudos
1648	* to intel!
1649	*/
1650	if (g_enmMicroarch == kCpumMicroarch_Intel_Core7_IvyBridge)
1651	switch (uMsr)
1652	{
1653	case 0x00000700: return "I7_IB_UNK_0000_0700"; case 0x00000701: return "I7_IB_UNK_0000_0701";
1654	case 0x00000702: return "I7_IB_UNK_0000_0702"; case 0x00000703: return "I7_IB_UNK_0000_0703";
1655	case 0x00000704: return "I7_IB_UNK_0000_0704"; case 0x00000705: return "I7_IB_UNK_0000_0705";
1656	case 0x00000706: return "I7_IB_UNK_0000_0706"; case 0x00000707: return "I7_IB_UNK_0000_0707";
1657	case 0x00000708: return "I7_IB_UNK_0000_0708"; case 0x00000709: return "I7_IB_UNK_0000_0709";
1658	case 0x00000710: return "I7_IB_UNK_0000_0710"; case 0x00000711: return "I7_IB_UNK_0000_0711";
1659	case 0x00000712: return "I7_IB_UNK_0000_0712"; case 0x00000713: return "I7_IB_UNK_0000_0713";
1660	case 0x00000714: return "I7_IB_UNK_0000_0714"; case 0x00000715: return "I7_IB_UNK_0000_0715";
1661	case 0x00000716: return "I7_IB_UNK_0000_0716"; case 0x00000717: return "I7_IB_UNK_0000_0717";
1662	case 0x00000718: return "I7_IB_UNK_0000_0718"; case 0x00000719: return "I7_IB_UNK_0000_0719";
1663	case 0x00000720: return "I7_IB_UNK_0000_0720"; case 0x00000721: return "I7_IB_UNK_0000_0721";
1664	case 0x00000722: return "I7_IB_UNK_0000_0722"; case 0x00000723: return "I7_IB_UNK_0000_0723";
1665	case 0x00000724: return "I7_IB_UNK_0000_0724"; case 0x00000725: return "I7_IB_UNK_0000_0725";
1666	case 0x00000726: return "I7_IB_UNK_0000_0726"; case 0x00000727: return "I7_IB_UNK_0000_0727";
1667	case 0x00000728: return "I7_IB_UNK_0000_0728"; case 0x00000729: return "I7_IB_UNK_0000_0729";
1668	case 0x00000730: return "I7_IB_UNK_0000_0730"; case 0x00000731: return "I7_IB_UNK_0000_0731";
1669	case 0x00000732: return "I7_IB_UNK_0000_0732"; case 0x00000733: return "I7_IB_UNK_0000_0733";
1670	case 0x00000734: return "I7_IB_UNK_0000_0734"; case 0x00000735: return "I7_IB_UNK_0000_0735";
1671	case 0x00000736: return "I7_IB_UNK_0000_0736"; case 0x00000737: return "I7_IB_UNK_0000_0737";
1672	case 0x00000738: return "I7_IB_UNK_0000_0738"; case 0x00000739: return "I7_IB_UNK_0000_0739";
1673	case 0x00000740: return "I7_IB_UNK_0000_0740"; case 0x00000741: return "I7_IB_UNK_0000_0741";
1674	case 0x00000742: return "I7_IB_UNK_0000_0742"; case 0x00000743: return "I7_IB_UNK_0000_0743";
1675	case 0x00000744: return "I7_IB_UNK_0000_0744"; case 0x00000745: return "I7_IB_UNK_0000_0745";
1676	case 0x00000746: return "I7_IB_UNK_0000_0746"; case 0x00000747: return "I7_IB_UNK_0000_0747";
1677	case 0x00000748: return "I7_IB_UNK_0000_0748"; case 0x00000749: return "I7_IB_UNK_0000_0749";
1678
1679	}
1680	return NULL;
1681	}
1682
1683
1684	/**
1685	* Gets the name of an MSR.
1686	*
1687	* This may return a static buffer, so the content should only be considered
1688	* valid until the next time this function is called!.
1689	*
1690	* @returns MSR name.
1691	* @param uMsr The MSR in question.
1692	*/
1693	static const char *getMsrName(uint32_t uMsr)
1694	{
1695	const char *pszReadOnly = getMsrNameHandled(uMsr);
1696	if (pszReadOnly)
1697	return pszReadOnly;
1698
1699	/*
1700	* This MSR needs looking into, return a TODO_XXXX_XXXX name.
1701	*/
1702	static char s_szBuf[32];
1703	RTStrPrintf(s_szBuf, sizeof(s_szBuf), "TODO_%04x_%04x", RT_HI_U16(uMsr), RT_LO_U16(uMsr));
1704	return s_szBuf;
1705	}
1706
1707
1708
1709	/**
1710	* Gets the name of an MSR range.
1711	*
1712	* This may return a static buffer, so the content should only be considered
1713	* valid until the next time this function is called!.
1714	*
1715	* @returns MSR name.
1716	* @param uMsr The first MSR in the range.
1717	*/
1718	static const char *getMsrRangeName(uint32_t uMsr)
1719	{
1720	switch (uMsr)
1721	{
1722	case 0x00000040:
1723	return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_n_FROM_IP" : "MSR_LASTBRANCH_n";
1724	case 0x00000060:
1725	if (g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah)
1726	return "MSR_LASTBRANCH_n_TO_IP";
1727	break;
1728
1729	case 0x000003f8:
1730	case 0x000003f9:
1731	case 0x000003fa:
1732	return "I7_MSR_PKG_Cn_RESIDENCY";
1733	case 0x000003fc:
1734	case 0x000003fd:
1735	case 0x000003fe:
1736	return "I7_MSR_CORE_Cn_RESIDENCY";
1737
1738	case 0x00000400:
1739	return "IA32_MCi_CTL_STATUS_ADDR_MISC";
1740
1741	case 0x00000680:
1742	return "MSR_LASTBRANCH_n_FROM_IP";
1743	case 0x000006c0:
1744	return "MSR_LASTBRANCH_n_TO_IP";
1745
1746	case 0x00000800: case 0x00000801: case 0x00000802: case 0x00000803:
1747	case 0x00000804: case 0x00000805: case 0x00000806: case 0x00000807:
1748	case 0x00000808: case 0x00000809: case 0x0000080a: case 0x0000080b:
1749	case 0x0000080c: case 0x0000080d: case 0x0000080e: case 0x0000080f:
1750	return "IA32_X2APIC_n";
1751	}
1752
1753	static char s_szBuf[96];
1754	const char *pszReadOnly = getMsrNameHandled(uMsr);
1755	if (pszReadOnly)
1756	{
1757	/*
1758	* Replace the last char with 'n'.
1759	*/
1760	RTStrCopy(s_szBuf, sizeof(s_szBuf), pszReadOnly);
1761	size_t off = strlen(s_szBuf);
1762	if (off > 0)
1763	off--;
1764	if (off + 1 < sizeof(s_szBuf))
1765	{
1766	s_szBuf[off] = 'n';
1767	s_szBuf[off + 1] = '\0';
1768	}
1769	}
1770	else
1771	{
1772	/*
1773	* This MSR needs looking into, return a TODO_XXXX_XXXX_n name.
1774	*/
1775	RTStrPrintf(s_szBuf, sizeof(s_szBuf), "TODO_%04x_%04x_n", RT_HI_U16(uMsr), RT_LO_U16(uMsr));
1776	}
1777	return s_szBuf;
1778	}
1779
1780
1781	/**
1782	* Returns the function name for MSRs that have one or two.
1783	*
1784	* @returns Function name if applicable, NULL if not.
1785	* @param uMsr The MSR in question.
1786	* @param pfTakesValue Whether this MSR function takes a value or not.
1787	* Optional.
1788	*/
1789	static const char getMsrFnName(uint32_t uMsr, bool pfTakesValue)
1790	{
1791	bool fTmp;
1792	if (!pfTakesValue)
1793	pfTakesValue = &fTmp;
1794
1795	*pfTakesValue = false;
1796
1797	switch (uMsr)
1798	{
1799	case 0x00000000: return "Ia32P5McAddr";
1800	case 0x00000001: return "Ia32P5McType";
1801	case 0x00000006:
1802	if (g_enmMicroarch >= kCpumMicroarch_Intel_First && g_enmMicroarch <= kCpumMicroarch_Intel_P6_Core_Atom_First)
1803	return NULL; /* TR4 / cache tag on Pentium, but that's for later. */
1804	return "Ia32MonitorFilterLineSize";
1805	case 0x00000010: return "Ia32TimestampCounter";
1806	case 0x00000017: *pfTakesValue = true; return "Ia32PlatformId";
1807	case 0x0000001b: return "Ia32ApicBase";
1808	case 0x0000002a: *pfTakesValue = true; return g_fIntelNetBurst ? "IntelP4EbcHardPowerOn" : "IntelEblCrPowerOn";
1809	case 0x0000002b: *pfTakesValue = true; return g_fIntelNetBurst ? "IntelP4EbcSoftPowerOn" : NULL;
1810	case 0x0000002c: *pfTakesValue = true; return g_fIntelNetBurst ? "IntelP4EbcFrequencyId" : NULL;
1811	//case 0x00000033: return "IntelTestCtl";
1812	case 0x0000003a: return "Ia32FeatureControl";
1813
1814	case 0x00000040:
1815	case 0x00000041:
1816	case 0x00000042:
1817	case 0x00000043:
1818	case 0x00000044:
1819	case 0x00000045:
1820	case 0x00000046:
1821	case 0x00000047:
1822	return "IntelLastBranchFromToN";
1823
1824	case 0x0000008b: return g_enmVendor == CPUMCPUVENDOR_AMD ? "AmdK8PatchLevel" : "Ia32BiosSignId";
1825	case 0x0000009b: return "Ia32SmmMonitorCtl";
1826
1827	case 0x000000a8:
1828	case 0x000000a9:
1829	case 0x000000aa:
1830	case 0x000000ab:
1831	case 0x000000ac:
1832	case 0x000000ad:
1833	*pfTakesValue = true;
1834	return "IntelCore2EmttmCrTablesN";
1835
1836	case 0x000000c1:
1837	case 0x000000c2:
1838	case 0x000000c3:
1839	case 0x000000c4:
1840	return "Ia32PmcN";
1841	case 0x000000c5:
1842	case 0x000000c6:
1843	case 0x000000c7:
1844	case 0x000000c8:
1845	if (g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First)
1846	return "Ia32PmcN";
1847	return NULL;
1848
1849	case 0x000000cd: *pfTakesValue = true; return "IntelP6FsbFrequency";
1850	case 0x000000ce: return CPUMMICROARCH_IS_INTEL_CORE7(g_enmMicroarch) ? "IntelPlatformInfo" : NULL;
1851	case 0x000000e2: return "IntelPkgCStConfigControl";
1852	case 0x000000e3: return "IntelCore2SmmCStMiscInfo";
1853	case 0x000000e4: return "IntelPmgIoCaptureBase";
1854	case 0x000000e7: return "Ia32MPerf";
1855	case 0x000000e8: return "Ia32APerf";
1856	case 0x000000ee: return "IntelCore1ExtConfig";
1857	case 0x000000fe: *pfTakesValue = true; return "Ia32MtrrCap";
1858	case 0x00000119: *pfTakesValue = true; return "IntelBblCrCtl";
1859	case 0x0000011e: *pfTakesValue = true; return "IntelBblCrCtl3";
1860
1861	case 0x00000130: return g_enmMicroarch == kCpumMicroarch_Intel_Core7_Westmere
1862	\|\| g_enmMicroarch == kCpumMicroarch_Intel_Core7_Nehalem
1863	? "IntelCpuId1FeatureMaskEcdx" : NULL;
1864	case 0x00000131: return g_enmMicroarch == kCpumMicroarch_Intel_Core7_Westmere
1865	\|\| g_enmMicroarch == kCpumMicroarch_Intel_Core7_Nehalem
1866	? "IntelCpuId80000001FeatureMaskEcdx" : NULL;
1867	case 0x00000132: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
1868	? "IntelCpuId1FeatureMaskEax" : NULL;
1869	case 0x00000133: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
1870	? "IntelCpuId1FeatureMaskEcdx" : NULL;
1871	case 0x00000134: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
1872	? "IntelCpuId80000001FeatureMaskEcdx" : NULL;
1873	case 0x0000013c: return "IntelI7SandyAesNiCtl";
1874	case 0x0000015f: return "IntelCore1DtsCalControl";
1875	case 0x00000174: return "Ia32SysEnterCs";
1876	case 0x00000175: return "Ia32SysEnterEsp";
1877	case 0x00000176: return "Ia32SysEnterEip";
1878	case 0x00000179: *pfTakesValue = true; return "Ia32McgCap";
1879	case 0x0000017a: return "Ia32McgStatus";
1880	case 0x0000017b: return "Ia32McgCtl";
1881	case 0x0000017f: return "IntelI7SandyErrorControl"; /* SandyBridge. */
1882	case 0x00000186: return "Ia32PerfEvtSelN";
1883	case 0x00000187: return "Ia32PerfEvtSelN";
1884	case 0x00000193: return /g_fIntelNetBurst ? NULL :/ NULL /* Core2_Penryn. */;
1885	case 0x00000194: if (g_fIntelNetBurst) break; *pfTakesValue = true; return "IntelFlexRatio";
1886	case 0x00000198: *pfTakesValue = true; return "Ia32PerfStatus";
1887	case 0x00000199: *pfTakesValue = true; return "Ia32PerfCtl";
1888	case 0x0000019a: *pfTakesValue = true; return "Ia32ClockModulation";
1889	case 0x0000019b: *pfTakesValue = true; return "Ia32ThermInterrupt";
1890	case 0x0000019c: *pfTakesValue = true; return "Ia32ThermStatus";
1891	case 0x0000019d: *pfTakesValue = true; return "Ia32Therm2Ctl";
1892	case 0x000001a0: *pfTakesValue = true; return "Ia32MiscEnable";
1893	case 0x000001a2: *pfTakesValue = true; return "IntelI7TemperatureTarget";
1894	case 0x000001a6: return "IntelI7MsrOffCoreResponseN";
1895	case 0x000001a7: return "IntelI7MsrOffCoreResponseN";
1896	case 0x000001aa: return CPUMMICROARCH_IS_INTEL_CORE7(g_enmMicroarch) ? "IntelI7MiscPwrMgmt" : NULL /"P6PicSensCfg"/;
1897	case 0x000001ad: pfTakesValue = true; return "IntelI7TurboRatioLimit"; / SandyBridge+, Silvermount+ */
1898	case 0x000001c8: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_Nehalem ? "IntelI7LbrSelect" : NULL;
1899	case 0x000001c9: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah
1900	&& g_enmMicroarch <= kCpumMicroarch_Intel_P6_Core_Atom_End
1901	? "IntelLastBranchTos" : NULL /* Pentium M Dothan seems to have something else here. */;
1902	case 0x000001d7: return g_fIntelNetBurst ? "P6LastIntFromIp" : NULL;
1903	case 0x000001d8: return g_fIntelNetBurst ? "P6LastIntToIp" : NULL;
1904	case 0x000001d9: return "Ia32DebugCtl";
1905	case 0x000001da: return g_fIntelNetBurst ? "IntelLastBranchTos" : NULL;
1906	case 0x000001db: return g_fIntelNetBurst ? "IntelLastBranchFromToN" : "P6LastBranchFromIp";
1907	case 0x000001dc: return g_fIntelNetBurst ? "IntelLastBranchFromToN" : "P6LastBranchToIp";
1908	case 0x000001dd: return g_fIntelNetBurst ? "IntelLastBranchFromToN" : "P6LastIntFromIp";
1909	case 0x000001de: return g_fIntelNetBurst ? "IntelLastBranchFromToN" : "P6LastIntToIp";
1910	case 0x000001f0: return "IntelI7VirtualLegacyWireCap"; /* SandyBridge. */
1911	case 0x000001f2: return "Ia32SmrrPhysBase";
1912	case 0x000001f3: return "Ia32SmrrPhysMask";
1913	case 0x000001f8: return "Ia32PlatformDcaCap";
1914	case 0x000001f9: return "Ia32CpuDcaCap";
1915	case 0x000001fa: return "Ia32Dca0Cap";
1916	case 0x000001fc: return "IntelI7PowerCtl";
1917
1918	case 0x00000200: case 0x00000202: case 0x00000204: case 0x00000206:
1919	case 0x00000208: case 0x0000020a: case 0x0000020c: case 0x0000020e:
1920	case 0x00000210: case 0x00000212: case 0x00000214: case 0x00000216:
1921	case 0x00000218: case 0x0000021a: case 0x0000021c: case 0x0000021e:
1922	return "Ia32MtrrPhysBaseN";
1923	case 0x00000201: case 0x00000203: case 0x00000205: case 0x00000207:
1924	case 0x00000209: case 0x0000020b: case 0x0000020d: case 0x0000020f:
1925	case 0x00000211: case 0x00000213: case 0x00000215: case 0x00000217:
1926	case 0x00000219: case 0x0000021b: case 0x0000021d: case 0x0000021f:
1927	return "Ia32MtrrPhysMaskN";
1928	case 0x00000250:
1929	case 0x00000258: case 0x00000259:
1930	case 0x00000268: case 0x00000269: case 0x0000026a: case 0x0000026b:
1931	case 0x0000026c: case 0x0000026d: case 0x0000026e: case 0x0000026f:
1932	return "Ia32MtrrFixed";
1933	case 0x00000277: *pfTakesValue = true; return "Ia32Pat";
1934
1935	case 0x00000280: case 0x00000281: case 0x00000282: case 0x00000283:
1936	case 0x00000284: case 0x00000285: case 0x00000286: case 0x00000287:
1937	case 0x00000288: case 0x00000289: case 0x0000028a: case 0x0000028b:
1938	case 0x0000028c: case 0x0000028d: case 0x0000028e: case 0x0000028f:
1939	case 0x00000290: case 0x00000291: case 0x00000292: case 0x00000293:
1940	case 0x00000294: case 0x00000295: //case 0x00000296: case 0x00000297:
1941	//case 0x00000298: case 0x00000299: case 0x0000029a: case 0x0000029b:
1942	//case 0x0000029c: case 0x0000029d: case 0x0000029e: case 0x0000029f:
1943	return "Ia32McNCtl2";
1944
1945	case 0x000002ff: return "Ia32MtrrDefType";
1946	//case 0x00000305: return g_fIntelNetBurst ? TODO : NULL;
1947	case 0x00000309: return g_fIntelNetBurst ? NULL /** @todo P4 */ : "Ia32FixedCtrN";
1948	case 0x0000030a: return g_fIntelNetBurst ? NULL /** @todo P4 */ : "Ia32FixedCtrN";
1949	case 0x0000030b: return g_fIntelNetBurst ? NULL /** @todo P4 */ : "Ia32FixedCtrN";
1950	case 0x00000345: *pfTakesValue = true; return "Ia32PerfCapabilities";
1951	/* Note! Lots of P4 MSR 0x00000360..0x00000371. */
1952	case 0x0000038d: return "Ia32FixedCtrCtrl";
1953	case 0x0000038e: *pfTakesValue = true; return "Ia32PerfGlobalStatus";
1954	case 0x0000038f: return "Ia32PerfGlobalCtrl";
1955	case 0x00000390: return "Ia32PerfGlobalOvfCtrl";
1956	case 0x00000391: return "IntelI7UncPerfGlobalCtrl"; /* S,H,X */
1957	case 0x00000392: return "IntelI7UncPerfGlobalStatus"; /* S,H,X */
1958	case 0x00000393: return "IntelI7UncPerfGlobalOvfCtrl"; /* X. ASSUMING this is the same on sandybridge and later. */
1959	case 0x00000394: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPerfFixedCtr" /* X / : "IntelI7UncPerfFixedCtrCtrl"; / >= S,H */
1960	case 0x00000395: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPerfFixedCtrCtrl" /* X/ : "IntelI7UncPerfFixedCtr"; / >= S,H */
1961	case 0x00000396: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncAddrOpcodeMatch" /* X / : "IntelI7UncCBoxConfig"; / >= S,H */
1962	case 0x0000039c: return "IntelI7SandyPebsNumAlt";
1963	/* Note! Lots of P4 MSR 0x000003a0..0x000003e1. */
1964	case 0x000003b0: return g_fIntelNetBurst ? NULL : g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPmcN" /* X / : "IntelI7UncArbPerfCtrN"; / >= S,H */
1965	case 0x000003b1: return g_fIntelNetBurst ? NULL : g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPmcN" /* X / : "IntelI7UncArbPerfCtrN"; / >= S,H */
1966	case 0x000003b2: return g_fIntelNetBurst ? NULL : g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPmcN" /* X / : "IntelI7UncArbPerfEvtSelN"; / >= S,H */
1967	case 0x000003b3: return g_fIntelNetBurst ? NULL : g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPmcN" /* X / : "IntelI7UncArbPerfEvtSelN"; / >= S,H */
1968	case 0x000003b4: case 0x000003b5: case 0x000003b6: case 0x000003b7:
1969	return g_fIntelNetBurst ? NULL : "IntelI7UncPmcN";
1970	case 0x000003c0: case 0x000003c1: case 0x000003c2: case 0x000003c3:
1971	case 0x000003c4: case 0x000003c5: case 0x000003c6: case 0x000003c7:
1972	return g_fIntelNetBurst ? NULL : "IntelI7UncPerfEvtSelN";
1973	case 0x000003f1: return "Ia32PebsEnable";
1974	case 0x000003f6: return g_fIntelNetBurst ? NULL /??/ : "IntelI7PebsLdLat";
1975	case 0x000003f8: return g_fIntelNetBurst ? NULL : "IntelI7PkgCnResidencyN";
1976	case 0x000003f9: return "IntelI7PkgCnResidencyN";
1977	case 0x000003fa: return "IntelI7PkgCnResidencyN";
1978	case 0x000003fc: return "IntelI7CoreCnResidencyN";
1979	case 0x000003fd: return "IntelI7CoreCnResidencyN";
1980	case 0x000003fe: return "IntelI7CoreCnResidencyN";
1981
1982	case 0x00000478: return g_enmMicroarch == kCpumMicroarch_Intel_Core2_Penryn ? "IntelCpuId1FeatureMaskEcdx" : NULL;
1983	case 0x00000480: *pfTakesValue = true; return "Ia32VmxBase";
1984	case 0x00000481: *pfTakesValue = true; return "Ia32VmxPinbasedCtls";
1985	case 0x00000482: *pfTakesValue = true; return "Ia32VmxProcbasedCtls";
1986	case 0x00000483: *pfTakesValue = true; return "Ia32VmxExitCtls";
1987	case 0x00000484: *pfTakesValue = true; return "Ia32VmxEntryCtls";
1988	case 0x00000485: *pfTakesValue = true; return "Ia32VmxMisc";
1989	case 0x00000486: *pfTakesValue = true; return "Ia32VmxCr0Fixed0";
1990	case 0x00000487: *pfTakesValue = true; return "Ia32VmxCr0Fixed1";
1991	case 0x00000488: *pfTakesValue = true; return "Ia32VmxCr4Fixed0";
1992	case 0x00000489: *pfTakesValue = true; return "Ia32VmxCr4Fixed1";
1993	case 0x0000048a: *pfTakesValue = true; return "Ia32VmxVmcsEnum";
1994	case 0x0000048b: *pfTakesValue = true; return "Ia32VmxProcBasedCtls2";
1995	case 0x0000048c: *pfTakesValue = true; return "Ia32VmxEptVpidCap";
1996	case 0x0000048d: *pfTakesValue = true; return "Ia32VmxTruePinbasedCtls";
1997	case 0x0000048e: *pfTakesValue = true; return "Ia32VmxTrueProcbasedCtls";
1998	case 0x0000048f: *pfTakesValue = true; return "Ia32VmxTrueExitCtls";
1999	case 0x00000490: *pfTakesValue = true; return "Ia32VmxTrueEntryCtls";
2000
2001	case 0x000004c1:
2002	case 0x000004c2:
2003	case 0x000004c3:
2004	case 0x000004c4:
2005	case 0x000004c5:
2006	case 0x000004c6:
2007	case 0x000004c7:
2008	case 0x000004c8:
2009	return "Ia32PmcN";
2010
2011	case 0x000005a0: return "IntelCore2PeciControl"; /* Core2_Penryn. */
2012
2013	case 0x00000600: return "Ia32DsArea";
2014	case 0x00000601: return "IntelI7SandyVrCurrentConfig";
2015	case 0x00000603: return "IntelI7SandyVrMiscConfig";
2016	case 0x00000606: return "IntelI7SandyRaplPowerUnit";
2017	case 0x0000060a: return "IntelI7SandyPkgCnIrtlN";
2018	case 0x0000060b: return "IntelI7SandyPkgCnIrtlN";
2019	case 0x0000060c: return "IntelI7SandyPkgCnIrtlN";
2020	case 0x0000060d: return "IntelI7SandyPkgC2Residency";
2021
2022	case 0x00000610: return "IntelI7RaplPkgPowerLimit";
2023	case 0x00000611: return "IntelI7RaplPkgEnergyStatus";
2024	case 0x00000613: return "IntelI7RaplPkgPerfStatus";
2025	case 0x00000614: return "IntelI7RaplPkgPowerInfo";
2026	case 0x00000618: return "IntelI7RaplDramPowerLimit";
2027	case 0x00000619: return "IntelI7RaplDramEnergyStatus";
2028	case 0x0000061b: return "IntelI7RaplDramPerfStatus";
2029	case 0x0000061c: return "IntelI7RaplDramPowerInfo";
2030	case 0x00000638: return "IntelI7RaplPp0PowerLimit";
2031	case 0x00000639: return "IntelI7RaplPp0EnergyStatus";
2032	case 0x0000063a: return "IntelI7RaplPp0Policy";
2033	case 0x0000063b: return "IntelI7RaplPp0PerfStatus";
2034	case 0x00000640: return "IntelI7RaplPp1PowerLimit";
2035	case 0x00000641: return "IntelI7RaplPp1EnergyStatus";
2036	case 0x00000642: return "IntelI7RaplPp1Policy";
2037	case 0x00000648: return "IntelI7IvyConfigTdpNominal";
2038	case 0x00000649: return "IntelI7IvyConfigTdpLevel1";
2039	case 0x0000064a: return "IntelI7IvyConfigTdpLevel2";
2040	case 0x0000064b: return "IntelI7IvyConfigTdpControl";
2041	case 0x0000064c: return "IntelI7IvyTurboActivationRatio";
2042
2043	case 0x00000680: case 0x00000681: case 0x00000682: case 0x00000683:
2044	case 0x00000684: case 0x00000685: case 0x00000686: case 0x00000687:
2045	case 0x00000688: case 0x00000689: case 0x0000068a: case 0x0000068b:
2046	case 0x0000068c: case 0x0000068d: case 0x0000068e: case 0x0000068f:
2047	//case 0x00000690: case 0x00000691: case 0x00000692: case 0x00000693:
2048	//case 0x00000694: case 0x00000695: case 0x00000696: case 0x00000697:
2049	//case 0x00000698: case 0x00000699: case 0x0000069a: case 0x0000069b:
2050	//case 0x0000069c: case 0x0000069d: case 0x0000069e: case 0x0000069f:
2051	return "IntelLastBranchFromN";
2052	case 0x000006c0: case 0x000006c1: case 0x000006c2: case 0x000006c3:
2053	case 0x000006c4: case 0x000006c5: case 0x000006c6: case 0x000006c7:
2054	case 0x000006c8: case 0x000006c9: case 0x000006ca: case 0x000006cb:
2055	case 0x000006cc: case 0x000006cd: case 0x000006ce: case 0x000006cf:
2056	//case 0x000006d0: case 0x000006d1: case 0x000006d2: case 0x000006d3:
2057	//case 0x000006d4: case 0x000006d5: case 0x000006d6: case 0x000006d7:
2058	//case 0x000006d8: case 0x000006d9: case 0x000006da: case 0x000006db:
2059	//case 0x000006dc: case 0x000006dd: case 0x000006de: case 0x000006df:
2060	return "IntelLastBranchToN";
2061	case 0x000006e0: return "Ia32TscDeadline"; /** @todo detect this correctly! */
2062
2063	case 0x00000c80: return g_enmMicroarch > kCpumMicroarch_Intel_Core7_Nehalem ? "Ia32DebugInterface" : NULL;
2064
2065	case 0xc0000080: return "Amd64Efer";
2066	case 0xc0000081: return "Amd64SyscallTarget";
2067	case 0xc0000082: return "Amd64LongSyscallTarget";
2068	case 0xc0000083: return "Amd64CompSyscallTarget";
2069	case 0xc0000084: return "Amd64SyscallFlagMask";
2070	case 0xc0000100: return "Amd64FsBase";
2071	case 0xc0000101: return "Amd64GsBase";
2072	case 0xc0000102: return "Amd64KernelGsBase";
2073	case 0xc0000103: return "Amd64TscAux";
2074	case 0xc0000104: return "AmdFam15hTscRate";
2075	case 0xc0000105: return "AmdFam15hLwpCfg";
2076	case 0xc0000106: return "AmdFam15hLwpCbAddr";
2077	case 0xc0000408: return "AmdFam10hMc4MiscN";
2078	case 0xc0000409: return "AmdFam10hMc4MiscN";
2079	case 0xc000040a: return "AmdFam10hMc4MiscN";
2080	case 0xc000040b: return "AmdFam10hMc4MiscN";
2081	case 0xc000040c: return "AmdFam10hMc4MiscN";
2082	case 0xc000040d: return "AmdFam10hMc4MiscN";
2083	case 0xc000040e: return "AmdFam10hMc4MiscN";
2084	case 0xc000040f: return "AmdFam10hMc4MiscN";
2085	case 0xc0010000: return "AmdK8PerfCtlN";
2086	case 0xc0010001: return "AmdK8PerfCtlN";
2087	case 0xc0010002: return "AmdK8PerfCtlN";
2088	case 0xc0010003: return "AmdK8PerfCtlN";
2089	case 0xc0010004: return "AmdK8PerfCtrN";
2090	case 0xc0010005: return "AmdK8PerfCtrN";
2091	case 0xc0010006: return "AmdK8PerfCtrN";
2092	case 0xc0010007: return "AmdK8PerfCtrN";
2093	case 0xc0010010: *pfTakesValue = true; return "AmdK8SysCfg";
2094	case 0xc0010015: return "AmdK8HwCr";
2095	case 0xc0010016: case 0xc0010018: return "AmdK8IorrBaseN";
2096	case 0xc0010017: case 0xc0010019: return "AmdK8IorrMaskN";
2097	case 0xc001001a: case 0xc001001d: return "AmdK8TopOfMemN";
2098	case 0xc001001f: return "AmdK8NbCfg1";
2099	case 0xc0010020: return "AmdK8PatchLoader";
2100	case 0xc0010022: return "AmdK8McXcptRedir";
2101	case 0xc0010030: case 0xc0010031: case 0xc0010032:
2102	case 0xc0010033: case 0xc0010034: case 0xc0010035:
2103	return "AmdK8CpuNameN";
2104	case 0xc001003e: *pfTakesValue = true; return "AmdK8HwThermalCtrl";
2105	case 0xc001003f: return "AmdK8SwThermalCtrl";
2106	case 0xc0010041: *pfTakesValue = true; return "AmdK8FidVidControl";
2107	case 0xc0010042: *pfTakesValue = true; return "AmdK8FidVidStatus";
2108	case 0xc0010044: case 0xc0010045: case 0xc0010046: case 0xc0010047:
2109	case 0xc0010048: case 0xc0010049: case 0xc001004a: //case 0xc001004b:
2110	return "AmdK8McCtlMaskN";
2111	case 0xc0010050: case 0xc0010051: case 0xc0010052: case 0xc0010053:
2112	return "AmdK8SmiOnIoTrapN";
2113	case 0xc0010054: return "AmdK8SmiOnIoTrapCtlSts";
2114	case 0xc0010055: return "AmdK8IntPendingMessage";
2115	case 0xc0010056: return "AmdK8SmiTriggerIoCycle";
2116	case 0xc0010058: return "AmdFam10hMmioCfgBaseAddr";
2117	case 0xc0010059: return "AmdFam10hTrapCtlMaybe";
2118	case 0xc0010061: *pfTakesValue = true; return "AmdFam10hPStateCurLimit";
2119	case 0xc0010062: *pfTakesValue = true; return "AmdFam10hPStateControl";
2120	case 0xc0010063: *pfTakesValue = true; return "AmdFam10hPStateStatus";
2121	case 0xc0010064: case 0xc0010065: case 0xc0010066: case 0xc0010067:
2122	case 0xc0010068: case 0xc0010069: case 0xc001006a: case 0xc001006b:
2123	*pfTakesValue = true; return "AmdFam10hPStateN";
2124	case 0xc0010070: *pfTakesValue = true; return "AmdFam10hCofVidControl";
2125	case 0xc0010071: *pfTakesValue = true; return "AmdFam10hCofVidStatus";
2126	case 0xc0010073: return "AmdFam10hCStateIoBaseAddr";
2127	case 0xc0010074: return "AmdFam10hCpuWatchdogTimer";
2128	// case 0xc0010075: return "AmdFam15hApmlTdpLimit";
2129	// case 0xc0010077: return "AmdFam15hCpuPowerInTdp";
2130	// case 0xc0010078: return "AmdFam15hPowerAveragingPeriod";
2131	// case 0xc0010079: return "AmdFam15hDramCtrlCmdThrottle";
2132	// case 0xc0010080: return "AmdFam16hFreqSensFeedbackMonActCnt0";
2133	// case 0xc0010081: return "AmdFam16hFreqSensFeedbackMonRefCnt0";
2134	case 0xc0010111: return "AmdK8SmmBase"; /** @todo probably misdetected ign/gp due to locking */
2135	case 0xc0010112: return "AmdK8SmmAddr"; /** @todo probably misdetected ign/gp due to locking */
2136	case 0xc0010113: return "AmdK8SmmMask"; /** @todo probably misdetected ign/gp due to locking */
2137	case 0xc0010114: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm_AMDV ? "AmdK8VmCr" : NULL; /** @todo probably misdetected due to locking */
2138	case 0xc0010115: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm ? "AmdK8IgnNe" : NULL;
2139	case 0xc0010116: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm ? "AmdK8SmmCtl" : NULL;
2140	case 0xc0010117: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm_AMDV ? "AmdK8VmHSavePa" : NULL; /** @todo probably misdetected due to locking */
2141	case 0xc0010118: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm_AMDV ? "AmdFam10hVmLockKey" : NULL;
2142	case 0xc0010119: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm ? "AmdFam10hSmmLockKey" : NULL; /* Not documented by BKDG, found in netbsd patch. */
2143	case 0xc001011a: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm ? "AmdFam10hLocalSmiStatus" : NULL;
2144	case 0xc0010140: *pfTakesValue = true; return "AmdFam10hOsVisWrkIdLength";
2145	case 0xc0010141: *pfTakesValue = true; return "AmdFam10hOsVisWrkStatus";
2146	case 0xc0010200: case 0xc0010202: case 0xc0010204: case 0xc0010206:
2147	case 0xc0010208: case 0xc001020a: //case 0xc001020c: case 0xc001020e:
2148	return "AmdK8PerfCtlN";
2149	case 0xc0010201: case 0xc0010203: case 0xc0010205: case 0xc0010207:
2150	case 0xc0010209: case 0xc001020b: //case 0xc001020d: case 0xc001020f:
2151	return "AmdK8PerfCtrN";
2152	case 0xc0010230: case 0xc0010232: case 0xc0010234: case 0xc0010236:
2153	//case 0xc0010238: case 0xc001023a: case 0xc001030c: case 0xc001023e:
2154	return "AmdFam16hL2IPerfCtlN";
2155	case 0xc0010231: case 0xc0010233: case 0xc0010235: case 0xc0010237:
2156	//case 0xc0010239: case 0xc001023b: case 0xc001023d: case 0xc001023f:
2157	return "AmdFam16hL2IPerfCtrN";
2158	case 0xc0010240: case 0xc0010242: case 0xc0010244: case 0xc0010246:
2159	//case 0xc0010248: case 0xc001024a: case 0xc001024c: case 0xc001024e:
2160	return "AmdFam15hNorthbridgePerfCtlN";
2161	case 0xc0010241: case 0xc0010243: case 0xc0010245: case 0xc0010247:
2162	//case 0xc0010249: case 0xc001024b: case 0xc001024d: case 0xc001024f:
2163	return "AmdFam15hNorthbridgePerfCtrN";
2164	case 0xc0011000: *pfTakesValue = true; return "AmdK7MicrocodeCtl";
2165	case 0xc0011001: *pfTakesValue = true; return "AmdK7ClusterIdMaybe";
2166	case 0xc0011002: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AmdK8CpuIdCtlStd07hEbax" : NULL;
2167	case 0xc0011003: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AmdK8CpuIdCtlStd06hEcx" : NULL;
2168	case 0xc0011004: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AmdK8CpuIdCtlStd01hEdcx" : NULL;
2169	case 0xc0011005: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AmdK8CpuIdCtlExt01hEdcx" : NULL;
2170	case 0xc0011006: return "AmdK7DebugStatusMaybe";
2171	case 0xc0011007: return "AmdK7BHTraceBaseMaybe";
2172	case 0xc0011008: return "AmdK7BHTracePtrMaybe";
2173	case 0xc0011009: return "AmdK7BHTraceLimitMaybe";
2174	case 0xc001100a: return "AmdK7HardwareDebugToolCfgMaybe";
2175	case 0xc001100b: return "AmdK7FastFlushCountMaybe";
2176	case 0xc001100c: return "AmdK7NodeId"; /** @todo dunno if this was there is K7 already. Kinda doubt it. */
2177	case 0xc0011019: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver ? "AmdK7DrXAddrMaskN" : NULL;
2178	case 0xc001101a: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver ? "AmdK7DrXAddrMaskN" : NULL;
2179	case 0xc001101b: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver ? "AmdK7DrXAddrMaskN" : NULL;
2180	case 0xc0011020: return "AmdK7LoadStoreCfg";
2181	case 0xc0011021: return "AmdK7InstrCacheCfg";
2182	case 0xc0011022: return "AmdK7DataCacheCfg";
2183	case 0xc0011023: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AmdFam15hCombUnitCfg" : "AmdK7BusUnitCfg";
2184	case 0xc0011024: return "AmdK7DebugCtl2Maybe";
2185	case 0xc0011025: return "AmdK7Dr0DataMatchMaybe";
2186	case 0xc0011026: return "AmdK7Dr0DataMaskMaybe";
2187	case 0xc0011027: return "AmdK7DrXAddrMaskN";
2188	case 0xc0011028: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_First ? "AmdFam15hFpuCfg" : NULL;
2189	case 0xc0011029: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_First ? "AmdFam15hDecoderCfg" : NULL;
2190	case 0xc001102a: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AmdFam15hCombUnitCfg2"
2191	: CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch) \|\| g_enmMicroarch > kCpumMicroarch_AMD_15h_End
2192	? "AmdFam10hBusUnitCfg2" /* 10h & 16h */ : NULL;
2193	case 0xc001102b: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AmdFam15hCombUnitCfg3" : NULL;
2194	case 0xc001102c: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AmdFam15hExecUnitCfg" : NULL;
2195	case 0xc001102d: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AmdFam15hLoadStoreCfg2" : NULL;
2196	case 0xc0011030: return "AmdFam10hIbsFetchCtl";
2197	case 0xc0011031: return "AmdFam10hIbsFetchLinAddr";
2198	case 0xc0011032: return "AmdFam10hIbsFetchPhysAddr";
2199	case 0xc0011033: return "AmdFam10hIbsOpExecCtl";
2200	case 0xc0011034: return "AmdFam10hIbsOpRip";
2201	case 0xc0011035: return "AmdFam10hIbsOpData";
2202	case 0xc0011036: return "AmdFam10hIbsOpData2";
2203	case 0xc0011037: return "AmdFam10hIbsOpData3";
2204	case 0xc0011038: return "AmdFam10hIbsDcLinAddr";
2205	case 0xc0011039: return "AmdFam10hIbsDcPhysAddr";
2206	case 0xc001103a: return "AmdFam10hIbsCtl";
2207	case 0xc001103b: return "AmdFam14hIbsBrTarget";
2208	}
2209	return NULL;
2210	}
2211
2212
2213	/**
2214	* Names CPUMCPU variables that MSRs corresponds to.
2215	*
2216	* @returns The variable name @a uMsr corresponds to, NULL if no variable.
2217	* @param uMsr The MSR in question.
2218	*/
2219	static const char *getMsrCpumCpuVarName(uint32_t uMsr)
2220	{
2221	switch (uMsr)
2222	{
2223	case 0x00000250: return "GuestMsrs.msr.MtrrFix64K_00000";
2224	case 0x00000258: return "GuestMsrs.msr.MtrrFix16K_80000";
2225	case 0x00000259: return "GuestMsrs.msr.MtrrFix16K_A0000";
2226	case 0x00000268: return "GuestMsrs.msr.MtrrFix4K_C0000";
2227	case 0x00000269: return "GuestMsrs.msr.MtrrFix4K_C8000";
2228	case 0x0000026a: return "GuestMsrs.msr.MtrrFix4K_D0000";
2229	case 0x0000026b: return "GuestMsrs.msr.MtrrFix4K_D8000";
2230	case 0x0000026c: return "GuestMsrs.msr.MtrrFix4K_E0000";
2231	case 0x0000026d: return "GuestMsrs.msr.MtrrFix4K_E8000";
2232	case 0x0000026e: return "GuestMsrs.msr.MtrrFix4K_F0000";
2233	case 0x0000026f: return "GuestMsrs.msr.MtrrFix4K_F8000";
2234	case 0x00000277: return "Guest.msrPAT";
2235	case 0x000002ff: return "GuestMsrs.msr.MtrrDefType";
2236	}
2237	return NULL;
2238	}
2239
2240
2241	/**
2242	* Checks whether the MSR should read as zero for some reason.
2243	*
2244	* @returns true if the register should read as zero, false if not.
2245	* @param uMsr The MSR.
2246	*/
2247	static bool doesMsrReadAsZero(uint32_t uMsr)
2248	{
2249	switch (uMsr)
2250	{
2251	case 0x00000088: return true; // "BBL_CR_D0" - RAZ until understood/needed.
2252	case 0x00000089: return true; // "BBL_CR_D1" - RAZ until understood/needed.
2253	case 0x0000008a: return true; // "BBL_CR_D2" - RAZ until understood/needed.
2254
2255	/* Non-zero, but unknown register. */
2256	case 0x0000004a:
2257	case 0x0000004b:
2258	case 0x0000004c:
2259	case 0x0000004d:
2260	case 0x0000004e:
2261	case 0x0000004f:
2262	case 0x00000050:
2263	case 0x00000051:
2264	case 0x00000052:
2265	case 0x00000053:
2266	case 0x00000054:
2267	case 0x0000008c:
2268	case 0x0000008d:
2269	case 0x0000008e:
2270	case 0x0000008f:
2271	case 0x00000090:
2272	case 0xc0011011:
2273	return true;
2274	}
2275
2276	return false;
2277	}
2278
2279
2280	/**
2281	* Gets the skip mask for the given MSR.
2282	*
2283	* @returns Skip mask (0 means skipping nothing).
2284	* @param uMsr The MSR.
2285	*/
2286	static uint64_t getGenericSkipMask(uint32_t uMsr)
2287	{
2288	switch (uMsr)
2289	{
2290	case 0x0000013c: return 3; /* AES-NI lock bit ++. */
2291
2292	case 0x000001f2: return UINT64_C(0xfffff00f); /* Ia32SmrrPhysBase - Only writable in SMM. */
2293	case 0x000001f3: return UINT64_C(0xfffff800); /* Ia32SmrrPhysMask - Only writable in SMM. */
2294
2295	/* these two have lock bits. */
2296	case 0x0000064b: return UINT64_C(0x80000003);
2297	case 0x0000064c: return UINT64_C(0x800000ff);
2298
2299	case 0xc0010015: return 1; /* SmmLock bit */
2300
2301	/* SmmLock effect: */
2302	case 0xc0010111: return UINT32_MAX;
2303	case 0xc0010112: return UINT64_C(0xfffe0000) \| ((RT_BIT_64(vbCpuRepGetPhysAddrWidth()) - 1) & ~(uint64_t)UINT32_MAX);
2304	case 0xc0010113: return UINT64_C(0xfffe773f) \| ((RT_BIT_64(vbCpuRepGetPhysAddrWidth()) - 1) & ~(uint64_t)UINT32_MAX);
2305	case 0xc0010116: return 0x1f;
2306
2307	case 0xc0010114: return RT_BIT_64(3) /* SVM lock / \| RT_BIT_64(4) / SvmeDisable */;
2308
2309	/* Canonical */
2310	case 0xc0011034:
2311	case 0xc0011038:
2312	case 0xc001103b:
2313	return UINT64_C(0xffff800000000000);
2314
2315	case 0x00000060: case 0x00000061: case 0x00000062: case 0x00000063:
2316	case 0x00000064: case 0x00000065: case 0x00000066: case 0x00000067:
2317	case 0x00000040: case 0x00000041: case 0x00000042: case 0x00000043:
2318	case 0x00000044: case 0x00000045: case 0x00000046: case 0x00000047:
2319	case 0x00000600:
2320	if (g_enmMicroarch >= kCpumMicroarch_Intel_Core2_First)
2321	return UINT64_C(0xffff800000000000);
2322	break;
2323
2324
2325	/* Write only bits. */
2326	case 0xc0010041: return RT_BIT_64(16); /* FIDVID_CTL.InitFidVid */
2327
2328	/* Time counters - fudge them to avoid incorrect ignore masks. */
2329	case 0x00000010:
2330	case 0x000000e7:
2331	case 0x000000e8:
2332	return RT_BIT_32(29) - 1;
2333	}
2334	return 0;
2335	}
2336
2337
2338
2339
2340	/** queryMsrWriteBadness return values. */
2341	typedef enum
2342	{
2343	/** . */
2344	VBCPUREPBADNESS_MOSTLY_HARMLESS = 0,
2345	/** Not a problem if accessed with care. */
2346	VBCPUREPBADNESS_MIGHT_BITE,
2347	/** Worse than a bad james bond villain. */
2348	VBCPUREPBADNESS_BOND_VILLAIN
2349	} VBCPUREPBADNESS;
2350
2351
2352	/**
2353	* Backlisting and graylisting of MSRs which may cause tripple faults.
2354	*
2355	* @returns Badness factor.
2356	* @param uMsr The MSR in question.
2357	*/
2358	static VBCPUREPBADNESS queryMsrWriteBadness(uint32_t uMsr)
2359	{
2360	/** @todo Having trouble in the 0xc0010247,0xc0011006,?? region on Bulldozer. */
2361	/** @todo Having trouble in the 0xc001100f,0xc001100d,?? region on Opteron
2362	* 2384. */
2363
2364	switch (uMsr)
2365	{
2366	case 0x00000050:
2367	case 0x00000051:
2368	case 0x00000052:
2369	case 0x00000053:
2370	case 0x00000054:
2371
2372	case 0x00001006:
2373	case 0x00001007:
2374	return VBCPUREPBADNESS_BOND_VILLAIN;
2375
2376	case 0x0000120e:
2377	case 0x00001233:
2378	case 0x00001239:
2379	case 0x00001249:
2380	case 0x0000124a:
2381	case 0x00001404:
2382	case 0x00001405:
2383	case 0x00001413:
2384	case 0x0000142c: /* Caused rip to be set to 297 or some such weirdness... */
2385	case 0x0000142e:
2386	case 0x00001435:
2387	case 0x00001436:
2388	case 0x00001438:
2389	case 0x0000317f:
2390	if (g_enmVendor == CPUMCPUVENDOR_VIA)
2391	return VBCPUREPBADNESS_BOND_VILLAIN;
2392	break;
2393
2394	case 0xc0010010:
2395	case 0xc0010016:
2396	case 0xc0010017:
2397	case 0xc0010018:
2398	case 0xc0010019:
2399	case 0xc001001a:
2400	case 0xc001001d:
2401	case 0xc0010064: /* P-state fequency, voltage, ++. */
2402	case 0xc0010065: /* P-state fequency, voltage, ++. */
2403	case 0xc0010066: /* P-state fequency, voltage, ++. */
2404	case 0xc0010067: /* P-state fequency, voltage, ++. */
2405	case 0xc0010068: /* P-state fequency, voltage, ++. */
2406	case 0xc0010069: /* P-state fequency, voltage, ++. */
2407	case 0xc001006a: /* P-state fequency, voltage, ++. */
2408	case 0xc001006b: /* P-state fequency, voltage, ++. */
2409	case 0xc0010070: /* COFVID Control. */
2410	case 0xc001101e:
2411	case 0xc0011021: /* IC_CFG (instruction cache configuration) */
2412	case 0xc0011023: /* CU_CFG (combined unit configuration) */
2413	case 0xc001102c: /* EX_CFG (execution unit configuration) */
2414	return VBCPUREPBADNESS_BOND_VILLAIN;
2415
2416	case 0xc0011012:
2417	if (CPUMMICROARCH_IS_AMD_FAM_0FH(g_enmMicroarch))
2418	return VBCPUREPBADNESS_MIGHT_BITE;
2419	break;
2420
2421	case 0x000001a0: /* IA32_MISC_ENABLE */
2422	case 0x00000199: /* IA32_PERF_CTL */
2423	return VBCPUREPBADNESS_MIGHT_BITE;
2424	case 0x00002000: /* P6_CR0. */
2425	case 0x00002003: /* P6_CR3. */
2426	case 0x00002004: /* P6_CR4. */
2427	if (g_enmVendor == CPUMCPUVENDOR_INTEL)
2428	return VBCPUREPBADNESS_MIGHT_BITE;
2429	break;
2430	case 0xc0000080: /* MSR_K6_EFER */
2431	return VBCPUREPBADNESS_MIGHT_BITE;
2432	}
2433	return VBCPUREPBADNESS_MOSTLY_HARMLESS;
2434	}
2435
2436
2437	/**
2438	* Checks if this might be a VIA dummy register.
2439	*
2440	* @returns true if it's a dummy, false if it isn't.
2441	* @param uMsr The MSR.
2442	* @param uValue The value.
2443	* @param fFlags The flags.
2444	*/
2445	static bool isMsrViaDummy(uint32_t uMsr, uint64_t uValue, uint32_t fFlags)
2446	{
2447	if (g_enmVendor != CPUMCPUVENDOR_VIA)
2448	return false;
2449
2450	if (uValue)
2451	return false;
2452
2453	if (fFlags)
2454	return false;
2455
2456	switch (uMsr)
2457	{
2458	case 0x00000010:
2459	case 0x0000001b:
2460	case 0x000000c1:
2461	case 0x000000c2:
2462	case 0x0000011e:
2463	case 0x00000186:
2464	case 0x00000187:
2465	//case 0x00000200 ... (mtrrs will be detected)
2466	return false;
2467
2468	case 0xc0000080:
2469	case 0xc0000081:
2470	case 0xc0000082:
2471	case 0xc0000083:
2472	if (vbCpuRepSupportsLongMode())
2473	return false;
2474	break;
2475	}
2476
2477	if (uMsr >= 0x00001200 && uMsr <= 0x00003fff && queryMsrWriteBadness(uMsr) != VBCPUREPBADNESS_MOSTLY_HARMLESS)
2478	return false;
2479
2480	if ( !msrProberModifyNoChange(uMsr)
2481	&& !msrProberModifyZero(uMsr))
2482	return false;
2483
2484	uint64_t fIgnMask = 0;
2485	uint64_t fGpMask = 0;
2486	int rc = msrProberModifyBitChanges(uMsr, &fIgnMask, &fGpMask, 0);
2487	if (RT_FAILURE(rc))
2488	return false;
2489
2490	if (fIgnMask != UINT64_MAX)
2491	return false;
2492	if (fGpMask != 0)
2493	return false;
2494
2495	return true;
2496	}
2497
2498
2499
2500
2501	/**
2502	* Prints a 64-bit value in the best way.
2503	*
2504	* @param uValue The value.
2505	*/
2506	static void printMsrValueU64(uint64_t uValue)
2507	{
2508	if (uValue == 0)
2509	vbCpuRepPrintf(", 0");
2510	else if (uValue == UINT16_MAX)
2511	vbCpuRepPrintf(", UINT16_MAX");
2512	else if (uValue == UINT32_MAX)
2513	vbCpuRepPrintf(", UINT32_MAX");
2514	else if (uValue == UINT64_MAX)
2515	vbCpuRepPrintf(", UINT64_MAX");
2516	else if (uValue == UINT64_C(0xffffffff00000000))
2517	vbCpuRepPrintf(", ~(uint64_t)UINT32_MAX");
2518	else if (uValue <= (UINT32_MAX >> 1))
2519	vbCpuRepPrintf(", %#llx", uValue);
2520	else if (uValue <= UINT32_MAX)
2521	vbCpuRepPrintf(", UINT32_C(%#llx)", uValue);
2522	else
2523	vbCpuRepPrintf(", UINT64_C(%#llx)", uValue);
2524	}
2525
2526
2527	/**
2528	* Prints the newline after an MSR line has been printed.
2529	*
2530	* This is used as a hook to slow down the output and make sure the remote
2531	* terminal or/and output file has received the last update before we go and
2532	* crash probing the next MSR.
2533	*/
2534	static void printMsrNewLine(void)
2535	{
2536	vbCpuRepPrintf("\n");
2537	#if 1
2538	RTThreadSleep(8);
2539	#endif
2540	}
2541
2542	static int printMsrWriteOnly(uint32_t uMsr, const char pszWrFnName, const char pszAnnotation)
2543	{
2544	if (!pszWrFnName)
2545	pszWrFnName = "IgnoreWrite";
2546	vbCpuRepPrintf(pszAnnotation
2547	? " MFN(%#010x, \"%s\", WriteOnly, %s), /* %s */"
2548	: " MFN(%#010x, \"%s\", WriteOnly, %s),",
2549	uMsr, getMsrName(uMsr), pszWrFnName, pszAnnotation);
2550	printMsrNewLine();
2551	return VINF_SUCCESS;
2552	}
2553
2554
2555	static int printMsrValueReadOnly(uint32_t uMsr, uint64_t uValue, const char *pszAnnotation)
2556	{
2557	vbCpuRepPrintf(" MVO(%#010x, \"%s\"", uMsr, getMsrName(uMsr));
2558	printMsrValueU64(uValue);
2559	vbCpuRepPrintf("),");
2560	if (pszAnnotation)
2561	vbCpuRepPrintf(" /* %s */", pszAnnotation);
2562	printMsrNewLine();
2563	return VINF_SUCCESS;
2564	}
2565
2566
2567
2568	static int printMsrValueIgnoreWritesNamed(uint32_t uMsr, uint64_t uValue, const char pszName, const char pszAnnotation)
2569	{
2570	vbCpuRepPrintf(" MVI(%#010x, \"%s\"", uMsr, pszName);
2571	printMsrValueU64(uValue);
2572	vbCpuRepPrintf("),");
2573	if (pszAnnotation)
2574	vbCpuRepPrintf(" /* %s */", pszAnnotation);
2575	printMsrNewLine();
2576	return VINF_SUCCESS;
2577	}
2578
2579
2580	static int printMsrValueIgnoreWrites(uint32_t uMsr, uint64_t uValue, const char *pszAnnotation)
2581	{
2582	return printMsrValueIgnoreWritesNamed(uMsr, uValue, getMsrName(uMsr), pszAnnotation);
2583	}
2584
2585
2586	static int printMsrValueExtended(uint32_t uMsr, uint64_t uValue, uint64_t fIgnMask, uint64_t fGpMask,
2587	const char *pszAnnotation)
2588	{
2589	vbCpuRepPrintf(" MVX(%#010x, \"%s\"", uMsr, getMsrName(uMsr));
2590	printMsrValueU64(uValue);
2591	printMsrValueU64(fIgnMask);
2592	printMsrValueU64(fGpMask);
2593	vbCpuRepPrintf("),");
2594	if (pszAnnotation)
2595	vbCpuRepPrintf(" /* %s */", pszAnnotation);
2596	printMsrNewLine();
2597	return VINF_SUCCESS;
2598	}
2599
2600
2601	static int printMsrRangeValueReadOnly(uint32_t uMsr, uint32_t uLast, uint64_t uValue, const char *pszAnnotation)
2602	{
2603	vbCpuRepPrintf(" RVO(%#010x, %#010x, \"%s\"", uMsr, uLast, getMsrRangeName(uMsr));
2604	printMsrValueU64(uValue);
2605	vbCpuRepPrintf("),");
2606	if (pszAnnotation)
2607	vbCpuRepPrintf(" /* %s */", pszAnnotation);
2608	printMsrNewLine();
2609	return VINF_SUCCESS;
2610	}
2611
2612
2613	static int printMsrRangeValueIgnoreWritesNamed(uint32_t uMsr, uint32_t uLast, uint64_t uValue, const char pszName, const char pszAnnotation)
2614	{
2615	vbCpuRepPrintf(" RVI(%#010x, %#010x, \"%s\"", uMsr, uLast, pszName);
2616	printMsrValueU64(uValue);
2617	vbCpuRepPrintf("),");
2618	if (pszAnnotation)
2619	vbCpuRepPrintf(" /* %s */", pszAnnotation);
2620	printMsrNewLine();
2621	return VINF_SUCCESS;
2622	}
2623
2624
2625	static int printMsrRangeValueIgnoreWrites(uint32_t uMsr, uint32_t uLast, uint64_t uValue, const char *pszAnnotation)
2626	{
2627	return printMsrRangeValueIgnoreWritesNamed(uMsr, uLast, uValue, getMsrRangeName(uMsr), pszAnnotation);
2628	}
2629
2630
2631	static int printMsrFunction(uint32_t uMsr, const char pszRdFnName, const char pszWrFnName, const char *pszAnnotation)
2632	{
2633	if (!pszRdFnName)
2634	pszRdFnName = getMsrFnName(uMsr, NULL);
2635	if (!pszWrFnName)
2636	pszWrFnName = pszRdFnName;
2637	vbCpuRepPrintf(" MFN(%#010x, \"%s\", %s, %s),", uMsr, getMsrName(uMsr), pszRdFnName, pszWrFnName);
2638	if (pszAnnotation)
2639	vbCpuRepPrintf(" /* %s */", pszAnnotation);
2640	printMsrNewLine();
2641	return VINF_SUCCESS;
2642	}
2643
2644
2645	static int printMsrFunctionReadOnly(uint32_t uMsr, const char pszRdFnName, const char pszAnnotation)
2646	{
2647	if (!pszRdFnName)
2648	pszRdFnName = getMsrFnName(uMsr, NULL);
2649	vbCpuRepPrintf(" MFO(%#010x, \"%s\", %s),", uMsr, getMsrName(uMsr), pszRdFnName);
2650	if (pszAnnotation)
2651	vbCpuRepPrintf(" /* %s */", pszAnnotation);
2652	printMsrNewLine();
2653	return VINF_SUCCESS;
2654	}
2655
2656
2657	static int printMsrFunctionIgnoreWrites(uint32_t uMsr, const char pszRdFnName, const char pszAnnotation)
2658	{
2659	if (!pszRdFnName)
2660	pszRdFnName = getMsrFnName(uMsr, NULL);
2661	vbCpuRepPrintf(" MFI(%#010x, \"%s\", %s),", uMsr, getMsrName(uMsr), pszRdFnName);
2662	if (pszAnnotation)
2663	vbCpuRepPrintf(" /* %s */", pszAnnotation);
2664	printMsrNewLine();
2665	return VINF_SUCCESS;
2666	}
2667
2668
2669	static int printMsrFunctionIgnoreMask(uint32_t uMsr, const char pszRdFnName, const char pszWrFnName,
2670	uint64_t fIgnMask, const char *pszAnnotation)
2671	{
2672	if (!pszRdFnName)
2673	pszRdFnName = getMsrFnName(uMsr, NULL);
2674	if (!pszWrFnName)
2675	pszWrFnName = pszRdFnName;
2676	vbCpuRepPrintf(" MFW(%#010x, \"%s\", %s, %s", uMsr, getMsrName(uMsr), pszRdFnName, pszWrFnName);
2677	printMsrValueU64(fIgnMask);
2678	vbCpuRepPrintf("),");
2679	if (pszAnnotation)
2680	vbCpuRepPrintf(" /* %s */", pszAnnotation);
2681	printMsrNewLine();
2682	return VINF_SUCCESS;
2683	}
2684
2685
2686	static int printMsrFunctionExtended(uint32_t uMsr, const char pszRdFnName, const char pszWrFnName, uint64_t uValue,
2687	uint64_t fIgnMask, uint64_t fGpMask, const char *pszAnnotation)
2688	{
2689	if (!pszRdFnName)
2690	pszRdFnName = getMsrFnName(uMsr, NULL);
2691	if (!pszWrFnName)
2692	pszWrFnName = pszRdFnName;
2693	vbCpuRepPrintf(" MFX(%#010x, \"%s\", %s, %s", uMsr, getMsrName(uMsr), pszRdFnName, pszWrFnName);
2694	printMsrValueU64(uValue);
2695	printMsrValueU64(fIgnMask);
2696	printMsrValueU64(fGpMask);
2697	vbCpuRepPrintf("),");
2698	if (pszAnnotation)
2699	vbCpuRepPrintf(" /* %s */", pszAnnotation);
2700	printMsrNewLine();
2701	return VINF_SUCCESS;
2702	}
2703
2704
2705	static int printMsrFunctionExtendedIdxVal(uint32_t uMsr, const char pszRdFnName, const char pszWrFnName, uint64_t uValue,
2706	uint64_t fIgnMask, uint64_t fGpMask, const char *pszAnnotation)
2707	{
2708	if (!pszRdFnName)
2709	pszRdFnName = getMsrFnName(uMsr, NULL);
2710	if (!pszWrFnName)
2711	pszWrFnName = pszRdFnName;
2712	vbCpuRepPrintf(" MFX(%#010x, \"%s\", %s, %s, %#x", uMsr, getMsrName(uMsr), pszRdFnName, pszWrFnName, uValue);
2713	printMsrValueU64(fIgnMask);
2714	printMsrValueU64(fGpMask);
2715	vbCpuRepPrintf("),");
2716	if (pszAnnotation)
2717	vbCpuRepPrintf(" /* %s */", pszAnnotation);
2718	printMsrNewLine();
2719	return VINF_SUCCESS;
2720	}
2721
2722
2723	static int printMsrFunctionCpumCpu(uint32_t uMsr, const char pszRdFnName, const char pszWrFnName,
2724	const char pszCpumCpuStorage, const char pszAnnotation)
2725	{
2726	if (!pszRdFnName)
2727	pszRdFnName = getMsrFnName(uMsr, NULL);
2728	if (!pszWrFnName)
2729	pszWrFnName = pszRdFnName;
2730	if (!pszCpumCpuStorage)
2731	pszCpumCpuStorage = getMsrCpumCpuVarName(uMsr);
2732	if (!pszCpumCpuStorage)
2733	return RTMsgErrorRc(VERR_NOT_FOUND, "Missing CPUMCPU member for %#s (%#x)\n", getMsrName(uMsr), uMsr);
2734	vbCpuRepPrintf(" MFS(%#010x, \"%s\", %s, %s, %s),", uMsr, getMsrName(uMsr), pszRdFnName, pszWrFnName, pszCpumCpuStorage);
2735	if (pszAnnotation)
2736	vbCpuRepPrintf(" /* %s */", pszAnnotation);
2737	printMsrNewLine();
2738	return VINF_SUCCESS;
2739	}
2740
2741
2742	static int printMsrFunctionCpumCpuEx(uint32_t uMsr, const char pszRdFnName, const char pszWrFnName,
2743	const char *pszCpumCpuStorage, uint64_t fIgnMask, uint64_t fGpMask,
2744	const char *pszAnnotation)
2745	{
2746	if (!pszRdFnName)
2747	pszRdFnName = getMsrFnName(uMsr, NULL);
2748	if (!pszWrFnName)
2749	pszWrFnName = pszRdFnName;
2750	if (!pszCpumCpuStorage)
2751	pszCpumCpuStorage = getMsrCpumCpuVarName(uMsr);
2752	if (!pszCpumCpuStorage)
2753	return RTMsgErrorRc(VERR_NOT_FOUND, "Missing CPUMCPU member for %#s (%#x)\n", getMsrName(uMsr), uMsr);
2754	vbCpuRepPrintf(" MFZ(%#010x, \"%s\", %s, %s, %s", uMsr, getMsrName(uMsr), pszRdFnName, pszWrFnName, pszCpumCpuStorage);
2755	printMsrValueU64(fIgnMask);
2756	printMsrValueU64(fGpMask);
2757	vbCpuRepPrintf("),");
2758	if (pszAnnotation)
2759	vbCpuRepPrintf(" /* %s */", pszAnnotation);
2760	printMsrNewLine();
2761	return VINF_SUCCESS;
2762	}
2763
2764
2765	static int printMsrRangeFunction(uint32_t uMsr, uint32_t uLast, const char pszRdFnName, const char pszWrFnName,
2766	const char *pszAnnotation)
2767	{
2768	if (!pszRdFnName)
2769	pszRdFnName = getMsrFnName(uMsr, NULL);
2770	if (!pszWrFnName)
2771	pszWrFnName = pszRdFnName;
2772	vbCpuRepPrintf(" RFN(%#010x, %#010x, \"%s\", %s, %s),", uMsr, uLast, getMsrRangeName(uMsr), pszRdFnName, pszWrFnName);
2773	if (pszAnnotation)
2774	vbCpuRepPrintf(" /* %s */", pszAnnotation);
2775	printMsrNewLine();
2776	return VINF_SUCCESS;
2777	}
2778
2779
2780	static int printMsrRangeFunctionEx(uint32_t uMsr, uint32_t uLast, const char pszRdFnName, const char pszWrFnName,
2781	uint64_t uValue, uint64_t fIgnMask, uint64_t fGpMask, const char *pszAnnotation)
2782	{
2783	if (!pszRdFnName)
2784	pszRdFnName = getMsrFnName(uMsr, NULL);
2785	if (!pszWrFnName)
2786	pszWrFnName = pszRdFnName;
2787	vbCpuRepPrintf(" RSN(%#010x, %#010x, \"%s\", %s, %s", uMsr, uLast, getMsrRangeName(uMsr), pszRdFnName, pszWrFnName);
2788	printMsrValueU64(uValue);
2789	printMsrValueU64(fIgnMask);
2790	printMsrValueU64(fGpMask);
2791	vbCpuRepPrintf("),");
2792	if (pszAnnotation)
2793	vbCpuRepPrintf(" /* %s */", pszAnnotation);
2794	printMsrNewLine();
2795	return VINF_SUCCESS;
2796	}
2797
2798
2799	static int printMsrRangeFunctionExIdxVal(uint32_t uMsr, uint32_t uLast, const char pszRdFnName, const char pszWrFnName,
2800	uint64_t uValue, uint64_t fIgnMask, uint64_t fGpMask, const char *pszAnnotation)
2801	{
2802	if (!pszRdFnName)
2803	pszRdFnName = getMsrFnName(uMsr, NULL);
2804	if (!pszWrFnName)
2805	pszWrFnName = pszRdFnName;
2806	vbCpuRepPrintf(" RSN(%#010x, %#010x, \"%s\", %s, %s, %#x",
2807	uMsr, uLast, getMsrRangeName(uMsr), pszRdFnName, pszWrFnName, uValue);
2808	printMsrValueU64(fIgnMask);
2809	printMsrValueU64(fGpMask);
2810	vbCpuRepPrintf("),");
2811	if (pszAnnotation)
2812	vbCpuRepPrintf(" /* %s */", pszAnnotation);
2813	printMsrNewLine();
2814	return VINF_SUCCESS;
2815	}
2816
2817
2818	static int printMsrAlias(uint32_t uMsr, uint32_t uTarget, const char *pszAnnotation)
2819	{
2820	vbCpuRepPrintf(" MAL(%#010x, \"%s\", %#010x),", uMsr, getMsrName(uMsr), uTarget);
2821	if (pszAnnotation)
2822	vbCpuRepPrintf(" /* %s */", pszAnnotation);
2823	printMsrNewLine();
2824	return VINF_SUCCESS;
2825	}
2826
2827
2828
2829	static const char *annotateValue(uint64_t uValue)
2830	{
2831	static char s_szBuf[40];
2832	if (uValue <= UINT32_MAX)
2833	RTStrPrintf(s_szBuf, sizeof(s_szBuf), "value=%#llx", uValue);
2834	else
2835	RTStrPrintf(s_szBuf, sizeof(s_szBuf), "value=%#x`%08x", RT_HI_U32(uValue), RT_LO_U32(uValue));
2836	return s_szBuf;
2837	}
2838
2839
2840	static const char annotateValueExtra(const char pszExtra, uint64_t uValue)
2841	{
2842	static char s_szBuf[40];
2843	if (uValue <= UINT32_MAX)
2844	RTStrPrintf(s_szBuf, sizeof(s_szBuf), "%s value=%#llx", pszExtra, uValue);
2845	else
2846	RTStrPrintf(s_szBuf, sizeof(s_szBuf), "%s value=%#x`%08x", pszExtra, RT_HI_U32(uValue), RT_LO_U32(uValue));
2847	return s_szBuf;
2848	}
2849
2850
2851	static const char *annotateIfMissingBits(uint64_t uValue, uint64_t fBits)
2852	{
2853	static char s_szBuf[80];
2854	if ((uValue & fBits) == fBits)
2855	return annotateValue(uValue);
2856	RTStrPrintf(s_szBuf, sizeof(s_szBuf), "XXX: Unexpected value %#llx - wanted bits %#llx to be set.", uValue, fBits);
2857	return s_szBuf;
2858	}
2859
2860
2861	static int reportMsr_Generic(uint32_t uMsr, uint32_t fFlags, uint64_t uValue)
2862	{
2863	int rc;
2864	bool fTakesValue = false;
2865	const char *pszFnName = getMsrFnName(uMsr, &fTakesValue);
2866
2867	if (fFlags & VBCPUREPMSR_F_WRITE_ONLY)
2868	rc = printMsrWriteOnly(uMsr, pszFnName, NULL);
2869	else
2870	{
2871	bool fReadAsZero = doesMsrReadAsZero(uMsr);
2872	fTakesValue = fTakesValue && !fReadAsZero;
2873
2874
2875	switch (queryMsrWriteBadness(uMsr))
2876	{
2877	/* This is what we're here for... */
2878	case VBCPUREPBADNESS_MOSTLY_HARMLESS:
2879	{
2880	if ( msrProberModifyNoChange(uMsr)
2881	\|\| msrProberModifyZero(uMsr))
2882	{
2883	uint64_t fSkipMask = getGenericSkipMask(uMsr);
2884	uint64_t fIgnMask = 0;
2885	uint64_t fGpMask = 0;
2886	rc = msrProberModifyBitChanges(uMsr, &fIgnMask, &fGpMask, fSkipMask);
2887	if (RT_FAILURE(rc))
2888	return rc;
2889
2890	if (pszFnName)
2891	{
2892	if (fGpMask == 0 && fIgnMask == UINT64_MAX && !fTakesValue)
2893	rc = printMsrFunctionIgnoreWrites(uMsr, pszFnName, annotateValue(uValue));
2894	else if (fGpMask == 0 && fIgnMask == 0 && (!fTakesValue \|\| uValue == 0))
2895	rc = printMsrFunction(uMsr, pszFnName, pszFnName, annotateValue(uValue));
2896	else
2897	rc = printMsrFunctionExtended(uMsr, pszFnName, pszFnName, fTakesValue ? uValue : 0,
2898	fIgnMask, fGpMask, annotateValue(uValue));
2899	}
2900	else if (fGpMask == 0 && fIgnMask == UINT64_MAX)
2901	rc = printMsrValueIgnoreWrites(uMsr, fReadAsZero ? 0 : uValue, fReadAsZero ? annotateValue(uValue) : NULL);
2902	else
2903	rc = printMsrValueExtended(uMsr, fReadAsZero ? 0 : uValue, fIgnMask, fGpMask,
2904	fReadAsZero ? annotateValue(uValue) : NULL);
2905	}
2906	/* Most likely read-only. */
2907	else if (pszFnName && !fTakesValue)
2908	rc = printMsrFunctionReadOnly(uMsr, pszFnName, annotateValue(uValue));
2909	else if (pszFnName)
2910	rc = printMsrFunctionExtended(uMsr, pszFnName, "ReadOnly", uValue, 0, 0, annotateValue(uValue));
2911	else if (fReadAsZero)
2912	rc = printMsrValueReadOnly(uMsr, 0, annotateValue(uValue));
2913	else
2914	rc = printMsrValueReadOnly(uMsr, uValue, NULL);
2915	break;
2916	}
2917
2918	/* These should have special handling, so just do a simple
2919	write back same value check to see if it's writable. */
2920	case VBCPUREPBADNESS_MIGHT_BITE:
2921	if (msrProberModifyNoChange(uMsr))
2922	{
2923	if (pszFnName && !fTakesValue)
2924	rc = printMsrFunction(uMsr, pszFnName, pszFnName, annotateValueExtra("Might bite.", uValue));
2925	else if (pszFnName)
2926	rc = printMsrFunctionExtended(uMsr, pszFnName, pszFnName, uValue, 0, 0,
2927	annotateValueExtra("Might bite.", uValue));
2928	else if (fReadAsZero)
2929	rc = printMsrValueIgnoreWrites(uMsr, 0, annotateValueExtra("Might bite.", uValue));
2930	else
2931	rc = printMsrValueIgnoreWrites(uMsr, uValue, "Might bite.");
2932	}
2933	else if (pszFnName && !fTakesValue)
2934	rc = printMsrFunctionReadOnly(uMsr, pszFnName, annotateValueExtra("Might bite.", uValue));
2935	else if (pszFnName)
2936	rc = printMsrFunctionExtended(uMsr, pszFnName, "ReadOnly", uValue, 0, UINT64_MAX,
2937	annotateValueExtra("Might bite.", uValue));
2938	else if (fReadAsZero)
2939	rc = printMsrValueReadOnly(uMsr, 0, annotateValueExtra("Might bite.", uValue));
2940	else
2941	rc = printMsrValueReadOnly(uMsr, uValue, "Might bite.");
2942	break;
2943
2944
2945	/* Don't try anything with these guys. */
2946	case VBCPUREPBADNESS_BOND_VILLAIN:
2947	default:
2948	if (pszFnName && !fTakesValue)
2949	rc = printMsrFunction(uMsr, pszFnName, pszFnName, annotateValueExtra("Villain?", uValue));
2950	else if (pszFnName)
2951	rc = printMsrFunctionExtended(uMsr, pszFnName, pszFnName, uValue, 0, 0,
2952	annotateValueExtra("Villain?", uValue));
2953	else if (fReadAsZero)
2954	rc = printMsrValueIgnoreWrites(uMsr, 0, annotateValueExtra("Villain?", uValue));
2955	else
2956	rc = printMsrValueIgnoreWrites(uMsr, uValue, "Villain?");
2957	break;
2958	}
2959	}
2960
2961	return rc;
2962	}
2963
2964
2965	static int reportMsr_GenRangeFunctionEx(VBCPUREPMSR const paMsrs, uint32_t cMsrs, uint32_t cMax, const char pszRdWrFnName,
2966	uint32_t uMsrBase, bool fEarlyEndOk, bool fNoIgnMask, uint64_t fSkipMask, uint32_t *pidxLoop)
2967	{
2968	uint32_t uMsr = paMsrs[0].uMsr;
2969	uint32_t iRange = uMsr - uMsrBase;
2970	Assert(cMax > iRange);
2971	cMax -= iRange;
2972
2973	/* Resolve default function name. */
2974	if (!pszRdWrFnName)
2975	{
2976	pszRdWrFnName = getMsrFnName(uMsr, NULL);
2977	if (!pszRdWrFnName)
2978	return RTMsgErrorRc(VERR_INVALID_PARAMETER, "uMsr=%#x no function name\n", uMsr);
2979	}
2980
2981	/* Figure the possible register count. */
2982	if (cMax > cMsrs)
2983	cMax = cMsrs;
2984	uint32_t cRegs = 1;
2985	while ( cRegs < cMax
2986	&& paMsrs[cRegs].uMsr == uMsr + cRegs)
2987	cRegs++;
2988
2989	/* Probe the first register and check that the others exhibit
2990	the same characteristics. */
2991	bool fReadOnly0;
2992	uint64_t fIgnMask0, fGpMask0;
2993	int rc = msrProberModifyBasicTests(uMsr, fSkipMask, &fReadOnly0, &fIgnMask0, &fGpMask0);
2994	if (RT_FAILURE(rc))
2995	return rc;
2996
2997	const char *pszAnnotation = NULL;
2998	for (uint32_t i = 1; i < cRegs; i++)
2999	{
3000	bool fReadOnlyN;
3001	uint64_t fIgnMaskN, fGpMaskN;
3002	rc = msrProberModifyBasicTests(paMsrs[i].uMsr, fSkipMask, &fReadOnlyN, &fIgnMaskN, &fGpMaskN);
3003	if (RT_FAILURE(rc))
3004	return rc;
3005	if ( fReadOnlyN != fReadOnly0
3006	\|\| (fIgnMaskN != fIgnMask0 && !fNoIgnMask)
3007	\|\| fGpMaskN != fGpMask0)
3008	{
3009	if (!fEarlyEndOk && !isMsrViaDummy(uMsr, paMsrs[i].uValue, paMsrs[i].fFlags))
3010	{
3011	vbCpuRepDebug("MSR %s (%#x) range ended unexpectedly early on %#x: ro=%d ign=%#llx/%#llx gp=%#llx/%#llx [N/0]\n",
3012	getMsrNameHandled(uMsr), uMsr, paMsrs[i].uMsr,
3013	fReadOnlyN, fReadOnly0, fIgnMaskN, fIgnMask0, fGpMaskN, fGpMask0);
3014	pszAnnotation = "XXX: The range ended earlier than expected!";
3015	}
3016	cRegs = i;
3017	break;
3018	}
3019	}
3020
3021	/*
3022	* Report the range (or single MSR as it might be).
3023	*/
3024	*pidxLoop += cRegs - 1;
3025
3026	if (fNoIgnMask)
3027	fIgnMask0 = 0;
3028	bool fSimple = fIgnMask0 == 0
3029	&& (fGpMask0 == 0 \|\| (fGpMask0 == UINT64_MAX && fReadOnly0))
3030	&& iRange == 0;
3031	if (cRegs == 1)
3032	return printMsrFunctionExtendedIdxVal(uMsr, pszRdWrFnName, fReadOnly0 ? "ReadOnly" : pszRdWrFnName,
3033	iRange, fIgnMask0, fGpMask0,
3034	pszAnnotation ? pszAnnotation : annotateValue(paMsrs[0].uValue));
3035	if (fSimple)
3036	return printMsrRangeFunction(uMsr, uMsr + cRegs - 1,
3037	pszRdWrFnName, fReadOnly0 ? "ReadOnly" : pszRdWrFnName, pszAnnotation);
3038
3039	return printMsrRangeFunctionExIdxVal(uMsr, uMsr + cRegs - 1, pszRdWrFnName, fReadOnly0 ? "ReadOnly" : pszRdWrFnName,
3040	iRange /uValue/, fIgnMask0, fGpMask0, pszAnnotation);
3041	}
3042
3043
3044	static int reportMsr_GenRangeFunction(VBCPUREPMSR const paMsrs, uint32_t cMsrs, uint32_t cMax, const char pszRdWrFnName,
3045	uint32_t *pidxLoop)
3046	{
3047	return reportMsr_GenRangeFunctionEx(paMsrs, cMsrs, cMax, pszRdWrFnName, paMsrs[0].uMsr, false /fEarlyEndOk/, false /fNoIgnMask/,
3048	getGenericSkipMask(paMsrs[0].uMsr), pidxLoop);
3049	}
3050
3051
3052	/**
3053	* Generic report for an MSR implemented by functions, extended version.
3054	*
3055	* @returns VBox status code.
3056	* @param uMsr The MSR.
3057	* @param pszRdWrFnName The read/write function name, optional.
3058	* @param uValue The MSR range value.
3059	* @param fSkipMask Mask of bits to skip.
3060	* @param fNoGpMask Mask of bits to remove from the GP mask after
3061	* probing
3062	* @param pszAnnotate Annotation.
3063	*/
3064	static int reportMsr_GenFunctionEx(uint32_t uMsr, const char *pszRdWrFnName, uint32_t uValue,
3065	uint64_t fSkipMask, uint64_t fNoGpMask, const char *pszAnnotate)
3066	{
3067	/* Resolve default function name. */
3068	if (!pszRdWrFnName)
3069	{
3070	pszRdWrFnName = getMsrFnName(uMsr, NULL);
3071	if (!pszRdWrFnName)
3072	return RTMsgErrorRc(VERR_INVALID_PARAMETER, "uMsr=%#x no function name\n", uMsr);
3073	}
3074
3075	/* Probe the register and report. */
3076	uint64_t fIgnMask = 0;
3077	uint64_t fGpMask = 0;
3078	int rc = msrProberModifyBitChanges(uMsr, &fIgnMask, &fGpMask, fSkipMask);
3079	if (RT_SUCCESS(rc))
3080	{
3081	fGpMask &= ~fNoGpMask;
3082
3083	if (fGpMask == UINT64_MAX && uValue == 0 && !msrProberModifyZero(uMsr))
3084	rc = printMsrFunctionReadOnly(uMsr, pszRdWrFnName, pszAnnotate);
3085	else if (fIgnMask == UINT64_MAX && fGpMask == 0 && uValue == 0)
3086	rc = printMsrFunctionIgnoreWrites(uMsr, pszRdWrFnName, pszAnnotate);
3087	else if (fIgnMask != 0 && fGpMask == 0 && uValue == 0)
3088	rc = printMsrFunctionIgnoreMask(uMsr, pszRdWrFnName, NULL, fIgnMask, pszAnnotate);
3089	else if (fIgnMask == 0 && fGpMask == 0 && uValue == 0)
3090	rc = printMsrFunction(uMsr, pszRdWrFnName, NULL, pszAnnotate);
3091	else
3092	rc = printMsrFunctionExtended(uMsr, pszRdWrFnName, NULL, uValue, fIgnMask, fGpMask, pszAnnotate);
3093	}
3094	return rc;
3095	}
3096
3097
3098	/**
3099	* Reports a VIA dummy range.
3100	*
3101	* @returns VBox status code.
3102	* @param paMsrs Pointer to the first MSR.
3103	* @param cMsrs The number of MSRs in the array @a paMsr.
3104	* @param pidxLoop Index variable that should be advanced to the
3105	* last MSR entry in the range.
3106	*/
3107	static int reportMsr_ViaDummyRange(VBCPUREPMSR const paMsrs, uint32_t cMsrs, uint32_t pidxLoop)
3108	{
3109	/* Figure how many. */
3110	uint32_t uMsr = paMsrs[0].uMsr;
3111	uint32_t cRegs = 1;
3112	while ( cRegs < cMsrs
3113	&& paMsrs[cRegs].uMsr == uMsr + cRegs
3114	&& isMsrViaDummy(paMsrs[cRegs].uMsr, paMsrs[cRegs].uValue, paMsrs[cRegs].fFlags))
3115	{
3116	cRegs++;
3117	if (!(cRegs % 0x80))
3118	vbCpuRepDebug("VIA dummy detection %#llx..%#llx (%#x regs)...\n", uMsr, uMsr + cRegs - 1, cRegs);
3119	}
3120
3121	/* Advance. */
3122	*pidxLoop += cRegs - 1;
3123
3124	/* Report it/them. */
3125	char szName[80];
3126	if (cRegs == 1)
3127	{
3128	RTStrPrintf(szName, sizeof(szName), "ZERO_%04x_%04x", RT_HI_U16(uMsr), RT_LO_U16(uMsr));
3129	return printMsrValueIgnoreWritesNamed(uMsr, 0, szName, NULL);
3130	}
3131
3132	uint32_t uMsrLast = uMsr + cRegs - 1;
3133	RTStrPrintf(szName, sizeof(szName), "ZERO_%04x_%04x_THRU_%04x_%04x",
3134	RT_HI_U16(uMsr), RT_LO_U16(uMsr), RT_HI_U16(uMsrLast), RT_LO_U16(uMsrLast));
3135	return printMsrRangeValueIgnoreWritesNamed(uMsr, uMsrLast, 0, szName, NULL);
3136	}
3137
3138
3139	/**
3140	* Special function for reporting the IA32_APIC_BASE register, as it seems to be
3141	* causing trouble on newer systems.
3142	*
3143	* @returns
3144	* @param uMsr The MSR number.
3145	* @param uValue The value.
3146	*/
3147	static int reportMsr_Ia32ApicBase(uint32_t uMsr, uint64_t uValue)
3148	{
3149	/* Trouble with the generic treatment of both the "APIC Global Enable" and
3150	"Enable x2APIC mode" bits on an i7-3820QM running OS X 10.8.5. */
3151	uint64_t fSkipMask = RT_BIT_64(11);
3152	if (vbCpuRepSupportsX2Apic())
3153	fSkipMask \|= RT_BIT_64(10);
3154	return reportMsr_GenFunctionEx(uMsr, "Ia32ApicBase", uValue, fSkipMask, 0, NULL);
3155	}
3156
3157
3158	/**
3159	* Special function for reporting the IA32_MISC_ENABLE register, as it seems to
3160	* be causing trouble on newer systems.
3161	*
3162	* @returns
3163	* @param uMsr The MSR number.
3164	* @param uValue The value.
3165	*/
3166	static int reportMsr_Ia32MiscEnable(uint32_t uMsr, uint64_t uValue)
3167	{
3168	uint64_t fSkipMask = 0;
3169
3170	if ( ( g_enmMicroarch >= kCpumMicroarch_Intel_Core7_Broadwell
3171	&& g_enmMicroarch <= kCpumMicroarch_Intel_Core7_End)
3172	\|\| ( g_enmMicroarch >= kCpumMicroarch_Intel_Atom_Airmount
3173	&& g_enmMicroarch <= kCpumMicroarch_Intel_Atom_End)
3174	)
3175	{
3176	vbCpuRepPrintf("WARNING: IA32_MISC_ENABLE probing needs hacking on this CPU!\n");
3177	RTThreadSleep(128);
3178	}
3179
3180	/* The no execute related flag is deadly if clear. */
3181	if ( !(uValue & MSR_IA32_MISC_ENABLE_XD_DISABLE)
3182	&& ( g_enmMicroarch < kCpumMicroarch_Intel_First
3183	\|\| g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah
3184	\|\| vbCpuRepSupportsNX() ) )
3185	fSkipMask \|= MSR_IA32_MISC_ENABLE_XD_DISABLE;
3186
3187	uint64_t fIgnMask = 0;
3188	uint64_t fGpMask = 0;
3189	int rc = msrProberModifyBitChanges(uMsr, &fIgnMask, &fGpMask, fSkipMask);
3190	if (RT_SUCCESS(rc))
3191	rc = printMsrFunctionExtended(uMsr, "Ia32MiscEnable", "Ia32MiscEnable", uValue,
3192	fIgnMask, fGpMask, annotateValue(uValue));
3193	return rc;
3194	}
3195
3196
3197	/**
3198	* Verifies that MTRR type field works correctly in the given MSR.
3199	*
3200	* @returns VBox status code (failure if bad MSR behavior).
3201	* @param uMsr The MSR.
3202	* @param iBit The first bit of the type field (8-bit wide).
3203	* @param cExpected The number of types expected - PAT=8, MTRR=7.
3204	*/
3205	static int msrVerifyMtrrTypeGPs(uint32_t uMsr, uint32_t iBit, uint32_t cExpected)
3206	{
3207	uint32_t uEndTypes = 0;
3208	while (uEndTypes < 255)
3209	{
3210	bool fGp = !msrProberModifySimpleGp(uMsr, ~(UINT64_C(0xff) << iBit), (uint64_t)uEndTypes << iBit);
3211	if (!fGp && (uEndTypes == 2 \|\| uEndTypes == 3))
3212	return RTMsgErrorRc(VERR_INVALID_PARAMETER, "MTRR types %u does not cause a GP as it should. (msr %#x)\n",
3213	uEndTypes, uMsr);
3214	if (fGp && uEndTypes != 2 && uEndTypes != 3)
3215	break;
3216	uEndTypes++;
3217	}
3218	if (uEndTypes != cExpected)
3219	return RTMsgErrorRc(VERR_INVALID_PARAMETER, "MTRR types detected to be %#x (msr %#x). Expected %#x.\n",
3220	uEndTypes, uMsr, cExpected);
3221	return VINF_SUCCESS;
3222	}
3223
3224
3225	/**
3226	* Deals with the variable MTRR MSRs.
3227	*
3228	* @returns VBox status code.
3229	* @param paMsrs Pointer to the first variable MTRR MSR (200h).
3230	* @param cMsrs The number of MSRs in the array @a paMsr.
3231	* @param pidxLoop Index variable that should be advanced to the
3232	* last MTRR MSR entry.
3233	*/
3234	static int reportMsr_Ia32MtrrPhysBaseMaskN(VBCPUREPMSR const paMsrs, uint32_t cMsrs, uint32_t pidxLoop)
3235	{
3236	uint32_t uMsr = paMsrs[0].uMsr;
3237
3238	/* Count them. */
3239	uint32_t cRegs = 1;
3240	while ( cRegs < cMsrs
3241	&& paMsrs[cRegs].uMsr == uMsr + cRegs
3242	&& !isMsrViaDummy(paMsrs[cRegs].uMsr, paMsrs[cRegs].uValue, paMsrs[cRegs].fFlags) )
3243	cRegs++;
3244	if (cRegs & 1)
3245	return RTMsgErrorRc(VERR_INVALID_PARAMETER, "MTRR variable MSR range is odd: cRegs=%#x\n", cRegs);
3246	if (cRegs > 0x20)
3247	return RTMsgErrorRc(VERR_INVALID_PARAMETER, "MTRR variable MSR range is too large: cRegs=%#x\n", cRegs);
3248
3249	/* Find a disabled register that we can play around with. */
3250	uint32_t iGuineaPig;
3251	for (iGuineaPig = 0; iGuineaPig < cRegs; iGuineaPig += 2)
3252	if (!(paMsrs[iGuineaPig + 1].uValue & RT_BIT_32(11)))
3253	break;
3254	if (iGuineaPig >= cRegs)
3255	iGuineaPig = cRegs - 2;
3256	vbCpuRepDebug("iGuineaPig=%#x -> %#x\n", iGuineaPig, uMsr + iGuineaPig);
3257
3258	/* Probe the base. */
3259	uint64_t fIgnBase = 0;
3260	uint64_t fGpBase = 0;
3261	int rc = msrProberModifyBitChanges(uMsr + iGuineaPig, &fIgnBase, &fGpBase, 0);
3262	if (RT_FAILURE(rc))
3263	return rc;
3264	rc = msrVerifyMtrrTypeGPs(uMsr + iGuineaPig, 0, 7);
3265	if (RT_FAILURE(rc))
3266	return rc;
3267	vbCpuRepDebug("fIgnBase=%#llx fGpBase=%#llx\n", fIgnBase, fGpBase);
3268
3269	/* Probing the mask is relatively straight forward. */
3270	uint64_t fIgnMask = 0;
3271	uint64_t fGpMask = 0;
3272	rc = msrProberModifyBitChanges(uMsr + iGuineaPig + 1, &fIgnMask, &fGpMask, 0);
3273	if (RT_FAILURE(rc))
3274	return rc;
3275	vbCpuRepDebug("fIgnMask=%#llx fGpMask=%#llx\n", fIgnMask, fGpMask);
3276
3277	/* Validate that the whole range subscribes to the apprimately same GP rules. */
3278	for (uint32_t i = 0; i < cRegs; i += 2)
3279	{
3280	uint64_t fSkipBase = ~fGpBase;
3281	uint64_t fSkipMask = ~fGpMask;
3282	if (!(paMsrs[i + 1].uValue & RT_BIT_32(11)))
3283	fSkipBase = fSkipMask = 0;
3284	fSkipBase \|= 0x7; /* Always skip the type. */
3285	fSkipMask \|= RT_BIT_32(11); /* Always skip the enable bit. */
3286
3287	vbCpuRepDebug("i=%#x fSkipBase=%#llx fSkipMask=%#llx\n", i, fSkipBase, fSkipMask);
3288
3289	if (!(paMsrs[i + 1].uValue & RT_BIT_32(11)))
3290	{
3291	rc = msrVerifyMtrrTypeGPs(uMsr + iGuineaPig, 0, 7);
3292	if (RT_FAILURE(rc))
3293	return rc;
3294	}
3295
3296	uint64_t fIgnBaseN = 0;
3297	uint64_t fGpBaseN = 0;
3298	rc = msrProberModifyBitChanges(uMsr + i, &fIgnBaseN, &fGpBaseN, fSkipBase);
3299	if (RT_FAILURE(rc))
3300	return rc;
3301
3302	if ( fIgnBaseN != (fIgnBase & ~fSkipBase)
3303	\|\| fGpBaseN != (fGpBase & ~fSkipBase) )
3304	return RTMsgErrorRc(VERR_INVALID_PARAMETER,
3305	"MTRR PHYS BASE register %#x behaves differently from %#x: ign=%#llx/%#llx gp=%#llx/%#llx (fSkipBase=%#llx)\n",
3306	uMsr + i, uMsr + iGuineaPig,
3307	fIgnBaseN, fIgnBase & ~fSkipBase, fGpBaseN, fGpBase & ~fSkipBase, fSkipBase);
3308
3309	uint64_t fIgnMaskN = 0;
3310	uint64_t fGpMaskN = 0;
3311	rc = msrProberModifyBitChanges(uMsr + i + 1, &fIgnMaskN, &fGpMaskN, fSkipMask);
3312	if (RT_FAILURE(rc))
3313	return rc;
3314	if ( fIgnMaskN != (fIgnMask & ~fSkipMask)
3315	\|\| fGpMaskN != (fGpMask & ~fSkipMask) )
3316	return RTMsgErrorRc(VERR_INVALID_PARAMETER,
3317	"MTRR PHYS MASK register %#x behaves differently from %#x: ign=%#llx/%#llx gp=%#llx/%#llx (fSkipMask=%#llx)\n",
3318	uMsr + i + 1, uMsr + iGuineaPig + 1,
3319	fIgnMaskN, fIgnMask & ~fSkipMask, fGpMaskN, fGpMask & ~fSkipMask, fSkipMask);
3320	}
3321
3322	/* Print the whole range. */
3323	fGpBase &= ~(uint64_t)0x7; /* Valid type bits, see msrVerifyMtrrTypeGPs(). */
3324	for (uint32_t i = 0; i < cRegs; i += 2)
3325	{
3326	printMsrFunctionExtendedIdxVal(uMsr + i, "Ia32MtrrPhysBaseN", NULL, i / 2, fIgnBase, fGpBase,
3327	annotateValue(paMsrs[i].uValue));
3328	printMsrFunctionExtendedIdxVal(uMsr + i + 1, "Ia32MtrrPhysMaskN", NULL, i / 2, fIgnMask, fGpMask,
3329	annotateValue(paMsrs[i + 1].uValue));
3330	}
3331
3332	*pidxLoop += cRegs - 1;
3333	return VINF_SUCCESS;
3334	}
3335
3336
3337	/**
3338	* Deals with fixed MTRR and PAT MSRs, checking the 8 memory type fields.
3339	*
3340	* @returns VBox status code.
3341	* @param uMsr The MSR.
3342	*/
3343	static int reportMsr_Ia32MtrrFixedOrPat(uint32_t uMsr)
3344	{
3345	/* Had a spot of trouble on an old macbook pro with core2 duo T9900 (penryn)
3346	running 64-bit win81pe. Not giving PAT such a scrutiny fixes it. */
3347	if ( uMsr != 0x00000277
3348	\|\| g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First)
3349	{
3350	/* Every 8 bytes is a type, check the type ranges one by one. */
3351	for (uint32_t iBit = 0; iBit < 64; iBit += 8)
3352	{
3353	int rc = msrVerifyMtrrTypeGPs(uMsr, iBit, 7 + (uMsr == 0x00000277));
3354	if (RT_FAILURE(rc))
3355	return rc;
3356	}
3357	}
3358
3359	return printMsrFunctionCpumCpu(uMsr, NULL, NULL, NULL, NULL);
3360	}
3361
3362
3363	/**
3364	* Deals with IA32_MTRR_DEF_TYPE.
3365	*
3366	* @returns VBox status code.
3367	* @param uMsr The MSR.
3368	*/
3369	static int reportMsr_Ia32MtrrDefType(uint32_t uMsr)
3370	{
3371	int rc = msrVerifyMtrrTypeGPs(uMsr, 0, 7);
3372	if (RT_FAILURE(rc))
3373	return rc;
3374
3375	uint64_t fGpMask = 0;
3376	uint64_t fIgnMask = 0;
3377	rc = msrProberModifyBitChanges(uMsr, &fIgnMask, &fGpMask, 0x7);
3378	if (RT_FAILURE(rc))
3379	return rc;
3380	Assert(!(fGpMask & 7)); Assert(!(fIgnMask & 7));
3381
3382	return printMsrFunctionCpumCpuEx(uMsr, NULL, NULL, NULL, fIgnMask, fGpMask, NULL);
3383	}
3384
3385
3386	/**
3387	* Deals with the Machine Check (MC) MSRs in the 400h+ area.
3388	*
3389	* @returns VBox status code.
3390	* @param paMsrs Pointer to the first MC MSR (400h).
3391	* @param cMsrs The number of MSRs in the array @a paMsr.
3392	* @param pidxLoop Index variable that should be advanced to the
3393	* last MC MSR entry.
3394	*/
3395	static int reportMsr_Ia32McCtlStatusAddrMiscN(VBCPUREPMSR const paMsrs, uint32_t cMsrs, uint32_t pidxLoop)
3396	{
3397	uint32_t uMsr = paMsrs[0].uMsr;
3398
3399	/* Count them. */
3400	uint32_t cRegs = 1;
3401	uint32_t cDetectedRegs = 1;
3402	while ( cDetectedRegs < cMsrs
3403	&& ( paMsrs[cDetectedRegs].uMsr == uMsr + cRegs
3404	\|\| (cRegs & 3) == 2 /* ADDR may or may not be there, depends on STATUS and CPU. */
3405	\|\| (cRegs & 3) == 3 /* MISC may or may not be there, depends on STATUS and CPU. */)
3406	&& cRegs < 0x7f )
3407	{
3408	if (paMsrs[cDetectedRegs].uMsr == uMsr + cRegs)
3409	cDetectedRegs++;
3410	cRegs++;
3411	}
3412	if (cRegs & 3)
3413	return RTMsgErrorRc(VERR_INVALID_PARAMETER, "MC MSR range is odd: cRegs=%#x\n", cRegs);
3414
3415	/* Just report them. We don't bother probing here as the CTL format
3416	and such seems to be a lot of work to test correctly and changes between
3417	cpu generations. */
3418	*pidxLoop += cDetectedRegs - 1;
3419	return printMsrRangeFunction(uMsr, uMsr + cRegs - 1, "Ia32McCtlStatusAddrMiscN", NULL, NULL);
3420	}
3421
3422
3423
3424	/**
3425	* Deals with the X2APIC msrs.
3426	*
3427	* @returns VBox status code.
3428	* @param paMsrs Pointer to the first X2APIC MSR.
3429	* @param cMsrs The number of MSRs in the array @a paMsr.
3430	* @param pidxLoop Index variable that should be advanced to the
3431	* last X2APIC MSR entry.
3432	*/
3433	static int reportMsr_GenX2Apic(VBCPUREPMSR const paMsrs, uint32_t cMsrs, uint32_t pidxLoop)
3434	{
3435	/* Advance. */
3436	uint32_t cRegs = 1;
3437	while ( cRegs < cMsrs
3438	&& paMsrs[cRegs].uMsr <= 0x8ff)
3439	cRegs++;
3440	*pidxLoop += cRegs - 1;
3441
3442	/* Just emit an X2APIC range. */
3443	return printMsrRangeFunction(0x800, 0x8ff, "Ia32X2ApicN", NULL, NULL);
3444	}
3445
3446
3447	/**
3448	* Deals carefully with the EFER register.
3449	*
3450	* @returns VBox status code.
3451	* @param uMsr The MSR number.
3452	* @param uValue The current value.
3453	*/
3454	static int reportMsr_Amd64Efer(uint32_t uMsr, uint64_t uValue)
3455	{
3456	uint64_t fSkipMask = 0;
3457	if (vbCpuRepSupportsLongMode())
3458	fSkipMask \|= MSR_K6_EFER_LME;
3459	if ( (uValue & MSR_K6_EFER_NXE)
3460	\|\| vbCpuRepSupportsNX())
3461	fSkipMask \|= MSR_K6_EFER_NXE;
3462
3463	/* NetBurst prescott 2MB (model 4) hung or triple faulted here. The extra
3464	sleep or something seemed to help for some screwed up reason. */
3465	if (g_fIntelNetBurst)
3466	{
3467	// This doesn't matter:
3468	//fSkipMask \|= MSR_K6_EFER_SCE;
3469	//if (vbCpuRepSupportsLongMode())
3470	// fSkipMask \|= MSR_K6_EFER_LMA;
3471	//vbCpuRepDebug("EFER - netburst workaround - ignore SCE & LMA (fSkipMask=%#llx)\n", fSkipMask);
3472
3473	vbCpuRepDebug("EFER - netburst sleep fudge - fSkipMask=%#llx\n", fSkipMask);
3474	RTThreadSleep(1000);
3475	}
3476
3477	return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, MSR_K6_EFER_LMA, NULL);
3478	}
3479
3480
3481	/**
3482	* Deals with the MC4_MISCn (n >= 1) range and the following reserved MSRs.
3483	*
3484	* @returns VBox status code.
3485	* @param paMsrs Pointer to the first MSR.
3486	* @param cMsrs The number of MSRs in the array @a paMsr.
3487	* @param pidxLoop Index variable that should be advanced to the
3488	* last MSR entry in the range.
3489	*/
3490	static int reportMsr_AmdFam10hMc4MiscN(VBCPUREPMSR const paMsrs, uint32_t cMsrs, uint32_t pidxLoop)
3491	{
3492	/* Count registers. */
3493	uint32_t cRegs = 1;
3494	while ( cRegs < cMsrs
3495	&& cRegs < 8
3496	&& paMsrs[cRegs].uMsr == paMsrs[0].uMsr + cRegs)
3497	cRegs++;
3498
3499	/* Probe & report used MSRs. */
3500	uint64_t fIgnMask = 0;
3501	uint64_t fGpMask = 0;
3502	uint32_t cUsed = 0;
3503	while (cUsed < cRegs)
3504	{
3505	uint64_t fIgnMaskN = 0;
3506	uint64_t fGpMaskN = 0;
3507	int rc = msrProberModifyBitChanges(paMsrs[cUsed].uMsr, &fIgnMaskN, &fGpMaskN, 0);
3508	if (RT_FAILURE(rc))
3509	return rc;
3510	if (fIgnMaskN == UINT64_MAX \|\| fGpMaskN == UINT64_MAX)
3511	break;
3512	if (cUsed == 0)
3513	{
3514	fIgnMask = fIgnMaskN;
3515	fGpMask = fGpMaskN;
3516	}
3517	else if ( fIgnMaskN != fIgnMask
3518	\|\| fGpMaskN != fGpMask)
3519	return RTMsgErrorRc(VERR_NOT_EQUAL, "AmdFam16hMc4MiscN mismatch: fIgn=%#llx/%#llx fGp=%#llx/%#llx uMsr=%#x\n",
3520	fIgnMaskN, fIgnMask, fGpMaskN, fGpMask, paMsrs[cUsed].uMsr);
3521	cUsed++;
3522	}
3523	if (cUsed > 0)
3524	printMsrRangeFunctionEx(paMsrs[0].uMsr, paMsrs[cUsed - 1].uMsr, "AmdFam10hMc4MiscN", NULL, 0, fIgnMask, fGpMask, NULL);
3525
3526	/* Probe & report reserved MSRs. */
3527	uint32_t cReserved = 0;
3528	while (cUsed + cReserved < cRegs)
3529	{
3530	fIgnMask = fGpMask = 0;
3531	int rc = msrProberModifyBitChanges(paMsrs[cUsed + cReserved].uMsr, &fIgnMask, &fGpMask, 0);
3532	if (RT_FAILURE(rc))
3533	return rc;
3534	if ((fIgnMask != UINT64_MAX && fGpMask != UINT64_MAX) \|\| paMsrs[cUsed + cReserved].uValue)
3535	return RTMsgErrorRc(VERR_NOT_EQUAL,
3536	"Unexpected reserved AmdFam16hMc4MiscN: fIgn=%#llx fGp=%#llx uMsr=%#x uValue=%#llx\n",
3537	fIgnMask, fGpMask, paMsrs[cUsed + cReserved].uMsr, paMsrs[cUsed + cReserved].uValue);
3538	cReserved++;
3539	}
3540	if (cReserved > 0 && fIgnMask == UINT64_MAX)
3541	printMsrRangeValueIgnoreWrites(paMsrs[cUsed].uMsr, paMsrs[cUsed + cReserved - 1].uMsr, 0, NULL);
3542	else if (cReserved > 0 && fGpMask == UINT64_MAX)
3543	printMsrRangeValueReadOnly(paMsrs[cUsed].uMsr, paMsrs[cUsed + cReserved - 1].uMsr, 0, NULL);
3544
3545	*pidxLoop += cRegs - 1;
3546	return VINF_SUCCESS;
3547	}
3548
3549
3550	/**
3551	* Deals with the AMD PERF_CTL range.
3552	*
3553	* @returns VBox status code.
3554	* @param paMsrs Pointer to the first MSR.
3555	* @param cMsrs The number of MSRs in the array @a paMsr.
3556	* @param pidxLoop Index variable that should be advanced to the
3557	* last MSR entry in the range.
3558	*/
3559	static int reportMsr_AmdK8PerfCtlN(VBCPUREPMSR const paMsrs, uint32_t cMsrs, uint32_t pidxLoop)
3560	{
3561	uint32_t uMsr = paMsrs[0].uMsr;
3562	Assert(uMsr == 0xc0010000);
3563
3564	/* Family 15h (bulldozer +) aliases these registers sparsely onto c001020x. */
3565	if (CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch))
3566	{
3567	for (uint32_t i = 0; i < 4; i++)
3568	printMsrAlias(uMsr + i, 0xc0010200 + i * 2, NULL);
3569	*pidxLoop += 3;
3570	}
3571	else
3572	return reportMsr_GenRangeFunction(paMsrs, cMsrs, 4, "AmdK8PerfCtlN", pidxLoop);
3573	return VINF_SUCCESS;
3574	}
3575
3576
3577	/**
3578	* Deals with the AMD PERF_CTR range.
3579	*
3580	* @returns VBox status code.
3581	* @param paMsrs Pointer to the first MSR.
3582	* @param cMsrs The number of MSRs in the array @a paMsr.
3583	* @param pidxLoop Index variable that should be advanced to the
3584	* last MSR entry in the range.
3585	*/
3586	static int reportMsr_AmdK8PerfCtrN(VBCPUREPMSR const paMsrs, uint32_t cMsrs, uint32_t pidxLoop)
3587	{
3588	uint32_t uMsr = paMsrs[0].uMsr;
3589	Assert(uMsr == 0xc0010004);
3590
3591	/* Family 15h (bulldozer +) aliases these registers sparsely onto c001020x. */
3592	if (CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch))
3593	{
3594	for (uint32_t i = 0; i < 4; i++)
3595	printMsrAlias(uMsr + i, 0xc0010201 + i * 2, NULL);
3596	*pidxLoop += 3;
3597	}
3598	else
3599	return reportMsr_GenRangeFunction(paMsrs, cMsrs, 4, "AmdK8PerfCtrN", pidxLoop);
3600	return VINF_SUCCESS;
3601	}
3602
3603
3604	/**
3605	* Deals carefully with the SYS_CFG register.
3606	*
3607	* @returns VBox status code.
3608	* @param uMsr The MSR number.
3609	* @param uValue The current value.
3610	*/
3611	static int reportMsr_AmdK8SysCfg(uint32_t uMsr, uint64_t uValue)
3612	{
3613	uint64_t fSkipMask = 0;
3614
3615	/* Bit 21 (MtrrTom2En) is marked reserved in family 0fh, while in family
3616	10h BKDG this changes (as does the document style). Testing this bit
3617	causes bulldozer running win64 to restart, thus this special treatment. */
3618	if (g_enmMicroarch >= kCpumMicroarch_AMD_K10)
3619	fSkipMask \|= RT_BIT(21);
3620
3621	/* Turns out there are more killer bits here, at least on Opteron 2384.
3622	Skipping all known bits. */
3623	if (g_enmMicroarch >= kCpumMicroarch_AMD_K8_65nm /* Not sure when introduced - harmless? */)
3624	fSkipMask \|= RT_BIT(22); /* Tom2ForceMemTypeWB */
3625	if (g_enmMicroarch >= kCpumMicroarch_AMD_K8_First)
3626	fSkipMask \|= RT_BIT(21); /* MtrrTom2En */
3627	if (g_enmMicroarch >= kCpumMicroarch_AMD_K8_First)
3628	fSkipMask \|= RT_BIT(20); /* MtrrVarDramEn*/
3629	if (g_enmMicroarch >= kCpumMicroarch_AMD_K8_First)
3630	fSkipMask \|= RT_BIT(19); /* MtrrFixDramModEn */
3631	if (g_enmMicroarch >= kCpumMicroarch_AMD_K8_First)
3632	fSkipMask \|= RT_BIT(18); /* MtrrFixDramEn */
3633	if (g_enmMicroarch >= kCpumMicroarch_AMD_K8_First)
3634	fSkipMask \|= RT_BIT(17); /* SysUcLockEn */
3635	if (g_enmMicroarch >= kCpumMicroarch_AMD_K8_First)
3636	fSkipMask \|= RT_BIT(16); /* ChgToDirtyDis */
3637	if (g_enmMicroarch >= kCpumMicroarch_AMD_K8_First && g_enmMicroarch < kCpumMicroarch_AMD_15h_First)
3638	fSkipMask \|= RT_BIT(10); /* SetDirtyEnO */
3639	if (g_enmMicroarch >= kCpumMicroarch_AMD_K8_First && g_enmMicroarch < kCpumMicroarch_AMD_15h_First)
3640	fSkipMask \|= RT_BIT(9); /* SetDirtyEnS */
3641	if ( CPUMMICROARCH_IS_AMD_FAM_0FH(g_enmMicroarch)
3642	\|\| CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch))
3643	fSkipMask \|= RT_BIT(8); /* SetDirtyEnE */
3644	if ( CPUMMICROARCH_IS_AMD_FAM_0FH(g_enmMicroarch)
3645	\|\| CPUMMICROARCH_IS_AMD_FAM_11H(g_enmMicroarch) )
3646	fSkipMask \|= RT_BIT(7) /* SysVicLimit */
3647	\| RT_BIT(6) /* SysVicLimit */
3648	\| RT_BIT(5) /* SysVicLimit */
3649	\| RT_BIT(4) /* SysAckLimit */
3650	\| RT_BIT(3) /* SysAckLimit */
3651	\| RT_BIT(2) /* SysAckLimit */
3652	\| RT_BIT(1) /* SysAckLimit */
3653	\| RT_BIT(0) /* SysAckLimit */;
3654
3655	return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, 0, annotateValue(uValue));
3656	}
3657
3658
3659	/**
3660	* Deals carefully with the HWCR register.
3661	*
3662	* @returns VBox status code.
3663	* @param uMsr The MSR number.
3664	* @param uValue The current value.
3665	*/
3666	static int reportMsr_AmdK8HwCr(uint32_t uMsr, uint64_t uValue)
3667	{
3668	uint64_t fSkipMask = 0;
3669
3670	/* Trouble on Opteron 2384, skip some of the known bits. */
3671	if (g_enmMicroarch >= kCpumMicroarch_AMD_K10 && !CPUMMICROARCH_IS_AMD_FAM_11H(g_enmMicroarch))
3672	fSkipMask \|= /RT_BIT(10)/ 0 /* MonMwaitUserEn */
3673	\| RT_BIT(9); /* MonMwaitDis */
3674	fSkipMask \|= RT_BIT(8); /* #IGNNE port emulation */
3675	if ( CPUMMICROARCH_IS_AMD_FAM_0FH(g_enmMicroarch)
3676	\|\| CPUMMICROARCH_IS_AMD_FAM_11H(g_enmMicroarch) )
3677	fSkipMask \|= RT_BIT(7) /* DisLock */
3678	\| RT_BIT(6); /* FFDis (TLB flush filter) */
3679	fSkipMask \|= RT_BIT(4); /* INVD to WBINVD */
3680	fSkipMask \|= RT_BIT(3); /* TLBCACHEDIS */
3681	if ( CPUMMICROARCH_IS_AMD_FAM_0FH(g_enmMicroarch)
3682	\|\| CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch)
3683	\|\| CPUMMICROARCH_IS_AMD_FAM_11H(g_enmMicroarch) )
3684	fSkipMask \|= RT_BIT(1); /* SLOWFENCE */
3685	fSkipMask \|= RT_BIT(0); /* SMMLOCK */
3686
3687	return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, 0, annotateValue(uValue));
3688	}
3689
3690
3691	/**
3692	* Deals carefully with a IORRBasei register.
3693	*
3694	* @returns VBox status code.
3695	* @param uMsr The MSR number.
3696	* @param uValue The current value.
3697	*/
3698	static int reportMsr_AmdK8IorrBaseN(uint32_t uMsr, uint64_t uValue)
3699	{
3700	/* Skip know bits here, as harm seems to come from messing with them. */
3701	uint64_t fSkipMask = RT_BIT(4) \| RT_BIT(3);
3702	fSkipMask \|= (RT_BIT_64(vbCpuRepGetPhysAddrWidth()) - 1) & X86_PAGE_4K_BASE_MASK;
3703	return reportMsr_GenFunctionEx(uMsr, NULL, (uMsr - 0xc0010016) / 2, fSkipMask, 0, annotateValue(uValue));
3704	}
3705
3706
3707	/**
3708	* Deals carefully with a IORRMaski register.
3709	*
3710	* @returns VBox status code.
3711	* @param uMsr The MSR number.
3712	* @param uValue The current value.
3713	*/
3714	static int reportMsr_AmdK8IorrMaskN(uint32_t uMsr, uint64_t uValue)
3715	{
3716	/* Skip know bits here, as harm seems to come from messing with them. */
3717	uint64_t fSkipMask = RT_BIT(11);
3718	fSkipMask \|= (RT_BIT_64(vbCpuRepGetPhysAddrWidth()) - 1) & X86_PAGE_4K_BASE_MASK;
3719	return reportMsr_GenFunctionEx(uMsr, NULL, (uMsr - 0xc0010017) / 2, fSkipMask, 0, annotateValue(uValue));
3720	}
3721
3722
3723	/**
3724	* Deals carefully with a IORRMaski register.
3725	*
3726	* @returns VBox status code.
3727	* @param uMsr The MSR number.
3728	* @param uValue The current value.
3729	*/
3730	static int reportMsr_AmdK8TopMemN(uint32_t uMsr, uint64_t uValue)
3731	{
3732	/* Skip know bits here, as harm seems to come from messing with them. */
3733	uint64_t fSkipMask = (RT_BIT_64(vbCpuRepGetPhysAddrWidth()) - 1) & ~(RT_BIT_64(23) - 1);
3734	return reportMsr_GenFunctionEx(uMsr, NULL, uMsr == 0xc001001d, fSkipMask, 0, annotateValue(uValue));
3735	}
3736
3737
3738	/**
3739	* Deals with the AMD P-state config range.
3740	*
3741	* @returns VBox status code.
3742	* @param paMsrs Pointer to the first MSR.
3743	* @param cMsrs The number of MSRs in the array @a paMsr.
3744	* @param pidxLoop Index variable that should be advanced to the
3745	* last MSR entry in the range.
3746	*/
3747	static int reportMsr_AmdFam10hPStateN(VBCPUREPMSR const paMsrs, uint32_t cMsrs, uint32_t pidxLoop)
3748	{
3749	uint32_t uMsr = paMsrs[0].uMsr;
3750	AssertRelease(uMsr == 0xc0010064);
3751
3752	/* Count them. */
3753	uint32_t cRegs = 1;
3754	while ( cRegs < 8
3755	&& cRegs < cMsrs
3756	&& paMsrs[cRegs].uMsr == uMsr + cRegs)
3757	cRegs++;
3758
3759	/* Figure out which bits we should skip when probing. This is based on
3760	specs and may need adjusting for real life when handy. */
3761	uint64_t fSkipMask = RT_BIT_64(63); /* PstateEn */
3762	fSkipMask \|= RT_BIT_64(41) \| RT_BIT_64(40); /* IddDiv */
3763	fSkipMask \|= UINT64_C(0x000000ff00000000); /* IddValue */
3764	if (CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch))
3765	fSkipMask \|= UINT32_C(0xfe000000); /* NbVid - Northbridge VID */
3766	if ( CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch)
3767	\|\| CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch))
3768	fSkipMask \|= RT_BIT_32(22); /* NbDid or NbPstate. */
3769	if (g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver) /* ?? - listed in 10-1Fh model BDKG as well asFam16h */
3770	fSkipMask \|= RT_BIT_32(16); /* CpuVid[7] */
3771	fSkipMask \|= UINT32_C(0x0000fe00); /* CpuVid[6:0] */
3772	fSkipMask \|= UINT32_C(0x000001c0); /* CpuDid */
3773	fSkipMask \|= UINT32_C(0x0000003f); /* CpuFid */
3774
3775	/* Probe and report them one by one since we're passing values instead of
3776	register indexes to the functions. */
3777	for (uint32_t i = 0; i < cRegs; i++)
3778	{
3779	uint64_t fIgnMask = 0;
3780	uint64_t fGpMask = 0;
3781	int rc = msrProberModifyBitChanges(uMsr + i, &fIgnMask, &fGpMask, fSkipMask);
3782	if (RT_FAILURE(rc))
3783	return rc;
3784	printMsrFunctionExtended(uMsr + i, "AmdFam10hPStateN", NULL, paMsrs[i].uValue, fIgnMask, fGpMask,
3785	annotateValue(paMsrs[i].uValue));
3786	}
3787
3788	/* Advance. */
3789	*pidxLoop += cRegs - 1;
3790	return VINF_SUCCESS;
3791	}
3792
3793
3794	/**
3795	* Deals carefully with a COFVID control register.
3796	*
3797	* @returns VBox status code.
3798	* @param uMsr The MSR number.
3799	* @param uValue The current value.
3800	*/
3801	static int reportMsr_AmdFam10hCofVidControl(uint32_t uMsr, uint64_t uValue)
3802	{
3803	/* Skip know bits here, as harm seems to come from messing with them. */
3804	uint64_t fSkipMask = 0;
3805	if (CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch))
3806	fSkipMask \|= UINT32_C(0xfe000000); /* NbVid - Northbridge VID */
3807	else if (g_enmMicroarch >= kCpumMicroarch_AMD_15h_First) /* Listed in preliminary Fam16h BDKG. */
3808	fSkipMask \|= UINT32_C(0xff000000); /* NbVid - Northbridge VID - includes bit 24 for Fam15h and Fam16h. Odd... */
3809	if ( CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch)
3810	\|\| g_enmMicroarch >= kCpumMicroarch_AMD_15h_First) /* Listed in preliminary Fam16h BDKG. */
3811	fSkipMask \|= RT_BIT_32(22); /* NbDid or NbPstate. */
3812	if (g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver) /* ?? - listed in 10-1Fh model BDKG as well asFam16h */
3813	fSkipMask \|= RT_BIT_32(20); /* CpuVid[7] */
3814	fSkipMask \|= UINT32_C(0x00070000); /* PstatId */
3815	fSkipMask \|= UINT32_C(0x0000fe00); /* CpuVid[6:0] */
3816	fSkipMask \|= UINT32_C(0x000001c0); /* CpuDid */
3817	fSkipMask \|= UINT32_C(0x0000003f); /* CpuFid */
3818
3819	return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, 0, annotateValue(uValue));
3820	}
3821
3822
3823	/**
3824	* Deals with the AMD [\|L2I_\|NB_]PERF_CT[LR] mixed ranges.
3825	*
3826	* Mixed here refers to the control and counter being in mixed in pairs as
3827	* opposed to them being two separate parallel arrays like in the 0xc0010000
3828	* area.
3829	*
3830	* @returns VBox status code.
3831	* @param paMsrs Pointer to the first MSR.
3832	* @param cMsrs The number of MSRs in the array @a paMsr.
3833	* @param cMax The max number of MSRs (not counters).
3834	* @param pidxLoop Index variable that should be advanced to the
3835	* last MSR entry in the range.
3836	*/
3837	static int reportMsr_AmdGenPerfMixedRange(VBCPUREPMSR const paMsrs, uint32_t cMsrs, uint32_t cMax, uint32_t pidxLoop)
3838	{
3839	uint32_t uMsr = paMsrs[0].uMsr;
3840
3841	/* Count them. */
3842	uint32_t cRegs = 1;
3843	while ( cRegs < cMax
3844	&& cRegs < cMsrs
3845	&& paMsrs[cRegs].uMsr == uMsr + cRegs)
3846	cRegs++;
3847	if (cRegs & 1)
3848	return RTMsgErrorRc(VERR_INVALID_PARAMETER, "PERF range at %#x is odd: cRegs=%#x\n", uMsr, cRegs);
3849
3850	/* Report them as individual entries, using default names and such. */
3851	for (uint32_t i = 0; i < cRegs; i++)
3852	{
3853	uint64_t fIgnMask = 0;
3854	uint64_t fGpMask = 0;
3855	int rc = msrProberModifyBitChanges(uMsr + i, &fIgnMask, &fGpMask, 0);
3856	if (RT_FAILURE(rc))
3857	return rc;
3858	printMsrFunctionExtendedIdxVal(uMsr + i, NULL, NULL, i / 2, fIgnMask, fGpMask, annotateValue(paMsrs[i].uValue));
3859	}
3860
3861	/* Advance. */
3862	*pidxLoop += cRegs - 1;
3863	return VINF_SUCCESS;
3864	}
3865
3866
3867	/**
3868	* Deals carefully with a LS_CFG register.
3869	*
3870	* @returns VBox status code.
3871	* @param uMsr The MSR number.
3872	* @param uValue The current value.
3873	*/
3874	static int reportMsr_AmdK7InstrCacheCfg(uint32_t uMsr, uint64_t uValue)
3875	{
3876	/* Skip know bits here, as harm seems to come from messing with them. */
3877	uint64_t fSkipMask = RT_BIT_64(9) /* DIS_SPEC_TLB_RLD */;
3878	if (CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch))
3879	fSkipMask \|= RT_BIT_64(14); /* DIS_IND */
3880	if (CPUMMICROARCH_IS_AMD_FAM_16H(g_enmMicroarch))
3881	fSkipMask \|= RT_BIT_64(26); /* DIS_WIDEREAD_PWR_SAVE */
3882	if (CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch))
3883	{
3884	fSkipMask \|= 0x1e; /* DisIcWayFilter */
3885	fSkipMask \|= RT_BIT_64(39); /* DisLoopPredictor */
3886	fSkipMask \|= RT_BIT_64(27); /* Unknown killer bit, possibly applicable to other microarchs. */
3887	fSkipMask \|= RT_BIT_64(28); /* Unknown killer bit, possibly applicable to other microarchs. */
3888	}
3889	return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, 0, annotateValue(uValue));
3890	}
3891
3892
3893	/**
3894	* Deals carefully with a CU_CFG register.
3895	*
3896	* @returns VBox status code.
3897	* @param uMsr The MSR number.
3898	* @param uValue The current value.
3899	*/
3900	static int reportMsr_AmdFam15hCombUnitCfg(uint32_t uMsr, uint64_t uValue)
3901	{
3902	/* Skip know bits here, as harm seems to come from messing with them. */
3903	uint64_t fSkipMask = RT_BIT_64(23) /* L2WayLock */
3904	\| RT_BIT_64(22) /* L2FirstLockWay */
3905	\| RT_BIT_64(21) /* L2FirstLockWay */
3906	\| RT_BIT_64(20) /* L2FirstLockWay */
3907	\| RT_BIT_64(19) /* L2FirstLockWay */
3908	\| RT_BIT_64(10) /* DcacheAggressivePriority */;
3909	fSkipMask \|= RT_BIT_64(46) \| RT_BIT_64(45); /* Killer field. Seen bit 46 set, 45 clear. Messing with either means reboot/BSOD. */
3910	return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, 0, annotateValue(uValue));
3911	}
3912
3913
3914	/**
3915	* Deals carefully with a EX_CFG register.
3916	*
3917	* @returns VBox status code.
3918	* @param uMsr The MSR number.
3919	* @param uValue The current value.
3920	*/
3921	static int reportMsr_AmdFam15hExecUnitCfg(uint32_t uMsr, uint64_t uValue)
3922	{
3923	/* Skip know bits here, as harm seems to come from messing with them. */
3924	uint64_t fSkipMask = RT_BIT_64(54) /* LateSbzResync */;
3925	fSkipMask \|= RT_BIT_64(35); /* Undocumented killer bit. */
3926	return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, 0, annotateValue(uValue));
3927	}
3928
3929
3930
3931	static int produceMsrReport(VBCPUREPMSR *paMsrs, uint32_t cMsrs)
3932	{
3933	vbCpuRepDebug("produceMsrReport\n");
3934	RTThreadSleep(500);
3935
3936	for (uint32_t i = 0; i < cMsrs; i++)
3937	{
3938	uint32_t uMsr = paMsrs[i].uMsr;
3939	uint32_t fFlags = paMsrs[i].fFlags;
3940	uint64_t uValue = paMsrs[i].uValue;
3941	int rc;
3942	#if 0
3943	if (uMsr < 0x00003170)
3944	continue;
3945	if (uMsr >= 0x00003170)
3946	{
3947	vbCpuRepDebug("produceMsrReport: uMsr=%#x (%s)...\n", uMsr, getMsrNameHandled(uMsr));
3948	RTThreadSleep(1000);
3949	}
3950	#endif
3951	/*
3952	* Deal with write only regs first to avoid having to avoid them all the time.
3953	*/
3954	if (fFlags & VBCPUREPMSR_F_WRITE_ONLY)
3955	{
3956	if (uMsr == 0x00000079)
3957	rc = printMsrWriteOnly(uMsr, NULL, NULL);
3958	else
3959	rc = reportMsr_Generic(uMsr, fFlags, uValue);
3960	}
3961	/*
3962	* VIA implement MSRs in a interesting way, so we have to select what we
3963	* want to handle there to avoid making the code below unreadable.
3964	*/
3965	else if (isMsrViaDummy(uMsr, uValue, fFlags))
3966	rc = reportMsr_ViaDummyRange(&paMsrs[i], cMsrs - i, &i);
3967	/*
3968	* This shall be sorted by uMsr as much as possible.
3969	*/
3970	else if (uMsr == 0x00000000 && g_enmVendor == CPUMCPUVENDOR_AMD && g_enmMicroarch >= kCpumMicroarch_AMD_K8_First)
3971	rc = printMsrAlias(uMsr, 0x00000402, NULL);
3972	else if (uMsr == 0x00000001 && g_enmVendor == CPUMCPUVENDOR_AMD && g_enmMicroarch >= kCpumMicroarch_AMD_K8_First)
3973	rc = printMsrAlias(uMsr, 0x00000401, NULL); /** @todo not 101% correct on Fam15h and later, 0xc0010015[McstatusWrEn] effect differs. */
3974	else if (uMsr == 0x0000001b)
3975	rc = reportMsr_Ia32ApicBase(uMsr, uValue);
3976	else if (uMsr == 0x00000040 && g_enmMicroarch <= kCpumMicroarch_Intel_P6_M_Dothan)
3977	rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, 8 /cMax/, "IntelLastBranchFromToN", &i);
3978	else if (uMsr == 0x00000040)
3979	rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 8 /cMax/, "IntelLastBranchToN", uMsr, false,
3980	true, getGenericSkipMask(uMsr), &i);
3981	else if (uMsr == 0x00000060 && g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah)
3982	rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 8 /cMax/, "IntelLastBranchFromN", uMsr, false,
3983	true, getGenericSkipMask(uMsr), &i);
3984	else if (uMsr == 0x000000c1)
3985	rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i,
3986	g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First ? 8 : 4 /cMax/,
3987	NULL, &i);
3988	else if (uMsr == 0x00000186 && !g_fIntelNetBurst)
3989	rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, 8 /cMax/, "Ia32PerfEvtSelN", &i);
3990	else if (uMsr == 0x000001a0)
3991	rc = reportMsr_Ia32MiscEnable(uMsr, uValue);
3992	else if (uMsr >= 0x000001a6 && uMsr <= 0x000001a7)
3993	rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, 2 /cMax/, "IntelI7MsrOffCoreResponseN", &i);
3994	else if (uMsr == 0x000001db && g_fIntelNetBurst)
3995	rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, 4 /cMax/, "IntelLastBranchFromToN", &i);
3996	else if (uMsr == 0x00000200)
3997	rc = reportMsr_Ia32MtrrPhysBaseMaskN(&paMsrs[i], cMsrs - i, &i);
3998	else if (uMsr >= 0x00000250 && uMsr <= 0x00000279)
3999	rc = reportMsr_Ia32MtrrFixedOrPat(uMsr);
4000	else if (uMsr >= 0x00000280 && uMsr <= 0x00000295)
4001	rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 22 /cMax/, NULL, 0x00000280, true /fEarlyEndOk/, false, 0, &i);
4002	else if (uMsr == 0x000002ff)
4003	rc = reportMsr_Ia32MtrrDefType(uMsr);
4004	else if (uMsr >= 0x00000309 && uMsr <= 0x0000030b && !g_fIntelNetBurst)
4005	rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 3 /cMax/, NULL, 0x00000309, true /fEarlyEndOk/, false, 0, &i);
4006	else if ((uMsr == 0x000003f8 \|\| uMsr == 0x000003fc \|\| uMsr == 0x0000060a) && !g_fIntelNetBurst)
4007	rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 4, NULL, uMsr - 3, true, false, 0, &i);
4008	else if ((uMsr == 0x000003f9 \|\| uMsr == 0x000003fd \|\| uMsr == 0x0000060b) && !g_fIntelNetBurst)
4009	rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 8, NULL, uMsr - 6, true, false, 0, &i);
4010	else if ((uMsr == 0x000003fa \|\| uMsr == 0x000003fe \|\| uMsr == 0x0000060c) && !g_fIntelNetBurst)
4011	rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 8, NULL, uMsr - 7, true, false, 0, &i);
4012	else if (uMsr >= 0x00000400 && uMsr <= 0x00000477)
4013	rc = reportMsr_Ia32McCtlStatusAddrMiscN(&paMsrs[i], cMsrs - i, &i);
4014	else if (uMsr == 0x000004c1)
4015	rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, 8, NULL, &i);
4016	else if (uMsr == 0x00000680 \|\| uMsr == 0x000006c0)
4017	rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 16, NULL, uMsr, false, false,
4018	g_fIntelNetBurst
4019	? UINT64_C(0xffffffffffffff00) /* kludge */
4020	: UINT64_C(0xffff800000000000), &i);
4021	else if (uMsr >= 0x00000800 && uMsr <= 0x000008ff)
4022	rc = reportMsr_GenX2Apic(&paMsrs[i], cMsrs - i, &i);
4023	else if (uMsr == 0x00002000 && g_enmVendor == CPUMCPUVENDOR_INTEL)
4024	rc = reportMsr_GenFunctionEx(uMsr, "IntelP6CrN", 0, X86_CR0_PE \| X86_CR0_PG, 0,
4025	annotateIfMissingBits(uValue, X86_CR0_PE \| X86_CR0_PE \| X86_CR0_ET));
4026	else if (uMsr == 0x00002002 && g_enmVendor == CPUMCPUVENDOR_INTEL)
4027	rc = reportMsr_GenFunctionEx(uMsr, "IntelP6CrN", 2, 0, 0, annotateValue(uValue));
4028	else if (uMsr == 0x00002003 && g_enmVendor == CPUMCPUVENDOR_INTEL)
4029	{
4030	uint64_t fCr3Mask = (RT_BIT_64(vbCpuRepGetPhysAddrWidth()) - 1) & (X86_CR3_PAE_PAGE_MASK \| X86_CR3_AMD64_PAGE_MASK);
4031	if (!vbCpuRepSupportsPae())
4032	fCr3Mask &= X86_CR3_PAGE_MASK \| X86_CR3_AMD64_PAGE_MASK;
4033	rc = reportMsr_GenFunctionEx(uMsr, "IntelP6CrN", 3, fCr3Mask, 0, annotateValue(uValue));
4034	}
4035	else if (uMsr == 0x00002004 && g_enmVendor == CPUMCPUVENDOR_INTEL)
4036	rc = reportMsr_GenFunctionEx(uMsr, "IntelP6CrN", 4,
4037	X86_CR4_PSE \| X86_CR4_PAE \| X86_CR4_MCE \| X86_CR4_SMXE, 0,
4038	annotateValue(uValue));
4039	else if (uMsr == 0xc0000080)
4040	rc = reportMsr_Amd64Efer(uMsr, uValue);
4041	else if (uMsr == 0xc0000082 \|\| uMsr == 0xc0000083 \|\| uMsr == 0xc0000100 \|\| uMsr == 0xc0000101 \|\| uMsr == 0xc0000102)
4042	rc = reportMsr_GenFunctionEx(uMsr, NULL, 0, UINT64_C(0xffff800000000000), 0, annotateValue(uValue)); /* Canoncial address hack. */
4043	else if (uMsr >= 0xc0000408 && uMsr <= 0xc000040f)
4044	rc = reportMsr_AmdFam10hMc4MiscN(&paMsrs[i], cMsrs - i, &i);
4045	else if (uMsr == 0xc0010000 && g_enmVendor == CPUMCPUVENDOR_AMD)
4046	rc = reportMsr_AmdK8PerfCtlN(&paMsrs[i], cMsrs - i, &i);
4047	else if (uMsr == 0xc0010004 && g_enmVendor == CPUMCPUVENDOR_AMD)
4048	rc = reportMsr_AmdK8PerfCtrN(&paMsrs[i], cMsrs - i, &i);
4049	else if (uMsr == 0xc0010010 && g_enmVendor == CPUMCPUVENDOR_AMD)
4050	rc = reportMsr_AmdK8SysCfg(uMsr, uValue);
4051	else if (uMsr == 0xc0010015 && g_enmVendor == CPUMCPUVENDOR_AMD)
4052	rc = reportMsr_AmdK8HwCr(uMsr, uValue);
4053	else if ((uMsr == 0xc0010016 \|\| uMsr == 0xc0010018) && g_enmVendor == CPUMCPUVENDOR_AMD)
4054	rc = reportMsr_AmdK8IorrBaseN(uMsr, uValue);
4055	else if ((uMsr == 0xc0010017 \|\| uMsr == 0xc0010019) && g_enmVendor == CPUMCPUVENDOR_AMD)
4056	rc = reportMsr_AmdK8IorrMaskN(uMsr, uValue);
4057	else if ((uMsr == 0xc001001a \|\| uMsr == 0xc001001d) && g_enmVendor == CPUMCPUVENDOR_AMD)
4058	rc = reportMsr_AmdK8TopMemN(uMsr, uValue);
4059	else if (uMsr == 0xc0010030 && g_enmVendor == CPUMCPUVENDOR_AMD)
4060	rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, 6, "AmdK8CpuNameN", &i);
4061	else if (uMsr >= 0xc0010044 && uMsr <= 0xc001004a && g_enmVendor == CPUMCPUVENDOR_AMD)
4062	rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 7, "AmdK8McCtlMaskN", 0xc0010044, true /fEarlyEndOk/, false, 0, &i);
4063	else if (uMsr == 0xc0010050 && g_enmVendor == CPUMCPUVENDOR_AMD)
4064	rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, 4, "AmdK8SmiOnIoTrapN", &i);
4065	else if (uMsr == 0xc0010064 && g_enmVendor == CPUMCPUVENDOR_AMD)
4066	rc = reportMsr_AmdFam10hPStateN(&paMsrs[i], cMsrs - i, &i);
4067	else if (uMsr == 0xc0010070 && g_enmVendor == CPUMCPUVENDOR_AMD)
4068	rc = reportMsr_AmdFam10hCofVidControl(uMsr, uValue);
4069	else if ((uMsr == 0xc0010118 \|\| uMsr == 0xc0010119) && getMsrFnName(uMsr, NULL) && g_enmVendor == CPUMCPUVENDOR_AMD)
4070	rc = printMsrFunction(uMsr, NULL, NULL, annotateValue(uValue)); /* RAZ, write key. */
4071	else if (uMsr == 0xc0010200 && g_enmVendor == CPUMCPUVENDOR_AMD)
4072	rc = reportMsr_AmdGenPerfMixedRange(&paMsrs[i], cMsrs - i, 12, &i);
4073	else if (uMsr == 0xc0010230 && g_enmVendor == CPUMCPUVENDOR_AMD)
4074	rc = reportMsr_AmdGenPerfMixedRange(&paMsrs[i], cMsrs - i, 8, &i);
4075	else if (uMsr == 0xc0010240 && g_enmVendor == CPUMCPUVENDOR_AMD)
4076	rc = reportMsr_AmdGenPerfMixedRange(&paMsrs[i], cMsrs - i, 8, &i);
4077	else if (uMsr == 0xc0011019 && g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver && g_enmVendor == CPUMCPUVENDOR_AMD)
4078	rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 3, "AmdK7DrXAddrMaskN", 0xc0011019 - 1,
4079	false /fEarlyEndOk/, false /fNoIgnMask/, 0, &i);
4080	else if (uMsr == 0xc0011021 && g_enmVendor == CPUMCPUVENDOR_AMD)
4081	rc = reportMsr_AmdK7InstrCacheCfg(uMsr, uValue);
4082	else if (uMsr == 0xc0011023 && CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch))
4083	rc = reportMsr_AmdFam15hCombUnitCfg(uMsr, uValue);
4084	else if (uMsr == 0xc0011027 && g_enmVendor == CPUMCPUVENDOR_AMD)
4085	rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 1, "AmdK7DrXAddrMaskN", 0xc0011027,
4086	false /fEarlyEndOk/, false /fNoIgnMask/, 0, &i);
4087	else if (uMsr == 0xc001102c && CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch))
4088	rc = reportMsr_AmdFam15hExecUnitCfg(uMsr, uValue);
4089	/* generic handling. */
4090	else
4091	rc = reportMsr_Generic(uMsr, fFlags, uValue);
4092
4093	if (RT_FAILURE(rc))
4094	return rc;
4095
4096	/*
4097	* A little ugly snooping.
4098	*/
4099	if (uMsr == 0x000000cd && !(fFlags & VBCPUREPMSR_F_WRITE_ONLY))
4100	g_uMsrIntelP6FsbFrequency = uValue;
4101	}
4102
4103	return VINF_SUCCESS;
4104	}
4105
4106
4107	/**
4108	* Custom MSR hacking & probing.
4109	*
4110	* Called when the '-d' option is given.
4111	*
4112	* @returns VBox status code.
4113	*/
4114	static int hackingMsrs(void)
4115	{
4116	#if 0
4117	vbCpuRepDebug("\nhackingMsrs:\n"); RTStrmFlush(g_pDebugOut); RTThreadSleep(2000);
4118
4119	uint32_t uMsr = 0xc0000081;
4120	vbCpuRepDebug("%#x: msrProberModifyNoChange -> %RTbool\n", uMsr, msrProberModifyNoChange(uMsr));
4121	RTThreadSleep(3000);
4122
4123	vbCpuRepDebug("%#x: msrProberModifyBit 30 -> %d\n", uMsr, msrProberModifyBit(uMsr, 30));
4124	RTThreadSleep(3000);
4125
4126	vbCpuRepDebug("%#x: msrProberModifyZero -> %RTbool\n", uMsr, msrProberModifyZero(uMsr));
4127	RTThreadSleep(3000);
4128
4129	for (uint32_t i = 0; i < 63; i++)
4130	{
4131	vbCpuRepDebug("%#x: bit=%02u -> %d\n", msrProberModifyBit(uMsr, i));
4132	RTThreadSleep(500);
4133	}
4134	#else
4135
4136	uint32_t uMsr = 0xc0000080;
4137	uint64_t uValue = 0;
4138	msrProberRead(uMsr, &uValue);
4139	/* Try for a triple fault... */
4140	msrProberWrite(uMsr, uValue ^ MSR_K6_EFER_LME);
4141	msrProberRead(uMsr, &uValue);
4142	msrProberWrite(uMsr, uValue ^ MSR_K6_EFER_NXE);
4143	#endif
4144	return VINF_SUCCESS;
4145	}
4146
4147
4148	static int probeMsrs(bool fHacking, const char pszNameC, const char pszCpuDesc,
4149	char *pszMsrMask, size_t cbMsrMask)
4150	{
4151	/* Initialize the mask. */
4152	if (pszMsrMask && cbMsrMask)
4153	RTStrCopy(pszMsrMask, cbMsrMask, "UINT32_MAX /** @todo */");
4154
4155	/*
4156	* Are MSRs supported by the CPU?
4157	*/
4158	if ( !ASMIsValidStdRange(ASMCpuId_EAX(0))
4159	\|\| !(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_MSR) )
4160	{
4161	vbCpuRepDebug("Skipping MSR probing, CPUID indicates there isn't any MSR support.\n");
4162	return VINF_SUCCESS;
4163	}
4164
4165	/*
4166	* Initialize the support library and check if we can read MSRs.
4167	*/
4168	int rc = SUPR3Init(NULL);
4169	if (RT_FAILURE(rc))
4170	{
4171	vbCpuRepDebug("warning: Unable to initialize the support library (%Rrc), skipping MSR detection.\n", rc);
4172	return VINF_SUCCESS;
4173	}
4174	uint64_t uValue;
4175	bool fGp;
4176	rc = SUPR3MsrProberRead(MSR_IA32_TSC, NIL_RTCPUID, &uValue, &fGp);
4177	if (RT_FAILURE(rc))
4178	{
4179	vbCpuRepDebug("warning: MSR probing not supported by the support driver (%Rrc), skipping MSR detection.\n", rc);
4180	return VINF_SUCCESS;
4181	}
4182	vbCpuRepDebug("MSR_IA32_TSC: %#llx fGp=%RTbool\n", uValue, fGp);
4183	rc = SUPR3MsrProberRead(0xdeadface, NIL_RTCPUID, &uValue, &fGp);
4184	vbCpuRepDebug("0xdeadface: %#llx fGp=%RTbool rc=%Rrc\n", uValue, fGp, rc);
4185
4186	/*
4187	* Initialize globals we use.
4188	*/
4189	uint32_t uEax, uEbx, uEcx, uEdx;
4190	ASMCpuIdExSlow(0, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
4191	if (!ASMIsValidStdRange(uEax))
4192	return RTMsgErrorRc(VERR_NOT_SUPPORTED, "Invalid std CPUID range: %#x\n", uEax);
4193	g_enmVendor = CPUMR3CpuIdDetectVendorEx(uEax, uEbx, uEcx, uEdx);
4194
4195	ASMCpuIdExSlow(1, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
4196	g_enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx(g_enmVendor,
4197	ASMGetCpuFamily(uEax),
4198	ASMGetCpuModel(uEax, g_enmVendor == CPUMCPUVENDOR_INTEL),
4199	ASMGetCpuStepping(uEax));
4200	g_fIntelNetBurst = CPUMMICROARCH_IS_INTEL_NETBURST(g_enmMicroarch);
4201
4202	/*
4203	* Do the probing.
4204	*/
4205	if (fHacking)
4206	rc = hackingMsrs();
4207	else
4208	{
4209	/* Determine the MSR mask. */
4210	uint32_t fMsrMask = determineMsrAndMask();
4211	if (fMsrMask == UINT32_MAX)
4212	RTStrCopy(pszMsrMask, cbMsrMask, "UINT32_MAX");
4213	else
4214	RTStrPrintf(pszMsrMask, cbMsrMask, "UINT32_C(%#x)", fMsrMask);
4215
4216	/* Detect MSR. */
4217	VBCPUREPMSR *paMsrs;
4218	uint32_t cMsrs;
4219	rc = findMsrs(&paMsrs, &cMsrs, fMsrMask);
4220	if (RT_FAILURE(rc))
4221	return rc;
4222
4223	/* Probe the MSRs and spit out the database table. */
4224	vbCpuRepPrintf("\n"
4225	"#ifndef CPUM_DB_STANDALONE\n"
4226	"/**\n"
4227	" * MSR ranges for %s.\n"
4228	" */\n"
4229	"static CPUMMSRRANGE const g_aMsrRanges_%s[] = \n{\n",
4230	pszCpuDesc,
4231	pszNameC);
4232	rc = produceMsrReport(paMsrs, cMsrs);
4233	vbCpuRepPrintf("};\n"
4234	"#endif /* !CPUM_DB_STANDALONE */\n"
4235	"\n"
4236	);
4237
4238	RTMemFree(paMsrs);
4239	paMsrs = NULL;
4240	}
4241	return rc;
4242	}
4243
4244
4245	static int produceCpuIdArray(const char pszNameC, const char pszCpuDesc)
4246	{
4247	/*
4248	* Collect the data.
4249	*/
4250	PCPUMCPUIDLEAF paLeaves;
4251	uint32_t cLeaves;
4252	int rc = CPUMR3CpuIdCollectLeaves(&paLeaves, &cLeaves);
4253	if (RT_FAILURE(rc))
4254	return RTMsgErrorRc(rc, "CPUMR3CollectCpuIdInfo failed: %Rrc\n", rc);
4255
4256	/*
4257	* Dump the array.
4258	*/
4259	vbCpuRepPrintf("\n"
4260	"#ifndef CPUM_DB_STANDALONE\n"
4261	"/**\n"
4262	" * CPUID leaves for %s.\n"
4263	" */\n"
4264	"static CPUMCPUIDLEAF const g_aCpuIdLeaves_%s[] = \n{\n",
4265	pszCpuDesc,
4266	pszNameC);
4267	for (uint32_t i = 0; i < cLeaves; i++)
4268	{
4269	vbCpuRepPrintf(" { %#010x, %#010x, ", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf);
4270	if (paLeaves[i].fSubLeafMask == UINT32_MAX)
4271	vbCpuRepPrintf("UINT32_MAX, ");
4272	else
4273	vbCpuRepPrintf("%#010x, ", paLeaves[i].fSubLeafMask);
4274	vbCpuRepPrintf("%#010x, %#010x, %#010x, %#010x, ",
4275	paLeaves[i].uEax, paLeaves[i].uEbx, paLeaves[i].uEcx, paLeaves[i].uEdx);
4276	if (paLeaves[i].fFlags == 0)
4277	vbCpuRepPrintf("0 },\n");
4278	else
4279	{
4280	vbCpuRepPrintf("0");
4281	uint32_t fFlags = paLeaves[i].fFlags;
4282	if (paLeaves[i].fFlags & CPUMCPUIDLEAF_F_SUBLEAVES_ECX_UNCHANGED)
4283	{
4284	vbCpuRepPrintf(" \| CPUMCPUIDLEAF_F_SUBLEAVES_ECX_UNCHANGED");
4285	fFlags &= ~CPUMCPUIDLEAF_F_SUBLEAVES_ECX_UNCHANGED;
4286	}
4287	if (fFlags)
4288	{
4289	RTMemFree(paLeaves);
4290	return RTMsgErrorRc(rc, "Unknown CPUID flags %#x\n", fFlags);
4291	}
4292	vbCpuRepPrintf(" },\n");
4293	}
4294	}
4295	vbCpuRepPrintf("};\n"
4296	"#endif /* !CPUM_DB_STANDALONE */\n"
4297	"\n");
4298	RTMemFree(paLeaves);
4299	return VINF_SUCCESS;
4300	}
4301
4302
4303	static const char *cpuVendorToString(CPUMCPUVENDOR enmCpuVendor)
4304	{
4305	switch (enmCpuVendor)
4306	{
4307	case CPUMCPUVENDOR_INTEL: return "Intel";
4308	case CPUMCPUVENDOR_AMD: return "AMD";
4309	case CPUMCPUVENDOR_VIA: return "VIA";
4310	case CPUMCPUVENDOR_CYRIX: return "Cyrix";
4311	case CPUMCPUVENDOR_INVALID:
4312	case CPUMCPUVENDOR_UNKNOWN:
4313	case CPUMCPUVENDOR_32BIT_HACK:
4314	break;
4315	}
4316	return "invalid-cpu-vendor";
4317	}
4318
4319
4320	/**
4321	* Takes a shot a the bus frequency name (last part).
4322	*
4323	* @returns Name suffix.
4324	*/
4325	static const char *vbCpuRepGuessScalableBusFrequencyName(void)
4326	{
4327	if (CPUMMICROARCH_IS_INTEL_CORE7(g_enmMicroarch))
4328	return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge ? "100MHZ" : "133MHZ";
4329
4330	if (g_uMsrIntelP6FsbFrequency != UINT64_MAX)
4331	switch (g_uMsrIntelP6FsbFrequency & 0x7)
4332	{
4333	case 5: return "100MHZ";
4334	case 1: return "133MHZ";
4335	case 3: return "167MHZ";
4336	case 2: return "200MHZ";
4337	case 0: return "267MHZ";
4338	case 4: return "333MHZ";
4339	case 6: return "400MHZ";
4340	}
4341
4342	return "UNKNOWN";
4343	}
4344
4345
4346	static int produceCpuReport(void)
4347	{
4348	/*
4349	* Figure the cpu vendor.
4350	*/
4351	if (!ASMHasCpuId())
4352	return RTMsgErrorRc(VERR_NOT_SUPPORTED, "No CPUID support.\n");
4353	uint32_t uEax, uEbx, uEcx, uEdx;
4354	ASMCpuIdExSlow(0, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
4355	if (!ASMIsValidStdRange(uEax))
4356	return RTMsgErrorRc(VERR_NOT_SUPPORTED, "Invalid std CPUID range: %#x\n", uEax);
4357
4358	CPUMCPUVENDOR enmVendor = CPUMR3CpuIdDetectVendorEx(uEax, uEbx, uEcx, uEdx);
4359	if (enmVendor == CPUMCPUVENDOR_UNKNOWN)
4360	return RTMsgErrorRc(VERR_NOT_IMPLEMENTED, "Unknown CPU vendor: %.4s%.4s%.4s\n", &uEbx, &uEdx, &uEcx);
4361	vbCpuRepDebug("CPU Vendor: %s - %.4s%.4s%.4s\n", CPUMR3CpuVendorName(enmVendor), &uEbx, &uEdx, &uEcx);
4362
4363	/*
4364	* Determine the micro arch.
4365	*/
4366	ASMCpuIdExSlow(1, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
4367	CPUMMICROARCH enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx(enmVendor,
4368	ASMGetCpuFamily(uEax),
4369	ASMGetCpuModel(uEax, enmVendor == CPUMCPUVENDOR_INTEL),
4370	ASMGetCpuStepping(uEax));
4371
4372	/*
4373	* Generate a name.
4374	*/
4375	char szName[16*3+1];
4376	char szNameC[16*3+1];
4377	char szNameRaw[16*3+1];
4378	char *pszName = szName;
4379	char pszCpuDesc = (char )"";
4380
4381	ASMCpuIdExSlow(0x80000000, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
4382	if (ASMIsValidExtRange(uEax) && uEax >= UINT32_C(0x80000004))
4383	{
4384	/* Get the raw name and strip leading spaces. */
4385	ASMCpuIdExSlow(0x80000002, 0, 0, 0, &szNameRaw[0 + 0], &szNameRaw[4 + 0], &szNameRaw[8 + 0], &szNameRaw[12 + 0]);
4386	ASMCpuIdExSlow(0x80000003, 0, 0, 0, &szNameRaw[0 + 16], &szNameRaw[4 + 16], &szNameRaw[8 + 16], &szNameRaw[12 + 16]);
4387	ASMCpuIdExSlow(0x80000004, 0, 0, 0, &szNameRaw[0 + 32], &szNameRaw[4 + 32], &szNameRaw[8 + 32], &szNameRaw[12 + 32]);
4388	szNameRaw[48] = '\0';
4389	pszCpuDesc = RTStrStrip(szNameRaw);
4390	vbCpuRepDebug("Name2: %s\n", pszCpuDesc);
4391
4392	/* Reduce the name. */
4393	pszName = strcpy(szName, pszCpuDesc);
4394
4395	static const char * const s_apszSuffixes[] =
4396	{
4397	"CPU @",
4398	};
4399	for (uint32_t i = 0; i < RT_ELEMENTS(s_apszSuffixes); i++)
4400	{
4401	char *pszHit = strstr(pszName, s_apszSuffixes[i]);
4402	if (pszHit)
4403	RT_BZERO(pszHit, strlen(pszHit));
4404	}
4405
4406	static const char * const s_apszWords[] =
4407	{
4408	"(TM)", "(tm)", "(R)", "(r)", "Processor", "CPU", "@",
4409	};
4410	for (uint32_t i = 0; i < RT_ELEMENTS(s_apszWords); i++)
4411	{
4412	const char *pszWord = s_apszWords[i];
4413	size_t cchWord = strlen(pszWord);
4414	char *pszHit;
4415	while ((pszHit = strstr(pszName, pszWord)) != NULL)
4416	memmove(pszHit, pszHit + cchWord, strlen(pszHit + cchWord) + 1);
4417	}
4418
4419	RTStrStripR(pszName);
4420	for (char psz = pszName; psz; psz++)
4421	if (RT_C_IS_BLANK(*psz))
4422	{
4423	size_t cchBlanks = 1;
4424	while (RT_C_IS_BLANK(psz[cchBlanks]))
4425	cchBlanks++;
4426	*psz = ' ';
4427	if (cchBlanks > 1)
4428	memmove(psz + 1, psz + cchBlanks, strlen(psz + cchBlanks) + 1);
4429	}
4430	pszName = RTStrStripL(pszName);
4431	vbCpuRepDebug("Name: %s\n", pszName);
4432
4433	/* Make it C/C++ acceptable. */
4434	strcpy(szNameC, pszName);
4435	unsigned offDst = 0;
4436	for (unsigned offSrc = 0; ; offSrc++)
4437	{
4438	char ch = szNameC[offSrc];
4439	if (!RT_C_IS_ALNUM(ch) && ch != '_' && ch != '\0')
4440	ch = '_';
4441	if (ch == '_' && offDst > 0 && szNameC[offDst - 1] == '_')
4442	offDst--;
4443	szNameC[offDst++] = ch;
4444	if (!ch)
4445	break;
4446	}
4447	while (offDst > 1 && szNameC[offDst - 1] == '_')
4448	szNameC[--offDst] = '\0';
4449
4450	vbCpuRepDebug("NameC: %s\n", szNameC);
4451	}
4452	else
4453	{
4454	ASMCpuIdExSlow(1, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
4455	RTStrPrintf(szNameC, sizeof(szNameC), "%s_%u_%u_%u", cpuVendorToString(enmVendor), ASMGetCpuFamily(uEax),
4456	ASMGetCpuModel(uEax, enmVendor == CPUMCPUVENDOR_INTEL), ASMGetCpuStepping(uEax));
4457	pszCpuDesc = pszName = szNameC;
4458	vbCpuRepDebug("Name/NameC: %s\n", szNameC);
4459	}
4460
4461	/*
4462	* Print a file header, if we're not outputting to stdout (assumption being
4463	* that stdout is used while hacking the reporter and too much output is
4464	* unwanted).
4465	*/
4466	if (g_pReportOut)
4467	{
4468	RTTIMESPEC Now;
4469	char szNow[64];
4470	RTTimeSpecToString(RTTimeNow(&Now), szNow, sizeof(szNow));
4471	char *pchDot = strchr(szNow, '.');
4472	if (pchDot)
4473	strcpy(pchDot, "Z");
4474
4475	vbCpuRepPrintf("/* $" "Id" "$ */\n"
4476	"/** @file\n"
4477	" * CPU database entry \"%s\".\n"
4478	" * Generated at %s by VBoxCpuReport v%sr%s on %s.%s.\n"
4479	" */\n"
4480	"\n"
4481	"/*\n"
4482	" * Copyright (C) 2013 Oracle Corporation\n"
4483	" *\n"
4484	" * This file is part of VirtualBox Open Source Edition (OSE), as\n"
4485	" * available from http://www.alldomusa.eu.org. This file is free software;\n"
4486	" * you can redistribute it and/or modify it under the terms of the GNU\n"
4487	" * General Public License (GPL) as published by the Free Software\n"
4488	" * Foundation, in version 2 as it comes in the \"COPYING\" file of the\n"
4489	" * VirtualBox OSE distribution. VirtualBox OSE is distributed in the\n"
4490	" * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.\n"
4491	" */\n"
4492	"\n"
4493	"#ifndef VBOX_CPUDB_%s\n"
4494	"#define VBOX_CPUDB_%s\n"
4495	"\n",
4496	pszName,
4497	szNow, RTBldCfgVersion(), RTBldCfgRevisionStr(), RTBldCfgTarget(), RTBldCfgTargetArch(),
4498	szNameC, szNameC);
4499	}
4500
4501	/*
4502	* Extract CPUID based data.
4503	*/
4504	int rc = produceCpuIdArray(szNameC, pszCpuDesc);
4505	if (RT_FAILURE(rc))
4506	return rc;
4507
4508	CPUMUKNOWNCPUID enmUnknownMethod;
4509	CPUMCPUID DefUnknown;
4510	rc = CPUMR3CpuIdDetectUnknownLeafMethod(&enmUnknownMethod, &DefUnknown);
4511	if (RT_FAILURE(rc))
4512	return RTMsgErrorRc(rc, "CPUMR3DetectCpuIdUnknownMethod failed: %Rrc\n", rc);
4513	vbCpuRepDebug("enmUnknownMethod=%s\n", CPUMR3CpuIdUnknownLeafMethodName(enmUnknownMethod));
4514
4515	/*
4516	* Do the MSRs, if we can.
4517	*/
4518	char szMsrMask[64];
4519	probeMsrs(false /fHacking/, szNameC, pszCpuDesc, szMsrMask, sizeof(szMsrMask));
4520
4521	/*
4522	* Emit the CPUMDBENTRY record.
4523	*/
4524	ASMCpuIdExSlow(1, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
4525	vbCpuRepPrintf("\n"
4526	"/**\n"
4527	" * Database entry for %s.\n"
4528	" */\n"
4529	"static CPUMDBENTRY const g_Entry_%s = \n"
4530	"{\n"
4531	" /.pszName = / \"%s\",\n"
4532	" /.pszFullName = / \"%s\",\n"
4533	" /.enmVendor = / CPUMCPUVENDOR_%s,\n"
4534	" /.uFamily = / %u,\n"
4535	" /.uModel = / %u,\n"
4536	" /.uStepping = / %u,\n"
4537	" /.enmMicroarch = / kCpumMicroarch_%s,\n"
4538	" /.uScalableBusFreq = / CPUM_SBUSFREQ_%s,\n"
4539	" /.fFlags = / 0,\n"
4540	" /.cMaxPhysAddrWidth= / %u,\n"
4541	" /.paCpuIdLeaves = / NULL_ALONE(g_aCpuIdLeaves_%s),\n"
4542	" /.cCpuIdLeaves = / ZERO_ALONE(RT_ELEMENTS(g_aCpuIdLeaves_%s)),\n"
4543	" /.enmUnknownCpuId = / CPUMUKNOWNCPUID_%s,\n"
4544	" /.DefUnknownCpuId = / { %#010x, %#010x, %#010x, %#010x },\n"
4545	" /.fMsrMask = / %s,\n"
4546	" /.cMsrRanges = / ZERO_ALONE(RT_ELEMENTS(g_aMsrRanges_%s)),\n"
4547	" /.paMsrRanges = / NULL_ALONE(g_aMsrRanges_%s),\n"
4548	"};\n"
4549	"\n"
4550	"#endif /* !VBOX_DB_%s */\n"
4551	"\n",
4552	pszCpuDesc,
4553	szNameC,
4554	pszName,
4555	pszCpuDesc,
4556	CPUMR3CpuVendorName(enmVendor),
4557	ASMGetCpuFamily(uEax),
4558	ASMGetCpuModel(uEax, enmVendor == CPUMCPUVENDOR_INTEL),
4559	ASMGetCpuStepping(uEax),
4560	CPUMR3MicroarchName(enmMicroarch),
4561	vbCpuRepGuessScalableBusFrequencyName(),
4562	vbCpuRepGetPhysAddrWidth(),
4563	szNameC,
4564	szNameC,
4565	CPUMR3CpuIdUnknownLeafMethodName(enmUnknownMethod),
4566	DefUnknown.eax,
4567	DefUnknown.ebx,
4568	DefUnknown.ecx,
4569	DefUnknown.edx,
4570	szMsrMask,
4571	szNameC,
4572	szNameC,
4573	szNameC
4574	);
4575
4576	return VINF_SUCCESS;
4577	}
4578
4579
4580	int main(int argc, char **argv)
4581	{
4582	int rc = RTR3InitExe(argc, &argv, 0 /fFlags/);
4583	if (RT_FAILURE(rc))
4584	return RTMsgInitFailure(rc);
4585
4586	/*
4587	* Argument parsing?
4588	*/
4589	static const RTGETOPTDEF s_aOptions[] =
4590	{
4591	{ "--msrs-only", 'm', RTGETOPT_REQ_NOTHING },
4592	{ "--msrs-dev", 'd', RTGETOPT_REQ_NOTHING },
4593	{ "--output", 'o', RTGETOPT_REQ_STRING },
4594	{ "--log", 'l', RTGETOPT_REQ_STRING },
4595	};
4596	RTGETOPTSTATE State;
4597	RTGetOptInit(&State, argc, argv, &s_aOptions[0], RT_ELEMENTS(s_aOptions), 1, RTGETOPTINIT_FLAGS_OPTS_FIRST);
4598
4599	enum
4600	{
4601	kCpuReportOp_Normal,
4602	kCpuReportOp_MsrsOnly,
4603	kCpuReportOp_MsrsHacking
4604	} enmOp = kCpuReportOp_Normal;
4605	g_pReportOut = NULL;
4606	g_pDebugOut = NULL;
4607	const char *pszOutput = NULL;
4608	const char *pszDebugOut = NULL;
4609
4610	int iOpt;
4611	RTGETOPTUNION ValueUnion;
4612	while ((iOpt = RTGetOpt(&State, &ValueUnion)) != 0)
4613	{
4614	switch (iOpt)
4615	{
4616	case 'm':
4617	enmOp = kCpuReportOp_MsrsOnly;
4618	break;
4619
4620	case 'd':
4621	enmOp = kCpuReportOp_MsrsHacking;
4622	break;
4623
4624	case 'o':
4625	pszOutput = ValueUnion.psz;
4626	break;
4627
4628	case 'l':
4629	pszDebugOut = ValueUnion.psz;
4630	break;
4631
4632	case 'h':
4633	RTPrintf("Usage: VBoxCpuReport [-m\|--msrs-only] [-d\|--msrs-dev] [-h\|--help] [-V\|--version] [-o filename.h] [-l debug.log]\n");
4634	RTPrintf("Internal tool for gathering information to the VMM CPU database.\n");
4635	return RTEXITCODE_SUCCESS;
4636	case 'V':
4637	RTPrintf("%sr%s\n", RTBldCfgVersion(), RTBldCfgRevisionStr());
4638	return RTEXITCODE_SUCCESS;
4639	default:
4640	return RTGetOptPrintError(iOpt, &ValueUnion);
4641	}
4642	}
4643
4644	/*
4645	* Open the alternative debug log stream.
4646	*/
4647	if (pszDebugOut)
4648	{
4649	if (RTFileExists(pszDebugOut) && !RTSymlinkExists(pszDebugOut))
4650	{
4651	char szOld[RTPATH_MAX];
4652	rc = RTStrCopy(szOld, sizeof(szOld), pszDebugOut);
4653	if (RT_SUCCESS(rc))
4654	rc = RTStrCat(szOld, sizeof(szOld), ".old");
4655	if (RT_SUCCESS(rc))
4656	RTFileRename(pszDebugOut, szOld, RTFILEMOVE_FLAGS_REPLACE);
4657	}
4658	rc = RTStrmOpen(pszDebugOut, "w", &g_pDebugOut);
4659	if (RT_FAILURE(rc))
4660	{
4661	RTMsgError("Error opening '%s': %Rrc", pszDebugOut, rc);
4662	g_pDebugOut = NULL;
4663	}
4664	}
4665
4666	/*
4667	* Do the requested job.
4668	*/
4669	rc = VERR_INTERNAL_ERROR;
4670	switch (enmOp)
4671	{
4672	case kCpuReportOp_Normal:
4673	/* switch output file. */
4674	if (pszOutput)
4675	{
4676	if (RTFileExists(pszOutput) && !RTSymlinkExists(pszOutput))
4677	{
4678	char szOld[RTPATH_MAX];
4679	rc = RTStrCopy(szOld, sizeof(szOld), pszOutput);
4680	if (RT_SUCCESS(rc))
4681	rc = RTStrCat(szOld, sizeof(szOld), ".old");
4682	if (RT_SUCCESS(rc))
4683	RTFileRename(pszOutput, szOld, RTFILEMOVE_FLAGS_REPLACE);
4684	}
4685	rc = RTStrmOpen(pszOutput, "w", &g_pReportOut);
4686	if (RT_FAILURE(rc))
4687	{
4688	RTMsgError("Error opening '%s': %Rrc", pszOutput, rc);
4689	break;
4690	}
4691	}
4692	rc = produceCpuReport();
4693	break;
4694	case kCpuReportOp_MsrsOnly:
4695	case kCpuReportOp_MsrsHacking:
4696	rc = probeMsrs(enmOp == kCpuReportOp_MsrsHacking, NULL, NULL, NULL, 0);
4697	break;
4698	}
4699
4700	/*
4701	* Close the output files.
4702	*/
4703	if (g_pReportOut)
4704	{
4705	RTStrmClose(g_pReportOut);
4706	g_pReportOut = NULL;
4707	}
4708
4709	if (g_pDebugOut)
4710	{
4711	RTStrmClose(g_pDebugOut);
4712	g_pDebugOut = NULL;
4713	}
4714
4715	return RT_SUCCESS(rc) ? RTEXITCODE_SUCCESS : RTEXITCODE_FAILURE;
4716	}
4717

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source: vbox/trunk/src/VBox/VMM/tools/VBoxCpuReport.cpp@ 50606

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