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source: vbox/trunk/src/VBox/VMM/include/PGMInternal.h@ 86462

最後變更 在這個檔案從86462是 86462,由 vboxsync 提交於 4 年 前

VMM/PGM: Don't check for, or even define, PGM_PLXFLAGS_MAPPING when PGM_WITHOUT_MAPPINGS is active (the default now).
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1/* $Id: PGMInternal.h 86462 2020-10-06 16:43:10Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.alldomusa.eu.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VMM_INCLUDED_SRC_include_PGMInternal_h
19#define VMM_INCLUDED_SRC_include_PGMInternal_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#include <VBox/cdefs.h>
25#include <VBox/types.h>
26#include <VBox/err.h>
27#include <VBox/dbg.h>
28#include <VBox/vmm/stam.h>
29#include <VBox/param.h>
30#include <VBox/vmm/vmm.h>
31#include <VBox/vmm/mm.h>
32#include <VBox/vmm/pdmcritsect.h>
33#include <VBox/vmm/pdmapi.h>
34#include <VBox/dis.h>
35#include <VBox/vmm/dbgf.h>
36#include <VBox/log.h>
37#include <VBox/vmm/gmm.h>
38#include <VBox/vmm/hm.h>
39#include <VBox/vmm/hm_vmx.h>
40#include <iprt/asm.h>
41#include <iprt/assert.h>
42#include <iprt/avl.h>
43#include <iprt/critsect.h>
44#include <iprt/list-off32.h>
45#include <iprt/sha.h>
46
47
48
49/** @defgroup grp_pgm_int Internals
50 * @ingroup grp_pgm
51 * @internal
52 * @{
53 */
54
55
56/** @name PGM Compile Time Config
57 * @{
58 */
59
60/**
61 * Indicates that there are no guest mappings in the shadow tables.
62 *
63 * Note! In ring-3 the macro is also used to exclude the managment of the
64 * intermediate context page tables. On 32-bit systems we use the intermediate
65 * context to support 64-bit guest execution. Thus, we cannot fully make it
66 * without mappings there even when VBOX_WITH_RAW_MODE is not defined.
67 *
68 * In raw-mode context there are by design always guest mappings (the code is
69 * executed from one), while in ring-0 there are none at all. Neither context
70 * manages the page tables for intermediate switcher context, that's all done in
71 * ring-3.
72 *
73 * Update 6.1: It is always defined now, in pgm.h
74 */
75#if defined(IN_RING0) \
76 || ( !defined(VBOX_WITH_RAW_MODE) \
77 && ( HC_ARCH_BITS != 32 \
78 || !defined(VBOX_WITH_64_BITS_GUESTS) \
79 ) \
80 )
81# undef PGM_WITHOUT_MAPPINGS
82# define PGM_WITHOUT_MAPPINGS
83#endif
84
85/**
86 * Check and skip global PDEs for non-global flushes
87 */
88#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
89
90/**
91 * Optimization for PAE page tables that are modified often
92 */
93//#if 0 /* disabled again while debugging */
94#define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
95//#endif
96
97/**
98 * Large page support enabled only on 64 bits hosts; applies to nested paging only.
99 */
100#define PGM_WITH_LARGE_PAGES
101
102/**
103 * Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
104 * VMX_EXIT_EPT_MISCONFIG.
105 */
106#define PGM_WITH_MMIO_OPTIMIZATIONS
107
108/**
109 * Sync N pages instead of a whole page table
110 */
111#define PGM_SYNC_N_PAGES
112
113/**
114 * Number of pages to sync during a page fault
115 *
116 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
117 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
118 *
119 * Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
120 * world switch overhead, so let's sync more.
121 */
122# ifdef IN_RING0
123/* Chose 32 based on the compile test in @bugref{4219}; 64 shows worse stats.
124 * 32 again shows better results than 16; slightly more overhead in the \#PF handler,
125 * but ~5% fewer faults.
126 */
127# define PGM_SYNC_NR_PAGES 32
128#else
129# define PGM_SYNC_NR_PAGES 8
130#endif
131
132/**
133 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
134 */
135#define PGM_MAX_PHYSCACHE_ENTRIES 64
136#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
137
138
139/** @def PGMPOOL_CFG_MAX_GROW
140 * The maximum number of pages to add to the pool in one go.
141 */
142#define PGMPOOL_CFG_MAX_GROW (_2M >> PAGE_SHIFT)
143
144/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
145 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
146 */
147#ifdef VBOX_STRICT
148# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
149#endif
150
151/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
152 * Enables the experimental lazy page allocation code. */
153#ifdef DOXYGEN_RUNNING
154# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC
155#endif
156
157/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
158 * Enables real write monitoring of pages, i.e. mapping them read-only and
159 * only making them writable when getting a write access \#PF. */
160#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
161
162/** @} */
163
164
165/** @name PDPT and PML4 flags.
166 * These are placed in the three bits available for system programs in
167 * the PDPT and PML4 entries.
168 * @{ */
169/** The entry is a permanent one and it's must always be present.
170 * Never free such an entry. */
171#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
172#ifndef PGM_WITHOUT_MAPPINGS
173/** Mapping (hypervisor allocated pagetable). */
174#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
175#endif
176/** @} */
177
178/** @name Page directory flags.
179 * These are placed in the three bits available for system programs in
180 * the page directory entries.
181 * @{ */
182/** Indicates the original entry was a big page.
183 * @remarks This is currently only used for statistics and can be recycled. */
184#define PGM_PDFLAGS_BIG_PAGE RT_BIT_64(9)
185#ifndef PGM_WITHOUT_MAPPINGS
186/** Mapping (hypervisor allocated pagetable). */
187# define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
188#endif
189/** Made read-only to facilitate dirty bit tracking. */
190#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
191/** @} */
192
193/** @name Page flags.
194 * These are placed in the three bits available for system programs in
195 * the page entries.
196 * @{ */
197/** Made read-only to facilitate dirty bit tracking. */
198#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
199
200#ifndef PGM_PTFLAGS_CSAM_VALIDATED
201/** Scanned and approved by CSAM (tm).
202 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
203 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/vmm/pgm.h. */
204#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
205#endif
206
207/** @} */
208
209/** @name Defines used to indicate the shadow and guest paging in the templates.
210 * @{ */
211#define PGM_TYPE_REAL 1
212#define PGM_TYPE_PROT 2
213#define PGM_TYPE_32BIT 3
214#define PGM_TYPE_PAE 4
215#define PGM_TYPE_AMD64 5
216#define PGM_TYPE_NESTED_32BIT 6
217#define PGM_TYPE_NESTED_PAE 7
218#define PGM_TYPE_NESTED_AMD64 8
219#define PGM_TYPE_EPT 9
220#define PGM_TYPE_NONE 10 /**< Dummy shadow paging mode for NEM. */
221#define PGM_TYPE_END (PGM_TYPE_NONE + 1)
222#define PGM_TYPE_FIRST_SHADOW PGM_TYPE_32BIT /**< The first type used by shadow paging. */
223/** @} */
224
225/** Macro for checking if the guest is using paging.
226 * @param uGstType PGM_TYPE_*
227 * @param uShwType PGM_TYPE_*
228 * @remark ASSUMES certain order of the PGM_TYPE_* values.
229 */
230#define PGM_WITH_PAGING(uGstType, uShwType) \
231 ( (uGstType) >= PGM_TYPE_32BIT \
232 && (uShwType) < PGM_TYPE_NESTED_32BIT)
233
234/** Macro for checking if the guest supports the NX bit.
235 * @param uGstType PGM_TYPE_*
236 * @param uShwType PGM_TYPE_*
237 * @remark ASSUMES certain order of the PGM_TYPE_* values.
238 */
239#define PGM_WITH_NX(uGstType, uShwType) \
240 ( (uGstType) >= PGM_TYPE_PAE \
241 && (uShwType) < PGM_TYPE_NESTED_32BIT)
242
243/** Macro for checking for nested or EPT.
244 * @param uType PGM_TYPE_*
245 */
246#define PGM_TYPE_IS_NESTED(uType) \
247 ( (uType) == PGM_TYPE_NESTED_32BIT \
248 || (uType) == PGM_TYPE_NESTED_PAE \
249 || (uType) == PGM_TYPE_NESTED_AMD64)
250
251/** Macro for checking for nested or EPT.
252 * @param uType PGM_TYPE_*
253 */
254#define PGM_TYPE_IS_NESTED_OR_EPT(uType) \
255 ( (uType) == PGM_TYPE_NESTED_32BIT \
256 || (uType) == PGM_TYPE_NESTED_PAE \
257 || (uType) == PGM_TYPE_NESTED_AMD64 \
258 || (uType) == PGM_TYPE_EPT)
259
260
261
262/** @def PGM_HCPHYS_2_PTR
263 * Maps a HC physical page pool address to a virtual address.
264 *
265 * @returns VBox status code.
266 * @param pVM The cross context VM structure.
267 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
268 * @param HCPhys The HC physical address to map to a virtual one.
269 * @param ppv Where to store the virtual address. No need to cast
270 * this.
271 *
272 * @remark There is no need to assert on the result.
273 */
274#define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) pgmPoolHCPhys2Ptr(pVM, HCPhys, (void **)(ppv))
275
276/** @def PGM_GCPHYS_2_PTR_V2
277 * Maps a GC physical page address to a virtual address.
278 *
279 * @returns VBox status code.
280 * @param pVM The cross context VM structure.
281 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
282 * @param GCPhys The GC physical address to map to a virtual one.
283 * @param ppv Where to store the virtual address. No need to cast this.
284 *
285 * @remark Use with care as we don't have so much dynamic mapping space in
286 * ring-0 on 32-bit darwin and in RC.
287 * @remark There is no need to assert on the result.
288 */
289#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
290# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
291 pgmRZDynMapGCPageV2Inlined(pVM, pVCpu, GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
292#else
293# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
294 pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
295#endif
296
297/** @def PGM_GCPHYS_2_PTR
298 * Maps a GC physical page address to a virtual address.
299 *
300 * @returns VBox status code.
301 * @param pVM The cross context VM structure.
302 * @param GCPhys The GC physical address to map to a virtual one.
303 * @param ppv Where to store the virtual address. No need to cast this.
304 *
305 * @remark Use with care as we don't have so much dynamic mapping space in
306 * ring-0 on 32-bit darwin and in RC.
307 * @remark There is no need to assert on the result.
308 */
309#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
310
311/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
312 * Maps a GC physical page address to a virtual address.
313 *
314 * @returns VBox status code.
315 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
316 * @param GCPhys The GC physical address to map to a virtual one.
317 * @param ppv Where to store the virtual address. No need to cast this.
318 *
319 * @remark Use with care as we don't have so much dynamic mapping space in
320 * ring-0 on 32-bit darwin and in RC.
321 * @remark There is no need to assert on the result.
322 */
323#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
324
325/** @def PGM_GCPHYS_2_PTR_EX
326 * Maps a unaligned GC physical page address to a virtual address.
327 *
328 * @returns VBox status code.
329 * @param pVM The cross context VM structure.
330 * @param GCPhys The GC physical address to map to a virtual one.
331 * @param ppv Where to store the virtual address. No need to cast this.
332 *
333 * @remark Use with care as we don't have so much dynamic mapping space in
334 * ring-0 on 32-bit darwin and in RC.
335 * @remark There is no need to assert on the result.
336 */
337#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
338# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
339 pgmRZDynMapGCPageOffInlined(VMMGetCpu(pVM), GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
340#else
341# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
342 pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
343#endif
344
345/** @def PGM_DYNMAP_UNUSED_HINT
346 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
347 * is no longer used.
348 *
349 * For best effect only apply this to the page that was mapped most recently.
350 *
351 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
352 * @param pvPage The pool page.
353 */
354#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
355# ifdef LOG_ENABLED
356# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage, RT_SRC_POS)
357# else
358# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage)
359# endif
360#else
361# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
362#endif
363
364/** @def PGM_DYNMAP_UNUSED_HINT_VM
365 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
366 * is no longer used.
367 *
368 * For best effect only apply this to the page that was mapped most recently.
369 *
370 * @param pVM The cross context VM structure.
371 * @param pvPage The pool page.
372 */
373#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
374
375
376/** @def PGM_INVL_PG
377 * Invalidates a page.
378 *
379 * @param pVCpu The cross context virtual CPU structure.
380 * @param GCVirt The virtual address of the page to invalidate.
381 */
382#ifdef IN_RING0
383# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
384#elif defined(IN_RING3)
385# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
386#else
387# error "Not IN_RING0 or IN_RING3!"
388#endif
389
390/** @def PGM_INVL_PG_ALL_VCPU
391 * Invalidates a page on all VCPUs
392 *
393 * @param pVM The cross context VM structure.
394 * @param GCVirt The virtual address of the page to invalidate.
395 */
396#ifdef IN_RING0
397# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
398#else
399# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
400#endif
401
402/** @def PGM_INVL_BIG_PG
403 * Invalidates a 4MB page directory entry.
404 *
405 * @param pVCpu The cross context virtual CPU structure.
406 * @param GCVirt The virtual address within the page directory to invalidate.
407 */
408#ifdef IN_RING0
409# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTlb(pVCpu)
410#else
411# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTlb(pVCpu)
412#endif
413
414/** @def PGM_INVL_VCPU_TLBS()
415 * Invalidates the TLBs of the specified VCPU
416 *
417 * @param pVCpu The cross context virtual CPU structure.
418 */
419#ifdef IN_RING0
420# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTlb(pVCpu)
421#else
422# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTlb(pVCpu)
423#endif
424
425/** @def PGM_INVL_ALL_VCPU_TLBS()
426 * Invalidates the TLBs of all VCPUs
427 *
428 * @param pVM The cross context VM structure.
429 */
430#ifdef IN_RING0
431# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTlbOnAllVCpus(pVM)
432#else
433# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTlbOnAllVCpus(pVM)
434#endif
435
436
437/** @name Safer Shadow PAE PT/PTE
438 * For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
439 * present.
440 *
441 * @{
442 */
443#if 1
444/**
445 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
446 * invalid entries for present.
447 * @sa X86PTEPAE.
448 */
449typedef union PGMSHWPTEPAE
450{
451 /** Unsigned integer view */
452 X86PGPAEUINT uCareful;
453 /* Not other views. */
454} PGMSHWPTEPAE;
455
456# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
457# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
458# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
459# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
460# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
461# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
462# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_RW | X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P | X86_PTE_RW) )
463# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
464# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
465# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /**< Use with care. */
466# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
467# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
468# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
469# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
470# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
471# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful |= X86_PTE_RW; } while (0)
472
473/**
474 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
475 * invalid entries for present.
476 * @sa X86PTPAE.
477 */
478typedef struct PGMSHWPTPAE
479{
480 PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
481} PGMSHWPTPAE;
482
483#else
484typedef X86PTEPAE PGMSHWPTEPAE;
485typedef X86PTPAE PGMSHWPTPAE;
486# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
487# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
488# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
489# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
490# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
491# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
492# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P | X86_PTE_RW)) == (X86_PTE_P | X86_PTE_RW) )
493# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
494# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
495# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /**< Use with care. */
496# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
497# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
498# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
499# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
500# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
501# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u |= X86_PTE_RW; } while (0)
502
503#endif
504
505/** Pointer to a shadow PAE PTE. */
506typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
507/** Pointer to a const shadow PAE PTE. */
508typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
509
510/** Pointer to a shadow PAE page table. */
511typedef PGMSHWPTPAE *PPGMSHWPTPAE;
512/** Pointer to a const shadow PAE page table. */
513typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
514/** @} */
515
516#ifndef PGM_WITHOUT_MAPPINGS
517
518/** Size of the GCPtrConflict array in PGMMAPPING.
519 * @remarks Must be a power of two. */
520# define PGMMAPPING_CONFLICT_MAX 8
521
522/**
523 * Structure for tracking GC Mappings.
524 *
525 * This structure is used by linked list in both GC and HC.
526 */
527typedef struct PGMMAPPING
528{
529 /** Pointer to next entry. */
530 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
531 /** Pointer to next entry. */
532 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
533 /** Indicate whether this entry is finalized. */
534 bool fFinalized;
535 bool afPadding[7];
536 /** Start Virtual address. */
537 RTGCPTR GCPtr;
538 /** Last Virtual address (inclusive). */
539 RTGCPTR GCPtrLast;
540 /** Range size (bytes). */
541 RTGCPTR cb;
542 /** Pointer to relocation callback function. */
543 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
544 /** User argument to the callback. */
545 R3PTRTYPE(void *) pvUser;
546 /** Mapping description / name. For easing debugging. */
547 R3PTRTYPE(const char *) pszDesc;
548 /** Last 8 addresses that caused conflicts. */
549 RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
550 /** Number of conflicts for this hypervisor mapping. */
551 uint32_t cConflicts;
552 /** Number of page tables. */
553 uint32_t cPTs;
554
555 /** Array of page table mapping data. Each entry
556 * describes one page table. The array can be longer
557 * than the declared length.
558 */
559 struct
560 {
561 /** The HC physical address of the page table. */
562 RTHCPHYS HCPhysPT;
563 /** The HC physical address of the first PAE page table. */
564 RTHCPHYS HCPhysPaePT0;
565 /** The HC physical address of the second PAE page table. */
566 RTHCPHYS HCPhysPaePT1;
567 /** The HC virtual address of the 32-bit page table. */
568 R3PTRTYPE(PX86PT) pPTR3;
569 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
570 R3PTRTYPE(PPGMSHWPTPAE) paPaePTsR3;
571 /** The R0 virtual address of the 32-bit page table. */
572 R0PTRTYPE(PX86PT) pPTR0;
573 /** The R0 virtual address of the two PAE page table. */
574 R0PTRTYPE(PPGMSHWPTPAE) paPaePTsR0;
575 } aPTs[1];
576} PGMMAPPING;
577/** Pointer to structure for tracking GC Mappings. */
578typedef struct PGMMAPPING *PPGMMAPPING;
579
580#endif /* !PGM_WITHOUT_MAPPINGS */
581
582
583/**
584 * Physical page access handler type registration.
585 */
586typedef struct PGMPHYSHANDLERTYPEINT
587{
588 /** Number of references. */
589 uint32_t volatile cRefs;
590 /** Magic number (PGMPHYSHANDLERTYPEINT_MAGIC). */
591 uint32_t u32Magic;
592 /** Link of handler types anchored in PGMTREES::HeadPhysHandlerTypes. */
593 RTLISTOFF32NODE ListNode;
594 /** The kind of accesses we're handling. */
595 PGMPHYSHANDLERKIND enmKind;
596 /** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
597 uint32_t uState;
598 /** Pointer to R3 callback function. */
599 R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3;
600 /** Pointer to R0 callback function. */
601 R0PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR0;
602 /** Pointer to R0 callback function for \#PFs. */
603 R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerR0;
604 /** Description / Name. For easing debugging. */
605 R3PTRTYPE(const char *) pszDesc;
606} PGMPHYSHANDLERTYPEINT;
607/** Pointer to a physical access handler type registration. */
608typedef PGMPHYSHANDLERTYPEINT *PPGMPHYSHANDLERTYPEINT;
609/** Magic value for the physical handler callbacks (Robert A. Heinlein). */
610#define PGMPHYSHANDLERTYPEINT_MAGIC UINT32_C(0x19070707)
611/** Magic value for the physical handler callbacks. */
612#define PGMPHYSHANDLERTYPEINT_MAGIC_DEAD UINT32_C(0x19880508)
613
614/**
615 * Converts a handle to a pointer.
616 * @returns PPGMPHYSHANDLERTYPEINT
617 * @param a_pVM The cross context VM structure.
618 * @param a_hType Physical access handler type handle.
619 */
620#define PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, a_hType) ((PPGMPHYSHANDLERTYPEINT)MMHyperHeapOffsetToPtr(a_pVM, a_hType))
621
622
623/**
624 * Physical page access handler structure.
625 *
626 * This is used to keep track of physical address ranges
627 * which are being monitored in some kind of way.
628 */
629typedef struct PGMPHYSHANDLER
630{
631 AVLROGCPHYSNODECORE Core;
632 /** Number of pages to update. */
633 uint32_t cPages;
634 /** Set if we have pages that have been aliased. */
635 uint32_t cAliasedPages;
636 /** Set if we have pages that have temporarily been disabled. */
637 uint32_t cTmpOffPages;
638 /** Registered handler type handle (heap offset). */
639 PGMPHYSHANDLERTYPE hType;
640 /** User argument for R3 handlers. */
641 R3PTRTYPE(void *) pvUserR3;
642 /** User argument for R0 handlers. */
643 R0PTRTYPE(void *) pvUserR0;
644 /** Description / Name. For easing debugging. */
645 R3PTRTYPE(const char *) pszDesc;
646#ifdef VBOX_WITH_STATISTICS
647 /** Profiling of this handler. */
648 STAMPROFILE Stat;
649#endif
650} PGMPHYSHANDLER;
651/** Pointer to a physical page access handler structure. */
652typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
653
654/**
655 * Gets the type record for a physical handler (no reference added).
656 * @returns PPGMPHYSHANDLERTYPEINT
657 * @param a_pVM The cross context VM structure.
658 * @param a_pPhysHandler Pointer to the physical handler structure
659 * (PGMPHYSHANDLER).
660 */
661#define PGMPHYSHANDLER_GET_TYPE(a_pVM, a_pPhysHandler) PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, (a_pPhysHandler)->hType)
662
663
664/**
665 * A Physical Guest Page tracking structure.
666 *
667 * The format of this structure is complicated because we have to fit a lot
668 * of information into as few bits as possible. The format is also subject
669 * to change (there is one coming up soon). Which means that for we'll be
670 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
671 * accesses to the structure.
672 */
673typedef union PGMPAGE
674{
675 /** Structured view. */
676 struct
677 {
678 /** 1:0 - The physical handler state (PGM_PAGE_HNDL_PHYS_STATE_*). */
679 uint64_t u2HandlerPhysStateY : 2;
680 /** 3:2 - Paging structure needed to map the page
681 * (PGM_PAGE_PDE_TYPE_*). */
682 uint64_t u2PDETypeY : 2;
683 /** 4 - Unused (was used by FTE for dirty tracking). */
684 uint64_t fUnused1 : 1;
685 /** 5 - Flag indicating that a write monitored page was written to
686 * when set. */
687 uint64_t fWrittenToY : 1;
688 /** 7:6 - Unused. */
689 uint64_t u2Unused0 : 2;
690 /** 9:8 - Unused (was used by PGM_PAGE_HNDL_VIRT_STATE_*). */
691 uint64_t u2Unused1 : 2;
692 /** 11:10 - NEM state bits. */
693 uint64_t u2NemStateY : 2;
694 /** 12:48 - The host physical frame number (shift left to get the
695 * address). */
696 uint64_t HCPhysFN : 36;
697 /** 50:48 - The page state. */
698 uint64_t uStateY : 3;
699 /** 51:53 - The page type (PGMPAGETYPE). */
700 uint64_t uTypeY : 3;
701 /** 63:54 - PTE index for usage tracking (page pool). */
702 uint64_t u10PteIdx : 10;
703
704 /** The GMM page ID.
705 * @remarks In the current implementation, MMIO2 and pages aliased to
706 * MMIO2 pages will be exploiting this field to calculate the
707 * ring-3 mapping address corresponding to the page.
708 * Later we may consider including MMIO2 management into GMM. */
709 uint32_t idPage;
710 /** Usage tracking (page pool). */
711 uint16_t u16TrackingY;
712 /** The number of read locks on this page. */
713 uint8_t cReadLocksY;
714 /** The number of write locks on this page. */
715 uint8_t cWriteLocksY;
716 } s;
717
718 /** 64-bit integer view. */
719 uint64_t au64[2];
720 /** 16-bit view. */
721 uint32_t au32[4];
722 /** 16-bit view. */
723 uint16_t au16[8];
724 /** 8-bit view. */
725 uint8_t au8[16];
726} PGMPAGE;
727AssertCompileSize(PGMPAGE, 16);
728/** Pointer to a physical guest page. */
729typedef PGMPAGE *PPGMPAGE;
730/** Pointer to a const physical guest page. */
731typedef const PGMPAGE *PCPGMPAGE;
732/** Pointer to a physical guest page pointer. */
733typedef PPGMPAGE *PPPGMPAGE;
734
735
736/**
737 * Clears the page structure.
738 * @param a_pPage Pointer to the physical guest page tracking structure.
739 */
740#define PGM_PAGE_CLEAR(a_pPage) \
741 do { \
742 (a_pPage)->au64[0] = 0; \
743 (a_pPage)->au64[1] = 0; \
744 } while (0)
745
746/**
747 * Initializes the page structure.
748 * @param a_pPage Pointer to the physical guest page tracking structure.
749 * @param a_HCPhys The host physical address of the page.
750 * @param a_idPage The (GMM) page ID of the page.
751 * @param a_uType The page type (PGMPAGETYPE).
752 * @param a_uState The page state (PGM_PAGE_STATE_XXX).
753 */
754#define PGM_PAGE_INIT(a_pPage, a_HCPhys, a_idPage, a_uType, a_uState) \
755 do { \
756 RTHCPHYS SetHCPhysTmp = (a_HCPhys); \
757 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
758 (a_pPage)->au64[0] = SetHCPhysTmp; \
759 (a_pPage)->au64[1] = 0; \
760 (a_pPage)->s.idPage = (a_idPage); \
761 (a_pPage)->s.uStateY = (a_uState); \
762 (a_pPage)->s.uTypeY = (a_uType); \
763 } while (0)
764
765/**
766 * Initializes the page structure of a ZERO page.
767 * @param a_pPage Pointer to the physical guest page tracking structure.
768 * @param a_pVM The VM handle (for getting the zero page address).
769 * @param a_uType The page type (PGMPAGETYPE).
770 */
771#define PGM_PAGE_INIT_ZERO(a_pPage, a_pVM, a_uType) \
772 PGM_PAGE_INIT((a_pPage), (a_pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (a_uType), PGM_PAGE_STATE_ZERO)
773
774
775/** @name The Page state, PGMPAGE::uStateY.
776 * @{ */
777/** The zero page.
778 * This is a per-VM page that's never ever mapped writable. */
779#define PGM_PAGE_STATE_ZERO 0U
780/** A allocated page.
781 * This is a per-VM page allocated from the page pool (or wherever
782 * we get MMIO2 pages from if the type is MMIO2).
783 */
784#define PGM_PAGE_STATE_ALLOCATED 1U
785/** A allocated page that's being monitored for writes.
786 * The shadow page table mappings are read-only. When a write occurs, the
787 * fWrittenTo member is set, the page remapped as read-write and the state
788 * moved back to allocated. */
789#define PGM_PAGE_STATE_WRITE_MONITORED 2U
790/** The page is shared, aka. copy-on-write.
791 * This is a page that's shared with other VMs. */
792#define PGM_PAGE_STATE_SHARED 3U
793/** The page is ballooned, so no longer available for this VM. */
794#define PGM_PAGE_STATE_BALLOONED 4U
795/** @} */
796
797
798/** Asserts lock ownership in some of the PGM_PAGE_XXX macros. */
799#if defined(VBOX_STRICT) && 0 /** @todo triggers in pgmRZDynMapGCPageV2Inlined */
800# define PGM_PAGE_ASSERT_LOCK(a_pVM) PGM_LOCK_ASSERT_OWNER(a_pVM)
801#else
802# define PGM_PAGE_ASSERT_LOCK(a_pVM) do { } while (0)
803#endif
804
805/**
806 * Gets the page state.
807 * @returns page state (PGM_PAGE_STATE_*).
808 * @param a_pPage Pointer to the physical guest page tracking structure.
809 *
810 * @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
811 * builds.
812 */
813#define PGM_PAGE_GET_STATE_NA(a_pPage) ( (a_pPage)->s.uStateY )
814#if defined(__GNUC__) && defined(VBOX_STRICT)
815# define PGM_PAGE_GET_STATE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_STATE_NA(a_pPage); })
816#else
817# define PGM_PAGE_GET_STATE PGM_PAGE_GET_STATE_NA
818#endif
819
820/**
821 * Sets the page state.
822 * @param a_pVM The VM handle, only used for lock ownership assertions.
823 * @param a_pPage Pointer to the physical guest page tracking structure.
824 * @param a_uState The new page state.
825 */
826#define PGM_PAGE_SET_STATE(a_pVM, a_pPage, a_uState) \
827 do { (a_pPage)->s.uStateY = (a_uState); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
828
829
830/**
831 * Gets the host physical address of the guest page.
832 * @returns host physical address (RTHCPHYS).
833 * @param a_pPage Pointer to the physical guest page tracking structure.
834 *
835 * @remarks In strict builds on gcc platforms, this macro will make some ugly
836 * assumption about a valid pVM variable/parameter being in the
837 * current context. It will use this pVM variable to assert that the
838 * PGM lock is held. Use the PGM_PAGE_GET_HCPHYS_NA in contexts where
839 * pVM is not around.
840 */
841#if 0
842# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->s.HCPhysFN << 12 )
843# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
844#else
845# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->au64[0] & UINT64_C(0x0000fffffffff000) )
846# if defined(__GNUC__) && defined(VBOX_STRICT)
847# define PGM_PAGE_GET_HCPHYS(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_HCPHYS_NA(a_pPage); })
848# else
849# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
850# endif
851#endif
852
853/**
854 * Sets the host physical address of the guest page.
855 *
856 * @param a_pVM The VM handle, only used for lock ownership assertions.
857 * @param a_pPage Pointer to the physical guest page tracking structure.
858 * @param a_HCPhys The new host physical address.
859 */
860#define PGM_PAGE_SET_HCPHYS(a_pVM, a_pPage, a_HCPhys) \
861 do { \
862 RTHCPHYS const SetHCPhysTmp = (a_HCPhys); \
863 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
864 (a_pPage)->s.HCPhysFN = SetHCPhysTmp >> 12; \
865 PGM_PAGE_ASSERT_LOCK(a_pVM); \
866 } while (0)
867
868/**
869 * Get the Page ID.
870 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
871 * @param a_pPage Pointer to the physical guest page tracking structure.
872 */
873#define PGM_PAGE_GET_PAGEID(a_pPage) ( (uint32_t)(a_pPage)->s.idPage )
874
875/**
876 * Sets the Page ID.
877 * @param a_pVM The VM handle, only used for lock ownership assertions.
878 * @param a_pPage Pointer to the physical guest page tracking structure.
879 * @param a_idPage The new page ID.
880 */
881#define PGM_PAGE_SET_PAGEID(a_pVM, a_pPage, a_idPage) \
882 do { \
883 (a_pPage)->s.idPage = (a_idPage); \
884 PGM_PAGE_ASSERT_LOCK(a_pVM); \
885 } while (0)
886
887/**
888 * Get the Chunk ID.
889 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
890 * @param a_pPage Pointer to the physical guest page tracking structure.
891 */
892#define PGM_PAGE_GET_CHUNKID(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) >> GMM_CHUNKID_SHIFT )
893
894/**
895 * Get the index of the page within the allocation chunk.
896 * @returns The page index.
897 * @param a_pPage Pointer to the physical guest page tracking structure.
898 */
899#define PGM_PAGE_GET_PAGE_IN_CHUNK(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) & GMM_PAGEID_IDX_MASK )
900
901/**
902 * Gets the page type.
903 * @returns The page type.
904 * @param a_pPage Pointer to the physical guest page tracking structure.
905 *
906 * @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
907 * builds.
908 */
909#define PGM_PAGE_GET_TYPE_NA(a_pPage) ( (a_pPage)->s.uTypeY )
910#if defined(__GNUC__) && defined(VBOX_STRICT)
911# define PGM_PAGE_GET_TYPE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TYPE_NA(a_pPage); })
912#else
913# define PGM_PAGE_GET_TYPE PGM_PAGE_GET_TYPE_NA
914#endif
915
916/**
917 * Sets the page type.
918 *
919 * @param a_pVM The VM handle, only used for lock ownership assertions.
920 * @param a_pPage Pointer to the physical guest page tracking structure.
921 * @param a_enmType The new page type (PGMPAGETYPE).
922 */
923#define PGM_PAGE_SET_TYPE(a_pVM, a_pPage, a_enmType) \
924 do { (a_pPage)->s.uTypeY = (a_enmType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
925
926/**
927 * Gets the page table index
928 * @returns The page table index.
929 * @param a_pPage Pointer to the physical guest page tracking structure.
930 */
931#define PGM_PAGE_GET_PTE_INDEX(a_pPage) ( (a_pPage)->s.u10PteIdx )
932
933/**
934 * Sets the page table index.
935 * @param a_pVM The VM handle, only used for lock ownership assertions.
936 * @param a_pPage Pointer to the physical guest page tracking structure.
937 * @param a_iPte New page table index.
938 */
939#define PGM_PAGE_SET_PTE_INDEX(a_pVM, a_pPage, a_iPte) \
940 do { (a_pPage)->s.u10PteIdx = (a_iPte); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
941
942/**
943 * Checks if the page is marked for MMIO, no MMIO2 aliasing.
944 * @returns true/false.
945 * @param a_pPage Pointer to the physical guest page tracking structure.
946 */
947#define PGM_PAGE_IS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO )
948
949/**
950 * Checks if the page is marked for MMIO, including both aliases.
951 * @returns true/false.
952 * @param a_pPage Pointer to the physical guest page tracking structure.
953 */
954#define PGM_PAGE_IS_MMIO_OR_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
955 || (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO2_ALIAS_MMIO \
956 || (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO \
957 )
958
959/**
960 * Checks if the page is marked for MMIO, including special aliases.
961 * @returns true/false.
962 * @param a_pPage Pointer to the physical guest page tracking structure.
963 */
964#define PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
965 || (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
966
967/**
968 * Checks if the page is a special aliased MMIO page.
969 * @returns true/false.
970 * @param a_pPage Pointer to the physical guest page tracking structure.
971 */
972#define PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
973
974/**
975 * Checks if the page is backed by the ZERO page.
976 * @returns true/false.
977 * @param a_pPage Pointer to the physical guest page tracking structure.
978 */
979#define PGM_PAGE_IS_ZERO(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ZERO )
980
981/**
982 * Checks if the page is backed by a SHARED page.
983 * @returns true/false.
984 * @param a_pPage Pointer to the physical guest page tracking structure.
985 */
986#define PGM_PAGE_IS_SHARED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_SHARED )
987
988/**
989 * Checks if the page is ballooned.
990 * @returns true/false.
991 * @param a_pPage Pointer to the physical guest page tracking structure.
992 */
993#define PGM_PAGE_IS_BALLOONED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_BALLOONED )
994
995/**
996 * Checks if the page is allocated.
997 * @returns true/false.
998 * @param a_pPage Pointer to the physical guest page tracking structure.
999 */
1000#define PGM_PAGE_IS_ALLOCATED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ALLOCATED )
1001
1002/**
1003 * Marks the page as written to (for GMM change monitoring).
1004 * @param a_pVM The VM handle, only used for lock ownership assertions.
1005 * @param a_pPage Pointer to the physical guest page tracking structure.
1006 */
1007#define PGM_PAGE_SET_WRITTEN_TO(a_pVM, a_pPage) \
1008 do { (a_pPage)->s.fWrittenToY = 1; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1009
1010/**
1011 * Clears the written-to indicator.
1012 * @param a_pVM The VM handle, only used for lock ownership assertions.
1013 * @param a_pPage Pointer to the physical guest page tracking structure.
1014 */
1015#define PGM_PAGE_CLEAR_WRITTEN_TO(a_pVM, a_pPage) \
1016 do { (a_pPage)->s.fWrittenToY = 0; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1017
1018/**
1019 * Checks if the page was marked as written-to.
1020 * @returns true/false.
1021 * @param a_pPage Pointer to the physical guest page tracking structure.
1022 */
1023#define PGM_PAGE_IS_WRITTEN_TO(a_pPage) ( (a_pPage)->s.fWrittenToY )
1024
1025
1026/** @name PT usage values (PGMPAGE::u2PDEType).
1027 *
1028 * @{ */
1029/** Either as a PT or PDE. */
1030#define PGM_PAGE_PDE_TYPE_DONTCARE 0
1031/** Must use a page table to map the range. */
1032#define PGM_PAGE_PDE_TYPE_PT 1
1033/** Can use a page directory entry to map the continuous range. */
1034#define PGM_PAGE_PDE_TYPE_PDE 2
1035/** Can use a page directory entry to map the continuous range - temporarily disabled (by page monitoring). */
1036#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
1037/** @} */
1038
1039/**
1040 * Set the PDE type of the page
1041 * @param a_pVM The VM handle, only used for lock ownership assertions.
1042 * @param a_pPage Pointer to the physical guest page tracking structure.
1043 * @param a_uType PGM_PAGE_PDE_TYPE_*.
1044 */
1045#define PGM_PAGE_SET_PDE_TYPE(a_pVM, a_pPage, a_uType) \
1046 do { (a_pPage)->s.u2PDETypeY = (a_uType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1047
1048/**
1049 * Checks if the page was marked being part of a large page
1050 * @returns true/false.
1051 * @param a_pPage Pointer to the physical guest page tracking structure.
1052 */
1053#define PGM_PAGE_GET_PDE_TYPE(a_pPage) ( (a_pPage)->s.u2PDETypeY )
1054
1055/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
1056 *
1057 * @remarks The values are assigned in order of priority, so we can calculate
1058 * the correct state for a page with different handlers installed.
1059 * @{ */
1060/** No handler installed. */
1061#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
1062/** Monitoring is temporarily disabled. */
1063#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
1064/** Write access is monitored. */
1065#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
1066/** All access is monitored. */
1067#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
1068/** @} */
1069
1070/**
1071 * Gets the physical access handler state of a page.
1072 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
1073 * @param a_pPage Pointer to the physical guest page tracking structure.
1074 */
1075#define PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) ( (a_pPage)->s.u2HandlerPhysStateY )
1076
1077/**
1078 * Sets the physical access handler state of a page.
1079 * @param a_pPage Pointer to the physical guest page tracking structure.
1080 * @param a_uState The new state value.
1081 */
1082#define PGM_PAGE_SET_HNDL_PHYS_STATE(a_pPage, a_uState) \
1083 do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); } while (0)
1084
1085/**
1086 * Checks if the page has any physical access handlers, including temporarily disabled ones.
1087 * @returns true/false
1088 * @param a_pPage Pointer to the physical guest page tracking structure.
1089 */
1090#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(a_pPage) \
1091 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1092
1093/**
1094 * Checks if the page has any active physical access handlers.
1095 * @returns true/false
1096 * @param a_pPage Pointer to the physical guest page tracking structure.
1097 */
1098#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(a_pPage) \
1099 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1100
1101/**
1102 * Checks if the page has any access handlers, including temporarily disabled ones.
1103 * @returns true/false
1104 * @param a_pPage Pointer to the physical guest page tracking structure.
1105 */
1106#define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1107 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1108
1109/**
1110 * Checks if the page has any active access handlers.
1111 * @returns true/false
1112 * @param a_pPage Pointer to the physical guest page tracking structure.
1113 */
1114#define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1115 (PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1116
1117/**
1118 * Checks if the page has any active access handlers catching all accesses.
1119 * @returns true/false
1120 * @param a_pPage Pointer to the physical guest page tracking structure.
1121 */
1122#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1123 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1124
1125
1126/** @def PGM_PAGE_GET_TRACKING
1127 * Gets the packed shadow page pool tracking data associated with a guest page.
1128 * @returns uint16_t containing the data.
1129 * @param a_pPage Pointer to the physical guest page tracking structure.
1130 */
1131#define PGM_PAGE_GET_TRACKING_NA(a_pPage) ( (a_pPage)->s.u16TrackingY )
1132#if defined(__GNUC__) && defined(VBOX_STRICT)
1133# define PGM_PAGE_GET_TRACKING(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TRACKING_NA(a_pPage); })
1134#else
1135# define PGM_PAGE_GET_TRACKING PGM_PAGE_GET_TRACKING_NA
1136#endif
1137
1138/** @def PGM_PAGE_SET_TRACKING
1139 * Sets the packed shadow page pool tracking data associated with a guest page.
1140 * @param a_pVM The VM handle, only used for lock ownership assertions.
1141 * @param a_pPage Pointer to the physical guest page tracking structure.
1142 * @param a_u16TrackingData The tracking data to store.
1143 */
1144#define PGM_PAGE_SET_TRACKING(a_pVM, a_pPage, a_u16TrackingData) \
1145 do { (a_pPage)->s.u16TrackingY = (a_u16TrackingData); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1146
1147/** @def PGM_PAGE_GET_TD_CREFS
1148 * Gets the @a cRefs tracking data member.
1149 * @returns cRefs.
1150 * @param a_pPage Pointer to the physical guest page tracking structure.
1151 */
1152#define PGM_PAGE_GET_TD_CREFS(a_pPage) \
1153 ((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1154#define PGM_PAGE_GET_TD_CREFS_NA(a_pPage) \
1155 ((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1156
1157/** @def PGM_PAGE_GET_TD_IDX
1158 * Gets the @a idx tracking data member.
1159 * @returns idx.
1160 * @param a_pPage Pointer to the physical guest page tracking structure.
1161 */
1162#define PGM_PAGE_GET_TD_IDX(a_pPage) \
1163 ((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1164#define PGM_PAGE_GET_TD_IDX_NA(a_pPage) \
1165 ((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1166
1167
1168/** Max number of locks on a page. */
1169#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1170
1171/** Get the read lock count.
1172 * @returns count.
1173 * @param a_pPage Pointer to the physical guest page tracking structure.
1174 */
1175#define PGM_PAGE_GET_READ_LOCKS(a_pPage) ( (a_pPage)->s.cReadLocksY )
1176
1177/** Get the write lock count.
1178 * @returns count.
1179 * @param a_pPage Pointer to the physical guest page tracking structure.
1180 */
1181#define PGM_PAGE_GET_WRITE_LOCKS(a_pPage) ( (a_pPage)->s.cWriteLocksY )
1182
1183/** Decrement the read lock counter.
1184 * @param a_pPage Pointer to the physical guest page tracking structure.
1185 */
1186#define PGM_PAGE_DEC_READ_LOCKS(a_pPage) do { --(a_pPage)->s.cReadLocksY; } while (0)
1187
1188/** Decrement the write lock counter.
1189 * @param a_pPage Pointer to the physical guest page tracking structure.
1190 */
1191#define PGM_PAGE_DEC_WRITE_LOCKS(a_pPage) do { --(a_pPage)->s.cWriteLocksY; } while (0)
1192
1193/** Increment the read lock counter.
1194 * @param a_pPage Pointer to the physical guest page tracking structure.
1195 */
1196#define PGM_PAGE_INC_READ_LOCKS(a_pPage) do { ++(a_pPage)->s.cReadLocksY; } while (0)
1197
1198/** Increment the write lock counter.
1199 * @param a_pPage Pointer to the physical guest page tracking structure.
1200 */
1201#define PGM_PAGE_INC_WRITE_LOCKS(a_pPage) do { ++(a_pPage)->s.cWriteLocksY; } while (0)
1202
1203
1204/** Gets the NEM state.
1205 * @returns NEM state value (two bits).
1206 * @param a_pPage Pointer to the physical guest page tracking structure.
1207 */
1208#define PGM_PAGE_GET_NEM_STATE(a_pPage) ((a_pPage)->s.u2NemStateY)
1209
1210/** Sets the NEM state.
1211 * @param a_pPage Pointer to the physical guest page tracking structure.
1212 * @param a_u2State The NEM state value (specific to NEM impl.).
1213 */
1214#define PGM_PAGE_SET_NEM_STATE(a_pPage, a_u2State) \
1215 do { Assert((a_u2State) < 4); (a_pPage)->s.u2NemStateY = (a_u2State); } while (0)
1216
1217
1218#if 0
1219/** Enables sanity checking of write monitoring using CRC-32. */
1220# define PGMLIVESAVERAMPAGE_WITH_CRC32
1221#endif
1222
1223/**
1224 * Per page live save tracking data.
1225 */
1226typedef struct PGMLIVESAVERAMPAGE
1227{
1228 /** Number of times it has been dirtied. */
1229 uint32_t cDirtied : 24;
1230 /** Whether it is currently dirty. */
1231 uint32_t fDirty : 1;
1232 /** Ignore the page.
1233 * This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1234 * deal with these after pausing the VM and DevPCI have said it bit about
1235 * remappings. */
1236 uint32_t fIgnore : 1;
1237 /** Was a ZERO page last time around. */
1238 uint32_t fZero : 1;
1239 /** Was a SHARED page last time around. */
1240 uint32_t fShared : 1;
1241 /** Whether the page is/was write monitored in a previous pass. */
1242 uint32_t fWriteMonitored : 1;
1243 /** Whether the page is/was write monitored earlier in this pass. */
1244 uint32_t fWriteMonitoredJustNow : 1;
1245 /** Bits reserved for future use. */
1246 uint32_t u2Reserved : 2;
1247#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1248 /** CRC-32 for the page. This is for internal consistency checks. */
1249 uint32_t u32Crc;
1250#endif
1251} PGMLIVESAVERAMPAGE;
1252#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1253AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1254#else
1255AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1256#endif
1257/** Pointer to the per page live save tracking data. */
1258typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1259
1260/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1261#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1262
1263
1264/**
1265 * RAM range for GC Phys to HC Phys conversion.
1266 *
1267 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1268 * conversions too, but we'll let MM handle that for now.
1269 *
1270 * This structure is used by linked lists in both GC and HC.
1271 */
1272typedef struct PGMRAMRANGE
1273{
1274 /** Start of the range. Page aligned. */
1275 RTGCPHYS GCPhys;
1276 /** Size of the range. (Page aligned of course). */
1277 RTGCPHYS cb;
1278 /** Pointer to the next RAM range - for R3. */
1279 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1280 /** Pointer to the next RAM range - for R0. */
1281 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1282 /** PGM_RAM_RANGE_FLAGS_* flags. */
1283 uint32_t fFlags;
1284 uint32_t fPadding1;
1285 /** Last address in the range (inclusive). Page aligned (-1). */
1286 RTGCPHYS GCPhysLast;
1287 /** Start of the HC mapping of the range. This is only used for MMIO2. */
1288 R3PTRTYPE(void *) pvR3;
1289 /** Live save per page tracking data. */
1290 R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1291 /** The range description. */
1292 R3PTRTYPE(const char *) pszDesc;
1293 /** Pointer to self - R0 pointer. */
1294 R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1295
1296 /** Pointer to the left search three node - ring-3 context. */
1297 R3PTRTYPE(struct PGMRAMRANGE *) pLeftR3;
1298 /** Pointer to the right search three node - ring-3 context. */
1299 R3PTRTYPE(struct PGMRAMRANGE *) pRightR3;
1300 /** Pointer to the left search three node - ring-0 context. */
1301 R0PTRTYPE(struct PGMRAMRANGE *) pLeftR0;
1302 /** Pointer to the right search three node - ring-0 context. */
1303 R0PTRTYPE(struct PGMRAMRANGE *) pRightR0;
1304
1305 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1306#if HC_ARCH_BITS == 32
1307 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 0];
1308#endif
1309 /** Array of physical guest page tracking structures. */
1310 PGMPAGE aPages[1];
1311} PGMRAMRANGE;
1312/** Pointer to RAM range for GC Phys to HC Phys conversion. */
1313typedef PGMRAMRANGE *PPGMRAMRANGE;
1314
1315/** @name PGMRAMRANGE::fFlags
1316 * @{ */
1317/** The RAM range is floating around as an independent guest mapping. */
1318#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1319/** Ad hoc RAM range for an ROM mapping. */
1320#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1321/** Ad hoc RAM range for an MMIO mapping. */
1322#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1323/** Ad hoc RAM range for an MMIO2 or pre-registered MMIO mapping. */
1324#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX RT_BIT(23)
1325/** @} */
1326
1327/** Tests if a RAM range is an ad hoc one or not.
1328 * @returns true/false.
1329 * @param pRam The RAM range.
1330 */
1331#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1332 (!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX) ) )
1333
1334/** The number of entries in the RAM range TLBs (there is one for each
1335 * context). Must be a power of two. */
1336#define PGM_RAMRANGE_TLB_ENTRIES 8
1337
1338/**
1339 * Calculates the RAM range TLB index for the physical address.
1340 *
1341 * @returns RAM range TLB index.
1342 * @param a_GCPhys The guest physical address.
1343 */
1344#define PGM_RAMRANGE_TLB_IDX(a_GCPhys) ( ((a_GCPhys) >> 20) & (PGM_RAMRANGE_TLB_ENTRIES - 1) )
1345
1346
1347
1348/**
1349 * Per page tracking structure for ROM image.
1350 *
1351 * A ROM image may have a shadow page, in which case we may have two pages
1352 * backing it. This structure contains the PGMPAGE for both while
1353 * PGMRAMRANGE have a copy of the active one. It is important that these
1354 * aren't out of sync in any regard other than page pool tracking data.
1355 */
1356typedef struct PGMROMPAGE
1357{
1358 /** The page structure for the virgin ROM page. */
1359 PGMPAGE Virgin;
1360 /** The page structure for the shadow RAM page. */
1361 PGMPAGE Shadow;
1362 /** The current protection setting. */
1363 PGMROMPROT enmProt;
1364 /** Live save status information. Makes use of unused alignment space. */
1365 struct
1366 {
1367 /** The previous protection value. */
1368 uint8_t u8Prot;
1369 /** Written to flag set by the handler. */
1370 bool fWrittenTo;
1371 /** Whether the shadow page is dirty or not. */
1372 bool fDirty;
1373 /** Whether it was dirtied in the recently. */
1374 bool fDirtiedRecently;
1375 } LiveSave;
1376} PGMROMPAGE;
1377AssertCompileSizeAlignment(PGMROMPAGE, 8);
1378/** Pointer to a ROM page tracking structure. */
1379typedef PGMROMPAGE *PPGMROMPAGE;
1380
1381
1382/**
1383 * A registered ROM image.
1384 *
1385 * This is needed to keep track of ROM image since they generally intrude
1386 * into a PGMRAMRANGE. It also keeps track of additional info like the
1387 * two page sets (read-only virgin and read-write shadow), the current
1388 * state of each page.
1389 *
1390 * Because access handlers cannot easily be executed in a different
1391 * context, the ROM ranges needs to be accessible and in all contexts.
1392 */
1393typedef struct PGMROMRANGE
1394{
1395 /** Pointer to the next range - R3. */
1396 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1397 /** Pointer to the next range - R0. */
1398 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1399 /** Address of the range. */
1400 RTGCPHYS GCPhys;
1401 /** Address of the last byte in the range. */
1402 RTGCPHYS GCPhysLast;
1403 /** Size of the range. */
1404 RTGCPHYS cb;
1405 /** The flags (PGMPHYS_ROM_FLAGS_*). */
1406 uint32_t fFlags;
1407 /** The saved state range ID. */
1408 uint8_t idSavedState;
1409 /** Alignment padding. */
1410 uint8_t au8Alignment[3];
1411 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1412 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 5 : 1];
1413 /** The size bits pvOriginal points to. */
1414 uint32_t cbOriginal;
1415 /** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1416 * This is used for strictness checks. */
1417 R3PTRTYPE(const void *) pvOriginal;
1418 /** The ROM description. */
1419 R3PTRTYPE(const char *) pszDesc;
1420 /** The per page tracking structures. */
1421 PGMROMPAGE aPages[1];
1422} PGMROMRANGE;
1423/** Pointer to a ROM range. */
1424typedef PGMROMRANGE *PPGMROMRANGE;
1425
1426
1427/**
1428 * Live save per page data for an MMIO2 page.
1429 *
1430 * Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1431 * of MMIO2 pages. The current approach is using some optimistic SHA-1 +
1432 * CRC-32 for detecting changes as well as special handling of zero pages. This
1433 * is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1434 * for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1435 * because of speed (2.5x and 6x slower).)
1436 *
1437 * @todo Implement dirty MMIO2 page reporting that can be enabled during live
1438 * save but normally is disabled. Since we can write monitor guest
1439 * accesses on our own, we only need this for host accesses. Shouldn't be
1440 * too difficult for DevVGA, VMMDev might be doable, the planned
1441 * networking fun will be fun since it involves ring-0.
1442 */
1443typedef struct PGMLIVESAVEMMIO2PAGE
1444{
1445 /** Set if the page is considered dirty. */
1446 bool fDirty;
1447 /** The number of scans this page has remained unchanged for.
1448 * Only updated for dirty pages. */
1449 uint8_t cUnchangedScans;
1450 /** Whether this page was zero at the last scan. */
1451 bool fZero;
1452 /** Alignment padding. */
1453 bool fReserved;
1454 /** CRC-32 for the first half of the page.
1455 * This is used together with u32CrcH2 to quickly detect changes in the page
1456 * during the non-final passes. */
1457 uint32_t u32CrcH1;
1458 /** CRC-32 for the second half of the page. */
1459 uint32_t u32CrcH2;
1460 /** SHA-1 for the saved page.
1461 * This is used in the final pass to skip pages without changes. */
1462 uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1463} PGMLIVESAVEMMIO2PAGE;
1464/** Pointer to a live save status data for an MMIO2 page. */
1465typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1466
1467/**
1468 * A registered MMIO2 (= Device RAM) range.
1469 *
1470 * There are a few reason why we need to keep track of these registrations. One
1471 * of them is the deregistration & cleanup stuff, while another is that the
1472 * PGMRAMRANGE associated with such a region may have to be removed from the ram
1473 * range list.
1474 *
1475 * Overlapping with a RAM range has to be 100% or none at all. The pages in the
1476 * existing RAM range must not be ROM nor MMIO. A guru meditation will be
1477 * raised if a partial overlap or an overlap of ROM pages is encountered. On an
1478 * overlap we will free all the existing RAM pages and put in the ram range
1479 * pages instead.
1480 */
1481typedef struct PGMREGMMIO2RANGE
1482{
1483 /** The owner of the range. (a device) */
1484 PPDMDEVINSR3 pDevInsR3;
1485 /** Pointer to the ring-3 mapping of the allocation. */
1486 RTR3PTR pvR3;
1487#if defined(VBOX_WITH_RAM_IN_KERNEL) && !defined(VBOX_WITH_LINEAR_HOST_PHYS_MEM)
1488 /** Pointer to the ring-0 mapping of the allocation. */
1489 RTR0PTR pvR0;
1490#endif
1491 /** Pointer to the next range - R3. */
1492 R3PTRTYPE(struct PGMREGMMIO2RANGE *) pNextR3;
1493 /** Flags (PGMREGMMIO2RANGE_F_XXX). */
1494 uint16_t fFlags;
1495 /** The sub device number (internal PCI config (CFGM) number). */
1496 uint8_t iSubDev;
1497 /** The PCI region number. */
1498 uint8_t iRegion;
1499 /** The saved state range ID. */
1500 uint8_t idSavedState;
1501 /** MMIO2 range identifier, for page IDs (PGMPAGE::s.idPage). */
1502 uint8_t idMmio2;
1503 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundary. */
1504#if defined(VBOX_WITH_RAM_IN_KERNEL) && !defined(VBOX_WITH_LINEAR_HOST_PHYS_MEM)
1505 uint8_t abAlignment[HC_ARCH_BITS == 32 ? 6 + 4 : 2];
1506#else
1507 uint8_t abAlignment[HC_ARCH_BITS == 32 ? 6 + 8 : 2 + 8];
1508#endif
1509 /** The real size.
1510 * This may be larger than indicated by RamRange.cb if the range has been
1511 * reduced during saved state loading. */
1512 RTGCPHYS cbReal;
1513 /** Pointer to the physical handler for MMIO. */
1514 R3PTRTYPE(PPGMPHYSHANDLER) pPhysHandlerR3;
1515 /** Live save per page tracking data for MMIO2. */
1516 R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1517 /** The associated RAM range. */
1518 PGMRAMRANGE RamRange;
1519} PGMREGMMIO2RANGE;
1520AssertCompileMemberAlignment(PGMREGMMIO2RANGE, RamRange, 16);
1521/** Pointer to a MMIO2 or pre-registered MMIO range. */
1522typedef PGMREGMMIO2RANGE *PPGMREGMMIO2RANGE;
1523
1524/** @name PGMREGMMIO2RANGE_F_XXX - Registered MMIO2 range flags.
1525 * @{ */
1526/** Set if it's an MMIO2 range.
1527 * @note Historical. For a while we did some of the MMIO this way too. */
1528#define PGMREGMMIO2RANGE_F_MMIO2 UINT16_C(0x0001)
1529/** Set if this is the first chunk in the MMIO2 range. */
1530#define PGMREGMMIO2RANGE_F_FIRST_CHUNK UINT16_C(0x0002)
1531/** Set if this is the last chunk in the MMIO2 range. */
1532#define PGMREGMMIO2RANGE_F_LAST_CHUNK UINT16_C(0x0004)
1533/** Set if the whole range is mapped. */
1534#define PGMREGMMIO2RANGE_F_MAPPED UINT16_C(0x0008)
1535/** Set if it's overlapping, clear if not. */
1536#define PGMREGMMIO2RANGE_F_OVERLAPPING UINT16_C(0x0010)
1537/** @} */
1538
1539
1540/** @name Internal MMIO2 constants.
1541 * @{ */
1542/** The maximum number of MMIO2 ranges. */
1543#define PGM_MMIO2_MAX_RANGES 32
1544/** The maximum number of pages in a MMIO2 range. */
1545#define PGM_MMIO2_MAX_PAGE_COUNT UINT32_C(0x01000000)
1546/** Makes a MMIO2 page ID out of a MMIO2 range ID and page index number. */
1547#define PGM_MMIO2_PAGEID_MAKE(a_idMmio2, a_iPage) ( ((uint32_t)(a_idMmio2) << 24) | (uint32_t)(a_iPage) )
1548/** Gets the MMIO2 range ID from an MMIO2 page ID. */
1549#define PGM_MMIO2_PAGEID_GET_MMIO2_ID(a_idPage) ( (uint8_t)((a_idPage) >> 24) )
1550/** Gets the MMIO2 page index from an MMIO2 page ID. */
1551#define PGM_MMIO2_PAGEID_GET_IDX(a_idPage) ( ((a_idPage) & UINT32_C(0x00ffffff)) )
1552/** @} */
1553
1554
1555
1556/**
1557 * PGMPhysRead/Write cache entry
1558 */
1559typedef struct PGMPHYSCACHEENTRY
1560{
1561 /** R3 pointer to physical page. */
1562 R3PTRTYPE(uint8_t *) pbR3;
1563 /** GC Physical address for cache entry */
1564 RTGCPHYS GCPhys;
1565#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1566 RTGCPHYS u32Padding0; /**< alignment padding. */
1567#endif
1568} PGMPHYSCACHEENTRY;
1569
1570/**
1571 * PGMPhysRead/Write cache to reduce REM memory access overhead
1572 */
1573typedef struct PGMPHYSCACHE
1574{
1575 /** Bitmap of valid cache entries */
1576 uint64_t aEntries;
1577 /** Cache entries */
1578 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1579} PGMPHYSCACHE;
1580
1581
1582/** @name Ring-3 page mapping TLBs
1583 * @{ */
1584
1585/** Pointer to an allocation chunk ring-3 mapping. */
1586typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1587/** Pointer to an allocation chunk ring-3 mapping pointer. */
1588typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1589
1590/**
1591 * Ring-3 tracking structure for an allocation chunk ring-3 mapping.
1592 *
1593 * The primary tree (Core) uses the chunk id as key.
1594 */
1595typedef struct PGMCHUNKR3MAP
1596{
1597 /** The key is the chunk id. */
1598 AVLU32NODECORE Core;
1599 /** The time (ChunkR3Map.iNow) this chunk was last used. Used for unmap
1600 * selection. */
1601 uint32_t iLastUsed;
1602 /** The current reference count. */
1603 uint32_t volatile cRefs;
1604 /** The current permanent reference count. */
1605 uint32_t volatile cPermRefs;
1606 /** The mapping address. */
1607 void *pv;
1608} PGMCHUNKR3MAP;
1609
1610/**
1611 * Allocation chunk ring-3 mapping TLB entry.
1612 */
1613typedef struct PGMCHUNKR3MAPTLBE
1614{
1615 /** The chunk id. */
1616 uint32_t volatile idChunk;
1617#if HC_ARCH_BITS == 64
1618 uint32_t u32Padding; /**< alignment padding. */
1619#endif
1620 /** The chunk map. */
1621#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) || defined(VBOX_WITH_RAM_IN_KERNEL)
1622 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1623#else
1624 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1625#endif
1626} PGMCHUNKR3MAPTLBE;
1627/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1628typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1629
1630/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1631 * @remark Must be a power of two value. */
1632#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1633
1634/**
1635 * Allocation chunk ring-3 mapping TLB.
1636 *
1637 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1638 * At first glance this might look kinda odd since AVL trees are
1639 * supposed to give the most optimal lookup times of all trees
1640 * due to their balancing. However, take a tree with 1023 nodes
1641 * in it, that's 10 levels, meaning that most searches has to go
1642 * down 9 levels before they find what they want. This isn't fast
1643 * compared to a TLB hit. There is the factor of cache misses,
1644 * and of course the problem with trees and branch prediction.
1645 * This is why we use TLBs in front of most of the trees.
1646 *
1647 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1648 * difficult when we switch to the new inlined AVL trees (from kStuff).
1649 */
1650typedef struct PGMCHUNKR3MAPTLB
1651{
1652 /** The TLB entries. */
1653 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1654} PGMCHUNKR3MAPTLB;
1655
1656/**
1657 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1658 * @returns Chunk TLB index.
1659 * @param idChunk The Chunk ID.
1660 */
1661#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1662
1663
1664/**
1665 * Ring-3 guest page mapping TLB entry.
1666 * @remarks used in ring-0 as well at the moment.
1667 */
1668typedef struct PGMPAGER3MAPTLBE
1669{
1670 /** Address of the page. */
1671 RTGCPHYS volatile GCPhys;
1672 /** The guest page. */
1673#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) || defined(VBOX_WITH_RAM_IN_KERNEL)
1674 R3PTRTYPE(PPGMPAGE) volatile pPage;
1675#else
1676 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1677#endif
1678 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1679#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) || defined(VBOX_WITH_RAM_IN_KERNEL)
1680 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1681#else
1682 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1683#endif
1684 /** The address */
1685#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) || defined(VBOX_WITH_RAM_IN_KERNEL)
1686 R3PTRTYPE(void *) volatile pv;
1687#else
1688 R3R0PTRTYPE(void *) volatile pv;
1689#endif
1690#if HC_ARCH_BITS == 32
1691 uint32_t u32Padding; /**< alignment padding. */
1692#endif
1693} PGMPAGER3MAPTLBE;
1694/** Pointer to an entry in the HC physical TLB. */
1695typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1696
1697
1698/** The number of entries in the ring-3 guest page mapping TLB.
1699 * @remarks The value must be a power of two. */
1700#define PGM_PAGER3MAPTLB_ENTRIES 256
1701
1702/**
1703 * Ring-3 guest page mapping TLB.
1704 * @remarks used in ring-0 as well at the moment.
1705 */
1706typedef struct PGMPAGER3MAPTLB
1707{
1708 /** The TLB entries. */
1709 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1710} PGMPAGER3MAPTLB;
1711/** Pointer to the ring-3 guest page mapping TLB. */
1712typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1713
1714/**
1715 * Calculates the index of the TLB entry for the specified guest page.
1716 * @returns Physical TLB index.
1717 * @param GCPhys The guest physical address.
1718 */
1719#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1720
1721/** @} */
1722
1723#if defined(VBOX_WITH_RAM_IN_KERNEL) || defined(DOXYGEN_RUNNING)
1724/** @name Ring-0 page mapping TLB
1725 * @{ */
1726/**
1727 * Ring-0 guest page mapping TLB entry.
1728 */
1729typedef struct PGMPAGER0MAPTLBE
1730{
1731 /** Address of the page. */
1732 RTGCPHYS volatile GCPhys;
1733 /** The guest page. */
1734 R0PTRTYPE(PPGMPAGE) volatile pPage;
1735 /** The address */
1736 R0PTRTYPE(void *) volatile pv;
1737} PGMPAGER0MAPTLBE;
1738/** Pointer to an entry in the HC physical TLB. */
1739typedef PGMPAGER0MAPTLBE *PPGMPAGER0MAPTLBE;
1740
1741
1742/** The number of entries in the ring-3 guest page mapping TLB.
1743 * @remarks The value must be a power of two. */
1744#define PGM_PAGER0MAPTLB_ENTRIES 256
1745
1746/**
1747 * Ring-3 guest page mapping TLB.
1748 * @remarks used in ring-0 as well at the moment.
1749 */
1750typedef struct PGMPAGER0MAPTLB
1751{
1752 /** The TLB entries. */
1753 PGMPAGER0MAPTLBE aEntries[PGM_PAGER0MAPTLB_ENTRIES];
1754} PGMPAGER0MAPTLB;
1755/** Pointer to the ring-3 guest page mapping TLB. */
1756typedef PGMPAGER0MAPTLB *PPGMPAGER0MAPTLB;
1757
1758/**
1759 * Calculates the index of the TLB entry for the specified guest page.
1760 * @returns Physical TLB index.
1761 * @param GCPhys The guest physical address.
1762 */
1763#define PGM_PAGER0MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER0MAPTLB_ENTRIES - 1) )
1764/** @} */
1765#endif /* VBOX_WITH_RAM_IN_KERNEL || DOXYGEN_RUNNING */
1766
1767/**
1768 * Raw-mode context dynamic mapping cache entry.
1769 *
1770 * Because of raw-mode context being reloctable and all relocations are applied
1771 * in ring-3, this has to be defined here and be RC specific.
1772 *
1773 * @sa PGMRZDYNMAPENTRY, PGMR0DYNMAPENTRY.
1774 */
1775typedef struct PGMRCDYNMAPENTRY
1776{
1777 /** The physical address of the currently mapped page.
1778 * This is duplicate for three reasons: cache locality, cache policy of the PT
1779 * mappings and sanity checks. */
1780 RTHCPHYS HCPhys;
1781 /** Pointer to the page. */
1782 RTRCPTR pvPage;
1783 /** The number of references. */
1784 int32_t volatile cRefs;
1785 /** PTE pointer union. */
1786 struct PGMRCDYNMAPENTRY_PPTE
1787 {
1788 /** PTE pointer, 32-bit legacy version. */
1789 RCPTRTYPE(PX86PTE) pLegacy;
1790 /** PTE pointer, PAE version. */
1791 RCPTRTYPE(PX86PTEPAE) pPae;
1792 } uPte;
1793} PGMRCDYNMAPENTRY;
1794/** Pointer to a dynamic mapping cache entry for the raw-mode context. */
1795typedef PGMRCDYNMAPENTRY *PPGMRCDYNMAPENTRY;
1796
1797
1798/**
1799 * Dynamic mapping cache for the raw-mode context.
1800 *
1801 * This is initialized during VMMRC init based upon the pbDynPageMapBaseGC and
1802 * paDynPageMap* PGM members. However, it has to be defined in PGMInternal.h
1803 * so that we can perform relocations from PGMR3Relocate. This has the
1804 * consequence that we must have separate ring-0 and raw-mode context versions
1805 * of this struct even if they share the basic elements.
1806 *
1807 * @sa PPGMRZDYNMAP, PGMR0DYNMAP.
1808 */
1809typedef struct PGMRCDYNMAP
1810{
1811 /** The usual magic number / eye catcher (PGMRZDYNMAP_MAGIC). */
1812 uint32_t u32Magic;
1813 /** Array for tracking and managing the pages. */
1814 RCPTRTYPE(PPGMRCDYNMAPENTRY) paPages;
1815 /** The cache size given as a number of pages. */
1816 uint32_t cPages;
1817 /** The current load.
1818 * This does not include guard pages. */
1819 uint32_t cLoad;
1820 /** The max load ever.
1821 * This is maintained to get trigger adding of more mapping space. */
1822 uint32_t cMaxLoad;
1823 /** The number of guard pages. */
1824 uint32_t cGuardPages;
1825 /** The number of users (protected by hInitLock). */
1826 uint32_t cUsers;
1827} PGMRCDYNMAP;
1828/** Pointer to the dynamic cache for the raw-mode context. */
1829typedef PGMRCDYNMAP *PPGMRCDYNMAP;
1830
1831
1832/**
1833 * Mapping cache usage set entry.
1834 *
1835 * @remarks 16-bit ints was chosen as the set is not expected to be used beyond
1836 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1837 * cache. If it's extended to include ring-3, well, then something
1838 * will have be changed here...
1839 */
1840typedef struct PGMMAPSETENTRY
1841{
1842 /** Pointer to the page. */
1843 RTR0PTR pvPage;
1844 /** The mapping cache index. */
1845 uint16_t iPage;
1846 /** The number of references.
1847 * The max is UINT16_MAX - 1. */
1848 uint16_t cRefs;
1849 /** The number inlined references.
1850 * The max is UINT16_MAX - 1. */
1851 uint16_t cInlinedRefs;
1852 /** Unreferences. */
1853 uint16_t cUnrefs;
1854
1855#if HC_ARCH_BITS == 32
1856 uint32_t u32Alignment1;
1857#endif
1858 /** The physical address for this entry. */
1859 RTHCPHYS HCPhys;
1860} PGMMAPSETENTRY;
1861AssertCompileMemberOffset(PGMMAPSETENTRY, iPage, RT_MAX(sizeof(RTR0PTR), sizeof(RTRCPTR)));
1862AssertCompileMemberAlignment(PGMMAPSETENTRY, HCPhys, sizeof(RTHCPHYS));
1863/** Pointer to a mapping cache usage set entry. */
1864typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1865
1866/**
1867 * Mapping cache usage set.
1868 *
1869 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1870 * done during exits / traps. The set is
1871 */
1872typedef struct PGMMAPSET
1873{
1874 /** The number of occupied entries.
1875 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1876 * dynamic mappings. */
1877 uint32_t cEntries;
1878 /** The start of the current subset.
1879 * This is UINT32_MAX if no subset is currently open. */
1880 uint32_t iSubset;
1881 /** The index of the current CPU, only valid if the set is open. */
1882 int32_t iCpu;
1883 uint32_t alignment;
1884 /** The entries. */
1885 PGMMAPSETENTRY aEntries[64];
1886 /** HCPhys -> iEntry fast lookup table.
1887 * Use PGMMAPSET_HASH for hashing.
1888 * The entries may or may not be valid, check against cEntries. */
1889 uint8_t aiHashTable[128];
1890} PGMMAPSET;
1891AssertCompileSizeAlignment(PGMMAPSET, 8);
1892/** Pointer to the mapping cache set. */
1893typedef PGMMAPSET *PPGMMAPSET;
1894
1895/** PGMMAPSET::cEntries value for a closed set. */
1896#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1897
1898/** Hash function for aiHashTable. */
1899#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1900
1901
1902/** @name Context neutral page mapper TLB.
1903 *
1904 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1905 * code is writting in a kind of context neutral way. Time will show whether
1906 * this actually makes sense or not...
1907 *
1908 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1909 * context ends up using a global mapping cache on some platforms
1910 * (darwin).
1911 *
1912 * @{ */
1913/** @typedef PPGMPAGEMAPTLB
1914 * The page mapper TLB pointer type for the current context. */
1915/** @typedef PPGMPAGEMAPTLB
1916 * The page mapper TLB entry pointer type for the current context. */
1917/** @typedef PPGMPAGEMAPTLB
1918 * The page mapper TLB entry pointer pointer type for the current context. */
1919/** @def PGM_PAGEMAPTLB_ENTRIES
1920 * The number of TLB entries in the page mapper TLB for the current context. */
1921/** @def PGM_PAGEMAPTLB_IDX
1922 * Calculate the TLB index for a guest physical address.
1923 * @returns The TLB index.
1924 * @param GCPhys The guest physical address. */
1925/** @typedef PPGMPAGEMAP
1926 * Pointer to a page mapper unit for current context. */
1927/** @typedef PPPGMPAGEMAP
1928 * Pointer to a page mapper unit pointer for current context. */
1929#if defined(IN_RING0) && defined(VBOX_WITH_RAM_IN_KERNEL)
1930typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1931typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1932typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1933# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1934# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1935typedef struct PGMCHUNKR0MAP *PPGMPAGEMAP;
1936typedef struct PGMCHUNKR0MAP **PPPGMPAGEMAP;
1937#else
1938typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1939typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1940typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1941# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1942# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1943typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1944typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1945#endif
1946/** @} */
1947
1948
1949/** @name PGM Pool Indexes.
1950 * Aka. the unique shadow page identifier.
1951 * @{ */
1952/** NIL page pool IDX. */
1953#define NIL_PGMPOOL_IDX 0
1954/** The first normal index. There used to be 5 fictive pages up front, now
1955 * there is only the NIL page. */
1956#define PGMPOOL_IDX_FIRST 1
1957/** The last valid index. (inclusive, 14 bits) */
1958#define PGMPOOL_IDX_LAST 0x3fff
1959/** @} */
1960
1961/** The NIL index for the parent chain. */
1962#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1963#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1964
1965/**
1966 * Node in the chain linking a shadowed page to it's parent (user).
1967 */
1968#pragma pack(1)
1969typedef struct PGMPOOLUSER
1970{
1971 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1972 uint16_t iNext;
1973 /** The user page index. */
1974 uint16_t iUser;
1975 /** Index into the user table. */
1976 uint32_t iUserTable;
1977} PGMPOOLUSER, *PPGMPOOLUSER;
1978typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1979#pragma pack()
1980
1981
1982/** The NIL index for the phys ext chain. */
1983#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1984/** The NIL pte index for a phys ext chain slot. */
1985#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
1986
1987/**
1988 * Node in the chain of physical cross reference extents.
1989 * @todo Calling this an 'extent' is not quite right, find a better name.
1990 * @todo find out the optimal size of the aidx array
1991 */
1992#pragma pack(1)
1993typedef struct PGMPOOLPHYSEXT
1994{
1995 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1996 uint16_t iNext;
1997 /** Alignment. */
1998 uint16_t u16Align;
1999 /** The user page index. */
2000 uint16_t aidx[3];
2001 /** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
2002 uint16_t apte[3];
2003} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
2004typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
2005#pragma pack()
2006
2007
2008/**
2009 * The kind of page that's being shadowed.
2010 */
2011typedef enum PGMPOOLKIND
2012{
2013 /** The virtual invalid 0 entry. */
2014 PGMPOOLKIND_INVALID = 0,
2015 /** The entry is free (=unused). */
2016 PGMPOOLKIND_FREE,
2017
2018 /** Shw: 32-bit page table; Gst: no paging. */
2019 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
2020 /** Shw: 32-bit page table; Gst: 32-bit page table. */
2021 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
2022 /** Shw: 32-bit page table; Gst: 4MB page. */
2023 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
2024 /** Shw: PAE page table; Gst: no paging. */
2025 PGMPOOLKIND_PAE_PT_FOR_PHYS,
2026 /** Shw: PAE page table; Gst: 32-bit page table. */
2027 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
2028 /** Shw: PAE page table; Gst: Half of a 4MB page. */
2029 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
2030 /** Shw: PAE page table; Gst: PAE page table. */
2031 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
2032 /** Shw: PAE page table; Gst: 2MB page. */
2033 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
2034
2035 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
2036 PGMPOOLKIND_32BIT_PD,
2037 /** Shw: 32-bit page directory. Gst: no paging. */
2038 PGMPOOLKIND_32BIT_PD_PHYS,
2039 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
2040 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
2041 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
2042 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
2043 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
2044 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
2045 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
2046 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
2047 /** Shw: PAE page directory; Gst: PAE page directory. */
2048 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
2049 /** Shw: PAE page directory; Gst: no paging. Note: +NP. */
2050 PGMPOOLKIND_PAE_PD_PHYS,
2051
2052 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
2053 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
2054 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
2055 PGMPOOLKIND_PAE_PDPT,
2056 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
2057 PGMPOOLKIND_PAE_PDPT_PHYS,
2058
2059 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
2060 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
2061 /** Shw: 64-bit page directory pointer table; Gst: no paging. */
2062 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
2063 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
2064 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
2065 /** Shw: 64-bit page directory table; Gst: no paging. */
2066 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 24 */
2067
2068 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
2069 PGMPOOLKIND_64BIT_PML4,
2070
2071 /** Shw: EPT page directory pointer table; Gst: no paging. */
2072 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
2073 /** Shw: EPT page directory table; Gst: no paging. */
2074 PGMPOOLKIND_EPT_PD_FOR_PHYS,
2075 /** Shw: EPT page table; Gst: no paging. */
2076 PGMPOOLKIND_EPT_PT_FOR_PHYS,
2077
2078 /** Shw: Root Nested paging table. */
2079 PGMPOOLKIND_ROOT_NESTED,
2080
2081 /** The last valid entry. */
2082 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
2083} PGMPOOLKIND;
2084
2085/**
2086 * The access attributes of the page; only applies to big pages.
2087 */
2088typedef enum
2089{
2090 PGMPOOLACCESS_DONTCARE = 0,
2091 PGMPOOLACCESS_USER_RW,
2092 PGMPOOLACCESS_USER_R,
2093 PGMPOOLACCESS_USER_RW_NX,
2094 PGMPOOLACCESS_USER_R_NX,
2095 PGMPOOLACCESS_SUPERVISOR_RW,
2096 PGMPOOLACCESS_SUPERVISOR_R,
2097 PGMPOOLACCESS_SUPERVISOR_RW_NX,
2098 PGMPOOLACCESS_SUPERVISOR_R_NX
2099} PGMPOOLACCESS;
2100
2101/**
2102 * The tracking data for a page in the pool.
2103 */
2104typedef struct PGMPOOLPAGE
2105{
2106 /** AVL node code with the (HC) physical address of this page. */
2107 AVLOHCPHYSNODECORE Core;
2108 /** Pointer to the R3 mapping of the page. */
2109 R3PTRTYPE(void *) pvPageR3;
2110 /** Pointer to the R0 mapping of the page. */
2111 R0PTRTYPE(void *) pvPageR0;
2112 /** The guest physical address. */
2113 RTGCPHYS GCPhys;
2114 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
2115 uint8_t enmKind;
2116 /** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
2117 uint8_t enmAccess;
2118 /** This supplements enmKind and enmAccess */
2119 bool fA20Enabled : 1;
2120
2121 /** Used to indicate that the page is zeroed. */
2122 bool fZeroed : 1;
2123 /** Used to indicate that a PT has non-global entries. */
2124 bool fSeenNonGlobal : 1;
2125 /** Used to indicate that we're monitoring writes to the guest page. */
2126 bool fMonitored : 1;
2127 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
2128 * (All pages are in the age list.) */
2129 bool fCached : 1;
2130 /** This is used by the R3 access handlers when invoked by an async thread.
2131 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
2132 bool volatile fReusedFlushPending : 1;
2133 /** Used to mark the page as dirty (write monitoring is temporarily
2134 * off). */
2135 bool fDirty : 1;
2136 bool fPadding1 : 1;
2137 bool fPadding2;
2138
2139 /** The index of this page. */
2140 uint16_t idx;
2141 /** The next entry in the list this page currently resides in.
2142 * It's either in the free list or in the GCPhys hash. */
2143 uint16_t iNext;
2144 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
2145 uint16_t iUserHead;
2146 /** The number of present entries. */
2147 uint16_t cPresent;
2148 /** The first entry in the table which is present. */
2149 uint16_t iFirstPresent;
2150 /** The number of modifications to the monitored page. */
2151 uint16_t cModifications;
2152 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
2153 uint16_t iModifiedNext;
2154 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
2155 uint16_t iModifiedPrev;
2156 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
2157 uint16_t iMonitoredNext;
2158 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
2159 uint16_t iMonitoredPrev;
2160 /** The next page in the age list. */
2161 uint16_t iAgeNext;
2162 /** The previous page in the age list. */
2163 uint16_t iAgePrev;
2164 /** Index into PGMPOOL::aDirtyPages if fDirty is set. */
2165 uint8_t idxDirtyEntry;
2166
2167 /** @name Access handler statistics to determine whether the guest is
2168 * (re)initializing a page table.
2169 * @{ */
2170 RTGCPTR GCPtrLastAccessHandlerRip;
2171 RTGCPTR GCPtrLastAccessHandlerFault;
2172 uint64_t cLastAccessHandler;
2173 /** @} */
2174 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages. */
2175 uint32_t volatile cLocked;
2176#if GC_ARCH_BITS == 64
2177 uint32_t u32Alignment3;
2178#endif
2179# ifdef VBOX_STRICT
2180 RTGCPTR GCPtrDirtyFault;
2181# endif
2182} PGMPOOLPAGE;
2183/** Pointer to a pool page. */
2184typedef PGMPOOLPAGE *PPGMPOOLPAGE;
2185/** Pointer to a const pool page. */
2186typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2187/** Pointer to a pool page pointer. */
2188typedef PGMPOOLPAGE **PPPGMPOOLPAGE;
2189
2190
2191/** The hash table size. */
2192# define PGMPOOL_HASH_SIZE 0x40
2193/** The hash function. */
2194# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2195
2196
2197/**
2198 * The shadow page pool instance data.
2199 *
2200 * It's all one big allocation made at init time, except for the
2201 * pages that is. The user nodes follows immediately after the
2202 * page structures.
2203 */
2204typedef struct PGMPOOL
2205{
2206 /** The VM handle - R3 Ptr. */
2207 PVMR3 pVMR3;
2208 /** The VM handle - R0 Ptr. */
2209 R0PTRTYPE(PVMCC) pVMR0;
2210 /** The max pool size. This includes the special IDs. */
2211 uint16_t cMaxPages;
2212 /** The current pool size. */
2213 uint16_t cCurPages;
2214 /** The head of the free page list. */
2215 uint16_t iFreeHead;
2216 /* Padding. */
2217 uint16_t u16Padding;
2218 /** Head of the chain of free user nodes. */
2219 uint16_t iUserFreeHead;
2220 /** The number of user nodes we've allocated. */
2221 uint16_t cMaxUsers;
2222 /** The number of present page table entries in the entire pool. */
2223 uint32_t cPresent;
2224 /** Pointer to the array of user nodes - R3 pointer. */
2225 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2226 /** Pointer to the array of user nodes - R0 pointer. */
2227 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2228 /** Head of the chain of free phys ext nodes. */
2229 uint16_t iPhysExtFreeHead;
2230 /** The number of user nodes we've allocated. */
2231 uint16_t cMaxPhysExts;
2232 uint32_t u32Padding0b;
2233 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
2234 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2235 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
2236 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2237 /** Hash table for GCPhys addresses. */
2238 uint16_t aiHash[PGMPOOL_HASH_SIZE];
2239 /** The head of the age list. */
2240 uint16_t iAgeHead;
2241 /** The tail of the age list. */
2242 uint16_t iAgeTail;
2243 /** Set if the cache is enabled. */
2244 bool fCacheEnabled;
2245 /** Alignment padding. */
2246 bool afPadding1[3];
2247 /** Head of the list of modified pages. */
2248 uint16_t iModifiedHead;
2249 /** The current number of modified pages. */
2250 uint16_t cModifiedPages;
2251 /** Physical access handler type registration handle. */
2252 PGMPHYSHANDLERTYPE hAccessHandlerType;
2253 /** Next available slot (in aDirtyPages). */
2254 uint32_t idxFreeDirtyPage;
2255 /** Number of active dirty pages. */
2256 uint32_t cDirtyPages;
2257 /** Array of current dirty pgm pool page indices. */
2258 uint16_t aidxDirtyPages[16];
2259 /** Array running in parallel to aidxDirtyPages with the page data. */
2260 struct
2261 {
2262 uint64_t aPage[512];
2263 } aDirtyPages[16];
2264
2265 /** The number of pages currently in use. */
2266 uint16_t cUsedPages;
2267#ifdef VBOX_WITH_STATISTICS
2268 /** The high water mark for cUsedPages. */
2269 uint16_t cUsedPagesHigh;
2270 uint32_t Alignment1; /**< Align the next member on a 64-bit boundary. */
2271 /** Profiling pgmPoolAlloc(). */
2272 STAMPROFILEADV StatAlloc;
2273 /** Profiling pgmR3PoolClearDoIt(). */
2274 STAMPROFILE StatClearAll;
2275 /** Profiling pgmR3PoolReset(). */
2276 STAMPROFILE StatR3Reset;
2277 /** Profiling pgmPoolFlushPage(). */
2278 STAMPROFILE StatFlushPage;
2279 /** Profiling pgmPoolFree(). */
2280 STAMPROFILE StatFree;
2281 /** Counting explicit flushes by PGMPoolFlushPage(). */
2282 STAMCOUNTER StatForceFlushPage;
2283 /** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2284 STAMCOUNTER StatForceFlushDirtyPage;
2285 /** Counting flushes for reused pages. */
2286 STAMCOUNTER StatForceFlushReused;
2287 /** Profiling time spent zeroing pages. */
2288 STAMPROFILE StatZeroPage;
2289 /** Profiling of pgmPoolTrackDeref. */
2290 STAMPROFILE StatTrackDeref;
2291 /** Profiling pgmTrackFlushGCPhysPT. */
2292 STAMPROFILE StatTrackFlushGCPhysPT;
2293 /** Profiling pgmTrackFlushGCPhysPTs. */
2294 STAMPROFILE StatTrackFlushGCPhysPTs;
2295 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
2296 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2297 /** Number of times we've been out of user records. */
2298 STAMCOUNTER StatTrackFreeUpOneUser;
2299 /** Nr of flushed entries. */
2300 STAMCOUNTER StatTrackFlushEntry;
2301 /** Nr of updated entries. */
2302 STAMCOUNTER StatTrackFlushEntryKeep;
2303 /** Profiling deref activity related tracking GC physical pages. */
2304 STAMPROFILE StatTrackDerefGCPhys;
2305 /** Number of linear searches for a HCPhys in the ram ranges. */
2306 STAMCOUNTER StatTrackLinearRamSearches;
2307 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2308 STAMCOUNTER StamTrackPhysExtAllocFailures;
2309
2310 /** Profiling the RC/R0 \#PF access handler. */
2311 STAMPROFILE StatMonitorPfRZ;
2312 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
2313 STAMPROFILE StatMonitorPfRZHandled;
2314 /** Times we've failed interpreting the instruction. */
2315 STAMCOUNTER StatMonitorPfRZEmulateInstr;
2316 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2317 STAMPROFILE StatMonitorPfRZFlushPage;
2318 /** Times we've detected a page table reinit. */
2319 STAMCOUNTER StatMonitorPfRZFlushReinit;
2320 /** Counting flushes for pages that are modified too often. */
2321 STAMCOUNTER StatMonitorPfRZFlushModOverflow;
2322 /** Times we've detected fork(). */
2323 STAMCOUNTER StatMonitorPfRZFork;
2324 /** Times we've failed interpreting a patch code instruction. */
2325 STAMCOUNTER StatMonitorPfRZIntrFailPatch1;
2326 /** Times we've failed interpreting a patch code instruction during flushing. */
2327 STAMCOUNTER StatMonitorPfRZIntrFailPatch2;
2328 /** The number of times we've seen rep prefixes we can't handle. */
2329 STAMCOUNTER StatMonitorPfRZRepPrefix;
2330 /** Profiling the REP STOSD cases we've handled. */
2331 STAMPROFILE StatMonitorPfRZRepStosd;
2332
2333 /** Profiling the R0/RC regular access handler. */
2334 STAMPROFILE StatMonitorRZ;
2335 /** Profiling the pgmPoolFlushPage calls made from the regular access handler in R0/RC. */
2336 STAMPROFILE StatMonitorRZFlushPage;
2337 /** Per access size counts indexed by size minus 1, last for larger. */
2338 STAMCOUNTER aStatMonitorRZSizes[16+3];
2339 /** Missaligned access counts indexed by offset - 1. */
2340 STAMCOUNTER aStatMonitorRZMisaligned[7];
2341
2342 /** Nr of handled PT faults. */
2343 STAMCOUNTER StatMonitorRZFaultPT;
2344 /** Nr of handled PD faults. */
2345 STAMCOUNTER StatMonitorRZFaultPD;
2346 /** Nr of handled PDPT faults. */
2347 STAMCOUNTER StatMonitorRZFaultPDPT;
2348 /** Nr of handled PML4 faults. */
2349 STAMCOUNTER StatMonitorRZFaultPML4;
2350
2351 /** Profiling the R3 access handler. */
2352 STAMPROFILE StatMonitorR3;
2353 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2354 STAMPROFILE StatMonitorR3FlushPage;
2355 /** Per access size counts indexed by size minus 1, last for larger. */
2356 STAMCOUNTER aStatMonitorR3Sizes[16+3];
2357 /** Missaligned access counts indexed by offset - 1. */
2358 STAMCOUNTER aStatMonitorR3Misaligned[7];
2359 /** Nr of handled PT faults. */
2360 STAMCOUNTER StatMonitorR3FaultPT;
2361 /** Nr of handled PD faults. */
2362 STAMCOUNTER StatMonitorR3FaultPD;
2363 /** Nr of handled PDPT faults. */
2364 STAMCOUNTER StatMonitorR3FaultPDPT;
2365 /** Nr of handled PML4 faults. */
2366 STAMCOUNTER StatMonitorR3FaultPML4;
2367
2368 /** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2369 STAMCOUNTER StatResetDirtyPages;
2370 /** Times we've called pgmPoolAddDirtyPage. */
2371 STAMCOUNTER StatDirtyPage;
2372 /** Times we've had to flush duplicates for dirty page management. */
2373 STAMCOUNTER StatDirtyPageDupFlush;
2374 /** Times we've had to flush because of overflow. */
2375 STAMCOUNTER StatDirtyPageOverFlowFlush;
2376
2377 /** The high water mark for cModifiedPages. */
2378 uint16_t cModifiedPagesHigh;
2379 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundary. */
2380
2381 /** The number of cache hits. */
2382 STAMCOUNTER StatCacheHits;
2383 /** The number of cache misses. */
2384 STAMCOUNTER StatCacheMisses;
2385 /** The number of times we've got a conflict of 'kind' in the cache. */
2386 STAMCOUNTER StatCacheKindMismatches;
2387 /** Number of times we've been out of pages. */
2388 STAMCOUNTER StatCacheFreeUpOne;
2389 /** The number of cacheable allocations. */
2390 STAMCOUNTER StatCacheCacheable;
2391 /** The number of uncacheable allocations. */
2392 STAMCOUNTER StatCacheUncacheable;
2393#else
2394 uint32_t Alignment3; /**< Align the next member on a 64-bit boundary. */
2395#endif
2396 /** Profiling PGMR0PoolGrow(). */
2397 STAMPROFILE StatGrow;
2398 /** The AVL tree for looking up a page by its HC physical address. */
2399 AVLOHCPHYSTREE HCPhysTree;
2400 uint32_t Alignment4; /**< Align the next member on a 64-bit boundary. */
2401 /** Array of pages. (cMaxPages in length)
2402 * The Id is the index into thist array.
2403 */
2404 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2405} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
2406AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2407AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2408AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2409#ifdef VBOX_WITH_STATISTICS
2410AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2411#endif
2412AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2413
2414
2415/** @def PGMPOOL_PAGE_2_PTR
2416 * Maps a pool page pool into the current context.
2417 *
2418 * @returns VBox status code.
2419 * @param a_pVM Pointer to the VM.
2420 * @param a_pPage The pool page.
2421 *
2422 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2423 * small page window employeed by that function. Be careful.
2424 * @remark There is no need to assert on the result.
2425 */
2426#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2427# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageInlined((a_pVM), (a_pPage) RTLOG_COMMA_SRC_POS)
2428#elif defined(VBOX_STRICT) || 1 /* temporarily going strict here */
2429# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageStrict(a_pPage, __FUNCTION__)
2430DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE a_pPage, const char *pszCaller)
2431{
2432 RT_NOREF(pszCaller);
2433 AssertPtr(a_pPage);
2434 AssertMsg(RT_VALID_PTR(a_pPage->CTX_SUFF(pvPage)),
2435 ("enmKind=%d idx=%#x HCPhys=%RHp GCPhys=%RGp pvPageR3=%p pvPageR0=%p caller=%s\n",
2436 a_pPage->enmKind, a_pPage->idx, a_pPage->Core.Key, a_pPage->GCPhys, a_pPage->pvPageR3, a_pPage->pvPageR0, pszCaller));
2437 return a_pPage->CTX_SUFF(pvPage);
2438}
2439#else
2440# define PGMPOOL_PAGE_2_PTR(pVM, a_pPage) ((a_pPage)->CTX_SUFF(pvPage))
2441#endif
2442
2443
2444/** @def PGMPOOL_PAGE_2_PTR_V2
2445 * Maps a pool page pool into the current context, taking both VM and VMCPU.
2446 *
2447 * @returns VBox status code.
2448 * @param a_pVM Pointer to the VM.
2449 * @param a_pVCpu The current CPU.
2450 * @param a_pPage The pool page.
2451 *
2452 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2453 * small page window employeed by that function. Be careful.
2454 * @remark There is no need to assert on the result.
2455 */
2456#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2457# define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) pgmPoolMapPageV2Inlined((a_pVM), (a_pVCpu), (a_pPage) RTLOG_COMMA_SRC_POS)
2458#else
2459# define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) PGMPOOL_PAGE_2_PTR((a_pVM), (a_pPage))
2460#endif
2461
2462
2463/** @name Per guest page tracking data.
2464 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2465 * is to use more bits for it and split it up later on. But for now we'll play
2466 * safe and change as little as possible.
2467 *
2468 * The 16-bit word has two parts:
2469 *
2470 * The first 14-bit forms the @a idx field. It is either the index of a page in
2471 * the shadow page pool, or and index into the extent list.
2472 *
2473 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
2474 * shadow page pool references to the page. If cRefs equals
2475 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2476 * (misnomer) table and not the shadow page pool.
2477 *
2478 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2479 * the 16-bit word.
2480 *
2481 * @{ */
2482/** The shift count for getting to the cRefs part. */
2483#define PGMPOOL_TD_CREFS_SHIFT 14
2484/** The mask applied after shifting the tracking data down by
2485 * PGMPOOL_TD_CREFS_SHIFT. */
2486#define PGMPOOL_TD_CREFS_MASK 0x3
2487/** The cRefs value used to indicate that the idx is the head of a
2488 * physical cross reference list. */
2489#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2490/** The shift used to get idx. */
2491#define PGMPOOL_TD_IDX_SHIFT 0
2492/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2493#define PGMPOOL_TD_IDX_MASK 0x3fff
2494/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2495 * simply too many mappings of this page. */
2496#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2497
2498/** @def PGMPOOL_TD_MAKE
2499 * Makes a 16-bit tracking data word.
2500 *
2501 * @returns tracking data.
2502 * @param cRefs The @a cRefs field. Must be within bounds!
2503 * @param idx The @a idx field. Must also be within bounds! */
2504#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
2505
2506/** @def PGMPOOL_TD_GET_CREFS
2507 * Get the @a cRefs field from a tracking data word.
2508 *
2509 * @returns The @a cRefs field
2510 * @param u16 The tracking data word.
2511 * @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2512 * non-zero @a u16. */
2513#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2514
2515/** @def PGMPOOL_TD_GET_IDX
2516 * Get the @a idx field from a tracking data word.
2517 *
2518 * @returns The @a idx field
2519 * @param u16 The tracking data word. */
2520#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2521/** @} */
2522
2523
2524
2525/** @name A20 gate macros
2526 * @{ */
2527#define PGM_WITH_A20
2528#ifdef PGM_WITH_A20
2529# define PGM_A20_IS_ENABLED(a_pVCpu) ((a_pVCpu)->pgm.s.fA20Enabled)
2530# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) ((a_GCPhys) & (a_pVCpu)->pgm.s.GCPhysA20Mask)
2531# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) \
2532 do { a_GCPhysVar &= (a_pVCpu)->pgm.s.GCPhysA20Mask; } while (0)
2533# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) Assert(PGM_A20_APPLY(pVCpu, a_GCPhys) == (a_GCPhys))
2534#else
2535# define PGM_A20_IS_ENABLED(a_pVCpu) (true)
2536# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) (a_GCPhys)
2537# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) do { } while (0)
2538# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) do { } while (0)
2539#endif
2540/** @} */
2541
2542
2543/**
2544 * Roots and anchors for trees and list employing self relative offsets as
2545 * pointers.
2546 *
2547 * When using self-relative offsets instead of pointers, the offsets needs to be
2548 * the same in all offsets. Thus the roots and anchors needs to live on the
2549 * hyper heap just like the nodes.
2550 */
2551typedef struct PGMTREES
2552{
2553 /** List of physical access handler types (offset pointers) of type
2554 * PGMPHYSHANDLERTYPEINT. This is needed for relocations. */
2555 RTLISTOFF32ANCHOR HeadPhysHandlerTypes;
2556 /** Physical access handlers (AVL range+offsetptr tree). */
2557 AVLROGCPHYSTREE PhysHandlers;
2558} PGMTREES;
2559/** Pointer to PGM trees. */
2560typedef PGMTREES *PPGMTREES;
2561
2562
2563/**
2564 * Page fault guest state for the AMD64 paging mode.
2565 */
2566typedef struct PGMPTWALKCORE
2567{
2568 /** The guest virtual address that is being resolved by the walk
2569 * (input). */
2570 RTGCPTR GCPtr;
2571
2572 /** The guest physical address that is the result of the walk.
2573 * @remarks only valid if fSucceeded is set. */
2574 RTGCPHYS GCPhys;
2575
2576 /** Set if the walk succeeded, i.d. GCPhys is valid. */
2577 bool fSucceeded;
2578 /** The level problem arrised at.
2579 * PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
2580 * level 8. This is 0 on success. */
2581 uint8_t uLevel;
2582 /** Set if the page isn't present. */
2583 bool fNotPresent;
2584 /** Encountered a bad physical address. */
2585 bool fBadPhysAddr;
2586 /** Set if there was reserved bit violations. */
2587 bool fRsvdError;
2588 /** Set if it involves a big page (2/4 MB). */
2589 bool fBigPage;
2590 /** Set if it involves a gigantic page (1 GB). */
2591 bool fGigantPage;
2592 /** The effective X86_PTE_US flag for the address. */
2593 bool fEffectiveUS;
2594 /** The effective X86_PTE_RW flag for the address. */
2595 bool fEffectiveRW;
2596 /** The effective X86_PTE_NX flag for the address. */
2597 bool fEffectiveNX;
2598 bool afPadding1[2];
2599 /** Effective flags thus far: RW, US, PWT, PCD, A, ~NX >> 63.
2600 * The NX bit is inverted and shifted down 63 places to bit 0. */
2601 uint32_t fEffective;
2602} PGMPTWALKCORE;
2603
2604/** @name PGMPTWALKCORE::fEffective bits.
2605 * @{ */
2606/** Effective execute bit (!NX). */
2607#define PGMPTWALK_EFF_X UINT32_C(1)
2608/** Effective write access bit. */
2609#define PGMPTWALK_EFF_RW X86_PTE_RW
2610/** Effective user-mode access bit. */
2611#define PGMPTWALK_EFF_US X86_PTE_US
2612/** Effective write through cache bit. */
2613#define PGMPTWALK_EFF_PWT X86_PTE_PWT
2614/** Effective cache disabled bit. */
2615#define PGMPTWALK_EFF_PCD X86_PTE_PCD
2616/** Effective accessed bit. */
2617#define PGMPTWALK_EFF_A X86_PTE_A
2618/** The dirty bit of the final entry. */
2619#define PGMPTWALK_EFF_D X86_PTE_D
2620/** The PAT bit of the final entry. */
2621#define PGMPTWALK_EFF_PAT X86_PTE_PAT
2622/** The global bit of the final entry. */
2623#define PGMPTWALK_EFF_G X86_PTE_G
2624/** @} */
2625
2626
2627/**
2628 * Guest page table walk for the AMD64 mode.
2629 */
2630typedef struct PGMPTWALKGSTAMD64
2631{
2632 /** The common core. */
2633 PGMPTWALKCORE Core;
2634
2635 PX86PML4 pPml4;
2636 PX86PML4E pPml4e;
2637 X86PML4E Pml4e;
2638
2639 PX86PDPT pPdpt;
2640 PX86PDPE pPdpe;
2641 X86PDPE Pdpe;
2642
2643 PX86PDPAE pPd;
2644 PX86PDEPAE pPde;
2645 X86PDEPAE Pde;
2646
2647 PX86PTPAE pPt;
2648 PX86PTEPAE pPte;
2649 X86PTEPAE Pte;
2650} PGMPTWALKGSTAMD64;
2651/** Pointer to a AMD64 guest page table walk. */
2652typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2653/** Pointer to a const AMD64 guest page table walk. */
2654typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2655
2656/**
2657 * Guest page table walk for the PAE mode.
2658 */
2659typedef struct PGMPTWALKGSTPAE
2660{
2661 /** The common core. */
2662 PGMPTWALKCORE Core;
2663
2664 PX86PDPT pPdpt;
2665 PX86PDPE pPdpe;
2666 X86PDPE Pdpe;
2667
2668 PX86PDPAE pPd;
2669 PX86PDEPAE pPde;
2670 X86PDEPAE Pde;
2671
2672 PX86PTPAE pPt;
2673 PX86PTEPAE pPte;
2674 X86PTEPAE Pte;
2675} PGMPTWALKGSTPAE;
2676/** Pointer to a PAE guest page table walk. */
2677typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2678/** Pointer to a const AMD64 guest page table walk. */
2679typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2680
2681/**
2682 * Guest page table walk for the 32-bit mode.
2683 */
2684typedef struct PGMPTWALKGST32BIT
2685{
2686 /** The common core. */
2687 PGMPTWALKCORE Core;
2688
2689 PX86PD pPd;
2690 PX86PDE pPde;
2691 X86PDE Pde;
2692
2693 PX86PT pPt;
2694 PX86PTE pPte;
2695 X86PTE Pte;
2696} PGMPTWALKGST32BIT;
2697/** Pointer to a 32-bit guest page table walk. */
2698typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2699/** Pointer to a const 32-bit guest page table walk. */
2700typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2701
2702/**
2703 * Which part of PGMPTWALKGST that is valid.
2704 */
2705typedef enum PGMPTWALKGSTTYPE
2706{
2707 /** Customary invalid 0 value. */
2708 PGMPTWALKGSTTYPE_INVALID = 0,
2709 /** PGMPTWALKGST::u.Amd64 is valid. */
2710 PGMPTWALKGSTTYPE_AMD64,
2711 /** PGMPTWALKGST::u.Pae is valid. */
2712 PGMPTWALKGSTTYPE_PAE,
2713 /** PGMPTWALKGST::u.Legacy is valid. */
2714 PGMPTWALKGSTTYPE_32BIT,
2715 /** Customary 32-bit type hack. */
2716 PGMPTWALKGSTTYPE_32BIT_HACK = 0x7fff0000
2717} PGMPTWALKGSTTYPE;
2718
2719/**
2720 * Combined guest page table walk result.
2721 */
2722typedef struct PGMPTWALKGST
2723{
2724 union
2725 {
2726 /** The page walker core - always valid. */
2727 PGMPTWALKCORE Core;
2728 /** The page walker for AMD64. */
2729 PGMPTWALKGSTAMD64 Amd64;
2730 /** The page walker for PAE (32-bit). */
2731 PGMPTWALKGSTPAE Pae;
2732 /** The page walker for 32-bit paging (called legacy due to C naming
2733 * convension). */
2734 PGMPTWALKGST32BIT Legacy;
2735 } u;
2736 /** Indicates which part of the union is valid. */
2737 PGMPTWALKGSTTYPE enmType;
2738} PGMPTWALKGST;
2739/** Pointer to a combined guest page table walk result. */
2740typedef PGMPTWALKGST *PPGMPTWALKGST;
2741/** Pointer to a read-only combined guest page table walk result. */
2742typedef PGMPTWALKGST const *PCPGMPTWALKGST;
2743
2744
2745/** @name Paging mode macros
2746 * @{
2747 */
2748#ifdef IN_RING3
2749# define PGM_CTX(a,b) a##R3##b
2750# define PGM_CTX_STR(a,b) a "R3" b
2751# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2752#elif defined(IN_RING0)
2753# define PGM_CTX(a,b) a##R0##b
2754# define PGM_CTX_STR(a,b) a "R0" b
2755# define PGM_CTX_DECL(type) VMMDECL(type)
2756#else
2757# error "Not IN_RING3 or IN_RING0!"
2758#endif
2759
2760#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2761#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2762#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2763#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2764#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2765#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2766#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2767#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2768#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2769#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2770#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2771#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2772#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2773#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2774#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2775#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2776
2777#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2778#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2779#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2780#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2781#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2782#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2783#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2784#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2785#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2786#define PGM_SHW_NAME_NESTED_32BIT(name) PGM_CTX(pgm,ShwNested32Bit##name)
2787#define PGM_SHW_NAME_RC_NESTED_32BIT_STR(name) "pgmRCShwNested32Bit" #name
2788#define PGM_SHW_NAME_R0_NESTED_32BIT_STR(name) "pgmR0ShwNested32Bit" #name
2789#define PGM_SHW_NAME_NESTED_PAE(name) PGM_CTX(pgm,ShwNestedPAE##name)
2790#define PGM_SHW_NAME_RC_NESTED_PAE_STR(name) "pgmRCShwNestedPAE" #name
2791#define PGM_SHW_NAME_R0_NESTED_PAE_STR(name) "pgmR0ShwNestedPAE" #name
2792#define PGM_SHW_NAME_NESTED_AMD64(name) PGM_CTX(pgm,ShwNestedAMD64##name)
2793#define PGM_SHW_NAME_RC_NESTED_AMD64_STR(name) "pgmRCShwNestedAMD64" #name
2794#define PGM_SHW_NAME_R0_NESTED_AMD64_STR(name) "pgmR0ShwNestedAMD64" #name
2795#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2796#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2797#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2798#define PGM_SHW_NAME_NONE(name) PGM_CTX(pgm,ShwNone##name)
2799#define PGM_SHW_NAME_RC_NONE_STR(name) "pgmRCShwNone" #name
2800#define PGM_SHW_NAME_R0_NONE_STR(name) "pgmR0ShwNone" #name
2801#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2802
2803/* Shw_Gst */
2804#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2805#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2806#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2807#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2808#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2809#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2810#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2811#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2812#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2813#define PGM_BTH_NAME_NESTED_32BIT_REAL(name) PGM_CTX(pgm,BthNested32BitReal##name)
2814#define PGM_BTH_NAME_NESTED_32BIT_PROT(name) PGM_CTX(pgm,BthNested32BitProt##name)
2815#define PGM_BTH_NAME_NESTED_32BIT_32BIT(name) PGM_CTX(pgm,BthNested32Bit32Bit##name)
2816#define PGM_BTH_NAME_NESTED_32BIT_PAE(name) PGM_CTX(pgm,BthNested32BitPAE##name)
2817#define PGM_BTH_NAME_NESTED_32BIT_AMD64(name) PGM_CTX(pgm,BthNested32BitAMD64##name)
2818#define PGM_BTH_NAME_NESTED_PAE_REAL(name) PGM_CTX(pgm,BthNestedPAEReal##name)
2819#define PGM_BTH_NAME_NESTED_PAE_PROT(name) PGM_CTX(pgm,BthNestedPAEProt##name)
2820#define PGM_BTH_NAME_NESTED_PAE_32BIT(name) PGM_CTX(pgm,BthNestedPAE32Bit##name)
2821#define PGM_BTH_NAME_NESTED_PAE_PAE(name) PGM_CTX(pgm,BthNestedPAEPAE##name)
2822#define PGM_BTH_NAME_NESTED_PAE_AMD64(name) PGM_CTX(pgm,BthNestedPAEAMD64##name)
2823#define PGM_BTH_NAME_NESTED_AMD64_REAL(name) PGM_CTX(pgm,BthNestedAMD64Real##name)
2824#define PGM_BTH_NAME_NESTED_AMD64_PROT(name) PGM_CTX(pgm,BthNestedAMD64Prot##name)
2825#define PGM_BTH_NAME_NESTED_AMD64_32BIT(name) PGM_CTX(pgm,BthNestedAMD6432Bit##name)
2826#define PGM_BTH_NAME_NESTED_AMD64_PAE(name) PGM_CTX(pgm,BthNestedAMD64PAE##name)
2827#define PGM_BTH_NAME_NESTED_AMD64_AMD64(name) PGM_CTX(pgm,BthNestedAMD64AMD64##name)
2828#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2829#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2830#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2831#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2832#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2833#define PGM_BTH_NAME_NONE_REAL(name) PGM_CTX(pgm,BthNoneReal##name)
2834#define PGM_BTH_NAME_NONE_PROT(name) PGM_CTX(pgm,BthNoneProt##name)
2835#define PGM_BTH_NAME_NONE_32BIT(name) PGM_CTX(pgm,BthNone32Bit##name)
2836#define PGM_BTH_NAME_NONE_PAE(name) PGM_CTX(pgm,BthNonePAE##name)
2837#define PGM_BTH_NAME_NONE_AMD64(name) PGM_CTX(pgm,BthNoneAMD64##name)
2838
2839#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2840#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2841#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2842#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2843#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2844#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2845#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2846#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2847#define PGM_BTH_NAME_RC_NESTED_32BIT_REAL_STR(name) "pgmRCBthNested32BitReal" #name
2848#define PGM_BTH_NAME_RC_NESTED_32BIT_PROT_STR(name) "pgmRCBthNested32BitProt" #name
2849#define PGM_BTH_NAME_RC_NESTED_32BIT_32BIT_STR(name) "pgmRCBthNested32Bit32Bit" #name
2850#define PGM_BTH_NAME_RC_NESTED_32BIT_PAE_STR(name) "pgmRCBthNested32BitPAE" #name
2851#define PGM_BTH_NAME_RC_NESTED_32BIT_AMD64_STR(name) "pgmRCBthNested32BitAMD64" #name
2852#define PGM_BTH_NAME_RC_NESTED_PAE_REAL_STR(name) "pgmRCBthNestedPAEReal" #name
2853#define PGM_BTH_NAME_RC_NESTED_PAE_PROT_STR(name) "pgmRCBthNestedPAEProt" #name
2854#define PGM_BTH_NAME_RC_NESTED_PAE_32BIT_STR(name) "pgmRCBthNestedPAE32Bit" #name
2855#define PGM_BTH_NAME_RC_NESTED_PAE_PAE_STR(name) "pgmRCBthNestedPAEPAE" #name
2856#define PGM_BTH_NAME_RC_NESTED_PAE_AMD64_STR(name) "pgmRCBthNestedPAEAMD64" #name
2857#define PGM_BTH_NAME_RC_NESTED_AMD64_REAL_STR(name) "pgmRCBthNestedAMD64Real" #name
2858#define PGM_BTH_NAME_RC_NESTED_AMD64_PROT_STR(name) "pgmRCBthNestedAMD64Prot" #name
2859#define PGM_BTH_NAME_RC_NESTED_AMD64_32BIT_STR(name) "pgmRCBthNestedAMD6432Bit" #name
2860#define PGM_BTH_NAME_RC_NESTED_AMD64_PAE_STR(name) "pgmRCBthNestedAMD64PAE" #name
2861#define PGM_BTH_NAME_RC_NESTED_AMD64_AMD64_STR(name) "pgmRCBthNestedAMD64AMD64" #name
2862#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2863#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2864#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2865#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2866#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2867
2868#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2869#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2870#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2871#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2872#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2873#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2874#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2875#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2876#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2877#define PGM_BTH_NAME_R0_NESTED_32BIT_REAL_STR(name) "pgmR0BthNested32BitReal" #name
2878#define PGM_BTH_NAME_R0_NESTED_32BIT_PROT_STR(name) "pgmR0BthNested32BitProt" #name
2879#define PGM_BTH_NAME_R0_NESTED_32BIT_32BIT_STR(name) "pgmR0BthNested32Bit32Bit" #name
2880#define PGM_BTH_NAME_R0_NESTED_32BIT_PAE_STR(name) "pgmR0BthNested32BitPAE" #name
2881#define PGM_BTH_NAME_R0_NESTED_32BIT_AMD64_STR(name) "pgmR0BthNested32BitAMD64" #name
2882#define PGM_BTH_NAME_R0_NESTED_PAE_REAL_STR(name) "pgmR0BthNestedPAEReal" #name
2883#define PGM_BTH_NAME_R0_NESTED_PAE_PROT_STR(name) "pgmR0BthNestedPAEProt" #name
2884#define PGM_BTH_NAME_R0_NESTED_PAE_32BIT_STR(name) "pgmR0BthNestedPAE32Bit" #name
2885#define PGM_BTH_NAME_R0_NESTED_PAE_PAE_STR(name) "pgmR0BthNestedPAEPAE" #name
2886#define PGM_BTH_NAME_R0_NESTED_PAE_AMD64_STR(name) "pgmR0BthNestedPAEAMD64" #name
2887#define PGM_BTH_NAME_R0_NESTED_AMD64_REAL_STR(name) "pgmR0BthNestedAMD64Real" #name
2888#define PGM_BTH_NAME_R0_NESTED_AMD64_PROT_STR(name) "pgmR0BthNestedAMD64Prot" #name
2889#define PGM_BTH_NAME_R0_NESTED_AMD64_32BIT_STR(name) "pgmR0BthNestedAMD6432Bit" #name
2890#define PGM_BTH_NAME_R0_NESTED_AMD64_PAE_STR(name) "pgmR0BthNestedAMD64PAE" #name
2891#define PGM_BTH_NAME_R0_NESTED_AMD64_AMD64_STR(name) "pgmR0BthNestedAMD64AMD64" #name
2892#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2893#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2894#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2895#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2896#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2897
2898#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2899/** @} */
2900
2901
2902/**
2903 * Function pointers for guest paging.
2904 */
2905typedef struct PGMMODEDATAGST
2906{
2907 /** The guest mode type. */
2908 uint32_t uType;
2909 DECLCALLBACKMEMBER(int, pfnGetPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2910 DECLCALLBACKMEMBER(int, pfnModifyPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2911 DECLCALLBACKMEMBER(int, pfnGetPDE,(PVMCPUCC pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2912 DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2913 DECLCALLBACKMEMBER(int, pfnExit,(PVMCPUCC pVCpu));
2914#ifdef IN_RING3
2915 DECLCALLBACKMEMBER(int, pfnRelocate,(PVMCPUCC pVCpu, RTGCPTR offDelta)); /**< Only in ring-3. */
2916#endif
2917} PGMMODEDATAGST;
2918
2919/** The length of g_aPgmGuestModeData. */
2920#ifdef VBOX_WITH_64_BITS_GUESTS
2921# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_AMD64 + 1)
2922#else
2923# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_PAE + 1)
2924#endif
2925/** The guest mode data array. */
2926extern PGMMODEDATAGST const g_aPgmGuestModeData[PGM_GUEST_MODE_DATA_ARRAY_SIZE];
2927
2928
2929/**
2930 * Function pointers for shadow paging.
2931 */
2932typedef struct PGMMODEDATASHW
2933{
2934 /** The shadow mode type. */
2935 uint32_t uType;
2936 DECLCALLBACKMEMBER(int, pfnGetPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2937 DECLCALLBACKMEMBER(int, pfnModifyPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags,
2938 uint64_t fMask, uint32_t fOpFlags));
2939 DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, bool fIs64BitsPagingMode));
2940 DECLCALLBACKMEMBER(int, pfnExit,(PVMCPUCC pVCpu));
2941#ifdef IN_RING3
2942 DECLCALLBACKMEMBER(int, pfnRelocate,(PVMCPUCC pVCpu, RTGCPTR offDelta)); /**< Only in ring-3. */
2943#endif
2944} PGMMODEDATASHW;
2945
2946/** The length of g_aPgmShadowModeData. */
2947#define PGM_SHADOW_MODE_DATA_ARRAY_SIZE PGM_TYPE_END
2948/** The shadow mode data array. */
2949extern PGMMODEDATASHW const g_aPgmShadowModeData[PGM_SHADOW_MODE_DATA_ARRAY_SIZE];
2950
2951
2952/**
2953 * Function pointers for guest+shadow paging.
2954 */
2955typedef struct PGMMODEDATABTH
2956{
2957 /** The shadow mode type. */
2958 uint32_t uShwType;
2959 /** The guest mode type. */
2960 uint32_t uGstType;
2961
2962 DECLCALLBACKMEMBER(int, pfnInvalidatePage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage));
2963 DECLCALLBACKMEMBER(int, pfnSyncCR3,(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2964 DECLCALLBACKMEMBER(int, pfnPrefetchPage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage));
2965 DECLCALLBACKMEMBER(int, pfnVerifyAccessSyncPage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2966 DECLCALLBACKMEMBER(int, pfnMapCR3,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2967 DECLCALLBACKMEMBER(int, pfnUnmapCR3,(PVMCPUCC pVCpu));
2968 DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2969#ifndef IN_RING3
2970 DECLCALLBACKMEMBER(int, pfnTrap0eHandler,(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2971#endif
2972#ifdef VBOX_STRICT
2973 DECLCALLBACKMEMBER(unsigned, pfnAssertCR3,(PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2974#endif
2975} PGMMODEDATABTH;
2976
2977/** The length of g_aPgmBothModeData. */
2978#define PGM_BOTH_MODE_DATA_ARRAY_SIZE ((PGM_TYPE_END - PGM_TYPE_FIRST_SHADOW) * PGM_TYPE_END)
2979/** The guest+shadow mode data array. */
2980extern PGMMODEDATABTH const g_aPgmBothModeData[PGM_BOTH_MODE_DATA_ARRAY_SIZE];
2981
2982
2983#ifdef VBOX_WITH_STATISTICS
2984/**
2985 * PGM statistics.
2986 *
2987 * These lives on the heap when compiled in as they would otherwise waste
2988 * unnecessary space in release builds.
2989 */
2990typedef struct PGMSTATS
2991{
2992 /* R3 only: */
2993 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2994 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2995
2996 /* R3+RZ */
2997 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2998 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2999 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
3000 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
3001 STAMCOUNTER StatPageMapTlbFlushes; /**< ALL: Ring-3/0 page mapper TLB flushes. */
3002 STAMCOUNTER StatPageMapTlbFlushEntry; /**< ALL: Ring-3/0 page mapper TLB flushes. */
3003 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
3004 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
3005 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
3006 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
3007 STAMCOUNTER StatRZRamRangeTlbHits; /**< RC/R0: RAM range TLB hits. */
3008 STAMCOUNTER StatRZRamRangeTlbMisses; /**< RC/R0: RAM range TLB misses. */
3009 STAMCOUNTER StatR3RamRangeTlbHits; /**< R3: RAM range TLB hits. */
3010 STAMCOUNTER StatR3RamRangeTlbMisses; /**< R3: RAM range TLB misses. */
3011 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
3012 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
3013 STAMCOUNTER StatR3PhysHandlerLookupHits; /**< R3: Number of cache hits when looking up physical handlers. */
3014 STAMCOUNTER StatR3PhysHandlerLookupMisses; /**< R3: Number of cache misses when looking up physical handlers. */
3015 STAMCOUNTER StatRZPhysHandlerLookupHits; /**< RC/R0: Number of cache hits when lookup up physical handlers. */
3016 STAMCOUNTER StatRZPhysHandlerLookupMisses; /**< RC/R0: Number of cache misses when looking up physical handlers */
3017 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
3018 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
3019/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
3020 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
3021 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
3022/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
3023
3024 /* RC only: */
3025 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
3026 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
3027
3028 STAMCOUNTER StatRZPhysRead;
3029 STAMCOUNTER StatRZPhysReadBytes;
3030 STAMCOUNTER StatRZPhysWrite;
3031 STAMCOUNTER StatRZPhysWriteBytes;
3032 STAMCOUNTER StatR3PhysRead;
3033 STAMCOUNTER StatR3PhysReadBytes;
3034 STAMCOUNTER StatR3PhysWrite;
3035 STAMCOUNTER StatR3PhysWriteBytes;
3036 STAMCOUNTER StatRCPhysRead;
3037 STAMCOUNTER StatRCPhysReadBytes;
3038 STAMCOUNTER StatRCPhysWrite;
3039 STAMCOUNTER StatRCPhysWriteBytes;
3040
3041 STAMCOUNTER StatRZPhysSimpleRead;
3042 STAMCOUNTER StatRZPhysSimpleReadBytes;
3043 STAMCOUNTER StatRZPhysSimpleWrite;
3044 STAMCOUNTER StatRZPhysSimpleWriteBytes;
3045 STAMCOUNTER StatR3PhysSimpleRead;
3046 STAMCOUNTER StatR3PhysSimpleReadBytes;
3047 STAMCOUNTER StatR3PhysSimpleWrite;
3048 STAMCOUNTER StatR3PhysSimpleWriteBytes;
3049 STAMCOUNTER StatRCPhysSimpleRead;
3050 STAMCOUNTER StatRCPhysSimpleReadBytes;
3051 STAMCOUNTER StatRCPhysSimpleWrite;
3052 STAMCOUNTER StatRCPhysSimpleWriteBytes;
3053
3054 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
3055 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
3056 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
3057 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
3058 STAMCOUNTER StatTrackNoExtentsLeft; /**< The number of times the extent list was exhausted. */
3059 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
3060 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
3061
3062 /** Time spent by the host OS for large page allocation. */
3063 STAMPROFILE StatAllocLargePage;
3064 /** Time spent clearing the newly allocated large pages. */
3065 STAMPROFILE StatClearLargePage;
3066 /** The number of times allocating a large pages takes more than the allowed period. */
3067 STAMCOUNTER StatLargePageOverflow;
3068 /** pgmPhysIsValidLargePage profiling - R3 */
3069 STAMPROFILE StatR3IsValidLargePage;
3070 /** pgmPhysIsValidLargePage profiling - RZ*/
3071 STAMPROFILE StatRZIsValidLargePage;
3072
3073 STAMPROFILE StatChunkAging;
3074 STAMPROFILE StatChunkFindCandidate;
3075 STAMPROFILE StatChunkUnmap;
3076 STAMPROFILE StatChunkMap;
3077} PGMSTATS;
3078#endif /* VBOX_WITH_STATISTICS */
3079
3080
3081/**
3082 * Converts a PGM pointer into a VM pointer.
3083 * @returns Pointer to the VM structure the PGM is part of.
3084 * @param pPGM Pointer to PGM instance data.
3085 */
3086#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
3087
3088/**
3089 * PGM Data (part of VM)
3090 */
3091typedef struct PGM
3092{
3093 /** Offset to the VM structure. */
3094 int32_t offVM;
3095 /** Offset of the PGMCPU structure relative to VMCPU. */
3096 int32_t offVCpuPGM;
3097
3098 /** @cfgm{/RamPreAlloc, boolean, false}
3099 * Indicates whether the base RAM should all be allocated before starting
3100 * the VM (default), or if it should be allocated when first written to.
3101 */
3102 bool fRamPreAlloc;
3103 /** Indicates whether write monitoring is currently in use.
3104 * This is used to prevent conflicts between live saving and page sharing
3105 * detection. */
3106 bool fPhysWriteMonitoringEngaged;
3107 /** Set if the CPU has less than 52-bit physical address width.
3108 * This is used */
3109 bool fLessThan52PhysicalAddressBits;
3110 /** Set when nested paging is active.
3111 * This is meant to save calls to HMIsNestedPagingActive and let the
3112 * compilers optimize the code better. Whether we use nested paging or
3113 * not is something we find out during VMM initialization and we won't
3114 * change this later on. */
3115 bool fNestedPaging;
3116 /** The host paging mode. (This is what SUPLib reports.) */
3117 SUPPAGINGMODE enmHostMode;
3118 /** We're not in a state which permits writes to guest memory.
3119 * (Only used in strict builds.) */
3120 bool fNoMorePhysWrites;
3121 /** @cfgm{/PageFusionAllowed, boolean, false}
3122 * Whether page fusion is allowed. */
3123 bool fPageFusionAllowed;
3124 /** @cfgm{/PGM/PciPassThrough, boolean, false}
3125 * Whether PCI passthrough is enabled. */
3126 bool fPciPassthrough;
3127 /** The number of MMIO2 regions (serves as the next MMIO2 ID). */
3128 uint8_t cMmio2Regions;
3129 /** Restore original ROM page content when resetting after loading state.
3130 * The flag is set by pgmR3LoadRomRanges and cleared at reset. This
3131 * enables the VM to start using an updated ROM without requiring powering
3132 * down the VM, just rebooting or resetting it. */
3133 bool fRestoreRomPagesOnReset;
3134 /** Whether to automatically clear all RAM pages on reset. */
3135 bool fZeroRamPagesOnReset;
3136 /** Alignment padding. */
3137 bool afAlignment3[7];
3138
3139 /** Indicates that PGMR3FinalizeMappings has been called and that further
3140 * PGMR3MapIntermediate calls will be rejected. */
3141 bool fFinalizedMappings;
3142 /** If set no conflict checks are required. */
3143 bool fMappingsFixed;
3144 /** If set if restored as fixed but we were unable to re-fixate at the old
3145 * location because of room or address incompatibilities. */
3146 bool fMappingsFixedRestored;
3147 /** Size of fixed mapping.
3148 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
3149 uint32_t cbMappingFixed;
3150 /** Generation ID for the RAM ranges. This member is incremented everytime
3151 * a RAM range is linked or unlinked. */
3152 uint32_t volatile idRamRangesGen;
3153
3154 /** Base address (GC) of fixed mapping.
3155 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
3156 RTGCPTR GCPtrMappingFixed;
3157 /** The address of the previous RAM range mapping. */
3158 RTGCPTR GCPtrPrevRamRangeMapping;
3159
3160 /** Physical access handler type for ROM protection. */
3161 PGMPHYSHANDLERTYPE hRomPhysHandlerType;
3162 /** Alignment padding. */
3163 uint32_t u32Padding;
3164
3165 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
3166 RTGCPHYS GCPhys4MBPSEMask;
3167 /** Mask containing the invalid bits of a guest physical address.
3168 * @remarks this does not stop at bit 52. */
3169 RTGCPHYS GCPhysInvAddrMask;
3170
3171
3172 /** RAM range TLB for R3. */
3173 R3PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR3[PGM_RAMRANGE_TLB_ENTRIES];
3174 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
3175 * This is sorted by physical address and contains no overlapping ranges. */
3176 R3PTRTYPE(PPGMRAMRANGE) pRamRangesXR3;
3177 /** Root of the RAM range search tree for ring-3. */
3178 R3PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR3;
3179 /** PGM offset based trees - R3 Ptr. */
3180 R3PTRTYPE(PPGMTREES) pTreesR3;
3181 /** Caching the last physical handler we looked up in R3. */
3182 R3PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR3;
3183 /** Shadow Page Pool - R3 Ptr. */
3184 R3PTRTYPE(PPGMPOOL) pPoolR3;
3185#ifndef PGM_WITHOUT_MAPPINGS
3186 /** Linked list of GC mappings - for HC.
3187 * The list is sorted ascending on address. */
3188 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
3189#endif
3190 /** Pointer to the list of ROM ranges - for R3.
3191 * This is sorted by physical address and contains no overlapping ranges. */
3192 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
3193 /** Pointer to the list of MMIO2 ranges - for R3.
3194 * Registration order. */
3195 R3PTRTYPE(PPGMREGMMIO2RANGE) pRegMmioRangesR3;
3196 /** MMIO2 lookup array for ring-3. Indexed by idMmio2 minus 1. */
3197 R3PTRTYPE(PPGMREGMMIO2RANGE) apMmio2RangesR3[PGM_MMIO2_MAX_RANGES];
3198
3199 /** RAM range TLB for R0. */
3200 R0PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR0[PGM_RAMRANGE_TLB_ENTRIES];
3201 /** R0 pointer corresponding to PGM::pRamRangesXR3. */
3202 R0PTRTYPE(PPGMRAMRANGE) pRamRangesXR0;
3203 /** Root of the RAM range search tree for ring-0. */
3204 R0PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR0;
3205 /** PGM offset based trees - R0 Ptr. */
3206 R0PTRTYPE(PPGMTREES) pTreesR0;
3207 /** Caching the last physical handler we looked up in R0. */
3208 R0PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR0;
3209 /** Shadow Page Pool - R0 Ptr. */
3210 R0PTRTYPE(PPGMPOOL) pPoolR0;
3211#ifndef PGM_WITHOUT_MAPPINGS
3212 /** Linked list of GC mappings - for R0.
3213 * The list is sorted ascending on address. */
3214 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
3215 RTR0PTR R0PtrAlignment0;
3216#endif
3217 /** R0 pointer corresponding to PGM::pRomRangesR3. */
3218 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
3219 /** MMIO2 lookup array for ring-0. Indexed by idMmio2 minus 1. */
3220 R0PTRTYPE(PPGMREGMMIO2RANGE) apMmio2RangesR0[PGM_MMIO2_MAX_RANGES];
3221
3222#ifndef PGM_WITHOUT_MAPPINGS
3223 /** Pointer to the 5 page CR3 content mapping.
3224 * The first page is always the CR3 (in some form) while the 4 other pages
3225 * are used for the PDs in PAE mode. */
3226 RTGCPTR GCPtrCR3Mapping;
3227
3228 /** @name Intermediate Context
3229 * @{ */
3230 /** Pointer to the intermediate page directory - Normal. */
3231 R3PTRTYPE(PX86PD) pInterPD;
3232 /** Pointer to the intermediate page tables - Normal.
3233 * There are two page tables, one for the identity mapping and one for
3234 * the host context mapping (of the core code). */
3235 R3PTRTYPE(PX86PT) apInterPTs[2];
3236 /** Pointer to the intermediate page tables - PAE. */
3237 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
3238 /** Pointer to the intermediate page directory - PAE. */
3239 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
3240 /** Pointer to the intermediate page directory - PAE. */
3241 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
3242 /** Pointer to the intermediate page-map level 4 - AMD64. */
3243 R3PTRTYPE(PX86PML4) pInterPaePML4;
3244 /** Pointer to the intermediate page directory - AMD64. */
3245 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
3246 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
3247 RTHCPHYS HCPhysInterPD;
3248 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
3249 RTHCPHYS HCPhysInterPaePDPT;
3250 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
3251 RTHCPHYS HCPhysInterPaePML4;
3252 /** @} */
3253#endif
3254
3255#ifndef PGM_WITHOUT_MAPPINGS
3256 /** Base address of the dynamic page mapping area.
3257 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
3258 *
3259 * @todo The plan of keeping PGMRCDYNMAP private to PGMRZDynMap.cpp didn't
3260 * work out. Some cleaning up of the initialization that would
3261 * remove this memory is yet to be done...
3262 */
3263 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
3264 /** The address of the raw-mode context mapping cache. */
3265 RCPTRTYPE(PPGMRCDYNMAP) pRCDynMap;
3266 /** The address of the ring-0 mapping cache if we're making use of it. */
3267 RTR0PTR pvR0DynMapUsed;
3268#endif
3269
3270 /** Hack: Number of deprecated page mapping locks taken by the current lock
3271 * owner via pgmPhysGCPhys2CCPtrInternalDepr. */
3272 uint32_t cDeprecatedPageLocks;
3273 /** Alignment padding. */
3274 uint32_t au32Alignment2[1];
3275
3276
3277 /** PGM critical section.
3278 * This protects the physical, ram ranges, and the page flag updating (some of
3279 * it anyway).
3280 */
3281 PDMCRITSECT CritSectX;
3282
3283 /**
3284 * Data associated with managing the ring-3 mappings of the allocation chunks.
3285 */
3286 struct
3287 {
3288 /** The chunk mapping TLB. */
3289 PGMCHUNKR3MAPTLB Tlb;
3290 /** The chunk tree, ordered by chunk id. */
3291#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) || defined(VBOX_WITH_RAM_IN_KERNEL)
3292 R3PTRTYPE(PAVLU32NODECORE) pTree;
3293#else
3294 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
3295#endif
3296#if HC_ARCH_BITS == 32
3297 uint32_t u32Alignment0;
3298#endif
3299 /** The number of mapped chunks. */
3300 uint32_t c;
3301 /** @cfgm{/PGM/MaxRing3Chunks, uint32_t, host dependent}
3302 * The maximum number of mapped chunks. On 64-bit this is unlimited by default,
3303 * on 32-bit it defaults to 1 or 3 GB depending on the host. */
3304 uint32_t cMax;
3305 /** The current time. This is incremented whenever a chunk is inserted. */
3306 uint32_t iNow;
3307 /** Alignment padding. */
3308 uint32_t au32Alignment1[3];
3309 } ChunkR3Map;
3310
3311 /** The page mapping TLB for ring-3. */
3312 PGMPAGER3MAPTLB PhysTlbR3;
3313#ifdef VBOX_WITH_RAM_IN_KERNEL
3314 /** The page mapping TLB for ring-0. */
3315 PGMPAGER0MAPTLB PhysTlbR0;
3316#else
3317 /** The page mapping TLB for ring-0 (still using ring-3 mappings). */
3318 PGMPAGER3MAPTLB PhysTlbR0;
3319#endif
3320
3321 /** @name The zero page.
3322 * @{ */
3323 /** The host physical address of the zero page. */
3324 RTHCPHYS HCPhysZeroPg;
3325 /** The ring-3 mapping of the zero page. */
3326 RTR3PTR pvZeroPgR3;
3327 /** The ring-0 mapping of the zero page. */
3328 RTR0PTR pvZeroPgR0;
3329 /** The GC mapping of the zero page. */
3330 RTRCPTR pvZeroPgRC;
3331 RTRCPTR RCPtrAlignment3;
3332 /** @}*/
3333
3334 /** @name The Invalid MMIO page.
3335 * This page is filled with 0xfeedface.
3336 * @{ */
3337 /** The host physical address of the invalid MMIO page. */
3338 RTHCPHYS HCPhysMmioPg;
3339 /** The host pysical address of the invalid MMIO page plus all invalid
3340 * physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
3341 * @remarks Check fLessThan52PhysicalAddressBits before use. */
3342 RTHCPHYS HCPhysInvMmioPg;
3343 /** The ring-3 mapping of the invalid MMIO page. */
3344 RTR3PTR pvMmioPgR3;
3345#if HC_ARCH_BITS == 32
3346 RTR3PTR R3PtrAlignment4;
3347#endif
3348 /** @} */
3349
3350
3351 /** The number of handy pages. */
3352 uint32_t cHandyPages;
3353
3354 /** The number of large handy pages. */
3355 uint32_t cLargeHandyPages;
3356
3357 /**
3358 * Array of handy pages.
3359 *
3360 * This array is used in a two way communication between pgmPhysAllocPage
3361 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3362 * an intermediary.
3363 *
3364 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
3365 * (The current size of 32 pages, means 128 KB of handy memory.)
3366 */
3367 GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3368
3369 /**
3370 * Array of large handy pages. (currently size 1)
3371 *
3372 * This array is used in a two way communication between pgmPhysAllocLargePage
3373 * and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3374 * an intermediary.
3375 */
3376 GMMPAGEDESC aLargeHandyPage[1];
3377
3378 /**
3379 * Live save data.
3380 */
3381 struct
3382 {
3383 /** Per type statistics. */
3384 struct
3385 {
3386 /** The number of ready pages. */
3387 uint32_t cReadyPages;
3388 /** The number of dirty pages. */
3389 uint32_t cDirtyPages;
3390 /** The number of ready zero pages. */
3391 uint32_t cZeroPages;
3392 /** The number of write monitored pages. */
3393 uint32_t cMonitoredPages;
3394 } Rom,
3395 Mmio2,
3396 Ram;
3397 /** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3398 uint32_t cIgnoredPages;
3399 /** Indicates that a live save operation is active. */
3400 bool fActive;
3401 /** Padding. */
3402 bool afReserved[2];
3403 /** The next history index. */
3404 uint8_t iDirtyPagesHistory;
3405 /** History of the total amount of dirty pages. */
3406 uint32_t acDirtyPagesHistory[64];
3407 /** Short term dirty page average. */
3408 uint32_t cDirtyPagesShort;
3409 /** Long term dirty page average. */
3410 uint32_t cDirtyPagesLong;
3411 /** The number of saved pages. This is used to get some kind of estimate of the
3412 * link speed so we can decide when we're done. It is reset after the first
3413 * 7 passes so the speed estimate doesn't get inflated by the initial set of
3414 * zero pages. */
3415 uint64_t cSavedPages;
3416 /** The nanosecond timestamp when cSavedPages was 0. */
3417 uint64_t uSaveStartNS;
3418 /** Pages per second (for statistics). */
3419 uint32_t cPagesPerSecond;
3420 uint32_t cAlignment;
3421 } LiveSave;
3422
3423 /** @name Error injection.
3424 * @{ */
3425 /** Inject handy page allocation errors pretending we're completely out of
3426 * memory. */
3427 bool volatile fErrInjHandyPages;
3428 /** Padding. */
3429 bool afReserved[3];
3430 /** @} */
3431
3432 /** @name Release Statistics
3433 * @{ */
3434 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) */
3435 uint32_t cPrivatePages; /**< The number of private pages. */
3436 uint32_t cSharedPages; /**< The number of shared pages. */
3437 uint32_t cReusedSharedPages; /**< The number of reused shared pages. */
3438 uint32_t cZeroPages; /**< The number of zero backed pages. */
3439 uint32_t cPureMmioPages; /**< The number of pure MMIO pages. */
3440 uint32_t cMonitoredPages; /**< The number of write monitored pages. */
3441 uint32_t cWrittenToPages; /**< The number of previously write monitored pages. */
3442 uint32_t cWriteLockedPages; /**< The number of write locked pages. */
3443 uint32_t cReadLockedPages; /**< The number of read locked pages. */
3444 uint32_t cBalloonedPages; /**< The number of ballooned pages. */
3445 uint32_t cMappedChunks; /**< Number of times we mapped a chunk. */
3446 uint32_t cUnmappedChunks; /**< Number of times we unmapped a chunk. */
3447 uint32_t cLargePages; /**< The number of large pages. */
3448 uint32_t cLargePagesDisabled; /**< The number of disabled large pages. */
3449/* uint32_t aAlignment4[1]; */
3450
3451 /** The number of times we were forced to change the hypervisor region location. */
3452 STAMCOUNTER cRelocations;
3453
3454 STAMCOUNTER StatLargePageReused; /**< The number of large pages we've reused.*/
3455 STAMCOUNTER StatLargePageRefused; /**< The number of times we couldn't use a large page.*/
3456 STAMCOUNTER StatLargePageRecheck; /**< The number of times we rechecked a disabled large page.*/
3457
3458 STAMPROFILE StatShModCheck; /**< Profiles shared module checks. */
3459 /** @} */
3460
3461#ifdef VBOX_WITH_STATISTICS
3462 /** @name Statistics on the heap.
3463 * @{ */
3464 R3PTRTYPE(PGMSTATS *) pStatsR3;
3465 R0PTRTYPE(PGMSTATS *) pStatsR0;
3466 /** @} */
3467#endif
3468} PGM;
3469#ifndef IN_TSTVMSTRUCTGC /* HACK */
3470# ifndef PGM_WITHOUT_MAPPINGS
3471AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
3472# endif
3473AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
3474# ifndef PGM_WITHOUT_MAPPINGS
3475AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
3476# endif
3477AssertCompileMemberAlignment(PGM, CritSectX, 8);
3478AssertCompileMemberAlignment(PGM, ChunkR3Map, 16);
3479AssertCompileMemberAlignment(PGM, PhysTlbR3, 32); /** @todo 32 byte alignment! */
3480AssertCompileMemberAlignment(PGM, PhysTlbR0, 32);
3481AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3482AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3483AssertCompileMemberAlignment(PGM, cRelocations, 8);
3484#endif /* !IN_TSTVMSTRUCTGC */
3485/** Pointer to the PGM instance data. */
3486typedef PGM *PPGM;
3487
3488
3489
3490typedef struct PGMCPUSTATS
3491{
3492 /* Common */
3493 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
3494 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
3495
3496 /* R0 only: */
3497 STAMPROFILE StatR0NpMiscfg; /**< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. */
3498 STAMCOUNTER StatR0NpMiscfgSyncPage; /**< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). */
3499
3500 /* RZ only: */
3501 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
3502 STAMPROFILE StatRZTrap0eTime2Ballooned; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. */
3503 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
3504 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
3505 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
3506 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
3507 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
3508 STAMPROFILE StatRZTrap0eTime2InvalidPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. */
3509 STAMPROFILE StatRZTrap0eTime2MakeWritable; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. */
3510 STAMPROFILE StatRZTrap0eTime2Mapping; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is the guest mappings. */
3511 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
3512 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
3513 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
3514 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
3515 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
3516 STAMPROFILE StatRZTrap0eTime2WPEmulation; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. */
3517 STAMPROFILE StatRZTrap0eTime2Wp0RoUsHack; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be enabled. */
3518 STAMPROFILE StatRZTrap0eTime2Wp0RoUsUnhack; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be disabled. */
3519 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
3520 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
3521 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
3522 STAMCOUNTER StatRZTrap0eHandlersPhysAll; /**< RC/R0: Number of traps due to physical all-access handlers. */
3523 STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /**< RC/R0: Number of the physical all-access handler traps using the optimization. */
3524 STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /**< RC/R0: Number of traps due to write-physical access handlers. */
3525 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
3526 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
3527 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: \#PF err kind */
3528 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: \#PF err kind */
3529 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: \#PF err kind */
3530 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: \#PF err kind */
3531 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: \#PF err kind */
3532 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: \#PF err kind */
3533 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: \#PF err kind */
3534 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: \#PF err kind */
3535 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: \#PF err kind */
3536 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: \#PF err kind */
3537 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: \#PF err kind */
3538 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest \#PFs. */
3539 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest \#PF to HMA or other mapping. */
3540 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
3541 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
3542 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the \#PFs. */
3543 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
3544 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
3545 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
3546 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
3547 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
3548 STAMCOUNTER StatRZDynMapMigrateInvlPg; /**< RZ: invlpg in PGMR0DynMapMigrateAutoSet. */
3549 STAMPROFILE StatRZDynMapGCPageInl; /**< RZ: Calls to pgmRZDynMapGCPageInlined. */
3550 STAMCOUNTER StatRZDynMapGCPageInlHits; /**< RZ: Hash table lookup hits. */
3551 STAMCOUNTER StatRZDynMapGCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3552 STAMCOUNTER StatRZDynMapGCPageInlRamHits; /**< RZ: 1st ram range hits. */
3553 STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /**< RZ: 1st ram range misses, takes slow path. */
3554 STAMPROFILE StatRZDynMapHCPageInl; /**< RZ: Calls to pgmRZDynMapHCPageInlined. */
3555 STAMCOUNTER StatRZDynMapHCPageInlHits; /**< RZ: Hash table lookup hits. */
3556 STAMCOUNTER StatRZDynMapHCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3557 STAMPROFILE StatRZDynMapHCPage; /**< RZ: Calls to pgmRZDynMapHCPageCommon. */
3558 STAMCOUNTER StatRZDynMapSetOptimize; /**< RZ: Calls to pgmRZDynMapOptimizeAutoSet. */
3559 STAMCOUNTER StatRZDynMapSetSearchFlushes; /**< RZ: Set search restoring to subset flushes. */
3560 STAMCOUNTER StatRZDynMapSetSearchHits; /**< RZ: Set search hits. */
3561 STAMCOUNTER StatRZDynMapSetSearchMisses; /**< RZ: Set search misses. */
3562 STAMCOUNTER StatRZDynMapPage; /**< RZ: Calls to pgmR0DynMapPage. */
3563 STAMCOUNTER StatRZDynMapPageHits0; /**< RZ: Hits at iPage+0. */
3564 STAMCOUNTER StatRZDynMapPageHits1; /**< RZ: Hits at iPage+1. */
3565 STAMCOUNTER StatRZDynMapPageHits2; /**< RZ: Hits at iPage+2. */
3566 STAMCOUNTER StatRZDynMapPageInvlPg; /**< RZ: invlpg. */
3567 STAMCOUNTER StatRZDynMapPageSlow; /**< RZ: Calls to pgmR0DynMapPageSlow. */
3568 STAMCOUNTER StatRZDynMapPageSlowLoopHits; /**< RZ: Hits in the pgmR0DynMapPageSlow search loop. */
3569 STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /**< RZ: Misses in the pgmR0DynMapPageSlow search loop. */
3570 //STAMCOUNTER StatRZDynMapPageSlowLostHits; /**< RZ: Lost hits. */
3571 STAMCOUNTER StatRZDynMapSubsets; /**< RZ: Times PGMDynMapPushAutoSubset was called. */
3572 STAMCOUNTER StatRZDynMapPopFlushes; /**< RZ: Times PGMDynMapPopAutoSubset flushes the subset. */
3573 STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /**< RZ: Set fill distribution, percent. */
3574
3575 /* HC - R3 and (maybe) R0: */
3576
3577 /* RZ & R3: */
3578 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
3579 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
3580 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
3581 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
3582 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
3583 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
3584 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
3585 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
3586 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
3587 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
3588 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
3589 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
3590 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
3591 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
3592 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3593 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
3594 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
3595 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault(). */
3596 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3597 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3598 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
3599 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
3600 STAMCOUNTER StatRZDirtyPageStale; /**< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) */
3601 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
3602 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
3603 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
3604 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
3605 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
3606 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
3607 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
3608 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3609 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3610 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
3611 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3612 STAMCOUNTER StatRZInvalidatePageSizeChanges ; /**< RC/R0: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). */
3613 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3614 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3615 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3616 STAMCOUNTER StatRZPageOutOfSyncUserWrite; /**< RC/R0: The number of times user page is out of sync was detected in \#PF. */
3617 STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. */
3618 STAMCOUNTER StatRZPageOutOfSyncBallloon; /**< RC/R0: The number of times a ballooned page was accessed (read). */
3619 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
3620 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
3621 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3622 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3623 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3624 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3625 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
3626
3627 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
3628 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
3629 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
3630 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
3631 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
3632 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
3633 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
3634 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
3635 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
3636 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
3637 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
3638 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
3639 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
3640 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
3641 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3642 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
3643 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
3644 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
3645 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3646 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3647 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
3648 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
3649 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
3650 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
3651 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
3652 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
3653 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
3654 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
3655 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
3656 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3657 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
3658 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3659 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3660 STAMCOUNTER StatR3InvalidatePageSizeChanges ; /**< R3: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). */
3661 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3662 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3663 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3664 STAMCOUNTER StatR3PageOutOfSyncUserWrite; /**< R3: The number of times user page is out of sync was detected in \#PF. */
3665 STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF. */
3666 STAMCOUNTER StatR3PageOutOfSyncBallloon; /**< R3: The number of times a ballooned page was accessed (read). */
3667 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
3668 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
3669 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3670 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3671 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3672 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3673 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
3674} PGMCPUSTATS;
3675
3676
3677/**
3678 * Converts a PGMCPU pointer into a VM pointer.
3679 * @returns Pointer to the VM structure the PGM is part of.
3680 * @param pPGM Pointer to PGMCPU instance data.
3681 */
3682#define PGMCPU2VM(pPGM) ( (PVM)((char*)(pPGM) - (pPGM)->offVM) )
3683
3684/**
3685 * Converts a PGMCPU pointer into a PGM pointer.
3686 * @returns Pointer to the VM structure the PGM is part of.
3687 * @param pPGMCpu Pointer to PGMCPU instance data.
3688 */
3689#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char *)(pPGMCpu) - (pPGMCpu)->offPGM) )
3690
3691/**
3692 * PGMCPU Data (part of VMCPU).
3693 */
3694typedef struct PGMCPU
3695{
3696 /** Offset to the VM structure. */
3697 int32_t offVM;
3698 /** Offset to the VMCPU structure. */
3699 int32_t offVCpu;
3700 /** Offset of the PGM structure relative to VMCPU. */
3701 int32_t offPGM;
3702 uint32_t uPadding0; /**< structure size alignment. */
3703
3704#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3705 /** Automatically tracked physical memory mapping set.
3706 * Ring-0 and strict raw-mode builds. */
3707 PGMMAPSET AutoSet;
3708#endif
3709
3710 /** A20 gate mask.
3711 * Our current approach to A20 emulation is to let REM do it and don't bother
3712 * anywhere else. The interesting Guests will be operating with it enabled anyway.
3713 * But whould need arrise, we'll subject physical addresses to this mask. */
3714 RTGCPHYS GCPhysA20Mask;
3715 /** A20 gate state - boolean! */
3716 bool fA20Enabled;
3717 /** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3718 bool fNoExecuteEnabled;
3719 /** Unused bits. */
3720 bool afUnused[2];
3721
3722 /** What needs syncing (PGM_SYNC_*).
3723 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3724 * PGMFlushTLB, and PGMR3Load. */
3725 uint32_t fSyncFlags;
3726
3727 /** The shadow paging mode. */
3728 PGMMODE enmShadowMode;
3729 /** The guest paging mode. */
3730 PGMMODE enmGuestMode;
3731 /** Guest mode data table index (PGM_TYPE_XXX). */
3732 uint8_t volatile idxGuestModeData;
3733 /** Shadow mode data table index (PGM_TYPE_XXX). */
3734 uint8_t volatile idxShadowModeData;
3735 /** Both mode data table index (complicated). */
3736 uint8_t volatile idxBothModeData;
3737 /** Alignment padding. */
3738 uint8_t abPadding[5];
3739
3740 /** The current physical address represented in the guest CR3 register. */
3741 RTGCPHYS GCPhysCR3;
3742
3743 /** @name 32-bit Guest Paging.
3744 * @{ */
3745 /** The guest's page directory, R3 pointer. */
3746 R3PTRTYPE(PX86PD) pGst32BitPdR3;
3747#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3748 /** The guest's page directory, R0 pointer. */
3749 R0PTRTYPE(PX86PD) pGst32BitPdR0;
3750#endif
3751 /** Mask containing the MBZ bits of a big page PDE. */
3752 uint32_t fGst32BitMbzBigPdeMask;
3753 /** Set if the page size extension (PSE) is enabled. */
3754 bool fGst32BitPageSizeExtension;
3755 /** Alignment padding. */
3756 bool afAlignment2[3];
3757 /** @} */
3758
3759 /** @name PAE Guest Paging.
3760 * @{ */
3761 /** The guest's page directory pointer table, R3 pointer. */
3762 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3763#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3764 /** The guest's page directory pointer table, R0 pointer. */
3765 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3766#endif
3767
3768 /** The guest's page directories, R3 pointers.
3769 * These are individual pointers and don't have to be adjacent.
3770 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3771 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3772 /** The guest's page directories, R0 pointers.
3773 * Same restrictions as apGstPaePDsR3. */
3774#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3775 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3776#endif
3777 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC.
3778 * @todo Remove this and use aGstPaePdpeRegs instead? */
3779 RTGCPHYS aGCPhysGstPaePDs[4];
3780 /** The values of the 4 PDPE CPU registers (PAE). */
3781 X86PDPE aGstPaePdpeRegs[4];
3782 /** The physical addresses of the monitored guest page directories (PAE). */
3783 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
3784 /** Mask containing the MBZ PTE bits. */
3785 uint64_t fGstPaeMbzPteMask;
3786 /** Mask containing the MBZ PDE bits. */
3787 uint64_t fGstPaeMbzPdeMask;
3788 /** Mask containing the MBZ big page PDE bits. */
3789 uint64_t fGstPaeMbzBigPdeMask;
3790 /** Mask containing the MBZ PDPE bits. */
3791 uint64_t fGstPaeMbzPdpeMask;
3792 /** @} */
3793
3794 /** @name AMD64 Guest Paging.
3795 * @{ */
3796 /** The guest's page directory pointer table, R3 pointer. */
3797 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3798#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3799 /** The guest's page directory pointer table, R0 pointer. */
3800 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3801#else
3802 RTR0PTR alignment6b; /**< alignment equalizer. */
3803#endif
3804 /** Mask containing the MBZ PTE bits. */
3805 uint64_t fGstAmd64MbzPteMask;
3806 /** Mask containing the MBZ PDE bits. */
3807 uint64_t fGstAmd64MbzPdeMask;
3808 /** Mask containing the MBZ big page PDE bits. */
3809 uint64_t fGstAmd64MbzBigPdeMask;
3810 /** Mask containing the MBZ PDPE bits. */
3811 uint64_t fGstAmd64MbzPdpeMask;
3812 /** Mask containing the MBZ big page PDPE bits. */
3813 uint64_t fGstAmd64MbzBigPdpeMask;
3814 /** Mask containing the MBZ PML4E bits. */
3815 uint64_t fGstAmd64MbzPml4eMask;
3816 /** Mask containing the PDPE bits that we shadow. */
3817 uint64_t fGstAmd64ShadowedPdpeMask;
3818 /** Mask containing the PML4E bits that we shadow. */
3819 uint64_t fGstAmd64ShadowedPml4eMask;
3820 /** @} */
3821
3822 /** @name PAE and AMD64 Guest Paging.
3823 * @{ */
3824 /** Mask containing the PTE bits that we shadow. */
3825 uint64_t fGst64ShadowedPteMask;
3826 /** Mask containing the PDE bits that we shadow. */
3827 uint64_t fGst64ShadowedPdeMask;
3828 /** Mask containing the big page PDE bits that we shadow in the PDE. */
3829 uint64_t fGst64ShadowedBigPdeMask;
3830 /** Mask containing the big page PDE bits that we shadow in the PTE. */
3831 uint64_t fGst64ShadowedBigPde4PteMask;
3832 /** @} */
3833
3834 /** Pointer to the page of the current active CR3 - R3 Ptr. */
3835 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3836 /** Pointer to the page of the current active CR3 - R0 Ptr. */
3837 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3838
3839 /** For saving stack space, the disassembler state is allocated here instead of
3840 * on the stack. */
3841 DISCPUSTATE DisState;
3842
3843 /** Counts the number of times the netware WP0+RO+US hack has been applied. */
3844 uint64_t cNetwareWp0Hacks;
3845
3846 /** Count the number of pgm pool access handler calls. */
3847 uint64_t cPoolAccessHandler;
3848
3849 /** @name Release Statistics
3850 * @{ */
3851 /** The number of times the guest has switched mode since last reset or statistics reset. */
3852 STAMCOUNTER cGuestModeChanges;
3853 /** The number of times the guest has switched mode since last reset or statistics reset. */
3854 STAMCOUNTER cA20Changes;
3855 /** @} */
3856
3857#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
3858 /** @name Statistics
3859 * @{ */
3860 /** R0: Pointer to the statistics. */
3861 R0PTRTYPE(PGMCPUSTATS *) pStatsR0;
3862 /** R0: Which statistic this \#PF should be attributed to. */
3863 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3864 /** R3: Pointer to the statistics. */
3865 R3PTRTYPE(PGMCPUSTATS *) pStatsR3;
3866 /** Alignment padding. */
3867 RTR3PTR pPaddingR3;
3868 /** @} */
3869#endif /* VBOX_WITH_STATISTICS */
3870} PGMCPU;
3871/** Pointer to the per-cpu PGM data. */
3872typedef PGMCPU *PPGMCPU;
3873
3874
3875/** @name PGM::fSyncFlags Flags
3876 * @note Was part of saved state a long time ago.
3877 * @{
3878 */
3879/* 0 used to be PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL */
3880/** Always sync CR3. */
3881#define PGM_SYNC_ALWAYS RT_BIT(1)
3882/** Check monitoring on next CR3 (re)load and invalidate page.
3883 * @todo This is obsolete now. Remove after 2.2.0 is branched off. */
3884#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
3885/** Check guest mapping in SyncCR3. */
3886#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3887/** Clear the page pool (a light weight flush). */
3888#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3889#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3890/** @} */
3891
3892
3893/**
3894 * PGM GVM instance data.
3895 */
3896typedef struct PGMR0PERVM
3897{
3898 /** @name PGM Pool related stuff.
3899 * @{ */
3900 /** Critical section for serializing pool growth. */
3901 RTCRITSECT PoolGrowCritSect;
3902 /** The memory objects for the pool pages. */
3903 RTR0MEMOBJ ahPoolMemObjs[(PGMPOOL_IDX_LAST + PGMPOOL_CFG_MAX_GROW - 1) / PGMPOOL_CFG_MAX_GROW];
3904 /** The ring-3 mapping objects for the pool pages. */
3905 RTR0MEMOBJ ahPoolMapObjs[(PGMPOOL_IDX_LAST + PGMPOOL_CFG_MAX_GROW - 1) / PGMPOOL_CFG_MAX_GROW];
3906 /** @} */
3907} PGMR0PERVM;
3908
3909RT_C_DECLS_BEGIN
3910
3911#if defined(VBOX_STRICT) && defined(IN_RING3)
3912int pgmLockDebug(PVMCC pVM, RT_SRC_POS_DECL);
3913# define pgmLock(a_pVM) pgmLockDebug(a_pVM, RT_SRC_POS)
3914#else
3915int pgmLock(PVMCC pVM);
3916#endif
3917void pgmUnlock(PVM pVM);
3918/**
3919 * Asserts that the caller owns the PDM lock.
3920 * This is the internal variant of PGMIsLockOwner.
3921 * @param a_pVM Pointer to the VM.
3922 */
3923#define PGM_LOCK_ASSERT_OWNER(a_pVM) Assert(PDMCritSectIsOwner(&(a_pVM)->pgm.s.CritSectX))
3924/**
3925 * Asserts that the caller owns the PDM lock.
3926 * This is the internal variant of PGMIsLockOwner.
3927 * @param a_pVM Pointer to the VM.
3928 * @param a_pVCpu The current CPU handle.
3929 */
3930#define PGM_LOCK_ASSERT_OWNER_EX(a_pVM, a_pVCpu) Assert(PDMCritSectIsOwnerEx(&(a_pVM)->pgm.s.CritSectX, a_pVCpu))
3931
3932#ifndef PGM_WITHOUT_MAPPINGS
3933int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
3934int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
3935int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
3936int pgmMapResolveConflicts(PVM pVM);
3937PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3938DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3939#endif /* !PGM_WITHOUT_MAPPINGS */
3940
3941int pgmHandlerPhysicalExCreate(PVMCC pVM, PGMPHYSHANDLERTYPE hType, RTR3PTR pvUserR3, RTR0PTR pvUserR0,
3942 RTRCPTR pvUserRC, R3PTRTYPE(const char *) pszDesc, PPGMPHYSHANDLER *ppPhysHandler);
3943int pgmHandlerPhysicalExDup(PVMCC pVM, PPGMPHYSHANDLER pPhysHandlerSrc, PPGMPHYSHANDLER *ppPhysHandler);
3944int pgmHandlerPhysicalExRegister(PVMCC pVM, PPGMPHYSHANDLER pPhysHandler, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
3945int pgmHandlerPhysicalExDeregister(PVMCC pVM, PPGMPHYSHANDLER pPhysHandler, int fRestoreAsRAM);
3946int pgmHandlerPhysicalExDestroy(PVMCC pVM, PPGMPHYSHANDLER pHandler);
3947void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3948bool pgmHandlerPhysicalIsAll(PVMCC pVM, RTGCPHYS GCPhys);
3949void pgmHandlerPhysicalResetAliasedPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, bool fDoAccounting);
3950DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3951int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3952
3953int pgmPhysAllocPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3954int pgmPhysAllocLargePage(PVMCC pVM, RTGCPHYS GCPhys);
3955int pgmPhysRecheckLargePage(PVMCC pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
3956int pgmPhysPageLoadIntoTlb(PVMCC pVM, RTGCPHYS GCPhys);
3957int pgmPhysPageLoadIntoTlbWithPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3958void pgmPhysPageMakeWriteMonitoredWritable(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3959int pgmPhysPageMakeWritable(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3960int pgmPhysPageMakeWritableAndMap(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3961int pgmPhysPageMap(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3962int pgmPhysPageMapReadOnly(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3963int pgmPhysPageMapByPageID(PVMCC pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3964int pgmPhysGCPhys2R3Ptr(PVMCC pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
3965int pgmPhysCr3ToHCPtr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
3966int pgmPhysGCPhys2CCPtrInternalDepr(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3967int pgmPhysGCPhys2CCPtrInternal(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
3968int pgmPhysGCPhys2CCPtrInternalReadOnly(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv, PPGMPAGEMAPLOCK pLock);
3969void pgmPhysReleaseInternalPageMappingLock(PVMCC pVM, PPGMPAGEMAPLOCK pLock);
3970PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) pgmPhysRomWriteHandler;
3971#ifndef IN_RING3
3972DECLEXPORT(FNPGMPHYSHANDLER) pgmPhysHandlerRedirectToHC;
3973DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysPfHandlerRedirectToHC;
3974DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysRomWritePfHandler;
3975#endif
3976int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys,
3977 PGMPAGETYPE enmNewType);
3978void pgmPhysInvalidRamRangeTlbs(PVMCC pVM);
3979void pgmPhysInvalidatePageMapTLB(PVMCC pVM);
3980void pgmPhysInvalidatePageMapTLBEntry(PVM pVM, RTGCPHYS GCPhys);
3981PPGMRAMRANGE pgmPhysGetRangeSlow(PVM pVM, RTGCPHYS GCPhys);
3982PPGMRAMRANGE pgmPhysGetRangeAtOrAboveSlow(PVM pVM, RTGCPHYS GCPhys);
3983PPGMPAGE pgmPhysGetPageSlow(PVM pVM, RTGCPHYS GCPhys);
3984int pgmPhysGetPageExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage);
3985int pgmPhysGetPageAndRangeExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam);
3986
3987#ifdef IN_RING3
3988void pgmR3PhysRelinkRamRanges(PVM pVM);
3989int pgmR3PhysRamPreAllocate(PVM pVM);
3990int pgmR3PhysRamReset(PVM pVM);
3991int pgmR3PhysRomReset(PVM pVM);
3992int pgmR3PhysRamZeroAll(PVM pVM);
3993int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3994int pgmR3PhysRamTerm(PVM pVM);
3995void pgmR3PhysRomTerm(PVM pVM);
3996void pgmR3PhysAssertSharedPageChecksums(PVM pVM);
3997
3998int pgmR3PoolInit(PVM pVM);
3999void pgmR3PoolRelocate(PVM pVM);
4000void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
4001void pgmR3PoolReset(PVM pVM);
4002void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
4003DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
4004void pgmR3PoolWriteProtectPages(PVM pVM);
4005
4006#endif /* IN_RING3 */
4007#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4008int pgmRZDynMapHCPageCommon(PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
4009int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
4010# ifdef LOG_ENABLED
4011void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint, RT_SRC_POS_DECL);
4012# else
4013void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint);
4014# endif
4015#endif
4016int pgmPoolAlloc(PVMCC pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
4017 uint16_t iUser, uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
4018void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
4019void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
4020int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
4021void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
4022PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
4023PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
4024int pgmPoolHCPhys2Ptr(PVM pVM, RTHCPHYS HCPhys, void **ppv);
4025int pgmPoolSyncCR3(PVMCPUCC pVCpu);
4026bool pgmPoolIsDirtyPageSlow(PVM pVM, RTGCPHYS GCPhys);
4027void pgmPoolInvalidateDirtyPage(PVMCC pVM, RTGCPHYS GCPhysPT);
4028int pgmPoolTrackUpdateGCPhys(PVMCC pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
4029void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
4030uint16_t pgmPoolTrackPhysExtAddref(PVMCC pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
4031void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
4032void pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4033void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4034PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) pgmPoolAccessHandler;
4035#ifndef IN_RING3
4036DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmRZPoolAccessPfHandler;
4037#endif
4038
4039void pgmPoolAddDirtyPage(PVMCC pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4040void pgmPoolResetDirtyPages(PVMCC pVM);
4041void pgmPoolResetDirtyPage(PVM pVM, RTGCPTR GCPtrPage);
4042
4043int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu);
4044int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
4045void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu);
4046
4047#ifndef PGM_WITHOUT_MAPPINGS
4048void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
4049void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
4050int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
4051int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
4052#endif
4053
4054int pgmShwMakePageSupervisorAndWritable(PVMCPUCC pVCpu, RTGCPTR GCPtr, bool fBigPage, uint32_t fOpFlags);
4055int pgmShwSyncPaePDPtr(PVMCPUCC pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
4056int pgmShwSyncNestedPageLocked(PVMCPUCC pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
4057
4058int pgmGstLazyMap32BitPD(PVMCPUCC pVCpu, PX86PD *ppPd);
4059int pgmGstLazyMapPaePDPT(PVMCPUCC pVCpu, PX86PDPT *ppPdpt);
4060int pgmGstLazyMapPaePD(PVMCPUCC pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
4061int pgmGstLazyMapPml4(PVMCPUCC pVCpu, PX86PML4 *ppPml4);
4062int pgmGstPtWalk(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk);
4063int pgmGstPtWalkNext(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk);
4064
4065# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64 && defined(IN_RING3)
4066FNDBGCCMD pgmR3CmdCheckDuplicatePages;
4067FNDBGCCMD pgmR3CmdShowSharedModules;
4068# endif
4069
4070void pgmLogState(PVM pVM);
4071
4072RT_C_DECLS_END
4073
4074/** @} */
4075
4076#endif /* !VMM_INCLUDED_SRC_include_PGMInternal_h */
4077
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