PGMInternal.h@ 100965

最後變更在這個檔案從100965是 100965,由 vboxsync 提交於 19 月前
VMM/PGM,++: Removing some CSAM traces.
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1	/* $Id: PGMInternal.h 100965 2023-08-24 21:25:53Z vboxsync $ */
2	/** @file
3	* PGM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.alldomusa.eu.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_PGMInternal_h
29	#define VMM_INCLUDED_SRC_include_PGMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#include <VBox/cdefs.h>
35	#include <VBox/types.h>
36	#include <VBox/err.h>
37	#include <VBox/dbg.h>
38	#include <VBox/vmm/stam.h>
39	#include <VBox/param.h>
40	#include <VBox/vmm/vmm.h>
41	#include <VBox/vmm/mm.h>
42	#include <VBox/vmm/pdmcritsect.h>
43	#include <VBox/vmm/pdmapi.h>
44	#include <VBox/dis.h>
45	#include <VBox/vmm/dbgf.h>
46	#include <VBox/log.h>
47	#include <VBox/vmm/gmm.h>
48	#include <VBox/vmm/hm.h>
49	#include <iprt/asm.h>
50	#include <iprt/assert.h>
51	#include <iprt/avl.h>
52	#include <iprt/critsect.h>
53	#include <iprt/list-off32.h>
54	#include <iprt/sha.h>
55	#include <iprt/cpp/hardavlrange.h>
56
57
58
59	/** @defgroup grp_pgm_int Internals
60	* @ingroup grp_pgm
61	* @internal
62	* @{
63	*/
64
65
66	/** @name PGM Compile Time Config
67	* @{
68	*/
69
70	/**
71	* Check and skip global PDEs for non-global flushes
72	*/
73	#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
74
75	/**
76	* Optimization for PAE page tables that are modified often
77	*/
78	#ifndef VBOX_VMM_TARGET_ARMV8
79	# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
80	#endif
81
82	/**
83	* Large page support enabled only on 64 bits hosts; applies to nested paging only.
84	*/
85	#define PGM_WITH_LARGE_PAGES
86
87	/**
88	* Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
89	* VMX_EXIT_EPT_MISCONFIG.
90	*/
91	#define PGM_WITH_MMIO_OPTIMIZATIONS
92
93	/**
94	* Sync N pages instead of a whole page table
95	*/
96	#define PGM_SYNC_N_PAGES
97
98	/**
99	* Number of pages to sync during a page fault
100	*
101	* When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
102	* causes a lot of unnecessary extents and also is slower than taking more \#PFs.
103	*
104	* Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
105	* world switch overhead, so let's sync more.
106	*/
107	#ifdef IN_RING0
108	/* Chose 32 based on the compile test in @bugref{4219}; 64 shows worse stats.
109	* 32 again shows better results than 16; slightly more overhead in the \#PF handler,
110	* but ~5% fewer faults.
111	*/
112	# define PGM_SYNC_NR_PAGES 32
113	#else
114	# define PGM_SYNC_NR_PAGES 8
115	#endif
116
117	/**
118	* Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
119	*/
120	#define PGM_MAX_PHYSCACHE_ENTRIES 64
121	#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
122
123
124	/** @def PGMPOOL_CFG_MAX_GROW
125	* The maximum number of pages to add to the pool in one go.
126	*/
127	#define PGMPOOL_CFG_MAX_GROW (_2M >> GUEST_PAGE_SHIFT) /** @todo or HOST_PAGE_SHIFT ? */
128
129	/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
130	* Enables some extra assertions for virtual handlers (mainly phys2virt related).
131	*/
132	#ifdef VBOX_STRICT
133	# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
134	#endif
135
136	/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
137	* Enables the experimental lazy page allocation code.
138	* @todo Problems with zero page tracking, see @bugref{}. */
139	#if defined(DOXYGEN_RUNNING)
140	# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC
141	#endif
142
143	/** @def PGM_WITH_PAGE_ZEROING_DETECTION
144	* Enables the code for detecting guest zeroing page in the ZERO state and
145	* tries to avoid allocating them in response.
146	* This kind of relies upon VBOX_WITH_NEW_LAZY_PAGE_ALLOC to work atm. */
147	#if defined(DOXYGEN_RUNNING)
148	# define PGM_WITH_PAGE_ZEROING_DETECTION
149	#endif
150
151	/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
152	* Enables real write monitoring of pages, i.e. mapping them read-only and
153	* only making them writable when getting a write access \#PF. */
154	#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
155
156	/** @def VBOX_WITH_PGM_NEM_MODE
157	* Enabled the NEM memory management mode in PGM. See PGM::fNemMode for
158	* details. */
159	#ifdef DOXYGEN_RUNNING
160	# define VBOX_WITH_PGM_NEM_MODE
161	#endif
162
163	/** @} */
164
165
166	/** @name PDPT and PML4 flags.
167	* These are placed in the three bits available for system programs in
168	* the PDPT and PML4 entries.
169	* @{ */
170	/** The entry is a permanent one and it's must always be present.
171	* Never free such an entry. */
172	#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
173	/** PGM specific bits in PML4 entries. */
174	#define PGM_PML4_FLAGS 0
175	/** PGM specific bits in PDPT entries. */
176	#define PGM_PDPT_FLAGS (PGM_PLXFLAGS_PERMANENT)
177	/** @} */
178
179	/** @name Page directory flags.
180	* These are placed in the three bits available for system programs in
181	* the page directory entries.
182	* @{ */
183	/** Indicates the original entry was a big page.
184	* @remarks This is currently only used for statistics and can be recycled. */
185	#define PGM_PDFLAGS_BIG_PAGE RT_BIT_64(9)
186	/** Made read-only to facilitate dirty bit tracking. */
187	#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
188	/** @} */
189
190	/** @name Page flags.
191	* These are placed in the three bits available for system programs in
192	* the page entries.
193	* @{ */
194	/** Made read-only to facilitate dirty bit tracking. */
195	#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
196	/** @} */
197
198	/** @name Defines used to indicate the shadow and guest paging in the templates.
199	* @{ */
200	#define PGM_TYPE_REAL 1
201	#define PGM_TYPE_PROT 2
202	#define PGM_TYPE_32BIT 3
203	#define PGM_TYPE_PAE 4
204	#define PGM_TYPE_AMD64 5
205	#define PGM_TYPE_NESTED_32BIT 6
206	#define PGM_TYPE_NESTED_PAE 7
207	#define PGM_TYPE_NESTED_AMD64 8
208	#define PGM_TYPE_EPT 9
209	#define PGM_TYPE_NONE 10 /*< Dummy shadow paging mode for NEM. /
210	#define PGM_TYPE_END (PGM_TYPE_NONE + 1)
211	#define PGM_TYPE_FIRST_SHADOW PGM_TYPE_32BIT /*< The first type used by shadow paging. /
212	/** @} */
213
214	/** @name Defines used to indicate the second-level
215	* address translation (SLAT) modes in the templates.
216	* @{ */
217	#define PGM_SLAT_TYPE_DIRECT (PGM_TYPE_END + 1)
218	#define PGM_SLAT_TYPE_EPT (PGM_TYPE_END + 2)
219	#define PGM_SLAT_TYPE_32BIT (PGM_TYPE_END + 3)
220	#define PGM_SLAT_TYPE_PAE (PGM_TYPE_END + 4)
221	#define PGM_SLAT_TYPE_AMD64 (PGM_TYPE_END + 5)
222	/** @} */
223
224	/** Macro for checking if the guest is using paging.
225	* @param uGstType PGM_TYPE_*
226	* @param uShwType PGM_TYPE_*
227	* @remark ASSUMES certain order of the PGM_TYPE_* values.
228	*/
229	#define PGM_WITH_PAGING(uGstType, uShwType) \
230	( (uGstType) >= PGM_TYPE_32BIT \
231	&& (uShwType) < PGM_TYPE_NESTED_32BIT)
232
233	/** Macro for checking if the guest supports the NX bit.
234	* @param uGstType PGM_TYPE_*
235	* @param uShwType PGM_TYPE_*
236	* @remark ASSUMES certain order of the PGM_TYPE_* values.
237	*/
238	#define PGM_WITH_NX(uGstType, uShwType) \
239	( (uGstType) >= PGM_TYPE_PAE \
240	&& (uShwType) < PGM_TYPE_NESTED_32BIT)
241
242	/** Macro for checking for nested.
243	* @param uType PGM_TYPE_*
244	*/
245	#define PGM_TYPE_IS_NESTED(uType) \
246	( (uType) == PGM_TYPE_NESTED_32BIT \
247	\|\| (uType) == PGM_TYPE_NESTED_PAE \
248	\|\| (uType) == PGM_TYPE_NESTED_AMD64)
249
250	/** Macro for checking for nested or EPT.
251	* @param uType PGM_TYPE_*
252	*/
253	#define PGM_TYPE_IS_NESTED_OR_EPT(uType) \
254	( (uType) == PGM_TYPE_NESTED_32BIT \
255	\|\| (uType) == PGM_TYPE_NESTED_PAE \
256	\|\| (uType) == PGM_TYPE_NESTED_AMD64 \
257	\|\| (uType) == PGM_TYPE_EPT)
258
259
260
261	/** @def PGM_HCPHYS_2_PTR
262	* Maps a HC physical page pool address to a virtual address.
263	*
264	* @returns VBox status code.
265	* @param pVM The cross context VM structure.
266	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
267	* @param HCPhys The HC physical address to map to a virtual one.
268	* @param ppv Where to store the virtual address. No need to cast
269	* this.
270	*
271	* @remark There is no need to assert on the result.
272	*/
273	#define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) pgmPoolHCPhys2Ptr(pVM, HCPhys, (void **)(ppv))
274
275	/** @def PGM_GCPHYS_2_PTR_V2
276	* Maps a GC physical page address to a virtual address.
277	*
278	* @returns VBox status code.
279	* @param pVM The cross context VM structure.
280	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
281	* @param GCPhys The GC physical address to map to a virtual one.
282	* @param ppv Where to store the virtual address. No need to cast this.
283	*
284	* @remark Use with care as we don't have so much dynamic mapping space in
285	* ring-0 on 32-bit darwin and in RC.
286	* @remark There is no need to assert on the result.
287	*/
288	#define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
289	pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
290
291	/** @def PGM_GCPHYS_2_PTR
292	* Maps a GC physical page address to a virtual address.
293	*
294	* @returns VBox status code.
295	* @param pVM The cross context VM structure.
296	* @param GCPhys The GC physical address to map to a virtual one.
297	* @param ppv Where to store the virtual address. No need to cast this.
298	*
299	* @remark Use with care as we don't have so much dynamic mapping space in
300	* ring-0 on 32-bit darwin and in RC.
301	* @remark There is no need to assert on the result.
302	*/
303	#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
304
305	/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
306	* Maps a GC physical page address to a virtual address.
307	*
308	* @returns VBox status code.
309	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
310	* @param GCPhys The GC physical address to map to a virtual one.
311	* @param ppv Where to store the virtual address. No need to cast this.
312	*
313	* @remark Use with care as we don't have so much dynamic mapping space in
314	* ring-0 on 32-bit darwin and in RC.
315	* @remark There is no need to assert on the result.
316	*/
317	#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
318
319	/** @def PGM_GCPHYS_2_PTR_EX
320	* Maps a unaligned GC physical page address to a virtual address.
321	*
322	* @returns VBox status code.
323	* @param pVM The cross context VM structure.
324	* @param GCPhys The GC physical address to map to a virtual one.
325	* @param ppv Where to store the virtual address. No need to cast this.
326	*
327	* @remark Use with care as we don't have so much dynamic mapping space in
328	* ring-0 on 32-bit darwin and in RC.
329	* @remark There is no need to assert on the result.
330	*/
331	#define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
332	pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
333
334	/** @def PGM_DYNMAP_UNUSED_HINT
335	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
336	* is no longer used.
337	*
338	* For best effect only apply this to the page that was mapped most recently.
339	*
340	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
341	* @param pvPage The pool page.
342	*/
343	#define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
344
345	/** @def PGM_DYNMAP_UNUSED_HINT_VM
346	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
347	* is no longer used.
348	*
349	* For best effect only apply this to the page that was mapped most recently.
350	*
351	* @param pVM The cross context VM structure.
352	* @param pvPage The pool page.
353	*/
354	#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
355
356
357	/** @def PGM_INVL_PG
358	* Invalidates a page.
359	*
360	* @param pVCpu The cross context virtual CPU structure.
361	* @param GCVirt The virtual address of the page to invalidate.
362	*/
363	#ifdef IN_RING0
364	# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
365	#elif defined(IN_RING3)
366	# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
367	#else
368	# error "Not IN_RING0 or IN_RING3!"
369	#endif
370
371	/** @def PGM_INVL_PG_ALL_VCPU
372	* Invalidates a page on all VCPUs
373	*
374	* @param pVM The cross context VM structure.
375	* @param GCVirt The virtual address of the page to invalidate.
376	*/
377	#if defined(VBOX_VMM_TARGET_ARMV8)
378	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) do { } while(0)
379	#else
380	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
381	#endif
382
383	/** @def PGM_INVL_BIG_PG
384	* Invalidates a 4MB page directory entry.
385	*
386	* @param pVCpu The cross context virtual CPU structure.
387	* @param GCVirt The virtual address within the page directory to invalidate.
388	*/
389	#if defined(VBOX_VMM_TARGET_ARMV8)
390	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) do { } while(0)
391	#else
392	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTlb(pVCpu)
393	#endif
394
395	/** @def PGM_INVL_VCPU_TLBS()
396	* Invalidates the TLBs of the specified VCPU
397	*
398	* @param pVCpu The cross context virtual CPU structure.
399	*/
400	#if defined(VBOX_VMM_TARGET_ARMV8)
401	# define PGM_INVL_VCPU_TLBS(pVCpu) do { } while(0)
402	#else
403	# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTlb(pVCpu)
404	#endif
405
406	/** @def PGM_INVL_ALL_VCPU_TLBS()
407	* Invalidates the TLBs of all VCPUs
408	*
409	* @param pVM The cross context VM structure.
410	*/
411	#if defined(VBOX_VMM_TARGET_ARMV8)
412	# define PGM_INVL_ALL_VCPU_TLBS(pVM) do { } while(0)
413	#else
414	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTlbOnAllVCpus(pVM)
415	#endif
416
417
418	/** @name Safer Shadow PAE PT/PTE
419	* For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
420	* present.
421	*
422	* @{
423	*/
424	#if 1
425	/**
426	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
427	* invalid entries for present.
428	* @sa X86PTEPAE.
429	*/
430	typedef union PGMSHWPTEPAE
431	{
432	/** Unsigned integer view */
433	X86PGPAEUINT uCareful;
434	/* Not other views. */
435	} PGMSHWPTEPAE;
436
437	# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
438	# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
439	# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
440	# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
441	# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
442	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
443	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_RW \| X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P \| X86_PTE_RW) )
444	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
445	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
446	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /*< Use with care. /
447	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
448	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
449	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
450	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
451	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
452	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful \|= X86_PTE_RW; } while (0)
453
454	/**
455	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
456	* invalid entries for present.
457	* @sa X86PTPAE.
458	*/
459	typedef struct PGMSHWPTPAE
460	{
461	PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
462	} PGMSHWPTPAE;
463
464	#else
465	typedef X86PTEPAE PGMSHWPTEPAE;
466	typedef X86PTPAE PGMSHWPTPAE;
467	# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
468	# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
469	# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
470	# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
471	# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
472	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
473	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P \| X86_PTE_RW)) == (X86_PTE_P \| X86_PTE_RW) )
474	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
475	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
476	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /*< Use with care. /
477	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
478	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
479	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
480	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
481	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
482	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u \|= X86_PTE_RW; } while (0)
483
484	#endif
485
486	/** Pointer to a shadow PAE PTE. */
487	typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
488	/** Pointer to a const shadow PAE PTE. */
489	typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
490
491	/** Pointer to a shadow PAE page table. */
492	typedef PGMSHWPTPAE *PPGMSHWPTPAE;
493	/** Pointer to a const shadow PAE page table. */
494	typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
495	/** @} */
496
497
498	/** The physical access handler type handle count (power of two). */
499	#define PGMPHYSHANDLERTYPE_COUNT 0x20
500	/** Mask for getting the array index from an access handler type handle.
501	* The other handle bits are random and non-zero to avoid mixups due to zero
502	* initialized fields. */
503	#define PGMPHYSHANDLERTYPE_IDX_MASK 0x1f
504
505	/**
506	* Physical page access handler type registration, ring-0 part.
507	*/
508	typedef struct PGMPHYSHANDLERTYPEINTR0
509	{
510	/** The handle value for verfication. */
511	PGMPHYSHANDLERTYPE hType;
512	/** The kind of accesses we're handling. */
513	PGMPHYSHANDLERKIND enmKind;
514	/** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
515	uint8_t uState;
516	/** Whether to keep the PGM lock when calling the handler.
517	* @sa PGMPHYSHANDLER_F_KEEP_PGM_LOCK */
518	bool fKeepPgmLock;
519	/** Set if this is registered by a device instance and uUser should be
520	* translated from a device instance ID to a pointer.
521	* @sa PGMPHYSHANDLER_F_R0_DEVINS_IDX */
522	bool fRing0DevInsIdx;
523	/** See PGMPHYSHANDLER_F_NOT_IN_HM. */
524	bool fNotInHm : 1;
525	/** Pointer to the ring-0 callback function. */
526	R0PTRTYPE(PFNPGMPHYSHANDLER) pfnHandler;
527	/** Pointer to the ring-0 callback function for \#PFs, can be NULL. */
528	R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandler;
529	/** Description / Name. For easing debugging. */
530	R0PTRTYPE(const char *) pszDesc;
531	} PGMPHYSHANDLERTYPEINTR0;
532	/** Pointer to a physical access handler type registration. */
533	typedef PGMPHYSHANDLERTYPEINTR0 *PPGMPHYSHANDLERTYPEINTR0;
534
535	/**
536	* Physical page access handler type registration, shared/ring-3 part.
537	*/
538	typedef struct PGMPHYSHANDLERTYPEINTR3
539	{
540	/** The handle value for verfication. */
541	PGMPHYSHANDLERTYPE hType;
542	/** The kind of accesses we're handling. */
543	PGMPHYSHANDLERKIND enmKind;
544	/** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
545	uint8_t uState;
546	/** Whether to keep the PGM lock when calling the handler.
547	* @sa PGMPHYSHANDLER_F_KEEP_PGM_LOCK */
548	bool fKeepPgmLock;
549	/** Set if this is registered by a device instance and uUser should be
550	* translated from a device instance ID to a pointer.
551	* @sa PGMPHYSHANDLER_F_R0_DEVINS_IDX */
552	bool fRing0DevInsIdx;
553	/** Set by ring-0 if the handler is ring-0 enabled (for debug). */
554	bool fRing0Enabled : 1;
555	/** See PGMPHYSHANDLER_F_NOT_IN_HM. */
556	bool fNotInHm : 1;
557	/** Pointer to the ring-3 callback function. */
558	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandler;
559	/** Description / Name. For easing debugging. */
560	R3PTRTYPE(const char *) pszDesc;
561	} PGMPHYSHANDLERTYPEINTR3;
562	/** Pointer to a physical access handler type registration. */
563	typedef PGMPHYSHANDLERTYPEINTR3 *PPGMPHYSHANDLERTYPEINTR3;
564
565	/** Pointer to a physical access handler type record for the current context. */
566	typedef CTX_SUFF(PPGMPHYSHANDLERTYPEINT) PPGMPHYSHANDLERTYPEINT;
567	/** Pointer to a const physical access handler type record for the current context. */
568	typedef CTX_SUFF(PGMPHYSHANDLERTYPEINT) const *PCPGMPHYSHANDLERTYPEINT;
569	/** Dummy physical access handler type record. */
570	extern CTX_SUFF(PGMPHYSHANDLERTYPEINT) const g_pgmHandlerPhysicalDummyType;
571
572
573	/**
574	* Physical page access handler structure.
575	*
576	* This is used to keep track of physical address ranges
577	* which are being monitored in some kind of way.
578	*/
579	typedef struct PGMPHYSHANDLER
580	{
581	/** @name Tree stuff.
582	* @{ */
583	/** First address. */
584	RTGCPHYS Key;
585	/** Last address. */
586	RTGCPHYS KeyLast;
587	uint32_t idxLeft;
588	uint32_t idxRight;
589	uint8_t cHeight;
590	/** @} */
591	uint8_t abPadding[3];
592	/** Number of pages to update. */
593	uint32_t cPages;
594	/** Set if we have pages that have been aliased. */
595	uint32_t cAliasedPages;
596	/** Set if we have pages that have temporarily been disabled. */
597	uint32_t cTmpOffPages;
598	/** Registered handler type handle.
599	* @note Marked volatile to prevent re-reading after validation. */
600	PGMPHYSHANDLERTYPE volatile hType;
601	/** User argument for the handlers. */
602	uint64_t uUser;
603	/** Description / Name. For easing debugging. */
604	R3PTRTYPE(const char *) pszDesc;
605	/** Profiling of this handler.
606	* @note VBOX_WITH_STATISTICS only, but included to keep structure stable. */
607	STAMPROFILE Stat;
608	} PGMPHYSHANDLER;
609	AssertCompileSize(PGMPHYSHANDLER, 12*8);
610	/** Pointer to a physical page access handler structure. */
611	typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
612
613	/**
614	* Gets the type record for a physical handler (no reference added).
615	* @returns PCPGMPHYSHANDLERTYPEINT, can be NULL
616	* @param a_pVM The cross context VM structure.
617	* @param a_pPhysHandler Pointer to the physical handler structure
618	* (PGMPHYSHANDLER).
619	*/
620	#define PGMPHYSHANDLER_GET_TYPE(a_pVM, a_pPhysHandler) \
621	pgmHandlerPhysicalTypeHandleToPtr(a_pVM, (a_pPhysHandler) ? (a_pPhysHandler)->hType : NIL_PGMPHYSHANDLERTYPE)
622
623	/**
624	* Gets the type record for a physical handler, never returns NULL.
625	*
626	* @returns PCPGMPHYSHANDLERTYPEINT, never NULL.
627	* @param a_pVM The cross context VM structure.
628	* @param a_pPhysHandler Pointer to the physical handler structure
629	* (PGMPHYSHANDLER).
630	*/
631	#define PGMPHYSHANDLER_GET_TYPE_NO_NULL(a_pVM, a_pPhysHandler) \
632	pgmHandlerPhysicalTypeHandleToPtr2(a_pVM, (a_pPhysHandler) ? (a_pPhysHandler)->hType : NIL_PGMPHYSHANDLERTYPE)
633
634	/** Physical access handler allocator. */
635	typedef RTCHardAvlTreeSlabAllocator<PGMPHYSHANDLER> PGMPHYSHANDLERALLOCATOR;
636
637	/** Physical access handler tree. */
638	typedef RTCHardAvlRangeTree<PGMPHYSHANDLER, RTGCPHYS> PGMPHYSHANDLERTREE;
639	/** Pointer to a physical access handler tree. */
640	typedef PGMPHYSHANDLERTREE *PPGMPHYSHANDLERTREE;
641
642
643	/**
644	* A Physical Guest Page tracking structure.
645	*
646	* The format of this structure is complicated because we have to fit a lot
647	* of information into as few bits as possible. The format is also subject
648	* to change (there is one coming up soon). Which means that for we'll be
649	* using PGM_PAGE_GET_, PGM_PAGE_IS_ and PGM_PAGE_SET_ macros for all
650	* accesses to the structure.
651	*/
652	typedef union PGMPAGE
653	{
654	/** Structured view. */
655	struct
656	{
657	/** 1:0 - The physical handler state (PGM_PAGE_HNDL_PHYS_STATE_). /
658	uint64_t u2HandlerPhysStateY : 2;
659	/** 2 - Don't apply the physical handler in HM mode (nested APIC hack). */
660	uint64_t fHandlerPhysNotInHm : 1;
661	/** 3 - Flag indicating that a write monitored page was written to
662	* when set. */
663	uint64_t fWrittenToY : 1;
664	/** 7:4 - Unused. */
665	uint64_t u2Unused0 : 4;
666	/** 9:8 - Paging structure needed to map the page
667	* (PGM_PAGE_PDE_TYPE_). /
668	uint64_t u2PDETypeY : 2;
669	/** 11:10 - NEM state bits. */
670	uint64_t u2NemStateY : 2;
671	/** 12:48 - The host physical frame number (shift left to get the
672	* address). */
673	uint64_t HCPhysFN : 36;
674	/** 50:48 - The page state. */
675	uint64_t uStateY : 3;
676	/** 51:53 - The page type (PGMPAGETYPE). */
677	uint64_t uTypeY : 3;
678	/** 63:54 - PTE index for usage tracking (page pool). */
679	uint64_t u10PteIdx : 10;
680
681	/** The GMM page ID.
682	* @remarks In the current implementation, MMIO2 and pages aliased to
683	* MMIO2 pages will be exploiting this field to calculate the
684	* ring-3 mapping address corresponding to the page.
685	* Later we may consider including MMIO2 management into GMM. */
686	uint32_t idPage;
687	/** Usage tracking (page pool). */
688	uint16_t u16TrackingY;
689	/** The number of read locks on this page. */
690	uint8_t cReadLocksY;
691	/** The number of write locks on this page. */
692	uint8_t cWriteLocksY;
693	} s;
694
695	/** 64-bit integer view. */
696	uint64_t au64[2];
697	/** 16-bit view. */
698	uint32_t au32[4];
699	/** 16-bit view. */
700	uint16_t au16[8];
701	/** 8-bit view. */
702	uint8_t au8[16];
703	} PGMPAGE;
704	AssertCompileSize(PGMPAGE, 16);
705	/** Pointer to a physical guest page. */
706	typedef PGMPAGE *PPGMPAGE;
707	/** Pointer to a const physical guest page. */
708	typedef const PGMPAGE *PCPGMPAGE;
709	/** Pointer to a physical guest page pointer. */
710	typedef PPGMPAGE *PPPGMPAGE;
711
712
713	/**
714	* Clears the page structure.
715	* @param a_pPage Pointer to the physical guest page tracking structure.
716	*/
717	#define PGM_PAGE_CLEAR(a_pPage) \
718	do { \
719	(a_pPage)->au64[0] = 0; \
720	(a_pPage)->au64[1] = 0; \
721	} while (0)
722
723	/**
724	* Initializes the page structure.
725	* @param a_pPage Pointer to the physical guest page tracking structure.
726	* @param a_HCPhys The host physical address of the page.
727	* @param a_idPage The (GMM) page ID of the page.
728	* @param a_uType The page type (PGMPAGETYPE).
729	* @param a_uState The page state (PGM_PAGE_STATE_XXX).
730	*/
731	#define PGM_PAGE_INIT(a_pPage, a_HCPhys, a_idPage, a_uType, a_uState) \
732	do { \
733	RTHCPHYS SetHCPhysTmp = (a_HCPhys); \
734	AssertFatalMsg(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000)), ("%RHp\n", SetHCPhysTmp)); \
735	(a_pPage)->au64[0] = SetHCPhysTmp; \
736	(a_pPage)->au64[1] = 0; \
737	(a_pPage)->s.idPage = (a_idPage); \
738	(a_pPage)->s.uStateY = (a_uState); \
739	(a_pPage)->s.uTypeY = (a_uType); \
740	} while (0)
741
742	/**
743	* Initializes the page structure of a ZERO page.
744	* @param a_pPage Pointer to the physical guest page tracking structure.
745	* @param a_pVM The VM handle (for getting the zero page address).
746	* @param a_uType The page type (PGMPAGETYPE).
747	*/
748	#define PGM_PAGE_INIT_ZERO(a_pPage, a_pVM, a_uType) \
749	PGM_PAGE_INIT((a_pPage), (a_pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (a_uType), PGM_PAGE_STATE_ZERO)
750
751
752	/** @name The Page state, PGMPAGE::uStateY.
753	* @{ */
754	/** The zero page.
755	* This is a per-VM page that's never ever mapped writable. */
756	#define PGM_PAGE_STATE_ZERO 0U
757	/** A allocated page.
758	* This is a per-VM page allocated from the page pool (or wherever
759	* we get MMIO2 pages from if the type is MMIO2).
760	*/
761	#define PGM_PAGE_STATE_ALLOCATED 1U
762	/** A allocated page that's being monitored for writes.
763	* The shadow page table mappings are read-only. When a write occurs, the
764	* fWrittenTo member is set, the page remapped as read-write and the state
765	* moved back to allocated. */
766	#define PGM_PAGE_STATE_WRITE_MONITORED 2U
767	/** The page is shared, aka. copy-on-write.
768	* This is a page that's shared with other VMs. */
769	#define PGM_PAGE_STATE_SHARED 3U
770	/** The page is ballooned, so no longer available for this VM. */
771	#define PGM_PAGE_STATE_BALLOONED 4U
772	/** @} */
773
774
775	/** Asserts lock ownership in some of the PGM_PAGE_XXX macros. */
776	#if defined(VBOX_STRICT) && 0 /** @todo triggers in pgmRZDynMapGCPageV2Inlined */
777	# define PGM_PAGE_ASSERT_LOCK(a_pVM) PGM_LOCK_ASSERT_OWNER(a_pVM)
778	#else
779	# define PGM_PAGE_ASSERT_LOCK(a_pVM) do { } while (0)
780	#endif
781
782	/**
783	* Gets the page state.
784	* @returns page state (PGM_PAGE_STATE_*).
785	* @param a_pPage Pointer to the physical guest page tracking structure.
786	*
787	* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
788	* builds.
789	*/
790	#define PGM_PAGE_GET_STATE_NA(a_pPage) ( (a_pPage)->s.uStateY )
791	#if defined(__GNUC__) && defined(VBOX_STRICT)
792	# define PGM_PAGE_GET_STATE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_STATE_NA(a_pPage); })
793	#else
794	# define PGM_PAGE_GET_STATE PGM_PAGE_GET_STATE_NA
795	#endif
796
797	/**
798	* Sets the page state.
799	* @param a_pVM The VM handle, only used for lock ownership assertions.
800	* @param a_pPage Pointer to the physical guest page tracking structure.
801	* @param a_uState The new page state.
802	*/
803	#define PGM_PAGE_SET_STATE(a_pVM, a_pPage, a_uState) \
804	do { (a_pPage)->s.uStateY = (a_uState); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
805
806
807	/**
808	* Gets the host physical address of the guest page.
809	* @returns host physical address (RTHCPHYS).
810	* @param a_pPage Pointer to the physical guest page tracking structure.
811	*
812	* @remarks In strict builds on gcc platforms, this macro will make some ugly
813	* assumption about a valid pVM variable/parameter being in the
814	* current context. It will use this pVM variable to assert that the
815	* PGM lock is held. Use the PGM_PAGE_GET_HCPHYS_NA in contexts where
816	* pVM is not around.
817	*/
818	#if 0
819	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->s.HCPhysFN << 12 )
820	# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
821	#else
822	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->au64[0] & UINT64_C(0x0000fffffffff000) )
823	# if defined(__GNUC__) && defined(VBOX_STRICT)
824	# define PGM_PAGE_GET_HCPHYS(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_HCPHYS_NA(a_pPage); })
825	# else
826	# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
827	# endif
828	#endif
829
830	/**
831	* Sets the host physical address of the guest page.
832	*
833	* @param a_pVM The VM handle, only used for lock ownership assertions.
834	* @param a_pPage Pointer to the physical guest page tracking structure.
835	* @param a_HCPhys The new host physical address.
836	*/
837	#define PGM_PAGE_SET_HCPHYS(a_pVM, a_pPage, a_HCPhys) \
838	do { \
839	RTHCPHYS const SetHCPhysTmp = (a_HCPhys); \
840	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
841	(a_pPage)->s.HCPhysFN = SetHCPhysTmp >> 12; \
842	PGM_PAGE_ASSERT_LOCK(a_pVM); \
843	} while (0)
844
845	/**
846	* Get the Page ID.
847	* @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
848	* @param a_pPage Pointer to the physical guest page tracking structure.
849	*/
850	#define PGM_PAGE_GET_PAGEID(a_pPage) ( (uint32_t)(a_pPage)->s.idPage )
851
852	/**
853	* Sets the Page ID.
854	* @param a_pVM The VM handle, only used for lock ownership assertions.
855	* @param a_pPage Pointer to the physical guest page tracking structure.
856	* @param a_idPage The new page ID.
857	*/
858	#define PGM_PAGE_SET_PAGEID(a_pVM, a_pPage, a_idPage) \
859	do { \
860	(a_pPage)->s.idPage = (a_idPage); \
861	PGM_PAGE_ASSERT_LOCK(a_pVM); \
862	} while (0)
863
864	/**
865	* Get the Chunk ID.
866	* @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
867	* @param a_pPage Pointer to the physical guest page tracking structure.
868	*/
869	#define PGM_PAGE_GET_CHUNKID(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) >> GMM_CHUNKID_SHIFT )
870
871	/**
872	* Get the index of the page within the allocation chunk.
873	* @returns The page index.
874	* @param a_pPage Pointer to the physical guest page tracking structure.
875	*/
876	#define PGM_PAGE_GET_PAGE_IN_CHUNK(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) & GMM_PAGEID_IDX_MASK )
877
878	/**
879	* Gets the page type.
880	* @returns The page type.
881	* @param a_pPage Pointer to the physical guest page tracking structure.
882	*
883	* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
884	* builds.
885	*/
886	#define PGM_PAGE_GET_TYPE_NA(a_pPage) ( (a_pPage)->s.uTypeY )
887	#if defined(__GNUC__) && defined(VBOX_STRICT)
888	# define PGM_PAGE_GET_TYPE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TYPE_NA(a_pPage); })
889	#else
890	# define PGM_PAGE_GET_TYPE PGM_PAGE_GET_TYPE_NA
891	#endif
892
893	/**
894	* Sets the page type.
895	*
896	* @param a_pVM The VM handle, only used for lock ownership assertions.
897	* @param a_pPage Pointer to the physical guest page tracking structure.
898	* @param a_enmType The new page type (PGMPAGETYPE).
899	*/
900	#define PGM_PAGE_SET_TYPE(a_pVM, a_pPage, a_enmType) \
901	do { (a_pPage)->s.uTypeY = (a_enmType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
902
903	/**
904	* Gets the page table index
905	* @returns The page table index.
906	* @param a_pPage Pointer to the physical guest page tracking structure.
907	*/
908	#define PGM_PAGE_GET_PTE_INDEX(a_pPage) ( (a_pPage)->s.u10PteIdx )
909
910	/**
911	* Sets the page table index.
912	* @param a_pVM The VM handle, only used for lock ownership assertions.
913	* @param a_pPage Pointer to the physical guest page tracking structure.
914	* @param a_iPte New page table index.
915	*/
916	#define PGM_PAGE_SET_PTE_INDEX(a_pVM, a_pPage, a_iPte) \
917	do { (a_pPage)->s.u10PteIdx = (a_iPte); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
918
919	/**
920	* Checks if the page is marked for MMIO, no MMIO2 aliasing.
921	* @returns true/false.
922	* @param a_pPage Pointer to the physical guest page tracking structure.
923	*/
924	#define PGM_PAGE_IS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO )
925
926	/**
927	* Checks if the page is marked for MMIO, including both aliases.
928	* @returns true/false.
929	* @param a_pPage Pointer to the physical guest page tracking structure.
930	*/
931	#define PGM_PAGE_IS_MMIO_OR_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
932	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO2_ALIAS_MMIO \
933	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO \
934	)
935
936	/**
937	* Checks if the page is marked for MMIO, including special aliases.
938	* @returns true/false.
939	* @param a_pPage Pointer to the physical guest page tracking structure.
940	*/
941	#define PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
942	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
943
944	/**
945	* Checks if the page is a special aliased MMIO page.
946	* @returns true/false.
947	* @param a_pPage Pointer to the physical guest page tracking structure.
948	*/
949	#define PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
950
951	/**
952	* Checks if the page is backed by the ZERO page.
953	* @returns true/false.
954	* @param a_pPage Pointer to the physical guest page tracking structure.
955	*/
956	#define PGM_PAGE_IS_ZERO(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ZERO )
957
958	/**
959	* Checks if the page is backed by a SHARED page.
960	* @returns true/false.
961	* @param a_pPage Pointer to the physical guest page tracking structure.
962	*/
963	#define PGM_PAGE_IS_SHARED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_SHARED )
964
965	/**
966	* Checks if the page is ballooned.
967	* @returns true/false.
968	* @param a_pPage Pointer to the physical guest page tracking structure.
969	*/
970	#define PGM_PAGE_IS_BALLOONED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_BALLOONED )
971
972	/**
973	* Checks if the page is allocated.
974	* @returns true/false.
975	* @param a_pPage Pointer to the physical guest page tracking structure.
976	*/
977	#define PGM_PAGE_IS_ALLOCATED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ALLOCATED )
978
979	/**
980	* Marks the page as written to (for GMM change monitoring).
981	* @param a_pVM The VM handle, only used for lock ownership assertions.
982	* @param a_pPage Pointer to the physical guest page tracking structure.
983	*/
984	#define PGM_PAGE_SET_WRITTEN_TO(a_pVM, a_pPage) \
985	do { (a_pPage)->s.fWrittenToY = 1; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
986
987	/**
988	* Clears the written-to indicator.
989	* @param a_pVM The VM handle, only used for lock ownership assertions.
990	* @param a_pPage Pointer to the physical guest page tracking structure.
991	*/
992	#define PGM_PAGE_CLEAR_WRITTEN_TO(a_pVM, a_pPage) \
993	do { (a_pPage)->s.fWrittenToY = 0; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
994
995	/**
996	* Checks if the page was marked as written-to.
997	* @returns true/false.
998	* @param a_pPage Pointer to the physical guest page tracking structure.
999	*/
1000	#define PGM_PAGE_IS_WRITTEN_TO(a_pPage) ( (a_pPage)->s.fWrittenToY )
1001
1002
1003	/** @name PT usage values (PGMPAGE::u2PDEType).
1004	*
1005	* @{ */
1006	/** Either as a PT or PDE. */
1007	#define PGM_PAGE_PDE_TYPE_DONTCARE 0
1008	/** Must use a page table to map the range. */
1009	#define PGM_PAGE_PDE_TYPE_PT 1
1010	/** Can use a page directory entry to map the continuous range. */
1011	#define PGM_PAGE_PDE_TYPE_PDE 2
1012	/** Can use a page directory entry to map the continuous range - temporarily disabled (by page monitoring). */
1013	#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
1014	/** @} */
1015
1016	/**
1017	* Set the PDE type of the page
1018	* @param a_pVM The VM handle, only used for lock ownership assertions.
1019	* @param a_pPage Pointer to the physical guest page tracking structure.
1020	* @param a_uType PGM_PAGE_PDE_TYPE_*.
1021	*/
1022	#define PGM_PAGE_SET_PDE_TYPE(a_pVM, a_pPage, a_uType) \
1023	do { (a_pPage)->s.u2PDETypeY = (a_uType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1024
1025	/**
1026	* Checks if the page was marked being part of a large page
1027	* @returns true/false.
1028	* @param a_pPage Pointer to the physical guest page tracking structure.
1029	*/
1030	#define PGM_PAGE_GET_PDE_TYPE(a_pPage) ( (a_pPage)->s.u2PDETypeY )
1031
1032	/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
1033	*
1034	* @remarks The values are assigned in order of priority, so we can calculate
1035	* the correct state for a page with different handlers installed.
1036	* @{ */
1037	/** No handler installed. */
1038	#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
1039	/** Monitoring is temporarily disabled. */
1040	#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
1041	/** Write access is monitored. */
1042	#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
1043	/** All access is monitored. */
1044	#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
1045	/** @} */
1046
1047	/**
1048	* Gets the physical access handler state of a page.
1049	* @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
1050	* @param a_pPage Pointer to the physical guest page tracking structure.
1051	*/
1052	#define PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) ( (a_pPage)->s.u2HandlerPhysStateY )
1053
1054	/**
1055	* Sets the physical access handler state of a page.
1056	* @param a_pPage Pointer to the physical guest page tracking structure.
1057	* @param a_uState The new state value.
1058	* @param a_fNotInHm The PGMPHYSHANDLER_F_NOT_HM bit.
1059	*/
1060	#define PGM_PAGE_SET_HNDL_PHYS_STATE(a_pPage, a_uState, a_fNotInHm) \
1061	do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); (a_pPage)->s.fHandlerPhysNotInHm = (a_fNotInHm); } while (0)
1062
1063	/**
1064	* Sets the physical access handler state of a page.
1065	* @param a_pPage Pointer to the physical guest page tracking structure.
1066	* @param a_uState The new state value.
1067	*/
1068	#define PGM_PAGE_SET_HNDL_PHYS_STATE_ONLY(a_pPage, a_uState) \
1069	do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); } while (0)
1070
1071	/**
1072	* Checks if the page has any physical access handlers, including temporarily disabled ones.
1073	* @returns true/false
1074	* @param a_pPage Pointer to the physical guest page tracking structure.
1075	*/
1076	#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(a_pPage) \
1077	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1078
1079	/**
1080	* Checks if the page has any active physical access handlers.
1081	* @returns true/false
1082	* @param a_pPage Pointer to the physical guest page tracking structure.
1083	*/
1084	#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(a_pPage) \
1085	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1086
1087	/**
1088	* Checks if the page has any access handlers, including temporarily disabled ones.
1089	* @returns true/false
1090	* @param a_pPage Pointer to the physical guest page tracking structure.
1091	*/
1092	#define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1093	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1094
1095	/**
1096	* Checks if the page has any active access handlers.
1097	* @returns true/false
1098	* @param a_pPage Pointer to the physical guest page tracking structure.
1099	*/
1100	#define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1101	(PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1102
1103	/**
1104	* Checks if the page has any active access handlers catching all accesses.
1105	* @returns true/false
1106	* @param a_pPage Pointer to the physical guest page tracking structure.
1107	*/
1108	#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1109	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1110
1111	/** @def PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM
1112	* Checks if the physical handlers of the page should be ignored in shadow page
1113	* tables and such.
1114	* @returns true/false
1115	* @param a_pPage Pointer to the physical guest page tracking structure.
1116	*/
1117	#define PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(a_pPage) ((a_pPage)->s.fHandlerPhysNotInHm)
1118
1119	/** @def PGM_PAGE_GET_TRACKING
1120	* Gets the packed shadow page pool tracking data associated with a guest page.
1121	* @returns uint16_t containing the data.
1122	* @param a_pPage Pointer to the physical guest page tracking structure.
1123	*/
1124	#define PGM_PAGE_GET_TRACKING_NA(a_pPage) ( (a_pPage)->s.u16TrackingY )
1125	#if defined(__GNUC__) && defined(VBOX_STRICT)
1126	# define PGM_PAGE_GET_TRACKING(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TRACKING_NA(a_pPage); })
1127	#else
1128	# define PGM_PAGE_GET_TRACKING PGM_PAGE_GET_TRACKING_NA
1129	#endif
1130
1131	/** @def PGM_PAGE_SET_TRACKING
1132	* Sets the packed shadow page pool tracking data associated with a guest page.
1133	* @param a_pVM The VM handle, only used for lock ownership assertions.
1134	* @param a_pPage Pointer to the physical guest page tracking structure.
1135	* @param a_u16TrackingData The tracking data to store.
1136	*/
1137	#define PGM_PAGE_SET_TRACKING(a_pVM, a_pPage, a_u16TrackingData) \
1138	do { (a_pPage)->s.u16TrackingY = (a_u16TrackingData); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1139
1140	/** @def PGM_PAGE_GET_TD_CREFS
1141	* Gets the @a cRefs tracking data member.
1142	* @returns cRefs.
1143	* @param a_pPage Pointer to the physical guest page tracking structure.
1144	*/
1145	#define PGM_PAGE_GET_TD_CREFS(a_pPage) \
1146	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1147	#define PGM_PAGE_GET_TD_CREFS_NA(a_pPage) \
1148	((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1149
1150	/** @def PGM_PAGE_GET_TD_IDX
1151	* Gets the @a idx tracking data member.
1152	* @returns idx.
1153	* @param a_pPage Pointer to the physical guest page tracking structure.
1154	*/
1155	#define PGM_PAGE_GET_TD_IDX(a_pPage) \
1156	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1157	#define PGM_PAGE_GET_TD_IDX_NA(a_pPage) \
1158	((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1159
1160
1161	/** Max number of locks on a page. */
1162	#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1163
1164	/** Get the read lock count.
1165	* @returns count.
1166	* @param a_pPage Pointer to the physical guest page tracking structure.
1167	*/
1168	#define PGM_PAGE_GET_READ_LOCKS(a_pPage) ( (a_pPage)->s.cReadLocksY )
1169
1170	/** Get the write lock count.
1171	* @returns count.
1172	* @param a_pPage Pointer to the physical guest page tracking structure.
1173	*/
1174	#define PGM_PAGE_GET_WRITE_LOCKS(a_pPage) ( (a_pPage)->s.cWriteLocksY )
1175
1176	/** Decrement the read lock counter.
1177	* @param a_pPage Pointer to the physical guest page tracking structure.
1178	*/
1179	#define PGM_PAGE_DEC_READ_LOCKS(a_pPage) do { --(a_pPage)->s.cReadLocksY; } while (0)
1180
1181	/** Decrement the write lock counter.
1182	* @param a_pPage Pointer to the physical guest page tracking structure.
1183	*/
1184	#define PGM_PAGE_DEC_WRITE_LOCKS(a_pPage) do { --(a_pPage)->s.cWriteLocksY; } while (0)
1185
1186	/** Increment the read lock counter.
1187	* @param a_pPage Pointer to the physical guest page tracking structure.
1188	*/
1189	#define PGM_PAGE_INC_READ_LOCKS(a_pPage) do { ++(a_pPage)->s.cReadLocksY; } while (0)
1190
1191	/** Increment the write lock counter.
1192	* @param a_pPage Pointer to the physical guest page tracking structure.
1193	*/
1194	#define PGM_PAGE_INC_WRITE_LOCKS(a_pPage) do { ++(a_pPage)->s.cWriteLocksY; } while (0)
1195
1196
1197	/** Gets the NEM state.
1198	* @returns NEM state value (two bits).
1199	* @param a_pPage Pointer to the physical guest page tracking structure.
1200	*/
1201	#define PGM_PAGE_GET_NEM_STATE(a_pPage) ((a_pPage)->s.u2NemStateY)
1202
1203	/** Sets the NEM state.
1204	* @param a_pPage Pointer to the physical guest page tracking structure.
1205	* @param a_u2State The NEM state value (specific to NEM impl.).
1206	*/
1207	#define PGM_PAGE_SET_NEM_STATE(a_pPage, a_u2State) \
1208	do { Assert((a_u2State) < 4); (a_pPage)->s.u2NemStateY = (a_u2State); } while (0)
1209
1210
1211	#if 0
1212	/** Enables sanity checking of write monitoring using CRC-32. */
1213	# define PGMLIVESAVERAMPAGE_WITH_CRC32
1214	#endif
1215
1216	/**
1217	* Per page live save tracking data.
1218	*/
1219	typedef struct PGMLIVESAVERAMPAGE
1220	{
1221	/** Number of times it has been dirtied. */
1222	uint32_t cDirtied : 24;
1223	/** Whether it is currently dirty. */
1224	uint32_t fDirty : 1;
1225	/** Ignore the page.
1226	* This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1227	* deal with these after pausing the VM and DevPCI have said it bit about
1228	* remappings. */
1229	uint32_t fIgnore : 1;
1230	/** Was a ZERO page last time around. */
1231	uint32_t fZero : 1;
1232	/** Was a SHARED page last time around. */
1233	uint32_t fShared : 1;
1234	/** Whether the page is/was write monitored in a previous pass. */
1235	uint32_t fWriteMonitored : 1;
1236	/** Whether the page is/was write monitored earlier in this pass. */
1237	uint32_t fWriteMonitoredJustNow : 1;
1238	/** Bits reserved for future use. */
1239	uint32_t u2Reserved : 2;
1240	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1241	/** CRC-32 for the page. This is for internal consistency checks. */
1242	uint32_t u32Crc;
1243	#endif
1244	} PGMLIVESAVERAMPAGE;
1245	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1246	AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1247	#else
1248	AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1249	#endif
1250	/** Pointer to the per page live save tracking data. */
1251	typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1252
1253	/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1254	#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1255
1256
1257	/**
1258	* RAM range for GC Phys to HC Phys conversion.
1259	*
1260	* Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1261	* conversions too, but we'll let MM handle that for now.
1262	*
1263	* This structure is used by linked lists in both GC and HC.
1264	*/
1265	typedef struct PGMRAMRANGE
1266	{
1267	/** Start of the range. Page aligned. */
1268	RTGCPHYS GCPhys;
1269	/** Size of the range. (Page aligned of course). */
1270	RTGCPHYS cb;
1271	/** Pointer to the next RAM range - for R3. */
1272	R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1273	/** Pointer to the next RAM range - for R0. */
1274	R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1275	/** PGM_RAM_RANGE_FLAGS_* flags. */
1276	uint32_t fFlags;
1277	/** NEM specific info, UINT32_MAX if not used. */
1278	uint32_t uNemRange;
1279	/** Last address in the range (inclusive). Page aligned (-1). */
1280	RTGCPHYS GCPhysLast;
1281	/** Start of the HC mapping of the range. This is only used for MMIO2 and in NEM mode. */
1282	R3PTRTYPE(void *) pvR3;
1283	/** Live save per page tracking data. */
1284	R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1285	/** The range description. */
1286	R3PTRTYPE(const char *) pszDesc;
1287	/** Pointer to self - R0 pointer. */
1288	R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1289
1290	/** Pointer to the left search three node - ring-3 context. */
1291	R3PTRTYPE(struct PGMRAMRANGE *) pLeftR3;
1292	/** Pointer to the right search three node - ring-3 context. */
1293	R3PTRTYPE(struct PGMRAMRANGE *) pRightR3;
1294	/** Pointer to the left search three node - ring-0 context. */
1295	R0PTRTYPE(struct PGMRAMRANGE *) pLeftR0;
1296	/** Pointer to the right search three node - ring-0 context. */
1297	R0PTRTYPE(struct PGMRAMRANGE *) pRightR0;
1298
1299	/** Padding to make aPage aligned on sizeof(PGMPAGE). */
1300	#if HC_ARCH_BITS == 32
1301	uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 0];
1302	#endif
1303	/** Array of physical guest page tracking structures.
1304	* @note Number of entries is PGMRAMRANGE::cb / GUEST_PAGE_SIZE. */
1305	PGMPAGE aPages[1];
1306	} PGMRAMRANGE;
1307	/** Pointer to RAM range for GC Phys to HC Phys conversion. */
1308	typedef PGMRAMRANGE *PPGMRAMRANGE;
1309
1310	/** @name PGMRAMRANGE::fFlags
1311	* @{ */
1312	/** The RAM range is floating around as an independent guest mapping. */
1313	#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1314	/** Ad hoc RAM range for an ROM mapping. */
1315	#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1316	/** Ad hoc RAM range for an MMIO mapping. */
1317	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1318	/** Ad hoc RAM range for an MMIO2 or pre-registered MMIO mapping. */
1319	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX RT_BIT(23)
1320	/** @} */
1321
1322	/** Tests if a RAM range is an ad hoc one or not.
1323	* @returns true/false.
1324	* @param pRam The RAM range.
1325	*/
1326	#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1327	(!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX) ) )
1328
1329	/** The number of entries in the RAM range TLBs (there is one for each
1330	* context). Must be a power of two. */
1331	#define PGM_RAMRANGE_TLB_ENTRIES 8
1332
1333	/**
1334	* Calculates the RAM range TLB index for the physical address.
1335	*
1336	* @returns RAM range TLB index.
1337	* @param a_GCPhys The guest physical address.
1338	*/
1339	#define PGM_RAMRANGE_TLB_IDX(a_GCPhys) ( ((a_GCPhys) >> 20) & (PGM_RAMRANGE_TLB_ENTRIES - 1) )
1340
1341	/**
1342	* Calculates the ring-3 address for a_GCPhysPage if the RAM range has a
1343	* mapping address.
1344	*/
1345	#define PGM_RAMRANGE_CALC_PAGE_R3PTR(a_pRam, a_GCPhysPage) \
1346	( (a_pRam)->pvR3 ? (R3PTRTYPE(uint8_t *))(a_pRam)->pvR3 + (a_GCPhysPage) - (a_pRam)->GCPhys : NULL )
1347
1348
1349	/**
1350	* Per page tracking structure for ROM image.
1351	*
1352	* A ROM image may have a shadow page, in which case we may have two pages
1353	* backing it. This structure contains the PGMPAGE for both while
1354	* PGMRAMRANGE have a copy of the active one. It is important that these
1355	* aren't out of sync in any regard other than page pool tracking data.
1356	*/
1357	typedef struct PGMROMPAGE
1358	{
1359	/** The page structure for the virgin ROM page. */
1360	PGMPAGE Virgin;
1361	/** The page structure for the shadow RAM page. */
1362	PGMPAGE Shadow;
1363	/** The current protection setting. */
1364	PGMROMPROT enmProt;
1365	/** Live save status information. Makes use of unused alignment space. */
1366	struct
1367	{
1368	/** The previous protection value. */
1369	uint8_t u8Prot;
1370	/** Written to flag set by the handler. */
1371	bool fWrittenTo;
1372	/** Whether the shadow page is dirty or not. */
1373	bool fDirty;
1374	/** Whether it was dirtied in the recently. */
1375	bool fDirtiedRecently;
1376	} LiveSave;
1377	} PGMROMPAGE;
1378	AssertCompileSizeAlignment(PGMROMPAGE, 8);
1379	/** Pointer to a ROM page tracking structure. */
1380	typedef PGMROMPAGE *PPGMROMPAGE;
1381
1382
1383	/**
1384	* A registered ROM image.
1385	*
1386	* This is needed to keep track of ROM image since they generally intrude
1387	* into a PGMRAMRANGE. It also keeps track of additional info like the
1388	* two page sets (read-only virgin and read-write shadow), the current
1389	* state of each page.
1390	*
1391	* Because access handlers cannot easily be executed in a different
1392	* context, the ROM ranges needs to be accessible and in all contexts.
1393	*/
1394	typedef struct PGMROMRANGE
1395	{
1396	/** Pointer to the next range - R3. */
1397	R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1398	/** Pointer to the next range - R0. */
1399	R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1400	/** Pointer to the this range - R0. */
1401	R0PTRTYPE(struct PGMROMRANGE *) pSelfR0;
1402	/** Address of the range. */
1403	RTGCPHYS GCPhys;
1404	/** Address of the last byte in the range. */
1405	RTGCPHYS GCPhysLast;
1406	/** Size of the range. */
1407	RTGCPHYS cb;
1408	/** The flags (PGMPHYS_ROM_FLAGS_). /
1409	uint8_t fFlags;
1410	/** The saved state range ID. */
1411	uint8_t idSavedState;
1412	/** Alignment padding. */
1413	uint8_t au8Alignment[2];
1414	/** The size bits pvOriginal points to. */
1415	uint32_t cbOriginal;
1416	/** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1417	* This is used for strictness checks. */
1418	R3PTRTYPE(const void *) pvOriginal;
1419	/** The ROM description. */
1420	R3PTRTYPE(const char *) pszDesc;
1421	#ifdef VBOX_WITH_PGM_NEM_MODE
1422	/** In simplified memory mode this provides alternate backing for shadowed ROMs.
1423	* - PGMROMPROT_READ_ROM_WRITE_IGNORE: Shadow
1424	* - PGMROMPROT_READ_ROM_WRITE_RAM: Shadow
1425	* - PGMROMPROT_READ_RAM_WRITE_IGNORE: ROM
1426	* - PGMROMPROT_READ_RAM_WRITE_RAM: ROM */
1427	R3PTRTYPE(uint8_t *) pbR3Alternate;
1428	RTR3PTR pvAlignment2;
1429	#endif
1430	/** The per page tracking structures. */
1431	PGMROMPAGE aPages[1];
1432	} PGMROMRANGE;
1433	/** Pointer to a ROM range. */
1434	typedef PGMROMRANGE *PPGMROMRANGE;
1435
1436
1437	/**
1438	* Live save per page data for an MMIO2 page.
1439	*
1440	* Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1441	* of MMIO2 pages. The current approach is using some optimistic SHA-1 +
1442	* CRC-32 for detecting changes as well as special handling of zero pages. This
1443	* is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1444	* for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1445	* because of speed (2.5x and 6x slower).)
1446	*
1447	* @todo Implement dirty MMIO2 page reporting that can be enabled during live
1448	* save but normally is disabled. Since we can write monitor guest
1449	* accesses on our own, we only need this for host accesses. Shouldn't be
1450	* too difficult for DevVGA, VMMDev might be doable, the planned
1451	* networking fun will be fun since it involves ring-0.
1452	*/
1453	typedef struct PGMLIVESAVEMMIO2PAGE
1454	{
1455	/** Set if the page is considered dirty. */
1456	bool fDirty;
1457	/** The number of scans this page has remained unchanged for.
1458	* Only updated for dirty pages. */
1459	uint8_t cUnchangedScans;
1460	/** Whether this page was zero at the last scan. */
1461	bool fZero;
1462	/** Alignment padding. */
1463	bool fReserved;
1464	/** CRC-32 for the first half of the page.
1465	* This is used together with u32CrcH2 to quickly detect changes in the page
1466	* during the non-final passes. */
1467	uint32_t u32CrcH1;
1468	/** CRC-32 for the second half of the page. */
1469	uint32_t u32CrcH2;
1470	/** SHA-1 for the saved page.
1471	* This is used in the final pass to skip pages without changes. */
1472	uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1473	} PGMLIVESAVEMMIO2PAGE;
1474	/** Pointer to a live save status data for an MMIO2 page. */
1475	typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1476
1477	/**
1478	* A registered MMIO2 (= Device RAM) range.
1479	*
1480	* There are a few reason why we need to keep track of these registrations. One
1481	* of them is the deregistration & cleanup stuff, while another is that the
1482	* PGMRAMRANGE associated with such a region may have to be removed from the ram
1483	* range list.
1484	*
1485	* Overlapping with a RAM range has to be 100% or none at all. The pages in the
1486	* existing RAM range must not be ROM nor MMIO. A guru meditation will be
1487	* raised if a partial overlap or an overlap of ROM pages is encountered. On an
1488	* overlap we will free all the existing RAM pages and put in the ram range
1489	* pages instead.
1490	*/
1491	typedef struct PGMREGMMIO2RANGE
1492	{
1493	/** The owner of the range. (a device) */
1494	PPDMDEVINSR3 pDevInsR3;
1495	/** Pointer to the ring-3 mapping of the allocation. */
1496	RTR3PTR pvR3;
1497	#ifndef VBOX_WITH_LINEAR_HOST_PHYS_MEM
1498	/** Pointer to the ring-0 mapping of the allocation. */
1499	RTR0PTR pvR0;
1500	#endif
1501	/** Pointer to the next range - R3. */
1502	R3PTRTYPE(struct PGMREGMMIO2RANGE *) pNextR3;
1503	/** Flags (PGMREGMMIO2RANGE_F_XXX). */
1504	uint16_t fFlags;
1505	/** The sub device number (internal PCI config (CFGM) number). */
1506	uint8_t iSubDev;
1507	/** The PCI region number. */
1508	uint8_t iRegion;
1509	/** The saved state range ID. */
1510	uint8_t idSavedState;
1511	/** MMIO2 range identifier, for page IDs (PGMPAGE::s.idPage). */
1512	uint8_t idMmio2;
1513	/** Alignment padding for putting the ram range on a PGMPAGE alignment boundary. */
1514	#ifndef VBOX_WITH_LINEAR_HOST_PHYS_MEM
1515	uint8_t abAlignment[HC_ARCH_BITS == 32 ? 6 + 4 : 2];
1516	#else
1517	uint8_t abAlignment[HC_ARCH_BITS == 32 ? 6 + 8 : 2 + 8];
1518	#endif
1519	/** The real size.
1520	* This may be larger than indicated by RamRange.cb if the range has been
1521	* reduced during saved state loading. */
1522	RTGCPHYS cbReal;
1523	/** Pointer to the physical handler for MMIO.
1524	* If NEM is responsible for tracking dirty pages in simple memory mode, this
1525	* will be NULL. */
1526	R3PTRTYPE(PPGMPHYSHANDLER) pPhysHandlerR3;
1527	/** Live save per page tracking data for MMIO2. */
1528	R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1529	/** The associated RAM range. */
1530	PGMRAMRANGE RamRange;
1531	} PGMREGMMIO2RANGE;
1532	AssertCompileMemberAlignment(PGMREGMMIO2RANGE, RamRange, 16);
1533	/** Pointer to a MMIO2 or pre-registered MMIO range. */
1534	typedef PGMREGMMIO2RANGE *PPGMREGMMIO2RANGE;
1535
1536	/** @name PGMREGMMIO2RANGE_F_XXX - Registered MMIO2 range flags.
1537	* @{ */
1538	/** Set if this is the first chunk in the MMIO2 range. */
1539	#define PGMREGMMIO2RANGE_F_FIRST_CHUNK UINT16_C(0x0001)
1540	/** Set if this is the last chunk in the MMIO2 range. */
1541	#define PGMREGMMIO2RANGE_F_LAST_CHUNK UINT16_C(0x0002)
1542	/** Set if the whole range is mapped. */
1543	#define PGMREGMMIO2RANGE_F_MAPPED UINT16_C(0x0004)
1544	/** Set if it's overlapping, clear if not. */
1545	#define PGMREGMMIO2RANGE_F_OVERLAPPING UINT16_C(0x0008)
1546	/** This mirrors the PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES creation flag.*/
1547	#define PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES UINT16_C(0x0010)
1548	/** Set if the access handler is registered. */
1549	#define PGMREGMMIO2RANGE_F_IS_TRACKING UINT16_C(0x0020)
1550	/** Set if dirty page tracking is currently enabled. */
1551	#define PGMREGMMIO2RANGE_F_TRACKING_ENABLED UINT16_C(0x0040)
1552	/** Set if there are dirty pages in the range. */
1553	#define PGMREGMMIO2RANGE_F_IS_DIRTY UINT16_C(0x0080)
1554	/** @} */
1555
1556
1557	/** @name Internal MMIO2 constants.
1558	* @{ */
1559	/** The maximum number of MMIO2 ranges. */
1560	#define PGM_MMIO2_MAX_RANGES 32
1561	/** The maximum number of pages in a MMIO2 range. */
1562	#define PGM_MMIO2_MAX_PAGE_COUNT UINT32_C(0x01000000)
1563	/** Makes a MMIO2 page ID out of a MMIO2 range ID and page index number. */
1564	#define PGM_MMIO2_PAGEID_MAKE(a_idMmio2, a_iPage) ( ((uint32_t)(a_idMmio2) << 24) \| (uint32_t)(a_iPage) )
1565	/** Gets the MMIO2 range ID from an MMIO2 page ID. */
1566	#define PGM_MMIO2_PAGEID_GET_MMIO2_ID(a_idPage) ( (uint8_t)((a_idPage) >> 24) )
1567	/** Gets the MMIO2 page index from an MMIO2 page ID. */
1568	#define PGM_MMIO2_PAGEID_GET_IDX(a_idPage) ( ((a_idPage) & UINT32_C(0x00ffffff)) )
1569	/** @} */
1570
1571
1572
1573	/**
1574	* PGMPhysRead/Write cache entry
1575	*/
1576	typedef struct PGMPHYSCACHEENTRY
1577	{
1578	/** R3 pointer to physical page. */
1579	R3PTRTYPE(uint8_t *) pbR3;
1580	/** GC Physical address for cache entry */
1581	RTGCPHYS GCPhys;
1582	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1583	RTGCPHYS u32Padding0; /*< alignment padding. /
1584	#endif
1585	} PGMPHYSCACHEENTRY;
1586
1587	/**
1588	* PGMPhysRead/Write cache to reduce REM memory access overhead
1589	*/
1590	typedef struct PGMPHYSCACHE
1591	{
1592	/** Bitmap of valid cache entries */
1593	uint64_t aEntries;
1594	/** Cache entries */
1595	PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1596	} PGMPHYSCACHE;
1597
1598
1599	/** @name Ring-3 page mapping TLBs
1600	* @{ */
1601
1602	/** Pointer to an allocation chunk ring-3 mapping. */
1603	typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1604	/** Pointer to an allocation chunk ring-3 mapping pointer. */
1605	typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1606
1607	/**
1608	* Ring-3 tracking structure for an allocation chunk ring-3 mapping.
1609	*
1610	* The primary tree (Core) uses the chunk id as key.
1611	*/
1612	typedef struct PGMCHUNKR3MAP
1613	{
1614	/** The key is the chunk id. */
1615	AVLU32NODECORE Core;
1616	/** The time (ChunkR3Map.iNow) this chunk was last used. Used for unmap
1617	* selection. */
1618	uint32_t iLastUsed;
1619	/** The current reference count. */
1620	uint32_t volatile cRefs;
1621	/** The current permanent reference count. */
1622	uint32_t volatile cPermRefs;
1623	/** The mapping address. */
1624	void *pv;
1625	} PGMCHUNKR3MAP;
1626
1627	/**
1628	* Allocation chunk ring-3 mapping TLB entry.
1629	*/
1630	typedef struct PGMCHUNKR3MAPTLBE
1631	{
1632	/** The chunk id. */
1633	uint32_t volatile idChunk;
1634	#if HC_ARCH_BITS == 64
1635	uint32_t u32Padding; /*< alignment padding. /
1636	#endif
1637	/** The chunk map. */
1638	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1639	} PGMCHUNKR3MAPTLBE;
1640	/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1641	typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1642
1643	/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1644	* @remark Must be a power of two value. */
1645	#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1646
1647	/**
1648	* Allocation chunk ring-3 mapping TLB.
1649	*
1650	* @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1651	* At first glance this might look kinda odd since AVL trees are
1652	* supposed to give the most optimal lookup times of all trees
1653	* due to their balancing. However, take a tree with 1023 nodes
1654	* in it, that's 10 levels, meaning that most searches has to go
1655	* down 9 levels before they find what they want. This isn't fast
1656	* compared to a TLB hit. There is the factor of cache misses,
1657	* and of course the problem with trees and branch prediction.
1658	* This is why we use TLBs in front of most of the trees.
1659	*
1660	* @todo Generalize this TLB + AVL stuff, shouldn't be all that
1661	* difficult when we switch to the new inlined AVL trees (from kStuff).
1662	*/
1663	typedef struct PGMCHUNKR3MAPTLB
1664	{
1665	/** The TLB entries. */
1666	PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1667	} PGMCHUNKR3MAPTLB;
1668
1669	/**
1670	* Calculates the index of a guest page in the Ring-3 Chunk TLB.
1671	* @returns Chunk TLB index.
1672	* @param idChunk The Chunk ID.
1673	*/
1674	#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1675
1676
1677	/**
1678	* Ring-3 guest page mapping TLB entry.
1679	* @remarks used in ring-0 as well at the moment.
1680	*/
1681	typedef struct PGMPAGER3MAPTLBE
1682	{
1683	/** Address of the page. */
1684	RTGCPHYS volatile GCPhys;
1685	/** The guest page. */
1686	R3PTRTYPE(PPGMPAGE) volatile pPage;
1687	/** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1688	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1689	/** The address */
1690	R3PTRTYPE(void *) volatile pv;
1691	#if HC_ARCH_BITS == 32
1692	uint32_t u32Padding; /*< alignment padding. /
1693	#endif
1694	} PGMPAGER3MAPTLBE;
1695	/** Pointer to an entry in the HC physical TLB. */
1696	typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1697
1698
1699	/** The number of entries in the ring-3 guest page mapping TLB.
1700	* @remarks The value must be a power of two. */
1701	#define PGM_PAGER3MAPTLB_ENTRIES 256
1702
1703	/**
1704	* Ring-3 guest page mapping TLB.
1705	* @remarks used in ring-0 as well at the moment.
1706	*/
1707	typedef struct PGMPAGER3MAPTLB
1708	{
1709	/** The TLB entries. */
1710	PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1711	} PGMPAGER3MAPTLB;
1712	/** Pointer to the ring-3 guest page mapping TLB. */
1713	typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1714
1715	/**
1716	* Calculates the index of the TLB entry for the specified guest page.
1717	* @returns Physical TLB index.
1718	* @param GCPhys The guest physical address.
1719	*/
1720	#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> GUEST_PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1721
1722	/** @} */
1723
1724
1725	/** @name Ring-0 page mapping TLB
1726	* @{ */
1727	/**
1728	* Ring-0 guest page mapping TLB entry.
1729	*/
1730	typedef struct PGMPAGER0MAPTLBE
1731	{
1732	/** Address of the page. */
1733	RTGCPHYS volatile GCPhys;
1734	/** The guest page. */
1735	R0PTRTYPE(PPGMPAGE) volatile pPage;
1736	/** The address */
1737	R0PTRTYPE(void *) volatile pv;
1738	} PGMPAGER0MAPTLBE;
1739	/** Pointer to an entry in the HC physical TLB. */
1740	typedef PGMPAGER0MAPTLBE *PPGMPAGER0MAPTLBE;
1741
1742
1743	/** The number of entries in the ring-3 guest page mapping TLB.
1744	* @remarks The value must be a power of two. */
1745	#define PGM_PAGER0MAPTLB_ENTRIES 256
1746
1747	/**
1748	* Ring-3 guest page mapping TLB.
1749	* @remarks used in ring-0 as well at the moment.
1750	*/
1751	typedef struct PGMPAGER0MAPTLB
1752	{
1753	/** The TLB entries. */
1754	PGMPAGER0MAPTLBE aEntries[PGM_PAGER0MAPTLB_ENTRIES];
1755	} PGMPAGER0MAPTLB;
1756	/** Pointer to the ring-3 guest page mapping TLB. */
1757	typedef PGMPAGER0MAPTLB *PPGMPAGER0MAPTLB;
1758
1759	/**
1760	* Calculates the index of the TLB entry for the specified guest page.
1761	* @returns Physical TLB index.
1762	* @param GCPhys The guest physical address.
1763	*/
1764	#define PGM_PAGER0MAPTLB_IDX(GCPhys) ( ((GCPhys) >> GUEST_PAGE_SHIFT) & (PGM_PAGER0MAPTLB_ENTRIES - 1) )
1765	/** @} */
1766
1767
1768	/** @name Context neutral page mapper TLB.
1769	*
1770	* Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1771	* code is writting in a kind of context neutral way. Time will show whether
1772	* this actually makes sense or not...
1773	*
1774	* @todo this needs to be reconsidered and dropped/redone since the ring-0
1775	* context ends up using a global mapping cache on some platforms
1776	* (darwin).
1777	*
1778	* @{ */
1779	/** @typedef PPGMPAGEMAPTLB
1780	* The page mapper TLB pointer type for the current context. */
1781	/** @typedef PPGMPAGEMAPTLB
1782	* The page mapper TLB entry pointer type for the current context. */
1783	/** @typedef PPGMPAGEMAPTLB
1784	* The page mapper TLB entry pointer pointer type for the current context. */
1785	/** @def PGM_PAGEMAPTLB_ENTRIES
1786	* The number of TLB entries in the page mapper TLB for the current context. */
1787	/** @def PGM_PAGEMAPTLB_IDX
1788	* Calculate the TLB index for a guest physical address.
1789	* @returns The TLB index.
1790	* @param GCPhys The guest physical address. */
1791	/** @typedef PPGMPAGEMAP
1792	* Pointer to a page mapper unit for current context. */
1793	/** @typedef PPPGMPAGEMAP
1794	* Pointer to a page mapper unit pointer for current context. */
1795	#if defined(IN_RING0)
1796	typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1797	typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1798	typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1799	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1800	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1801	typedef struct PGMCHUNKR0MAP *PPGMPAGEMAP;
1802	typedef struct PGMCHUNKR0MAP **PPPGMPAGEMAP;
1803	#else
1804	typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1805	typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1806	typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1807	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1808	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1809	typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1810	typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1811	#endif
1812	/** @} */
1813
1814
1815	/** @name PGM Pool Indexes.
1816	* Aka. the unique shadow page identifier.
1817	* @{ */
1818	/** NIL page pool IDX. */
1819	#define NIL_PGMPOOL_IDX 0
1820	/** The first normal index. There used to be 5 fictive pages up front, now
1821	* there is only the NIL page. */
1822	#define PGMPOOL_IDX_FIRST 1
1823	/** The last valid index. (inclusive, 14 bits) */
1824	#define PGMPOOL_IDX_LAST 0x3fff
1825	/** @} */
1826
1827	/** The NIL index for the parent chain. */
1828	#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1829	#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1830
1831	/**
1832	* Node in the chain linking a shadowed page to it's parent (user).
1833	*/
1834	#pragma pack(1)
1835	typedef struct PGMPOOLUSER
1836	{
1837	/** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1838	uint16_t iNext;
1839	/** The user page index. */
1840	uint16_t iUser;
1841	/** Index into the user table. */
1842	uint32_t iUserTable;
1843	} PGMPOOLUSER, *PPGMPOOLUSER;
1844	typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1845	#pragma pack()
1846
1847
1848	/** The NIL index for the phys ext chain. */
1849	#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1850	/** The NIL pte index for a phys ext chain slot. */
1851	#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
1852
1853	/**
1854	* Node in the chain of physical cross reference extents.
1855	* @todo Calling this an 'extent' is not quite right, find a better name.
1856	* @todo find out the optimal size of the aidx array
1857	*/
1858	#pragma pack(1)
1859	typedef struct PGMPOOLPHYSEXT
1860	{
1861	/** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1862	uint16_t iNext;
1863	/** Alignment. */
1864	uint16_t u16Align;
1865	/** The user page index. */
1866	uint16_t aidx[3];
1867	/** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
1868	uint16_t apte[3];
1869	} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1870	typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1871	#pragma pack()
1872
1873
1874	/**
1875	* The kind of page that's being shadowed.
1876	*/
1877	typedef enum PGMPOOLKIND
1878	{
1879	/** The virtual invalid 0 entry. */
1880	PGMPOOLKIND_INVALID = 0,
1881	/** The entry is free (=unused). */
1882	PGMPOOLKIND_FREE,
1883
1884	/** Shw: 32-bit page table; Gst: no paging. */
1885	PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1886	/** Shw: 32-bit page table; Gst: 32-bit page table. */
1887	PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1888	/** Shw: 32-bit page table; Gst: 4MB page. */
1889	PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1890	/** Shw: PAE page table; Gst: no paging. */
1891	PGMPOOLKIND_PAE_PT_FOR_PHYS,
1892	/** Shw: PAE page table; Gst: 32-bit page table. */
1893	PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1894	/** Shw: PAE page table; Gst: Half of a 4MB page. */
1895	PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1896	/** Shw: PAE page table; Gst: PAE page table. */
1897	PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1898	/** Shw: PAE page table; Gst: 2MB page. */
1899	PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1900
1901	/** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1902	PGMPOOLKIND_32BIT_PD,
1903	/** Shw: 32-bit page directory. Gst: no paging. */
1904	PGMPOOLKIND_32BIT_PD_PHYS,
1905	/** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1906	PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1907	/** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1908	PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1909	/** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1910	PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1911	/** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1912	PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1913	/** Shw: PAE page directory; Gst: PAE page directory. */
1914	PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1915	/** Shw: PAE page directory; Gst: no paging. Note: +NP. */
1916	PGMPOOLKIND_PAE_PD_PHYS,
1917
1918	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1919	PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1920	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1921	PGMPOOLKIND_PAE_PDPT,
1922	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1923	PGMPOOLKIND_PAE_PDPT_PHYS,
1924
1925	/** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1926	PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1927	/** Shw: 64-bit page directory pointer table; Gst: no paging. */
1928	PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1929	/** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1930	PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1931	/** Shw: 64-bit page directory table; Gst: no paging. */
1932	PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 24 */
1933
1934	/** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1935	PGMPOOLKIND_64BIT_PML4,
1936
1937	/** Shw: EPT page directory pointer table; Gst: no paging. */
1938	PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1939	/** Shw: EPT page directory table; Gst: no paging. */
1940	PGMPOOLKIND_EPT_PD_FOR_PHYS,
1941	/** Shw: EPT page table; Gst: no paging. */
1942	PGMPOOLKIND_EPT_PT_FOR_PHYS,
1943
1944	/** Shw: Root Nested paging table. */
1945	PGMPOOLKIND_ROOT_NESTED,
1946
1947	/** Shw: EPT page table; Gst: EPT page table. */
1948	PGMPOOLKIND_EPT_PT_FOR_EPT_PT,
1949	/** Shw: EPT page table; Gst: 2MB page. */
1950	PGMPOOLKIND_EPT_PT_FOR_EPT_2MB,
1951	/** Shw: EPT page directory table; Gst: EPT page directory. */
1952	PGMPOOLKIND_EPT_PD_FOR_EPT_PD,
1953	/** Shw: EPT page directory pointer table; Gst: EPT page directory pointer table. */
1954	PGMPOOLKIND_EPT_PDPT_FOR_EPT_PDPT,
1955	/** Shw: EPT PML4; Gst: EPT PML4. */
1956	PGMPOOLKIND_EPT_PML4_FOR_EPT_PML4,
1957
1958	/** The last valid entry. */
1959	PGMPOOLKIND_LAST = PGMPOOLKIND_EPT_PML4_FOR_EPT_PML4
1960	} PGMPOOLKIND;
1961
1962	/**
1963	* The access attributes of the page; only applies to big pages.
1964	*/
1965	typedef enum
1966	{
1967	PGMPOOLACCESS_DONTCARE = 0,
1968	PGMPOOLACCESS_USER_RW,
1969	PGMPOOLACCESS_USER_R,
1970	PGMPOOLACCESS_USER_RW_NX,
1971	PGMPOOLACCESS_USER_R_NX,
1972	PGMPOOLACCESS_SUPERVISOR_RW,
1973	PGMPOOLACCESS_SUPERVISOR_R,
1974	PGMPOOLACCESS_SUPERVISOR_RW_NX,
1975	PGMPOOLACCESS_SUPERVISOR_R_NX
1976	} PGMPOOLACCESS;
1977
1978	/**
1979	* The tracking data for a page in the pool.
1980	*/
1981	typedef struct PGMPOOLPAGE
1982	{
1983	/** AVL node code with the (HC) physical address of this page. */
1984	AVLOHCPHYSNODECORE Core;
1985	/** Pointer to the R3 mapping of the page. */
1986	R3PTRTYPE(void *) pvPageR3;
1987	/** Pointer to the R0 mapping of the page. */
1988	R0PTRTYPE(void *) pvPageR0;
1989	/** The guest physical address. */
1990	RTGCPHYS GCPhys;
1991	/** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1992	uint8_t enmKind;
1993	/** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
1994	uint8_t enmAccess;
1995	/** This supplements enmKind and enmAccess */
1996	bool fA20Enabled : 1;
1997
1998	/** Used to indicate that the page is zeroed. */
1999	bool fZeroed : 1;
2000	/** Used to indicate that a PT has non-global entries. */
2001	bool fSeenNonGlobal : 1;
2002	/** Used to indicate that we're monitoring writes to the guest page. */
2003	bool fMonitored : 1;
2004	/** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
2005	* (All pages are in the age list.) */
2006	bool fCached : 1;
2007	/** This is used by the R3 access handlers when invoked by an async thread.
2008	* It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
2009	bool volatile fReusedFlushPending : 1;
2010	/** Used to mark the page as dirty (write monitoring is temporarily
2011	* off). */
2012	bool fDirty : 1;
2013	bool fPadding1 : 1;
2014	bool fPadding2;
2015
2016	/** The index of this page. */
2017	uint16_t idx;
2018	/** The next entry in the list this page currently resides in.
2019	* It's either in the free list or in the GCPhys hash. */
2020	uint16_t iNext;
2021	/** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
2022	uint16_t iUserHead;
2023	/** The number of present entries. */
2024	uint16_t cPresent;
2025	/** The first entry in the table which is present. */
2026	uint16_t iFirstPresent;
2027	/** The number of modifications to the monitored page. */
2028	uint16_t cModifications;
2029	/** The next modified page. NIL_PGMPOOL_IDX if tail. */
2030	uint16_t iModifiedNext;
2031	/** The previous modified page. NIL_PGMPOOL_IDX if head. */
2032	uint16_t iModifiedPrev;
2033	/** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
2034	uint16_t iMonitoredNext;
2035	/** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
2036	uint16_t iMonitoredPrev;
2037	/** The next page in the age list. */
2038	uint16_t iAgeNext;
2039	/** The previous page in the age list. */
2040	uint16_t iAgePrev;
2041	/** Index into PGMPOOL::aDirtyPages if fDirty is set. */
2042	uint8_t idxDirtyEntry;
2043
2044	/** @name Access handler statistics to determine whether the guest is
2045	* (re)initializing a page table.
2046	* @{ */
2047	RTGCPTR GCPtrLastAccessHandlerRip;
2048	RTGCPTR GCPtrLastAccessHandlerFault;
2049	uint64_t cLastAccessHandler;
2050	/** @} */
2051	/** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages. */
2052	uint32_t volatile cLocked;
2053	#if GC_ARCH_BITS == 64
2054	uint32_t u32Alignment3;
2055	#endif
2056	# ifdef VBOX_STRICT
2057	RTGCPTR GCPtrDirtyFault;
2058	# endif
2059	} PGMPOOLPAGE;
2060	/** Pointer to a pool page. */
2061	typedef PGMPOOLPAGE *PPGMPOOLPAGE;
2062	/** Pointer to a const pool page. */
2063	typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2064	/** Pointer to a pool page pointer. */
2065	typedef PGMPOOLPAGE **PPPGMPOOLPAGE;
2066
2067
2068	/** The hash table size. */
2069	# define PGMPOOL_HASH_SIZE 0x8000
2070	/** The hash function. */
2071	# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> GUEST_PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2072
2073
2074	/**
2075	* The shadow page pool instance data.
2076	*
2077	* It's all one big allocation made at init time, except for the
2078	* pages that is. The user nodes follows immediately after the
2079	* page structures.
2080	*/
2081	typedef struct PGMPOOL
2082	{
2083	/** The VM handle - R3 Ptr. */
2084	PVMR3 pVMR3;
2085	/** The VM handle - R0 Ptr. */
2086	R0PTRTYPE(PVMCC) pVMR0;
2087	/** The ring-3 pointer to this structure. */
2088	R3PTRTYPE(struct PGMPOOL *) pPoolR3;
2089	/** The ring-0 pointer to this structure. */
2090	R0PTRTYPE(struct PGMPOOL *) pPoolR0;
2091	/** The max pool size. This includes the special IDs. */
2092	uint16_t cMaxPages;
2093	/** The current pool size. */
2094	uint16_t cCurPages;
2095	/** The head of the free page list. */
2096	uint16_t iFreeHead;
2097	/* Padding. */
2098	uint16_t u16Padding;
2099	/** Head of the chain of free user nodes. */
2100	uint16_t iUserFreeHead;
2101	/** The number of user nodes we've allocated. */
2102	uint16_t cMaxUsers;
2103	/** The number of present page table entries in the entire pool. */
2104	uint32_t cPresent;
2105	/** Pointer to the array of user nodes - R3 pointer. */
2106	R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2107	/** Pointer to the array of user nodes - R0 pointer. */
2108	R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2109	/** Head of the chain of free phys ext nodes. */
2110	uint16_t iPhysExtFreeHead;
2111	/** The number of user nodes we've allocated. */
2112	uint16_t cMaxPhysExts;
2113	uint32_t u32Padding0b;
2114	/** Pointer to the array of physical xref extent nodes - R3 pointer. */
2115	R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2116	/** Pointer to the array of physical xref extent nodes - R0 pointer. */
2117	R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2118	/** Hash table for GCPhys addresses. */
2119	uint16_t aiHash[PGMPOOL_HASH_SIZE];
2120	/** The head of the age list. */
2121	uint16_t iAgeHead;
2122	/** The tail of the age list. */
2123	uint16_t iAgeTail;
2124	/** Set if the cache is enabled. */
2125	bool fCacheEnabled;
2126	/** Alignment padding. */
2127	bool afPadding1[3];
2128	/** Head of the list of modified pages. */
2129	uint16_t iModifiedHead;
2130	/** The current number of modified pages. */
2131	uint16_t cModifiedPages;
2132	/** Alignment padding. */
2133	uint32_t u32Padding2;
2134	/** Physical access handler type registration handle. */
2135	PGMPHYSHANDLERTYPE hAccessHandlerType;
2136	/** Next available slot (in aDirtyPages). */
2137	uint32_t idxFreeDirtyPage;
2138	/** Number of active dirty pages. */
2139	uint32_t cDirtyPages;
2140	/** Array of current dirty pgm pool page indices. */
2141	uint16_t aidxDirtyPages[16];
2142	/** Array running in parallel to aidxDirtyPages with the page data. */
2143	struct
2144	{
2145	uint64_t aPage[512];
2146	} aDirtyPages[16];
2147
2148	/** The number of pages currently in use. */
2149	uint16_t cUsedPages;
2150	#ifdef VBOX_WITH_STATISTICS
2151	/** The high water mark for cUsedPages. */
2152	uint16_t cUsedPagesHigh;
2153	uint32_t Alignment1; /*< Align the next member on a 64-bit boundary. /
2154	/** Profiling pgmPoolAlloc(). */
2155	STAMPROFILEADV StatAlloc;
2156	/** Profiling pgmR3PoolClearDoIt(). */
2157	STAMPROFILE StatClearAll;
2158	/** Profiling pgmR3PoolReset(). */
2159	STAMPROFILE StatR3Reset;
2160	/** Profiling pgmPoolFlushPage(). */
2161	STAMPROFILE StatFlushPage;
2162	/** Profiling pgmPoolFree(). */
2163	STAMPROFILE StatFree;
2164	/** Counting explicit flushes by PGMPoolFlushPage(). */
2165	STAMCOUNTER StatForceFlushPage;
2166	/** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2167	STAMCOUNTER StatForceFlushDirtyPage;
2168	/** Counting flushes for reused pages. */
2169	STAMCOUNTER StatForceFlushReused;
2170	/** Profiling time spent zeroing pages. */
2171	STAMPROFILE StatZeroPage;
2172	/** Profiling of pgmPoolTrackDeref. */
2173	STAMPROFILE StatTrackDeref;
2174	/** Profiling pgmTrackFlushGCPhysPT. */
2175	STAMPROFILE StatTrackFlushGCPhysPT;
2176	/** Profiling pgmTrackFlushGCPhysPTs. */
2177	STAMPROFILE StatTrackFlushGCPhysPTs;
2178	/** Profiling pgmTrackFlushGCPhysPTsSlow. */
2179	STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2180	/** Number of times we've been out of user records. */
2181	STAMCOUNTER StatTrackFreeUpOneUser;
2182	/** Nr of flushed entries. */
2183	STAMCOUNTER StatTrackFlushEntry;
2184	/** Nr of updated entries. */
2185	STAMCOUNTER StatTrackFlushEntryKeep;
2186	/** Profiling deref activity related tracking GC physical pages. */
2187	STAMPROFILE StatTrackDerefGCPhys;
2188	/** Number of linear searches for a HCPhys in the ram ranges. */
2189	STAMCOUNTER StatTrackLinearRamSearches;
2190	/** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2191	STAMCOUNTER StamTrackPhysExtAllocFailures;
2192
2193	/** Profiling the RC/R0 \#PF access handler. */
2194	STAMPROFILE StatMonitorPfRZ;
2195	/** Profiling the RC/R0 access we've handled (except REP STOSD). */
2196	STAMPROFILE StatMonitorPfRZHandled;
2197	/** Times we've failed interpreting the instruction. */
2198	STAMCOUNTER StatMonitorPfRZEmulateInstr;
2199	/** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2200	STAMPROFILE StatMonitorPfRZFlushPage;
2201	/** Times we've detected a page table reinit. */
2202	STAMCOUNTER StatMonitorPfRZFlushReinit;
2203	/** Counting flushes for pages that are modified too often. */
2204	STAMCOUNTER StatMonitorPfRZFlushModOverflow;
2205	/** Times we've detected fork(). */
2206	STAMCOUNTER StatMonitorPfRZFork;
2207	/** Times we've failed interpreting a patch code instruction. */
2208	STAMCOUNTER StatMonitorPfRZIntrFailPatch1;
2209	/** Times we've failed interpreting a patch code instruction during flushing. */
2210	STAMCOUNTER StatMonitorPfRZIntrFailPatch2;
2211	/** The number of times we've seen rep prefixes we can't handle. */
2212	STAMCOUNTER StatMonitorPfRZRepPrefix;
2213	/** Profiling the REP STOSD cases we've handled. */
2214	STAMPROFILE StatMonitorPfRZRepStosd;
2215
2216	/** Profiling the R0/RC regular access handler. */
2217	STAMPROFILE StatMonitorRZ;
2218	/** Profiling the pgmPoolFlushPage calls made from the regular access handler in R0/RC. */
2219	STAMPROFILE StatMonitorRZFlushPage;
2220	/** Per access size counts indexed by size minus 1, last for larger. */
2221	STAMCOUNTER aStatMonitorRZSizes[16+3];
2222	/** Missaligned access counts indexed by offset - 1. */
2223	STAMCOUNTER aStatMonitorRZMisaligned[7];
2224
2225	/** Nr of handled PT faults. */
2226	STAMCOUNTER StatMonitorRZFaultPT;
2227	/** Nr of handled PD faults. */
2228	STAMCOUNTER StatMonitorRZFaultPD;
2229	/** Nr of handled PDPT faults. */
2230	STAMCOUNTER StatMonitorRZFaultPDPT;
2231	/** Nr of handled PML4 faults. */
2232	STAMCOUNTER StatMonitorRZFaultPML4;
2233
2234	/** Profiling the R3 access handler. */
2235	STAMPROFILE StatMonitorR3;
2236	/** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2237	STAMPROFILE StatMonitorR3FlushPage;
2238	/** Per access size counts indexed by size minus 1, last for larger. */
2239	STAMCOUNTER aStatMonitorR3Sizes[16+3];
2240	/** Missaligned access counts indexed by offset - 1. */
2241	STAMCOUNTER aStatMonitorR3Misaligned[7];
2242	/** Nr of handled PT faults. */
2243	STAMCOUNTER StatMonitorR3FaultPT;
2244	/** Nr of handled PD faults. */
2245	STAMCOUNTER StatMonitorR3FaultPD;
2246	/** Nr of handled PDPT faults. */
2247	STAMCOUNTER StatMonitorR3FaultPDPT;
2248	/** Nr of handled PML4 faults. */
2249	STAMCOUNTER StatMonitorR3FaultPML4;
2250
2251	/** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2252	STAMCOUNTER StatResetDirtyPages;
2253	/** Times we've called pgmPoolAddDirtyPage. */
2254	STAMCOUNTER StatDirtyPage;
2255	/** Times we've had to flush duplicates for dirty page management. */
2256	STAMCOUNTER StatDirtyPageDupFlush;
2257	/** Times we've had to flush because of overflow. */
2258	STAMCOUNTER StatDirtyPageOverFlowFlush;
2259
2260	/** The high water mark for cModifiedPages. */
2261	uint16_t cModifiedPagesHigh;
2262	uint16_t Alignment2[3]; /*< Align the next member on a 64-bit boundary. /
2263
2264	/** The number of cache hits. */
2265	STAMCOUNTER StatCacheHits;
2266	/** The number of cache misses. */
2267	STAMCOUNTER StatCacheMisses;
2268	/** The number of times we've got a conflict of 'kind' in the cache. */
2269	STAMCOUNTER StatCacheKindMismatches;
2270	/** Number of times we've been out of pages. */
2271	STAMCOUNTER StatCacheFreeUpOne;
2272	/** The number of cacheable allocations. */
2273	STAMCOUNTER StatCacheCacheable;
2274	/** The number of uncacheable allocations. */
2275	STAMCOUNTER StatCacheUncacheable;
2276	#else
2277	uint32_t Alignment3; /*< Align the next member on a 64-bit boundary. /
2278	#endif
2279	/** Profiling PGMR0PoolGrow(). */
2280	STAMPROFILE StatGrow;
2281	/** The AVL tree for looking up a page by its HC physical address. */
2282	AVLOHCPHYSTREE HCPhysTree;
2283	uint32_t Alignment4; /*< Align the next member on a 64-bit boundary. /
2284	/** Array of pages. (cMaxPages in length)
2285	* The Id is the index into thist array.
2286	*/
2287	PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2288	} PGMPOOL, PPGMPOOL, *PPPGMPOOL;
2289	AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2290	AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2291	AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2292	#ifdef VBOX_WITH_STATISTICS
2293	AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2294	#endif
2295	AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2296
2297
2298	/** @def PGMPOOL_PAGE_2_PTR
2299	* Maps a pool page pool into the current context.
2300	*
2301	* @returns VBox status code.
2302	* @param a_pVM Pointer to the VM.
2303	* @param a_pPage The pool page.
2304	*
2305	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2306	* small page window employeed by that function. Be careful.
2307	* @remark There is no need to assert on the result.
2308	*/
2309	#if defined(VBOX_STRICT) \|\| 1 /* temporarily going strict here */
2310	# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageStrict(a_pPage, __FUNCTION__)
2311	DECLINLINE(void ) pgmPoolMapPageStrict(PPGMPOOLPAGE a_pPage, const char pszCaller)
2312	{
2313	RT_NOREF(pszCaller);
2314	AssertPtr(a_pPage);
2315	AssertMsg(RT_VALID_PTR(a_pPage->CTX_SUFF(pvPage)),
2316	("enmKind=%d idx=%#x HCPhys=%RHp GCPhys=%RGp pvPageR3=%p pvPageR0=%p caller=%s\n",
2317	a_pPage->enmKind, a_pPage->idx, a_pPage->Core.Key, a_pPage->GCPhys, a_pPage->pvPageR3, a_pPage->pvPageR0, pszCaller));
2318	return a_pPage->CTX_SUFF(pvPage);
2319	}
2320	#else
2321	# define PGMPOOL_PAGE_2_PTR(pVM, a_pPage) ((a_pPage)->CTX_SUFF(pvPage))
2322	#endif
2323
2324
2325	/** @def PGMPOOL_PAGE_2_PTR_V2
2326	* Maps a pool page pool into the current context, taking both VM and VMCPU.
2327	*
2328	* @returns VBox status code.
2329	* @param a_pVM Pointer to the VM.
2330	* @param a_pVCpu The current CPU.
2331	* @param a_pPage The pool page.
2332	*
2333	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2334	* small page window employeed by that function. Be careful.
2335	* @remark There is no need to assert on the result.
2336	*/
2337	#define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) PGMPOOL_PAGE_2_PTR((a_pVM), (a_pPage))
2338
2339
2340	/** @def PGMPOOL_PAGE_IS_NESTED
2341	* Checks whether the given pool page is a nested-guest pool page.
2342	*
2343	* @returns @c true if a nested-guest pool page, @c false otherwise.
2344	* @param a_pPage The pool page.
2345	* @todo We can optimize the conditionals later.
2346	*/
2347	#define PGMPOOL_PAGE_IS_NESTED(a_pPage) PGMPOOL_PAGE_IS_KIND_NESTED((a_pPage)->enmKind)
2348	#define PGMPOOL_PAGE_IS_KIND_NESTED(a_enmKind) ( (a_enmKind) == PGMPOOLKIND_EPT_PT_FOR_EPT_PT \
2349	\|\| (a_enmKind) == PGMPOOLKIND_EPT_PT_FOR_EPT_2MB \
2350	\|\| (a_enmKind) == PGMPOOLKIND_EPT_PD_FOR_EPT_PD \
2351	\|\| (a_enmKind) == PGMPOOLKIND_EPT_PDPT_FOR_EPT_PDPT \
2352	\|\| (a_enmKind) == PGMPOOLKIND_EPT_PML4_FOR_EPT_PML4)
2353
2354	/** @name Per guest page tracking data.
2355	* This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2356	* is to use more bits for it and split it up later on. But for now we'll play
2357	* safe and change as little as possible.
2358	*
2359	* The 16-bit word has two parts:
2360	*
2361	* The first 14-bit forms the @a idx field. It is either the index of a page in
2362	* the shadow page pool, or and index into the extent list.
2363	*
2364	* The 2 topmost bits makes up the @a cRefs field, which counts the number of
2365	* shadow page pool references to the page. If cRefs equals
2366	* PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2367	* (misnomer) table and not the shadow page pool.
2368	*
2369	* See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2370	* the 16-bit word.
2371	*
2372	* @{ */
2373	/** The shift count for getting to the cRefs part. */
2374	#define PGMPOOL_TD_CREFS_SHIFT 14
2375	/** The mask applied after shifting the tracking data down by
2376	* PGMPOOL_TD_CREFS_SHIFT. */
2377	#define PGMPOOL_TD_CREFS_MASK 0x3
2378	/** The cRefs value used to indicate that the idx is the head of a
2379	* physical cross reference list. */
2380	#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2381	/** The shift used to get idx. */
2382	#define PGMPOOL_TD_IDX_SHIFT 0
2383	/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2384	#define PGMPOOL_TD_IDX_MASK 0x3fff
2385	/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2386	* simply too many mappings of this page. */
2387	#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2388
2389	/** @def PGMPOOL_TD_MAKE
2390	* Makes a 16-bit tracking data word.
2391	*
2392	* @returns tracking data.
2393	* @param cRefs The @a cRefs field. Must be within bounds!
2394	* @param idx The @a idx field. Must also be within bounds! */
2395	#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) \| (idx) )
2396
2397	/** @def PGMPOOL_TD_GET_CREFS
2398	* Get the @a cRefs field from a tracking data word.
2399	*
2400	* @returns The @a cRefs field
2401	* @param u16 The tracking data word.
2402	* @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2403	* non-zero @a u16. */
2404	#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2405
2406	/** @def PGMPOOL_TD_GET_IDX
2407	* Get the @a idx field from a tracking data word.
2408	*
2409	* @returns The @a idx field
2410	* @param u16 The tracking data word. */
2411	#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2412	/** @} */
2413
2414
2415
2416	/** @name A20 gate macros
2417	* @{ */
2418	#define PGM_WITH_A20
2419	#ifdef PGM_WITH_A20
2420	# define PGM_A20_IS_ENABLED(a_pVCpu) ((a_pVCpu)->pgm.s.fA20Enabled)
2421	# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) ((a_GCPhys) & (a_pVCpu)->pgm.s.GCPhysA20Mask)
2422	# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) \
2423	do { a_GCPhysVar &= (a_pVCpu)->pgm.s.GCPhysA20Mask; } while (0)
2424	# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) Assert(PGM_A20_APPLY(pVCpu, a_GCPhys) == (a_GCPhys))
2425	#else
2426	# define PGM_A20_IS_ENABLED(a_pVCpu) (true)
2427	# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) (a_GCPhys)
2428	# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) do { } while (0)
2429	# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) do { } while (0)
2430	#endif
2431	/** @} */
2432
2433
2434	/**
2435	* Guest page table walk for the AMD64 mode.
2436	*/
2437	typedef struct PGMPTWALKGSTAMD64
2438	{
2439	PX86PML4 pPml4;
2440	PX86PML4E pPml4e;
2441	X86PML4E Pml4e;
2442
2443	PX86PDPT pPdpt;
2444	PX86PDPE pPdpe;
2445	X86PDPE Pdpe;
2446
2447	PX86PDPAE pPd;
2448	PX86PDEPAE pPde;
2449	X86PDEPAE Pde;
2450
2451	PX86PTPAE pPt;
2452	PX86PTEPAE pPte;
2453	X86PTEPAE Pte;
2454	} PGMPTWALKGSTAMD64;
2455	/** Pointer to a AMD64 guest page table walk. */
2456	typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2457	/** Pointer to a const AMD64 guest page table walk. */
2458	typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2459
2460	/**
2461	* Guest page table walk for the EPT mode.
2462	*/
2463	typedef struct PGMPTWALKGSTEPT
2464	{
2465	PEPTPML4 pPml4;
2466	PEPTPML4E pPml4e;
2467	EPTPML4E Pml4e;
2468
2469	PEPTPDPT pPdpt;
2470	PEPTPDPTE pPdpte;
2471	EPTPDPTE Pdpte;
2472
2473	PEPTPD pPd;
2474	PEPTPDE pPde;
2475	EPTPDE Pde;
2476
2477	PEPTPT pPt;
2478	PEPTPTE pPte;
2479	EPTPTE Pte;
2480	} PGMPTWALKGSTEPT;
2481	/** Pointer to an EPT guest page table walk. */
2482	typedef PGMPTWALKGSTEPT *PPGMPTWALKGSTEPT;
2483	/** Pointer to a const EPT guest page table walk. */
2484	typedef PGMPTWALKGSTEPT const *PCPGMPTWALKGSTEPT;
2485
2486	/**
2487	* Guest page table walk for the PAE mode.
2488	*/
2489	typedef struct PGMPTWALKGSTPAE
2490	{
2491	PX86PDPT pPdpt;
2492	PX86PDPE pPdpe;
2493	X86PDPE Pdpe;
2494
2495	PX86PDPAE pPd;
2496	PX86PDEPAE pPde;
2497	X86PDEPAE Pde;
2498
2499	PX86PTPAE pPt;
2500	PX86PTEPAE pPte;
2501	X86PTEPAE Pte;
2502	} PGMPTWALKGSTPAE;
2503	/** Pointer to a PAE guest page table walk. */
2504	typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2505	/** Pointer to a const AMD64 guest page table walk. */
2506	typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2507
2508	/**
2509	* Guest page table walk for the 32-bit mode.
2510	*/
2511	typedef struct PGMPTWALKGST32BIT
2512	{
2513	PX86PD pPd;
2514	PX86PDE pPde;
2515	X86PDE Pde;
2516
2517	PX86PT pPt;
2518	PX86PTE pPte;
2519	X86PTE Pte;
2520	} PGMPTWALKGST32BIT;
2521	/** Pointer to a 32-bit guest page table walk. */
2522	typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2523	/** Pointer to a const 32-bit guest page table walk. */
2524	typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2525
2526	/**
2527	* Which part of PGMPTWALKGST that is valid.
2528	*/
2529	typedef enum PGMPTWALKGSTTYPE
2530	{
2531	/** Customary invalid 0 value. */
2532	PGMPTWALKGSTTYPE_INVALID = 0,
2533	/** PGMPTWALKGST::u.Amd64 is valid. */
2534	PGMPTWALKGSTTYPE_AMD64,
2535	/** PGMPTWALKGST::u.Pae is valid. */
2536	PGMPTWALKGSTTYPE_PAE,
2537	/** PGMPTWALKGST::u.Legacy is valid. */
2538	PGMPTWALKGSTTYPE_32BIT,
2539	/** PGMPTWALKGST::u.Ept is valid. */
2540	PGMPTWALKGSTTYPE_EPT,
2541	/** Customary 32-bit type hack. */
2542	PGMPTWALKGSTTYPE_32BIT_HACK = 0x7fff0000
2543	} PGMPTWALKGSTTYPE;
2544
2545	/**
2546	* Combined guest page table walk result.
2547	*/
2548	typedef struct PGMPTWALKGST
2549	{
2550	union
2551	{
2552	/** The page walker for AMD64. */
2553	PGMPTWALKGSTAMD64 Amd64;
2554	/** The page walker for PAE (32-bit). */
2555	PGMPTWALKGSTPAE Pae;
2556	/** The page walker for 32-bit paging (called legacy due to C naming
2557	* convension). */
2558	PGMPTWALKGST32BIT Legacy;
2559	/** The page walker for EPT (SLAT). */
2560	PGMPTWALKGSTEPT Ept;
2561	} u;
2562	/** Indicates which part of the union is valid. */
2563	PGMPTWALKGSTTYPE enmType;
2564	} PGMPTWALKGST;
2565	/** Pointer to a combined guest page table walk result. */
2566	typedef PGMPTWALKGST *PPGMPTWALKGST;
2567	/** Pointer to a read-only combined guest page table walk result. */
2568	typedef PGMPTWALKGST const *PCPGMPTWALKGST;
2569
2570
2571	/** @name Paging mode macros
2572	* @{
2573	*/
2574	#ifdef IN_RING3
2575	# define PGM_CTX(a,b) a##R3##b
2576	# define PGM_CTX_STR(a,b) a "R3" b
2577	# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2578	#elif defined(IN_RING0)
2579	# define PGM_CTX(a,b) a##R0##b
2580	# define PGM_CTX_STR(a,b) a "R0" b
2581	# define PGM_CTX_DECL(type) VMMDECL(type)
2582	#else
2583	# error "Not IN_RING3 or IN_RING0!"
2584	#endif
2585
2586	#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2587	#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2588	#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2589	#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2590	#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2591	#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2592	#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2593	#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2594	#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2595	#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2596	#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2597	#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2598	#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2599	#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2600	#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2601	#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2602
2603	#define PGM_GST_SLAT_NAME_EPT(name) PGM_CTX(pgm,GstSlatEpt##name)
2604	#define PGM_GST_SLAT_NAME_RC_EPT_STR(name) "pgmRCGstSlatEpt" #name
2605	#define PGM_GST_SLAT_NAME_R0_EPT_STR(name) "pgmR0GstSlatEpt" #name
2606	#define PGM_GST_SLAT_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_SLAT_NAME(name)
2607
2608	#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2609	#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2610	#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2611	#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2612	#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2613	#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2614	#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2615	#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2616	#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2617	#define PGM_SHW_NAME_NESTED_32BIT(name) PGM_CTX(pgm,ShwNested32Bit##name)
2618	#define PGM_SHW_NAME_RC_NESTED_32BIT_STR(name) "pgmRCShwNested32Bit" #name
2619	#define PGM_SHW_NAME_R0_NESTED_32BIT_STR(name) "pgmR0ShwNested32Bit" #name
2620	#define PGM_SHW_NAME_NESTED_PAE(name) PGM_CTX(pgm,ShwNestedPAE##name)
2621	#define PGM_SHW_NAME_RC_NESTED_PAE_STR(name) "pgmRCShwNestedPAE" #name
2622	#define PGM_SHW_NAME_R0_NESTED_PAE_STR(name) "pgmR0ShwNestedPAE" #name
2623	#define PGM_SHW_NAME_NESTED_AMD64(name) PGM_CTX(pgm,ShwNestedAMD64##name)
2624	#define PGM_SHW_NAME_RC_NESTED_AMD64_STR(name) "pgmRCShwNestedAMD64" #name
2625	#define PGM_SHW_NAME_R0_NESTED_AMD64_STR(name) "pgmR0ShwNestedAMD64" #name
2626	#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2627	#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2628	#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2629	#define PGM_SHW_NAME_NONE(name) PGM_CTX(pgm,ShwNone##name)
2630	#define PGM_SHW_NAME_RC_NONE_STR(name) "pgmRCShwNone" #name
2631	#define PGM_SHW_NAME_R0_NONE_STR(name) "pgmR0ShwNone" #name
2632	#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2633
2634	/* Shw_Gst */
2635	#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2636	#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2637	#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2638	#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2639	#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2640	#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2641	#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2642	#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2643	#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2644	#define PGM_BTH_NAME_NESTED_32BIT_REAL(name) PGM_CTX(pgm,BthNested32BitReal##name)
2645	#define PGM_BTH_NAME_NESTED_32BIT_PROT(name) PGM_CTX(pgm,BthNested32BitProt##name)
2646	#define PGM_BTH_NAME_NESTED_32BIT_32BIT(name) PGM_CTX(pgm,BthNested32Bit32Bit##name)
2647	#define PGM_BTH_NAME_NESTED_32BIT_PAE(name) PGM_CTX(pgm,BthNested32BitPAE##name)
2648	#define PGM_BTH_NAME_NESTED_32BIT_AMD64(name) PGM_CTX(pgm,BthNested32BitAMD64##name)
2649	#define PGM_BTH_NAME_NESTED_PAE_REAL(name) PGM_CTX(pgm,BthNestedPAEReal##name)
2650	#define PGM_BTH_NAME_NESTED_PAE_PROT(name) PGM_CTX(pgm,BthNestedPAEProt##name)
2651	#define PGM_BTH_NAME_NESTED_PAE_32BIT(name) PGM_CTX(pgm,BthNestedPAE32Bit##name)
2652	#define PGM_BTH_NAME_NESTED_PAE_PAE(name) PGM_CTX(pgm,BthNestedPAEPAE##name)
2653	#define PGM_BTH_NAME_NESTED_PAE_AMD64(name) PGM_CTX(pgm,BthNestedPAEAMD64##name)
2654	#define PGM_BTH_NAME_NESTED_AMD64_REAL(name) PGM_CTX(pgm,BthNestedAMD64Real##name)
2655	#define PGM_BTH_NAME_NESTED_AMD64_PROT(name) PGM_CTX(pgm,BthNestedAMD64Prot##name)
2656	#define PGM_BTH_NAME_NESTED_AMD64_32BIT(name) PGM_CTX(pgm,BthNestedAMD6432Bit##name)
2657	#define PGM_BTH_NAME_NESTED_AMD64_PAE(name) PGM_CTX(pgm,BthNestedAMD64PAE##name)
2658	#define PGM_BTH_NAME_NESTED_AMD64_AMD64(name) PGM_CTX(pgm,BthNestedAMD64AMD64##name)
2659	#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2660	#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2661	#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2662	#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2663	#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2664	#define PGM_BTH_NAME_NONE_REAL(name) PGM_CTX(pgm,BthNoneReal##name)
2665	#define PGM_BTH_NAME_NONE_PROT(name) PGM_CTX(pgm,BthNoneProt##name)
2666	#define PGM_BTH_NAME_NONE_32BIT(name) PGM_CTX(pgm,BthNone32Bit##name)
2667	#define PGM_BTH_NAME_NONE_PAE(name) PGM_CTX(pgm,BthNonePAE##name)
2668	#define PGM_BTH_NAME_NONE_AMD64(name) PGM_CTX(pgm,BthNoneAMD64##name)
2669
2670	#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2671	#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2672	#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2673	#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2674	#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2675	#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2676	#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2677	#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2678	#define PGM_BTH_NAME_RC_NESTED_32BIT_REAL_STR(name) "pgmRCBthNested32BitReal" #name
2679	#define PGM_BTH_NAME_RC_NESTED_32BIT_PROT_STR(name) "pgmRCBthNested32BitProt" #name
2680	#define PGM_BTH_NAME_RC_NESTED_32BIT_32BIT_STR(name) "pgmRCBthNested32Bit32Bit" #name
2681	#define PGM_BTH_NAME_RC_NESTED_32BIT_PAE_STR(name) "pgmRCBthNested32BitPAE" #name
2682	#define PGM_BTH_NAME_RC_NESTED_32BIT_AMD64_STR(name) "pgmRCBthNested32BitAMD64" #name
2683	#define PGM_BTH_NAME_RC_NESTED_PAE_REAL_STR(name) "pgmRCBthNestedPAEReal" #name
2684	#define PGM_BTH_NAME_RC_NESTED_PAE_PROT_STR(name) "pgmRCBthNestedPAEProt" #name
2685	#define PGM_BTH_NAME_RC_NESTED_PAE_32BIT_STR(name) "pgmRCBthNestedPAE32Bit" #name
2686	#define PGM_BTH_NAME_RC_NESTED_PAE_PAE_STR(name) "pgmRCBthNestedPAEPAE" #name
2687	#define PGM_BTH_NAME_RC_NESTED_PAE_AMD64_STR(name) "pgmRCBthNestedPAEAMD64" #name
2688	#define PGM_BTH_NAME_RC_NESTED_AMD64_REAL_STR(name) "pgmRCBthNestedAMD64Real" #name
2689	#define PGM_BTH_NAME_RC_NESTED_AMD64_PROT_STR(name) "pgmRCBthNestedAMD64Prot" #name
2690	#define PGM_BTH_NAME_RC_NESTED_AMD64_32BIT_STR(name) "pgmRCBthNestedAMD6432Bit" #name
2691	#define PGM_BTH_NAME_RC_NESTED_AMD64_PAE_STR(name) "pgmRCBthNestedAMD64PAE" #name
2692	#define PGM_BTH_NAME_RC_NESTED_AMD64_AMD64_STR(name) "pgmRCBthNestedAMD64AMD64" #name
2693	#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2694	#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2695	#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2696	#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2697	#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2698
2699	#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2700	#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2701	#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2702	#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2703	#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2704	#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2705	#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2706	#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2707	#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2708	#define PGM_BTH_NAME_R0_NESTED_32BIT_REAL_STR(name) "pgmR0BthNested32BitReal" #name
2709	#define PGM_BTH_NAME_R0_NESTED_32BIT_PROT_STR(name) "pgmR0BthNested32BitProt" #name
2710	#define PGM_BTH_NAME_R0_NESTED_32BIT_32BIT_STR(name) "pgmR0BthNested32Bit32Bit" #name
2711	#define PGM_BTH_NAME_R0_NESTED_32BIT_PAE_STR(name) "pgmR0BthNested32BitPAE" #name
2712	#define PGM_BTH_NAME_R0_NESTED_32BIT_AMD64_STR(name) "pgmR0BthNested32BitAMD64" #name
2713	#define PGM_BTH_NAME_R0_NESTED_PAE_REAL_STR(name) "pgmR0BthNestedPAEReal" #name
2714	#define PGM_BTH_NAME_R0_NESTED_PAE_PROT_STR(name) "pgmR0BthNestedPAEProt" #name
2715	#define PGM_BTH_NAME_R0_NESTED_PAE_32BIT_STR(name) "pgmR0BthNestedPAE32Bit" #name
2716	#define PGM_BTH_NAME_R0_NESTED_PAE_PAE_STR(name) "pgmR0BthNestedPAEPAE" #name
2717	#define PGM_BTH_NAME_R0_NESTED_PAE_AMD64_STR(name) "pgmR0BthNestedPAEAMD64" #name
2718	#define PGM_BTH_NAME_R0_NESTED_AMD64_REAL_STR(name) "pgmR0BthNestedAMD64Real" #name
2719	#define PGM_BTH_NAME_R0_NESTED_AMD64_PROT_STR(name) "pgmR0BthNestedAMD64Prot" #name
2720	#define PGM_BTH_NAME_R0_NESTED_AMD64_32BIT_STR(name) "pgmR0BthNestedAMD6432Bit" #name
2721	#define PGM_BTH_NAME_R0_NESTED_AMD64_PAE_STR(name) "pgmR0BthNestedAMD64PAE" #name
2722	#define PGM_BTH_NAME_R0_NESTED_AMD64_AMD64_STR(name) "pgmR0BthNestedAMD64AMD64" #name
2723	#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2724	#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2725	#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2726	#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2727	#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2728
2729	#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2730	/** @} */
2731
2732
2733	/**
2734	* Function pointers for guest paging.
2735	*/
2736	typedef struct PGMMODEDATAGST
2737	{
2738	/** The guest mode type. */
2739	uint32_t uType;
2740	DECLCALLBACKMEMBER(int, pfnGetPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk));
2741	DECLCALLBACKMEMBER(int, pfnModifyPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2742	DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2743	DECLCALLBACKMEMBER(int, pfnExit,(PVMCPUCC pVCpu));
2744	#ifdef IN_RING3
2745	DECLCALLBACKMEMBER(int, pfnRelocate,(PVMCPUCC pVCpu, RTGCPTR offDelta)); /*< Only in ring-3. /
2746	#endif
2747	} PGMMODEDATAGST;
2748
2749	/** The length of g_aPgmGuestModeData. */
2750	#if VBOX_WITH_64_BITS_GUESTS
2751	# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_AMD64 + 1)
2752	#else
2753	# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_PAE + 1)
2754	#endif
2755	/** The guest mode data array. */
2756	extern PGMMODEDATAGST const g_aPgmGuestModeData[PGM_GUEST_MODE_DATA_ARRAY_SIZE];
2757
2758
2759	/**
2760	* Function pointers for shadow paging.
2761	*/
2762	typedef struct PGMMODEDATASHW
2763	{
2764	/** The shadow mode type. */
2765	uint32_t uType;
2766	DECLCALLBACKMEMBER(int, pfnGetPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2767	DECLCALLBACKMEMBER(int, pfnModifyPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags,
2768	uint64_t fMask, uint32_t fOpFlags));
2769	DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu));
2770	DECLCALLBACKMEMBER(int, pfnExit,(PVMCPUCC pVCpu));
2771	#ifdef IN_RING3
2772	DECLCALLBACKMEMBER(int, pfnRelocate,(PVMCPUCC pVCpu, RTGCPTR offDelta)); /*< Only in ring-3. /
2773	#endif
2774	} PGMMODEDATASHW;
2775
2776	/** The length of g_aPgmShadowModeData. */
2777	#define PGM_SHADOW_MODE_DATA_ARRAY_SIZE PGM_TYPE_END
2778	/** The shadow mode data array. */
2779	extern PGMMODEDATASHW const g_aPgmShadowModeData[PGM_SHADOW_MODE_DATA_ARRAY_SIZE];
2780
2781
2782	/**
2783	* Function pointers for guest+shadow paging.
2784	*/
2785	typedef struct PGMMODEDATABTH
2786	{
2787	/** The shadow mode type. */
2788	uint32_t uShwType;
2789	/** The guest mode type. */
2790	uint32_t uGstType;
2791
2792	DECLCALLBACKMEMBER(int, pfnInvalidatePage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage));
2793	DECLCALLBACKMEMBER(int, pfnSyncCR3,(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2794	DECLCALLBACKMEMBER(int, pfnPrefetchPage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage));
2795	DECLCALLBACKMEMBER(int, pfnVerifyAccessSyncPage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2796	DECLCALLBACKMEMBER(int, pfnMapCR3,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2797	DECLCALLBACKMEMBER(int, pfnUnmapCR3,(PVMCPUCC pVCpu));
2798	DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2799	#ifndef IN_RING3
2800	DECLCALLBACKMEMBER(int, pfnTrap0eHandler,(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPTR pvFault, bool *pfLockTaken));
2801	DECLCALLBACKMEMBER(int, pfnNestedTrap0eHandler,(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPHYS GCPhysNested,
2802	bool fIsLinearAddrValid, RTGCPTR GCPtrNested, PPGMPTWALK pWalk,
2803	bool *pfLockTaken));
2804	#endif
2805	#ifdef VBOX_STRICT
2806	DECLCALLBACKMEMBER(unsigned, pfnAssertCR3,(PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2807	#endif
2808	} PGMMODEDATABTH;
2809
2810	/** The length of g_aPgmBothModeData. */
2811	#define PGM_BOTH_MODE_DATA_ARRAY_SIZE ((PGM_TYPE_END - PGM_TYPE_FIRST_SHADOW) * PGM_TYPE_END)
2812	/** The guest+shadow mode data array. */
2813	extern PGMMODEDATABTH const g_aPgmBothModeData[PGM_BOTH_MODE_DATA_ARRAY_SIZE];
2814
2815
2816	#ifdef VBOX_WITH_STATISTICS
2817	/**
2818	* PGM statistics.
2819	*/
2820	typedef struct PGMSTATS
2821	{
2822	/* R3 only: */
2823	STAMCOUNTER StatR3DetectedConflicts; /*< R3: Number of times PGMR3MapHasConflicts() detected a conflict. /
2824	STAMPROFILE StatR3ResolveConflict; /*< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). /
2825
2826	/* R3+RZ */
2827	STAMCOUNTER StatRZChunkR3MapTlbHits; /*< RC/R0: Ring-3/0 chunk mapper TLB hits. /
2828	STAMCOUNTER StatRZChunkR3MapTlbMisses; /*< RC/R0: Ring-3/0 chunk mapper TLB misses. /
2829	STAMCOUNTER StatRZPageMapTlbHits; /*< RC/R0: Ring-3/0 page mapper TLB hits. /
2830	STAMCOUNTER StatRZPageMapTlbMisses; /*< RC/R0: Ring-3/0 page mapper TLB misses. /
2831	STAMCOUNTER StatPageMapTlbFlushes; /*< ALL: Ring-3/0 page mapper TLB flushes. /
2832	STAMCOUNTER StatPageMapTlbFlushEntry; /*< ALL: Ring-3/0 page mapper TLB flushes. /
2833	STAMCOUNTER StatR3ChunkR3MapTlbHits; /*< R3: Ring-3/0 chunk mapper TLB hits. /
2834	STAMCOUNTER StatR3ChunkR3MapTlbMisses; /*< R3: Ring-3/0 chunk mapper TLB misses. /
2835	STAMCOUNTER StatR3PageMapTlbHits; /*< R3: Ring-3/0 page mapper TLB hits. /
2836	STAMCOUNTER StatR3PageMapTlbMisses; /*< R3: Ring-3/0 page mapper TLB misses. /
2837	STAMCOUNTER StatRZRamRangeTlbHits; /*< RC/R0: RAM range TLB hits. /
2838	STAMCOUNTER StatRZRamRangeTlbMisses; /*< RC/R0: RAM range TLB misses. /
2839	STAMCOUNTER StatR3RamRangeTlbHits; /*< R3: RAM range TLB hits. /
2840	STAMCOUNTER StatR3RamRangeTlbMisses; /*< R3: RAM range TLB misses. /
2841	STAMCOUNTER StatR3PhysHandlerReset; /*< R3: The number of times PGMHandlerPhysicalReset is called. /
2842	STAMCOUNTER StatRZPhysHandlerReset; /*< RC/R0: The number of times PGMHandlerPhysicalReset is called. /
2843	STAMCOUNTER StatR3PhysHandlerLookupHits; /*< R3: Number of cache hits when looking up physical handlers. /
2844	STAMCOUNTER StatR3PhysHandlerLookupMisses; /*< R3: Number of cache misses when looking up physical handlers. /
2845	STAMCOUNTER StatRZPhysHandlerLookupHits; /*< RC/R0: Number of cache hits when lookup up physical handlers. /
2846	STAMCOUNTER StatRZPhysHandlerLookupMisses; /*< RC/R0: Number of cache misses when looking up physical handlers /
2847	STAMCOUNTER StatRZPageReplaceShared; /*< RC/R0: Times a shared page has been replaced by a private one. /
2848	STAMCOUNTER StatRZPageReplaceZero; /*< RC/R0: Times the zero page has been replaced by a private one. /
2849	/// @todo STAMCOUNTER StatRZPageHandyAllocs; /*< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. /
2850	STAMCOUNTER StatR3PageReplaceShared; /*< R3: Times a shared page has been replaced by a private one. /
2851	STAMCOUNTER StatR3PageReplaceZero; /*< R3: Times the zero page has been replaced by a private one. /
2852	/// @todo STAMCOUNTER StatR3PageHandyAllocs; /*< R3: The number of times we've executed GMMR3AllocateHandyPages. /
2853
2854	/* RC only: */
2855	STAMCOUNTER StatRCInvlPgConflict; /*< RC: Number of times PGMInvalidatePage() detected a mapping conflict. /
2856	STAMCOUNTER StatRCInvlPgSyncMonCR3; /*< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. /
2857
2858	STAMCOUNTER StatRZPhysRead;
2859	STAMCOUNTER StatRZPhysReadBytes;
2860	STAMCOUNTER StatRZPhysWrite;
2861	STAMCOUNTER StatRZPhysWriteBytes;
2862	STAMCOUNTER StatR3PhysRead;
2863	STAMCOUNTER StatR3PhysReadBytes;
2864	STAMCOUNTER StatR3PhysWrite;
2865	STAMCOUNTER StatR3PhysWriteBytes;
2866	STAMCOUNTER StatRCPhysRead;
2867	STAMCOUNTER StatRCPhysReadBytes;
2868	STAMCOUNTER StatRCPhysWrite;
2869	STAMCOUNTER StatRCPhysWriteBytes;
2870
2871	STAMCOUNTER StatRZPhysSimpleRead;
2872	STAMCOUNTER StatRZPhysSimpleReadBytes;
2873	STAMCOUNTER StatRZPhysSimpleWrite;
2874	STAMCOUNTER StatRZPhysSimpleWriteBytes;
2875	STAMCOUNTER StatR3PhysSimpleRead;
2876	STAMCOUNTER StatR3PhysSimpleReadBytes;
2877	STAMCOUNTER StatR3PhysSimpleWrite;
2878	STAMCOUNTER StatR3PhysSimpleWriteBytes;
2879	STAMCOUNTER StatRCPhysSimpleRead;
2880	STAMCOUNTER StatRCPhysSimpleReadBytes;
2881	STAMCOUNTER StatRCPhysSimpleWrite;
2882	STAMCOUNTER StatRCPhysSimpleWriteBytes;
2883
2884	STAMCOUNTER StatTrackVirgin; /*< The number of first time shadowings. /
2885	STAMCOUNTER StatTrackAliased; /*< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. /
2886	STAMCOUNTER StatTrackAliasedMany; /*< The number of times we're tracking using cRef2. /
2887	STAMCOUNTER StatTrackAliasedLots; /*< The number of times we're hitting pages which has overflowed cRef2. /
2888	STAMCOUNTER StatTrackNoExtentsLeft; /*< The number of times the extent list was exhausted. /
2889	STAMCOUNTER StatTrackOverflows; /*< The number of times the extent list grows to long. /
2890	STAMPROFILE StatTrackDeref; /*< Profiling of SyncPageWorkerTrackDeref (expensive). /
2891
2892	STAMPROFILE StatLargePageAlloc2; /*< Time spent setting up newly allocated large pages. /
2893	STAMPROFILE StatLargePageSetup; /*< Time spent setting up newly allocated large pages. /
2894	/** pgmPhysIsValidLargePage profiling - R3 */
2895	STAMPROFILE StatR3IsValidLargePage;
2896	/** pgmPhysIsValidLargePage profiling - RZ*/
2897	STAMPROFILE StatRZIsValidLargePage;
2898
2899	STAMPROFILE StatChunkAging;
2900	STAMPROFILE StatChunkFindCandidate;
2901	STAMPROFILE StatChunkUnmap;
2902	STAMPROFILE StatChunkMap;
2903	} PGMSTATS;
2904	#endif /* VBOX_WITH_STATISTICS */
2905
2906
2907	/**
2908	* PGM Data (part of VM)
2909	*/
2910	typedef struct PGM
2911	{
2912	/** The zero page. */
2913	uint8_t abZeroPg[RT_MAX(HOST_PAGE_SIZE, GUEST_PAGE_SIZE)];
2914	/** The MMIO placeholder page. */
2915	uint8_t abMmioPg[RT_MAX(HOST_PAGE_SIZE, GUEST_PAGE_SIZE)];
2916
2917	/** @name The zero page (abPagePg).
2918	* @{ */
2919	/** The host physical address of the zero page. */
2920	RTHCPHYS HCPhysZeroPg;
2921	/** @}*/
2922
2923	/** @name The Invalid MMIO page (abMmioPg).
2924	* This page is filled with 0xfeedface.
2925	* @{ */
2926	/** The host physical address of the invalid MMIO page. */
2927	RTHCPHYS HCPhysMmioPg;
2928	/** The host pysical address of the invalid MMIO page plus all invalid
2929	* physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
2930	* @remarks Check fLessThan52PhysicalAddressBits before use. */
2931	RTHCPHYS HCPhysInvMmioPg;
2932	/** @} */
2933
2934	/** @cfgm{/RamPreAlloc, boolean, false}
2935	* Indicates whether the base RAM should all be allocated before starting
2936	* the VM (default), or if it should be allocated when first written to.
2937	*/
2938	bool fRamPreAlloc;
2939	#ifdef VBOX_WITH_PGM_NEM_MODE
2940	/** Set if we're operating in NEM memory mode.
2941	*
2942	* NEM mode implies that memory is allocated in big chunks for each RAM range
2943	* rather than on demand page by page. Memory is also not locked and PGM has
2944	* therefore no physical addresses for them. Page sharing is out of the
2945	* question. Ballooning depends on the native execution engine, but probably
2946	* pointless as well. */
2947	bool fNemMode;
2948	# define PGM_IS_IN_NEM_MODE(a_pVM) ((a_pVM)->pgm.s.fNemMode)
2949	#else
2950	# define PGM_IS_IN_NEM_MODE(a_pVM) (false)
2951	#endif
2952	/** Indicates whether write monitoring is currently in use.
2953	* This is used to prevent conflicts between live saving and page sharing
2954	* detection. */
2955	bool fPhysWriteMonitoringEngaged;
2956	/** Set if the CPU has less than 52-bit physical address width.
2957	* This is used */
2958	bool fLessThan52PhysicalAddressBits;
2959	/** Set when nested paging is active.
2960	* This is meant to save calls to HMIsNestedPagingActive and let the
2961	* compilers optimize the code better. Whether we use nested paging or
2962	* not is something we find out during VMM initialization and we won't
2963	* change this later on. */
2964	bool fNestedPaging;
2965	/** We're not in a state which permits writes to guest memory.
2966	* (Only used in strict builds.) */
2967	bool fNoMorePhysWrites;
2968	/** @cfgm{/PageFusionAllowed, boolean, false}
2969	* Whether page fusion is allowed. */
2970	bool fPageFusionAllowed;
2971	/** @cfgm{/PGM/PciPassThrough, boolean, false}
2972	* Whether PCI passthrough is enabled. */
2973	bool fPciPassthrough;
2974	/** The number of MMIO2 regions (serves as the next MMIO2 ID). */
2975	uint8_t cMmio2Regions;
2976	/** Restore original ROM page content when resetting after loading state.
2977	* The flag is set by pgmR3LoadRomRanges and cleared at reset. This
2978	* enables the VM to start using an updated ROM without requiring powering
2979	* down the VM, just rebooting or resetting it. */
2980	bool fRestoreRomPagesOnReset;
2981	/** Whether to automatically clear all RAM pages on reset. */
2982	bool fZeroRamPagesOnReset;
2983	/** Large page enabled flag. */
2984	bool fUseLargePages;
2985	/** Alignment padding. */
2986	#ifndef VBOX_WITH_PGM_NEM_MODE
2987	bool afAlignment3[1];
2988	#endif
2989	/** The host paging mode. (This is what SUPLib reports.) */
2990	SUPPAGINGMODE enmHostMode;
2991	bool afAlignment3b[2];
2992
2993	/** Generation ID for the RAM ranges. This member is incremented everytime
2994	* a RAM range is linked or unlinked. */
2995	uint32_t volatile idRamRangesGen;
2996
2997	/** Physical access handler type for ROM protection. */
2998	PGMPHYSHANDLERTYPE hRomPhysHandlerType;
2999	/** Physical access handler type for MMIO2 dirty page tracing. */
3000	PGMPHYSHANDLERTYPE hMmio2DirtyPhysHandlerType;
3001
3002	/** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
3003	RTGCPHYS GCPhys4MBPSEMask;
3004	/** Mask containing the invalid bits of a guest physical address.
3005	* @remarks this does not stop at bit 52. */
3006	RTGCPHYS GCPhysInvAddrMask;
3007
3008
3009	/** RAM range TLB for R3. */
3010	R3PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR3[PGM_RAMRANGE_TLB_ENTRIES];
3011	/** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
3012	* This is sorted by physical address and contains no overlapping ranges. */
3013	R3PTRTYPE(PPGMRAMRANGE) pRamRangesXR3;
3014	/** Root of the RAM range search tree for ring-3. */
3015	R3PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR3;
3016	/** Shadow Page Pool - R3 Ptr. */
3017	R3PTRTYPE(PPGMPOOL) pPoolR3;
3018	/** Pointer to the list of ROM ranges - for R3.
3019	* This is sorted by physical address and contains no overlapping ranges. */
3020	R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
3021	/** Pointer to the list of MMIO2 ranges - for R3.
3022	* Registration order. */
3023	R3PTRTYPE(PPGMREGMMIO2RANGE) pRegMmioRangesR3;
3024	/** MMIO2 lookup array for ring-3. Indexed by idMmio2 minus 1. */
3025	R3PTRTYPE(PPGMREGMMIO2RANGE) apMmio2RangesR3[PGM_MMIO2_MAX_RANGES];
3026
3027	/** RAM range TLB for R0. */
3028	R0PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR0[PGM_RAMRANGE_TLB_ENTRIES];
3029	/** R0 pointer corresponding to PGM::pRamRangesXR3. */
3030	R0PTRTYPE(PPGMRAMRANGE) pRamRangesXR0;
3031	/** Root of the RAM range search tree for ring-0. */
3032	R0PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR0;
3033	/** Shadow Page Pool - R0 Ptr. */
3034	R0PTRTYPE(PPGMPOOL) pPoolR0;
3035	/** R0 pointer corresponding to PGM::pRomRangesR3. */
3036	R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
3037	/** MMIO2 lookup array for ring-0. Indexed by idMmio2 minus 1. */
3038	R0PTRTYPE(PPGMREGMMIO2RANGE) apMmio2RangesR0[PGM_MMIO2_MAX_RANGES];
3039
3040	/** Hack: Number of deprecated page mapping locks taken by the current lock
3041	* owner via pgmPhysGCPhys2CCPtrInternalDepr. */
3042	uint32_t cDeprecatedPageLocks;
3043
3044	/** Registered physical access handler types. */
3045	uint32_t cPhysHandlerTypes;
3046	/** Physical access handler types.
3047	* Initialized to callback causing guru meditations and invalid enmKind. */
3048	PGMPHYSHANDLERTYPEINTR3 aPhysHandlerTypes[PGMPHYSHANDLERTYPE_COUNT];
3049	/** Physical handler allocator, ring-3 edition. */
3050	#ifdef IN_RING3
3051	PGMPHYSHANDLERALLOCATOR PhysHandlerAllocator;
3052	#else
3053	RTCHardAvlTreeSlabAllocatorR3_T PhysHandlerAllocator;
3054	#endif
3055	/** The pointer to the ring-3 mapping of the physical access handler tree. */
3056	R3PTRTYPE(PPGMPHYSHANDLERTREE) pPhysHandlerTree;
3057	/** Caching the last physical handler we looked. */
3058	uint32_t idxLastPhysHandler;
3059
3060	uint32_t au64Padding3[5];
3061
3062	/** PGM critical section.
3063	* This protects the physical, ram ranges, and the page flag updating (some of
3064	* it anyway).
3065	*/
3066	PDMCRITSECT CritSectX;
3067
3068	/**
3069	* Data associated with managing the ring-3 mappings of the allocation chunks.
3070	*/
3071	struct
3072	{
3073	/** The chunk mapping TLB. */
3074	PGMCHUNKR3MAPTLB Tlb;
3075	/** The chunk tree, ordered by chunk id. */
3076	R3PTRTYPE(PAVLU32NODECORE) pTree;
3077	#if HC_ARCH_BITS == 32
3078	uint32_t u32Alignment0;
3079	#endif
3080	/** The number of mapped chunks. */
3081	uint32_t c;
3082	/** @cfgm{/PGM/MaxRing3Chunks, uint32_t, host dependent}
3083	* The maximum number of mapped chunks. On 64-bit this is unlimited by default,
3084	* on 32-bit it defaults to 1 or 3 GB depending on the host. */
3085	uint32_t cMax;
3086	/** The current time. This is incremented whenever a chunk is inserted. */
3087	uint32_t iNow;
3088	/** Alignment padding. */
3089	uint32_t au32Alignment1[3];
3090	} ChunkR3Map;
3091
3092	/** The page mapping TLB for ring-3. */
3093	PGMPAGER3MAPTLB PhysTlbR3;
3094	/** The page mapping TLB for ring-0. */
3095	PGMPAGER0MAPTLB PhysTlbR0;
3096
3097	/** The number of handy pages. */
3098	uint32_t cHandyPages;
3099
3100	/** The number of large handy pages. */
3101	uint32_t cLargeHandyPages;
3102
3103	/**
3104	* Array of handy pages.
3105	*
3106	* This array is used in a two way communication between pgmPhysAllocPage
3107	* and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3108	* an intermediary.
3109	*
3110	* The size of this array is important, see pgmPhysEnsureHandyPage for details.
3111	* (The current size of 32 pages, means 128 KB of handy memory.)
3112	*/
3113	GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3114
3115	/**
3116	* Array of large handy pages. (currently size 1)
3117	*
3118	* This array is used in a two way communication between pgmPhysAllocLargePage
3119	* and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3120	* an intermediary.
3121	*/
3122	GMMPAGEDESC aLargeHandyPage[1];
3123	/** When to try allocate large pages again after a failure. */
3124	uint64_t nsLargePageRetry;
3125	/** Number of repeated long allocation times. */
3126	uint32_t cLargePageLongAllocRepeats;
3127	uint32_t uPadding5;
3128
3129	/**
3130	* Live save data.
3131	*/
3132	struct
3133	{
3134	/** Per type statistics. */
3135	struct
3136	{
3137	/** The number of ready pages. */
3138	uint32_t cReadyPages;
3139	/** The number of dirty pages. */
3140	uint32_t cDirtyPages;
3141	/** The number of ready zero pages. */
3142	uint32_t cZeroPages;
3143	/** The number of write monitored pages. */
3144	uint32_t cMonitoredPages;
3145	} Rom,
3146	Mmio2,
3147	Ram;
3148	/** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3149	uint32_t cIgnoredPages;
3150	/** Indicates that a live save operation is active. */
3151	bool fActive;
3152	/** Padding. */
3153	bool afReserved[2];
3154	/** The next history index. */
3155	uint8_t iDirtyPagesHistory;
3156	/** History of the total amount of dirty pages. */
3157	uint32_t acDirtyPagesHistory[64];
3158	/** Short term dirty page average. */
3159	uint32_t cDirtyPagesShort;
3160	/** Long term dirty page average. */
3161	uint32_t cDirtyPagesLong;
3162	/** The number of saved pages. This is used to get some kind of estimate of the
3163	* link speed so we can decide when we're done. It is reset after the first
3164	* 7 passes so the speed estimate doesn't get inflated by the initial set of
3165	* zero pages. */
3166	uint64_t cSavedPages;
3167	/** The nanosecond timestamp when cSavedPages was 0. */
3168	uint64_t uSaveStartNS;
3169	/** Pages per second (for statistics). */
3170	uint32_t cPagesPerSecond;
3171	uint32_t cAlignment;
3172	} LiveSave;
3173
3174	/** @name Error injection.
3175	* @{ */
3176	/** Inject handy page allocation errors pretending we're completely out of
3177	* memory. */
3178	bool volatile fErrInjHandyPages;
3179	/** Padding. */
3180	bool afReserved[3];
3181	/** @} */
3182
3183	/** @name Release Statistics
3184	* @{ */
3185	uint32_t cAllPages; /*< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) /
3186	uint32_t cPrivatePages; /*< The number of private pages. /
3187	uint32_t cSharedPages; /*< The number of shared pages. /
3188	uint32_t cReusedSharedPages; /*< The number of reused shared pages. /
3189	uint32_t cZeroPages; /*< The number of zero backed pages. /
3190	uint32_t cPureMmioPages; /*< The number of pure MMIO pages. /
3191	uint32_t cMonitoredPages; /*< The number of write monitored pages. /
3192	uint32_t cWrittenToPages; /*< The number of previously write monitored pages. /
3193	uint32_t cWriteLockedPages; /*< The number of write locked pages. /
3194	uint32_t cReadLockedPages; /*< The number of read locked pages. /
3195	uint32_t cBalloonedPages; /*< The number of ballooned pages. /
3196	uint32_t cMappedChunks; /*< Number of times we mapped a chunk. /
3197	uint32_t cUnmappedChunks; /*< Number of times we unmapped a chunk. /
3198	uint32_t cLargePages; /*< The number of large pages. /
3199	uint32_t cLargePagesDisabled; /*< The number of disabled large pages. /
3200	/* uint32_t aAlignment4[1]; */
3201
3202	STAMPROFILE StatLargePageAlloc; /*< Time spent by the host OS for large page allocation. /
3203	STAMCOUNTER StatLargePageAllocFailed; /*< Count allocation failures. /
3204	STAMCOUNTER StatLargePageOverflow; /*< The number of times allocating a large pages takes more than the allowed period. /
3205	STAMCOUNTER StatLargePageReused; /*< The number of large pages we've reused./
3206	STAMCOUNTER StatLargePageRefused; /*< The number of times we couldn't use a large page./
3207	STAMCOUNTER StatLargePageRecheck; /*< The number of times we rechecked a disabled large page./
3208	STAMCOUNTER StatLargePageTlbFlush; /*< The number of a full VCPU TLB flush was required after allocation. /
3209	STAMCOUNTER StatLargePageZeroEvict; /*< The number of zero page mappings we had to evict when allocating a large page. /
3210
3211	STAMPROFILE StatShModCheck; /*< Profiles shared module checks. /
3212
3213	STAMPROFILE StatMmio2QueryAndResetDirtyBitmap; /*< Profiling PGMR3PhysMmio2QueryAndResetDirtyBitmap. /
3214	/** @} */
3215
3216	#ifdef VBOX_WITH_STATISTICS
3217	/** These are optional statistics that used to be on the hyper heap. */
3218	PGMSTATS Stats;
3219	#endif
3220	} PGM;
3221	#ifndef IN_TSTVMSTRUCTGC /* HACK */
3222	AssertCompileMemberAlignment(PGM, CritSectX, 8);
3223	AssertCompileMemberAlignment(PGM, ChunkR3Map, 16);
3224	AssertCompileMemberAlignment(PGM, PhysTlbR3, 32); /** @todo 32 byte alignment! */
3225	AssertCompileMemberAlignment(PGM, PhysTlbR0, 32);
3226	AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3227	AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3228	#endif /* !IN_TSTVMSTRUCTGC */
3229	/** Pointer to the PGM instance data. */
3230	typedef PGM *PPGM;
3231
3232
3233	#ifdef VBOX_WITH_STATISTICS
3234	/**
3235	* Per CPU statistis for PGM (used to be on the heap).
3236	*/
3237	typedef struct PGMCPUSTATS
3238	{
3239	/* Common */
3240	STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /*< SyncPT - PD distribution. /
3241	STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /*< SyncPage - PD distribution. /
3242
3243	/* R0 only: */
3244	STAMPROFILE StatR0NpMiscfg; /*< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. /
3245	STAMCOUNTER StatR0NpMiscfgSyncPage; /*< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). /
3246
3247	/* RZ only: */
3248	STAMPROFILE StatRZTrap0e; /*< RC/R0: PGMTrap0eHandler() profiling. /
3249	STAMPROFILE StatRZTrap0eTime2Ballooned; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. /
3250	STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. /
3251	STAMPROFILE StatRZTrap0eTime2GuestTrap; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. /
3252	STAMPROFILE StatRZTrap0eTime2HndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. /
3253	STAMPROFILE StatRZTrap0eTime2HndUnhandled; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. /
3254	STAMPROFILE StatRZTrap0eTime2InvalidPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. /
3255	STAMPROFILE StatRZTrap0eTime2MakeWritable; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. /
3256	STAMPROFILE StatRZTrap0eTime2Misc; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. /
3257	STAMPROFILE StatRZTrap0eTime2OutOfSync; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. /
3258	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. /
3259	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. /
3260	STAMPROFILE StatRZTrap0eTime2PageZeroing; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a zero page that is being zeroed. /
3261	STAMPROFILE StatRZTrap0eTime2SyncPT; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. /
3262	STAMPROFILE StatRZTrap0eTime2WPEmulation; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. /
3263	STAMPROFILE StatRZTrap0eTime2Wp0RoUsHack; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be enabled. /
3264	STAMPROFILE StatRZTrap0eTime2Wp0RoUsUnhack; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be disabled. /
3265	STAMCOUNTER StatRZTrap0eConflicts; /*< RC/R0: The number of times \#PF was caused by an undetected conflict. /
3266	STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /*< RC/R0: Number of out-of-sync handled pages. /
3267	STAMCOUNTER StatRZTrap0eHandlersPhysAll; /*< RC/R0: Number of traps due to physical all-access handlers. /
3268	STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /*< RC/R0: Number of the physical all-access handler traps using the optimization. /
3269	STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /*< RC/R0: Number of traps due to write-physical access handlers. /
3270	STAMCOUNTER StatRZTrap0eHandlersUnhandled; /*< RC/R0: Number of traps due to access outside range of monitored page(s). /
3271	STAMCOUNTER StatRZTrap0eHandlersInvalid; /*< RC/R0: Number of traps due to access to invalid physical memory. /
3272	STAMCOUNTER StatRZTrap0eUSNotPresentRead; /*< RC/R0: \#PF err kind /
3273	STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /*< RC/R0: \#PF err kind /
3274	STAMCOUNTER StatRZTrap0eUSWrite; /*< RC/R0: \#PF err kind /
3275	STAMCOUNTER StatRZTrap0eUSReserved; /*< RC/R0: \#PF err kind /
3276	STAMCOUNTER StatRZTrap0eUSNXE; /*< RC/R0: \#PF err kind /
3277	STAMCOUNTER StatRZTrap0eUSRead; /*< RC/R0: \#PF err kind /
3278	STAMCOUNTER StatRZTrap0eSVNotPresentRead; /*< RC/R0: \#PF err kind /
3279	STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /*< RC/R0: \#PF err kind /
3280	STAMCOUNTER StatRZTrap0eSVWrite; /*< RC/R0: \#PF err kind /
3281	STAMCOUNTER StatRZTrap0eSVReserved; /*< RC/R0: \#PF err kind /
3282	STAMCOUNTER StatRZTrap0eSNXE; /*< RC/R0: \#PF err kind /
3283	STAMCOUNTER StatRZTrap0eGuestPF; /*< RC/R0: Real guest \#PFs. /
3284	STAMCOUNTER StatRZTrap0eWPEmulInRZ; /*< RC/R0: WP=0 virtualization trap, handled. /
3285	STAMCOUNTER StatRZTrap0eWPEmulToR3; /*< RC/R0: WP=0 virtualization trap, chickened out. /
3286	STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /*< RC/R0: PD distribution of the \#PFs. /
3287	STAMCOUNTER StatRZGuestCR3WriteHandled; /*< RC/R0: The number of times WriteHandlerCR3() was successfully called. /
3288	STAMCOUNTER StatRZGuestCR3WriteUnhandled; /*< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. /
3289	STAMCOUNTER StatRZGuestCR3WriteConflict; /*< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. /
3290	STAMCOUNTER StatRZGuestROMWriteHandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. /
3291	STAMCOUNTER StatRZGuestROMWriteUnhandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler /
3292	STAMCOUNTER StatRZDynMapMigrateInvlPg; /*< RZ: invlpg in PGMR0DynMapMigrateAutoSet. /
3293	STAMPROFILE StatRZDynMapGCPageInl; /*< RZ: Calls to pgmRZDynMapGCPageInlined. /
3294	STAMCOUNTER StatRZDynMapGCPageInlHits; /*< RZ: Hash table lookup hits. /
3295	STAMCOUNTER StatRZDynMapGCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3296	STAMCOUNTER StatRZDynMapGCPageInlRamHits; /*< RZ: 1st ram range hits. /
3297	STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /*< RZ: 1st ram range misses, takes slow path. /
3298	STAMPROFILE StatRZDynMapHCPageInl; /*< RZ: Calls to pgmRZDynMapHCPageInlined. /
3299	STAMCOUNTER StatRZDynMapHCPageInlHits; /*< RZ: Hash table lookup hits. /
3300	STAMCOUNTER StatRZDynMapHCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3301	STAMPROFILE StatRZDynMapHCPage; /*< RZ: Calls to pgmRZDynMapHCPageCommon. /
3302	STAMCOUNTER StatRZDynMapSetOptimize; /*< RZ: Calls to pgmRZDynMapOptimizeAutoSet. /
3303	STAMCOUNTER StatRZDynMapSetSearchFlushes; /*< RZ: Set search restoring to subset flushes. /
3304	STAMCOUNTER StatRZDynMapSetSearchHits; /*< RZ: Set search hits. /
3305	STAMCOUNTER StatRZDynMapSetSearchMisses; /*< RZ: Set search misses. /
3306	STAMCOUNTER StatRZDynMapPage; /*< RZ: Calls to pgmR0DynMapPage. /
3307	STAMCOUNTER StatRZDynMapPageHits0; /*< RZ: Hits at iPage+0. /
3308	STAMCOUNTER StatRZDynMapPageHits1; /*< RZ: Hits at iPage+1. /
3309	STAMCOUNTER StatRZDynMapPageHits2; /*< RZ: Hits at iPage+2. /
3310	STAMCOUNTER StatRZDynMapPageInvlPg; /*< RZ: invlpg. /
3311	STAMCOUNTER StatRZDynMapPageSlow; /*< RZ: Calls to pgmR0DynMapPageSlow. /
3312	STAMCOUNTER StatRZDynMapPageSlowLoopHits; /*< RZ: Hits in the pgmR0DynMapPageSlow search loop. /
3313	STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /*< RZ: Misses in the pgmR0DynMapPageSlow search loop. /
3314	//STAMCOUNTER StatRZDynMapPageSlowLostHits; /*< RZ: Lost hits. /
3315	STAMCOUNTER StatRZDynMapSubsets; /*< RZ: Times PGMDynMapPushAutoSubset was called. /
3316	STAMCOUNTER StatRZDynMapPopFlushes; /*< RZ: Times PGMDynMapPopAutoSubset flushes the subset. /
3317	STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /*< RZ: Set fill distribution, percent. /
3318
3319	/* HC - R3 and (maybe) R0: */
3320
3321	/* RZ & R3: */
3322	STAMPROFILE StatRZSyncCR3; /*< RC/R0: PGMSyncCR3() profiling. /
3323	STAMPROFILE StatRZSyncCR3Handlers; /*< RC/R0: Profiling of the PGMSyncCR3() update handler section. /
3324	STAMCOUNTER StatRZSyncCR3Global; /*< RC/R0: The number of global CR3 syncs. /
3325	STAMCOUNTER StatRZSyncCR3NotGlobal; /*< RC/R0: The number of non-global CR3 syncs. /
3326	STAMCOUNTER StatRZSyncCR3DstCacheHit; /*< RC/R0: The number of times we got some kind of cache hit on a page table. /
3327	STAMCOUNTER StatRZSyncCR3DstFreed; /*< RC/R0: The number of times we've had to free a shadow entry. /
3328	STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /*< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. /
3329	STAMCOUNTER StatRZSyncCR3DstNotPresent; /*< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. /
3330	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /*< RC/R0: The number of times a global page directory wasn't flushed. /
3331	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /*< RC/R0: The number of times a page table with only global entries wasn't flushed. /
3332	STAMPROFILE StatRZSyncPT; /*< RC/R0: PGMSyncPT() profiling. /
3333	STAMCOUNTER StatRZSyncPTFailed; /*< RC/R0: The number of times PGMSyncPT() failed. /
3334	STAMCOUNTER StatRZSyncPT4K; /*< RC/R0: Number of 4KB syncs. /
3335	STAMCOUNTER StatRZSyncPT4M; /*< RC/R0: Number of 4MB syncs. /
3336	STAMCOUNTER StatRZSyncPagePDNAs; /*< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3337	STAMCOUNTER StatRZSyncPagePDOutOfSync; /*< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. /
3338	STAMCOUNTER StatRZAccessedPage; /*< RC/R0: The number of pages marked not present for accessed bit emulation. /
3339	STAMPROFILE StatRZDirtyBitTracking; /*< RC/R0: Profiling the dirty bit tracking in CheckPageFault(). /
3340	STAMCOUNTER StatRZDirtyPage; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3341	STAMCOUNTER StatRZDirtyPageBig; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3342	STAMCOUNTER StatRZDirtyPageSkipped; /*< RC/R0: The number of pages already dirty or readonly. /
3343	STAMCOUNTER StatRZDirtyPageTrap; /*< RC/R0: The number of traps generated for dirty bit tracking. /
3344	STAMCOUNTER StatRZDirtyPageStale; /*< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) /
3345	STAMCOUNTER StatRZDirtyTrackRealPF; /*< RC/R0: The number of real pages faults during dirty bit tracking. /
3346	STAMCOUNTER StatRZDirtiedPage; /*< RC/R0: The number of pages marked dirty because of write accesses. /
3347	STAMCOUNTER StatRZPageAlreadyDirty; /*< RC/R0: The number of pages already marked dirty because of write accesses. /
3348	STAMPROFILE StatRZInvalidatePage; /*< RC/R0: PGMInvalidatePage() profiling. /
3349	STAMCOUNTER StatRZInvalidatePage4KBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. /
3350	STAMCOUNTER StatRZInvalidatePage4MBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. /
3351	STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /*< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. /
3352	STAMCOUNTER StatRZInvalidatePagePDNAs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3353	STAMCOUNTER StatRZInvalidatePagePDNPs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. /
3354	STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /*< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3355	STAMCOUNTER StatRZInvalidatePageSizeChanges ; /*< RC/R0: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). /
3356	STAMCOUNTER StatRZInvalidatePageSkipped; /*< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3357	STAMCOUNTER StatRZPageOutOfSyncUser; /*< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3358	STAMCOUNTER StatRZPageOutOfSyncSupervisor; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3359	STAMCOUNTER StatRZPageOutOfSyncUserWrite; /*< RC/R0: The number of times user page is out of sync was detected in \#PF. /
3360	STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. /
3361	STAMCOUNTER StatRZPageOutOfSyncBallloon; /*< RC/R0: The number of times a ballooned page was accessed (read). /
3362	STAMPROFILE StatRZPrefetch; /*< RC/R0: PGMPrefetchPage. /
3363	STAMPROFILE StatRZFlushTLB; /*< RC/R0: Profiling of the PGMFlushTLB() body. /
3364	STAMCOUNTER StatRZFlushTLBNewCR3; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3365	STAMCOUNTER StatRZFlushTLBNewCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3366	STAMCOUNTER StatRZFlushTLBSameCR3; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3367	STAMCOUNTER StatRZFlushTLBSameCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3368	STAMPROFILE StatRZGstModifyPage; /*< RC/R0: Profiling of the PGMGstModifyPage() body /
3369
3370	STAMPROFILE StatR3SyncCR3; /*< R3: PGMSyncCR3() profiling. /
3371	STAMPROFILE StatR3SyncCR3Handlers; /*< R3: Profiling of the PGMSyncCR3() update handler section. /
3372	STAMCOUNTER StatR3SyncCR3Global; /*< R3: The number of global CR3 syncs. /
3373	STAMCOUNTER StatR3SyncCR3NotGlobal; /*< R3: The number of non-global CR3 syncs. /
3374	STAMCOUNTER StatR3SyncCR3DstFreed; /*< R3: The number of times we've had to free a shadow entry. /
3375	STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /*< R3: The number of times we've had to free a shadow entry for which the source entry was not present. /
3376	STAMCOUNTER StatR3SyncCR3DstNotPresent; /*< R3: The number of times we've encountered a not present shadow entry for a present guest entry. /
3377	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /*< R3: The number of times a global page directory wasn't flushed. /
3378	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /*< R3: The number of times a page table with only global entries wasn't flushed. /
3379	STAMCOUNTER StatR3SyncCR3DstCacheHit; /*< R3: The number of times we got some kind of cache hit on a page table. /
3380	STAMPROFILE StatR3SyncPT; /*< R3: PGMSyncPT() profiling. /
3381	STAMCOUNTER StatR3SyncPTFailed; /*< R3: The number of times PGMSyncPT() failed. /
3382	STAMCOUNTER StatR3SyncPT4K; /*< R3: Number of 4KB syncs. /
3383	STAMCOUNTER StatR3SyncPT4M; /*< R3: Number of 4MB syncs. /
3384	STAMCOUNTER StatR3SyncPagePDNAs; /*< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3385	STAMCOUNTER StatR3SyncPagePDOutOfSync; /*< R3: The number of time we've encountered an out-of-sync PD in SyncPage. /
3386	STAMCOUNTER StatR3AccessedPage; /*< R3: The number of pages marked not present for accessed bit emulation. /
3387	STAMPROFILE StatR3DirtyBitTracking; /*< R3: Profiling the dirty bit tracking in CheckPageFault(). /
3388	STAMCOUNTER StatR3DirtyPage; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3389	STAMCOUNTER StatR3DirtyPageBig; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3390	STAMCOUNTER StatR3DirtyPageSkipped; /*< R3: The number of pages already dirty or readonly. /
3391	STAMCOUNTER StatR3DirtyPageTrap; /*< R3: The number of traps generated for dirty bit tracking. /
3392	STAMCOUNTER StatR3DirtyTrackRealPF; /*< R3: The number of real pages faults during dirty bit tracking. /
3393	STAMCOUNTER StatR3DirtiedPage; /*< R3: The number of pages marked dirty because of write accesses. /
3394	STAMCOUNTER StatR3PageAlreadyDirty; /*< R3: The number of pages already marked dirty because of write accesses. /
3395	STAMPROFILE StatR3InvalidatePage; /*< R3: PGMInvalidatePage() profiling. /
3396	STAMCOUNTER StatR3InvalidatePage4KBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4KB page. /
3397	STAMCOUNTER StatR3InvalidatePage4MBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4MB page. /
3398	STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /*< R3: The number of times PGMInvalidatePage() skipped a 4MB page. /
3399	STAMCOUNTER StatR3InvalidatePagePDNAs; /*< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3400	STAMCOUNTER StatR3InvalidatePagePDNPs; /*< R3: The number of times PGMInvalidatePage() was called for a not present page directory. /
3401	STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /*< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3402	STAMCOUNTER StatR3InvalidatePageSizeChanges ; /*< R3: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). /
3403	STAMCOUNTER StatR3InvalidatePageSkipped; /*< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3404	STAMCOUNTER StatR3PageOutOfSyncUser; /*< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3405	STAMCOUNTER StatR3PageOutOfSyncSupervisor; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3406	STAMCOUNTER StatR3PageOutOfSyncUserWrite; /*< R3: The number of times user page is out of sync was detected in \#PF. /
3407	STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF. /
3408	STAMCOUNTER StatR3PageOutOfSyncBallloon; /*< R3: The number of times a ballooned page was accessed (read). /
3409	STAMPROFILE StatR3Prefetch; /*< R3: PGMPrefetchPage. /
3410	STAMPROFILE StatR3FlushTLB; /*< R3: Profiling of the PGMFlushTLB() body. /
3411	STAMCOUNTER StatR3FlushTLBNewCR3; /*< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3412	STAMCOUNTER StatR3FlushTLBNewCR3Global; /*< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3413	STAMCOUNTER StatR3FlushTLBSameCR3; /*< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3414	STAMCOUNTER StatR3FlushTLBSameCR3Global; /*< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3415	STAMPROFILE StatR3GstModifyPage; /*< R3: Profiling of the PGMGstModifyPage() body /
3416	} PGMCPUSTATS;
3417	#endif /* VBOX_WITH_STATISTICS */
3418
3419
3420	/**
3421	* PGMCPU Data (part of VMCPU).
3422	*/
3423	typedef struct PGMCPU
3424	{
3425	/** A20 gate mask.
3426	* Our current approach to A20 emulation is to let REM do it and don't bother
3427	* anywhere else. The interesting Guests will be operating with it enabled anyway.
3428	* But whould need arrise, we'll subject physical addresses to this mask. */
3429	RTGCPHYS GCPhysA20Mask;
3430	/** A20 gate state - boolean! */
3431	bool fA20Enabled;
3432	/** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3433	bool fNoExecuteEnabled;
3434	/** Whether the guest CR3 and PAE PDPEs have been mapped when guest PAE mode is
3435	* active. */
3436	bool fPaePdpesAndCr3MappedR3;
3437	bool fPaePdpesAndCr3MappedR0;
3438
3439	/** What needs syncing (PGM_SYNC_*).
3440	* This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3441	* PGMFlushTLB, and PGMR3Load. */
3442	uint32_t fSyncFlags;
3443
3444	/** The shadow paging mode. */
3445	PGMMODE enmShadowMode;
3446	/** The guest paging mode. */
3447	PGMMODE enmGuestMode;
3448	/** The guest second level address translation mode. */
3449	PGMSLAT enmGuestSlatMode;
3450	/** Guest mode data table index (PGM_TYPE_XXX). */
3451	uint8_t volatile idxGuestModeData;
3452	/** Shadow mode data table index (PGM_TYPE_XXX). */
3453	uint8_t volatile idxShadowModeData;
3454	/** Both mode data table index (complicated). */
3455	uint8_t volatile idxBothModeData;
3456	/** Alignment padding. */
3457	uint8_t abPadding[1];
3458
3459	/** The guest CR3.
3460	* When SLAT is active, this is the translated physical address.
3461	* When SLAT is inactive, this is the physical address in CR3. */
3462	RTGCPHYS GCPhysCR3;
3463
3464	/** The nested-guest CR3.
3465	* When SLAT is active, this is CR3 prior to translation.
3466	* When SLAT is inactive, this is unused (and NIL_RTGCPHYS). */
3467	RTGCPHYS GCPhysNstGstCR3;
3468
3469	/** The cached guest CR3 when it has been mapped in PAE mode.
3470	* This allows us to skip remapping the CR3 and PAE PDPEs
3471	* (in PGMFlushTLB or similar) when it was already done as
3472	* part of MOV CRx instruction emulation.
3473	*/
3474	RTGCPHYS GCPhysPaeCR3;
3475
3476	/** @name 32-bit Guest Paging.
3477	* @{ */
3478	/** The guest's page directory, R3 pointer. */
3479	R3PTRTYPE(PX86PD) pGst32BitPdR3;
3480	/** The guest's page directory, R0 pointer. */
3481	R0PTRTYPE(PX86PD) pGst32BitPdR0;
3482	/** Mask containing the MBZ bits of a big page PDE. */
3483	uint32_t fGst32BitMbzBigPdeMask;
3484	/** Set if the page size extension (PSE) is enabled. */
3485	bool fGst32BitPageSizeExtension;
3486	/** Alignment padding. */
3487	bool afAlignment2[3];
3488	/** @} */
3489
3490	/** @name PAE Guest Paging.
3491	* @{ */
3492	/** The guest's page directory pointer table, R3 pointer. */
3493	R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3494	/** The guest's page directory pointer table, R0 pointer. */
3495	R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3496
3497	/** The guest's page directories, R3 pointers.
3498	* These are individual pointers and don't have to be adjacent.
3499	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3500	R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3501	/** The guest's page directories, R0 pointers.
3502	* Same restrictions as apGstPaePDsR3. */
3503	R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3504	/** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
3505	RTGCPHYS aGCPhysGstPaePDs[4];
3506	/** Mask containing the MBZ PTE bits. */
3507	uint64_t fGstPaeMbzPteMask;
3508	/** Mask containing the MBZ PDE bits. */
3509	uint64_t fGstPaeMbzPdeMask;
3510	/** Mask containing the MBZ big page PDE bits. */
3511	uint64_t fGstPaeMbzBigPdeMask;
3512	/** Mask containing the MBZ PDPE bits. */
3513	uint64_t fGstPaeMbzPdpeMask;
3514	/** @} */
3515
3516	/** @name AMD64 Guest Paging.
3517	* @{ */
3518	/** The guest's page directory pointer table, R3 pointer. */
3519	R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3520	/** The guest's page directory pointer table, R0 pointer. */
3521	R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3522	/** Mask containing the MBZ PTE bits. */
3523	uint64_t fGstAmd64MbzPteMask;
3524	/** Mask containing the MBZ PDE bits. */
3525	uint64_t fGstAmd64MbzPdeMask;
3526	/** Mask containing the MBZ big page PDE bits. */
3527	uint64_t fGstAmd64MbzBigPdeMask;
3528	/** Mask containing the MBZ PDPE bits. */
3529	uint64_t fGstAmd64MbzPdpeMask;
3530	/** Mask containing the MBZ big page PDPE bits. */
3531	uint64_t fGstAmd64MbzBigPdpeMask;
3532	/** Mask containing the MBZ PML4E bits. */
3533	uint64_t fGstAmd64MbzPml4eMask;
3534	/** Mask containing the PDPE bits that we shadow. */
3535	uint64_t fGstAmd64ShadowedPdpeMask;
3536	/** Mask containing the PML4E bits that we shadow. */
3537	uint64_t fGstAmd64ShadowedPml4eMask;
3538	/** @} */
3539
3540	/** @name PAE and AMD64 Guest Paging.
3541	* @{ */
3542	/** Mask containing the PTE bits that we shadow. */
3543	uint64_t fGst64ShadowedPteMask;
3544	/** Mask containing the PDE bits that we shadow. */
3545	uint64_t fGst64ShadowedPdeMask;
3546	/** Mask containing the big page PDE bits that we shadow in the PDE. */
3547	uint64_t fGst64ShadowedBigPdeMask;
3548	/** Mask containing the big page PDE bits that we shadow in the PTE. */
3549	uint64_t fGst64ShadowedBigPde4PteMask;
3550	/** @} */
3551
3552	/** @name EPT Guest Paging.
3553	* @{ */
3554	/** The guest's EPT PML4 table, R3 pointer. */
3555	R3PTRTYPE(PEPTPML4) pGstEptPml4R3;
3556	/** The guest's EPT PML4 table, R0 pointer. */
3557	R0PTRTYPE(PEPTPML4) pGstEptPml4R0;
3558	/** The guest's EPT pointer (copy of virtual VMCS). */
3559	uint64_t uEptPtr;
3560	/** Copy of the VM's IA32_VMX_EPT_VPID_CAP VPID MSR for faster access. Doesn't
3561	* change through the lifetime of the VM. */
3562	uint64_t uEptVpidCapMsr;
3563	/** Mask containing the MBZ PTE bits. */
3564	uint64_t fGstEptMbzPteMask;
3565	/** Mask containing the MBZ PDE bits. */
3566	uint64_t fGstEptMbzPdeMask;
3567	/** Mask containing the MBZ big page (2M) PDE bits. */
3568	uint64_t fGstEptMbzBigPdeMask;
3569	/** Mask containing the MBZ PDPTE bits. */
3570	uint64_t fGstEptMbzPdpteMask;
3571	/** Mask containing the MBZ big page (1G) PDPTE bits. */
3572	uint64_t fGstEptMbzBigPdpteMask;
3573	/** Mask containing the MBZ PML4E bits. */
3574	uint64_t fGstEptMbzPml4eMask;
3575	/** Mask to determine whether an entry is present. */
3576	uint64_t fGstEptPresentMask;
3577
3578	/** Mask containing the EPT PTE bits we shadow. */
3579	uint64_t fGstEptShadowedPteMask;
3580	/** Mask containing the EPT PDE bits we shadow. */
3581	uint64_t fGstEptShadowedPdeMask;
3582	/** Mask containing the EPT PDE (2M) bits we shadow. */
3583	uint64_t fGstEptShadowedBigPdeMask;
3584	/** Mask containing the EPT PDPTE bits we shadow. */
3585	uint64_t fGstEptShadowedPdpteMask;
3586	/** Mask containing the EPT PML4E bits we shadow. */
3587	uint64_t fGstEptShadowedPml4eMask;
3588	/** @} */
3589
3590	/** Pointer to the page of the current active CR3 - R3 Ptr. */
3591	R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3592	/** Pointer to the page of the current active CR3 - R0 Ptr. */
3593	R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3594
3595	/** For saving stack space, the disassembler state is allocated here instead of
3596	* on the stack. */
3597	DISSTATE Dis;
3598
3599	/** Counts the number of times the netware WP0+RO+US hack has been applied. */
3600	uint64_t cNetwareWp0Hacks;
3601
3602	/** Count the number of pgm pool access handler calls. */
3603	uint64_t cPoolAccessHandler;
3604
3605	/** @name Release Statistics
3606	* @{ */
3607	/** The number of times the guest has switched mode since last reset or statistics reset. */
3608	STAMCOUNTER cGuestModeChanges;
3609	/** The number of times the guest has switched mode since last reset or statistics reset. */
3610	STAMCOUNTER cA20Changes;
3611	/** @} */
3612
3613	#ifdef VBOX_WITH_STATISTICS
3614	/** These are statistics that used to be on the hyper heap. */
3615	PGMCPUSTATS Stats;
3616	#endif
3617	} PGMCPU;
3618	/** Pointer to the per-cpu PGM data. */
3619	typedef PGMCPU *PPGMCPU;
3620
3621
3622	/** @name PGM::fSyncFlags Flags
3623	* @note Was part of saved state a long time ago.
3624	* @{
3625	*/
3626	/* 0 used to be PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL */
3627	/** Always sync CR3. */
3628	#define PGM_SYNC_ALWAYS RT_BIT(1)
3629	/** Check guest mapping in SyncCR3. */
3630	#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3631	/** Clear the page pool (a light weight flush). */
3632	#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3633	#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3634	/** @} */
3635
3636
3637	#if defined(IN_RING0) \|\| defined(DOXYGEN_RUNNING)
3638
3639	/**
3640	* PGM GVMCPU instance data.
3641	*/
3642	typedef struct PGMR0PERVCPU
3643	{
3644	# ifdef VBOX_WITH_STATISTICS
3645	/** R0: Which statistic this \#PF should be attributed to. */
3646	R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3647	# endif
3648	uint64_t u64Dummy;
3649	} PGMR0PERVCPU;
3650
3651
3652	/**
3653	* PGM GVM instance data.
3654	*/
3655	typedef struct PGMR0PERVM
3656	{
3657	/** @name PGM Pool related stuff.
3658	* @{ */
3659	/** Critical section for serializing pool growth. */
3660	RTCRITSECT PoolGrowCritSect;
3661	/** The memory objects for the pool pages. */
3662	RTR0MEMOBJ ahPoolMemObjs[(PGMPOOL_IDX_LAST + PGMPOOL_CFG_MAX_GROW - 1) / PGMPOOL_CFG_MAX_GROW];
3663	/** The ring-3 mapping objects for the pool pages. */
3664	RTR0MEMOBJ ahPoolMapObjs[(PGMPOOL_IDX_LAST + PGMPOOL_CFG_MAX_GROW - 1) / PGMPOOL_CFG_MAX_GROW];
3665	/** @} */
3666
3667	/** Physical access handler types for ring-0.
3668	* Initialized to callback causing return to ring-3 and invalid enmKind. */
3669	PGMPHYSHANDLERTYPEINTR0 aPhysHandlerTypes[PGMPHYSHANDLERTYPE_COUNT];
3670	/** Physical handler allocator, ring-3 edition. */
3671	PGMPHYSHANDLERALLOCATOR PhysHandlerAllocator;
3672	/** The pointer to the ring-3 mapping of the physical access handler tree. */
3673	PPGMPHYSHANDLERTREE pPhysHandlerTree;
3674	/** The allocation object for the physical access handler tree. */
3675	RTR0MEMOBJ hPhysHandlerMemObj;
3676	/** The ring-3 mapping object for the physicall access handler tree. */
3677	RTR0MEMOBJ hPhysHandlerMapObj;
3678	} PGMR0PERVM;
3679
3680	#endif /* IN_RING0 \|\| DOXYGEN_RUNNING */
3681
3682	RT_C_DECLS_BEGIN
3683
3684	#if defined(VBOX_STRICT)
3685	int pgmLockDebug(PVMCC pVM, bool fVoid, RT_SRC_POS_DECL);
3686	# define PGM_LOCK_VOID(a_pVM) pgmLockDebug((a_pVM), true, RT_SRC_POS)
3687	# define PGM_LOCK(a_pVM) pgmLockDebug((a_pVM), false, RT_SRC_POS)
3688	#else
3689	int pgmLock(PVMCC pVM, bool fVoid);
3690	# define PGM_LOCK_VOID(a_pVM) pgmLock((a_pVM), true)
3691	# define PGM_LOCK(a_pVM) pgmLock((a_pVM), false)
3692	#endif
3693	void pgmUnlock(PVMCC pVM);
3694	# define PGM_UNLOCK(a_pVM) pgmUnlock((a_pVM))
3695	/**
3696	* Asserts that the caller owns the PDM lock.
3697	* This is the internal variant of PGMIsLockOwner.
3698	* @param a_pVM Pointer to the VM.
3699	*/
3700	#define PGM_LOCK_ASSERT_OWNER(a_pVM) Assert(PDMCritSectIsOwner((a_pVM), &(a_pVM)->pgm.s.CritSectX))
3701	/**
3702	* Asserts that the caller owns the PDM lock.
3703	* This is the internal variant of PGMIsLockOwner.
3704	* @param a_pVM Pointer to the VM.
3705	* @param a_pVCpu The current CPU handle.
3706	*/
3707	#define PGM_LOCK_ASSERT_OWNER_EX(a_pVM, a_pVCpu) Assert(PDMCritSectIsOwnerEx((a_pVCpu), &(a_pVM)->pgm.s.CritSectX))
3708
3709	uint32_t pgmHandlerPhysicalCalcTableSizes(uint32_t pcEntries, uint32_t pcbTreeAndBitmap);
3710	int pgmHandlerPhysicalExCreate(PVMCC pVM, PGMPHYSHANDLERTYPE hType, uint64_t uUser,
3711	R3PTRTYPE(const char ) pszDesc, PPGMPHYSHANDLER ppPhysHandler);
3712	int pgmHandlerPhysicalExDup(PVMCC pVM, PPGMPHYSHANDLER pPhysHandlerSrc, PPGMPHYSHANDLER *ppPhysHandler);
3713	int pgmHandlerPhysicalExRegister(PVMCC pVM, PPGMPHYSHANDLER pPhysHandler, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
3714	int pgmHandlerPhysicalExDeregister(PVMCC pVM, PPGMPHYSHANDLER pPhysHandler);
3715	int pgmHandlerPhysicalExDestroy(PVMCC pVM, PPGMPHYSHANDLER pHandler);
3716	void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3717	bool pgmHandlerPhysicalIsAll(PVMCC pVM, RTGCPHYS GCPhys);
3718	void pgmHandlerPhysicalResetAliasedPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, PPGMRAMRANGE pRam,
3719	bool fDoAccounting, bool fFlushIemTlbs);
3720	DECLHIDDEN(int) pgmHandlerPhysicalResetMmio2WithBitmap(PVMCC pVM, RTGCPHYS GCPhys, void *pvBitmap, uint32_t offBitmap);
3721	DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3722	DECLCALLBACK(FNPGMPHYSHANDLER) pgmR3HandlerPhysicalHandlerInvalid;
3723	#ifndef IN_RING3
3724	DECLCALLBACK(FNPGMPHYSHANDLER) pgmR0HandlerPhysicalHandlerToRing3;
3725	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) pgmR0HandlerPhysicalPfHandlerToRing3;
3726	#endif
3727
3728	int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3729
3730	int pgmPhysAllocPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3731	int pgmPhysAllocLargePage(PVMCC pVM, RTGCPHYS GCPhys);
3732	#ifdef IN_RING0
3733	int pgmR0PhysAllocateHandyPages(PGVM pGVM, VMCPUID idCpu, bool fRing3);
3734	int pgmR0PhysAllocateLargePage(PGVM pGVM, VMCPUID idCpu, RTGCPHYS GCPhys);
3735	#endif
3736	int pgmPhysRecheckLargePage(PVMCC pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
3737	int pgmPhysPageLoadIntoTlb(PVMCC pVM, RTGCPHYS GCPhys);
3738	int pgmPhysPageLoadIntoTlbWithPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3739	void pgmPhysPageMakeWriteMonitoredWritable(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3740	int pgmPhysPageMakeWritable(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3741	int pgmPhysPageMakeWritableAndMap(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3742	int pgmPhysPageMap(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3743	int pgmPhysPageMapReadOnly(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3744	int pgmPhysPageMapByPageID(PVMCC pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3745	int pgmPhysGCPhys2R3Ptr(PVMCC pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
3746	int pgmPhysCr3ToHCPtr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
3747	int pgmPhysGCPhys2CCPtrInternalDepr(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3748	int pgmPhysGCPhys2CCPtrInternal(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
3749	int pgmPhysGCPhys2CCPtrInternalReadOnly(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv, PPGMPAGEMAPLOCK pLock);
3750	void pgmPhysReleaseInternalPageMappingLock(PVMCC pVM, PPGMPAGEMAPLOCK pLock);
3751	DECLCALLBACK(FNPGMPHYSHANDLER) pgmPhysRomWriteHandler;
3752	DECLCALLBACK(FNPGMPHYSHANDLER) pgmPhysMmio2WriteHandler;
3753	#ifndef IN_RING3
3754	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) pgmPhysRomWritePfHandler;
3755	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) pgmPhysMmio2WritePfHandler;
3756	#endif
3757	int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys,
3758	PGMPAGETYPE enmNewType);
3759	void pgmPhysInvalidRamRangeTlbs(PVMCC pVM);
3760	void pgmPhysInvalidatePageMapTLB(PVMCC pVM);
3761	void pgmPhysInvalidatePageMapTLBEntry(PVMCC pVM, RTGCPHYS GCPhys);
3762	PPGMRAMRANGE pgmPhysGetRangeSlow(PVM pVM, RTGCPHYS GCPhys);
3763	PPGMRAMRANGE pgmPhysGetRangeAtOrAboveSlow(PVM pVM, RTGCPHYS GCPhys);
3764	PPGMPAGE pgmPhysGetPageSlow(PVM pVM, RTGCPHYS GCPhys);
3765	int pgmPhysGetPageExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage);
3766	int pgmPhysGetPageAndRangeExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam);
3767	#ifdef VBOX_WITH_NATIVE_NEM
3768	void pgmPhysSetNemStateForPages(PPGMPAGE paPages, RTGCPHYS cPages, uint8_t u2State);
3769	#endif
3770
3771	#ifdef IN_RING3
3772	void pgmR3PhysRelinkRamRanges(PVM pVM);
3773	int pgmR3PhysRamPreAllocate(PVM pVM);
3774	int pgmR3PhysRamReset(PVM pVM);
3775	int pgmR3PhysRomReset(PVM pVM);
3776	int pgmR3PhysRamZeroAll(PVM pVM);
3777	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3778	int pgmR3PhysRamTerm(PVM pVM);
3779	void pgmR3PhysRomTerm(PVM pVM);
3780	void pgmR3PhysAssertSharedPageChecksums(PVM pVM);
3781
3782	int pgmR3PoolInit(PVM pVM);
3783	void pgmR3PoolRelocate(PVM pVM);
3784	void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3785	void pgmR3PoolReset(PVM pVM);
3786	void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
3787	DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
3788	void pgmR3PoolWriteProtectPages(PVM pVM);
3789
3790	#endif /* IN_RING3 */
3791	#ifdef IN_RING0
3792	int pgmR0PoolInitVM(PGVM pGVM);
3793	#endif
3794	int pgmPoolAlloc(PVMCC pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
3795	uint16_t iUser, uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
3796	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3797	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3798	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
3799	void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3800	PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3801	PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
3802	int pgmPoolHCPhys2Ptr(PVM pVM, RTHCPHYS HCPhys, void **ppv);
3803	int pgmPoolSyncCR3(PVMCPUCC pVCpu);
3804	bool pgmPoolIsDirtyPageSlow(PVMCC pVM, RTGCPHYS GCPhys);
3805	void pgmPoolInvalidateDirtyPage(PVMCC pVM, RTGCPHYS GCPhysPT);
3806	int pgmPoolTrackUpdateGCPhys(PVMCC pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3807	void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
3808	uint16_t pgmPoolTrackPhysExtAddref(PVMCC pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
3809	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
3810	void pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3811	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3812	FNPGMPHYSHANDLER pgmPoolAccessHandler;
3813	#ifndef IN_RING3
3814	FNPGMRZPHYSPFHANDLER pgmRZPoolAccessPfHandler;
3815	#endif
3816
3817	void pgmPoolAddDirtyPage(PVMCC pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3818	void pgmPoolResetDirtyPages(PVMCC pVM);
3819	void pgmPoolResetDirtyPage(PVMCC pVM, RTGCPTR GCPtrPage);
3820
3821	/** Gets the ring-0 pointer for the given pool page. */
3822	DECLINLINE(R0PTRTYPE(PPGMPOOLPAGE)) pgmPoolConvertPageToR0(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3823	{
3824	#ifdef IN_RING3
3825	size_t offPage = (uintptr_t)pPage - (uintptr_t)pPool;
3826	# ifdef VBOX_STRICT
3827	size_t iPage = (offPage - RT_UOFFSETOF(PGMPOOL, aPages)) / sizeof(*pPage);
3828	AssertReturn(iPage < pPool->cMaxPages, NIL_RTR0PTR);
3829	AssertReturn(iPage * sizeof(*pPage) + RT_UOFFSETOF(PGMPOOL, aPages) == offPage, NIL_RTR0PTR);
3830	# endif
3831	return pPool->pPoolR0 + offPage;
3832	#else
3833	RT_NOREF(pPool);
3834	return pPage;
3835	#endif
3836	}
3837
3838	/** Gets the ring-3 pointer for the given pool page. */
3839	DECLINLINE(R3PTRTYPE(PPGMPOOLPAGE)) pgmPoolConvertPageToR3(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3840	{
3841	#ifdef IN_RING3
3842	RT_NOREF(pPool);
3843	return pPage;
3844	#else
3845	size_t offPage = (uintptr_t)pPage - (uintptr_t)pPool;
3846	# ifdef VBOX_STRICT
3847	size_t iPage = (offPage - RT_UOFFSETOF(PGMPOOL, aPages)) / sizeof(*pPage);
3848	AssertReturn(iPage < pPool->cMaxPages, NIL_RTR3PTR);
3849	AssertReturn(iPage * sizeof(*pPage) + RT_UOFFSETOF(PGMPOOL, aPages) == offPage, NIL_RTR3PTR);
3850	# endif
3851	return pPool->pPoolR3 + offPage;
3852	#endif
3853	}
3854
3855	int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu);
3856	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3857	void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu);
3858
3859	int pgmShwMakePageSupervisorAndWritable(PVMCPUCC pVCpu, RTGCPTR GCPtr, bool fBigPage, uint32_t fOpFlags);
3860	int pgmShwSyncPaePDPtr(PVMCPUCC pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
3861	int pgmShwSyncNestedPageLocked(PVMCPUCC pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
3862
3863	int pgmGstLazyMap32BitPD(PVMCPUCC pVCpu, PX86PD *ppPd);
3864	int pgmGstLazyMapPaePDPT(PVMCPUCC pVCpu, PX86PDPT *ppPdpt);
3865	int pgmGstLazyMapPaePD(PVMCPUCC pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
3866	int pgmGstLazyMapPml4(PVMCPUCC pVCpu, PX86PML4 *ppPml4);
3867	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
3868	int pgmGstLazyMapEptPml4(PVMCPUCC pVCpu, PEPTPML4 *ppPml4);
3869	#endif
3870	int pgmGstPtWalk(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk, PPGMPTWALKGST pGstWalk);
3871	int pgmGstPtWalkNext(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk, PPGMPTWALKGST pGstWalk);
3872
3873	# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64 && defined(IN_RING3)
3874	FNDBGCCMD pgmR3CmdCheckDuplicatePages;
3875	FNDBGCCMD pgmR3CmdShowSharedModules;
3876	# endif
3877
3878	void pgmLogState(PVM pVM);
3879
3880	RT_C_DECLS_END
3881
3882	/** @} */
3883
3884	#endif /* !VMM_INCLUDED_SRC_include_PGMInternal_h */
3885

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source: vbox/trunk/src/VBox/VMM/include/PGMInternal.h@ 100965

以其他格式下載: