PGMInternal.h@ 100964

最後變更在這個檔案從100964是 100964,由 vboxsync 提交於 19 月前
VMM/PGM: Some experiments wrt preseving ZERO page status as the (windows) guest zero's all memory prior to use. bugref:6385 bugref:10509
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1	/* $Id: PGMInternal.h 100964 2023-08-24 14:45:42Z vboxsync $ */
2	/** @file
3	* PGM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.alldomusa.eu.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_PGMInternal_h
29	#define VMM_INCLUDED_SRC_include_PGMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#include <VBox/cdefs.h>
35	#include <VBox/types.h>
36	#include <VBox/err.h>
37	#include <VBox/dbg.h>
38	#include <VBox/vmm/stam.h>
39	#include <VBox/param.h>
40	#include <VBox/vmm/vmm.h>
41	#include <VBox/vmm/mm.h>
42	#include <VBox/vmm/pdmcritsect.h>
43	#include <VBox/vmm/pdmapi.h>
44	#include <VBox/dis.h>
45	#include <VBox/vmm/dbgf.h>
46	#include <VBox/log.h>
47	#include <VBox/vmm/gmm.h>
48	#include <VBox/vmm/hm.h>
49	#include <iprt/asm.h>
50	#include <iprt/assert.h>
51	#include <iprt/avl.h>
52	#include <iprt/critsect.h>
53	#include <iprt/list-off32.h>
54	#include <iprt/sha.h>
55	#include <iprt/cpp/hardavlrange.h>
56
57
58
59	/** @defgroup grp_pgm_int Internals
60	* @ingroup grp_pgm
61	* @internal
62	* @{
63	*/
64
65
66	/** @name PGM Compile Time Config
67	* @{
68	*/
69
70	/**
71	* Check and skip global PDEs for non-global flushes
72	*/
73	#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
74
75	/**
76	* Optimization for PAE page tables that are modified often
77	*/
78	#ifndef VBOX_VMM_TARGET_ARMV8
79	# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
80	#endif
81
82	/**
83	* Large page support enabled only on 64 bits hosts; applies to nested paging only.
84	*/
85	#define PGM_WITH_LARGE_PAGES
86
87	/**
88	* Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
89	* VMX_EXIT_EPT_MISCONFIG.
90	*/
91	#define PGM_WITH_MMIO_OPTIMIZATIONS
92
93	/**
94	* Sync N pages instead of a whole page table
95	*/
96	#define PGM_SYNC_N_PAGES
97
98	/**
99	* Number of pages to sync during a page fault
100	*
101	* When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
102	* causes a lot of unnecessary extents and also is slower than taking more \#PFs.
103	*
104	* Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
105	* world switch overhead, so let's sync more.
106	*/
107	#ifdef IN_RING0
108	/* Chose 32 based on the compile test in @bugref{4219}; 64 shows worse stats.
109	* 32 again shows better results than 16; slightly more overhead in the \#PF handler,
110	* but ~5% fewer faults.
111	*/
112	# define PGM_SYNC_NR_PAGES 32
113	#else
114	# define PGM_SYNC_NR_PAGES 8
115	#endif
116
117	/**
118	* Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
119	*/
120	#define PGM_MAX_PHYSCACHE_ENTRIES 64
121	#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
122
123
124	/** @def PGMPOOL_CFG_MAX_GROW
125	* The maximum number of pages to add to the pool in one go.
126	*/
127	#define PGMPOOL_CFG_MAX_GROW (_2M >> GUEST_PAGE_SHIFT) /** @todo or HOST_PAGE_SHIFT ? */
128
129	/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
130	* Enables some extra assertions for virtual handlers (mainly phys2virt related).
131	*/
132	#ifdef VBOX_STRICT
133	# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
134	#endif
135
136	/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
137	* Enables the experimental lazy page allocation code.
138	* @todo Problems with zero page tracking, see @bugref{}. */
139	#if defined(DOXYGEN_RUNNING)
140	# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC
141	#endif
142
143	/** @def PGM_WITH_PAGE_ZEROING_DETECTION
144	* Enables the code for detecting guest zeroing page in the ZERO state and
145	* tries to avoid allocating them in response.
146	* This kind of relies upon VBOX_WITH_NEW_LAZY_PAGE_ALLOC to work atm. */
147	#if defined(DOXYGEN_RUNNING)
148	# define PGM_WITH_PAGE_ZEROING_DETECTION
149	#endif
150
151	/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
152	* Enables real write monitoring of pages, i.e. mapping them read-only and
153	* only making them writable when getting a write access \#PF. */
154	#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
155
156	/** @def VBOX_WITH_PGM_NEM_MODE
157	* Enabled the NEM memory management mode in PGM. See PGM::fNemMode for
158	* details. */
159	#ifdef DOXYGEN_RUNNING
160	# define VBOX_WITH_PGM_NEM_MODE
161	#endif
162
163	/** @} */
164
165
166	/** @name PDPT and PML4 flags.
167	* These are placed in the three bits available for system programs in
168	* the PDPT and PML4 entries.
169	* @{ */
170	/** The entry is a permanent one and it's must always be present.
171	* Never free such an entry. */
172	#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
173	/** PGM specific bits in PML4 entries. */
174	#define PGM_PML4_FLAGS 0
175	/** PGM specific bits in PDPT entries. */
176	#define PGM_PDPT_FLAGS (PGM_PLXFLAGS_PERMANENT)
177	/** @} */
178
179	/** @name Page directory flags.
180	* These are placed in the three bits available for system programs in
181	* the page directory entries.
182	* @{ */
183	/** Indicates the original entry was a big page.
184	* @remarks This is currently only used for statistics and can be recycled. */
185	#define PGM_PDFLAGS_BIG_PAGE RT_BIT_64(9)
186	/** Made read-only to facilitate dirty bit tracking. */
187	#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
188	/** @} */
189
190	/** @name Page flags.
191	* These are placed in the three bits available for system programs in
192	* the page entries.
193	* @{ */
194	/** Made read-only to facilitate dirty bit tracking. */
195	#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
196
197	#ifndef PGM_PTFLAGS_CSAM_VALIDATED
198	/** Scanned and approved by CSAM (tm).
199	* NOTE: Must be identical to the one defined in CSAMInternal.h!!
200	* @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/vmm/pgm.h. */
201	#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
202	#endif
203
204	/** @} */
205
206	/** @name Defines used to indicate the shadow and guest paging in the templates.
207	* @{ */
208	#define PGM_TYPE_REAL 1
209	#define PGM_TYPE_PROT 2
210	#define PGM_TYPE_32BIT 3
211	#define PGM_TYPE_PAE 4
212	#define PGM_TYPE_AMD64 5
213	#define PGM_TYPE_NESTED_32BIT 6
214	#define PGM_TYPE_NESTED_PAE 7
215	#define PGM_TYPE_NESTED_AMD64 8
216	#define PGM_TYPE_EPT 9
217	#define PGM_TYPE_NONE 10 /*< Dummy shadow paging mode for NEM. /
218	#define PGM_TYPE_END (PGM_TYPE_NONE + 1)
219	#define PGM_TYPE_FIRST_SHADOW PGM_TYPE_32BIT /*< The first type used by shadow paging. /
220	/** @} */
221
222	/** @name Defines used to indicate the second-level
223	* address translation (SLAT) modes in the templates.
224	* @{ */
225	#define PGM_SLAT_TYPE_DIRECT (PGM_TYPE_END + 1)
226	#define PGM_SLAT_TYPE_EPT (PGM_TYPE_END + 2)
227	#define PGM_SLAT_TYPE_32BIT (PGM_TYPE_END + 3)
228	#define PGM_SLAT_TYPE_PAE (PGM_TYPE_END + 4)
229	#define PGM_SLAT_TYPE_AMD64 (PGM_TYPE_END + 5)
230	/** @} */
231
232	/** Macro for checking if the guest is using paging.
233	* @param uGstType PGM_TYPE_*
234	* @param uShwType PGM_TYPE_*
235	* @remark ASSUMES certain order of the PGM_TYPE_* values.
236	*/
237	#define PGM_WITH_PAGING(uGstType, uShwType) \
238	( (uGstType) >= PGM_TYPE_32BIT \
239	&& (uShwType) < PGM_TYPE_NESTED_32BIT)
240
241	/** Macro for checking if the guest supports the NX bit.
242	* @param uGstType PGM_TYPE_*
243	* @param uShwType PGM_TYPE_*
244	* @remark ASSUMES certain order of the PGM_TYPE_* values.
245	*/
246	#define PGM_WITH_NX(uGstType, uShwType) \
247	( (uGstType) >= PGM_TYPE_PAE \
248	&& (uShwType) < PGM_TYPE_NESTED_32BIT)
249
250	/** Macro for checking for nested.
251	* @param uType PGM_TYPE_*
252	*/
253	#define PGM_TYPE_IS_NESTED(uType) \
254	( (uType) == PGM_TYPE_NESTED_32BIT \
255	\|\| (uType) == PGM_TYPE_NESTED_PAE \
256	\|\| (uType) == PGM_TYPE_NESTED_AMD64)
257
258	/** Macro for checking for nested or EPT.
259	* @param uType PGM_TYPE_*
260	*/
261	#define PGM_TYPE_IS_NESTED_OR_EPT(uType) \
262	( (uType) == PGM_TYPE_NESTED_32BIT \
263	\|\| (uType) == PGM_TYPE_NESTED_PAE \
264	\|\| (uType) == PGM_TYPE_NESTED_AMD64 \
265	\|\| (uType) == PGM_TYPE_EPT)
266
267
268
269	/** @def PGM_HCPHYS_2_PTR
270	* Maps a HC physical page pool address to a virtual address.
271	*
272	* @returns VBox status code.
273	* @param pVM The cross context VM structure.
274	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
275	* @param HCPhys The HC physical address to map to a virtual one.
276	* @param ppv Where to store the virtual address. No need to cast
277	* this.
278	*
279	* @remark There is no need to assert on the result.
280	*/
281	#define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) pgmPoolHCPhys2Ptr(pVM, HCPhys, (void **)(ppv))
282
283	/** @def PGM_GCPHYS_2_PTR_V2
284	* Maps a GC physical page address to a virtual address.
285	*
286	* @returns VBox status code.
287	* @param pVM The cross context VM structure.
288	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
289	* @param GCPhys The GC physical address to map to a virtual one.
290	* @param ppv Where to store the virtual address. No need to cast this.
291	*
292	* @remark Use with care as we don't have so much dynamic mapping space in
293	* ring-0 on 32-bit darwin and in RC.
294	* @remark There is no need to assert on the result.
295	*/
296	#define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
297	pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
298
299	/** @def PGM_GCPHYS_2_PTR
300	* Maps a GC physical page address to a virtual address.
301	*
302	* @returns VBox status code.
303	* @param pVM The cross context VM structure.
304	* @param GCPhys The GC physical address to map to a virtual one.
305	* @param ppv Where to store the virtual address. No need to cast this.
306	*
307	* @remark Use with care as we don't have so much dynamic mapping space in
308	* ring-0 on 32-bit darwin and in RC.
309	* @remark There is no need to assert on the result.
310	*/
311	#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
312
313	/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
314	* Maps a GC physical page address to a virtual address.
315	*
316	* @returns VBox status code.
317	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
318	* @param GCPhys The GC physical address to map to a virtual one.
319	* @param ppv Where to store the virtual address. No need to cast this.
320	*
321	* @remark Use with care as we don't have so much dynamic mapping space in
322	* ring-0 on 32-bit darwin and in RC.
323	* @remark There is no need to assert on the result.
324	*/
325	#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
326
327	/** @def PGM_GCPHYS_2_PTR_EX
328	* Maps a unaligned GC physical page address to a virtual address.
329	*
330	* @returns VBox status code.
331	* @param pVM The cross context VM structure.
332	* @param GCPhys The GC physical address to map to a virtual one.
333	* @param ppv Where to store the virtual address. No need to cast this.
334	*
335	* @remark Use with care as we don't have so much dynamic mapping space in
336	* ring-0 on 32-bit darwin and in RC.
337	* @remark There is no need to assert on the result.
338	*/
339	#define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
340	pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
341
342	/** @def PGM_DYNMAP_UNUSED_HINT
343	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
344	* is no longer used.
345	*
346	* For best effect only apply this to the page that was mapped most recently.
347	*
348	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
349	* @param pvPage The pool page.
350	*/
351	#define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
352
353	/** @def PGM_DYNMAP_UNUSED_HINT_VM
354	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
355	* is no longer used.
356	*
357	* For best effect only apply this to the page that was mapped most recently.
358	*
359	* @param pVM The cross context VM structure.
360	* @param pvPage The pool page.
361	*/
362	#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
363
364
365	/** @def PGM_INVL_PG
366	* Invalidates a page.
367	*
368	* @param pVCpu The cross context virtual CPU structure.
369	* @param GCVirt The virtual address of the page to invalidate.
370	*/
371	#ifdef IN_RING0
372	# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
373	#elif defined(IN_RING3)
374	# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
375	#else
376	# error "Not IN_RING0 or IN_RING3!"
377	#endif
378
379	/** @def PGM_INVL_PG_ALL_VCPU
380	* Invalidates a page on all VCPUs
381	*
382	* @param pVM The cross context VM structure.
383	* @param GCVirt The virtual address of the page to invalidate.
384	*/
385	#if defined(VBOX_VMM_TARGET_ARMV8)
386	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) do { } while(0)
387	#else
388	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
389	#endif
390
391	/** @def PGM_INVL_BIG_PG
392	* Invalidates a 4MB page directory entry.
393	*
394	* @param pVCpu The cross context virtual CPU structure.
395	* @param GCVirt The virtual address within the page directory to invalidate.
396	*/
397	#if defined(VBOX_VMM_TARGET_ARMV8)
398	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) do { } while(0)
399	#else
400	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTlb(pVCpu)
401	#endif
402
403	/** @def PGM_INVL_VCPU_TLBS()
404	* Invalidates the TLBs of the specified VCPU
405	*
406	* @param pVCpu The cross context virtual CPU structure.
407	*/
408	#if defined(VBOX_VMM_TARGET_ARMV8)
409	# define PGM_INVL_VCPU_TLBS(pVCpu) do { } while(0)
410	#else
411	# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTlb(pVCpu)
412	#endif
413
414	/** @def PGM_INVL_ALL_VCPU_TLBS()
415	* Invalidates the TLBs of all VCPUs
416	*
417	* @param pVM The cross context VM structure.
418	*/
419	#if defined(VBOX_VMM_TARGET_ARMV8)
420	# define PGM_INVL_ALL_VCPU_TLBS(pVM) do { } while(0)
421	#else
422	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTlbOnAllVCpus(pVM)
423	#endif
424
425
426	/** @name Safer Shadow PAE PT/PTE
427	* For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
428	* present.
429	*
430	* @{
431	*/
432	#if 1
433	/**
434	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
435	* invalid entries for present.
436	* @sa X86PTEPAE.
437	*/
438	typedef union PGMSHWPTEPAE
439	{
440	/** Unsigned integer view */
441	X86PGPAEUINT uCareful;
442	/* Not other views. */
443	} PGMSHWPTEPAE;
444
445	# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
446	# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
447	# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
448	# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
449	# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
450	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
451	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_RW \| X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P \| X86_PTE_RW) )
452	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
453	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
454	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /*< Use with care. /
455	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
456	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
457	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
458	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
459	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
460	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful \|= X86_PTE_RW; } while (0)
461
462	/**
463	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
464	* invalid entries for present.
465	* @sa X86PTPAE.
466	*/
467	typedef struct PGMSHWPTPAE
468	{
469	PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
470	} PGMSHWPTPAE;
471
472	#else
473	typedef X86PTEPAE PGMSHWPTEPAE;
474	typedef X86PTPAE PGMSHWPTPAE;
475	# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
476	# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
477	# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
478	# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
479	# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
480	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
481	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P \| X86_PTE_RW)) == (X86_PTE_P \| X86_PTE_RW) )
482	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
483	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
484	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /*< Use with care. /
485	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
486	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
487	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
488	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
489	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
490	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u \|= X86_PTE_RW; } while (0)
491
492	#endif
493
494	/** Pointer to a shadow PAE PTE. */
495	typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
496	/** Pointer to a const shadow PAE PTE. */
497	typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
498
499	/** Pointer to a shadow PAE page table. */
500	typedef PGMSHWPTPAE *PPGMSHWPTPAE;
501	/** Pointer to a const shadow PAE page table. */
502	typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
503	/** @} */
504
505
506	/** The physical access handler type handle count (power of two). */
507	#define PGMPHYSHANDLERTYPE_COUNT 0x20
508	/** Mask for getting the array index from an access handler type handle.
509	* The other handle bits are random and non-zero to avoid mixups due to zero
510	* initialized fields. */
511	#define PGMPHYSHANDLERTYPE_IDX_MASK 0x1f
512
513	/**
514	* Physical page access handler type registration, ring-0 part.
515	*/
516	typedef struct PGMPHYSHANDLERTYPEINTR0
517	{
518	/** The handle value for verfication. */
519	PGMPHYSHANDLERTYPE hType;
520	/** The kind of accesses we're handling. */
521	PGMPHYSHANDLERKIND enmKind;
522	/** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
523	uint8_t uState;
524	/** Whether to keep the PGM lock when calling the handler.
525	* @sa PGMPHYSHANDLER_F_KEEP_PGM_LOCK */
526	bool fKeepPgmLock;
527	/** Set if this is registered by a device instance and uUser should be
528	* translated from a device instance ID to a pointer.
529	* @sa PGMPHYSHANDLER_F_R0_DEVINS_IDX */
530	bool fRing0DevInsIdx;
531	/** See PGMPHYSHANDLER_F_NOT_IN_HM. */
532	bool fNotInHm : 1;
533	/** Pointer to the ring-0 callback function. */
534	R0PTRTYPE(PFNPGMPHYSHANDLER) pfnHandler;
535	/** Pointer to the ring-0 callback function for \#PFs, can be NULL. */
536	R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandler;
537	/** Description / Name. For easing debugging. */
538	R0PTRTYPE(const char *) pszDesc;
539	} PGMPHYSHANDLERTYPEINTR0;
540	/** Pointer to a physical access handler type registration. */
541	typedef PGMPHYSHANDLERTYPEINTR0 *PPGMPHYSHANDLERTYPEINTR0;
542
543	/**
544	* Physical page access handler type registration, shared/ring-3 part.
545	*/
546	typedef struct PGMPHYSHANDLERTYPEINTR3
547	{
548	/** The handle value for verfication. */
549	PGMPHYSHANDLERTYPE hType;
550	/** The kind of accesses we're handling. */
551	PGMPHYSHANDLERKIND enmKind;
552	/** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
553	uint8_t uState;
554	/** Whether to keep the PGM lock when calling the handler.
555	* @sa PGMPHYSHANDLER_F_KEEP_PGM_LOCK */
556	bool fKeepPgmLock;
557	/** Set if this is registered by a device instance and uUser should be
558	* translated from a device instance ID to a pointer.
559	* @sa PGMPHYSHANDLER_F_R0_DEVINS_IDX */
560	bool fRing0DevInsIdx;
561	/** Set by ring-0 if the handler is ring-0 enabled (for debug). */
562	bool fRing0Enabled : 1;
563	/** See PGMPHYSHANDLER_F_NOT_IN_HM. */
564	bool fNotInHm : 1;
565	/** Pointer to the ring-3 callback function. */
566	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandler;
567	/** Description / Name. For easing debugging. */
568	R3PTRTYPE(const char *) pszDesc;
569	} PGMPHYSHANDLERTYPEINTR3;
570	/** Pointer to a physical access handler type registration. */
571	typedef PGMPHYSHANDLERTYPEINTR3 *PPGMPHYSHANDLERTYPEINTR3;
572
573	/** Pointer to a physical access handler type record for the current context. */
574	typedef CTX_SUFF(PPGMPHYSHANDLERTYPEINT) PPGMPHYSHANDLERTYPEINT;
575	/** Pointer to a const physical access handler type record for the current context. */
576	typedef CTX_SUFF(PGMPHYSHANDLERTYPEINT) const *PCPGMPHYSHANDLERTYPEINT;
577	/** Dummy physical access handler type record. */
578	extern CTX_SUFF(PGMPHYSHANDLERTYPEINT) const g_pgmHandlerPhysicalDummyType;
579
580
581	/**
582	* Physical page access handler structure.
583	*
584	* This is used to keep track of physical address ranges
585	* which are being monitored in some kind of way.
586	*/
587	typedef struct PGMPHYSHANDLER
588	{
589	/** @name Tree stuff.
590	* @{ */
591	/** First address. */
592	RTGCPHYS Key;
593	/** Last address. */
594	RTGCPHYS KeyLast;
595	uint32_t idxLeft;
596	uint32_t idxRight;
597	uint8_t cHeight;
598	/** @} */
599	uint8_t abPadding[3];
600	/** Number of pages to update. */
601	uint32_t cPages;
602	/** Set if we have pages that have been aliased. */
603	uint32_t cAliasedPages;
604	/** Set if we have pages that have temporarily been disabled. */
605	uint32_t cTmpOffPages;
606	/** Registered handler type handle.
607	* @note Marked volatile to prevent re-reading after validation. */
608	PGMPHYSHANDLERTYPE volatile hType;
609	/** User argument for the handlers. */
610	uint64_t uUser;
611	/** Description / Name. For easing debugging. */
612	R3PTRTYPE(const char *) pszDesc;
613	/** Profiling of this handler.
614	* @note VBOX_WITH_STATISTICS only, but included to keep structure stable. */
615	STAMPROFILE Stat;
616	} PGMPHYSHANDLER;
617	AssertCompileSize(PGMPHYSHANDLER, 12*8);
618	/** Pointer to a physical page access handler structure. */
619	typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
620
621	/**
622	* Gets the type record for a physical handler (no reference added).
623	* @returns PCPGMPHYSHANDLERTYPEINT, can be NULL
624	* @param a_pVM The cross context VM structure.
625	* @param a_pPhysHandler Pointer to the physical handler structure
626	* (PGMPHYSHANDLER).
627	*/
628	#define PGMPHYSHANDLER_GET_TYPE(a_pVM, a_pPhysHandler) \
629	pgmHandlerPhysicalTypeHandleToPtr(a_pVM, (a_pPhysHandler) ? (a_pPhysHandler)->hType : NIL_PGMPHYSHANDLERTYPE)
630
631	/**
632	* Gets the type record for a physical handler, never returns NULL.
633	*
634	* @returns PCPGMPHYSHANDLERTYPEINT, never NULL.
635	* @param a_pVM The cross context VM structure.
636	* @param a_pPhysHandler Pointer to the physical handler structure
637	* (PGMPHYSHANDLER).
638	*/
639	#define PGMPHYSHANDLER_GET_TYPE_NO_NULL(a_pVM, a_pPhysHandler) \
640	pgmHandlerPhysicalTypeHandleToPtr2(a_pVM, (a_pPhysHandler) ? (a_pPhysHandler)->hType : NIL_PGMPHYSHANDLERTYPE)
641
642	/** Physical access handler allocator. */
643	typedef RTCHardAvlTreeSlabAllocator<PGMPHYSHANDLER> PGMPHYSHANDLERALLOCATOR;
644
645	/** Physical access handler tree. */
646	typedef RTCHardAvlRangeTree<PGMPHYSHANDLER, RTGCPHYS> PGMPHYSHANDLERTREE;
647	/** Pointer to a physical access handler tree. */
648	typedef PGMPHYSHANDLERTREE *PPGMPHYSHANDLERTREE;
649
650
651	/**
652	* A Physical Guest Page tracking structure.
653	*
654	* The format of this structure is complicated because we have to fit a lot
655	* of information into as few bits as possible. The format is also subject
656	* to change (there is one coming up soon). Which means that for we'll be
657	* using PGM_PAGE_GET_, PGM_PAGE_IS_ and PGM_PAGE_SET_ macros for all
658	* accesses to the structure.
659	*/
660	typedef union PGMPAGE
661	{
662	/** Structured view. */
663	struct
664	{
665	/** 1:0 - The physical handler state (PGM_PAGE_HNDL_PHYS_STATE_). /
666	uint64_t u2HandlerPhysStateY : 2;
667	/** 2 - Don't apply the physical handler in HM mode (nested APIC hack). */
668	uint64_t fHandlerPhysNotInHm : 1;
669	/** 3 - Flag indicating that a write monitored page was written to
670	* when set. */
671	uint64_t fWrittenToY : 1;
672	/** 7:4 - Unused. */
673	uint64_t u2Unused0 : 4;
674	/** 9:8 - Paging structure needed to map the page
675	* (PGM_PAGE_PDE_TYPE_). /
676	uint64_t u2PDETypeY : 2;
677	/** 11:10 - NEM state bits. */
678	uint64_t u2NemStateY : 2;
679	/** 12:48 - The host physical frame number (shift left to get the
680	* address). */
681	uint64_t HCPhysFN : 36;
682	/** 50:48 - The page state. */
683	uint64_t uStateY : 3;
684	/** 51:53 - The page type (PGMPAGETYPE). */
685	uint64_t uTypeY : 3;
686	/** 63:54 - PTE index for usage tracking (page pool). */
687	uint64_t u10PteIdx : 10;
688
689	/** The GMM page ID.
690	* @remarks In the current implementation, MMIO2 and pages aliased to
691	* MMIO2 pages will be exploiting this field to calculate the
692	* ring-3 mapping address corresponding to the page.
693	* Later we may consider including MMIO2 management into GMM. */
694	uint32_t idPage;
695	/** Usage tracking (page pool). */
696	uint16_t u16TrackingY;
697	/** The number of read locks on this page. */
698	uint8_t cReadLocksY;
699	/** The number of write locks on this page. */
700	uint8_t cWriteLocksY;
701	} s;
702
703	/** 64-bit integer view. */
704	uint64_t au64[2];
705	/** 16-bit view. */
706	uint32_t au32[4];
707	/** 16-bit view. */
708	uint16_t au16[8];
709	/** 8-bit view. */
710	uint8_t au8[16];
711	} PGMPAGE;
712	AssertCompileSize(PGMPAGE, 16);
713	/** Pointer to a physical guest page. */
714	typedef PGMPAGE *PPGMPAGE;
715	/** Pointer to a const physical guest page. */
716	typedef const PGMPAGE *PCPGMPAGE;
717	/** Pointer to a physical guest page pointer. */
718	typedef PPGMPAGE *PPPGMPAGE;
719
720
721	/**
722	* Clears the page structure.
723	* @param a_pPage Pointer to the physical guest page tracking structure.
724	*/
725	#define PGM_PAGE_CLEAR(a_pPage) \
726	do { \
727	(a_pPage)->au64[0] = 0; \
728	(a_pPage)->au64[1] = 0; \
729	} while (0)
730
731	/**
732	* Initializes the page structure.
733	* @param a_pPage Pointer to the physical guest page tracking structure.
734	* @param a_HCPhys The host physical address of the page.
735	* @param a_idPage The (GMM) page ID of the page.
736	* @param a_uType The page type (PGMPAGETYPE).
737	* @param a_uState The page state (PGM_PAGE_STATE_XXX).
738	*/
739	#define PGM_PAGE_INIT(a_pPage, a_HCPhys, a_idPage, a_uType, a_uState) \
740	do { \
741	RTHCPHYS SetHCPhysTmp = (a_HCPhys); \
742	AssertFatalMsg(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000)), ("%RHp\n", SetHCPhysTmp)); \
743	(a_pPage)->au64[0] = SetHCPhysTmp; \
744	(a_pPage)->au64[1] = 0; \
745	(a_pPage)->s.idPage = (a_idPage); \
746	(a_pPage)->s.uStateY = (a_uState); \
747	(a_pPage)->s.uTypeY = (a_uType); \
748	} while (0)
749
750	/**
751	* Initializes the page structure of a ZERO page.
752	* @param a_pPage Pointer to the physical guest page tracking structure.
753	* @param a_pVM The VM handle (for getting the zero page address).
754	* @param a_uType The page type (PGMPAGETYPE).
755	*/
756	#define PGM_PAGE_INIT_ZERO(a_pPage, a_pVM, a_uType) \
757	PGM_PAGE_INIT((a_pPage), (a_pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (a_uType), PGM_PAGE_STATE_ZERO)
758
759
760	/** @name The Page state, PGMPAGE::uStateY.
761	* @{ */
762	/** The zero page.
763	* This is a per-VM page that's never ever mapped writable. */
764	#define PGM_PAGE_STATE_ZERO 0U
765	/** A allocated page.
766	* This is a per-VM page allocated from the page pool (or wherever
767	* we get MMIO2 pages from if the type is MMIO2).
768	*/
769	#define PGM_PAGE_STATE_ALLOCATED 1U
770	/** A allocated page that's being monitored for writes.
771	* The shadow page table mappings are read-only. When a write occurs, the
772	* fWrittenTo member is set, the page remapped as read-write and the state
773	* moved back to allocated. */
774	#define PGM_PAGE_STATE_WRITE_MONITORED 2U
775	/** The page is shared, aka. copy-on-write.
776	* This is a page that's shared with other VMs. */
777	#define PGM_PAGE_STATE_SHARED 3U
778	/** The page is ballooned, so no longer available for this VM. */
779	#define PGM_PAGE_STATE_BALLOONED 4U
780	/** @} */
781
782
783	/** Asserts lock ownership in some of the PGM_PAGE_XXX macros. */
784	#if defined(VBOX_STRICT) && 0 /** @todo triggers in pgmRZDynMapGCPageV2Inlined */
785	# define PGM_PAGE_ASSERT_LOCK(a_pVM) PGM_LOCK_ASSERT_OWNER(a_pVM)
786	#else
787	# define PGM_PAGE_ASSERT_LOCK(a_pVM) do { } while (0)
788	#endif
789
790	/**
791	* Gets the page state.
792	* @returns page state (PGM_PAGE_STATE_*).
793	* @param a_pPage Pointer to the physical guest page tracking structure.
794	*
795	* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
796	* builds.
797	*/
798	#define PGM_PAGE_GET_STATE_NA(a_pPage) ( (a_pPage)->s.uStateY )
799	#if defined(__GNUC__) && defined(VBOX_STRICT)
800	# define PGM_PAGE_GET_STATE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_STATE_NA(a_pPage); })
801	#else
802	# define PGM_PAGE_GET_STATE PGM_PAGE_GET_STATE_NA
803	#endif
804
805	/**
806	* Sets the page state.
807	* @param a_pVM The VM handle, only used for lock ownership assertions.
808	* @param a_pPage Pointer to the physical guest page tracking structure.
809	* @param a_uState The new page state.
810	*/
811	#define PGM_PAGE_SET_STATE(a_pVM, a_pPage, a_uState) \
812	do { (a_pPage)->s.uStateY = (a_uState); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
813
814
815	/**
816	* Gets the host physical address of the guest page.
817	* @returns host physical address (RTHCPHYS).
818	* @param a_pPage Pointer to the physical guest page tracking structure.
819	*
820	* @remarks In strict builds on gcc platforms, this macro will make some ugly
821	* assumption about a valid pVM variable/parameter being in the
822	* current context. It will use this pVM variable to assert that the
823	* PGM lock is held. Use the PGM_PAGE_GET_HCPHYS_NA in contexts where
824	* pVM is not around.
825	*/
826	#if 0
827	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->s.HCPhysFN << 12 )
828	# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
829	#else
830	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->au64[0] & UINT64_C(0x0000fffffffff000) )
831	# if defined(__GNUC__) && defined(VBOX_STRICT)
832	# define PGM_PAGE_GET_HCPHYS(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_HCPHYS_NA(a_pPage); })
833	# else
834	# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
835	# endif
836	#endif
837
838	/**
839	* Sets the host physical address of the guest page.
840	*
841	* @param a_pVM The VM handle, only used for lock ownership assertions.
842	* @param a_pPage Pointer to the physical guest page tracking structure.
843	* @param a_HCPhys The new host physical address.
844	*/
845	#define PGM_PAGE_SET_HCPHYS(a_pVM, a_pPage, a_HCPhys) \
846	do { \
847	RTHCPHYS const SetHCPhysTmp = (a_HCPhys); \
848	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
849	(a_pPage)->s.HCPhysFN = SetHCPhysTmp >> 12; \
850	PGM_PAGE_ASSERT_LOCK(a_pVM); \
851	} while (0)
852
853	/**
854	* Get the Page ID.
855	* @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
856	* @param a_pPage Pointer to the physical guest page tracking structure.
857	*/
858	#define PGM_PAGE_GET_PAGEID(a_pPage) ( (uint32_t)(a_pPage)->s.idPage )
859
860	/**
861	* Sets the Page ID.
862	* @param a_pVM The VM handle, only used for lock ownership assertions.
863	* @param a_pPage Pointer to the physical guest page tracking structure.
864	* @param a_idPage The new page ID.
865	*/
866	#define PGM_PAGE_SET_PAGEID(a_pVM, a_pPage, a_idPage) \
867	do { \
868	(a_pPage)->s.idPage = (a_idPage); \
869	PGM_PAGE_ASSERT_LOCK(a_pVM); \
870	} while (0)
871
872	/**
873	* Get the Chunk ID.
874	* @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
875	* @param a_pPage Pointer to the physical guest page tracking structure.
876	*/
877	#define PGM_PAGE_GET_CHUNKID(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) >> GMM_CHUNKID_SHIFT )
878
879	/**
880	* Get the index of the page within the allocation chunk.
881	* @returns The page index.
882	* @param a_pPage Pointer to the physical guest page tracking structure.
883	*/
884	#define PGM_PAGE_GET_PAGE_IN_CHUNK(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) & GMM_PAGEID_IDX_MASK )
885
886	/**
887	* Gets the page type.
888	* @returns The page type.
889	* @param a_pPage Pointer to the physical guest page tracking structure.
890	*
891	* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
892	* builds.
893	*/
894	#define PGM_PAGE_GET_TYPE_NA(a_pPage) ( (a_pPage)->s.uTypeY )
895	#if defined(__GNUC__) && defined(VBOX_STRICT)
896	# define PGM_PAGE_GET_TYPE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TYPE_NA(a_pPage); })
897	#else
898	# define PGM_PAGE_GET_TYPE PGM_PAGE_GET_TYPE_NA
899	#endif
900
901	/**
902	* Sets the page type.
903	*
904	* @param a_pVM The VM handle, only used for lock ownership assertions.
905	* @param a_pPage Pointer to the physical guest page tracking structure.
906	* @param a_enmType The new page type (PGMPAGETYPE).
907	*/
908	#define PGM_PAGE_SET_TYPE(a_pVM, a_pPage, a_enmType) \
909	do { (a_pPage)->s.uTypeY = (a_enmType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
910
911	/**
912	* Gets the page table index
913	* @returns The page table index.
914	* @param a_pPage Pointer to the physical guest page tracking structure.
915	*/
916	#define PGM_PAGE_GET_PTE_INDEX(a_pPage) ( (a_pPage)->s.u10PteIdx )
917
918	/**
919	* Sets the page table index.
920	* @param a_pVM The VM handle, only used for lock ownership assertions.
921	* @param a_pPage Pointer to the physical guest page tracking structure.
922	* @param a_iPte New page table index.
923	*/
924	#define PGM_PAGE_SET_PTE_INDEX(a_pVM, a_pPage, a_iPte) \
925	do { (a_pPage)->s.u10PteIdx = (a_iPte); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
926
927	/**
928	* Checks if the page is marked for MMIO, no MMIO2 aliasing.
929	* @returns true/false.
930	* @param a_pPage Pointer to the physical guest page tracking structure.
931	*/
932	#define PGM_PAGE_IS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO )
933
934	/**
935	* Checks if the page is marked for MMIO, including both aliases.
936	* @returns true/false.
937	* @param a_pPage Pointer to the physical guest page tracking structure.
938	*/
939	#define PGM_PAGE_IS_MMIO_OR_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
940	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO2_ALIAS_MMIO \
941	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO \
942	)
943
944	/**
945	* Checks if the page is marked for MMIO, including special aliases.
946	* @returns true/false.
947	* @param a_pPage Pointer to the physical guest page tracking structure.
948	*/
949	#define PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
950	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
951
952	/**
953	* Checks if the page is a special aliased MMIO page.
954	* @returns true/false.
955	* @param a_pPage Pointer to the physical guest page tracking structure.
956	*/
957	#define PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
958
959	/**
960	* Checks if the page is backed by the ZERO page.
961	* @returns true/false.
962	* @param a_pPage Pointer to the physical guest page tracking structure.
963	*/
964	#define PGM_PAGE_IS_ZERO(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ZERO )
965
966	/**
967	* Checks if the page is backed by a SHARED page.
968	* @returns true/false.
969	* @param a_pPage Pointer to the physical guest page tracking structure.
970	*/
971	#define PGM_PAGE_IS_SHARED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_SHARED )
972
973	/**
974	* Checks if the page is ballooned.
975	* @returns true/false.
976	* @param a_pPage Pointer to the physical guest page tracking structure.
977	*/
978	#define PGM_PAGE_IS_BALLOONED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_BALLOONED )
979
980	/**
981	* Checks if the page is allocated.
982	* @returns true/false.
983	* @param a_pPage Pointer to the physical guest page tracking structure.
984	*/
985	#define PGM_PAGE_IS_ALLOCATED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ALLOCATED )
986
987	/**
988	* Marks the page as written to (for GMM change monitoring).
989	* @param a_pVM The VM handle, only used for lock ownership assertions.
990	* @param a_pPage Pointer to the physical guest page tracking structure.
991	*/
992	#define PGM_PAGE_SET_WRITTEN_TO(a_pVM, a_pPage) \
993	do { (a_pPage)->s.fWrittenToY = 1; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
994
995	/**
996	* Clears the written-to indicator.
997	* @param a_pVM The VM handle, only used for lock ownership assertions.
998	* @param a_pPage Pointer to the physical guest page tracking structure.
999	*/
1000	#define PGM_PAGE_CLEAR_WRITTEN_TO(a_pVM, a_pPage) \
1001	do { (a_pPage)->s.fWrittenToY = 0; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1002
1003	/**
1004	* Checks if the page was marked as written-to.
1005	* @returns true/false.
1006	* @param a_pPage Pointer to the physical guest page tracking structure.
1007	*/
1008	#define PGM_PAGE_IS_WRITTEN_TO(a_pPage) ( (a_pPage)->s.fWrittenToY )
1009
1010
1011	/** @name PT usage values (PGMPAGE::u2PDEType).
1012	*
1013	* @{ */
1014	/** Either as a PT or PDE. */
1015	#define PGM_PAGE_PDE_TYPE_DONTCARE 0
1016	/** Must use a page table to map the range. */
1017	#define PGM_PAGE_PDE_TYPE_PT 1
1018	/** Can use a page directory entry to map the continuous range. */
1019	#define PGM_PAGE_PDE_TYPE_PDE 2
1020	/** Can use a page directory entry to map the continuous range - temporarily disabled (by page monitoring). */
1021	#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
1022	/** @} */
1023
1024	/**
1025	* Set the PDE type of the page
1026	* @param a_pVM The VM handle, only used for lock ownership assertions.
1027	* @param a_pPage Pointer to the physical guest page tracking structure.
1028	* @param a_uType PGM_PAGE_PDE_TYPE_*.
1029	*/
1030	#define PGM_PAGE_SET_PDE_TYPE(a_pVM, a_pPage, a_uType) \
1031	do { (a_pPage)->s.u2PDETypeY = (a_uType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1032
1033	/**
1034	* Checks if the page was marked being part of a large page
1035	* @returns true/false.
1036	* @param a_pPage Pointer to the physical guest page tracking structure.
1037	*/
1038	#define PGM_PAGE_GET_PDE_TYPE(a_pPage) ( (a_pPage)->s.u2PDETypeY )
1039
1040	/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
1041	*
1042	* @remarks The values are assigned in order of priority, so we can calculate
1043	* the correct state for a page with different handlers installed.
1044	* @{ */
1045	/** No handler installed. */
1046	#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
1047	/** Monitoring is temporarily disabled. */
1048	#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
1049	/** Write access is monitored. */
1050	#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
1051	/** All access is monitored. */
1052	#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
1053	/** @} */
1054
1055	/**
1056	* Gets the physical access handler state of a page.
1057	* @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
1058	* @param a_pPage Pointer to the physical guest page tracking structure.
1059	*/
1060	#define PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) ( (a_pPage)->s.u2HandlerPhysStateY )
1061
1062	/**
1063	* Sets the physical access handler state of a page.
1064	* @param a_pPage Pointer to the physical guest page tracking structure.
1065	* @param a_uState The new state value.
1066	* @param a_fNotInHm The PGMPHYSHANDLER_F_NOT_HM bit.
1067	*/
1068	#define PGM_PAGE_SET_HNDL_PHYS_STATE(a_pPage, a_uState, a_fNotInHm) \
1069	do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); (a_pPage)->s.fHandlerPhysNotInHm = (a_fNotInHm); } while (0)
1070
1071	/**
1072	* Sets the physical access handler state of a page.
1073	* @param a_pPage Pointer to the physical guest page tracking structure.
1074	* @param a_uState The new state value.
1075	*/
1076	#define PGM_PAGE_SET_HNDL_PHYS_STATE_ONLY(a_pPage, a_uState) \
1077	do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); } while (0)
1078
1079	/**
1080	* Checks if the page has any physical access handlers, including temporarily disabled ones.
1081	* @returns true/false
1082	* @param a_pPage Pointer to the physical guest page tracking structure.
1083	*/
1084	#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(a_pPage) \
1085	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1086
1087	/**
1088	* Checks if the page has any active physical access handlers.
1089	* @returns true/false
1090	* @param a_pPage Pointer to the physical guest page tracking structure.
1091	*/
1092	#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(a_pPage) \
1093	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1094
1095	/**
1096	* Checks if the page has any access handlers, including temporarily disabled ones.
1097	* @returns true/false
1098	* @param a_pPage Pointer to the physical guest page tracking structure.
1099	*/
1100	#define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1101	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1102
1103	/**
1104	* Checks if the page has any active access handlers.
1105	* @returns true/false
1106	* @param a_pPage Pointer to the physical guest page tracking structure.
1107	*/
1108	#define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1109	(PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1110
1111	/**
1112	* Checks if the page has any active access handlers catching all accesses.
1113	* @returns true/false
1114	* @param a_pPage Pointer to the physical guest page tracking structure.
1115	*/
1116	#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1117	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1118
1119	/** @def PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM
1120	* Checks if the physical handlers of the page should be ignored in shadow page
1121	* tables and such.
1122	* @returns true/false
1123	* @param a_pPage Pointer to the physical guest page tracking structure.
1124	*/
1125	#define PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(a_pPage) ((a_pPage)->s.fHandlerPhysNotInHm)
1126
1127	/** @def PGM_PAGE_GET_TRACKING
1128	* Gets the packed shadow page pool tracking data associated with a guest page.
1129	* @returns uint16_t containing the data.
1130	* @param a_pPage Pointer to the physical guest page tracking structure.
1131	*/
1132	#define PGM_PAGE_GET_TRACKING_NA(a_pPage) ( (a_pPage)->s.u16TrackingY )
1133	#if defined(__GNUC__) && defined(VBOX_STRICT)
1134	# define PGM_PAGE_GET_TRACKING(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TRACKING_NA(a_pPage); })
1135	#else
1136	# define PGM_PAGE_GET_TRACKING PGM_PAGE_GET_TRACKING_NA
1137	#endif
1138
1139	/** @def PGM_PAGE_SET_TRACKING
1140	* Sets the packed shadow page pool tracking data associated with a guest page.
1141	* @param a_pVM The VM handle, only used for lock ownership assertions.
1142	* @param a_pPage Pointer to the physical guest page tracking structure.
1143	* @param a_u16TrackingData The tracking data to store.
1144	*/
1145	#define PGM_PAGE_SET_TRACKING(a_pVM, a_pPage, a_u16TrackingData) \
1146	do { (a_pPage)->s.u16TrackingY = (a_u16TrackingData); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1147
1148	/** @def PGM_PAGE_GET_TD_CREFS
1149	* Gets the @a cRefs tracking data member.
1150	* @returns cRefs.
1151	* @param a_pPage Pointer to the physical guest page tracking structure.
1152	*/
1153	#define PGM_PAGE_GET_TD_CREFS(a_pPage) \
1154	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1155	#define PGM_PAGE_GET_TD_CREFS_NA(a_pPage) \
1156	((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1157
1158	/** @def PGM_PAGE_GET_TD_IDX
1159	* Gets the @a idx tracking data member.
1160	* @returns idx.
1161	* @param a_pPage Pointer to the physical guest page tracking structure.
1162	*/
1163	#define PGM_PAGE_GET_TD_IDX(a_pPage) \
1164	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1165	#define PGM_PAGE_GET_TD_IDX_NA(a_pPage) \
1166	((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1167
1168
1169	/** Max number of locks on a page. */
1170	#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1171
1172	/** Get the read lock count.
1173	* @returns count.
1174	* @param a_pPage Pointer to the physical guest page tracking structure.
1175	*/
1176	#define PGM_PAGE_GET_READ_LOCKS(a_pPage) ( (a_pPage)->s.cReadLocksY )
1177
1178	/** Get the write lock count.
1179	* @returns count.
1180	* @param a_pPage Pointer to the physical guest page tracking structure.
1181	*/
1182	#define PGM_PAGE_GET_WRITE_LOCKS(a_pPage) ( (a_pPage)->s.cWriteLocksY )
1183
1184	/** Decrement the read lock counter.
1185	* @param a_pPage Pointer to the physical guest page tracking structure.
1186	*/
1187	#define PGM_PAGE_DEC_READ_LOCKS(a_pPage) do { --(a_pPage)->s.cReadLocksY; } while (0)
1188
1189	/** Decrement the write lock counter.
1190	* @param a_pPage Pointer to the physical guest page tracking structure.
1191	*/
1192	#define PGM_PAGE_DEC_WRITE_LOCKS(a_pPage) do { --(a_pPage)->s.cWriteLocksY; } while (0)
1193
1194	/** Increment the read lock counter.
1195	* @param a_pPage Pointer to the physical guest page tracking structure.
1196	*/
1197	#define PGM_PAGE_INC_READ_LOCKS(a_pPage) do { ++(a_pPage)->s.cReadLocksY; } while (0)
1198
1199	/** Increment the write lock counter.
1200	* @param a_pPage Pointer to the physical guest page tracking structure.
1201	*/
1202	#define PGM_PAGE_INC_WRITE_LOCKS(a_pPage) do { ++(a_pPage)->s.cWriteLocksY; } while (0)
1203
1204
1205	/** Gets the NEM state.
1206	* @returns NEM state value (two bits).
1207	* @param a_pPage Pointer to the physical guest page tracking structure.
1208	*/
1209	#define PGM_PAGE_GET_NEM_STATE(a_pPage) ((a_pPage)->s.u2NemStateY)
1210
1211	/** Sets the NEM state.
1212	* @param a_pPage Pointer to the physical guest page tracking structure.
1213	* @param a_u2State The NEM state value (specific to NEM impl.).
1214	*/
1215	#define PGM_PAGE_SET_NEM_STATE(a_pPage, a_u2State) \
1216	do { Assert((a_u2State) < 4); (a_pPage)->s.u2NemStateY = (a_u2State); } while (0)
1217
1218
1219	#if 0
1220	/** Enables sanity checking of write monitoring using CRC-32. */
1221	# define PGMLIVESAVERAMPAGE_WITH_CRC32
1222	#endif
1223
1224	/**
1225	* Per page live save tracking data.
1226	*/
1227	typedef struct PGMLIVESAVERAMPAGE
1228	{
1229	/** Number of times it has been dirtied. */
1230	uint32_t cDirtied : 24;
1231	/** Whether it is currently dirty. */
1232	uint32_t fDirty : 1;
1233	/** Ignore the page.
1234	* This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1235	* deal with these after pausing the VM and DevPCI have said it bit about
1236	* remappings. */
1237	uint32_t fIgnore : 1;
1238	/** Was a ZERO page last time around. */
1239	uint32_t fZero : 1;
1240	/** Was a SHARED page last time around. */
1241	uint32_t fShared : 1;
1242	/** Whether the page is/was write monitored in a previous pass. */
1243	uint32_t fWriteMonitored : 1;
1244	/** Whether the page is/was write monitored earlier in this pass. */
1245	uint32_t fWriteMonitoredJustNow : 1;
1246	/** Bits reserved for future use. */
1247	uint32_t u2Reserved : 2;
1248	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1249	/** CRC-32 for the page. This is for internal consistency checks. */
1250	uint32_t u32Crc;
1251	#endif
1252	} PGMLIVESAVERAMPAGE;
1253	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1254	AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1255	#else
1256	AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1257	#endif
1258	/** Pointer to the per page live save tracking data. */
1259	typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1260
1261	/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1262	#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1263
1264
1265	/**
1266	* RAM range for GC Phys to HC Phys conversion.
1267	*
1268	* Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1269	* conversions too, but we'll let MM handle that for now.
1270	*
1271	* This structure is used by linked lists in both GC and HC.
1272	*/
1273	typedef struct PGMRAMRANGE
1274	{
1275	/** Start of the range. Page aligned. */
1276	RTGCPHYS GCPhys;
1277	/** Size of the range. (Page aligned of course). */
1278	RTGCPHYS cb;
1279	/** Pointer to the next RAM range - for R3. */
1280	R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1281	/** Pointer to the next RAM range - for R0. */
1282	R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1283	/** PGM_RAM_RANGE_FLAGS_* flags. */
1284	uint32_t fFlags;
1285	/** NEM specific info, UINT32_MAX if not used. */
1286	uint32_t uNemRange;
1287	/** Last address in the range (inclusive). Page aligned (-1). */
1288	RTGCPHYS GCPhysLast;
1289	/** Start of the HC mapping of the range. This is only used for MMIO2 and in NEM mode. */
1290	R3PTRTYPE(void *) pvR3;
1291	/** Live save per page tracking data. */
1292	R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1293	/** The range description. */
1294	R3PTRTYPE(const char *) pszDesc;
1295	/** Pointer to self - R0 pointer. */
1296	R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1297
1298	/** Pointer to the left search three node - ring-3 context. */
1299	R3PTRTYPE(struct PGMRAMRANGE *) pLeftR3;
1300	/** Pointer to the right search three node - ring-3 context. */
1301	R3PTRTYPE(struct PGMRAMRANGE *) pRightR3;
1302	/** Pointer to the left search three node - ring-0 context. */
1303	R0PTRTYPE(struct PGMRAMRANGE *) pLeftR0;
1304	/** Pointer to the right search three node - ring-0 context. */
1305	R0PTRTYPE(struct PGMRAMRANGE *) pRightR0;
1306
1307	/** Padding to make aPage aligned on sizeof(PGMPAGE). */
1308	#if HC_ARCH_BITS == 32
1309	uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 0];
1310	#endif
1311	/** Array of physical guest page tracking structures.
1312	* @note Number of entries is PGMRAMRANGE::cb / GUEST_PAGE_SIZE. */
1313	PGMPAGE aPages[1];
1314	} PGMRAMRANGE;
1315	/** Pointer to RAM range for GC Phys to HC Phys conversion. */
1316	typedef PGMRAMRANGE *PPGMRAMRANGE;
1317
1318	/** @name PGMRAMRANGE::fFlags
1319	* @{ */
1320	/** The RAM range is floating around as an independent guest mapping. */
1321	#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1322	/** Ad hoc RAM range for an ROM mapping. */
1323	#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1324	/** Ad hoc RAM range for an MMIO mapping. */
1325	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1326	/** Ad hoc RAM range for an MMIO2 or pre-registered MMIO mapping. */
1327	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX RT_BIT(23)
1328	/** @} */
1329
1330	/** Tests if a RAM range is an ad hoc one or not.
1331	* @returns true/false.
1332	* @param pRam The RAM range.
1333	*/
1334	#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1335	(!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX) ) )
1336
1337	/** The number of entries in the RAM range TLBs (there is one for each
1338	* context). Must be a power of two. */
1339	#define PGM_RAMRANGE_TLB_ENTRIES 8
1340
1341	/**
1342	* Calculates the RAM range TLB index for the physical address.
1343	*
1344	* @returns RAM range TLB index.
1345	* @param a_GCPhys The guest physical address.
1346	*/
1347	#define PGM_RAMRANGE_TLB_IDX(a_GCPhys) ( ((a_GCPhys) >> 20) & (PGM_RAMRANGE_TLB_ENTRIES - 1) )
1348
1349	/**
1350	* Calculates the ring-3 address for a_GCPhysPage if the RAM range has a
1351	* mapping address.
1352	*/
1353	#define PGM_RAMRANGE_CALC_PAGE_R3PTR(a_pRam, a_GCPhysPage) \
1354	( (a_pRam)->pvR3 ? (R3PTRTYPE(uint8_t *))(a_pRam)->pvR3 + (a_GCPhysPage) - (a_pRam)->GCPhys : NULL )
1355
1356
1357	/**
1358	* Per page tracking structure for ROM image.
1359	*
1360	* A ROM image may have a shadow page, in which case we may have two pages
1361	* backing it. This structure contains the PGMPAGE for both while
1362	* PGMRAMRANGE have a copy of the active one. It is important that these
1363	* aren't out of sync in any regard other than page pool tracking data.
1364	*/
1365	typedef struct PGMROMPAGE
1366	{
1367	/** The page structure for the virgin ROM page. */
1368	PGMPAGE Virgin;
1369	/** The page structure for the shadow RAM page. */
1370	PGMPAGE Shadow;
1371	/** The current protection setting. */
1372	PGMROMPROT enmProt;
1373	/** Live save status information. Makes use of unused alignment space. */
1374	struct
1375	{
1376	/** The previous protection value. */
1377	uint8_t u8Prot;
1378	/** Written to flag set by the handler. */
1379	bool fWrittenTo;
1380	/** Whether the shadow page is dirty or not. */
1381	bool fDirty;
1382	/** Whether it was dirtied in the recently. */
1383	bool fDirtiedRecently;
1384	} LiveSave;
1385	} PGMROMPAGE;
1386	AssertCompileSizeAlignment(PGMROMPAGE, 8);
1387	/** Pointer to a ROM page tracking structure. */
1388	typedef PGMROMPAGE *PPGMROMPAGE;
1389
1390
1391	/**
1392	* A registered ROM image.
1393	*
1394	* This is needed to keep track of ROM image since they generally intrude
1395	* into a PGMRAMRANGE. It also keeps track of additional info like the
1396	* two page sets (read-only virgin and read-write shadow), the current
1397	* state of each page.
1398	*
1399	* Because access handlers cannot easily be executed in a different
1400	* context, the ROM ranges needs to be accessible and in all contexts.
1401	*/
1402	typedef struct PGMROMRANGE
1403	{
1404	/** Pointer to the next range - R3. */
1405	R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1406	/** Pointer to the next range - R0. */
1407	R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1408	/** Pointer to the this range - R0. */
1409	R0PTRTYPE(struct PGMROMRANGE *) pSelfR0;
1410	/** Address of the range. */
1411	RTGCPHYS GCPhys;
1412	/** Address of the last byte in the range. */
1413	RTGCPHYS GCPhysLast;
1414	/** Size of the range. */
1415	RTGCPHYS cb;
1416	/** The flags (PGMPHYS_ROM_FLAGS_). /
1417	uint8_t fFlags;
1418	/** The saved state range ID. */
1419	uint8_t idSavedState;
1420	/** Alignment padding. */
1421	uint8_t au8Alignment[2];
1422	/** The size bits pvOriginal points to. */
1423	uint32_t cbOriginal;
1424	/** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1425	* This is used for strictness checks. */
1426	R3PTRTYPE(const void *) pvOriginal;
1427	/** The ROM description. */
1428	R3PTRTYPE(const char *) pszDesc;
1429	#ifdef VBOX_WITH_PGM_NEM_MODE
1430	/** In simplified memory mode this provides alternate backing for shadowed ROMs.
1431	* - PGMROMPROT_READ_ROM_WRITE_IGNORE: Shadow
1432	* - PGMROMPROT_READ_ROM_WRITE_RAM: Shadow
1433	* - PGMROMPROT_READ_RAM_WRITE_IGNORE: ROM
1434	* - PGMROMPROT_READ_RAM_WRITE_RAM: ROM */
1435	R3PTRTYPE(uint8_t *) pbR3Alternate;
1436	RTR3PTR pvAlignment2;
1437	#endif
1438	/** The per page tracking structures. */
1439	PGMROMPAGE aPages[1];
1440	} PGMROMRANGE;
1441	/** Pointer to a ROM range. */
1442	typedef PGMROMRANGE *PPGMROMRANGE;
1443
1444
1445	/**
1446	* Live save per page data for an MMIO2 page.
1447	*
1448	* Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1449	* of MMIO2 pages. The current approach is using some optimistic SHA-1 +
1450	* CRC-32 for detecting changes as well as special handling of zero pages. This
1451	* is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1452	* for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1453	* because of speed (2.5x and 6x slower).)
1454	*
1455	* @todo Implement dirty MMIO2 page reporting that can be enabled during live
1456	* save but normally is disabled. Since we can write monitor guest
1457	* accesses on our own, we only need this for host accesses. Shouldn't be
1458	* too difficult for DevVGA, VMMDev might be doable, the planned
1459	* networking fun will be fun since it involves ring-0.
1460	*/
1461	typedef struct PGMLIVESAVEMMIO2PAGE
1462	{
1463	/** Set if the page is considered dirty. */
1464	bool fDirty;
1465	/** The number of scans this page has remained unchanged for.
1466	* Only updated for dirty pages. */
1467	uint8_t cUnchangedScans;
1468	/** Whether this page was zero at the last scan. */
1469	bool fZero;
1470	/** Alignment padding. */
1471	bool fReserved;
1472	/** CRC-32 for the first half of the page.
1473	* This is used together with u32CrcH2 to quickly detect changes in the page
1474	* during the non-final passes. */
1475	uint32_t u32CrcH1;
1476	/** CRC-32 for the second half of the page. */
1477	uint32_t u32CrcH2;
1478	/** SHA-1 for the saved page.
1479	* This is used in the final pass to skip pages without changes. */
1480	uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1481	} PGMLIVESAVEMMIO2PAGE;
1482	/** Pointer to a live save status data for an MMIO2 page. */
1483	typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1484
1485	/**
1486	* A registered MMIO2 (= Device RAM) range.
1487	*
1488	* There are a few reason why we need to keep track of these registrations. One
1489	* of them is the deregistration & cleanup stuff, while another is that the
1490	* PGMRAMRANGE associated with such a region may have to be removed from the ram
1491	* range list.
1492	*
1493	* Overlapping with a RAM range has to be 100% or none at all. The pages in the
1494	* existing RAM range must not be ROM nor MMIO. A guru meditation will be
1495	* raised if a partial overlap or an overlap of ROM pages is encountered. On an
1496	* overlap we will free all the existing RAM pages and put in the ram range
1497	* pages instead.
1498	*/
1499	typedef struct PGMREGMMIO2RANGE
1500	{
1501	/** The owner of the range. (a device) */
1502	PPDMDEVINSR3 pDevInsR3;
1503	/** Pointer to the ring-3 mapping of the allocation. */
1504	RTR3PTR pvR3;
1505	#ifndef VBOX_WITH_LINEAR_HOST_PHYS_MEM
1506	/** Pointer to the ring-0 mapping of the allocation. */
1507	RTR0PTR pvR0;
1508	#endif
1509	/** Pointer to the next range - R3. */
1510	R3PTRTYPE(struct PGMREGMMIO2RANGE *) pNextR3;
1511	/** Flags (PGMREGMMIO2RANGE_F_XXX). */
1512	uint16_t fFlags;
1513	/** The sub device number (internal PCI config (CFGM) number). */
1514	uint8_t iSubDev;
1515	/** The PCI region number. */
1516	uint8_t iRegion;
1517	/** The saved state range ID. */
1518	uint8_t idSavedState;
1519	/** MMIO2 range identifier, for page IDs (PGMPAGE::s.idPage). */
1520	uint8_t idMmio2;
1521	/** Alignment padding for putting the ram range on a PGMPAGE alignment boundary. */
1522	#ifndef VBOX_WITH_LINEAR_HOST_PHYS_MEM
1523	uint8_t abAlignment[HC_ARCH_BITS == 32 ? 6 + 4 : 2];
1524	#else
1525	uint8_t abAlignment[HC_ARCH_BITS == 32 ? 6 + 8 : 2 + 8];
1526	#endif
1527	/** The real size.
1528	* This may be larger than indicated by RamRange.cb if the range has been
1529	* reduced during saved state loading. */
1530	RTGCPHYS cbReal;
1531	/** Pointer to the physical handler for MMIO.
1532	* If NEM is responsible for tracking dirty pages in simple memory mode, this
1533	* will be NULL. */
1534	R3PTRTYPE(PPGMPHYSHANDLER) pPhysHandlerR3;
1535	/** Live save per page tracking data for MMIO2. */
1536	R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1537	/** The associated RAM range. */
1538	PGMRAMRANGE RamRange;
1539	} PGMREGMMIO2RANGE;
1540	AssertCompileMemberAlignment(PGMREGMMIO2RANGE, RamRange, 16);
1541	/** Pointer to a MMIO2 or pre-registered MMIO range. */
1542	typedef PGMREGMMIO2RANGE *PPGMREGMMIO2RANGE;
1543
1544	/** @name PGMREGMMIO2RANGE_F_XXX - Registered MMIO2 range flags.
1545	* @{ */
1546	/** Set if this is the first chunk in the MMIO2 range. */
1547	#define PGMREGMMIO2RANGE_F_FIRST_CHUNK UINT16_C(0x0001)
1548	/** Set if this is the last chunk in the MMIO2 range. */
1549	#define PGMREGMMIO2RANGE_F_LAST_CHUNK UINT16_C(0x0002)
1550	/** Set if the whole range is mapped. */
1551	#define PGMREGMMIO2RANGE_F_MAPPED UINT16_C(0x0004)
1552	/** Set if it's overlapping, clear if not. */
1553	#define PGMREGMMIO2RANGE_F_OVERLAPPING UINT16_C(0x0008)
1554	/** This mirrors the PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES creation flag.*/
1555	#define PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES UINT16_C(0x0010)
1556	/** Set if the access handler is registered. */
1557	#define PGMREGMMIO2RANGE_F_IS_TRACKING UINT16_C(0x0020)
1558	/** Set if dirty page tracking is currently enabled. */
1559	#define PGMREGMMIO2RANGE_F_TRACKING_ENABLED UINT16_C(0x0040)
1560	/** Set if there are dirty pages in the range. */
1561	#define PGMREGMMIO2RANGE_F_IS_DIRTY UINT16_C(0x0080)
1562	/** @} */
1563
1564
1565	/** @name Internal MMIO2 constants.
1566	* @{ */
1567	/** The maximum number of MMIO2 ranges. */
1568	#define PGM_MMIO2_MAX_RANGES 32
1569	/** The maximum number of pages in a MMIO2 range. */
1570	#define PGM_MMIO2_MAX_PAGE_COUNT UINT32_C(0x01000000)
1571	/** Makes a MMIO2 page ID out of a MMIO2 range ID and page index number. */
1572	#define PGM_MMIO2_PAGEID_MAKE(a_idMmio2, a_iPage) ( ((uint32_t)(a_idMmio2) << 24) \| (uint32_t)(a_iPage) )
1573	/** Gets the MMIO2 range ID from an MMIO2 page ID. */
1574	#define PGM_MMIO2_PAGEID_GET_MMIO2_ID(a_idPage) ( (uint8_t)((a_idPage) >> 24) )
1575	/** Gets the MMIO2 page index from an MMIO2 page ID. */
1576	#define PGM_MMIO2_PAGEID_GET_IDX(a_idPage) ( ((a_idPage) & UINT32_C(0x00ffffff)) )
1577	/** @} */
1578
1579
1580
1581	/**
1582	* PGMPhysRead/Write cache entry
1583	*/
1584	typedef struct PGMPHYSCACHEENTRY
1585	{
1586	/** R3 pointer to physical page. */
1587	R3PTRTYPE(uint8_t *) pbR3;
1588	/** GC Physical address for cache entry */
1589	RTGCPHYS GCPhys;
1590	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1591	RTGCPHYS u32Padding0; /*< alignment padding. /
1592	#endif
1593	} PGMPHYSCACHEENTRY;
1594
1595	/**
1596	* PGMPhysRead/Write cache to reduce REM memory access overhead
1597	*/
1598	typedef struct PGMPHYSCACHE
1599	{
1600	/** Bitmap of valid cache entries */
1601	uint64_t aEntries;
1602	/** Cache entries */
1603	PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1604	} PGMPHYSCACHE;
1605
1606
1607	/** @name Ring-3 page mapping TLBs
1608	* @{ */
1609
1610	/** Pointer to an allocation chunk ring-3 mapping. */
1611	typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1612	/** Pointer to an allocation chunk ring-3 mapping pointer. */
1613	typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1614
1615	/**
1616	* Ring-3 tracking structure for an allocation chunk ring-3 mapping.
1617	*
1618	* The primary tree (Core) uses the chunk id as key.
1619	*/
1620	typedef struct PGMCHUNKR3MAP
1621	{
1622	/** The key is the chunk id. */
1623	AVLU32NODECORE Core;
1624	/** The time (ChunkR3Map.iNow) this chunk was last used. Used for unmap
1625	* selection. */
1626	uint32_t iLastUsed;
1627	/** The current reference count. */
1628	uint32_t volatile cRefs;
1629	/** The current permanent reference count. */
1630	uint32_t volatile cPermRefs;
1631	/** The mapping address. */
1632	void *pv;
1633	} PGMCHUNKR3MAP;
1634
1635	/**
1636	* Allocation chunk ring-3 mapping TLB entry.
1637	*/
1638	typedef struct PGMCHUNKR3MAPTLBE
1639	{
1640	/** The chunk id. */
1641	uint32_t volatile idChunk;
1642	#if HC_ARCH_BITS == 64
1643	uint32_t u32Padding; /*< alignment padding. /
1644	#endif
1645	/** The chunk map. */
1646	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1647	} PGMCHUNKR3MAPTLBE;
1648	/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1649	typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1650
1651	/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1652	* @remark Must be a power of two value. */
1653	#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1654
1655	/**
1656	* Allocation chunk ring-3 mapping TLB.
1657	*
1658	* @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1659	* At first glance this might look kinda odd since AVL trees are
1660	* supposed to give the most optimal lookup times of all trees
1661	* due to their balancing. However, take a tree with 1023 nodes
1662	* in it, that's 10 levels, meaning that most searches has to go
1663	* down 9 levels before they find what they want. This isn't fast
1664	* compared to a TLB hit. There is the factor of cache misses,
1665	* and of course the problem with trees and branch prediction.
1666	* This is why we use TLBs in front of most of the trees.
1667	*
1668	* @todo Generalize this TLB + AVL stuff, shouldn't be all that
1669	* difficult when we switch to the new inlined AVL trees (from kStuff).
1670	*/
1671	typedef struct PGMCHUNKR3MAPTLB
1672	{
1673	/** The TLB entries. */
1674	PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1675	} PGMCHUNKR3MAPTLB;
1676
1677	/**
1678	* Calculates the index of a guest page in the Ring-3 Chunk TLB.
1679	* @returns Chunk TLB index.
1680	* @param idChunk The Chunk ID.
1681	*/
1682	#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1683
1684
1685	/**
1686	* Ring-3 guest page mapping TLB entry.
1687	* @remarks used in ring-0 as well at the moment.
1688	*/
1689	typedef struct PGMPAGER3MAPTLBE
1690	{
1691	/** Address of the page. */
1692	RTGCPHYS volatile GCPhys;
1693	/** The guest page. */
1694	R3PTRTYPE(PPGMPAGE) volatile pPage;
1695	/** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1696	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1697	/** The address */
1698	R3PTRTYPE(void *) volatile pv;
1699	#if HC_ARCH_BITS == 32
1700	uint32_t u32Padding; /*< alignment padding. /
1701	#endif
1702	} PGMPAGER3MAPTLBE;
1703	/** Pointer to an entry in the HC physical TLB. */
1704	typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1705
1706
1707	/** The number of entries in the ring-3 guest page mapping TLB.
1708	* @remarks The value must be a power of two. */
1709	#define PGM_PAGER3MAPTLB_ENTRIES 256
1710
1711	/**
1712	* Ring-3 guest page mapping TLB.
1713	* @remarks used in ring-0 as well at the moment.
1714	*/
1715	typedef struct PGMPAGER3MAPTLB
1716	{
1717	/** The TLB entries. */
1718	PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1719	} PGMPAGER3MAPTLB;
1720	/** Pointer to the ring-3 guest page mapping TLB. */
1721	typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1722
1723	/**
1724	* Calculates the index of the TLB entry for the specified guest page.
1725	* @returns Physical TLB index.
1726	* @param GCPhys The guest physical address.
1727	*/
1728	#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> GUEST_PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1729
1730	/** @} */
1731
1732
1733	/** @name Ring-0 page mapping TLB
1734	* @{ */
1735	/**
1736	* Ring-0 guest page mapping TLB entry.
1737	*/
1738	typedef struct PGMPAGER0MAPTLBE
1739	{
1740	/** Address of the page. */
1741	RTGCPHYS volatile GCPhys;
1742	/** The guest page. */
1743	R0PTRTYPE(PPGMPAGE) volatile pPage;
1744	/** The address */
1745	R0PTRTYPE(void *) volatile pv;
1746	} PGMPAGER0MAPTLBE;
1747	/** Pointer to an entry in the HC physical TLB. */
1748	typedef PGMPAGER0MAPTLBE *PPGMPAGER0MAPTLBE;
1749
1750
1751	/** The number of entries in the ring-3 guest page mapping TLB.
1752	* @remarks The value must be a power of two. */
1753	#define PGM_PAGER0MAPTLB_ENTRIES 256
1754
1755	/**
1756	* Ring-3 guest page mapping TLB.
1757	* @remarks used in ring-0 as well at the moment.
1758	*/
1759	typedef struct PGMPAGER0MAPTLB
1760	{
1761	/** The TLB entries. */
1762	PGMPAGER0MAPTLBE aEntries[PGM_PAGER0MAPTLB_ENTRIES];
1763	} PGMPAGER0MAPTLB;
1764	/** Pointer to the ring-3 guest page mapping TLB. */
1765	typedef PGMPAGER0MAPTLB *PPGMPAGER0MAPTLB;
1766
1767	/**
1768	* Calculates the index of the TLB entry for the specified guest page.
1769	* @returns Physical TLB index.
1770	* @param GCPhys The guest physical address.
1771	*/
1772	#define PGM_PAGER0MAPTLB_IDX(GCPhys) ( ((GCPhys) >> GUEST_PAGE_SHIFT) & (PGM_PAGER0MAPTLB_ENTRIES - 1) )
1773	/** @} */
1774
1775
1776	/** @name Context neutral page mapper TLB.
1777	*
1778	* Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1779	* code is writting in a kind of context neutral way. Time will show whether
1780	* this actually makes sense or not...
1781	*
1782	* @todo this needs to be reconsidered and dropped/redone since the ring-0
1783	* context ends up using a global mapping cache on some platforms
1784	* (darwin).
1785	*
1786	* @{ */
1787	/** @typedef PPGMPAGEMAPTLB
1788	* The page mapper TLB pointer type for the current context. */
1789	/** @typedef PPGMPAGEMAPTLB
1790	* The page mapper TLB entry pointer type for the current context. */
1791	/** @typedef PPGMPAGEMAPTLB
1792	* The page mapper TLB entry pointer pointer type for the current context. */
1793	/** @def PGM_PAGEMAPTLB_ENTRIES
1794	* The number of TLB entries in the page mapper TLB for the current context. */
1795	/** @def PGM_PAGEMAPTLB_IDX
1796	* Calculate the TLB index for a guest physical address.
1797	* @returns The TLB index.
1798	* @param GCPhys The guest physical address. */
1799	/** @typedef PPGMPAGEMAP
1800	* Pointer to a page mapper unit for current context. */
1801	/** @typedef PPPGMPAGEMAP
1802	* Pointer to a page mapper unit pointer for current context. */
1803	#if defined(IN_RING0)
1804	typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1805	typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1806	typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1807	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1808	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1809	typedef struct PGMCHUNKR0MAP *PPGMPAGEMAP;
1810	typedef struct PGMCHUNKR0MAP **PPPGMPAGEMAP;
1811	#else
1812	typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1813	typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1814	typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1815	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1816	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1817	typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1818	typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1819	#endif
1820	/** @} */
1821
1822
1823	/** @name PGM Pool Indexes.
1824	* Aka. the unique shadow page identifier.
1825	* @{ */
1826	/** NIL page pool IDX. */
1827	#define NIL_PGMPOOL_IDX 0
1828	/** The first normal index. There used to be 5 fictive pages up front, now
1829	* there is only the NIL page. */
1830	#define PGMPOOL_IDX_FIRST 1
1831	/** The last valid index. (inclusive, 14 bits) */
1832	#define PGMPOOL_IDX_LAST 0x3fff
1833	/** @} */
1834
1835	/** The NIL index for the parent chain. */
1836	#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1837	#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1838
1839	/**
1840	* Node in the chain linking a shadowed page to it's parent (user).
1841	*/
1842	#pragma pack(1)
1843	typedef struct PGMPOOLUSER
1844	{
1845	/** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1846	uint16_t iNext;
1847	/** The user page index. */
1848	uint16_t iUser;
1849	/** Index into the user table. */
1850	uint32_t iUserTable;
1851	} PGMPOOLUSER, *PPGMPOOLUSER;
1852	typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1853	#pragma pack()
1854
1855
1856	/** The NIL index for the phys ext chain. */
1857	#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1858	/** The NIL pte index for a phys ext chain slot. */
1859	#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
1860
1861	/**
1862	* Node in the chain of physical cross reference extents.
1863	* @todo Calling this an 'extent' is not quite right, find a better name.
1864	* @todo find out the optimal size of the aidx array
1865	*/
1866	#pragma pack(1)
1867	typedef struct PGMPOOLPHYSEXT
1868	{
1869	/** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1870	uint16_t iNext;
1871	/** Alignment. */
1872	uint16_t u16Align;
1873	/** The user page index. */
1874	uint16_t aidx[3];
1875	/** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
1876	uint16_t apte[3];
1877	} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1878	typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1879	#pragma pack()
1880
1881
1882	/**
1883	* The kind of page that's being shadowed.
1884	*/
1885	typedef enum PGMPOOLKIND
1886	{
1887	/** The virtual invalid 0 entry. */
1888	PGMPOOLKIND_INVALID = 0,
1889	/** The entry is free (=unused). */
1890	PGMPOOLKIND_FREE,
1891
1892	/** Shw: 32-bit page table; Gst: no paging. */
1893	PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1894	/** Shw: 32-bit page table; Gst: 32-bit page table. */
1895	PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1896	/** Shw: 32-bit page table; Gst: 4MB page. */
1897	PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1898	/** Shw: PAE page table; Gst: no paging. */
1899	PGMPOOLKIND_PAE_PT_FOR_PHYS,
1900	/** Shw: PAE page table; Gst: 32-bit page table. */
1901	PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1902	/** Shw: PAE page table; Gst: Half of a 4MB page. */
1903	PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1904	/** Shw: PAE page table; Gst: PAE page table. */
1905	PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1906	/** Shw: PAE page table; Gst: 2MB page. */
1907	PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1908
1909	/** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1910	PGMPOOLKIND_32BIT_PD,
1911	/** Shw: 32-bit page directory. Gst: no paging. */
1912	PGMPOOLKIND_32BIT_PD_PHYS,
1913	/** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1914	PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1915	/** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1916	PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1917	/** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1918	PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1919	/** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1920	PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1921	/** Shw: PAE page directory; Gst: PAE page directory. */
1922	PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1923	/** Shw: PAE page directory; Gst: no paging. Note: +NP. */
1924	PGMPOOLKIND_PAE_PD_PHYS,
1925
1926	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1927	PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1928	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1929	PGMPOOLKIND_PAE_PDPT,
1930	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1931	PGMPOOLKIND_PAE_PDPT_PHYS,
1932
1933	/** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1934	PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1935	/** Shw: 64-bit page directory pointer table; Gst: no paging. */
1936	PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1937	/** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1938	PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1939	/** Shw: 64-bit page directory table; Gst: no paging. */
1940	PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 24 */
1941
1942	/** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1943	PGMPOOLKIND_64BIT_PML4,
1944
1945	/** Shw: EPT page directory pointer table; Gst: no paging. */
1946	PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1947	/** Shw: EPT page directory table; Gst: no paging. */
1948	PGMPOOLKIND_EPT_PD_FOR_PHYS,
1949	/** Shw: EPT page table; Gst: no paging. */
1950	PGMPOOLKIND_EPT_PT_FOR_PHYS,
1951
1952	/** Shw: Root Nested paging table. */
1953	PGMPOOLKIND_ROOT_NESTED,
1954
1955	/** Shw: EPT page table; Gst: EPT page table. */
1956	PGMPOOLKIND_EPT_PT_FOR_EPT_PT,
1957	/** Shw: EPT page table; Gst: 2MB page. */
1958	PGMPOOLKIND_EPT_PT_FOR_EPT_2MB,
1959	/** Shw: EPT page directory table; Gst: EPT page directory. */
1960	PGMPOOLKIND_EPT_PD_FOR_EPT_PD,
1961	/** Shw: EPT page directory pointer table; Gst: EPT page directory pointer table. */
1962	PGMPOOLKIND_EPT_PDPT_FOR_EPT_PDPT,
1963	/** Shw: EPT PML4; Gst: EPT PML4. */
1964	PGMPOOLKIND_EPT_PML4_FOR_EPT_PML4,
1965
1966	/** The last valid entry. */
1967	PGMPOOLKIND_LAST = PGMPOOLKIND_EPT_PML4_FOR_EPT_PML4
1968	} PGMPOOLKIND;
1969
1970	/**
1971	* The access attributes of the page; only applies to big pages.
1972	*/
1973	typedef enum
1974	{
1975	PGMPOOLACCESS_DONTCARE = 0,
1976	PGMPOOLACCESS_USER_RW,
1977	PGMPOOLACCESS_USER_R,
1978	PGMPOOLACCESS_USER_RW_NX,
1979	PGMPOOLACCESS_USER_R_NX,
1980	PGMPOOLACCESS_SUPERVISOR_RW,
1981	PGMPOOLACCESS_SUPERVISOR_R,
1982	PGMPOOLACCESS_SUPERVISOR_RW_NX,
1983	PGMPOOLACCESS_SUPERVISOR_R_NX
1984	} PGMPOOLACCESS;
1985
1986	/**
1987	* The tracking data for a page in the pool.
1988	*/
1989	typedef struct PGMPOOLPAGE
1990	{
1991	/** AVL node code with the (HC) physical address of this page. */
1992	AVLOHCPHYSNODECORE Core;
1993	/** Pointer to the R3 mapping of the page. */
1994	R3PTRTYPE(void *) pvPageR3;
1995	/** Pointer to the R0 mapping of the page. */
1996	R0PTRTYPE(void *) pvPageR0;
1997	/** The guest physical address. */
1998	RTGCPHYS GCPhys;
1999	/** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
2000	uint8_t enmKind;
2001	/** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
2002	uint8_t enmAccess;
2003	/** This supplements enmKind and enmAccess */
2004	bool fA20Enabled : 1;
2005
2006	/** Used to indicate that the page is zeroed. */
2007	bool fZeroed : 1;
2008	/** Used to indicate that a PT has non-global entries. */
2009	bool fSeenNonGlobal : 1;
2010	/** Used to indicate that we're monitoring writes to the guest page. */
2011	bool fMonitored : 1;
2012	/** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
2013	* (All pages are in the age list.) */
2014	bool fCached : 1;
2015	/** This is used by the R3 access handlers when invoked by an async thread.
2016	* It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
2017	bool volatile fReusedFlushPending : 1;
2018	/** Used to mark the page as dirty (write monitoring is temporarily
2019	* off). */
2020	bool fDirty : 1;
2021	bool fPadding1 : 1;
2022	bool fPadding2;
2023
2024	/** The index of this page. */
2025	uint16_t idx;
2026	/** The next entry in the list this page currently resides in.
2027	* It's either in the free list or in the GCPhys hash. */
2028	uint16_t iNext;
2029	/** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
2030	uint16_t iUserHead;
2031	/** The number of present entries. */
2032	uint16_t cPresent;
2033	/** The first entry in the table which is present. */
2034	uint16_t iFirstPresent;
2035	/** The number of modifications to the monitored page. */
2036	uint16_t cModifications;
2037	/** The next modified page. NIL_PGMPOOL_IDX if tail. */
2038	uint16_t iModifiedNext;
2039	/** The previous modified page. NIL_PGMPOOL_IDX if head. */
2040	uint16_t iModifiedPrev;
2041	/** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
2042	uint16_t iMonitoredNext;
2043	/** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
2044	uint16_t iMonitoredPrev;
2045	/** The next page in the age list. */
2046	uint16_t iAgeNext;
2047	/** The previous page in the age list. */
2048	uint16_t iAgePrev;
2049	/** Index into PGMPOOL::aDirtyPages if fDirty is set. */
2050	uint8_t idxDirtyEntry;
2051
2052	/** @name Access handler statistics to determine whether the guest is
2053	* (re)initializing a page table.
2054	* @{ */
2055	RTGCPTR GCPtrLastAccessHandlerRip;
2056	RTGCPTR GCPtrLastAccessHandlerFault;
2057	uint64_t cLastAccessHandler;
2058	/** @} */
2059	/** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages. */
2060	uint32_t volatile cLocked;
2061	#if GC_ARCH_BITS == 64
2062	uint32_t u32Alignment3;
2063	#endif
2064	# ifdef VBOX_STRICT
2065	RTGCPTR GCPtrDirtyFault;
2066	# endif
2067	} PGMPOOLPAGE;
2068	/** Pointer to a pool page. */
2069	typedef PGMPOOLPAGE *PPGMPOOLPAGE;
2070	/** Pointer to a const pool page. */
2071	typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2072	/** Pointer to a pool page pointer. */
2073	typedef PGMPOOLPAGE **PPPGMPOOLPAGE;
2074
2075
2076	/** The hash table size. */
2077	# define PGMPOOL_HASH_SIZE 0x8000
2078	/** The hash function. */
2079	# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> GUEST_PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2080
2081
2082	/**
2083	* The shadow page pool instance data.
2084	*
2085	* It's all one big allocation made at init time, except for the
2086	* pages that is. The user nodes follows immediately after the
2087	* page structures.
2088	*/
2089	typedef struct PGMPOOL
2090	{
2091	/** The VM handle - R3 Ptr. */
2092	PVMR3 pVMR3;
2093	/** The VM handle - R0 Ptr. */
2094	R0PTRTYPE(PVMCC) pVMR0;
2095	/** The ring-3 pointer to this structure. */
2096	R3PTRTYPE(struct PGMPOOL *) pPoolR3;
2097	/** The ring-0 pointer to this structure. */
2098	R0PTRTYPE(struct PGMPOOL *) pPoolR0;
2099	/** The max pool size. This includes the special IDs. */
2100	uint16_t cMaxPages;
2101	/** The current pool size. */
2102	uint16_t cCurPages;
2103	/** The head of the free page list. */
2104	uint16_t iFreeHead;
2105	/* Padding. */
2106	uint16_t u16Padding;
2107	/** Head of the chain of free user nodes. */
2108	uint16_t iUserFreeHead;
2109	/** The number of user nodes we've allocated. */
2110	uint16_t cMaxUsers;
2111	/** The number of present page table entries in the entire pool. */
2112	uint32_t cPresent;
2113	/** Pointer to the array of user nodes - R3 pointer. */
2114	R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2115	/** Pointer to the array of user nodes - R0 pointer. */
2116	R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2117	/** Head of the chain of free phys ext nodes. */
2118	uint16_t iPhysExtFreeHead;
2119	/** The number of user nodes we've allocated. */
2120	uint16_t cMaxPhysExts;
2121	uint32_t u32Padding0b;
2122	/** Pointer to the array of physical xref extent nodes - R3 pointer. */
2123	R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2124	/** Pointer to the array of physical xref extent nodes - R0 pointer. */
2125	R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2126	/** Hash table for GCPhys addresses. */
2127	uint16_t aiHash[PGMPOOL_HASH_SIZE];
2128	/** The head of the age list. */
2129	uint16_t iAgeHead;
2130	/** The tail of the age list. */
2131	uint16_t iAgeTail;
2132	/** Set if the cache is enabled. */
2133	bool fCacheEnabled;
2134	/** Alignment padding. */
2135	bool afPadding1[3];
2136	/** Head of the list of modified pages. */
2137	uint16_t iModifiedHead;
2138	/** The current number of modified pages. */
2139	uint16_t cModifiedPages;
2140	/** Alignment padding. */
2141	uint32_t u32Padding2;
2142	/** Physical access handler type registration handle. */
2143	PGMPHYSHANDLERTYPE hAccessHandlerType;
2144	/** Next available slot (in aDirtyPages). */
2145	uint32_t idxFreeDirtyPage;
2146	/** Number of active dirty pages. */
2147	uint32_t cDirtyPages;
2148	/** Array of current dirty pgm pool page indices. */
2149	uint16_t aidxDirtyPages[16];
2150	/** Array running in parallel to aidxDirtyPages with the page data. */
2151	struct
2152	{
2153	uint64_t aPage[512];
2154	} aDirtyPages[16];
2155
2156	/** The number of pages currently in use. */
2157	uint16_t cUsedPages;
2158	#ifdef VBOX_WITH_STATISTICS
2159	/** The high water mark for cUsedPages. */
2160	uint16_t cUsedPagesHigh;
2161	uint32_t Alignment1; /*< Align the next member on a 64-bit boundary. /
2162	/** Profiling pgmPoolAlloc(). */
2163	STAMPROFILEADV StatAlloc;
2164	/** Profiling pgmR3PoolClearDoIt(). */
2165	STAMPROFILE StatClearAll;
2166	/** Profiling pgmR3PoolReset(). */
2167	STAMPROFILE StatR3Reset;
2168	/** Profiling pgmPoolFlushPage(). */
2169	STAMPROFILE StatFlushPage;
2170	/** Profiling pgmPoolFree(). */
2171	STAMPROFILE StatFree;
2172	/** Counting explicit flushes by PGMPoolFlushPage(). */
2173	STAMCOUNTER StatForceFlushPage;
2174	/** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2175	STAMCOUNTER StatForceFlushDirtyPage;
2176	/** Counting flushes for reused pages. */
2177	STAMCOUNTER StatForceFlushReused;
2178	/** Profiling time spent zeroing pages. */
2179	STAMPROFILE StatZeroPage;
2180	/** Profiling of pgmPoolTrackDeref. */
2181	STAMPROFILE StatTrackDeref;
2182	/** Profiling pgmTrackFlushGCPhysPT. */
2183	STAMPROFILE StatTrackFlushGCPhysPT;
2184	/** Profiling pgmTrackFlushGCPhysPTs. */
2185	STAMPROFILE StatTrackFlushGCPhysPTs;
2186	/** Profiling pgmTrackFlushGCPhysPTsSlow. */
2187	STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2188	/** Number of times we've been out of user records. */
2189	STAMCOUNTER StatTrackFreeUpOneUser;
2190	/** Nr of flushed entries. */
2191	STAMCOUNTER StatTrackFlushEntry;
2192	/** Nr of updated entries. */
2193	STAMCOUNTER StatTrackFlushEntryKeep;
2194	/** Profiling deref activity related tracking GC physical pages. */
2195	STAMPROFILE StatTrackDerefGCPhys;
2196	/** Number of linear searches for a HCPhys in the ram ranges. */
2197	STAMCOUNTER StatTrackLinearRamSearches;
2198	/** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2199	STAMCOUNTER StamTrackPhysExtAllocFailures;
2200
2201	/** Profiling the RC/R0 \#PF access handler. */
2202	STAMPROFILE StatMonitorPfRZ;
2203	/** Profiling the RC/R0 access we've handled (except REP STOSD). */
2204	STAMPROFILE StatMonitorPfRZHandled;
2205	/** Times we've failed interpreting the instruction. */
2206	STAMCOUNTER StatMonitorPfRZEmulateInstr;
2207	/** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2208	STAMPROFILE StatMonitorPfRZFlushPage;
2209	/** Times we've detected a page table reinit. */
2210	STAMCOUNTER StatMonitorPfRZFlushReinit;
2211	/** Counting flushes for pages that are modified too often. */
2212	STAMCOUNTER StatMonitorPfRZFlushModOverflow;
2213	/** Times we've detected fork(). */
2214	STAMCOUNTER StatMonitorPfRZFork;
2215	/** Times we've failed interpreting a patch code instruction. */
2216	STAMCOUNTER StatMonitorPfRZIntrFailPatch1;
2217	/** Times we've failed interpreting a patch code instruction during flushing. */
2218	STAMCOUNTER StatMonitorPfRZIntrFailPatch2;
2219	/** The number of times we've seen rep prefixes we can't handle. */
2220	STAMCOUNTER StatMonitorPfRZRepPrefix;
2221	/** Profiling the REP STOSD cases we've handled. */
2222	STAMPROFILE StatMonitorPfRZRepStosd;
2223
2224	/** Profiling the R0/RC regular access handler. */
2225	STAMPROFILE StatMonitorRZ;
2226	/** Profiling the pgmPoolFlushPage calls made from the regular access handler in R0/RC. */
2227	STAMPROFILE StatMonitorRZFlushPage;
2228	/** Per access size counts indexed by size minus 1, last for larger. */
2229	STAMCOUNTER aStatMonitorRZSizes[16+3];
2230	/** Missaligned access counts indexed by offset - 1. */
2231	STAMCOUNTER aStatMonitorRZMisaligned[7];
2232
2233	/** Nr of handled PT faults. */
2234	STAMCOUNTER StatMonitorRZFaultPT;
2235	/** Nr of handled PD faults. */
2236	STAMCOUNTER StatMonitorRZFaultPD;
2237	/** Nr of handled PDPT faults. */
2238	STAMCOUNTER StatMonitorRZFaultPDPT;
2239	/** Nr of handled PML4 faults. */
2240	STAMCOUNTER StatMonitorRZFaultPML4;
2241
2242	/** Profiling the R3 access handler. */
2243	STAMPROFILE StatMonitorR3;
2244	/** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2245	STAMPROFILE StatMonitorR3FlushPage;
2246	/** Per access size counts indexed by size minus 1, last for larger. */
2247	STAMCOUNTER aStatMonitorR3Sizes[16+3];
2248	/** Missaligned access counts indexed by offset - 1. */
2249	STAMCOUNTER aStatMonitorR3Misaligned[7];
2250	/** Nr of handled PT faults. */
2251	STAMCOUNTER StatMonitorR3FaultPT;
2252	/** Nr of handled PD faults. */
2253	STAMCOUNTER StatMonitorR3FaultPD;
2254	/** Nr of handled PDPT faults. */
2255	STAMCOUNTER StatMonitorR3FaultPDPT;
2256	/** Nr of handled PML4 faults. */
2257	STAMCOUNTER StatMonitorR3FaultPML4;
2258
2259	/** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2260	STAMCOUNTER StatResetDirtyPages;
2261	/** Times we've called pgmPoolAddDirtyPage. */
2262	STAMCOUNTER StatDirtyPage;
2263	/** Times we've had to flush duplicates for dirty page management. */
2264	STAMCOUNTER StatDirtyPageDupFlush;
2265	/** Times we've had to flush because of overflow. */
2266	STAMCOUNTER StatDirtyPageOverFlowFlush;
2267
2268	/** The high water mark for cModifiedPages. */
2269	uint16_t cModifiedPagesHigh;
2270	uint16_t Alignment2[3]; /*< Align the next member on a 64-bit boundary. /
2271
2272	/** The number of cache hits. */
2273	STAMCOUNTER StatCacheHits;
2274	/** The number of cache misses. */
2275	STAMCOUNTER StatCacheMisses;
2276	/** The number of times we've got a conflict of 'kind' in the cache. */
2277	STAMCOUNTER StatCacheKindMismatches;
2278	/** Number of times we've been out of pages. */
2279	STAMCOUNTER StatCacheFreeUpOne;
2280	/** The number of cacheable allocations. */
2281	STAMCOUNTER StatCacheCacheable;
2282	/** The number of uncacheable allocations. */
2283	STAMCOUNTER StatCacheUncacheable;
2284	#else
2285	uint32_t Alignment3; /*< Align the next member on a 64-bit boundary. /
2286	#endif
2287	/** Profiling PGMR0PoolGrow(). */
2288	STAMPROFILE StatGrow;
2289	/** The AVL tree for looking up a page by its HC physical address. */
2290	AVLOHCPHYSTREE HCPhysTree;
2291	uint32_t Alignment4; /*< Align the next member on a 64-bit boundary. /
2292	/** Array of pages. (cMaxPages in length)
2293	* The Id is the index into thist array.
2294	*/
2295	PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2296	} PGMPOOL, PPGMPOOL, *PPPGMPOOL;
2297	AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2298	AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2299	AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2300	#ifdef VBOX_WITH_STATISTICS
2301	AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2302	#endif
2303	AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2304
2305
2306	/** @def PGMPOOL_PAGE_2_PTR
2307	* Maps a pool page pool into the current context.
2308	*
2309	* @returns VBox status code.
2310	* @param a_pVM Pointer to the VM.
2311	* @param a_pPage The pool page.
2312	*
2313	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2314	* small page window employeed by that function. Be careful.
2315	* @remark There is no need to assert on the result.
2316	*/
2317	#if defined(VBOX_STRICT) \|\| 1 /* temporarily going strict here */
2318	# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageStrict(a_pPage, __FUNCTION__)
2319	DECLINLINE(void ) pgmPoolMapPageStrict(PPGMPOOLPAGE a_pPage, const char pszCaller)
2320	{
2321	RT_NOREF(pszCaller);
2322	AssertPtr(a_pPage);
2323	AssertMsg(RT_VALID_PTR(a_pPage->CTX_SUFF(pvPage)),
2324	("enmKind=%d idx=%#x HCPhys=%RHp GCPhys=%RGp pvPageR3=%p pvPageR0=%p caller=%s\n",
2325	a_pPage->enmKind, a_pPage->idx, a_pPage->Core.Key, a_pPage->GCPhys, a_pPage->pvPageR3, a_pPage->pvPageR0, pszCaller));
2326	return a_pPage->CTX_SUFF(pvPage);
2327	}
2328	#else
2329	# define PGMPOOL_PAGE_2_PTR(pVM, a_pPage) ((a_pPage)->CTX_SUFF(pvPage))
2330	#endif
2331
2332
2333	/** @def PGMPOOL_PAGE_2_PTR_V2
2334	* Maps a pool page pool into the current context, taking both VM and VMCPU.
2335	*
2336	* @returns VBox status code.
2337	* @param a_pVM Pointer to the VM.
2338	* @param a_pVCpu The current CPU.
2339	* @param a_pPage The pool page.
2340	*
2341	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2342	* small page window employeed by that function. Be careful.
2343	* @remark There is no need to assert on the result.
2344	*/
2345	#define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) PGMPOOL_PAGE_2_PTR((a_pVM), (a_pPage))
2346
2347
2348	/** @def PGMPOOL_PAGE_IS_NESTED
2349	* Checks whether the given pool page is a nested-guest pool page.
2350	*
2351	* @returns @c true if a nested-guest pool page, @c false otherwise.
2352	* @param a_pPage The pool page.
2353	* @todo We can optimize the conditionals later.
2354	*/
2355	#define PGMPOOL_PAGE_IS_NESTED(a_pPage) PGMPOOL_PAGE_IS_KIND_NESTED((a_pPage)->enmKind)
2356	#define PGMPOOL_PAGE_IS_KIND_NESTED(a_enmKind) ( (a_enmKind) == PGMPOOLKIND_EPT_PT_FOR_EPT_PT \
2357	\|\| (a_enmKind) == PGMPOOLKIND_EPT_PT_FOR_EPT_2MB \
2358	\|\| (a_enmKind) == PGMPOOLKIND_EPT_PD_FOR_EPT_PD \
2359	\|\| (a_enmKind) == PGMPOOLKIND_EPT_PDPT_FOR_EPT_PDPT \
2360	\|\| (a_enmKind) == PGMPOOLKIND_EPT_PML4_FOR_EPT_PML4)
2361
2362	/** @name Per guest page tracking data.
2363	* This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2364	* is to use more bits for it and split it up later on. But for now we'll play
2365	* safe and change as little as possible.
2366	*
2367	* The 16-bit word has two parts:
2368	*
2369	* The first 14-bit forms the @a idx field. It is either the index of a page in
2370	* the shadow page pool, or and index into the extent list.
2371	*
2372	* The 2 topmost bits makes up the @a cRefs field, which counts the number of
2373	* shadow page pool references to the page. If cRefs equals
2374	* PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2375	* (misnomer) table and not the shadow page pool.
2376	*
2377	* See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2378	* the 16-bit word.
2379	*
2380	* @{ */
2381	/** The shift count for getting to the cRefs part. */
2382	#define PGMPOOL_TD_CREFS_SHIFT 14
2383	/** The mask applied after shifting the tracking data down by
2384	* PGMPOOL_TD_CREFS_SHIFT. */
2385	#define PGMPOOL_TD_CREFS_MASK 0x3
2386	/** The cRefs value used to indicate that the idx is the head of a
2387	* physical cross reference list. */
2388	#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2389	/** The shift used to get idx. */
2390	#define PGMPOOL_TD_IDX_SHIFT 0
2391	/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2392	#define PGMPOOL_TD_IDX_MASK 0x3fff
2393	/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2394	* simply too many mappings of this page. */
2395	#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2396
2397	/** @def PGMPOOL_TD_MAKE
2398	* Makes a 16-bit tracking data word.
2399	*
2400	* @returns tracking data.
2401	* @param cRefs The @a cRefs field. Must be within bounds!
2402	* @param idx The @a idx field. Must also be within bounds! */
2403	#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) \| (idx) )
2404
2405	/** @def PGMPOOL_TD_GET_CREFS
2406	* Get the @a cRefs field from a tracking data word.
2407	*
2408	* @returns The @a cRefs field
2409	* @param u16 The tracking data word.
2410	* @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2411	* non-zero @a u16. */
2412	#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2413
2414	/** @def PGMPOOL_TD_GET_IDX
2415	* Get the @a idx field from a tracking data word.
2416	*
2417	* @returns The @a idx field
2418	* @param u16 The tracking data word. */
2419	#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2420	/** @} */
2421
2422
2423
2424	/** @name A20 gate macros
2425	* @{ */
2426	#define PGM_WITH_A20
2427	#ifdef PGM_WITH_A20
2428	# define PGM_A20_IS_ENABLED(a_pVCpu) ((a_pVCpu)->pgm.s.fA20Enabled)
2429	# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) ((a_GCPhys) & (a_pVCpu)->pgm.s.GCPhysA20Mask)
2430	# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) \
2431	do { a_GCPhysVar &= (a_pVCpu)->pgm.s.GCPhysA20Mask; } while (0)
2432	# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) Assert(PGM_A20_APPLY(pVCpu, a_GCPhys) == (a_GCPhys))
2433	#else
2434	# define PGM_A20_IS_ENABLED(a_pVCpu) (true)
2435	# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) (a_GCPhys)
2436	# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) do { } while (0)
2437	# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) do { } while (0)
2438	#endif
2439	/** @} */
2440
2441
2442	/**
2443	* Guest page table walk for the AMD64 mode.
2444	*/
2445	typedef struct PGMPTWALKGSTAMD64
2446	{
2447	PX86PML4 pPml4;
2448	PX86PML4E pPml4e;
2449	X86PML4E Pml4e;
2450
2451	PX86PDPT pPdpt;
2452	PX86PDPE pPdpe;
2453	X86PDPE Pdpe;
2454
2455	PX86PDPAE pPd;
2456	PX86PDEPAE pPde;
2457	X86PDEPAE Pde;
2458
2459	PX86PTPAE pPt;
2460	PX86PTEPAE pPte;
2461	X86PTEPAE Pte;
2462	} PGMPTWALKGSTAMD64;
2463	/** Pointer to a AMD64 guest page table walk. */
2464	typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2465	/** Pointer to a const AMD64 guest page table walk. */
2466	typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2467
2468	/**
2469	* Guest page table walk for the EPT mode.
2470	*/
2471	typedef struct PGMPTWALKGSTEPT
2472	{
2473	PEPTPML4 pPml4;
2474	PEPTPML4E pPml4e;
2475	EPTPML4E Pml4e;
2476
2477	PEPTPDPT pPdpt;
2478	PEPTPDPTE pPdpte;
2479	EPTPDPTE Pdpte;
2480
2481	PEPTPD pPd;
2482	PEPTPDE pPde;
2483	EPTPDE Pde;
2484
2485	PEPTPT pPt;
2486	PEPTPTE pPte;
2487	EPTPTE Pte;
2488	} PGMPTWALKGSTEPT;
2489	/** Pointer to an EPT guest page table walk. */
2490	typedef PGMPTWALKGSTEPT *PPGMPTWALKGSTEPT;
2491	/** Pointer to a const EPT guest page table walk. */
2492	typedef PGMPTWALKGSTEPT const *PCPGMPTWALKGSTEPT;
2493
2494	/**
2495	* Guest page table walk for the PAE mode.
2496	*/
2497	typedef struct PGMPTWALKGSTPAE
2498	{
2499	PX86PDPT pPdpt;
2500	PX86PDPE pPdpe;
2501	X86PDPE Pdpe;
2502
2503	PX86PDPAE pPd;
2504	PX86PDEPAE pPde;
2505	X86PDEPAE Pde;
2506
2507	PX86PTPAE pPt;
2508	PX86PTEPAE pPte;
2509	X86PTEPAE Pte;
2510	} PGMPTWALKGSTPAE;
2511	/** Pointer to a PAE guest page table walk. */
2512	typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2513	/** Pointer to a const AMD64 guest page table walk. */
2514	typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2515
2516	/**
2517	* Guest page table walk for the 32-bit mode.
2518	*/
2519	typedef struct PGMPTWALKGST32BIT
2520	{
2521	PX86PD pPd;
2522	PX86PDE pPde;
2523	X86PDE Pde;
2524
2525	PX86PT pPt;
2526	PX86PTE pPte;
2527	X86PTE Pte;
2528	} PGMPTWALKGST32BIT;
2529	/** Pointer to a 32-bit guest page table walk. */
2530	typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2531	/** Pointer to a const 32-bit guest page table walk. */
2532	typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2533
2534	/**
2535	* Which part of PGMPTWALKGST that is valid.
2536	*/
2537	typedef enum PGMPTWALKGSTTYPE
2538	{
2539	/** Customary invalid 0 value. */
2540	PGMPTWALKGSTTYPE_INVALID = 0,
2541	/** PGMPTWALKGST::u.Amd64 is valid. */
2542	PGMPTWALKGSTTYPE_AMD64,
2543	/** PGMPTWALKGST::u.Pae is valid. */
2544	PGMPTWALKGSTTYPE_PAE,
2545	/** PGMPTWALKGST::u.Legacy is valid. */
2546	PGMPTWALKGSTTYPE_32BIT,
2547	/** PGMPTWALKGST::u.Ept is valid. */
2548	PGMPTWALKGSTTYPE_EPT,
2549	/** Customary 32-bit type hack. */
2550	PGMPTWALKGSTTYPE_32BIT_HACK = 0x7fff0000
2551	} PGMPTWALKGSTTYPE;
2552
2553	/**
2554	* Combined guest page table walk result.
2555	*/
2556	typedef struct PGMPTWALKGST
2557	{
2558	union
2559	{
2560	/** The page walker for AMD64. */
2561	PGMPTWALKGSTAMD64 Amd64;
2562	/** The page walker for PAE (32-bit). */
2563	PGMPTWALKGSTPAE Pae;
2564	/** The page walker for 32-bit paging (called legacy due to C naming
2565	* convension). */
2566	PGMPTWALKGST32BIT Legacy;
2567	/** The page walker for EPT (SLAT). */
2568	PGMPTWALKGSTEPT Ept;
2569	} u;
2570	/** Indicates which part of the union is valid. */
2571	PGMPTWALKGSTTYPE enmType;
2572	} PGMPTWALKGST;
2573	/** Pointer to a combined guest page table walk result. */
2574	typedef PGMPTWALKGST *PPGMPTWALKGST;
2575	/** Pointer to a read-only combined guest page table walk result. */
2576	typedef PGMPTWALKGST const *PCPGMPTWALKGST;
2577
2578
2579	/** @name Paging mode macros
2580	* @{
2581	*/
2582	#ifdef IN_RING3
2583	# define PGM_CTX(a,b) a##R3##b
2584	# define PGM_CTX_STR(a,b) a "R3" b
2585	# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2586	#elif defined(IN_RING0)
2587	# define PGM_CTX(a,b) a##R0##b
2588	# define PGM_CTX_STR(a,b) a "R0" b
2589	# define PGM_CTX_DECL(type) VMMDECL(type)
2590	#else
2591	# error "Not IN_RING3 or IN_RING0!"
2592	#endif
2593
2594	#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2595	#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2596	#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2597	#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2598	#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2599	#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2600	#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2601	#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2602	#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2603	#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2604	#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2605	#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2606	#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2607	#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2608	#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2609	#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2610
2611	#define PGM_GST_SLAT_NAME_EPT(name) PGM_CTX(pgm,GstSlatEpt##name)
2612	#define PGM_GST_SLAT_NAME_RC_EPT_STR(name) "pgmRCGstSlatEpt" #name
2613	#define PGM_GST_SLAT_NAME_R0_EPT_STR(name) "pgmR0GstSlatEpt" #name
2614	#define PGM_GST_SLAT_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_SLAT_NAME(name)
2615
2616	#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2617	#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2618	#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2619	#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2620	#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2621	#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2622	#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2623	#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2624	#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2625	#define PGM_SHW_NAME_NESTED_32BIT(name) PGM_CTX(pgm,ShwNested32Bit##name)
2626	#define PGM_SHW_NAME_RC_NESTED_32BIT_STR(name) "pgmRCShwNested32Bit" #name
2627	#define PGM_SHW_NAME_R0_NESTED_32BIT_STR(name) "pgmR0ShwNested32Bit" #name
2628	#define PGM_SHW_NAME_NESTED_PAE(name) PGM_CTX(pgm,ShwNestedPAE##name)
2629	#define PGM_SHW_NAME_RC_NESTED_PAE_STR(name) "pgmRCShwNestedPAE" #name
2630	#define PGM_SHW_NAME_R0_NESTED_PAE_STR(name) "pgmR0ShwNestedPAE" #name
2631	#define PGM_SHW_NAME_NESTED_AMD64(name) PGM_CTX(pgm,ShwNestedAMD64##name)
2632	#define PGM_SHW_NAME_RC_NESTED_AMD64_STR(name) "pgmRCShwNestedAMD64" #name
2633	#define PGM_SHW_NAME_R0_NESTED_AMD64_STR(name) "pgmR0ShwNestedAMD64" #name
2634	#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2635	#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2636	#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2637	#define PGM_SHW_NAME_NONE(name) PGM_CTX(pgm,ShwNone##name)
2638	#define PGM_SHW_NAME_RC_NONE_STR(name) "pgmRCShwNone" #name
2639	#define PGM_SHW_NAME_R0_NONE_STR(name) "pgmR0ShwNone" #name
2640	#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2641
2642	/* Shw_Gst */
2643	#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2644	#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2645	#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2646	#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2647	#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2648	#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2649	#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2650	#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2651	#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2652	#define PGM_BTH_NAME_NESTED_32BIT_REAL(name) PGM_CTX(pgm,BthNested32BitReal##name)
2653	#define PGM_BTH_NAME_NESTED_32BIT_PROT(name) PGM_CTX(pgm,BthNested32BitProt##name)
2654	#define PGM_BTH_NAME_NESTED_32BIT_32BIT(name) PGM_CTX(pgm,BthNested32Bit32Bit##name)
2655	#define PGM_BTH_NAME_NESTED_32BIT_PAE(name) PGM_CTX(pgm,BthNested32BitPAE##name)
2656	#define PGM_BTH_NAME_NESTED_32BIT_AMD64(name) PGM_CTX(pgm,BthNested32BitAMD64##name)
2657	#define PGM_BTH_NAME_NESTED_PAE_REAL(name) PGM_CTX(pgm,BthNestedPAEReal##name)
2658	#define PGM_BTH_NAME_NESTED_PAE_PROT(name) PGM_CTX(pgm,BthNestedPAEProt##name)
2659	#define PGM_BTH_NAME_NESTED_PAE_32BIT(name) PGM_CTX(pgm,BthNestedPAE32Bit##name)
2660	#define PGM_BTH_NAME_NESTED_PAE_PAE(name) PGM_CTX(pgm,BthNestedPAEPAE##name)
2661	#define PGM_BTH_NAME_NESTED_PAE_AMD64(name) PGM_CTX(pgm,BthNestedPAEAMD64##name)
2662	#define PGM_BTH_NAME_NESTED_AMD64_REAL(name) PGM_CTX(pgm,BthNestedAMD64Real##name)
2663	#define PGM_BTH_NAME_NESTED_AMD64_PROT(name) PGM_CTX(pgm,BthNestedAMD64Prot##name)
2664	#define PGM_BTH_NAME_NESTED_AMD64_32BIT(name) PGM_CTX(pgm,BthNestedAMD6432Bit##name)
2665	#define PGM_BTH_NAME_NESTED_AMD64_PAE(name) PGM_CTX(pgm,BthNestedAMD64PAE##name)
2666	#define PGM_BTH_NAME_NESTED_AMD64_AMD64(name) PGM_CTX(pgm,BthNestedAMD64AMD64##name)
2667	#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2668	#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2669	#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2670	#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2671	#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2672	#define PGM_BTH_NAME_NONE_REAL(name) PGM_CTX(pgm,BthNoneReal##name)
2673	#define PGM_BTH_NAME_NONE_PROT(name) PGM_CTX(pgm,BthNoneProt##name)
2674	#define PGM_BTH_NAME_NONE_32BIT(name) PGM_CTX(pgm,BthNone32Bit##name)
2675	#define PGM_BTH_NAME_NONE_PAE(name) PGM_CTX(pgm,BthNonePAE##name)
2676	#define PGM_BTH_NAME_NONE_AMD64(name) PGM_CTX(pgm,BthNoneAMD64##name)
2677
2678	#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2679	#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2680	#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2681	#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2682	#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2683	#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2684	#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2685	#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2686	#define PGM_BTH_NAME_RC_NESTED_32BIT_REAL_STR(name) "pgmRCBthNested32BitReal" #name
2687	#define PGM_BTH_NAME_RC_NESTED_32BIT_PROT_STR(name) "pgmRCBthNested32BitProt" #name
2688	#define PGM_BTH_NAME_RC_NESTED_32BIT_32BIT_STR(name) "pgmRCBthNested32Bit32Bit" #name
2689	#define PGM_BTH_NAME_RC_NESTED_32BIT_PAE_STR(name) "pgmRCBthNested32BitPAE" #name
2690	#define PGM_BTH_NAME_RC_NESTED_32BIT_AMD64_STR(name) "pgmRCBthNested32BitAMD64" #name
2691	#define PGM_BTH_NAME_RC_NESTED_PAE_REAL_STR(name) "pgmRCBthNestedPAEReal" #name
2692	#define PGM_BTH_NAME_RC_NESTED_PAE_PROT_STR(name) "pgmRCBthNestedPAEProt" #name
2693	#define PGM_BTH_NAME_RC_NESTED_PAE_32BIT_STR(name) "pgmRCBthNestedPAE32Bit" #name
2694	#define PGM_BTH_NAME_RC_NESTED_PAE_PAE_STR(name) "pgmRCBthNestedPAEPAE" #name
2695	#define PGM_BTH_NAME_RC_NESTED_PAE_AMD64_STR(name) "pgmRCBthNestedPAEAMD64" #name
2696	#define PGM_BTH_NAME_RC_NESTED_AMD64_REAL_STR(name) "pgmRCBthNestedAMD64Real" #name
2697	#define PGM_BTH_NAME_RC_NESTED_AMD64_PROT_STR(name) "pgmRCBthNestedAMD64Prot" #name
2698	#define PGM_BTH_NAME_RC_NESTED_AMD64_32BIT_STR(name) "pgmRCBthNestedAMD6432Bit" #name
2699	#define PGM_BTH_NAME_RC_NESTED_AMD64_PAE_STR(name) "pgmRCBthNestedAMD64PAE" #name
2700	#define PGM_BTH_NAME_RC_NESTED_AMD64_AMD64_STR(name) "pgmRCBthNestedAMD64AMD64" #name
2701	#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2702	#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2703	#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2704	#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2705	#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2706
2707	#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2708	#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2709	#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2710	#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2711	#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2712	#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2713	#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2714	#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2715	#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2716	#define PGM_BTH_NAME_R0_NESTED_32BIT_REAL_STR(name) "pgmR0BthNested32BitReal" #name
2717	#define PGM_BTH_NAME_R0_NESTED_32BIT_PROT_STR(name) "pgmR0BthNested32BitProt" #name
2718	#define PGM_BTH_NAME_R0_NESTED_32BIT_32BIT_STR(name) "pgmR0BthNested32Bit32Bit" #name
2719	#define PGM_BTH_NAME_R0_NESTED_32BIT_PAE_STR(name) "pgmR0BthNested32BitPAE" #name
2720	#define PGM_BTH_NAME_R0_NESTED_32BIT_AMD64_STR(name) "pgmR0BthNested32BitAMD64" #name
2721	#define PGM_BTH_NAME_R0_NESTED_PAE_REAL_STR(name) "pgmR0BthNestedPAEReal" #name
2722	#define PGM_BTH_NAME_R0_NESTED_PAE_PROT_STR(name) "pgmR0BthNestedPAEProt" #name
2723	#define PGM_BTH_NAME_R0_NESTED_PAE_32BIT_STR(name) "pgmR0BthNestedPAE32Bit" #name
2724	#define PGM_BTH_NAME_R0_NESTED_PAE_PAE_STR(name) "pgmR0BthNestedPAEPAE" #name
2725	#define PGM_BTH_NAME_R0_NESTED_PAE_AMD64_STR(name) "pgmR0BthNestedPAEAMD64" #name
2726	#define PGM_BTH_NAME_R0_NESTED_AMD64_REAL_STR(name) "pgmR0BthNestedAMD64Real" #name
2727	#define PGM_BTH_NAME_R0_NESTED_AMD64_PROT_STR(name) "pgmR0BthNestedAMD64Prot" #name
2728	#define PGM_BTH_NAME_R0_NESTED_AMD64_32BIT_STR(name) "pgmR0BthNestedAMD6432Bit" #name
2729	#define PGM_BTH_NAME_R0_NESTED_AMD64_PAE_STR(name) "pgmR0BthNestedAMD64PAE" #name
2730	#define PGM_BTH_NAME_R0_NESTED_AMD64_AMD64_STR(name) "pgmR0BthNestedAMD64AMD64" #name
2731	#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2732	#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2733	#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2734	#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2735	#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2736
2737	#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2738	/** @} */
2739
2740
2741	/**
2742	* Function pointers for guest paging.
2743	*/
2744	typedef struct PGMMODEDATAGST
2745	{
2746	/** The guest mode type. */
2747	uint32_t uType;
2748	DECLCALLBACKMEMBER(int, pfnGetPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk));
2749	DECLCALLBACKMEMBER(int, pfnModifyPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2750	DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2751	DECLCALLBACKMEMBER(int, pfnExit,(PVMCPUCC pVCpu));
2752	#ifdef IN_RING3
2753	DECLCALLBACKMEMBER(int, pfnRelocate,(PVMCPUCC pVCpu, RTGCPTR offDelta)); /*< Only in ring-3. /
2754	#endif
2755	} PGMMODEDATAGST;
2756
2757	/** The length of g_aPgmGuestModeData. */
2758	#if VBOX_WITH_64_BITS_GUESTS
2759	# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_AMD64 + 1)
2760	#else
2761	# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_PAE + 1)
2762	#endif
2763	/** The guest mode data array. */
2764	extern PGMMODEDATAGST const g_aPgmGuestModeData[PGM_GUEST_MODE_DATA_ARRAY_SIZE];
2765
2766
2767	/**
2768	* Function pointers for shadow paging.
2769	*/
2770	typedef struct PGMMODEDATASHW
2771	{
2772	/** The shadow mode type. */
2773	uint32_t uType;
2774	DECLCALLBACKMEMBER(int, pfnGetPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2775	DECLCALLBACKMEMBER(int, pfnModifyPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags,
2776	uint64_t fMask, uint32_t fOpFlags));
2777	DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu));
2778	DECLCALLBACKMEMBER(int, pfnExit,(PVMCPUCC pVCpu));
2779	#ifdef IN_RING3
2780	DECLCALLBACKMEMBER(int, pfnRelocate,(PVMCPUCC pVCpu, RTGCPTR offDelta)); /*< Only in ring-3. /
2781	#endif
2782	} PGMMODEDATASHW;
2783
2784	/** The length of g_aPgmShadowModeData. */
2785	#define PGM_SHADOW_MODE_DATA_ARRAY_SIZE PGM_TYPE_END
2786	/** The shadow mode data array. */
2787	extern PGMMODEDATASHW const g_aPgmShadowModeData[PGM_SHADOW_MODE_DATA_ARRAY_SIZE];
2788
2789
2790	/**
2791	* Function pointers for guest+shadow paging.
2792	*/
2793	typedef struct PGMMODEDATABTH
2794	{
2795	/** The shadow mode type. */
2796	uint32_t uShwType;
2797	/** The guest mode type. */
2798	uint32_t uGstType;
2799
2800	DECLCALLBACKMEMBER(int, pfnInvalidatePage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage));
2801	DECLCALLBACKMEMBER(int, pfnSyncCR3,(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2802	DECLCALLBACKMEMBER(int, pfnPrefetchPage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage));
2803	DECLCALLBACKMEMBER(int, pfnVerifyAccessSyncPage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2804	DECLCALLBACKMEMBER(int, pfnMapCR3,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2805	DECLCALLBACKMEMBER(int, pfnUnmapCR3,(PVMCPUCC pVCpu));
2806	DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2807	#ifndef IN_RING3
2808	DECLCALLBACKMEMBER(int, pfnTrap0eHandler,(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPTR pvFault, bool *pfLockTaken));
2809	DECLCALLBACKMEMBER(int, pfnNestedTrap0eHandler,(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPHYS GCPhysNested,
2810	bool fIsLinearAddrValid, RTGCPTR GCPtrNested, PPGMPTWALK pWalk,
2811	bool *pfLockTaken));
2812	#endif
2813	#ifdef VBOX_STRICT
2814	DECLCALLBACKMEMBER(unsigned, pfnAssertCR3,(PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2815	#endif
2816	} PGMMODEDATABTH;
2817
2818	/** The length of g_aPgmBothModeData. */
2819	#define PGM_BOTH_MODE_DATA_ARRAY_SIZE ((PGM_TYPE_END - PGM_TYPE_FIRST_SHADOW) * PGM_TYPE_END)
2820	/** The guest+shadow mode data array. */
2821	extern PGMMODEDATABTH const g_aPgmBothModeData[PGM_BOTH_MODE_DATA_ARRAY_SIZE];
2822
2823
2824	#ifdef VBOX_WITH_STATISTICS
2825	/**
2826	* PGM statistics.
2827	*/
2828	typedef struct PGMSTATS
2829	{
2830	/* R3 only: */
2831	STAMCOUNTER StatR3DetectedConflicts; /*< R3: Number of times PGMR3MapHasConflicts() detected a conflict. /
2832	STAMPROFILE StatR3ResolveConflict; /*< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). /
2833
2834	/* R3+RZ */
2835	STAMCOUNTER StatRZChunkR3MapTlbHits; /*< RC/R0: Ring-3/0 chunk mapper TLB hits. /
2836	STAMCOUNTER StatRZChunkR3MapTlbMisses; /*< RC/R0: Ring-3/0 chunk mapper TLB misses. /
2837	STAMCOUNTER StatRZPageMapTlbHits; /*< RC/R0: Ring-3/0 page mapper TLB hits. /
2838	STAMCOUNTER StatRZPageMapTlbMisses; /*< RC/R0: Ring-3/0 page mapper TLB misses. /
2839	STAMCOUNTER StatPageMapTlbFlushes; /*< ALL: Ring-3/0 page mapper TLB flushes. /
2840	STAMCOUNTER StatPageMapTlbFlushEntry; /*< ALL: Ring-3/0 page mapper TLB flushes. /
2841	STAMCOUNTER StatR3ChunkR3MapTlbHits; /*< R3: Ring-3/0 chunk mapper TLB hits. /
2842	STAMCOUNTER StatR3ChunkR3MapTlbMisses; /*< R3: Ring-3/0 chunk mapper TLB misses. /
2843	STAMCOUNTER StatR3PageMapTlbHits; /*< R3: Ring-3/0 page mapper TLB hits. /
2844	STAMCOUNTER StatR3PageMapTlbMisses; /*< R3: Ring-3/0 page mapper TLB misses. /
2845	STAMCOUNTER StatRZRamRangeTlbHits; /*< RC/R0: RAM range TLB hits. /
2846	STAMCOUNTER StatRZRamRangeTlbMisses; /*< RC/R0: RAM range TLB misses. /
2847	STAMCOUNTER StatR3RamRangeTlbHits; /*< R3: RAM range TLB hits. /
2848	STAMCOUNTER StatR3RamRangeTlbMisses; /*< R3: RAM range TLB misses. /
2849	STAMCOUNTER StatR3PhysHandlerReset; /*< R3: The number of times PGMHandlerPhysicalReset is called. /
2850	STAMCOUNTER StatRZPhysHandlerReset; /*< RC/R0: The number of times PGMHandlerPhysicalReset is called. /
2851	STAMCOUNTER StatR3PhysHandlerLookupHits; /*< R3: Number of cache hits when looking up physical handlers. /
2852	STAMCOUNTER StatR3PhysHandlerLookupMisses; /*< R3: Number of cache misses when looking up physical handlers. /
2853	STAMCOUNTER StatRZPhysHandlerLookupHits; /*< RC/R0: Number of cache hits when lookup up physical handlers. /
2854	STAMCOUNTER StatRZPhysHandlerLookupMisses; /*< RC/R0: Number of cache misses when looking up physical handlers /
2855	STAMCOUNTER StatRZPageReplaceShared; /*< RC/R0: Times a shared page has been replaced by a private one. /
2856	STAMCOUNTER StatRZPageReplaceZero; /*< RC/R0: Times the zero page has been replaced by a private one. /
2857	/// @todo STAMCOUNTER StatRZPageHandyAllocs; /*< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. /
2858	STAMCOUNTER StatR3PageReplaceShared; /*< R3: Times a shared page has been replaced by a private one. /
2859	STAMCOUNTER StatR3PageReplaceZero; /*< R3: Times the zero page has been replaced by a private one. /
2860	/// @todo STAMCOUNTER StatR3PageHandyAllocs; /*< R3: The number of times we've executed GMMR3AllocateHandyPages. /
2861
2862	/* RC only: */
2863	STAMCOUNTER StatRCInvlPgConflict; /*< RC: Number of times PGMInvalidatePage() detected a mapping conflict. /
2864	STAMCOUNTER StatRCInvlPgSyncMonCR3; /*< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. /
2865
2866	STAMCOUNTER StatRZPhysRead;
2867	STAMCOUNTER StatRZPhysReadBytes;
2868	STAMCOUNTER StatRZPhysWrite;
2869	STAMCOUNTER StatRZPhysWriteBytes;
2870	STAMCOUNTER StatR3PhysRead;
2871	STAMCOUNTER StatR3PhysReadBytes;
2872	STAMCOUNTER StatR3PhysWrite;
2873	STAMCOUNTER StatR3PhysWriteBytes;
2874	STAMCOUNTER StatRCPhysRead;
2875	STAMCOUNTER StatRCPhysReadBytes;
2876	STAMCOUNTER StatRCPhysWrite;
2877	STAMCOUNTER StatRCPhysWriteBytes;
2878
2879	STAMCOUNTER StatRZPhysSimpleRead;
2880	STAMCOUNTER StatRZPhysSimpleReadBytes;
2881	STAMCOUNTER StatRZPhysSimpleWrite;
2882	STAMCOUNTER StatRZPhysSimpleWriteBytes;
2883	STAMCOUNTER StatR3PhysSimpleRead;
2884	STAMCOUNTER StatR3PhysSimpleReadBytes;
2885	STAMCOUNTER StatR3PhysSimpleWrite;
2886	STAMCOUNTER StatR3PhysSimpleWriteBytes;
2887	STAMCOUNTER StatRCPhysSimpleRead;
2888	STAMCOUNTER StatRCPhysSimpleReadBytes;
2889	STAMCOUNTER StatRCPhysSimpleWrite;
2890	STAMCOUNTER StatRCPhysSimpleWriteBytes;
2891
2892	STAMCOUNTER StatTrackVirgin; /*< The number of first time shadowings. /
2893	STAMCOUNTER StatTrackAliased; /*< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. /
2894	STAMCOUNTER StatTrackAliasedMany; /*< The number of times we're tracking using cRef2. /
2895	STAMCOUNTER StatTrackAliasedLots; /*< The number of times we're hitting pages which has overflowed cRef2. /
2896	STAMCOUNTER StatTrackNoExtentsLeft; /*< The number of times the extent list was exhausted. /
2897	STAMCOUNTER StatTrackOverflows; /*< The number of times the extent list grows to long. /
2898	STAMPROFILE StatTrackDeref; /*< Profiling of SyncPageWorkerTrackDeref (expensive). /
2899
2900	STAMPROFILE StatLargePageAlloc2; /*< Time spent setting up newly allocated large pages. /
2901	STAMPROFILE StatLargePageSetup; /*< Time spent setting up newly allocated large pages. /
2902	/** pgmPhysIsValidLargePage profiling - R3 */
2903	STAMPROFILE StatR3IsValidLargePage;
2904	/** pgmPhysIsValidLargePage profiling - RZ*/
2905	STAMPROFILE StatRZIsValidLargePage;
2906
2907	STAMPROFILE StatChunkAging;
2908	STAMPROFILE StatChunkFindCandidate;
2909	STAMPROFILE StatChunkUnmap;
2910	STAMPROFILE StatChunkMap;
2911	} PGMSTATS;
2912	#endif /* VBOX_WITH_STATISTICS */
2913
2914
2915	/**
2916	* PGM Data (part of VM)
2917	*/
2918	typedef struct PGM
2919	{
2920	/** The zero page. */
2921	uint8_t abZeroPg[RT_MAX(HOST_PAGE_SIZE, GUEST_PAGE_SIZE)];
2922	/** The MMIO placeholder page. */
2923	uint8_t abMmioPg[RT_MAX(HOST_PAGE_SIZE, GUEST_PAGE_SIZE)];
2924
2925	/** @name The zero page (abPagePg).
2926	* @{ */
2927	/** The host physical address of the zero page. */
2928	RTHCPHYS HCPhysZeroPg;
2929	/** @}*/
2930
2931	/** @name The Invalid MMIO page (abMmioPg).
2932	* This page is filled with 0xfeedface.
2933	* @{ */
2934	/** The host physical address of the invalid MMIO page. */
2935	RTHCPHYS HCPhysMmioPg;
2936	/** The host pysical address of the invalid MMIO page plus all invalid
2937	* physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
2938	* @remarks Check fLessThan52PhysicalAddressBits before use. */
2939	RTHCPHYS HCPhysInvMmioPg;
2940	/** @} */
2941
2942	/** @cfgm{/RamPreAlloc, boolean, false}
2943	* Indicates whether the base RAM should all be allocated before starting
2944	* the VM (default), or if it should be allocated when first written to.
2945	*/
2946	bool fRamPreAlloc;
2947	#ifdef VBOX_WITH_PGM_NEM_MODE
2948	/** Set if we're operating in NEM memory mode.
2949	*
2950	* NEM mode implies that memory is allocated in big chunks for each RAM range
2951	* rather than on demand page by page. Memory is also not locked and PGM has
2952	* therefore no physical addresses for them. Page sharing is out of the
2953	* question. Ballooning depends on the native execution engine, but probably
2954	* pointless as well. */
2955	bool fNemMode;
2956	# define PGM_IS_IN_NEM_MODE(a_pVM) ((a_pVM)->pgm.s.fNemMode)
2957	#else
2958	# define PGM_IS_IN_NEM_MODE(a_pVM) (false)
2959	#endif
2960	/** Indicates whether write monitoring is currently in use.
2961	* This is used to prevent conflicts between live saving and page sharing
2962	* detection. */
2963	bool fPhysWriteMonitoringEngaged;
2964	/** Set if the CPU has less than 52-bit physical address width.
2965	* This is used */
2966	bool fLessThan52PhysicalAddressBits;
2967	/** Set when nested paging is active.
2968	* This is meant to save calls to HMIsNestedPagingActive and let the
2969	* compilers optimize the code better. Whether we use nested paging or
2970	* not is something we find out during VMM initialization and we won't
2971	* change this later on. */
2972	bool fNestedPaging;
2973	/** We're not in a state which permits writes to guest memory.
2974	* (Only used in strict builds.) */
2975	bool fNoMorePhysWrites;
2976	/** @cfgm{/PageFusionAllowed, boolean, false}
2977	* Whether page fusion is allowed. */
2978	bool fPageFusionAllowed;
2979	/** @cfgm{/PGM/PciPassThrough, boolean, false}
2980	* Whether PCI passthrough is enabled. */
2981	bool fPciPassthrough;
2982	/** The number of MMIO2 regions (serves as the next MMIO2 ID). */
2983	uint8_t cMmio2Regions;
2984	/** Restore original ROM page content when resetting after loading state.
2985	* The flag is set by pgmR3LoadRomRanges and cleared at reset. This
2986	* enables the VM to start using an updated ROM without requiring powering
2987	* down the VM, just rebooting or resetting it. */
2988	bool fRestoreRomPagesOnReset;
2989	/** Whether to automatically clear all RAM pages on reset. */
2990	bool fZeroRamPagesOnReset;
2991	/** Large page enabled flag. */
2992	bool fUseLargePages;
2993	/** Alignment padding. */
2994	#ifndef VBOX_WITH_PGM_NEM_MODE
2995	bool afAlignment3[1];
2996	#endif
2997	/** The host paging mode. (This is what SUPLib reports.) */
2998	SUPPAGINGMODE enmHostMode;
2999	bool afAlignment3b[2];
3000
3001	/** Generation ID for the RAM ranges. This member is incremented everytime
3002	* a RAM range is linked or unlinked. */
3003	uint32_t volatile idRamRangesGen;
3004
3005	/** Physical access handler type for ROM protection. */
3006	PGMPHYSHANDLERTYPE hRomPhysHandlerType;
3007	/** Physical access handler type for MMIO2 dirty page tracing. */
3008	PGMPHYSHANDLERTYPE hMmio2DirtyPhysHandlerType;
3009
3010	/** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
3011	RTGCPHYS GCPhys4MBPSEMask;
3012	/** Mask containing the invalid bits of a guest physical address.
3013	* @remarks this does not stop at bit 52. */
3014	RTGCPHYS GCPhysInvAddrMask;
3015
3016
3017	/** RAM range TLB for R3. */
3018	R3PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR3[PGM_RAMRANGE_TLB_ENTRIES];
3019	/** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
3020	* This is sorted by physical address and contains no overlapping ranges. */
3021	R3PTRTYPE(PPGMRAMRANGE) pRamRangesXR3;
3022	/** Root of the RAM range search tree for ring-3. */
3023	R3PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR3;
3024	/** Shadow Page Pool - R3 Ptr. */
3025	R3PTRTYPE(PPGMPOOL) pPoolR3;
3026	/** Pointer to the list of ROM ranges - for R3.
3027	* This is sorted by physical address and contains no overlapping ranges. */
3028	R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
3029	/** Pointer to the list of MMIO2 ranges - for R3.
3030	* Registration order. */
3031	R3PTRTYPE(PPGMREGMMIO2RANGE) pRegMmioRangesR3;
3032	/** MMIO2 lookup array for ring-3. Indexed by idMmio2 minus 1. */
3033	R3PTRTYPE(PPGMREGMMIO2RANGE) apMmio2RangesR3[PGM_MMIO2_MAX_RANGES];
3034
3035	/** RAM range TLB for R0. */
3036	R0PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR0[PGM_RAMRANGE_TLB_ENTRIES];
3037	/** R0 pointer corresponding to PGM::pRamRangesXR3. */
3038	R0PTRTYPE(PPGMRAMRANGE) pRamRangesXR0;
3039	/** Root of the RAM range search tree for ring-0. */
3040	R0PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR0;
3041	/** Shadow Page Pool - R0 Ptr. */
3042	R0PTRTYPE(PPGMPOOL) pPoolR0;
3043	/** R0 pointer corresponding to PGM::pRomRangesR3. */
3044	R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
3045	/** MMIO2 lookup array for ring-0. Indexed by idMmio2 minus 1. */
3046	R0PTRTYPE(PPGMREGMMIO2RANGE) apMmio2RangesR0[PGM_MMIO2_MAX_RANGES];
3047
3048	/** Hack: Number of deprecated page mapping locks taken by the current lock
3049	* owner via pgmPhysGCPhys2CCPtrInternalDepr. */
3050	uint32_t cDeprecatedPageLocks;
3051
3052	/** Registered physical access handler types. */
3053	uint32_t cPhysHandlerTypes;
3054	/** Physical access handler types.
3055	* Initialized to callback causing guru meditations and invalid enmKind. */
3056	PGMPHYSHANDLERTYPEINTR3 aPhysHandlerTypes[PGMPHYSHANDLERTYPE_COUNT];
3057	/** Physical handler allocator, ring-3 edition. */
3058	#ifdef IN_RING3
3059	PGMPHYSHANDLERALLOCATOR PhysHandlerAllocator;
3060	#else
3061	RTCHardAvlTreeSlabAllocatorR3_T PhysHandlerAllocator;
3062	#endif
3063	/** The pointer to the ring-3 mapping of the physical access handler tree. */
3064	R3PTRTYPE(PPGMPHYSHANDLERTREE) pPhysHandlerTree;
3065	/** Caching the last physical handler we looked. */
3066	uint32_t idxLastPhysHandler;
3067
3068	uint32_t au64Padding3[5];
3069
3070	/** PGM critical section.
3071	* This protects the physical, ram ranges, and the page flag updating (some of
3072	* it anyway).
3073	*/
3074	PDMCRITSECT CritSectX;
3075
3076	/**
3077	* Data associated with managing the ring-3 mappings of the allocation chunks.
3078	*/
3079	struct
3080	{
3081	/** The chunk mapping TLB. */
3082	PGMCHUNKR3MAPTLB Tlb;
3083	/** The chunk tree, ordered by chunk id. */
3084	R3PTRTYPE(PAVLU32NODECORE) pTree;
3085	#if HC_ARCH_BITS == 32
3086	uint32_t u32Alignment0;
3087	#endif
3088	/** The number of mapped chunks. */
3089	uint32_t c;
3090	/** @cfgm{/PGM/MaxRing3Chunks, uint32_t, host dependent}
3091	* The maximum number of mapped chunks. On 64-bit this is unlimited by default,
3092	* on 32-bit it defaults to 1 or 3 GB depending on the host. */
3093	uint32_t cMax;
3094	/** The current time. This is incremented whenever a chunk is inserted. */
3095	uint32_t iNow;
3096	/** Alignment padding. */
3097	uint32_t au32Alignment1[3];
3098	} ChunkR3Map;
3099
3100	/** The page mapping TLB for ring-3. */
3101	PGMPAGER3MAPTLB PhysTlbR3;
3102	/** The page mapping TLB for ring-0. */
3103	PGMPAGER0MAPTLB PhysTlbR0;
3104
3105	/** The number of handy pages. */
3106	uint32_t cHandyPages;
3107
3108	/** The number of large handy pages. */
3109	uint32_t cLargeHandyPages;
3110
3111	/**
3112	* Array of handy pages.
3113	*
3114	* This array is used in a two way communication between pgmPhysAllocPage
3115	* and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3116	* an intermediary.
3117	*
3118	* The size of this array is important, see pgmPhysEnsureHandyPage for details.
3119	* (The current size of 32 pages, means 128 KB of handy memory.)
3120	*/
3121	GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3122
3123	/**
3124	* Array of large handy pages. (currently size 1)
3125	*
3126	* This array is used in a two way communication between pgmPhysAllocLargePage
3127	* and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3128	* an intermediary.
3129	*/
3130	GMMPAGEDESC aLargeHandyPage[1];
3131	/** When to try allocate large pages again after a failure. */
3132	uint64_t nsLargePageRetry;
3133	/** Number of repeated long allocation times. */
3134	uint32_t cLargePageLongAllocRepeats;
3135	uint32_t uPadding5;
3136
3137	/**
3138	* Live save data.
3139	*/
3140	struct
3141	{
3142	/** Per type statistics. */
3143	struct
3144	{
3145	/** The number of ready pages. */
3146	uint32_t cReadyPages;
3147	/** The number of dirty pages. */
3148	uint32_t cDirtyPages;
3149	/** The number of ready zero pages. */
3150	uint32_t cZeroPages;
3151	/** The number of write monitored pages. */
3152	uint32_t cMonitoredPages;
3153	} Rom,
3154	Mmio2,
3155	Ram;
3156	/** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3157	uint32_t cIgnoredPages;
3158	/** Indicates that a live save operation is active. */
3159	bool fActive;
3160	/** Padding. */
3161	bool afReserved[2];
3162	/** The next history index. */
3163	uint8_t iDirtyPagesHistory;
3164	/** History of the total amount of dirty pages. */
3165	uint32_t acDirtyPagesHistory[64];
3166	/** Short term dirty page average. */
3167	uint32_t cDirtyPagesShort;
3168	/** Long term dirty page average. */
3169	uint32_t cDirtyPagesLong;
3170	/** The number of saved pages. This is used to get some kind of estimate of the
3171	* link speed so we can decide when we're done. It is reset after the first
3172	* 7 passes so the speed estimate doesn't get inflated by the initial set of
3173	* zero pages. */
3174	uint64_t cSavedPages;
3175	/** The nanosecond timestamp when cSavedPages was 0. */
3176	uint64_t uSaveStartNS;
3177	/** Pages per second (for statistics). */
3178	uint32_t cPagesPerSecond;
3179	uint32_t cAlignment;
3180	} LiveSave;
3181
3182	/** @name Error injection.
3183	* @{ */
3184	/** Inject handy page allocation errors pretending we're completely out of
3185	* memory. */
3186	bool volatile fErrInjHandyPages;
3187	/** Padding. */
3188	bool afReserved[3];
3189	/** @} */
3190
3191	/** @name Release Statistics
3192	* @{ */
3193	uint32_t cAllPages; /*< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) /
3194	uint32_t cPrivatePages; /*< The number of private pages. /
3195	uint32_t cSharedPages; /*< The number of shared pages. /
3196	uint32_t cReusedSharedPages; /*< The number of reused shared pages. /
3197	uint32_t cZeroPages; /*< The number of zero backed pages. /
3198	uint32_t cPureMmioPages; /*< The number of pure MMIO pages. /
3199	uint32_t cMonitoredPages; /*< The number of write monitored pages. /
3200	uint32_t cWrittenToPages; /*< The number of previously write monitored pages. /
3201	uint32_t cWriteLockedPages; /*< The number of write locked pages. /
3202	uint32_t cReadLockedPages; /*< The number of read locked pages. /
3203	uint32_t cBalloonedPages; /*< The number of ballooned pages. /
3204	uint32_t cMappedChunks; /*< Number of times we mapped a chunk. /
3205	uint32_t cUnmappedChunks; /*< Number of times we unmapped a chunk. /
3206	uint32_t cLargePages; /*< The number of large pages. /
3207	uint32_t cLargePagesDisabled; /*< The number of disabled large pages. /
3208	/* uint32_t aAlignment4[1]; */
3209
3210	STAMPROFILE StatLargePageAlloc; /*< Time spent by the host OS for large page allocation. /
3211	STAMCOUNTER StatLargePageAllocFailed; /*< Count allocation failures. /
3212	STAMCOUNTER StatLargePageOverflow; /*< The number of times allocating a large pages takes more than the allowed period. /
3213	STAMCOUNTER StatLargePageReused; /*< The number of large pages we've reused./
3214	STAMCOUNTER StatLargePageRefused; /*< The number of times we couldn't use a large page./
3215	STAMCOUNTER StatLargePageRecheck; /*< The number of times we rechecked a disabled large page./
3216	STAMCOUNTER StatLargePageTlbFlush; /*< The number of a full VCPU TLB flush was required after allocation. /
3217	STAMCOUNTER StatLargePageZeroEvict; /*< The number of zero page mappings we had to evict when allocating a large page. /
3218
3219	STAMPROFILE StatShModCheck; /*< Profiles shared module checks. /
3220
3221	STAMPROFILE StatMmio2QueryAndResetDirtyBitmap; /*< Profiling PGMR3PhysMmio2QueryAndResetDirtyBitmap. /
3222	/** @} */
3223
3224	#ifdef VBOX_WITH_STATISTICS
3225	/** These are optional statistics that used to be on the hyper heap. */
3226	PGMSTATS Stats;
3227	#endif
3228	} PGM;
3229	#ifndef IN_TSTVMSTRUCTGC /* HACK */
3230	AssertCompileMemberAlignment(PGM, CritSectX, 8);
3231	AssertCompileMemberAlignment(PGM, ChunkR3Map, 16);
3232	AssertCompileMemberAlignment(PGM, PhysTlbR3, 32); /** @todo 32 byte alignment! */
3233	AssertCompileMemberAlignment(PGM, PhysTlbR0, 32);
3234	AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3235	AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3236	#endif /* !IN_TSTVMSTRUCTGC */
3237	/** Pointer to the PGM instance data. */
3238	typedef PGM *PPGM;
3239
3240
3241	#ifdef VBOX_WITH_STATISTICS
3242	/**
3243	* Per CPU statistis for PGM (used to be on the heap).
3244	*/
3245	typedef struct PGMCPUSTATS
3246	{
3247	/* Common */
3248	STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /*< SyncPT - PD distribution. /
3249	STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /*< SyncPage - PD distribution. /
3250
3251	/* R0 only: */
3252	STAMPROFILE StatR0NpMiscfg; /*< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. /
3253	STAMCOUNTER StatR0NpMiscfgSyncPage; /*< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). /
3254
3255	/* RZ only: */
3256	STAMPROFILE StatRZTrap0e; /*< RC/R0: PGMTrap0eHandler() profiling. /
3257	STAMPROFILE StatRZTrap0eTime2Ballooned; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. /
3258	STAMPROFILE StatRZTrap0eTime2CSAM; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. /
3259	STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. /
3260	STAMPROFILE StatRZTrap0eTime2GuestTrap; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. /
3261	STAMPROFILE StatRZTrap0eTime2HndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. /
3262	STAMPROFILE StatRZTrap0eTime2HndUnhandled; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. /
3263	STAMPROFILE StatRZTrap0eTime2InvalidPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. /
3264	STAMPROFILE StatRZTrap0eTime2MakeWritable; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. /
3265	STAMPROFILE StatRZTrap0eTime2Misc; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. /
3266	STAMPROFILE StatRZTrap0eTime2OutOfSync; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. /
3267	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. /
3268	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. /
3269	STAMPROFILE StatRZTrap0eTime2PageZeroing; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a zero page that is being zeroed. /
3270	STAMPROFILE StatRZTrap0eTime2SyncPT; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. /
3271	STAMPROFILE StatRZTrap0eTime2WPEmulation; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. /
3272	STAMPROFILE StatRZTrap0eTime2Wp0RoUsHack; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be enabled. /
3273	STAMPROFILE StatRZTrap0eTime2Wp0RoUsUnhack; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be disabled. /
3274	STAMCOUNTER StatRZTrap0eConflicts; /*< RC/R0: The number of times \#PF was caused by an undetected conflict. /
3275	STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /*< RC/R0: Number of out-of-sync handled pages. /
3276	STAMCOUNTER StatRZTrap0eHandlersPhysAll; /*< RC/R0: Number of traps due to physical all-access handlers. /
3277	STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /*< RC/R0: Number of the physical all-access handler traps using the optimization. /
3278	STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /*< RC/R0: Number of traps due to write-physical access handlers. /
3279	STAMCOUNTER StatRZTrap0eHandlersUnhandled; /*< RC/R0: Number of traps due to access outside range of monitored page(s). /
3280	STAMCOUNTER StatRZTrap0eHandlersInvalid; /*< RC/R0: Number of traps due to access to invalid physical memory. /
3281	STAMCOUNTER StatRZTrap0eUSNotPresentRead; /*< RC/R0: \#PF err kind /
3282	STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /*< RC/R0: \#PF err kind /
3283	STAMCOUNTER StatRZTrap0eUSWrite; /*< RC/R0: \#PF err kind /
3284	STAMCOUNTER StatRZTrap0eUSReserved; /*< RC/R0: \#PF err kind /
3285	STAMCOUNTER StatRZTrap0eUSNXE; /*< RC/R0: \#PF err kind /
3286	STAMCOUNTER StatRZTrap0eUSRead; /*< RC/R0: \#PF err kind /
3287	STAMCOUNTER StatRZTrap0eSVNotPresentRead; /*< RC/R0: \#PF err kind /
3288	STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /*< RC/R0: \#PF err kind /
3289	STAMCOUNTER StatRZTrap0eSVWrite; /*< RC/R0: \#PF err kind /
3290	STAMCOUNTER StatRZTrap0eSVReserved; /*< RC/R0: \#PF err kind /
3291	STAMCOUNTER StatRZTrap0eSNXE; /*< RC/R0: \#PF err kind /
3292	STAMCOUNTER StatRZTrap0eGuestPF; /*< RC/R0: Real guest \#PFs. /
3293	STAMCOUNTER StatRZTrap0eWPEmulInRZ; /*< RC/R0: WP=0 virtualization trap, handled. /
3294	STAMCOUNTER StatRZTrap0eWPEmulToR3; /*< RC/R0: WP=0 virtualization trap, chickened out. /
3295	STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /*< RC/R0: PD distribution of the \#PFs. /
3296	STAMCOUNTER StatRZGuestCR3WriteHandled; /*< RC/R0: The number of times WriteHandlerCR3() was successfully called. /
3297	STAMCOUNTER StatRZGuestCR3WriteUnhandled; /*< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. /
3298	STAMCOUNTER StatRZGuestCR3WriteConflict; /*< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. /
3299	STAMCOUNTER StatRZGuestROMWriteHandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. /
3300	STAMCOUNTER StatRZGuestROMWriteUnhandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler /
3301	STAMCOUNTER StatRZDynMapMigrateInvlPg; /*< RZ: invlpg in PGMR0DynMapMigrateAutoSet. /
3302	STAMPROFILE StatRZDynMapGCPageInl; /*< RZ: Calls to pgmRZDynMapGCPageInlined. /
3303	STAMCOUNTER StatRZDynMapGCPageInlHits; /*< RZ: Hash table lookup hits. /
3304	STAMCOUNTER StatRZDynMapGCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3305	STAMCOUNTER StatRZDynMapGCPageInlRamHits; /*< RZ: 1st ram range hits. /
3306	STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /*< RZ: 1st ram range misses, takes slow path. /
3307	STAMPROFILE StatRZDynMapHCPageInl; /*< RZ: Calls to pgmRZDynMapHCPageInlined. /
3308	STAMCOUNTER StatRZDynMapHCPageInlHits; /*< RZ: Hash table lookup hits. /
3309	STAMCOUNTER StatRZDynMapHCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3310	STAMPROFILE StatRZDynMapHCPage; /*< RZ: Calls to pgmRZDynMapHCPageCommon. /
3311	STAMCOUNTER StatRZDynMapSetOptimize; /*< RZ: Calls to pgmRZDynMapOptimizeAutoSet. /
3312	STAMCOUNTER StatRZDynMapSetSearchFlushes; /*< RZ: Set search restoring to subset flushes. /
3313	STAMCOUNTER StatRZDynMapSetSearchHits; /*< RZ: Set search hits. /
3314	STAMCOUNTER StatRZDynMapSetSearchMisses; /*< RZ: Set search misses. /
3315	STAMCOUNTER StatRZDynMapPage; /*< RZ: Calls to pgmR0DynMapPage. /
3316	STAMCOUNTER StatRZDynMapPageHits0; /*< RZ: Hits at iPage+0. /
3317	STAMCOUNTER StatRZDynMapPageHits1; /*< RZ: Hits at iPage+1. /
3318	STAMCOUNTER StatRZDynMapPageHits2; /*< RZ: Hits at iPage+2. /
3319	STAMCOUNTER StatRZDynMapPageInvlPg; /*< RZ: invlpg. /
3320	STAMCOUNTER StatRZDynMapPageSlow; /*< RZ: Calls to pgmR0DynMapPageSlow. /
3321	STAMCOUNTER StatRZDynMapPageSlowLoopHits; /*< RZ: Hits in the pgmR0DynMapPageSlow search loop. /
3322	STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /*< RZ: Misses in the pgmR0DynMapPageSlow search loop. /
3323	//STAMCOUNTER StatRZDynMapPageSlowLostHits; /*< RZ: Lost hits. /
3324	STAMCOUNTER StatRZDynMapSubsets; /*< RZ: Times PGMDynMapPushAutoSubset was called. /
3325	STAMCOUNTER StatRZDynMapPopFlushes; /*< RZ: Times PGMDynMapPopAutoSubset flushes the subset. /
3326	STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /*< RZ: Set fill distribution, percent. /
3327
3328	/* HC - R3 and (maybe) R0: */
3329
3330	/* RZ & R3: */
3331	STAMPROFILE StatRZSyncCR3; /*< RC/R0: PGMSyncCR3() profiling. /
3332	STAMPROFILE StatRZSyncCR3Handlers; /*< RC/R0: Profiling of the PGMSyncCR3() update handler section. /
3333	STAMCOUNTER StatRZSyncCR3Global; /*< RC/R0: The number of global CR3 syncs. /
3334	STAMCOUNTER StatRZSyncCR3NotGlobal; /*< RC/R0: The number of non-global CR3 syncs. /
3335	STAMCOUNTER StatRZSyncCR3DstCacheHit; /*< RC/R0: The number of times we got some kind of cache hit on a page table. /
3336	STAMCOUNTER StatRZSyncCR3DstFreed; /*< RC/R0: The number of times we've had to free a shadow entry. /
3337	STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /*< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. /
3338	STAMCOUNTER StatRZSyncCR3DstNotPresent; /*< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. /
3339	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /*< RC/R0: The number of times a global page directory wasn't flushed. /
3340	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /*< RC/R0: The number of times a page table with only global entries wasn't flushed. /
3341	STAMPROFILE StatRZSyncPT; /*< RC/R0: PGMSyncPT() profiling. /
3342	STAMCOUNTER StatRZSyncPTFailed; /*< RC/R0: The number of times PGMSyncPT() failed. /
3343	STAMCOUNTER StatRZSyncPT4K; /*< RC/R0: Number of 4KB syncs. /
3344	STAMCOUNTER StatRZSyncPT4M; /*< RC/R0: Number of 4MB syncs. /
3345	STAMCOUNTER StatRZSyncPagePDNAs; /*< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3346	STAMCOUNTER StatRZSyncPagePDOutOfSync; /*< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. /
3347	STAMCOUNTER StatRZAccessedPage; /*< RC/R0: The number of pages marked not present for accessed bit emulation. /
3348	STAMPROFILE StatRZDirtyBitTracking; /*< RC/R0: Profiling the dirty bit tracking in CheckPageFault(). /
3349	STAMCOUNTER StatRZDirtyPage; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3350	STAMCOUNTER StatRZDirtyPageBig; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3351	STAMCOUNTER StatRZDirtyPageSkipped; /*< RC/R0: The number of pages already dirty or readonly. /
3352	STAMCOUNTER StatRZDirtyPageTrap; /*< RC/R0: The number of traps generated for dirty bit tracking. /
3353	STAMCOUNTER StatRZDirtyPageStale; /*< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) /
3354	STAMCOUNTER StatRZDirtyTrackRealPF; /*< RC/R0: The number of real pages faults during dirty bit tracking. /
3355	STAMCOUNTER StatRZDirtiedPage; /*< RC/R0: The number of pages marked dirty because of write accesses. /
3356	STAMCOUNTER StatRZPageAlreadyDirty; /*< RC/R0: The number of pages already marked dirty because of write accesses. /
3357	STAMPROFILE StatRZInvalidatePage; /*< RC/R0: PGMInvalidatePage() profiling. /
3358	STAMCOUNTER StatRZInvalidatePage4KBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. /
3359	STAMCOUNTER StatRZInvalidatePage4MBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. /
3360	STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /*< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. /
3361	STAMCOUNTER StatRZInvalidatePagePDNAs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3362	STAMCOUNTER StatRZInvalidatePagePDNPs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. /
3363	STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /*< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3364	STAMCOUNTER StatRZInvalidatePageSizeChanges ; /*< RC/R0: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). /
3365	STAMCOUNTER StatRZInvalidatePageSkipped; /*< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3366	STAMCOUNTER StatRZPageOutOfSyncUser; /*< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3367	STAMCOUNTER StatRZPageOutOfSyncSupervisor; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3368	STAMCOUNTER StatRZPageOutOfSyncUserWrite; /*< RC/R0: The number of times user page is out of sync was detected in \#PF. /
3369	STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. /
3370	STAMCOUNTER StatRZPageOutOfSyncBallloon; /*< RC/R0: The number of times a ballooned page was accessed (read). /
3371	STAMPROFILE StatRZPrefetch; /*< RC/R0: PGMPrefetchPage. /
3372	STAMPROFILE StatRZFlushTLB; /*< RC/R0: Profiling of the PGMFlushTLB() body. /
3373	STAMCOUNTER StatRZFlushTLBNewCR3; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3374	STAMCOUNTER StatRZFlushTLBNewCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3375	STAMCOUNTER StatRZFlushTLBSameCR3; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3376	STAMCOUNTER StatRZFlushTLBSameCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3377	STAMPROFILE StatRZGstModifyPage; /*< RC/R0: Profiling of the PGMGstModifyPage() body /
3378
3379	STAMPROFILE StatR3SyncCR3; /*< R3: PGMSyncCR3() profiling. /
3380	STAMPROFILE StatR3SyncCR3Handlers; /*< R3: Profiling of the PGMSyncCR3() update handler section. /
3381	STAMCOUNTER StatR3SyncCR3Global; /*< R3: The number of global CR3 syncs. /
3382	STAMCOUNTER StatR3SyncCR3NotGlobal; /*< R3: The number of non-global CR3 syncs. /
3383	STAMCOUNTER StatR3SyncCR3DstFreed; /*< R3: The number of times we've had to free a shadow entry. /
3384	STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /*< R3: The number of times we've had to free a shadow entry for which the source entry was not present. /
3385	STAMCOUNTER StatR3SyncCR3DstNotPresent; /*< R3: The number of times we've encountered a not present shadow entry for a present guest entry. /
3386	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /*< R3: The number of times a global page directory wasn't flushed. /
3387	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /*< R3: The number of times a page table with only global entries wasn't flushed. /
3388	STAMCOUNTER StatR3SyncCR3DstCacheHit; /*< R3: The number of times we got some kind of cache hit on a page table. /
3389	STAMPROFILE StatR3SyncPT; /*< R3: PGMSyncPT() profiling. /
3390	STAMCOUNTER StatR3SyncPTFailed; /*< R3: The number of times PGMSyncPT() failed. /
3391	STAMCOUNTER StatR3SyncPT4K; /*< R3: Number of 4KB syncs. /
3392	STAMCOUNTER StatR3SyncPT4M; /*< R3: Number of 4MB syncs. /
3393	STAMCOUNTER StatR3SyncPagePDNAs; /*< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3394	STAMCOUNTER StatR3SyncPagePDOutOfSync; /*< R3: The number of time we've encountered an out-of-sync PD in SyncPage. /
3395	STAMCOUNTER StatR3AccessedPage; /*< R3: The number of pages marked not present for accessed bit emulation. /
3396	STAMPROFILE StatR3DirtyBitTracking; /*< R3: Profiling the dirty bit tracking in CheckPageFault(). /
3397	STAMCOUNTER StatR3DirtyPage; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3398	STAMCOUNTER StatR3DirtyPageBig; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3399	STAMCOUNTER StatR3DirtyPageSkipped; /*< R3: The number of pages already dirty or readonly. /
3400	STAMCOUNTER StatR3DirtyPageTrap; /*< R3: The number of traps generated for dirty bit tracking. /
3401	STAMCOUNTER StatR3DirtyTrackRealPF; /*< R3: The number of real pages faults during dirty bit tracking. /
3402	STAMCOUNTER StatR3DirtiedPage; /*< R3: The number of pages marked dirty because of write accesses. /
3403	STAMCOUNTER StatR3PageAlreadyDirty; /*< R3: The number of pages already marked dirty because of write accesses. /
3404	STAMPROFILE StatR3InvalidatePage; /*< R3: PGMInvalidatePage() profiling. /
3405	STAMCOUNTER StatR3InvalidatePage4KBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4KB page. /
3406	STAMCOUNTER StatR3InvalidatePage4MBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4MB page. /
3407	STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /*< R3: The number of times PGMInvalidatePage() skipped a 4MB page. /
3408	STAMCOUNTER StatR3InvalidatePagePDNAs; /*< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3409	STAMCOUNTER StatR3InvalidatePagePDNPs; /*< R3: The number of times PGMInvalidatePage() was called for a not present page directory. /
3410	STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /*< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3411	STAMCOUNTER StatR3InvalidatePageSizeChanges ; /*< R3: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). /
3412	STAMCOUNTER StatR3InvalidatePageSkipped; /*< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3413	STAMCOUNTER StatR3PageOutOfSyncUser; /*< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3414	STAMCOUNTER StatR3PageOutOfSyncSupervisor; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3415	STAMCOUNTER StatR3PageOutOfSyncUserWrite; /*< R3: The number of times user page is out of sync was detected in \#PF. /
3416	STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF. /
3417	STAMCOUNTER StatR3PageOutOfSyncBallloon; /*< R3: The number of times a ballooned page was accessed (read). /
3418	STAMPROFILE StatR3Prefetch; /*< R3: PGMPrefetchPage. /
3419	STAMPROFILE StatR3FlushTLB; /*< R3: Profiling of the PGMFlushTLB() body. /
3420	STAMCOUNTER StatR3FlushTLBNewCR3; /*< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3421	STAMCOUNTER StatR3FlushTLBNewCR3Global; /*< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3422	STAMCOUNTER StatR3FlushTLBSameCR3; /*< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3423	STAMCOUNTER StatR3FlushTLBSameCR3Global; /*< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3424	STAMPROFILE StatR3GstModifyPage; /*< R3: Profiling of the PGMGstModifyPage() body /
3425	} PGMCPUSTATS;
3426	#endif /* VBOX_WITH_STATISTICS */
3427
3428
3429	/**
3430	* PGMCPU Data (part of VMCPU).
3431	*/
3432	typedef struct PGMCPU
3433	{
3434	/** A20 gate mask.
3435	* Our current approach to A20 emulation is to let REM do it and don't bother
3436	* anywhere else. The interesting Guests will be operating with it enabled anyway.
3437	* But whould need arrise, we'll subject physical addresses to this mask. */
3438	RTGCPHYS GCPhysA20Mask;
3439	/** A20 gate state - boolean! */
3440	bool fA20Enabled;
3441	/** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3442	bool fNoExecuteEnabled;
3443	/** Whether the guest CR3 and PAE PDPEs have been mapped when guest PAE mode is
3444	* active. */
3445	bool fPaePdpesAndCr3MappedR3;
3446	bool fPaePdpesAndCr3MappedR0;
3447
3448	/** What needs syncing (PGM_SYNC_*).
3449	* This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3450	* PGMFlushTLB, and PGMR3Load. */
3451	uint32_t fSyncFlags;
3452
3453	/** The shadow paging mode. */
3454	PGMMODE enmShadowMode;
3455	/** The guest paging mode. */
3456	PGMMODE enmGuestMode;
3457	/** The guest second level address translation mode. */
3458	PGMSLAT enmGuestSlatMode;
3459	/** Guest mode data table index (PGM_TYPE_XXX). */
3460	uint8_t volatile idxGuestModeData;
3461	/** Shadow mode data table index (PGM_TYPE_XXX). */
3462	uint8_t volatile idxShadowModeData;
3463	/** Both mode data table index (complicated). */
3464	uint8_t volatile idxBothModeData;
3465	/** Alignment padding. */
3466	uint8_t abPadding[1];
3467
3468	/** The guest CR3.
3469	* When SLAT is active, this is the translated physical address.
3470	* When SLAT is inactive, this is the physical address in CR3. */
3471	RTGCPHYS GCPhysCR3;
3472
3473	/** The nested-guest CR3.
3474	* When SLAT is active, this is CR3 prior to translation.
3475	* When SLAT is inactive, this is unused (and NIL_RTGCPHYS). */
3476	RTGCPHYS GCPhysNstGstCR3;
3477
3478	/** The cached guest CR3 when it has been mapped in PAE mode.
3479	* This allows us to skip remapping the CR3 and PAE PDPEs
3480	* (in PGMFlushTLB or similar) when it was already done as
3481	* part of MOV CRx instruction emulation.
3482	*/
3483	RTGCPHYS GCPhysPaeCR3;
3484
3485	/** @name 32-bit Guest Paging.
3486	* @{ */
3487	/** The guest's page directory, R3 pointer. */
3488	R3PTRTYPE(PX86PD) pGst32BitPdR3;
3489	/** The guest's page directory, R0 pointer. */
3490	R0PTRTYPE(PX86PD) pGst32BitPdR0;
3491	/** Mask containing the MBZ bits of a big page PDE. */
3492	uint32_t fGst32BitMbzBigPdeMask;
3493	/** Set if the page size extension (PSE) is enabled. */
3494	bool fGst32BitPageSizeExtension;
3495	/** Alignment padding. */
3496	bool afAlignment2[3];
3497	/** @} */
3498
3499	/** @name PAE Guest Paging.
3500	* @{ */
3501	/** The guest's page directory pointer table, R3 pointer. */
3502	R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3503	/** The guest's page directory pointer table, R0 pointer. */
3504	R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3505
3506	/** The guest's page directories, R3 pointers.
3507	* These are individual pointers and don't have to be adjacent.
3508	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3509	R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3510	/** The guest's page directories, R0 pointers.
3511	* Same restrictions as apGstPaePDsR3. */
3512	R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3513	/** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
3514	RTGCPHYS aGCPhysGstPaePDs[4];
3515	/** Mask containing the MBZ PTE bits. */
3516	uint64_t fGstPaeMbzPteMask;
3517	/** Mask containing the MBZ PDE bits. */
3518	uint64_t fGstPaeMbzPdeMask;
3519	/** Mask containing the MBZ big page PDE bits. */
3520	uint64_t fGstPaeMbzBigPdeMask;
3521	/** Mask containing the MBZ PDPE bits. */
3522	uint64_t fGstPaeMbzPdpeMask;
3523	/** @} */
3524
3525	/** @name AMD64 Guest Paging.
3526	* @{ */
3527	/** The guest's page directory pointer table, R3 pointer. */
3528	R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3529	/** The guest's page directory pointer table, R0 pointer. */
3530	R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3531	/** Mask containing the MBZ PTE bits. */
3532	uint64_t fGstAmd64MbzPteMask;
3533	/** Mask containing the MBZ PDE bits. */
3534	uint64_t fGstAmd64MbzPdeMask;
3535	/** Mask containing the MBZ big page PDE bits. */
3536	uint64_t fGstAmd64MbzBigPdeMask;
3537	/** Mask containing the MBZ PDPE bits. */
3538	uint64_t fGstAmd64MbzPdpeMask;
3539	/** Mask containing the MBZ big page PDPE bits. */
3540	uint64_t fGstAmd64MbzBigPdpeMask;
3541	/** Mask containing the MBZ PML4E bits. */
3542	uint64_t fGstAmd64MbzPml4eMask;
3543	/** Mask containing the PDPE bits that we shadow. */
3544	uint64_t fGstAmd64ShadowedPdpeMask;
3545	/** Mask containing the PML4E bits that we shadow. */
3546	uint64_t fGstAmd64ShadowedPml4eMask;
3547	/** @} */
3548
3549	/** @name PAE and AMD64 Guest Paging.
3550	* @{ */
3551	/** Mask containing the PTE bits that we shadow. */
3552	uint64_t fGst64ShadowedPteMask;
3553	/** Mask containing the PDE bits that we shadow. */
3554	uint64_t fGst64ShadowedPdeMask;
3555	/** Mask containing the big page PDE bits that we shadow in the PDE. */
3556	uint64_t fGst64ShadowedBigPdeMask;
3557	/** Mask containing the big page PDE bits that we shadow in the PTE. */
3558	uint64_t fGst64ShadowedBigPde4PteMask;
3559	/** @} */
3560
3561	/** @name EPT Guest Paging.
3562	* @{ */
3563	/** The guest's EPT PML4 table, R3 pointer. */
3564	R3PTRTYPE(PEPTPML4) pGstEptPml4R3;
3565	/** The guest's EPT PML4 table, R0 pointer. */
3566	R0PTRTYPE(PEPTPML4) pGstEptPml4R0;
3567	/** The guest's EPT pointer (copy of virtual VMCS). */
3568	uint64_t uEptPtr;
3569	/** Copy of the VM's IA32_VMX_EPT_VPID_CAP VPID MSR for faster access. Doesn't
3570	* change through the lifetime of the VM. */
3571	uint64_t uEptVpidCapMsr;
3572	/** Mask containing the MBZ PTE bits. */
3573	uint64_t fGstEptMbzPteMask;
3574	/** Mask containing the MBZ PDE bits. */
3575	uint64_t fGstEptMbzPdeMask;
3576	/** Mask containing the MBZ big page (2M) PDE bits. */
3577	uint64_t fGstEptMbzBigPdeMask;
3578	/** Mask containing the MBZ PDPTE bits. */
3579	uint64_t fGstEptMbzPdpteMask;
3580	/** Mask containing the MBZ big page (1G) PDPTE bits. */
3581	uint64_t fGstEptMbzBigPdpteMask;
3582	/** Mask containing the MBZ PML4E bits. */
3583	uint64_t fGstEptMbzPml4eMask;
3584	/** Mask to determine whether an entry is present. */
3585	uint64_t fGstEptPresentMask;
3586
3587	/** Mask containing the EPT PTE bits we shadow. */
3588	uint64_t fGstEptShadowedPteMask;
3589	/** Mask containing the EPT PDE bits we shadow. */
3590	uint64_t fGstEptShadowedPdeMask;
3591	/** Mask containing the EPT PDE (2M) bits we shadow. */
3592	uint64_t fGstEptShadowedBigPdeMask;
3593	/** Mask containing the EPT PDPTE bits we shadow. */
3594	uint64_t fGstEptShadowedPdpteMask;
3595	/** Mask containing the EPT PML4E bits we shadow. */
3596	uint64_t fGstEptShadowedPml4eMask;
3597	/** @} */
3598
3599	/** Pointer to the page of the current active CR3 - R3 Ptr. */
3600	R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3601	/** Pointer to the page of the current active CR3 - R0 Ptr. */
3602	R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3603
3604	/** For saving stack space, the disassembler state is allocated here instead of
3605	* on the stack. */
3606	DISSTATE Dis;
3607
3608	/** Counts the number of times the netware WP0+RO+US hack has been applied. */
3609	uint64_t cNetwareWp0Hacks;
3610
3611	/** Count the number of pgm pool access handler calls. */
3612	uint64_t cPoolAccessHandler;
3613
3614	/** @name Release Statistics
3615	* @{ */
3616	/** The number of times the guest has switched mode since last reset or statistics reset. */
3617	STAMCOUNTER cGuestModeChanges;
3618	/** The number of times the guest has switched mode since last reset or statistics reset. */
3619	STAMCOUNTER cA20Changes;
3620	/** @} */
3621
3622	#ifdef VBOX_WITH_STATISTICS
3623	/** These are statistics that used to be on the hyper heap. */
3624	PGMCPUSTATS Stats;
3625	#endif
3626	} PGMCPU;
3627	/** Pointer to the per-cpu PGM data. */
3628	typedef PGMCPU *PPGMCPU;
3629
3630
3631	/** @name PGM::fSyncFlags Flags
3632	* @note Was part of saved state a long time ago.
3633	* @{
3634	*/
3635	/* 0 used to be PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL */
3636	/** Always sync CR3. */
3637	#define PGM_SYNC_ALWAYS RT_BIT(1)
3638	/** Check guest mapping in SyncCR3. */
3639	#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3640	/** Clear the page pool (a light weight flush). */
3641	#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3642	#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3643	/** @} */
3644
3645
3646	#if defined(IN_RING0) \|\| defined(DOXYGEN_RUNNING)
3647
3648	/**
3649	* PGM GVMCPU instance data.
3650	*/
3651	typedef struct PGMR0PERVCPU
3652	{
3653	# ifdef VBOX_WITH_STATISTICS
3654	/** R0: Which statistic this \#PF should be attributed to. */
3655	R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3656	# endif
3657	uint64_t u64Dummy;
3658	} PGMR0PERVCPU;
3659
3660
3661	/**
3662	* PGM GVM instance data.
3663	*/
3664	typedef struct PGMR0PERVM
3665	{
3666	/** @name PGM Pool related stuff.
3667	* @{ */
3668	/** Critical section for serializing pool growth. */
3669	RTCRITSECT PoolGrowCritSect;
3670	/** The memory objects for the pool pages. */
3671	RTR0MEMOBJ ahPoolMemObjs[(PGMPOOL_IDX_LAST + PGMPOOL_CFG_MAX_GROW - 1) / PGMPOOL_CFG_MAX_GROW];
3672	/** The ring-3 mapping objects for the pool pages. */
3673	RTR0MEMOBJ ahPoolMapObjs[(PGMPOOL_IDX_LAST + PGMPOOL_CFG_MAX_GROW - 1) / PGMPOOL_CFG_MAX_GROW];
3674	/** @} */
3675
3676	/** Physical access handler types for ring-0.
3677	* Initialized to callback causing return to ring-3 and invalid enmKind. */
3678	PGMPHYSHANDLERTYPEINTR0 aPhysHandlerTypes[PGMPHYSHANDLERTYPE_COUNT];
3679	/** Physical handler allocator, ring-3 edition. */
3680	PGMPHYSHANDLERALLOCATOR PhysHandlerAllocator;
3681	/** The pointer to the ring-3 mapping of the physical access handler tree. */
3682	PPGMPHYSHANDLERTREE pPhysHandlerTree;
3683	/** The allocation object for the physical access handler tree. */
3684	RTR0MEMOBJ hPhysHandlerMemObj;
3685	/** The ring-3 mapping object for the physicall access handler tree. */
3686	RTR0MEMOBJ hPhysHandlerMapObj;
3687	} PGMR0PERVM;
3688
3689	#endif /* IN_RING0 \|\| DOXYGEN_RUNNING */
3690
3691	RT_C_DECLS_BEGIN
3692
3693	#if defined(VBOX_STRICT)
3694	int pgmLockDebug(PVMCC pVM, bool fVoid, RT_SRC_POS_DECL);
3695	# define PGM_LOCK_VOID(a_pVM) pgmLockDebug((a_pVM), true, RT_SRC_POS)
3696	# define PGM_LOCK(a_pVM) pgmLockDebug((a_pVM), false, RT_SRC_POS)
3697	#else
3698	int pgmLock(PVMCC pVM, bool fVoid);
3699	# define PGM_LOCK_VOID(a_pVM) pgmLock((a_pVM), true)
3700	# define PGM_LOCK(a_pVM) pgmLock((a_pVM), false)
3701	#endif
3702	void pgmUnlock(PVMCC pVM);
3703	# define PGM_UNLOCK(a_pVM) pgmUnlock((a_pVM))
3704	/**
3705	* Asserts that the caller owns the PDM lock.
3706	* This is the internal variant of PGMIsLockOwner.
3707	* @param a_pVM Pointer to the VM.
3708	*/
3709	#define PGM_LOCK_ASSERT_OWNER(a_pVM) Assert(PDMCritSectIsOwner((a_pVM), &(a_pVM)->pgm.s.CritSectX))
3710	/**
3711	* Asserts that the caller owns the PDM lock.
3712	* This is the internal variant of PGMIsLockOwner.
3713	* @param a_pVM Pointer to the VM.
3714	* @param a_pVCpu The current CPU handle.
3715	*/
3716	#define PGM_LOCK_ASSERT_OWNER_EX(a_pVM, a_pVCpu) Assert(PDMCritSectIsOwnerEx((a_pVCpu), &(a_pVM)->pgm.s.CritSectX))
3717
3718	uint32_t pgmHandlerPhysicalCalcTableSizes(uint32_t pcEntries, uint32_t pcbTreeAndBitmap);
3719	int pgmHandlerPhysicalExCreate(PVMCC pVM, PGMPHYSHANDLERTYPE hType, uint64_t uUser,
3720	R3PTRTYPE(const char ) pszDesc, PPGMPHYSHANDLER ppPhysHandler);
3721	int pgmHandlerPhysicalExDup(PVMCC pVM, PPGMPHYSHANDLER pPhysHandlerSrc, PPGMPHYSHANDLER *ppPhysHandler);
3722	int pgmHandlerPhysicalExRegister(PVMCC pVM, PPGMPHYSHANDLER pPhysHandler, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
3723	int pgmHandlerPhysicalExDeregister(PVMCC pVM, PPGMPHYSHANDLER pPhysHandler);
3724	int pgmHandlerPhysicalExDestroy(PVMCC pVM, PPGMPHYSHANDLER pHandler);
3725	void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3726	bool pgmHandlerPhysicalIsAll(PVMCC pVM, RTGCPHYS GCPhys);
3727	void pgmHandlerPhysicalResetAliasedPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, PPGMRAMRANGE pRam,
3728	bool fDoAccounting, bool fFlushIemTlbs);
3729	DECLHIDDEN(int) pgmHandlerPhysicalResetMmio2WithBitmap(PVMCC pVM, RTGCPHYS GCPhys, void *pvBitmap, uint32_t offBitmap);
3730	DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3731	DECLCALLBACK(FNPGMPHYSHANDLER) pgmR3HandlerPhysicalHandlerInvalid;
3732	#ifndef IN_RING3
3733	DECLCALLBACK(FNPGMPHYSHANDLER) pgmR0HandlerPhysicalHandlerToRing3;
3734	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) pgmR0HandlerPhysicalPfHandlerToRing3;
3735	#endif
3736
3737	int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3738
3739	int pgmPhysAllocPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3740	int pgmPhysAllocLargePage(PVMCC pVM, RTGCPHYS GCPhys);
3741	#ifdef IN_RING0
3742	int pgmR0PhysAllocateHandyPages(PGVM pGVM, VMCPUID idCpu, bool fRing3);
3743	int pgmR0PhysAllocateLargePage(PGVM pGVM, VMCPUID idCpu, RTGCPHYS GCPhys);
3744	#endif
3745	int pgmPhysRecheckLargePage(PVMCC pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
3746	int pgmPhysPageLoadIntoTlb(PVMCC pVM, RTGCPHYS GCPhys);
3747	int pgmPhysPageLoadIntoTlbWithPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3748	void pgmPhysPageMakeWriteMonitoredWritable(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3749	int pgmPhysPageMakeWritable(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3750	int pgmPhysPageMakeWritableAndMap(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3751	int pgmPhysPageMap(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3752	int pgmPhysPageMapReadOnly(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3753	int pgmPhysPageMapByPageID(PVMCC pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3754	int pgmPhysGCPhys2R3Ptr(PVMCC pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
3755	int pgmPhysCr3ToHCPtr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
3756	int pgmPhysGCPhys2CCPtrInternalDepr(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3757	int pgmPhysGCPhys2CCPtrInternal(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
3758	int pgmPhysGCPhys2CCPtrInternalReadOnly(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv, PPGMPAGEMAPLOCK pLock);
3759	void pgmPhysReleaseInternalPageMappingLock(PVMCC pVM, PPGMPAGEMAPLOCK pLock);
3760	DECLCALLBACK(FNPGMPHYSHANDLER) pgmPhysRomWriteHandler;
3761	DECLCALLBACK(FNPGMPHYSHANDLER) pgmPhysMmio2WriteHandler;
3762	#ifndef IN_RING3
3763	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) pgmPhysRomWritePfHandler;
3764	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) pgmPhysMmio2WritePfHandler;
3765	#endif
3766	int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys,
3767	PGMPAGETYPE enmNewType);
3768	void pgmPhysInvalidRamRangeTlbs(PVMCC pVM);
3769	void pgmPhysInvalidatePageMapTLB(PVMCC pVM);
3770	void pgmPhysInvalidatePageMapTLBEntry(PVMCC pVM, RTGCPHYS GCPhys);
3771	PPGMRAMRANGE pgmPhysGetRangeSlow(PVM pVM, RTGCPHYS GCPhys);
3772	PPGMRAMRANGE pgmPhysGetRangeAtOrAboveSlow(PVM pVM, RTGCPHYS GCPhys);
3773	PPGMPAGE pgmPhysGetPageSlow(PVM pVM, RTGCPHYS GCPhys);
3774	int pgmPhysGetPageExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage);
3775	int pgmPhysGetPageAndRangeExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam);
3776	#ifdef VBOX_WITH_NATIVE_NEM
3777	void pgmPhysSetNemStateForPages(PPGMPAGE paPages, RTGCPHYS cPages, uint8_t u2State);
3778	#endif
3779
3780	#ifdef IN_RING3
3781	void pgmR3PhysRelinkRamRanges(PVM pVM);
3782	int pgmR3PhysRamPreAllocate(PVM pVM);
3783	int pgmR3PhysRamReset(PVM pVM);
3784	int pgmR3PhysRomReset(PVM pVM);
3785	int pgmR3PhysRamZeroAll(PVM pVM);
3786	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3787	int pgmR3PhysRamTerm(PVM pVM);
3788	void pgmR3PhysRomTerm(PVM pVM);
3789	void pgmR3PhysAssertSharedPageChecksums(PVM pVM);
3790
3791	int pgmR3PoolInit(PVM pVM);
3792	void pgmR3PoolRelocate(PVM pVM);
3793	void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3794	void pgmR3PoolReset(PVM pVM);
3795	void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
3796	DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
3797	void pgmR3PoolWriteProtectPages(PVM pVM);
3798
3799	#endif /* IN_RING3 */
3800	#ifdef IN_RING0
3801	int pgmR0PoolInitVM(PGVM pGVM);
3802	#endif
3803	int pgmPoolAlloc(PVMCC pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
3804	uint16_t iUser, uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
3805	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3806	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3807	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
3808	void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3809	PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3810	PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
3811	int pgmPoolHCPhys2Ptr(PVM pVM, RTHCPHYS HCPhys, void **ppv);
3812	int pgmPoolSyncCR3(PVMCPUCC pVCpu);
3813	bool pgmPoolIsDirtyPageSlow(PVMCC pVM, RTGCPHYS GCPhys);
3814	void pgmPoolInvalidateDirtyPage(PVMCC pVM, RTGCPHYS GCPhysPT);
3815	int pgmPoolTrackUpdateGCPhys(PVMCC pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3816	void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
3817	uint16_t pgmPoolTrackPhysExtAddref(PVMCC pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
3818	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
3819	void pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3820	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3821	FNPGMPHYSHANDLER pgmPoolAccessHandler;
3822	#ifndef IN_RING3
3823	FNPGMRZPHYSPFHANDLER pgmRZPoolAccessPfHandler;
3824	#endif
3825
3826	void pgmPoolAddDirtyPage(PVMCC pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3827	void pgmPoolResetDirtyPages(PVMCC pVM);
3828	void pgmPoolResetDirtyPage(PVMCC pVM, RTGCPTR GCPtrPage);
3829
3830	/** Gets the ring-0 pointer for the given pool page. */
3831	DECLINLINE(R0PTRTYPE(PPGMPOOLPAGE)) pgmPoolConvertPageToR0(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3832	{
3833	#ifdef IN_RING3
3834	size_t offPage = (uintptr_t)pPage - (uintptr_t)pPool;
3835	# ifdef VBOX_STRICT
3836	size_t iPage = (offPage - RT_UOFFSETOF(PGMPOOL, aPages)) / sizeof(*pPage);
3837	AssertReturn(iPage < pPool->cMaxPages, NIL_RTR0PTR);
3838	AssertReturn(iPage * sizeof(*pPage) + RT_UOFFSETOF(PGMPOOL, aPages) == offPage, NIL_RTR0PTR);
3839	# endif
3840	return pPool->pPoolR0 + offPage;
3841	#else
3842	RT_NOREF(pPool);
3843	return pPage;
3844	#endif
3845	}
3846
3847	/** Gets the ring-3 pointer for the given pool page. */
3848	DECLINLINE(R3PTRTYPE(PPGMPOOLPAGE)) pgmPoolConvertPageToR3(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3849	{
3850	#ifdef IN_RING3
3851	RT_NOREF(pPool);
3852	return pPage;
3853	#else
3854	size_t offPage = (uintptr_t)pPage - (uintptr_t)pPool;
3855	# ifdef VBOX_STRICT
3856	size_t iPage = (offPage - RT_UOFFSETOF(PGMPOOL, aPages)) / sizeof(*pPage);
3857	AssertReturn(iPage < pPool->cMaxPages, NIL_RTR3PTR);
3858	AssertReturn(iPage * sizeof(*pPage) + RT_UOFFSETOF(PGMPOOL, aPages) == offPage, NIL_RTR3PTR);
3859	# endif
3860	return pPool->pPoolR3 + offPage;
3861	#endif
3862	}
3863
3864	int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu);
3865	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3866	void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu);
3867
3868	int pgmShwMakePageSupervisorAndWritable(PVMCPUCC pVCpu, RTGCPTR GCPtr, bool fBigPage, uint32_t fOpFlags);
3869	int pgmShwSyncPaePDPtr(PVMCPUCC pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
3870	int pgmShwSyncNestedPageLocked(PVMCPUCC pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
3871
3872	int pgmGstLazyMap32BitPD(PVMCPUCC pVCpu, PX86PD *ppPd);
3873	int pgmGstLazyMapPaePDPT(PVMCPUCC pVCpu, PX86PDPT *ppPdpt);
3874	int pgmGstLazyMapPaePD(PVMCPUCC pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
3875	int pgmGstLazyMapPml4(PVMCPUCC pVCpu, PX86PML4 *ppPml4);
3876	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
3877	int pgmGstLazyMapEptPml4(PVMCPUCC pVCpu, PEPTPML4 *ppPml4);
3878	#endif
3879	int pgmGstPtWalk(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk, PPGMPTWALKGST pGstWalk);
3880	int pgmGstPtWalkNext(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk, PPGMPTWALKGST pGstWalk);
3881
3882	# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64 && defined(IN_RING3)
3883	FNDBGCCMD pgmR3CmdCheckDuplicatePages;
3884	FNDBGCCMD pgmR3CmdShowSharedModules;
3885	# endif
3886
3887	void pgmLogState(PVM pVM);
3888
3889	RT_C_DECLS_END
3890
3891	/** @} */
3892
3893	#endif /* !VMM_INCLUDED_SRC_include_PGMInternal_h */
3894

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source: vbox/trunk/src/VBox/VMM/include/PGMInternal.h@ 100964

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