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source: vbox/trunk/src/VBox/VMM/include/PDMInternal.h@ 108379

最後變更 在這個檔案從108379是 108132,由 vboxsync 提交於 7 週 前

VMM/PGM: Merge and deduplicate code targeting x86 & amd64 in PGM.cpp. Don't bother compiling pool stuff on arm and darwin.amd64. jiraref:VBP-1531
  • 屬性 svn:eol-style 設為 native
  • 屬性 svn:keywords 設為 Id Revision
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1/* $Id: PDMInternal.h 108132 2025-02-10 11:05:23Z vboxsync $ */
2/** @file
3 * PDM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2024 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.alldomusa.eu.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_PDMInternal_h
29#define VMM_INCLUDED_SRC_include_PDMInternal_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#include <VBox/types.h>
35#include <VBox/param.h>
36#include <VBox/vmm/cfgm.h>
37#include <VBox/vmm/stam.h>
38#include <VBox/vusb.h>
39#include <VBox/vmm/iom.h>
40#include <VBox/vmm/pdmasynccompletion.h>
41#ifdef VBOX_WITH_NETSHAPER
42# include <VBox/vmm/pdmnetshaper.h>
43#endif
44#ifdef VBOX_WITH_PDM_ASYNC_COMPLETION
45# include <VBox/vmm/pdmasynccompletion.h>
46#endif
47#include <VBox/vmm/pdmblkcache.h>
48#include <VBox/vmm/pdmcommon.h>
49#include <VBox/vmm/pdmtask.h>
50#if defined(VBOX_VMM_TARGET_X86) || defined(VBOX_VMM_TARGET_AGNOSTIC)
51# include <VBox/vmm/pdmapic.h>
52#endif
53#if defined(VBOX_VMM_TARGET_ARMV8) || defined(VBOX_VMM_TARGET_AGNOSTIC)
54# include <VBox/vmm/pdmgic.h>
55#endif
56#include <VBox/sup.h>
57#include <VBox/msi.h>
58#include <iprt/assert.h>
59#include <iprt/critsect.h>
60#ifdef IN_RING3
61# include <iprt/thread.h>
62#endif
63
64RT_C_DECLS_BEGIN
65
66
67/** @defgroup grp_pdm_int Internal
68 * @ingroup grp_pdm
69 * @internal
70 * @{
71 */
72
73/** @def PDM_WITH_R3R0_CRIT_SECT
74 * Enables or disabled ring-3/ring-0 critical sections. */
75#if defined(DOXYGEN_RUNNING) || 1
76# define PDM_WITH_R3R0_CRIT_SECT
77#endif
78
79/** @def PDMCRITSECT_STRICT
80 * Enables/disables PDM critsect strictness like deadlock detection. */
81#if (defined(RT_LOCK_STRICT) && defined(IN_RING3) && !defined(PDMCRITSECT_STRICT)) \
82 || defined(DOXYGEN_RUNNING)
83# define PDMCRITSECT_STRICT
84#endif
85
86/** @def PDMCRITSECT_STRICT
87 * Enables/disables PDM read/write critsect strictness like deadlock
88 * detection. */
89#if (defined(RT_LOCK_STRICT) && defined(IN_RING3) && !defined(PDMCRITSECTRW_STRICT)) \
90 || defined(DOXYGEN_RUNNING)
91# define PDMCRITSECTRW_STRICT
92#endif
93
94/** The maximum device instance (total) size, ring-0/raw-mode capable devices. */
95#define PDM_MAX_DEVICE_INSTANCE_SIZE _4M
96/** The maximum device instance (total) size, ring-3 only devices. */
97#define PDM_MAX_DEVICE_INSTANCE_SIZE_R3 _8M
98/** The maximum size for the DBGF tracing tracking structure allocated for each device. */
99#define PDM_MAX_DEVICE_DBGF_TRACING_TRACK HOST_PAGE_SIZE
100
101
102
103/*******************************************************************************
104* Structures and Typedefs *
105*******************************************************************************/
106
107/** Pointer to a PDM Device. */
108typedef struct PDMDEV *PPDMDEV;
109/** Pointer to a pointer to a PDM Device. */
110typedef PPDMDEV *PPPDMDEV;
111
112/** Pointer to a PDM USB Device. */
113typedef struct PDMUSB *PPDMUSB;
114/** Pointer to a pointer to a PDM USB Device. */
115typedef PPDMUSB *PPPDMUSB;
116
117/** Pointer to a PDM Driver. */
118typedef struct PDMDRV *PPDMDRV;
119/** Pointer to a pointer to a PDM Driver. */
120typedef PPDMDRV *PPPDMDRV;
121
122/** Pointer to a PDM Logical Unit. */
123typedef struct PDMLUN *PPDMLUN;
124/** Pointer to a pointer to a PDM Logical Unit. */
125typedef PPDMLUN *PPPDMLUN;
126
127/** Pointer to a DMAC instance. */
128typedef struct PDMDMAC *PPDMDMAC;
129/** Pointer to a RTC instance. */
130typedef struct PDMRTC *PPDMRTC;
131
132/** Pointer to an USB HUB registration record. */
133typedef struct PDMUSBHUB *PPDMUSBHUB;
134
135/**
136 * Supported asynchronous completion endpoint classes.
137 */
138typedef enum PDMASYNCCOMPLETIONEPCLASSTYPE
139{
140 /** File class. */
141 PDMASYNCCOMPLETIONEPCLASSTYPE_FILE = 0,
142 /** Number of supported classes. */
143 PDMASYNCCOMPLETIONEPCLASSTYPE_MAX,
144 /** 32bit hack. */
145 PDMASYNCCOMPLETIONEPCLASSTYPE_32BIT_HACK = 0x7fffffff
146} PDMASYNCCOMPLETIONEPCLASSTYPE;
147
148
149/**
150 * MMIO/IO port registration tracking structure for DBGF tracing.
151 */
152typedef struct PDMDEVINSDBGFTRACK
153{
154 /** Flag whether this tracks a IO port or MMIO registration. */
155 bool fMmio;
156 /** Opaque user data passed during registration. */
157 void *pvUser;
158 /** Type dependent data. */
159 union
160 {
161 /** I/O port registration. */
162 struct
163 {
164 /** IOM I/O port handle. */
165 IOMIOPORTHANDLE hIoPorts;
166 /** Original OUT handler of the device. */
167 PFNIOMIOPORTNEWOUT pfnOut;
168 /** Original IN handler of the device. */
169 PFNIOMIOPORTNEWIN pfnIn;
170 /** Original string OUT handler of the device. */
171 PFNIOMIOPORTNEWOUTSTRING pfnOutStr;
172 /** Original string IN handler of the device. */
173 PFNIOMIOPORTNEWINSTRING pfnInStr;
174 } IoPort;
175 /** MMIO registration. */
176 struct
177 {
178 /** IOM MMIO region handle. */
179 IOMMMIOHANDLE hMmioRegion;
180 /** Original MMIO write handler of the device. */
181 PFNIOMMMIONEWWRITE pfnWrite;
182 /** Original MMIO read handler of the device. */
183 PFNIOMMMIONEWREAD pfnRead;
184 /** Original MMIO fill handler of the device. */
185 PFNIOMMMIONEWFILL pfnFill;
186 } Mmio;
187 } u;
188} PDMDEVINSDBGFTRACK;
189/** Pointer to a MMIO/IO port registration tracking structure. */
190typedef PDMDEVINSDBGFTRACK *PPDMDEVINSDBGFTRACK;
191/** Pointer to a const MMIO/IO port registration tracking structure. */
192typedef const PDMDEVINSDBGFTRACK *PCPDMDEVINSDBGFTRACK;
193
194
195/**
196 * Private device instance data, ring-3.
197 */
198typedef struct PDMDEVINSINTR3
199{
200 /** Pointer to the next instance.
201 * (Head is pointed to by PDM::pDevInstances.) */
202 R3PTRTYPE(PPDMDEVINS) pNextR3;
203 /** Pointer to the next per device instance.
204 * (Head is pointed to by PDMDEV::pInstances.) */
205 R3PTRTYPE(PPDMDEVINS) pPerDeviceNextR3;
206 /** Pointer to device structure. */
207 R3PTRTYPE(PPDMDEV) pDevR3;
208 /** Pointer to the list of logical units associated with the device. (FIFO) */
209 R3PTRTYPE(PPDMLUN) pLunsR3;
210 /** Pointer to the asynchronous notification callback set while in
211 * FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
212 R3PTRTYPE(PFNPDMDEVASYNCNOTIFY) pfnAsyncNotify;
213 /** Configuration handle to the instance node. */
214 R3PTRTYPE(PCFGMNODE) pCfgHandle;
215
216 /** R3 pointer to the VM this instance was created for. */
217 PVMR3 pVMR3;
218 /** DBGF trace event source handle if tracing is configured. */
219 DBGFTRACEREVTSRC hDbgfTraceEvtSrc;
220 /** Pointer to the base of the page containing the DBGF tracing tracking structures. */
221 PPDMDEVINSDBGFTRACK paDbgfTraceTrack;
222 /** Index of the next entry to use for tracking. */
223 uint32_t idxDbgfTraceTrackNext;
224 /** Maximum number of records fitting into the single page. */
225 uint32_t cDbgfTraceTrackMax;
226
227 /** Flags, see PDMDEVINSINT_FLAGS_XXX. */
228 uint32_t fIntFlags;
229 /** The last IRQ tag (for tracing it thru clearing). */
230 uint32_t uLastIrqTag;
231 /** The ring-0 device index (for making ring-0 calls). */
232 uint32_t idxR0Device;
233} PDMDEVINSINTR3;
234
235
236/**
237 * Private device instance data, ring-0.
238 */
239typedef struct PDMDEVINSINTR0
240{
241 /** Pointer to the VM this instance was created for. */
242 R0PTRTYPE(PGVM) pGVM;
243 /** Pointer to device structure. */
244 R0PTRTYPE(struct PDMDEVREGR0 const *) pRegR0;
245 /** The ring-0 module reference. */
246 RTR0PTR hMod;
247 /** Pointer to the ring-0 mapping of the ring-3 internal data (for uLastIrqTag). */
248 R0PTRTYPE(PDMDEVINSINTR3 *) pIntR3R0;
249 /** Pointer to the ring-0 mapping of the ring-3 instance (for idTracing). */
250 R0PTRTYPE(struct PDMDEVINSR3 *) pInsR3R0;
251 /** DBGF trace event source handle if tracing is configured. */
252 DBGFTRACEREVTSRC hDbgfTraceEvtSrc;
253 /** The device instance memory. */
254 RTR0MEMOBJ hMemObj;
255 /** The ring-3 mapping object. */
256 RTR0MEMOBJ hMapObj;
257 /** The page memory object for tracking MMIO and I/O port registrations when tracing is configured. */
258 RTR0MEMOBJ hDbgfTraceObj;
259 /** Pointer to the base of the page containing the DBGF tracing tracking structures. */
260 PPDMDEVINSDBGFTRACK paDbgfTraceTrack;
261 /** Index of the next entry to use for tracking. */
262 uint32_t idxDbgfTraceTrackNext;
263 /** Maximum number of records fitting into the single page. */
264 uint32_t cDbgfTraceTrackMax;
265 /** Index into PDMR0PERVM::apDevInstances. */
266 uint32_t idxR0Device;
267} PDMDEVINSINTR0;
268
269
270/**
271 * Private device instance data, raw-mode
272 */
273typedef struct PDMDEVINSINTRC
274{
275 /** Pointer to the VM this instance was created for. */
276 RGPTRTYPE(PVM) pVMRC;
277} PDMDEVINSINTRC;
278
279
280/**
281 * Private device instance data.
282 */
283typedef struct PDMDEVINSINT
284{
285 /** Pointer to the next instance (HC Ptr).
286 * (Head is pointed to by PDM::pDevInstances.) */
287 R3PTRTYPE(PPDMDEVINS) pNextR3;
288 /** Pointer to the next per device instance (HC Ptr).
289 * (Head is pointed to by PDMDEV::pInstances.) */
290 R3PTRTYPE(PPDMDEVINS) pPerDeviceNextR3;
291 /** Pointer to device structure - HC Ptr. */
292 R3PTRTYPE(PPDMDEV) pDevR3;
293 /** Pointer to the list of logical units associated with the device. (FIFO) */
294 R3PTRTYPE(PPDMLUN) pLunsR3;
295 /** Pointer to the asynchronous notification callback set while in
296 * FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
297 R3PTRTYPE(PFNPDMDEVASYNCNOTIFY) pfnAsyncNotify;
298 /** Configuration handle to the instance node. */
299 R3PTRTYPE(PCFGMNODE) pCfgHandle;
300
301 /** R3 pointer to the VM this instance was created for. */
302 PVMR3 pVMR3;
303
304 /** R0 pointer to the VM this instance was created for. */
305 R0PTRTYPE(PVMCC) pVMR0;
306
307 /** RC pointer to the VM this instance was created for. */
308 PVMRC pVMRC;
309
310 /** Flags, see PDMDEVINSINT_FLAGS_XXX. */
311 uint32_t fIntFlags;
312 /** The last IRQ tag (for tracing it thru clearing). */
313 uint32_t uLastIrqTag;
314} PDMDEVINSINT;
315
316/** @name PDMDEVINSINT::fIntFlags
317 * @{ */
318/** Used by pdmR3Load to mark device instances it found in the saved state. */
319#define PDMDEVINSINT_FLAGS_FOUND RT_BIT_32(0)
320/** Indicates that the device hasn't been powered on or resumed.
321 * This is used by PDMR3PowerOn, PDMR3Resume, PDMR3Suspend and PDMR3PowerOff
322 * to make sure each device gets exactly one notification for each of those
323 * events. PDMR3Resume and PDMR3PowerOn also makes use of it to bail out on
324 * a failure (already resumed/powered-on devices are suspended).
325 * PDMR3PowerOff resets this flag once before going through the devices to make sure
326 * every device gets the power off notification even if it was suspended before with
327 * PDMR3Suspend.
328 */
329#define PDMDEVINSINT_FLAGS_SUSPENDED RT_BIT_32(1)
330/** Indicates that the device has been reset already. Used by PDMR3Reset. */
331#define PDMDEVINSINT_FLAGS_RESET RT_BIT_32(2)
332#define PDMDEVINSINT_FLAGS_R0_ENABLED RT_BIT_32(3)
333#define PDMDEVINSINT_FLAGS_RC_ENABLED RT_BIT_32(4)
334/** Set if we've called the ring-0 constructor. */
335#define PDMDEVINSINT_FLAGS_R0_CONTRUCT RT_BIT_32(5)
336/** Set if using non-default critical section. */
337#define PDMDEVINSINT_FLAGS_CHANGED_CRITSECT RT_BIT_32(6)
338/** @} */
339
340
341/**
342 * Private USB device instance data.
343 */
344typedef struct PDMUSBINSINT
345{
346 /** The UUID of this instance. */
347 RTUUID Uuid;
348 /** Pointer to the next instance.
349 * (Head is pointed to by PDM::pUsbInstances.) */
350 R3PTRTYPE(PPDMUSBINS) pNext;
351 /** Pointer to the next per USB device instance.
352 * (Head is pointed to by PDMUSB::pInstances.) */
353 R3PTRTYPE(PPDMUSBINS) pPerDeviceNext;
354
355 /** Pointer to device structure. */
356 R3PTRTYPE(PPDMUSB) pUsbDev;
357
358 /** Pointer to the VM this instance was created for. */
359 PVMR3 pVM;
360 /** Pointer to the list of logical units associated with the device. (FIFO) */
361 R3PTRTYPE(PPDMLUN) pLuns;
362 /** The per instance device configuration. */
363 R3PTRTYPE(PCFGMNODE) pCfg;
364 /** Same as pCfg if the configuration should be deleted when detaching the device. */
365 R3PTRTYPE(PCFGMNODE) pCfgDelete;
366 /** The global device configuration. */
367 R3PTRTYPE(PCFGMNODE) pCfgGlobal;
368
369 /** Pointer to the USB hub this device is attached to.
370 * This is NULL if the device isn't connected to any HUB. */
371 R3PTRTYPE(PPDMUSBHUB) pHub;
372 /** The port number that we're connected to. */
373 uint32_t iPort;
374 /** Indicates that the USB device hasn't been powered on or resumed.
375 * See PDMDEVINSINT_FLAGS_SUSPENDED.
376 * @note Runtime attached USB devices gets a pfnHotPlugged callback rather than
377 * a pfnVMResume one. */
378 bool fVMSuspended;
379 /** Indicates that the USB device has been reset. */
380 bool fVMReset;
381 /** Pointer to the asynchronous notification callback set while in
382 * FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
383 R3PTRTYPE(PFNPDMUSBASYNCNOTIFY) pfnAsyncNotify;
384} PDMUSBINSINT;
385
386
387/**
388 * Private driver instance data.
389 */
390typedef struct PDMDRVINSINT
391{
392 /** Pointer to the driver instance above.
393 * This is NULL for the topmost drive. */
394 R3PTRTYPE(PPDMDRVINS) pUp;
395 /** Pointer to the driver instance below.
396 * This is NULL for the bottommost driver. */
397 R3PTRTYPE(PPDMDRVINS) pDown;
398 /** Pointer to the logical unit this driver chained on. */
399 R3PTRTYPE(PPDMLUN) pLun;
400 /** Pointer to driver structure from which this was instantiated. */
401 R3PTRTYPE(PPDMDRV) pDrv;
402 /** Pointer to the VM this instance was created for, ring-3 context. */
403 PVMR3 pVMR3;
404 /** Pointer to the VM this instance was created for, ring-0 context. */
405 R0PTRTYPE(PVMCC) pVMR0;
406 /** Pointer to the VM this instance was created for, raw-mode context. */
407 PVMRC pVMRC;
408 /** Flag indicating that the driver is being detached and destroyed.
409 * (Helps detect potential recursive detaching.) */
410 bool fDetaching;
411 /** Indicates that the driver hasn't been powered on or resumed.
412 * See PDMDEVINSINT_FLAGS_SUSPENDED. */
413 bool fVMSuspended;
414 /** Indicates that the driver has been reset already. */
415 bool fVMReset;
416 /** Set if allocated on the hyper heap, false if on the ring-3 heap. */
417 bool fHyperHeap;
418 /** Pointer to the asynchronous notification callback set while in
419 * PDMUSBREG::pfnVMSuspend or PDMUSBREG::pfnVMPowerOff. */
420 R3PTRTYPE(PFNPDMDRVASYNCNOTIFY) pfnAsyncNotify;
421 /** Configuration handle to the instance node. */
422 R3PTRTYPE(PCFGMNODE) pCfgHandle;
423 /** Pointer to the ring-0 request handler function. */
424 PFNPDMDRVREQHANDLERR0 pfnReqHandlerR0;
425 /** Pointer to the next instance (starts at PDMDRV::pInstances). */
426 R3PTRTYPE(PPDMDRVINS) pNext;
427} PDMDRVINSINT;
428
429
430/**
431 * Private critical section data.
432 */
433typedef struct PDMCRITSECTINT
434{
435 /** The critical section core which is shared with IPRT.
436 * @note The semaphore is a SUPSEMEVENT. */
437 RTCRITSECT Core;
438 /** Pointer to the next critical section.
439 * This chain is used for device cleanup and the dbgf info item. */
440 R3PTRTYPE(struct PDMCRITSECTINT *) pNext;
441 /** Owner identifier.
442 * This is pDevIns if the owner is a device. Similarly for a driver or service.
443 * PDMR3CritSectInit() sets this to point to the critsect itself. */
444 RTR3PTR pvKey;
445 /** Set if this critical section is the automatically created default
446 * section of a device. */
447 bool fAutomaticDefaultCritsect;
448 /** Set if the critical section is used by a timer or similar.
449 * See PDMR3DevGetCritSect. */
450 bool fUsedByTimerOrSimilar;
451 /** Alignment padding. */
452 bool afPadding[2+4];
453 /** Support driver event semaphore that is scheduled to be signaled upon leaving
454 * the critical section. This is only for Ring-3 and Ring-0. */
455 SUPSEMEVENT volatile hEventToSignal;
456 /** The lock name. */
457 R3PTRTYPE(const char *) pszName;
458 /** The ring-3 pointer to this critical section, for leave queueing. */
459 R3PTRTYPE(PPDMCRITSECT) pSelfR3;
460 /** R0/RC lock contention. */
461 STAMCOUNTER StatContentionRZLock;
462 /** R0/RC lock contention: returning rcBusy or VERR_SEM_BUSY (try). */
463 STAMCOUNTER StatContentionRZLockBusy;
464 /** R0/RC lock contention: Profiling waiting time. */
465 STAMPROFILE StatContentionRZWait;
466 /** R0/RC unlock contention. */
467 STAMCOUNTER StatContentionRZUnlock;
468 /** R3 lock contention. */
469 STAMCOUNTER StatContentionR3;
470 /** R3 lock contention: Profiling waiting time. */
471 STAMPROFILE StatContentionR3Wait;
472 /** Profiling the time the section is locked. */
473 STAMPROFILEADV StatLocked;
474} PDMCRITSECTINT;
475AssertCompileMemberAlignment(PDMCRITSECTINT, StatContentionRZLock, 8);
476/** Pointer to private critical section data. */
477typedef PDMCRITSECTINT *PPDMCRITSECTINT;
478
479/** Special magic value set when we failed to abort entering in ring-0 due to a
480 * timeout, interruption or pending thread termination. */
481#define PDMCRITSECT_MAGIC_FAILED_ABORT UINT32_C(0x0bad0326)
482/** Special magic value set if we detected data/state corruption. */
483#define PDMCRITSECT_MAGIC_CORRUPTED UINT32_C(0x0bad2603)
484
485/** Indicates that the critical section is queued for unlock.
486 * PDMCritSectIsOwner and PDMCritSectIsOwned optimizations. */
487#define PDMCRITSECT_FLAGS_PENDING_UNLOCK RT_BIT_32(17)
488
489
490/**
491 * Private critical section data.
492 */
493typedef struct PDMCRITSECTRWINT
494{
495 /** The read/write critical section core which is shared with IPRT.
496 * @note The semaphores are SUPSEMEVENT and SUPSEMEVENTMULTI. */
497 RTCRITSECTRW Core;
498
499 /** Pointer to the next critical section.
500 * This chain is used for device cleanup and the dbgf info item. */
501 R3PTRTYPE(struct PDMCRITSECTRWINT *) pNext;
502 /** Self pointer. */
503 R3PTRTYPE(PPDMCRITSECTRW) pSelfR3;
504 /** Owner identifier.
505 * This is pDevIns if the owner is a device. Similarly for a driver or service.
506 * PDMR3CritSectRwInit() sets this to point to the critsect itself. */
507 RTR3PTR pvKey;
508 /** The lock name. */
509 R3PTRTYPE(const char *) pszName;
510
511 /** R0/RC write lock contention. */
512 STAMCOUNTER StatContentionRZEnterExcl;
513 /** R0/RC write unlock contention. */
514 STAMCOUNTER StatContentionRZLeaveExcl;
515 /** R0/RC read lock contention. */
516 STAMCOUNTER StatContentionRZEnterShared;
517 /** R0/RC read unlock contention. */
518 STAMCOUNTER StatContentionRZLeaveShared;
519 /** R0/RC writes. */
520 STAMCOUNTER StatRZEnterExcl;
521 /** R0/RC reads. */
522 STAMCOUNTER StatRZEnterShared;
523 /** R3 write lock contention. */
524 STAMCOUNTER StatContentionR3EnterExcl;
525 /** R3 write unlock contention. */
526 STAMCOUNTER StatContentionR3LeaveExcl;
527 /** R3 read lock contention. */
528 STAMCOUNTER StatContentionR3EnterShared;
529 /** R3 writes. */
530 STAMCOUNTER StatR3EnterExcl;
531 /** R3 reads. */
532 STAMCOUNTER StatR3EnterShared;
533 /** Profiling the time the section is write locked. */
534 STAMPROFILEADV StatWriteLocked;
535} PDMCRITSECTRWINT;
536AssertCompileMemberAlignment(PDMCRITSECTRWINT, StatContentionRZEnterExcl, 8);
537AssertCompileMemberAlignment(PDMCRITSECTRWINT, Core.u, 16);
538AssertCompileMemberAlignment(PDMCRITSECTRWINT, Core.u.s.u64State, 8);
539/** Pointer to private critical section data. */
540typedef PDMCRITSECTRWINT *PPDMCRITSECTRWINT;
541
542/** Special magic value we set the structure has become corrupted. */
543#define PDMCRITSECTRW_MAGIC_CORRUPT UINT32_C(0x0bad0620)
544
545
546/**
547 * The usual device/driver/internal/external stuff.
548 */
549typedef enum
550{
551 /** The usual invalid entry. */
552 PDMTHREADTYPE_INVALID = 0,
553 /** Device type. */
554 PDMTHREADTYPE_DEVICE,
555 /** USB Device type. */
556 PDMTHREADTYPE_USB,
557 /** Driver type. */
558 PDMTHREADTYPE_DRIVER,
559 /** Internal type. */
560 PDMTHREADTYPE_INTERNAL,
561 /** External type. */
562 PDMTHREADTYPE_EXTERNAL,
563 /** The usual 32-bit hack. */
564 PDMTHREADTYPE_32BIT_HACK = 0x7fffffff
565} PDMTHREADTYPE;
566
567
568/**
569 * The internal structure for the thread.
570 */
571typedef struct PDMTHREADINT
572{
573 /** The VM pointer. */
574 PVMR3 pVM;
575 /** The event semaphore the thread blocks on when not running. */
576 RTSEMEVENTMULTI BlockEvent;
577 /** The event semaphore the thread sleeps on while running. */
578 RTSEMEVENTMULTI SleepEvent;
579 /** Pointer to the next thread. */
580 R3PTRTYPE(struct PDMTHREAD *) pNext;
581 /** The thread type. */
582 PDMTHREADTYPE enmType;
583} PDMTHREADINT;
584
585
586
587/* Must be included after PDMDEVINSINT is defined. */
588#define PDMDEVINSINT_DECLARED
589#define PDMUSBINSINT_DECLARED
590#define PDMDRVINSINT_DECLARED
591#define PDMCRITSECTINT_DECLARED
592#define PDMCRITSECTRWINT_DECLARED
593#define PDMTHREADINT_DECLARED
594#ifdef ___VBox_pdm_h
595# error "Invalid header PDM order. Include PDMInternal.h before VBox/vmm/pdm.h!"
596#endif
597RT_C_DECLS_END
598#include <VBox/vmm/pdm.h>
599RT_C_DECLS_BEGIN
600
601/**
602 * PDM Logical Unit.
603 *
604 * This typically the representation of a physical port on a
605 * device, like for instance the PS/2 keyboard port on the
606 * keyboard controller device. The LUNs are chained on the
607 * device they belong to (PDMDEVINSINT::pLunsR3).
608 */
609typedef struct PDMLUN
610{
611 /** The LUN - The Logical Unit Number. */
612 RTUINT iLun;
613 /** Pointer to the next LUN. */
614 PPDMLUN pNext;
615 /** Pointer to the top driver in the driver chain. */
616 PPDMDRVINS pTop;
617 /** Pointer to the bottom driver in the driver chain. */
618 PPDMDRVINS pBottom;
619 /** Pointer to the device instance which the LUN belongs to.
620 * Either this is set or pUsbIns is set. Both are never set at the same time. */
621 PPDMDEVINS pDevIns;
622 /** Pointer to the USB device instance which the LUN belongs to. */
623 PPDMUSBINS pUsbIns;
624 /** Pointer to the device base interface. */
625 PPDMIBASE pBase;
626 /** Description of this LUN. */
627 const char *pszDesc;
628} PDMLUN;
629
630
631/**
632 * PDM Device, ring-3.
633 */
634typedef struct PDMDEV
635{
636 /** Pointer to the next device (R3 Ptr). */
637 R3PTRTYPE(PPDMDEV) pNext;
638 /** Device name length. (search optimization) */
639 uint32_t cchName;
640 /** Registration structure. */
641 R3PTRTYPE(const struct PDMDEVREGR3 *) pReg;
642 /** Number of instances. */
643 uint32_t cInstances;
644 /** Pointer to chain of instances (R3 Ptr). */
645 PPDMDEVINSR3 pInstances;
646 /** The search path for raw-mode context modules (';' as separator). */
647 char *pszRCSearchPath;
648 /** The search path for ring-0 context modules (';' as separator). */
649 char *pszR0SearchPath;
650} PDMDEV;
651
652
653#if 0
654/**
655 * PDM Device, ring-0.
656 */
657typedef struct PDMDEVR0
658{
659 /** Pointer to the next device. */
660 R0PTRTYPE(PPDMDEVR0) pNext;
661 /** Device name length. (search optimization) */
662 uint32_t cchName;
663 /** Registration structure. */
664 R3PTRTYPE(const struct PDMDEVREGR0 *) pReg;
665 /** Number of instances. */
666 uint32_t cInstances;
667 /** Pointer to chain of instances. */
668 PPDMDEVINSR0 pInstances;
669} PDMDEVR0;
670#endif
671
672
673/**
674 * PDM USB Device.
675 */
676typedef struct PDMUSB
677{
678 /** Pointer to the next device (R3 Ptr). */
679 R3PTRTYPE(PPDMUSB) pNext;
680 /** Device name length. (search optimization) */
681 RTUINT cchName;
682 /** Registration structure. */
683 R3PTRTYPE(const struct PDMUSBREG *) pReg;
684 /** Next instance number. */
685 uint32_t iNextInstance;
686 /** Pointer to chain of instances (R3 Ptr). */
687 R3PTRTYPE(PPDMUSBINS) pInstances;
688} PDMUSB;
689
690
691/**
692 * PDM Driver.
693 */
694typedef struct PDMDRV
695{
696 /** Pointer to the next device. */
697 PPDMDRV pNext;
698 /** Registration structure. */
699 const struct PDMDRVREG * pReg;
700 /** Current number of instances. */
701 uint32_t cInstances;
702 /** The next instance number. */
703 uint32_t iNextInstance;
704 /** The search path for raw-mode context modules (';' as separator). */
705 char *pszRCSearchPath;
706 /** The search path for ring-0 context modules (';' as separator). */
707 char *pszR0SearchPath;
708 /** Pointer to chain of instances. */
709 PPDMDRVINSR3 pInstances;
710} PDMDRV;
711
712
713/**
714 * PDM IOMMU, shared ring-3.
715 */
716typedef struct PDMIOMMUR3
717{
718 /** IOMMU index. */
719 uint32_t idxIommu;
720 uint32_t uPadding0; /**< Alignment padding.*/
721
722 /** Pointer to the IOMMU device instance - R3. */
723 PPDMDEVINSR3 pDevInsR3;
724 /** @copydoc PDMIOMMUREGR3::pfnMemAccess */
725 DECLR3CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
726 uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContig));
727 /** @copydoc PDMIOMMUREGR3::pfnMemBulkAccess */
728 DECLR3CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
729 uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
730 /** @copydoc PDMIOMMUREGR3::pfnMsiRemap */
731 DECLR3CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
732} PDMIOMMUR3;
733/** Pointer to a PDM IOMMU instance. */
734typedef PDMIOMMUR3 *PPDMIOMMUR3;
735/** Pointer to a const PDM IOMMU instance. */
736typedef const PDMIOMMUR3 *PCPDMIOMMUR3;
737
738
739/**
740 * PDM IOMMU, ring-0.
741 */
742typedef struct PDMIOMMUR0
743{
744 /** IOMMU index. */
745 uint32_t idxIommu;
746 uint32_t uPadding0; /**< Alignment padding.*/
747
748 /** Pointer to IOMMU device instance. */
749 PPDMDEVINSR0 pDevInsR0;
750 /** @copydoc PDMIOMMUREGR3::pfnMemAccess */
751 DECLR0CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
752 uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContig));
753 /** @copydoc PDMIOMMUREGR3::pfnMemBulkAccess */
754 DECLR0CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
755 uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
756 /** @copydoc PDMIOMMUREGR3::pfnMsiRemap */
757 DECLR0CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
758} PDMIOMMUR0;
759/** Pointer to a ring-0 IOMMU data. */
760typedef PDMIOMMUR0 *PPDMIOMMUR0;
761/** Pointer to a const ring-0 IOMMU data. */
762typedef const PDMIOMMUR0 *PCPDMIOMMUR0;
763
764/** Pointer to a PDM IOMMU for the current context. */
765#ifdef IN_RING3
766typedef PPDMIOMMUR3 PPDMIOMMU;
767#else
768typedef PPDMIOMMUR0 PPDMIOMMU;
769#endif
770
771
772/**
773 * PDM registered PIC device.
774 */
775typedef struct PDMPIC
776{
777 /** Pointer to the PIC device instance - R3. */
778 PPDMDEVINSR3 pDevInsR3;
779 /** @copydoc PDMPICREG::pfnSetIrq */
780 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
781 /** @copydoc PDMPICREG::pfnGetInterrupt */
782 DECLR3CALLBACKMEMBER(int, pfnGetInterruptR3,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
783
784 /** Pointer to the PIC device instance - R0. */
785 PPDMDEVINSR0 pDevInsR0;
786 /** @copydoc PDMPICREG::pfnSetIrq */
787 DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
788 /** @copydoc PDMPICREG::pfnGetInterrupt */
789 DECLR0CALLBACKMEMBER(int, pfnGetInterruptR0,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
790
791 /** Pointer to the PIC device instance - RC. */
792 PPDMDEVINSRC pDevInsRC;
793 /** @copydoc PDMPICREG::pfnSetIrq */
794 DECLRCCALLBACKMEMBER(void, pfnSetIrqRC,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
795 /** @copydoc PDMPICREG::pfnGetInterrupt */
796 DECLRCCALLBACKMEMBER(int, pfnGetInterruptRC,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
797 /** Alignment padding. */
798 RTRCPTR RCPtrPadding;
799} PDMPIC;
800
801
802/**
803 * PDM IC (Interrupt Controller), shared ring-3.
804 */
805typedef struct PDMICR3
806{
807 /** Pointer to the interrupt controller instance - R3 Ptr. */
808 PPDMDEVINSR3 pDevInsR3;
809 union
810 {
811#if defined(VBOX_VMM_TARGET_X86) || defined(VBOX_VMM_TARGET_AGNOSTIC)
812 struct
813 {
814 /** The type of APIC backend. */
815 PDMAPICBACKENDTYPE enmKind;
816 uint32_t uPadding;
817 /** The APIC backend. */
818 PDMAPICBACKENDR3 ApicBackend;
819 } x86;
820#endif
821#ifdef VBOX_VMM_TARGET_ARMV8
822 struct
823 {
824 /** The type of GIC backend. */
825 PDMGICBACKENDTYPE enmKind;
826 uint32_t uPadding;
827 /** The APIC backend. */
828 PDMGICBACKENDR3 GicBackend;
829 } armv8;
830#endif
831 uint8_t abPadding[256-8];
832 } u;
833} PDMICR3;
834AssertCompileSizeAlignment(PDMICR3, 8);
835
836/**
837 * PDM IC (Interrupt Controller), ring-0.
838 */
839typedef struct PDMICR0
840{
841 /** Pointer to the interrupt controller instance - R0 Ptr. */
842 PPDMDEVINSR0 pDevInsR0;
843 union
844 {
845#if defined(VBOX_VMM_TARGET_X86) || defined(VBOX_VMM_TARGET_AGNOSTIC)
846 struct
847 {
848 /** The APIC backend. */
849 PDMAPICBACKENDR0 ApicBackend;
850 } x86;
851#endif
852 /** Padding to keep alignment common between x86 and arm (there's no ring-0
853 * armv8 code. */
854 uint8_t abPadding[256-8];
855 } u;
856} PDMICR0;
857AssertCompileSizeAlignment(PDMICR0, 8);
858
859/**
860 * PDM IC (Interrupt Controller), raw-mode context.
861 */
862typedef struct PDMICRC
863{
864 /** Pointer to the interrupt controller instance - RC Ptr. */
865 PPDMDEVINSRC pDevInsR0;
866 RTRCPTR avPadding;
867 union
868 {
869#if defined(VBOX_VMM_TARGET_X86) || defined(VBOX_VMM_TARGET_AGNOSTIC)
870 struct
871 {
872 /** The APIC backend. */
873 PDMAPICBACKENDRC ApicBackend;
874 } x86;
875#endif
876 /** Padding to keep alignment common between x86 and arm (there's no ring-context
877 * armv8 code. */
878 uint8_t abPadding[256-4-4];
879 } u;
880} PDMICRC;
881AssertCompileSizeAlignment(PDMICRC, 8);
882
883/**
884 * PDM registered I/O APIC device.
885 */
886typedef struct PDMIOAPIC
887{
888 /** Pointer to the I/O APIC device instance - R3 Ptr. */
889 PPDMDEVINSR3 pDevInsR3;
890 /** @copydoc PDMIOAPICREG::pfnSetIrq */
891 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
892 /** @copydoc PDMIOAPICREG::pfnSendMsi */
893 DECLR3CALLBACKMEMBER(void, pfnSendMsiR3,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
894 /** @copydoc PDMIOAPICREG::pfnSetEoi */
895 DECLR3CALLBACKMEMBER(void, pfnSetEoiR3,(PPDMDEVINS pDevIns, uint8_t u8Vector));
896
897 /** Pointer to the I/O APIC device instance - R0. */
898 PPDMDEVINSR0 pDevInsR0;
899 /** @copydoc PDMIOAPICREG::pfnSetIrq */
900 DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
901 /** @copydoc PDMIOAPICREG::pfnSendMsi */
902 DECLR0CALLBACKMEMBER(void, pfnSendMsiR0,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
903 /** @copydoc PDMIOAPICREG::pfnSetEoi */
904 DECLR0CALLBACKMEMBER(void, pfnSetEoiR0,(PPDMDEVINS pDevIns, uint8_t u8Vector));
905
906 /** Pointer to the I/O APIC device instance - RC Ptr. */
907 PPDMDEVINSRC pDevInsRC;
908 /** @copydoc PDMIOAPICREG::pfnSetIrq */
909 DECLRCCALLBACKMEMBER(void, pfnSetIrqRC,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
910 /** @copydoc PDMIOAPICREG::pfnSendMsi */
911 DECLRCCALLBACKMEMBER(void, pfnSendMsiRC,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
912 /** @copydoc PDMIOAPICREG::pfnSendMsi */
913 DECLRCCALLBACKMEMBER(void, pfnSetEoiRC,(PPDMDEVINS pDevIns, uint8_t u8Vector));
914} PDMIOAPIC;
915/** Pointer to a PDM IOAPIC instance. */
916typedef PDMIOAPIC *PPDMIOAPIC;
917/** Pointer to a const PDM IOAPIC instance. */
918typedef PDMIOAPIC const *PCPDMIOAPIC;
919
920/** Maximum number of PCI busses for a VM. */
921#define PDM_PCI_BUSSES_MAX 8
922/** Maximum number of IOMMUs (at most one per PCI bus). */
923#define PDM_IOMMUS_MAX PDM_PCI_BUSSES_MAX
924
925
926#ifdef IN_RING3
927/**
928 * PDM registered firmware device.
929 */
930typedef struct PDMFW
931{
932 /** Pointer to the firmware device instance. */
933 PPDMDEVINSR3 pDevIns;
934 /** Copy of the registration structure. */
935 PDMFWREG Reg;
936} PDMFW;
937/** Pointer to a firmware instance. */
938typedef PDMFW *PPDMFW;
939#endif
940
941
942/**
943 * PDM PCI bus instance.
944 */
945typedef struct PDMPCIBUS
946{
947 /** PCI bus number. */
948 uint32_t iBus;
949 uint32_t uPadding0; /**< Alignment padding.*/
950
951 /** Pointer to PCI bus device instance. */
952 PPDMDEVINSR3 pDevInsR3;
953 /** @copydoc PDMPCIBUSREGR3::pfnSetIrqR3 */
954 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
955
956 /** @copydoc PDMPCIBUSREGR3::pfnRegisterR3 */
957 DECLR3CALLBACKMEMBER(int, pfnRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
958 uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
959 /** @copydoc PDMPCIBUSREGR3::pfnRegisterMsiR3 */
960 DECLR3CALLBACKMEMBER(int, pfnRegisterMsi,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
961 /** @copydoc PDMPCIBUSREGR3::pfnIORegionRegisterR3 */
962 DECLR3CALLBACKMEMBER(int, pfnIORegionRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
963 RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
964 uint64_t hHandle, PFNPCIIOREGIONMAP pfnCallback));
965 /** @copydoc PDMPCIBUSREGR3::pfnInterceptConfigAccesses */
966 DECLR3CALLBACKMEMBER(void, pfnInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
967 PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
968 /** @copydoc PDMPCIBUSREGR3::pfnConfigWrite */
969 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
970 uint32_t uAddress, unsigned cb, uint32_t u32Value));
971 /** @copydoc PDMPCIBUSREGR3::pfnConfigRead */
972 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
973 uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
974} PDMPCIBUS;
975/** Pointer to a PDM PCI Bus instance. */
976typedef PDMPCIBUS *PPDMPCIBUS;
977/** Pointer to a const PDM PCI Bus instance. */
978typedef const PDMPCIBUS *PCPDMPCIBUS;
979
980
981/**
982 * Ring-0 PDM PCI bus instance data.
983 */
984typedef struct PDMPCIBUSR0
985{
986 /** PCI bus number. */
987 uint32_t iBus;
988 uint32_t uPadding0; /**< Alignment padding.*/
989 /** Pointer to PCI bus device instance. */
990 PPDMDEVINSR0 pDevInsR0;
991 /** @copydoc PDMPCIBUSREGR0::pfnSetIrq */
992 DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
993} PDMPCIBUSR0;
994/** Pointer to the ring-0 PCI bus data. */
995typedef PDMPCIBUSR0 *PPDMPCIBUSR0;
996/** Pointer to the const ring-0 PCI bus data. */
997typedef const PDMPCIBUSR0 *PCPDMPCIBUSR0;
998
999
1000#ifdef IN_RING3
1001/**
1002 * PDM registered DMAC (DMA Controller) device.
1003 */
1004typedef struct PDMDMAC
1005{
1006 /** Pointer to the DMAC device instance. */
1007 PPDMDEVINSR3 pDevIns;
1008 /** Copy of the registration structure. */
1009 PDMDMACREG Reg;
1010} PDMDMAC;
1011
1012
1013/**
1014 * PDM registered RTC (Real Time Clock) device.
1015 */
1016typedef struct PDMRTC
1017{
1018 /** Pointer to the RTC device instance. */
1019 PPDMDEVINSR3 pDevIns;
1020 /** Copy of the registration structure. */
1021 PDMRTCREG Reg;
1022} PDMRTC;
1023
1024#endif /* IN_RING3 */
1025
1026/**
1027 * Module type.
1028 */
1029typedef enum PDMMODTYPE
1030{
1031 /** Raw-mode (RC) context module. */
1032 PDMMOD_TYPE_RC,
1033 /** Ring-0 (host) context module. */
1034 PDMMOD_TYPE_R0,
1035 /** Ring-3 (host) context module. */
1036 PDMMOD_TYPE_R3
1037} PDMMODTYPE;
1038
1039
1040/** The module name length including the terminator. */
1041#define PDMMOD_NAME_LEN 32
1042
1043/**
1044 * Loaded module instance.
1045 */
1046typedef struct PDMMOD
1047{
1048 /** Module name. This is used for referring to
1049 * the module internally, sort of like a handle. */
1050 char szName[PDMMOD_NAME_LEN];
1051 /** Module type. */
1052 PDMMODTYPE eType;
1053 /** Loader module handle. Not used for R0 modules. */
1054 RTLDRMOD hLdrMod;
1055 /** Loaded address.
1056 * This is the 'handle' for R0 modules. */
1057 RTUINTPTR ImageBase;
1058 /** Old loaded address.
1059 * This is used during relocation of GC modules. Not used for R0 modules. */
1060 RTUINTPTR OldImageBase;
1061 /** Where the R3 HC bits are stored.
1062 * This can be equal to ImageBase but doesn't have to. Not used for R0 modules. */
1063 void *pvBits;
1064
1065 /** Pointer to next module. */
1066 struct PDMMOD *pNext;
1067 /** Module filename. */
1068 char szFilename[1];
1069} PDMMOD;
1070/** Pointer to loaded module instance. */
1071typedef PDMMOD *PPDMMOD;
1072
1073
1074
1075/** Max number of items in a queue. */
1076#define PDMQUEUE_MAX_ITEMS _16K
1077/** Max item size. */
1078#define PDMQUEUE_MAX_ITEM_SIZE _1M
1079/** Max total queue item size for ring-0 capable queues. */
1080#define PDMQUEUE_MAX_TOTAL_SIZE_R0 _8M
1081/** Max total queue item size for ring-3 only queues. */
1082#define PDMQUEUE_MAX_TOTAL_SIZE_R3 _32M
1083
1084/**
1085 * Queue type.
1086 */
1087typedef enum PDMQUEUETYPE
1088{
1089 /** Device consumer. */
1090 PDMQUEUETYPE_DEV = 1,
1091 /** Driver consumer. */
1092 PDMQUEUETYPE_DRV,
1093 /** Internal consumer. */
1094 PDMQUEUETYPE_INTERNAL,
1095 /** External consumer. */
1096 PDMQUEUETYPE_EXTERNAL
1097} PDMQUEUETYPE;
1098
1099/**
1100 * PDM Queue.
1101 */
1102typedef struct PDMQUEUE
1103{
1104 /** Magic value (PDMQUEUE_MAGIC). */
1105 uint32_t u32Magic;
1106 /** Item size (bytes). */
1107 uint32_t cbItem;
1108 /** Number of items in the queue. */
1109 uint32_t cItems;
1110 /** Offset of the the queue items relative to the PDMQUEUE structure. */
1111 uint32_t offItems;
1112
1113 /** Interval timer. Only used if cMilliesInterval is non-zero. */
1114 TMTIMERHANDLE hTimer;
1115 /** The interval between checking the queue for events.
1116 * The realtime timer below is used to do the waiting.
1117 * If 0, the queue will use the VM_FF_PDM_QUEUE forced action. */
1118 uint32_t cMilliesInterval;
1119
1120 /** This is VINF_SUCCESS if the queue is okay, error status if not. */
1121 int32_t rcOkay;
1122 uint32_t u32Padding;
1123
1124 /** Queue type. */
1125 PDMQUEUETYPE enmType;
1126 /** Type specific data. */
1127 union
1128 {
1129 /** PDMQUEUETYPE_DEV */
1130 struct
1131 {
1132 /** Pointer to consumer function. */
1133 R3PTRTYPE(PFNPDMQUEUEDEV) pfnCallback;
1134 /** Pointer to the device instance owning the queue. */
1135 R3PTRTYPE(PPDMDEVINS) pDevIns;
1136 } Dev;
1137 /** PDMQUEUETYPE_DRV */
1138 struct
1139 {
1140 /** Pointer to consumer function. */
1141 R3PTRTYPE(PFNPDMQUEUEDRV) pfnCallback;
1142 /** Pointer to the driver instance owning the queue. */
1143 R3PTRTYPE(PPDMDRVINS) pDrvIns;
1144 } Drv;
1145 /** PDMQUEUETYPE_INTERNAL */
1146 struct
1147 {
1148 /** Pointer to consumer function. */
1149 R3PTRTYPE(PFNPDMQUEUEINT) pfnCallback;
1150 } Int;
1151 /** PDMQUEUETYPE_EXTERNAL */
1152 struct
1153 {
1154 /** Pointer to consumer function. */
1155 R3PTRTYPE(PFNPDMQUEUEEXT) pfnCallback;
1156 /** Pointer to user argument. */
1157 R3PTRTYPE(void *) pvUser;
1158 } Ext;
1159 struct
1160 {
1161 /** Generic callback pointer. */
1162 RTR3PTR pfnCallback;
1163 /** Generic owner pointer. */
1164 RTR3PTR pvOwner;
1165 } Gen;
1166 } u;
1167
1168 /** Unique queue name. */
1169 char szName[40];
1170
1171 /** LIFO of pending items (item index), UINT32_MAX if empty. */
1172 uint32_t volatile iPending;
1173
1174 /** State: Pending items. */
1175 uint32_t volatile cStatPending;
1176 /** Stat: Times PDMQueueAlloc fails. */
1177 STAMCOUNTER StatAllocFailures;
1178 /** Stat: PDMQueueInsert calls. */
1179 STAMCOUNTER StatInsert;
1180 /** Stat: Queue flushes. */
1181 STAMCOUNTER StatFlush;
1182 /** Stat: Queue flushes with pending items left over. */
1183 STAMCOUNTER StatFlushLeftovers;
1184 /** State: Profiling the flushing. */
1185 STAMPROFILE StatFlushPrf;
1186 uint64_t au64Padding[3];
1187
1188 /** Allocation bitmap: Set bits means free, clear means allocated. */
1189 RT_FLEXIBLE_ARRAY_EXTENSION
1190 uint64_t bmAlloc[RT_FLEXIBLE_ARRAY];
1191 /* The items follows after the end of the bitmap */
1192} PDMQUEUE;
1193AssertCompileMemberAlignment(PDMQUEUE, bmAlloc, 64);
1194/** Pointer to a PDM Queue. */
1195typedef struct PDMQUEUE *PPDMQUEUE;
1196
1197/** Magic value PDMQUEUE::u32Magic (Bud Powell). */
1198#define PDMQUEUE_MAGIC UINT32_C(0x19240927)
1199/** Magic value PDMQUEUE::u32Magic after destroy. */
1200#define PDMQUEUE_MAGIC_DEAD UINT32_C(0x19660731)
1201
1202/** @name PDM::fQueueFlushing
1203 * @{ */
1204/** Used to make sure only one EMT will flush the queues.
1205 * Set when an EMT is flushing queues, clear otherwise. */
1206#define PDM_QUEUE_FLUSH_FLAG_ACTIVE_BIT 0
1207/** Indicating there are queues with items pending.
1208 * This is make sure we don't miss inserts happening during flushing. The FF
1209 * cannot be used for this since it has to be cleared immediately to prevent
1210 * other EMTs from spinning. */
1211#define PDM_QUEUE_FLUSH_FLAG_PENDING_BIT 1
1212/** @} */
1213
1214/**
1215 * Ring-0 queue
1216 *
1217 * @author bird (2022-02-04)
1218 */
1219typedef struct PDMQUEUER0
1220{
1221 /** Pointer to the shared queue data. */
1222 R0PTRTYPE(PPDMQUEUE) pQueue;
1223 /** The memory allocation. */
1224 RTR0MEMOBJ hMemObj;
1225 /** The ring-3 mapping object. */
1226 RTR0MEMOBJ hMapObj;
1227 /** The owner pointer. This is NULL if not allocated. */
1228 RTR0PTR pvOwner;
1229 /** Queue item size. */
1230 uint32_t cbItem;
1231 /** Number of queue items. */
1232 uint32_t cItems;
1233 /** Offset of the the queue items relative to the PDMQUEUE structure. */
1234 uint32_t offItems;
1235 uint32_t u32Reserved;
1236} PDMQUEUER0;
1237
1238
1239/** @name PDM task structures.
1240 * @{ */
1241
1242/**
1243 * A asynchronous user mode task.
1244 */
1245typedef struct PDMTASK
1246{
1247 /** Task owner type. */
1248 PDMTASKTYPE volatile enmType;
1249 /** Queue flags. */
1250 uint32_t volatile fFlags;
1251 /** User argument for the callback. */
1252 R3PTRTYPE(void *) volatile pvUser;
1253 /** The callback (will be cast according to enmType before callout). */
1254 R3PTRTYPE(PFNRT) volatile pfnCallback;
1255 /** The owner identifier. */
1256 R3PTRTYPE(void *) volatile pvOwner;
1257 /** Task name. */
1258 R3PTRTYPE(const char *) pszName;
1259 /** Number of times already triggered when PDMTaskTrigger was called. */
1260 uint32_t volatile cAlreadyTrigged;
1261 /** Number of runs. */
1262 uint32_t cRuns;
1263} PDMTASK;
1264/** Pointer to a PDM task. */
1265typedef PDMTASK *PPDMTASK;
1266
1267/**
1268 * A task set.
1269 *
1270 * This is served by one task executor thread.
1271 */
1272typedef struct PDMTASKSET
1273{
1274 /** Magic value (PDMTASKSET_MAGIC). */
1275 uint32_t u32Magic;
1276 /** Set if this task set works for ring-0 and raw-mode. */
1277 bool fRZEnabled;
1278 /** Number of allocated taks. */
1279 uint8_t volatile cAllocated;
1280 /** Base handle value for this set. */
1281 uint16_t uHandleBase;
1282 /** The task executor thread. */
1283 R3PTRTYPE(RTTHREAD) hThread;
1284 /** Event semaphore for waking up the thread when fRZEnabled is set. */
1285 SUPSEMEVENT hEventR0;
1286 /** Event semaphore for waking up the thread when fRZEnabled is clear. */
1287 R3PTRTYPE(RTSEMEVENT) hEventR3;
1288 /** The VM pointer. */
1289 PVM pVM;
1290 /** Padding so fTriggered is in its own cacheline. */
1291 uint64_t au64Padding2[3];
1292
1293 /** Bitmask of triggered tasks. */
1294 uint64_t volatile fTriggered;
1295 /** Shutdown thread indicator. */
1296 bool volatile fShutdown;
1297 /** Padding. */
1298 bool volatile afPadding3[3];
1299 /** Task currently running, UINT32_MAX if idle. */
1300 uint32_t volatile idxRunning;
1301 /** Padding so fTriggered and fShutdown are in their own cacheline. */
1302 uint64_t volatile au64Padding3[6];
1303
1304 /** The individual tasks. (Unallocated tasks have NULL pvOwner.) */
1305 PDMTASK aTasks[64];
1306} PDMTASKSET;
1307AssertCompileMemberAlignment(PDMTASKSET, fTriggered, 64);
1308AssertCompileMemberAlignment(PDMTASKSET, aTasks, 64);
1309/** Magic value for PDMTASKSET::u32Magic (Quincy Delight Jones Jr.). */
1310#define PDMTASKSET_MAGIC UINT32_C(0x19330314)
1311/** Pointer to a task set. */
1312typedef PDMTASKSET *PPDMTASKSET;
1313
1314/** @} */
1315
1316
1317/** @name PDM Network Shaper
1318 * @{ */
1319
1320/**
1321 * Bandwidth group.
1322 */
1323typedef struct PDMNSBWGROUP
1324{
1325 /** Critical section protecting all members below. */
1326 PDMCRITSECT Lock;
1327 /** List of filters in this group (PDMNSFILTER). */
1328 RTLISTANCHORR3 FilterList;
1329 /** Reference counter - How many filters are associated with this group. */
1330 volatile uint32_t cRefs;
1331 uint32_t uPadding1;
1332 /** The group name. */
1333 char szName[PDM_NET_SHAPER_MAX_NAME_LEN + 1];
1334 /** Maximum number of bytes filters are allowed to transfer. */
1335 volatile uint64_t cbPerSecMax;
1336 /** Number of bytes we are allowed to transfer in one burst. */
1337 volatile uint32_t cbBucket;
1338 /** Number of bytes we were allowed to transfer at the last update. */
1339 volatile uint32_t cbTokensLast;
1340 /** Timestamp of the last update */
1341 volatile uint64_t tsUpdatedLast;
1342 /** Number of times a filter was choked. */
1343 volatile uint64_t cTotalChokings;
1344 /** Pad the structure to a multiple of 64 bytes. */
1345 uint64_t au64Padding[1];
1346} PDMNSBWGROUP;
1347AssertCompileSizeAlignment(PDMNSBWGROUP, 64);
1348/** Pointer to a bandwidth group. */
1349typedef PDMNSBWGROUP *PPDMNSBWGROUP;
1350
1351/** @} */
1352
1353
1354/**
1355 * Queue device helper task operation.
1356 */
1357typedef enum PDMDEVHLPTASKOP
1358{
1359 /** The usual invalid 0 entry. */
1360 PDMDEVHLPTASKOP_INVALID = 0,
1361 /** IsaSetIrq, IoApicSetIrq */
1362 PDMDEVHLPTASKOP_ISA_SET_IRQ,
1363 /** PciSetIrq */
1364 PDMDEVHLPTASKOP_PCI_SET_IRQ,
1365 /** PciSetIrq */
1366 PDMDEVHLPTASKOP_IOAPIC_SET_IRQ,
1367 /** IoApicSendMsi */
1368 PDMDEVHLPTASKOP_IOAPIC_SEND_MSI,
1369 /** IoApicSettEoi */
1370 PDMDEVHLPTASKOP_IOAPIC_SET_EOI,
1371 /** The usual 32-bit hack. */
1372 PDMDEVHLPTASKOP_32BIT_HACK = 0x7fffffff
1373} PDMDEVHLPTASKOP;
1374
1375/**
1376 * Queued Device Helper Task.
1377 */
1378typedef struct PDMDEVHLPTASK
1379{
1380 /** The queue item core (don't touch). */
1381 PDMQUEUEITEMCORE Core;
1382 /** Pointer to the device instance (R3 Ptr). */
1383 PPDMDEVINSR3 pDevInsR3;
1384 /** This operation to perform. */
1385 PDMDEVHLPTASKOP enmOp;
1386#if HC_ARCH_BITS == 64
1387 uint32_t Alignment0;
1388#endif
1389 /** Parameters to the operation. */
1390 union PDMDEVHLPTASKPARAMS
1391 {
1392 /**
1393 * PDMDEVHLPTASKOP_ISA_SET_IRQ and PDMDEVHLPTASKOP_IOAPIC_SET_IRQ.
1394 */
1395 struct PDMDEVHLPTASKISASETIRQ
1396 {
1397 /** The bus:device:function of the device initiating the IRQ. Can be NIL_PCIBDF. */
1398 PCIBDF uBusDevFn;
1399 /** The IRQ */
1400 int iIrq;
1401 /** The new level. */
1402 int iLevel;
1403 /** The IRQ tag and source. */
1404 uint32_t uTagSrc;
1405 } IsaSetIrq, IoApicSetIrq;
1406
1407 /**
1408 * PDMDEVHLPTASKOP_PCI_SET_IRQ
1409 */
1410 struct PDMDEVHLPTASKPCISETIRQ
1411 {
1412 /** Index of the PCI device (into PDMDEVINSR3::apPciDevs). */
1413 uint32_t idxPciDev;
1414 /** The IRQ */
1415 int32_t iIrq;
1416 /** The new level. */
1417 int32_t iLevel;
1418 /** The IRQ tag and source. */
1419 uint32_t uTagSrc;
1420 } PciSetIrq;
1421
1422 /**
1423 * PDMDEVHLPTASKOP_IOAPIC_SEND_MSI
1424 */
1425 struct PDMDEVHLPTASKIOAPICSENDMSI
1426 {
1427 /** The bus:device:function of the device sending the MSI. */
1428 PCIBDF uBusDevFn;
1429 /** The MSI. */
1430 MSIMSG Msi;
1431 /** The IRQ tag and source. */
1432 uint32_t uTagSrc;
1433 } IoApicSendMsi;
1434
1435 /**
1436 * PDMDEVHLPTASKOP_IOAPIC_SET_EOI
1437 */
1438 struct PDMDEVHLPTASKIOAPICSETEOI
1439 {
1440 /** The vector corresponding to the EOI. */
1441 uint8_t uVector;
1442 } IoApicSetEoi;
1443
1444 /** Expanding the structure. */
1445 uint64_t au64[3];
1446 } u;
1447} PDMDEVHLPTASK;
1448/** Pointer to a queued Device Helper Task. */
1449typedef PDMDEVHLPTASK *PPDMDEVHLPTASK;
1450/** Pointer to a const queued Device Helper Task. */
1451typedef const PDMDEVHLPTASK *PCPDMDEVHLPTASK;
1452
1453
1454
1455/**
1456 * An USB hub registration record.
1457 */
1458typedef struct PDMUSBHUB
1459{
1460 /** The USB versions this hub support.
1461 * Note that 1.1 hubs can take on 2.0 devices. */
1462 uint32_t fVersions;
1463 /** The number of ports on the hub. */
1464 uint32_t cPorts;
1465 /** The number of available ports (0..cPorts). */
1466 uint32_t cAvailablePorts;
1467 /** The driver instance of the hub. */
1468 PPDMDRVINS pDrvIns;
1469 /** Copy of the to the registration structure. */
1470 PDMUSBHUBREG Reg;
1471
1472 /** Pointer to the next hub in the list. */
1473 struct PDMUSBHUB *pNext;
1474} PDMUSBHUB;
1475
1476/** Pointer to a const USB HUB registration record. */
1477typedef const PDMUSBHUB *PCPDMUSBHUB;
1478
1479/** Pointer to a PDM Async I/O template. */
1480typedef struct PDMASYNCCOMPLETIONTEMPLATE *PPDMASYNCCOMPLETIONTEMPLATE;
1481
1482/** Pointer to the main PDM Async completion endpoint class. */
1483typedef struct PDMASYNCCOMPLETIONEPCLASS *PPDMASYNCCOMPLETIONEPCLASS;
1484
1485/** Pointer to the global block cache structure. */
1486typedef struct PDMBLKCACHEGLOBAL *PPDMBLKCACHEGLOBAL;
1487
1488/**
1489 * PDM VMCPU Instance data.
1490 * Changes to this must checked against the padding of the pdm union in VMCPU!
1491 */
1492typedef struct PDMCPU
1493{
1494 /** The number of entries in the apQueuedCritSectsLeaves table that's currently
1495 * in use. */
1496 uint32_t cQueuedCritSectLeaves;
1497 uint32_t uPadding0; /**< Alignment padding.*/
1498 /** Critical sections queued in RC/R0 because of contention preventing leave to
1499 * complete. (R3 Ptrs)
1500 * We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1501 R3PTRTYPE(PPDMCRITSECT) apQueuedCritSectLeaves[8];
1502
1503 /** The number of entries in the apQueuedCritSectRwExclLeaves table that's
1504 * currently in use. */
1505 uint32_t cQueuedCritSectRwExclLeaves;
1506 uint32_t uPadding1; /**< Alignment padding.*/
1507 /** Read/write critical sections queued in RC/R0 because of contention
1508 * preventing exclusive leave to complete. (R3 Ptrs)
1509 * We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1510 R3PTRTYPE(PPDMCRITSECTRW) apQueuedCritSectRwExclLeaves[8];
1511
1512 /** The number of entries in the apQueuedCritSectsRwShrdLeaves table that's
1513 * currently in use. */
1514 uint32_t cQueuedCritSectRwShrdLeaves;
1515 uint32_t uPadding2; /**< Alignment padding.*/
1516 /** Read/write critical sections queued in RC/R0 because of contention
1517 * preventing shared leave to complete. (R3 Ptrs)
1518 * We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1519 R3PTRTYPE(PPDMCRITSECTRW) apQueuedCritSectRwShrdLeaves[8];
1520} PDMCPU;
1521
1522
1523/** Max number of ring-0 device instances. */
1524#define PDM_MAX_RING0_DEVICE_INSTANCES 190
1525
1526
1527/**
1528 * PDM VM Instance data.
1529 * Changes to this must checked against the padding of the cfgm union in VM!
1530 */
1531typedef struct PDM
1532{
1533 /** The PDM lock.
1534 * This is used to protect everything that deals with interrupts, i.e.
1535 * the PIC, APIC, IOAPIC and PCI devices plus some PDM functions. */
1536 PDMCRITSECT CritSect;
1537 /** The NOP critical section.
1538 * This is a dummy critical section that will not do any thread
1539 * serialization but instead let all threads enter immediately and
1540 * concurrently. */
1541 PDMCRITSECT NopCritSect;
1542 /** Critical read/write section protecting the core list: devices,
1543 * usb devices, drivers.
1544 * @note The PDMUSERPERVM::ListCritSect lock covers queues and the stuff in
1545 * PDMUSERPERVM. */
1546 RTCRITSECTRW CoreListCritSectRw;
1547
1548 /** The ring-0 capable task sets (max 128). */
1549 PDMTASKSET aTaskSets[2];
1550 /** Pointer to task sets (max 512). */
1551 R3PTRTYPE(PPDMTASKSET) apTaskSets[8];
1552
1553 /** PCI Buses. */
1554 PDMPCIBUS aPciBuses[PDM_PCI_BUSSES_MAX];
1555 /** IOMMU devices. */
1556 PDMIOMMUR3 aIommus[PDM_IOMMUS_MAX];
1557 /** The register PIC device. */
1558 PDMPIC Pic;
1559 /** The registered IC device. */
1560 PDMICR3 Ic;
1561 /** The registered I/O APIC device. */
1562 PDMIOAPIC IoApic;
1563 /** The registered HPET device. */
1564 PPDMDEVINSR3 pHpet;
1565
1566 /** List of registered devices. (FIFO) */
1567 R3PTRTYPE(PPDMDEV) pDevs;
1568 /** List of devices instances. (FIFO) */
1569 PPDMDEVINSR3 pDevInstances;
1570 /** This runs parallel to PDMR0PERVM::apDevInstances and is used with
1571 * physical access handlers to get the ring-3 device instance for passing down
1572 * as uUser. */
1573 PPDMDEVINSR3 apDevRing0Instances[PDM_MAX_RING0_DEVICE_INSTANCES];
1574
1575 /** List of registered USB devices. (FIFO) */
1576 R3PTRTYPE(PPDMUSB) pUsbDevs;
1577 /** List of USB devices instances. (FIFO) */
1578 R3PTRTYPE(PPDMUSBINS) pUsbInstances;
1579 /** List of registered drivers. (FIFO) */
1580 R3PTRTYPE(PPDMDRV) pDrvs;
1581 /** The registered firmware device (can be NULL). */
1582 R3PTRTYPE(PPDMFW) pFirmware;
1583 /** The registered DMAC device. */
1584 R3PTRTYPE(PPDMDMAC) pDmac;
1585 /** The registered RTC device. */
1586 R3PTRTYPE(PPDMRTC) pRtc;
1587 /** The registered USB HUBs. (FIFO)
1588 * @note Protected by CoreListCritSectRw. */
1589 R3PTRTYPE(PPDMUSBHUB) pUsbHubs;
1590
1591 /** @name Queues
1592 * @note Protected by PDMUSERPERVM::ListCritSect.
1593 * @{ */
1594 /** Number of ring-0 capable queues in apQueues. */
1595 uint32_t cRing0Queues;
1596 uint32_t u32Padding1;
1597 /** Array of ring-0 capable queues running in parallel to PDMR0PERVM::aQueues. */
1598 R3PTRTYPE(PPDMQUEUE) apRing0Queues[16];
1599
1600 /** Number of ring-3 only queues.
1601 * PDMUSERPERVM::ListCritSect protects this and the next two members. */
1602 uint32_t cRing3Queues;
1603 /** The allocation size of the ring-3 queue handle table. */
1604 uint32_t cRing3QueuesAlloc;
1605 /** Handle table for the ring-3 only queues. */
1606 R3PTRTYPE(PPDMQUEUE *) papRing3Queues;
1607
1608 /** Queue in which devhlp tasks are queued for R3 execution. */
1609 PDMQUEUEHANDLE hDevHlpQueue;
1610 /** Bitmask controlling the queue flushing.
1611 * See PDM_QUEUE_FLUSH_FLAG_ACTIVE and PDM_QUEUE_FLUSH_FLAG_PENDING. */
1612 uint32_t volatile fQueueFlushing;
1613 /** @} */
1614
1615 /** The current IRQ tag (tracing purposes). */
1616 uint32_t volatile uIrqTag;
1617
1618 /** Pending reset flags (PDMVMRESET_F_XXX). */
1619 uint32_t volatile fResetFlags;
1620
1621 /** Set by pdmR3LoadExec for use in assertions. */
1622 bool fStateLoaded;
1623 /** Alignment padding. */
1624 bool afPadding1[3];
1625
1626 /** The tracing ID of the next device instance.
1627 *
1628 * @remarks We keep the device tracing ID seperate from the rest as these are
1629 * then more likely to end up with the same ID from one run to
1630 * another, making analysis somewhat easier. Drivers and USB devices
1631 * are more volatile and can be changed at runtime, thus these are much
1632 * less likely to remain stable, so just heap them all together. */
1633 uint32_t idTracingDev;
1634 /** The tracing ID of the next driver instance, USB device instance or other
1635 * PDM entity requiring an ID. */
1636 uint32_t idTracingOther;
1637
1638 /** @name VMM device heap
1639 * @{ */
1640 /** The heap size. */
1641 uint32_t cbVMMDevHeap;
1642 /** Free space. */
1643 uint32_t cbVMMDevHeapLeft;
1644 /** Pointer to the heap base (MMIO2 ring-3 mapping). NULL if not registered. */
1645 RTR3PTR pvVMMDevHeap;
1646 /** Ring-3 mapping/unmapping notification callback for the user. */
1647 PFNPDMVMMDEVHEAPNOTIFY pfnVMMDevHeapNotify;
1648 /** The current mapping. NIL_RTGCPHYS if not mapped or registered. */
1649 RTGCPHYS GCPhysVMMDevHeap;
1650 /** @} */
1651
1652 /** @name Network Shaper
1653 * @{ */
1654 /** Thread that processes choked filter drivers after
1655 * the a PDM_NETSHAPER_MAX_LATENCY period has elapsed. */
1656 PPDMTHREAD pNsUnchokeThread;
1657 /** Semaphore that the TX thread waits on. */
1658 RTSEMEVENT hNsUnchokeEvt;
1659 /** Timer handle for waking up pNsUnchokeThread. */
1660 TMTIMERHANDLE hNsUnchokeTimer;
1661 /** Indicates whether the unchoke timer has been armed already or not. */
1662 bool volatile fNsUnchokeTimerArmed;
1663 /** Align aNsGroups on a cacheline. */
1664 bool afPadding2[19+16+17];
1665 /** Number of network shaper groups.
1666 * @note Marked volatile to prevent re-reading after validation. */
1667 uint32_t volatile cNsGroups;
1668 /** The network shaper groups. */
1669 PDMNSBWGROUP aNsGroups[PDM_NET_SHAPER_MAX_GROUPS];
1670 /** Critical section protecting attaching, detaching and unchoking.
1671 * This helps making sure pNsTxThread can do unchoking w/o needing to lock the
1672 * individual groups and cause unnecessary contention. */
1673 RTCRITSECT NsLock;
1674 /** @} */
1675
1676 /** Number of times a critical section leave request needed to be queued for ring-3 execution. */
1677 STAMCOUNTER StatQueuedCritSectLeaves;
1678 /** Number of times we've successfully aborted a wait in ring-0. */
1679 STAMCOUNTER StatAbortedCritSectEnters;
1680 /** Number of times we've got the critical section ownership while trying to
1681 * abort a wait due to VERR_INTERRUPTED. */
1682 STAMCOUNTER StatCritSectEntersWhileAborting;
1683 STAMCOUNTER StatCritSectVerrTimeout;
1684 STAMCOUNTER StatCritSectVerrInterrupted;
1685 STAMCOUNTER StatCritSectNonInterruptibleWaits;
1686
1687 STAMCOUNTER StatCritSectRwExclVerrTimeout;
1688 STAMCOUNTER StatCritSectRwExclVerrInterrupted;
1689 STAMCOUNTER StatCritSectRwExclNonInterruptibleWaits;
1690
1691 STAMCOUNTER StatCritSectRwEnterSharedWhileAborting;
1692 STAMCOUNTER StatCritSectRwSharedVerrTimeout;
1693 STAMCOUNTER StatCritSectRwSharedVerrInterrupted;
1694 STAMCOUNTER StatCritSectRwSharedNonInterruptibleWaits;
1695} PDM;
1696AssertCompileMemberAlignment(PDM, CritSect, 8);
1697AssertCompileMemberAlignment(PDM, aTaskSets, 64);
1698AssertCompileMemberAlignment(PDM, aNsGroups, 8);
1699AssertCompileMemberAlignment(PDM, aNsGroups, 16);
1700AssertCompileMemberAlignment(PDM, aNsGroups, 32);
1701AssertCompileMemberAlignment(PDM, aNsGroups, 64);
1702AssertCompileMemberAlignment(PDM, StatQueuedCritSectLeaves, 8);
1703AssertCompileMemberAlignment(PDM, GCPhysVMMDevHeap, sizeof(RTGCPHYS));
1704/** Pointer to PDM VM instance data. */
1705typedef PDM *PPDM;
1706
1707
1708/**
1709 * PDM data kept in the ring-0 GVM.
1710 */
1711typedef struct PDMR0PERVM
1712{
1713 /** PCI Buses, ring-0 data. */
1714 PDMPCIBUSR0 aPciBuses[PDM_PCI_BUSSES_MAX];
1715 /** IOMMUs, ring-0 data. */
1716 PDMIOMMUR0 aIommus[PDM_IOMMUS_MAX];
1717 /** Number of valid ring-0 device instances (apDevInstances). */
1718 uint32_t cDevInstances;
1719 uint32_t u32Padding1;
1720 /** Pointer to ring-0 device instances. */
1721 R0PTRTYPE(struct PDMDEVINSR0 *) apDevInstances[PDM_MAX_RING0_DEVICE_INSTANCES];
1722 /** Number of valid ring-0 queue instances (aQueues). */
1723 uint32_t cQueues;
1724 uint32_t u32Padding2;
1725 /** Array of ring-0 queues. */
1726 PDMQUEUER0 aQueues[16];
1727 /** The interrupt-controller, ring-0 data. */
1728 PDMICR0 Ic;
1729} PDMR0PERVM;
1730
1731
1732/**
1733 * PDM data kept in the UVM.
1734 */
1735typedef struct PDMUSERPERVM
1736{
1737 /** @todo move more stuff over here. */
1738
1739 /** Lock protecting the lists below it and the queue list (in PDM). */
1740 RTCRITSECT ListCritSect;
1741 /** Pointer to list of loaded modules. */
1742 PPDMMOD pModules;
1743 /** List of initialized critical sections. (LIFO) */
1744 R3PTRTYPE(PPDMCRITSECTINT) pCritSects;
1745 /** List of initialized read/write critical sections. (LIFO) */
1746 R3PTRTYPE(PPDMCRITSECTRWINT) pRwCritSects;
1747 /** Head of the PDM Thread list. (singly linked) */
1748 R3PTRTYPE(PPDMTHREAD) pThreads;
1749 /** Tail of the PDM Thread list. (singly linked) */
1750 R3PTRTYPE(PPDMTHREAD) pThreadsTail;
1751
1752 /** @name PDM Async Completion
1753 * @{ */
1754 /** Pointer to the array of supported endpoint classes. */
1755 PPDMASYNCCOMPLETIONEPCLASS apAsyncCompletionEndpointClass[PDMASYNCCOMPLETIONEPCLASSTYPE_MAX];
1756 /** Head of the templates. Singly linked, protected by ListCritSect. */
1757 R3PTRTYPE(PPDMASYNCCOMPLETIONTEMPLATE) pAsyncCompletionTemplates;
1758 /** @} */
1759
1760 /** Global block cache data. */
1761 R3PTRTYPE(PPDMBLKCACHEGLOBAL) pBlkCacheGlobal;
1762} PDMUSERPERVM;
1763/** Pointer to the PDM data kept in the UVM. */
1764typedef PDMUSERPERVM *PPDMUSERPERVM;
1765
1766
1767
1768/*******************************************************************************
1769* Global Variables *
1770*******************************************************************************/
1771#ifdef IN_RING3
1772extern const PDMDRVHLPR3 g_pdmR3DrvHlp;
1773extern const PDMDEVHLPR3 g_pdmR3DevHlpTrusted;
1774# ifdef VBOX_WITH_DBGF_TRACING
1775extern const PDMDEVHLPR3 g_pdmR3DevHlpTracing;
1776# endif
1777extern const PDMDEVHLPR3 g_pdmR3DevHlpUnTrusted;
1778extern const PDMPICHLP g_pdmR3DevPicHlp;
1779extern const PDMIOAPICHLP g_pdmR3DevIoApicHlp;
1780extern const PDMFWHLPR3 g_pdmR3DevFirmwareHlp;
1781extern const PDMPCIHLPR3 g_pdmR3DevPciHlp;
1782extern const PDMIOMMUHLPR3 g_pdmR3DevIommuHlp;
1783extern const PDMDMACHLP g_pdmR3DevDmacHlp;
1784extern const PDMRTCHLP g_pdmR3DevRtcHlp;
1785extern const PDMHPETHLPR3 g_pdmR3DevHpetHlp;
1786extern const PDMPCIRAWHLPR3 g_pdmR3DevPciRawHlp;
1787#endif
1788
1789
1790/*******************************************************************************
1791* Defined Constants And Macros *
1792*******************************************************************************/
1793/** @def PDMDEV_ASSERT_DEVINS
1794 * Asserts the validity of the device instance.
1795 */
1796#ifdef VBOX_STRICT
1797# define PDMDEV_ASSERT_DEVINS(pDevIns) \
1798 do { \
1799 AssertPtr(pDevIns); \
1800 Assert(pDevIns->u32Version == PDM_DEVINS_VERSION); \
1801 Assert(pDevIns->CTX_SUFF(pvInstanceDataFor) == (void *)&pDevIns->achInstanceData[0]); \
1802 } while (0)
1803#else
1804# define PDMDEV_ASSERT_DEVINS(pDevIns) do { } while (0)
1805#endif
1806
1807/** @def PDMDRV_ASSERT_DRVINS
1808 * Asserts the validity of the driver instance.
1809 */
1810#ifdef VBOX_STRICT
1811# define PDMDRV_ASSERT_DRVINS(pDrvIns) \
1812 do { \
1813 AssertPtr(pDrvIns); \
1814 Assert(pDrvIns->u32Version == PDM_DRVINS_VERSION); \
1815 Assert(pDrvIns->CTX_SUFF(pvInstanceData) == (void *)&pDrvIns->achInstanceData[0]); \
1816 } while (0)
1817#else
1818# define PDMDRV_ASSERT_DRVINS(pDrvIns) do { } while (0)
1819#endif
1820
1821#ifndef VBOX_VMM_TARGET_ARMV8
1822/** @def PDM_TO_APICBACKEND
1823 * Gets the APIC backend given the VM cross-context structure.
1824 */
1825/** @def PDMCPU_TO_APICBACKEND
1826 * Gets the APIC backend given VMCPU cross-context structure.
1827 */
1828# ifdef IN_RING3
1829# define PDM_TO_APICBACKEND(a_pVM) (&((a_pVM)->pdm.s.Ic.u.x86.ApicBackend))
1830# define PDMCPU_TO_APICBACKEND(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->pdm.s.Ic.u.x86.ApicBackend))
1831# else
1832# define PDM_TO_APICBACKEND(a_pVM) (&((a_pVM)->pdmr0.s.Ic.u.x86.ApicBackend))
1833# define PDMCPU_TO_APICBACKEND(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->pdmr0.s.Ic.u.x86.ApicBackend))
1834# endif
1835#else
1836# ifdef IN_RING3
1837# define PDM_TO_GICBACKEND(a_pVM) (&((a_pVM)->pdm.s.Ic.u.armv8.GicBackend))
1838# define PDMCPU_TO_GICBACKEND(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->pdm.s.Ic.u.armv8.GicBackend))
1839# else
1840# ifndef VBOX_WITH_MINIMAL_R0 /* hack for AllPdbTypeHack.cpp */
1841# error "Implement me"
1842# endif
1843# endif
1844#endif
1845
1846/*******************************************************************************
1847* Internal Functions *
1848*******************************************************************************/
1849#ifdef IN_RING3
1850bool pdmR3IsValidName(const char *pszName);
1851
1852int pdmR3CritSectBothInitStatsAndInfo(PVM pVM);
1853int pdmR3CritSectBothDeleteDevice(PVM pVM, PPDMDEVINS pDevIns);
1854int pdmR3CritSectBothDeleteDriver(PVM pVM, PPDMDRVINS pDrvIns);
1855int pdmR3CritSectInitDevice( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1856 const char *pszNameFmt, va_list va);
1857int pdmR3CritSectInitDeviceAuto( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1858 const char *pszNameFmt, ...);
1859int pdmR3CritSectInitDriver( PVM pVM, PPDMDRVINS pDrvIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1860 const char *pszNameFmt, ...);
1861int pdmR3CritSectRwInitDevice( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1862 const char *pszNameFmt, va_list va);
1863int pdmR3CritSectRwInitDeviceAuto( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1864 const char *pszNameFmt, ...);
1865int pdmR3CritSectRwInitDriver( PVM pVM, PPDMDRVINS pDrvIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1866 const char *pszNameFmt, ...);
1867
1868int pdmR3DevInit(PVM pVM);
1869int pdmR3DevInitComplete(PVM pVM);
1870PPDMDEV pdmR3DevLookup(PVM pVM, const char *pszName);
1871int pdmR3DevFindLun(PVM pVM, const char *pszDevice, unsigned iInstance, unsigned iLun, PPDMLUN *ppLun);
1872DECLCALLBACK(bool) pdmR3DevHlpQueueConsumer(PVM pVM, PPDMQUEUEITEMCORE pItem);
1873
1874int pdmR3UsbLoadModules(PVM pVM);
1875int pdmR3UsbInstantiateDevices(PVM pVM);
1876PPDMUSB pdmR3UsbLookup(PVM pVM, const char *pszName);
1877int pdmR3UsbRegisterHub(PVM pVM, PPDMDRVINS pDrvIns, uint32_t fVersions, uint32_t cPorts, PCPDMUSBHUBREG pUsbHubReg, PPCPDMUSBHUBHLP ppUsbHubHlp);
1878int pdmR3UsbVMInitComplete(PVM pVM);
1879
1880int pdmR3DrvInit(PVM pVM);
1881int pdmR3DrvInstantiate(PVM pVM, PCFGMNODE pNode, PPDMIBASE pBaseInterface, PPDMDRVINS pDrvAbove,
1882 PPDMLUN pLun, PPDMIBASE *ppBaseInterface);
1883int pdmR3DrvDetach(PVM pVM, PPDMDRVINS pDrvIns, uint32_t fFlags);
1884void pdmR3DrvDestroyChain(PVM pVM, PPDMDRVINS pDrvIns, uint32_t fFlags);
1885PPDMDRV pdmR3DrvLookup(PVM pVM, const char *pszName);
1886
1887int pdmR3LdrInitU(PUVM pUVM);
1888void pdmR3LdrTermU(PUVM pUVM, bool fFinal);
1889char *pdmR3FileR3(const char *pszFile, bool fShared);
1890int pdmR3LoadR3U(PUVM pUVM, const char *pszFilename, const char *pszName);
1891#endif /* IN_RING3 */
1892
1893void pdmQueueInit(PPDMQUEUE pQueue, uint32_t cbBitmap, uint32_t cbItem, uint32_t cItems,
1894 const char *pszName, PDMQUEUETYPE enmType, RTR3PTR pfnCallback, RTR3PTR pvOwner);
1895
1896#ifdef IN_RING3
1897int pdmR3TaskInit(PVM pVM);
1898void pdmR3TaskTerm(PVM pVM);
1899
1900int pdmR3ThreadCreateDevice(PVM pVM, PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
1901 PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1902int pdmR3ThreadCreateUsb(PVM pVM, PPDMUSBINS pUsbIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADUSB pfnThread,
1903 PFNPDMTHREADWAKEUPUSB pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1904int pdmR3ThreadCreateDriver(PVM pVM, PPDMDRVINS pDrvIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDRV pfnThread,
1905 PFNPDMTHREADWAKEUPDRV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1906int pdmR3ThreadDestroyDevice(PVM pVM, PPDMDEVINS pDevIns);
1907int pdmR3ThreadDestroyUsb(PVM pVM, PPDMUSBINS pUsbIns);
1908int pdmR3ThreadDestroyDriver(PVM pVM, PPDMDRVINS pDrvIns);
1909void pdmR3ThreadDestroyAll(PVM pVM);
1910int pdmR3ThreadResumeAll(PVM pVM);
1911int pdmR3ThreadSuspendAll(PVM pVM);
1912
1913# ifdef VBOX_WITH_PDM_ASYNC_COMPLETION
1914int pdmR3AsyncCompletionInit(PVM pVM);
1915int pdmR3AsyncCompletionTerm(PVM pVM);
1916void pdmR3AsyncCompletionResume(PVM pVM);
1917int pdmR3AsyncCompletionTemplateCreateDevice(PVM pVM, PPDMDEVINS pDevIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate, PFNPDMASYNCCOMPLETEDEV pfnCompleted, const char *pszDesc);
1918int pdmR3AsyncCompletionTemplateCreateDriver(PVM pVM, PPDMDRVINS pDrvIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate,
1919 PFNPDMASYNCCOMPLETEDRV pfnCompleted, void *pvTemplateUser, const char *pszDesc);
1920int pdmR3AsyncCompletionTemplateCreateUsb(PVM pVM, PPDMUSBINS pUsbIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate, PFNPDMASYNCCOMPLETEUSB pfnCompleted, const char *pszDesc);
1921int pdmR3AsyncCompletionTemplateDestroyDevice(PVM pVM, PPDMDEVINS pDevIns);
1922int pdmR3AsyncCompletionTemplateDestroyDriver(PVM pVM, PPDMDRVINS pDrvIns);
1923int pdmR3AsyncCompletionTemplateDestroyUsb(PVM pVM, PPDMUSBINS pUsbIns);
1924# endif
1925
1926# ifdef VBOX_WITH_NETSHAPER
1927int pdmR3NetShaperInit(PVM pVM);
1928void pdmR3NetShaperTerm(PVM pVM);
1929# endif
1930
1931int pdmR3BlkCacheInit(PVM pVM);
1932void pdmR3BlkCacheTerm(PVM pVM);
1933int pdmR3BlkCacheResume(PVM pVM);
1934
1935DECLHIDDEN(void) pdmR3QueueTerm(PVM pVM);
1936#endif /* IN_RING3 */
1937
1938void pdmLock(PVMCC pVM);
1939int pdmLockEx(PVMCC pVM, int rcBusy);
1940void pdmUnlock(PVMCC pVM);
1941bool pdmLockIsOwner(PVMCC pVM);
1942
1943#if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
1944bool pdmIommuIsPresent(PPDMDEVINS pDevIns);
1945int pdmIommuMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut);
1946int pdmIommuMemAccessRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1947int pdmIommuMemAccessWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1948# ifdef IN_RING3
1949int pdmR3IommuMemAccessReadCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags, void const **ppv, PPGMPAGEMAPLOCK pLock);
1950int pdmR3IommuMemAccessWriteCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv, PPGMPAGEMAPLOCK pLock);
1951int pdmR3IommuMemAccessBulkReadCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages, PCRTGCPHYS paGCPhysPages, uint32_t fFlags, const void **papvPages, PPGMPAGEMAPLOCK paLocks);
1952int pdmR3IommuMemAccessBulkWriteCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages, PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks);
1953# endif
1954#endif
1955
1956#if defined(IN_RING3) || defined(IN_RING0)
1957void pdmCritSectRwLeaveSharedQueued(PVMCC pVM, PPDMCRITSECTRW pThis);
1958void pdmCritSectRwLeaveExclQueued(PVMCC pVM, PPDMCRITSECTRW pThis);
1959#endif
1960
1961#ifdef IN_RING0
1962DECLHIDDEN(bool) pdmR0IsaSetIrq(PGVM pGVM, int iIrq, int iLevel, uint32_t uTagSrc);
1963DECLHIDDEN(void) pdmR0QueueDestroy(PGVM pGVM, uint32_t iQueue);
1964
1965#endif
1966
1967#ifdef VBOX_WITH_DBGF_TRACING
1968# ifdef IN_RING3
1969DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_IoPortCreateEx(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
1970 uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
1971 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
1972 const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts);
1973DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_IoPortMap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port);
1974DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_IoPortUnmap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts);
1975DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_MmioCreateEx(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
1976 uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
1977 PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
1978 void *pvUser, const char *pszDesc, PIOMMMIOHANDLE phRegion);
1979DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_MmioMap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys);
1980DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_MmioUnmap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion);
1981DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1982DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1983DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PCIPhysRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1984DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PCIPhysWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1985DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_PCISetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1986DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_PCISetIrqNoWait(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1987DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1988DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_ISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1989# elif defined(IN_RING0)
1990DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_IoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
1991 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
1992 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
1993 void *pvUser);
1994DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_MmioSetUpContextEx(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
1995 PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser);
1996DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1997DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1998DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PCIPhysRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1999DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PCIPhysWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
2000DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_PCISetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
2001DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_PCISetIrqNoWait(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
2002DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
2003DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_ISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel);
2004# else
2005# error "Invalid environment selected"
2006# endif
2007#endif
2008
2009
2010/** @} */
2011
2012RT_C_DECLS_END
2013
2014#endif /* !VMM_INCLUDED_SRC_include_PDMInternal_h */
2015
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