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source: vbox/trunk/src/VBox/VMM/include/IEMN8veRecompiler.h@ 103720

最後變更 在這個檔案從103720是 103671,由 vboxsync 提交於 13 月 前

VMM/IEM: Native translation of IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() body, bugref:10371
  • 屬性 svn:eol-style 設為 native
  • 屬性 svn:keywords 設為 Author Date Id Revision
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1/* $Id: IEMN8veRecompiler.h 103671 2024-03-04 15:48:34Z vboxsync $ */
2/** @file
3 * IEM - Interpreted Execution Manager - Native Recompiler Internals.
4 */
5
6/*
7 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.alldomusa.eu.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_IEMN8veRecompiler_h
29#define VMM_INCLUDED_SRC_include_IEMN8veRecompiler_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34
35/** @defgroup grp_iem_n8ve_re Native Recompiler Internals.
36 * @ingroup grp_iem_int
37 * @{
38 */
39
40/** @def IEMNATIVE_WITH_TB_DEBUG_INFO
41 * Enables generating internal debug info for better TB disassembly dumping. */
42#if defined(DEBUG) || defined(DOXYGEN_RUNNING)
43# define IEMNATIVE_WITH_TB_DEBUG_INFO
44#endif
45
46/** @def IEMNATIVE_WITH_LIVENESS_ANALYSIS
47 * Enables liveness analysis. */
48#if 1 || defined(DOXYGEN_RUNNING)
49# define IEMNATIVE_WITH_LIVENESS_ANALYSIS
50/*# define IEMLIVENESS_EXTENDED_LAYOUT*/
51#endif
52
53#ifdef VBOX_WITH_STATISTICS
54/** Always count instructions for now. */
55# define IEMNATIVE_WITH_INSTRUCTION_COUNTING
56#endif
57
58
59/** @name Stack Frame Layout
60 *
61 * @{ */
62/** The size of the area for stack variables and spills and stuff.
63 * @note This limit is duplicated in the python script(s). We add 0x40 for
64 * alignment padding. */
65#define IEMNATIVE_FRAME_VAR_SIZE (0xc0 + 0x40)
66/** Number of 64-bit variable slots (0x100 / 8 = 32. */
67#define IEMNATIVE_FRAME_VAR_SLOTS (IEMNATIVE_FRAME_VAR_SIZE / 8)
68AssertCompile(IEMNATIVE_FRAME_VAR_SLOTS == 32);
69
70#ifdef RT_ARCH_AMD64
71/** An stack alignment adjustment (between non-volatile register pushes and
72 * the stack variable area, so the latter better aligned). */
73# define IEMNATIVE_FRAME_ALIGN_SIZE 8
74
75/** Number of stack arguments slots for calls made from the frame. */
76# ifdef RT_OS_WINDOWS
77# define IEMNATIVE_FRAME_STACK_ARG_COUNT 4
78# else
79# define IEMNATIVE_FRAME_STACK_ARG_COUNT 2
80# endif
81/** Number of any shadow arguments (spill area) for calls we make. */
82# ifdef RT_OS_WINDOWS
83# define IEMNATIVE_FRAME_SHADOW_ARG_COUNT 4
84# else
85# define IEMNATIVE_FRAME_SHADOW_ARG_COUNT 0
86# endif
87
88/** Frame pointer (RBP) relative offset of the last push. */
89# ifdef RT_OS_WINDOWS
90# define IEMNATIVE_FP_OFF_LAST_PUSH (7 * -8)
91# else
92# define IEMNATIVE_FP_OFF_LAST_PUSH (5 * -8)
93# endif
94/** Frame pointer (RBP) relative offset of the stack variable area (the lowest
95 * address for it). */
96# define IEMNATIVE_FP_OFF_STACK_VARS (IEMNATIVE_FP_OFF_LAST_PUSH - IEMNATIVE_FRAME_ALIGN_SIZE - IEMNATIVE_FRAME_VAR_SIZE)
97/** Frame pointer (RBP) relative offset of the first stack argument for calls. */
98# define IEMNATIVE_FP_OFF_STACK_ARG0 (IEMNATIVE_FP_OFF_STACK_VARS - IEMNATIVE_FRAME_STACK_ARG_COUNT * 8)
99/** Frame pointer (RBP) relative offset of the second stack argument for calls. */
100# define IEMNATIVE_FP_OFF_STACK_ARG1 (IEMNATIVE_FP_OFF_STACK_ARG0 + 8)
101# ifdef RT_OS_WINDOWS
102/** Frame pointer (RBP) relative offset of the third stack argument for calls. */
103# define IEMNATIVE_FP_OFF_STACK_ARG2 (IEMNATIVE_FP_OFF_STACK_ARG0 + 16)
104/** Frame pointer (RBP) relative offset of the fourth stack argument for calls. */
105# define IEMNATIVE_FP_OFF_STACK_ARG3 (IEMNATIVE_FP_OFF_STACK_ARG0 + 24)
106# endif
107
108# ifdef RT_OS_WINDOWS
109/** Frame pointer (RBP) relative offset of the first incoming shadow argument. */
110# define IEMNATIVE_FP_OFF_IN_SHADOW_ARG0 (16)
111/** Frame pointer (RBP) relative offset of the second incoming shadow argument. */
112# define IEMNATIVE_FP_OFF_IN_SHADOW_ARG1 (24)
113/** Frame pointer (RBP) relative offset of the third incoming shadow argument. */
114# define IEMNATIVE_FP_OFF_IN_SHADOW_ARG2 (32)
115/** Frame pointer (RBP) relative offset of the fourth incoming shadow argument. */
116# define IEMNATIVE_FP_OFF_IN_SHADOW_ARG3 (40)
117# endif
118
119#elif RT_ARCH_ARM64
120/** No alignment padding needed for arm64. */
121# define IEMNATIVE_FRAME_ALIGN_SIZE 0
122/** No stack argument slots, got 8 registers for arguments will suffice. */
123# define IEMNATIVE_FRAME_STACK_ARG_COUNT 0
124/** There are no argument spill area. */
125# define IEMNATIVE_FRAME_SHADOW_ARG_COUNT 0
126
127/** Number of saved registers at the top of our stack frame.
128 * This includes the return address and old frame pointer, so x19 thru x30. */
129# define IEMNATIVE_FRAME_SAVE_REG_COUNT (12)
130/** The size of the save registered (IEMNATIVE_FRAME_SAVE_REG_COUNT). */
131# define IEMNATIVE_FRAME_SAVE_REG_SIZE (IEMNATIVE_FRAME_SAVE_REG_COUNT * 8)
132
133/** Frame pointer (BP) relative offset of the last push. */
134# define IEMNATIVE_FP_OFF_LAST_PUSH (10 * -8)
135
136/** Frame pointer (BP) relative offset of the stack variable area (the lowest
137 * address for it). */
138# define IEMNATIVE_FP_OFF_STACK_VARS (IEMNATIVE_FP_OFF_LAST_PUSH - IEMNATIVE_FRAME_ALIGN_SIZE - IEMNATIVE_FRAME_VAR_SIZE)
139
140#else
141# error "port me"
142#endif
143/** @} */
144
145
146/** @name Fixed Register Allocation(s)
147 * @{ */
148/** @def IEMNATIVE_REG_FIXED_PVMCPU
149 * The number of the register holding the pVCpu pointer. */
150/** @def IEMNATIVE_REG_FIXED_PCPUMCTX
151 * The number of the register holding the &pVCpu->cpum.GstCtx pointer.
152 * @note This not available on AMD64, only ARM64. */
153/** @def IEMNATIVE_REG_FIXED_TMP0
154 * Dedicated temporary register.
155 * @todo replace this by a register allocator and content tracker. */
156/** @def IEMNATIVE_REG_FIXED_MASK
157 * Mask GPRs with fixes assignments, either by us or dictated by the CPU/OS
158 * architecture. */
159#if defined(RT_ARCH_AMD64) && !defined(DOXYGEN_RUNNING)
160# define IEMNATIVE_REG_FIXED_PVMCPU X86_GREG_xBX
161# define IEMNATIVE_REG_FIXED_TMP0 X86_GREG_x11
162# define IEMNATIVE_REG_FIXED_MASK ( RT_BIT_32(IEMNATIVE_REG_FIXED_PVMCPU) \
163 | RT_BIT_32(IEMNATIVE_REG_FIXED_TMP0) \
164 | RT_BIT_32(X86_GREG_xSP) \
165 | RT_BIT_32(X86_GREG_xBP) )
166
167#elif defined(RT_ARCH_ARM64) || defined(DOXYGEN_RUNNING)
168# define IEMNATIVE_REG_FIXED_PVMCPU ARMV8_A64_REG_X28
169# define IEMNATIVE_REG_FIXED_PCPUMCTX ARMV8_A64_REG_X27
170# define IEMNATIVE_REG_FIXED_TMP0 ARMV8_A64_REG_X15
171# if defined(IEMNATIVE_WITH_DELAYED_PC_UPDATING) && 0 /* debug the updating with a shadow RIP. */
172# define IEMNATIVE_REG_FIXED_TMP1 ARMV8_A64_REG_X16
173# define IEMNATIVE_REG_FIXED_PC_DBG ARMV8_A64_REG_X26
174# define IEMNATIVE_REG_FIXED_MASK_ADD ( RT_BIT_32(IEMNATIVE_REG_FIXED_TMP1) \
175 | RT_BIT_32(IEMNATIVE_REG_FIXED_PC_DBG))
176# else
177# define IEMNATIVE_REG_FIXED_MASK_ADD 0
178# endif
179# define IEMNATIVE_REG_FIXED_MASK ( RT_BIT_32(ARMV8_A64_REG_SP) \
180 | RT_BIT_32(ARMV8_A64_REG_LR) \
181 | RT_BIT_32(ARMV8_A64_REG_BP) \
182 | RT_BIT_32(IEMNATIVE_REG_FIXED_PVMCPU) \
183 | RT_BIT_32(IEMNATIVE_REG_FIXED_PCPUMCTX) \
184 | RT_BIT_32(ARMV8_A64_REG_X18) \
185 | RT_BIT_32(IEMNATIVE_REG_FIXED_TMP0) \
186 | IEMNATIVE_REG_FIXED_MASK_ADD)
187
188#else
189# error "port me"
190#endif
191/** @} */
192
193/** @name Call related registers.
194 * @{ */
195/** @def IEMNATIVE_CALL_RET_GREG
196 * The return value register. */
197/** @def IEMNATIVE_CALL_ARG_GREG_COUNT
198 * Number of arguments in registers. */
199/** @def IEMNATIVE_CALL_ARG0_GREG
200 * The general purpose register carrying argument \#0. */
201/** @def IEMNATIVE_CALL_ARG1_GREG
202 * The general purpose register carrying argument \#1. */
203/** @def IEMNATIVE_CALL_ARG2_GREG
204 * The general purpose register carrying argument \#2. */
205/** @def IEMNATIVE_CALL_ARG3_GREG
206 * The general purpose register carrying argument \#3. */
207/** @def IEMNATIVE_CALL_VOLATILE_GREG_MASK
208 * Mask of registers the callee will not save and may trash. */
209#ifdef RT_ARCH_AMD64
210# define IEMNATIVE_CALL_RET_GREG X86_GREG_xAX
211
212# ifdef RT_OS_WINDOWS
213# define IEMNATIVE_CALL_ARG_GREG_COUNT 4
214# define IEMNATIVE_CALL_ARG0_GREG X86_GREG_xCX
215# define IEMNATIVE_CALL_ARG1_GREG X86_GREG_xDX
216# define IEMNATIVE_CALL_ARG2_GREG X86_GREG_x8
217# define IEMNATIVE_CALL_ARG3_GREG X86_GREG_x9
218# define IEMNATIVE_CALL_ARGS_GREG_MASK ( RT_BIT_32(IEMNATIVE_CALL_ARG0_GREG) \
219 | RT_BIT_32(IEMNATIVE_CALL_ARG1_GREG) \
220 | RT_BIT_32(IEMNATIVE_CALL_ARG2_GREG) \
221 | RT_BIT_32(IEMNATIVE_CALL_ARG3_GREG) )
222# define IEMNATIVE_CALL_VOLATILE_GREG_MASK ( RT_BIT_32(X86_GREG_xAX) \
223 | RT_BIT_32(X86_GREG_xCX) \
224 | RT_BIT_32(X86_GREG_xDX) \
225 | RT_BIT_32(X86_GREG_x8) \
226 | RT_BIT_32(X86_GREG_x9) \
227 | RT_BIT_32(X86_GREG_x10) \
228 | RT_BIT_32(X86_GREG_x11) )
229# else
230# define IEMNATIVE_CALL_ARG_GREG_COUNT 6
231# define IEMNATIVE_CALL_ARG0_GREG X86_GREG_xDI
232# define IEMNATIVE_CALL_ARG1_GREG X86_GREG_xSI
233# define IEMNATIVE_CALL_ARG2_GREG X86_GREG_xDX
234# define IEMNATIVE_CALL_ARG3_GREG X86_GREG_xCX
235# define IEMNATIVE_CALL_ARG4_GREG X86_GREG_x8
236# define IEMNATIVE_CALL_ARG5_GREG X86_GREG_x9
237# define IEMNATIVE_CALL_ARGS_GREG_MASK ( RT_BIT_32(IEMNATIVE_CALL_ARG0_GREG) \
238 | RT_BIT_32(IEMNATIVE_CALL_ARG1_GREG) \
239 | RT_BIT_32(IEMNATIVE_CALL_ARG2_GREG) \
240 | RT_BIT_32(IEMNATIVE_CALL_ARG3_GREG) \
241 | RT_BIT_32(IEMNATIVE_CALL_ARG4_GREG) \
242 | RT_BIT_32(IEMNATIVE_CALL_ARG5_GREG) )
243# define IEMNATIVE_CALL_VOLATILE_GREG_MASK ( RT_BIT_32(X86_GREG_xAX) \
244 | RT_BIT_32(X86_GREG_xCX) \
245 | RT_BIT_32(X86_GREG_xDX) \
246 | RT_BIT_32(X86_GREG_xDI) \
247 | RT_BIT_32(X86_GREG_xSI) \
248 | RT_BIT_32(X86_GREG_x8) \
249 | RT_BIT_32(X86_GREG_x9) \
250 | RT_BIT_32(X86_GREG_x10) \
251 | RT_BIT_32(X86_GREG_x11) )
252# endif
253
254#elif defined(RT_ARCH_ARM64)
255# define IEMNATIVE_CALL_RET_GREG ARMV8_A64_REG_X0
256# define IEMNATIVE_CALL_ARG_GREG_COUNT 8
257# define IEMNATIVE_CALL_ARG0_GREG ARMV8_A64_REG_X0
258# define IEMNATIVE_CALL_ARG1_GREG ARMV8_A64_REG_X1
259# define IEMNATIVE_CALL_ARG2_GREG ARMV8_A64_REG_X2
260# define IEMNATIVE_CALL_ARG3_GREG ARMV8_A64_REG_X3
261# define IEMNATIVE_CALL_ARG4_GREG ARMV8_A64_REG_X4
262# define IEMNATIVE_CALL_ARG5_GREG ARMV8_A64_REG_X5
263# define IEMNATIVE_CALL_ARG6_GREG ARMV8_A64_REG_X6
264# define IEMNATIVE_CALL_ARG7_GREG ARMV8_A64_REG_X7
265# define IEMNATIVE_CALL_ARGS_GREG_MASK ( RT_BIT_32(ARMV8_A64_REG_X0) \
266 | RT_BIT_32(ARMV8_A64_REG_X1) \
267 | RT_BIT_32(ARMV8_A64_REG_X2) \
268 | RT_BIT_32(ARMV8_A64_REG_X3) \
269 | RT_BIT_32(ARMV8_A64_REG_X4) \
270 | RT_BIT_32(ARMV8_A64_REG_X5) \
271 | RT_BIT_32(ARMV8_A64_REG_X6) \
272 | RT_BIT_32(ARMV8_A64_REG_X7) )
273# define IEMNATIVE_CALL_VOLATILE_GREG_MASK ( RT_BIT_32(ARMV8_A64_REG_X0) \
274 | RT_BIT_32(ARMV8_A64_REG_X1) \
275 | RT_BIT_32(ARMV8_A64_REG_X2) \
276 | RT_BIT_32(ARMV8_A64_REG_X3) \
277 | RT_BIT_32(ARMV8_A64_REG_X4) \
278 | RT_BIT_32(ARMV8_A64_REG_X5) \
279 | RT_BIT_32(ARMV8_A64_REG_X6) \
280 | RT_BIT_32(ARMV8_A64_REG_X7) \
281 | RT_BIT_32(ARMV8_A64_REG_X8) \
282 | RT_BIT_32(ARMV8_A64_REG_X9) \
283 | RT_BIT_32(ARMV8_A64_REG_X10) \
284 | RT_BIT_32(ARMV8_A64_REG_X11) \
285 | RT_BIT_32(ARMV8_A64_REG_X12) \
286 | RT_BIT_32(ARMV8_A64_REG_X13) \
287 | RT_BIT_32(ARMV8_A64_REG_X14) \
288 | RT_BIT_32(ARMV8_A64_REG_X15) \
289 | RT_BIT_32(ARMV8_A64_REG_X16) \
290 | RT_BIT_32(ARMV8_A64_REG_X17) )
291
292#endif
293
294/** This is the maximum argument count we'll ever be needing. */
295#if defined(RT_OS_WINDOWS) && defined(VBOXSTRICTRC_STRICT_ENABLED)
296# define IEMNATIVE_CALL_MAX_ARG_COUNT 8
297#else
298# define IEMNATIVE_CALL_MAX_ARG_COUNT 7
299#endif
300/** @} */
301
302
303/** @def IEMNATIVE_HST_GREG_COUNT
304 * Number of host general purpose registers we tracker. */
305/** @def IEMNATIVE_HST_GREG_MASK
306 * Mask corresponding to IEMNATIVE_HST_GREG_COUNT that can be applied to
307 * inverted register masks and such to get down to a correct set of regs. */
308#ifdef RT_ARCH_AMD64
309# define IEMNATIVE_HST_GREG_COUNT 16
310# define IEMNATIVE_HST_GREG_MASK UINT32_C(0xffff)
311
312#elif defined(RT_ARCH_ARM64)
313# define IEMNATIVE_HST_GREG_COUNT 32
314# define IEMNATIVE_HST_GREG_MASK UINT32_MAX
315#else
316# error "Port me!"
317#endif
318
319
320/** Native code generator label types. */
321typedef enum
322{
323 kIemNativeLabelType_Invalid = 0,
324 /* Labels w/o data, only once instance per TB: */
325 kIemNativeLabelType_Return,
326 kIemNativeLabelType_ReturnBreak,
327 kIemNativeLabelType_ReturnWithFlags,
328 kIemNativeLabelType_NonZeroRetOrPassUp,
329 kIemNativeLabelType_RaiseGp0,
330 kIemNativeLabelType_RaiseNm,
331 kIemNativeLabelType_RaiseUd,
332 kIemNativeLabelType_RaiseMf,
333 kIemNativeLabelType_RaiseXf,
334 kIemNativeLabelType_ObsoleteTb,
335 kIemNativeLabelType_NeedCsLimChecking,
336 kIemNativeLabelType_CheckBranchMiss,
337 /* Labels with data, potentially multiple instances per TB: */
338 kIemNativeLabelType_FirstWithMultipleInstances,
339 kIemNativeLabelType_If = kIemNativeLabelType_FirstWithMultipleInstances,
340 kIemNativeLabelType_Else,
341 kIemNativeLabelType_Endif,
342 kIemNativeLabelType_CheckIrq,
343 kIemNativeLabelType_TlbLookup,
344 kIemNativeLabelType_TlbMiss,
345 kIemNativeLabelType_TlbDone,
346 kIemNativeLabelType_End
347} IEMNATIVELABELTYPE;
348
349/** Native code generator label definition. */
350typedef struct IEMNATIVELABEL
351{
352 /** Code offset if defined, UINT32_MAX if it needs to be generated after/in
353 * the epilog. */
354 uint32_t off;
355 /** The type of label (IEMNATIVELABELTYPE). */
356 uint16_t enmType;
357 /** Additional label data, type specific. */
358 uint16_t uData;
359} IEMNATIVELABEL;
360/** Pointer to a label. */
361typedef IEMNATIVELABEL *PIEMNATIVELABEL;
362
363
364/** Native code generator fixup types. */
365typedef enum
366{
367 kIemNativeFixupType_Invalid = 0,
368#if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86)
369 /** AMD64 fixup: PC relative 32-bit with addend in bData. */
370 kIemNativeFixupType_Rel32,
371#elif defined(RT_ARCH_ARM64)
372 /** ARM64 fixup: PC relative offset at bits 25:0 (B, BL). */
373 kIemNativeFixupType_RelImm26At0,
374 /** ARM64 fixup: PC relative offset at bits 23:5 (CBZ, CBNZ, B.CC). */
375 kIemNativeFixupType_RelImm19At5,
376 /** ARM64 fixup: PC relative offset at bits 18:5 (TBZ, TBNZ). */
377 kIemNativeFixupType_RelImm14At5,
378#endif
379 kIemNativeFixupType_End
380} IEMNATIVEFIXUPTYPE;
381
382/** Native code generator fixup. */
383typedef struct IEMNATIVEFIXUP
384{
385 /** Code offset of the fixup location. */
386 uint32_t off;
387 /** The IEMNATIVELABEL this is a fixup for. */
388 uint16_t idxLabel;
389 /** The fixup type (IEMNATIVEFIXUPTYPE). */
390 uint8_t enmType;
391 /** Addend or other data. */
392 int8_t offAddend;
393} IEMNATIVEFIXUP;
394/** Pointer to a native code generator fixup. */
395typedef IEMNATIVEFIXUP *PIEMNATIVEFIXUP;
396
397
398/**
399 * One bit of the state.
400 *
401 * Each register state takes up two bits. We keep the two bits in two separate
402 * 64-bit words to simplify applying them to the guest shadow register mask in
403 * the register allocator.
404 */
405typedef union IEMLIVENESSBIT
406{
407 uint64_t bm64;
408 RT_GCC_EXTENSION struct
409 { /* bit no */
410 uint64_t bmGprs : 16; /**< 0x00 / 0: The 16 general purpose registers. */
411 uint64_t fUnusedPc : 1; /**< 0x10 / 16: (PC in ) */
412 uint64_t fCr0 : 1; /**< 0x11 / 17: */
413 uint64_t fFcw : 1; /**< 0x12 / 18: */
414 uint64_t fFsw : 1; /**< 0x13 / 19: */
415 uint64_t bmSegBase : 6; /**< 0x14 / 20: */
416 uint64_t bmSegAttrib : 6; /**< 0x1a / 26: */
417 uint64_t bmSegLimit : 6; /**< 0x20 / 32: */
418 uint64_t bmSegSel : 6; /**< 0x26 / 38: */
419 uint64_t fCr4 : 1; /**< 0x2c / 44: */
420 uint64_t fXcr0 : 1; /**< 0x2d / 45: */
421 uint64_t fMxCsr : 1; /**< 0x2e / 46: */
422 uint64_t fEflOther : 1; /**< 0x2f / 47: Other EFLAGS bits (~X86_EFL_STATUS_BITS & X86_EFL_LIVE_MASK). First! */
423 uint64_t fEflCf : 1; /**< 0x30 / 48: Carry flag (X86_EFL_CF / 0). */
424 uint64_t fEflPf : 1; /**< 0x31 / 49: Parity flag (X86_EFL_PF / 2). */
425 uint64_t fEflAf : 1; /**< 0x32 / 50: Auxilary carry flag (X86_EFL_AF / 4). */
426 uint64_t fEflZf : 1; /**< 0x33 / 51: Zero flag (X86_EFL_ZF / 6). */
427 uint64_t fEflSf : 1; /**< 0x34 / 52: Signed flag (X86_EFL_SF / 7). */
428 uint64_t fEflOf : 1; /**< 0x35 / 53: Overflow flag (X86_EFL_OF / 12). */
429 uint64_t uUnused : 10; /* 0x36 / 54 -> 0x40/64 */
430 };
431} IEMLIVENESSBIT;
432AssertCompileSize(IEMLIVENESSBIT, 8);
433
434#define IEMLIVENESSBIT_IDX_EFL_OTHER ((unsigned)kIemNativeGstReg_EFlags + 0)
435#define IEMLIVENESSBIT_IDX_EFL_CF ((unsigned)kIemNativeGstReg_EFlags + 1)
436#define IEMLIVENESSBIT_IDX_EFL_PF ((unsigned)kIemNativeGstReg_EFlags + 2)
437#define IEMLIVENESSBIT_IDX_EFL_AF ((unsigned)kIemNativeGstReg_EFlags + 3)
438#define IEMLIVENESSBIT_IDX_EFL_ZF ((unsigned)kIemNativeGstReg_EFlags + 4)
439#define IEMLIVENESSBIT_IDX_EFL_SF ((unsigned)kIemNativeGstReg_EFlags + 5)
440#define IEMLIVENESSBIT_IDX_EFL_OF ((unsigned)kIemNativeGstReg_EFlags + 6)
441
442
443/**
444 * A liveness state entry.
445 *
446 * The first 128 bits runs parallel to kIemNativeGstReg_xxx for the most part.
447 * Once we add a SSE register shadowing, we'll add another 64-bit element for
448 * that.
449 */
450typedef union IEMLIVENESSENTRY
451{
452#ifndef IEMLIVENESS_EXTENDED_LAYOUT
453 uint64_t bm64[16 / 8];
454 uint16_t bm32[16 / 4];
455 uint16_t bm16[16 / 2];
456 uint8_t bm8[ 16 / 1];
457 IEMLIVENESSBIT aBits[2];
458#else
459 uint64_t bm64[32 / 8];
460 uint16_t bm32[32 / 4];
461 uint16_t bm16[32 / 2];
462 uint8_t bm8[ 32 / 1];
463 IEMLIVENESSBIT aBits[4];
464#endif
465 RT_GCC_EXTENSION struct
466 {
467 /** Bit \#0 of the register states. */
468 IEMLIVENESSBIT Bit0;
469 /** Bit \#1 of the register states. */
470 IEMLIVENESSBIT Bit1;
471#ifdef IEMLIVENESS_EXTENDED_LAYOUT
472 /** Bit \#2 of the register states. */
473 IEMLIVENESSBIT Bit2;
474 /** Bit \#3 of the register states. */
475 IEMLIVENESSBIT Bit3;
476#endif
477 };
478} IEMLIVENESSENTRY;
479#ifndef IEMLIVENESS_EXTENDED_LAYOUT
480AssertCompileSize(IEMLIVENESSENTRY, 16);
481#else
482AssertCompileSize(IEMLIVENESSENTRY, 32);
483#endif
484/** Pointer to a liveness state entry. */
485typedef IEMLIVENESSENTRY *PIEMLIVENESSENTRY;
486/** Pointer to a const liveness state entry. */
487typedef IEMLIVENESSENTRY const *PCIEMLIVENESSENTRY;
488
489/** @name 64-bit value masks for IEMLIVENESSENTRY.
490 * @{ */ /* 0xzzzzyyyyxxxxwwww */
491#define IEMLIVENESSBIT_MASK UINT64_C(0x003ffffffffeffff)
492
493#ifndef IEMLIVENESS_EXTENDED_LAYOUT
494# define IEMLIVENESSBIT0_XCPT_OR_CALL UINT64_C(0x0000000000000000)
495# define IEMLIVENESSBIT1_XCPT_OR_CALL IEMLIVENESSBIT_MASK
496
497# define IEMLIVENESSBIT0_ALL_UNUSED IEMLIVENESSBIT_MASK
498# define IEMLIVENESSBIT1_ALL_UNUSED UINT64_C(0x0000000000000000)
499#endif
500
501#define IEMLIVENESSBIT_ALL_EFL_MASK UINT64_C(0x003f800000000000)
502
503#ifndef IEMLIVENESS_EXTENDED_LAYOUT
504# define IEMLIVENESSBIT0_ALL_EFL_INPUT IEMLIVENESSBIT_ALL_EFL_MASK
505# define IEMLIVENESSBIT1_ALL_EFL_INPUT IEMLIVENESSBIT_ALL_EFL_MASK
506#endif
507/** @} */
508
509
510/** @name The liveness state for a register.
511 *
512 * The state values have been picked to with state accumulation in mind (what
513 * the iemNativeLivenessFunc_xxxx functions does), as that is the most
514 * performance critical work done with the values.
515 *
516 * This is a compressed state that only requires 2 bits per register.
517 * When accumulating state, we'll be using three IEMLIVENESSENTRY copies:
518 * 1. the incoming state from the following call,
519 * 2. the outgoing state for this call,
520 * 3. mask of the entries set in the 2nd.
521 *
522 * The mask entry (3rd one above) will be used both when updating the outgoing
523 * state and when merging in incoming state for registers not touched by the
524 * current call.
525 *
526 * @{ */
527#ifndef IEMLIVENESS_EXTENDED_LAYOUT
528/** The register will be clobbered and the current value thrown away.
529 *
530 * When this is applied to the state (2) we'll simply be AND'ing it with the
531 * (old) mask (3) and adding the register to the mask. This way we'll
532 * preserve the high priority IEMLIVENESS_STATE_XCPT_OR_CALL and
533 * IEMLIVENESS_STATE_INPUT states. */
534# define IEMLIVENESS_STATE_CLOBBERED 0
535/** The register is unused in the remainder of the TB.
536 *
537 * This is an initial state and can not be set by any of the
538 * iemNativeLivenessFunc_xxxx callbacks. */
539# define IEMLIVENESS_STATE_UNUSED 1
540/** The register value is required in a potential call or exception.
541 *
542 * This means that the register value must be calculated and is best written to
543 * the state, but that any shadowing registers can be flushed thereafter as it's
544 * not used again. This state has lower priority than IEMLIVENESS_STATE_INPUT.
545 *
546 * It is typically applied across the board, but we preserve incoming
547 * IEMLIVENESS_STATE_INPUT values. This latter means we have to do some extra
548 * trickery to filter out IEMLIVENESS_STATE_UNUSED:
549 * 1. r0 = old & ~mask;
550 * 2. r0 = t1 & (t1 >> 1)'
551 * 3. state |= r0 | 0b10;
552 * 4. mask = ~0;
553 */
554# define IEMLIVENESS_STATE_XCPT_OR_CALL 2
555/** The register value is used as input.
556 *
557 * This means that the register value must be calculated and it is best to keep
558 * it in a register. It does not need to be writtent out as such. This is the
559 * highest priority state.
560 *
561 * Whether the call modifies the register or not isn't relevant to earlier
562 * calls, so that's not recorded.
563 *
564 * When applying this state we just or in the value in the outgoing state and
565 * mask. */
566# define IEMLIVENESS_STATE_INPUT 3
567/** Mask of the state bits. */
568# define IEMLIVENESS_STATE_MASK 3
569/** The number of bits per state. */
570# define IEMLIVENESS_STATE_BIT_COUNT 2
571/** Check if we're expecting read & write accesses to a register with the given (previous) liveness state. */
572# define IEMLIVENESS_STATE_IS_MODIFY_EXPECTED(a_uState) ((uint32_t)((a_uState) - 1U) >= (uint32_t)(IEMLIVENESS_STATE_INPUT - 1U))
573/** Check if we're expecting read accesses to a register with the given (previous) liveness state. */
574# define IEMLIVENESS_STATE_IS_INPUT_EXPECTED(a_uState) IEMLIVENESS_STATE_IS_MODIFY_EXPECTED(a_uState)
575/** Check if a register clobbering is expected given the (previous) liveness state.
576 * The state must be either CLOBBERED or XCPT_OR_CALL, but it may also
577 * include INPUT if the register is used in more than one place. */
578# define IEMLIVENESS_STATE_IS_CLOBBER_EXPECTED(a_uState) ((uint32_t)(a_uState) != IEMLIVENESS_STATE_UNUSED)
579
580#else /* IEMLIVENESS_EXTENDED_LAYOUT */
581/** The register is not used any more. */
582# define IEMLIVENESS_STATE_UNUSED 0
583/** Flag: The register is required in a potential exception or call. */
584# define IEMLIVENESS_STATE_POT_XCPT_OR_CALL 1
585# define IEMLIVENESS_BIT_POT_XCPT_OR_CALL 0
586/** Flag: The register is read. */
587# define IEMLIVENESS_STATE_READ 2
588# define IEMLIVENESS_BIT_READ 1
589/** Flag: The register is written. */
590# define IEMLIVENESS_STATE_WRITE 4
591# define IEMLIVENESS_BIT_WRITE 2
592/** Flag: Unconditional call (not needed, can be redefined for research). */
593# define IEMLIVENESS_STATE_CALL 8
594# define IEMLIVENESS_BIT_CALL 3
595# define IEMLIVENESS_BIT_OTHER 3 /**< More convenient name for this one. */
596# define IEMLIVENESS_STATE_IS_MODIFY_EXPECTED(a_uState) \
597 ( ((a_uState) & (IEMLIVENESS_STATE_WRITE | IEMLIVENESS_STATE_READ)) == (IEMLIVENESS_STATE_WRITE | IEMLIVENESS_STATE_READ) )
598# define IEMLIVENESS_STATE_IS_INPUT_EXPECTED(a_uState) RT_BOOL((a_uState) & IEMLIVENESS_STATE_READ)
599# define IEMLIVENESS_STATE_IS_CLOBBER_EXPECTED(a_uState) RT_BOOL((a_uState) & IEMLIVENESS_STATE_WRITE)
600#endif /* IEMLIVENESS_EXTENDED_LAYOUT */
601/** @} */
602
603/** @name Liveness helpers for builtin functions and similar.
604 *
605 * These are not used by IEM_MC_BEGIN/END blocks, IEMAllN8veLiveness.cpp has its
606 * own set of manimulator macros for those.
607 *
608 * @{ */
609/** Initializing the state as all unused. */
610#ifndef IEMLIVENESS_EXTENDED_LAYOUT
611# define IEM_LIVENESS_RAW_INIT_AS_UNUSED(a_pOutgoing) \
612 do { \
613 (a_pOutgoing)->Bit0.bm64 = IEMLIVENESSBIT0_ALL_UNUSED; \
614 (a_pOutgoing)->Bit1.bm64 = IEMLIVENESSBIT1_ALL_UNUSED; \
615 } while (0)
616#else
617# define IEM_LIVENESS_RAW_INIT_AS_UNUSED(a_pOutgoing) \
618 do { \
619 (a_pOutgoing)->aBits[IEMLIVENESS_BIT_POT_XCPT_OR_CALL].bm64 = 0; \
620 (a_pOutgoing)->aBits[IEMLIVENESS_BIT_READ ].bm64 = 0; \
621 (a_pOutgoing)->aBits[IEMLIVENESS_BIT_WRITE ].bm64 = 0; \
622 (a_pOutgoing)->aBits[IEMLIVENESS_BIT_OTHER ].bm64 = 0; \
623 } while (0)
624#endif
625
626/** Initializing the outgoing state with a potential xcpt or call state.
627 * This only works when all later changes will be IEMLIVENESS_STATE_INPUT. */
628#ifndef IEMLIVENESS_EXTENDED_LAYOUT
629# define IEM_LIVENESS_RAW_INIT_WITH_XCPT_OR_CALL(a_pOutgoing, a_pIncoming) \
630 do { \
631 (a_pOutgoing)->Bit0.bm64 = (a_pIncoming)->Bit0.bm64 & (a_pIncoming)->Bit1.bm64; \
632 (a_pOutgoing)->Bit1.bm64 = IEMLIVENESSBIT1_XCPT_OR_CALL; \
633 } while (0)
634#else
635# define IEM_LIVENESS_RAW_INIT_WITH_XCPT_OR_CALL(a_pOutgoing, a_pIncoming) \
636 do { \
637 (a_pOutgoing)->aBits[IEMLIVENESS_BIT_POT_XCPT_OR_CALL].bm64 = IEMLIVENESSBIT_MASK; \
638 (a_pOutgoing)->aBits[IEMLIVENESS_BIT_READ ].bm64 = (a_pIncoming)->aBits[IEMLIVENESS_BIT_READ].bm64; \
639 (a_pOutgoing)->aBits[IEMLIVENESS_BIT_WRITE ].bm64 = 0; \
640 (a_pOutgoing)->aBits[IEMLIVENESS_BIT_OTHER ].bm64 = 0; \
641 } while (0)
642#endif
643
644/** Adds a segment base register as input to the outgoing state. */
645#ifndef IEMLIVENESS_EXTENDED_LAYOUT
646# define IEM_LIVENESS_RAW_SEG_BASE_INPUT(a_pOutgoing, a_iSReg) do { \
647 (a_pOutgoing)->Bit0.bmSegBase |= RT_BIT_64(a_iSReg); \
648 (a_pOutgoing)->Bit1.bmSegBase |= RT_BIT_64(a_iSReg); \
649 } while (0)
650#else
651# define IEM_LIVENESS_RAW_SEG_BASE_INPUT(a_pOutgoing, a_iSReg) do { \
652 (a_pOutgoing)->aBits[IEMLIVENESS_BIT_READ].bmSegBase |= RT_BIT_64(a_iSReg); \
653 } while (0)
654#endif
655
656/** Adds a segment attribute register as input to the outgoing state. */
657#ifndef IEMLIVENESS_EXTENDED_LAYOUT
658# define IEM_LIVENESS_RAW_SEG_ATTRIB_INPUT(a_pOutgoing, a_iSReg) do { \
659 (a_pOutgoing)->Bit0.bmSegAttrib |= RT_BIT_64(a_iSReg); \
660 (a_pOutgoing)->Bit1.bmSegAttrib |= RT_BIT_64(a_iSReg); \
661 } while (0)
662#else
663# define IEM_LIVENESS_RAW_SEG_ATTRIB_INPUT(a_pOutgoing, a_iSReg) do { \
664 (a_pOutgoing)->aBits[IEMLIVENESS_BIT_READ].bmSegAttrib |= RT_BIT_64(a_iSReg); \
665 } while (0)
666#endif
667
668/** Adds a segment limit register as input to the outgoing state. */
669#ifndef IEMLIVENESS_EXTENDED_LAYOUT
670# define IEM_LIVENESS_RAW_SEG_LIMIT_INPUT(a_pOutgoing, a_iSReg) do { \
671 (a_pOutgoing)->Bit0.bmSegLimit |= RT_BIT_64(a_iSReg); \
672 (a_pOutgoing)->Bit1.bmSegLimit |= RT_BIT_64(a_iSReg); \
673 } while (0)
674#else
675# define IEM_LIVENESS_RAW_SEG_LIMIT_INPUT(a_pOutgoing, a_iSReg) do { \
676 (a_pOutgoing)->aBits[IEMLIVENESS_BIT_READ].bmSegLimit |= RT_BIT_64(a_iSReg); \
677 } while (0)
678#endif
679
680/** Adds a segment limit register as input to the outgoing state. */
681#ifndef IEMLIVENESS_EXTENDED_LAYOUT
682# define IEM_LIVENESS_RAW_EFLAGS_ONE_INPUT(a_pOutgoing, a_fEflMember) do { \
683 (a_pOutgoing)->Bit0.a_fEflMember |= 1; \
684 (a_pOutgoing)->Bit1.a_fEflMember |= 1; \
685 } while (0)
686#else
687# define IEM_LIVENESS_RAW_EFLAGS_ONE_INPUT(a_pOutgoing, a_fEflMember) do { \
688 (a_pOutgoing)->aBits[IEMLIVENESS_BIT_READ].a_fEflMember |= 1; \
689 } while (0)
690#endif
691/** @} */
692
693/**
694 * Guest registers that can be shadowed in GPRs.
695 *
696 * This runs parallel to the liveness state (IEMLIVENESSBIT, ++). The EFlags
697 * must be placed last, as the liveness state tracks it as 7 subcomponents and
698 * we don't want to waste space here.
699 *
700 * @note Make sure to update IEMLIVENESSBIT, IEMLIVENESSBIT_ALL_EFL_MASK and
701 * friends as well as IEMAllN8veLiveness.cpp.
702 */
703typedef enum IEMNATIVEGSTREG : uint8_t
704{
705 kIemNativeGstReg_GprFirst = 0,
706 kIemNativeGstReg_GprLast = kIemNativeGstReg_GprFirst + 15,
707 kIemNativeGstReg_Pc,
708 kIemNativeGstReg_Cr0,
709 kIemNativeGstReg_FpuFcw,
710 kIemNativeGstReg_FpuFsw,
711 kIemNativeGstReg_SegBaseFirst,
712 kIemNativeGstReg_SegBaseLast = kIemNativeGstReg_SegBaseFirst + 5,
713 kIemNativeGstReg_SegAttribFirst,
714 kIemNativeGstReg_SegAttribLast = kIemNativeGstReg_SegAttribFirst + 5,
715 kIemNativeGstReg_SegLimitFirst,
716 kIemNativeGstReg_SegLimitLast = kIemNativeGstReg_SegLimitFirst + 5,
717 kIemNativeGstReg_SegSelFirst,
718 kIemNativeGstReg_SegSelLast = kIemNativeGstReg_SegSelFirst + 5,
719 kIemNativeGstReg_Cr4,
720 kIemNativeGstReg_Xcr0,
721 kIemNativeGstReg_MxCsr,
722 kIemNativeGstReg_EFlags, /**< 32-bit, includes internal flags - last! */
723 kIemNativeGstReg_End
724} IEMNATIVEGSTREG;
725AssertCompile((int)kIemNativeGstReg_SegLimitFirst == 32);
726AssertCompile((UINT64_C(0x7f) << kIemNativeGstReg_EFlags) == IEMLIVENESSBIT_ALL_EFL_MASK);
727
728/** @name Helpers for converting register numbers to IEMNATIVEGSTREG values.
729 * @{ */
730#define IEMNATIVEGSTREG_GPR(a_iGpr) ((IEMNATIVEGSTREG)(kIemNativeGstReg_GprFirst + (a_iGpr) ))
731#define IEMNATIVEGSTREG_SEG_SEL(a_iSegReg) ((IEMNATIVEGSTREG)(kIemNativeGstReg_SegSelFirst + (a_iSegReg) ))
732#define IEMNATIVEGSTREG_SEG_BASE(a_iSegReg) ((IEMNATIVEGSTREG)(kIemNativeGstReg_SegBaseFirst + (a_iSegReg) ))
733#define IEMNATIVEGSTREG_SEG_LIMIT(a_iSegReg) ((IEMNATIVEGSTREG)(kIemNativeGstReg_SegLimitFirst + (a_iSegReg) ))
734#define IEMNATIVEGSTREG_SEG_ATTRIB(a_iSegReg) ((IEMNATIVEGSTREG)(kIemNativeGstReg_SegAttribFirst + (a_iSegReg) ))
735/** @} */
736
737/**
738 * Intended use statement for iemNativeRegAllocTmpForGuestReg().
739 */
740typedef enum IEMNATIVEGSTREGUSE
741{
742 /** The usage is read-only, the register holding the guest register
743 * shadow copy will not be modified by the caller. */
744 kIemNativeGstRegUse_ReadOnly = 0,
745 /** The caller will update the guest register (think: PC += cbInstr).
746 * The guest shadow copy will follow the returned register. */
747 kIemNativeGstRegUse_ForUpdate,
748 /** The call will put an entirely new value in the guest register, so
749 * if new register is allocate it will be returned uninitialized. */
750 kIemNativeGstRegUse_ForFullWrite,
751 /** The caller will use the guest register value as input in a calculation
752 * and the host register will be modified.
753 * This means that the returned host register will not be marked as a shadow
754 * copy of the guest register. */
755 kIemNativeGstRegUse_Calculation
756} IEMNATIVEGSTREGUSE;
757
758/**
759 * Guest registers (classes) that can be referenced.
760 */
761typedef enum IEMNATIVEGSTREGREF : uint8_t
762{
763 kIemNativeGstRegRef_Invalid = 0,
764 kIemNativeGstRegRef_Gpr,
765 kIemNativeGstRegRef_GprHighByte, /**< AH, CH, DH, BH*/
766 kIemNativeGstRegRef_EFlags,
767 kIemNativeGstRegRef_MxCsr,
768 kIemNativeGstRegRef_FpuReg,
769 kIemNativeGstRegRef_MReg,
770 kIemNativeGstRegRef_XReg,
771 //kIemNativeGstRegRef_YReg, - doesn't work.
772 kIemNativeGstRegRef_End
773} IEMNATIVEGSTREGREF;
774
775
776/** Variable kinds. */
777typedef enum IEMNATIVEVARKIND : uint8_t
778{
779 /** Customary invalid zero value. */
780 kIemNativeVarKind_Invalid = 0,
781 /** This is either in a register or on the stack. */
782 kIemNativeVarKind_Stack,
783 /** Immediate value - loaded into register when needed, or can live on the
784 * stack if referenced (in theory). */
785 kIemNativeVarKind_Immediate,
786 /** Variable reference - loaded into register when needed, never stack. */
787 kIemNativeVarKind_VarRef,
788 /** Guest register reference - loaded into register when needed, never stack. */
789 kIemNativeVarKind_GstRegRef,
790 /** End of valid values. */
791 kIemNativeVarKind_End
792} IEMNATIVEVARKIND;
793
794
795/** Variable or argument. */
796typedef struct IEMNATIVEVAR
797{
798 /** The kind of variable. */
799 IEMNATIVEVARKIND enmKind;
800 /** The variable size in bytes. */
801 uint8_t cbVar;
802 /** The first stack slot (uint64_t), except for immediate and references
803 * where it usually is UINT8_MAX. This is allocated lazily, so if a variable
804 * has a stack slot it has been initialized and has a value. Unused variables
805 * has neither a stack slot nor a host register assignment. */
806 uint8_t idxStackSlot;
807 /** The host register allocated for the variable, UINT8_MAX if not. */
808 uint8_t idxReg;
809 /** The argument number if argument, UINT8_MAX if regular variable. */
810 uint8_t uArgNo;
811 /** If referenced, the index (unpacked) of the variable referencing this one,
812 * otherwise UINT8_MAX. A referenced variable must only be placed on the stack
813 * and must be either kIemNativeVarKind_Stack or kIemNativeVarKind_Immediate. */
814 uint8_t idxReferrerVar;
815 /** Guest register being shadowed here, kIemNativeGstReg_End(/UINT8_MAX) if not.
816 * @todo not sure what this really is for... */
817 IEMNATIVEGSTREG enmGstReg;
818 /** Set if the registered is currently used exclusively, false if the
819 * variable is idle and the register can be grabbed. */
820 bool fRegAcquired;
821
822 union
823 {
824 /** kIemNativeVarKind_Immediate: The immediate value. */
825 uint64_t uValue;
826 /** kIemNativeVarKind_VarRef: The index (unpacked) of the variable being referenced. */
827 uint8_t idxRefVar;
828 /** kIemNativeVarKind_GstRegRef: The guest register being referrenced. */
829 struct
830 {
831 /** The class of register. */
832 IEMNATIVEGSTREGREF enmClass;
833 /** Index within the class. */
834 uint8_t idx;
835 } GstRegRef;
836 } u;
837} IEMNATIVEVAR;
838/** Pointer to a variable or argument. */
839typedef IEMNATIVEVAR *PIEMNATIVEVAR;
840/** Pointer to a const variable or argument. */
841typedef IEMNATIVEVAR const *PCIEMNATIVEVAR;
842
843/** What is being kept in a host register. */
844typedef enum IEMNATIVEWHAT : uint8_t
845{
846 /** The traditional invalid zero value. */
847 kIemNativeWhat_Invalid = 0,
848 /** Mapping a variable (IEMNATIVEHSTREG::idxVar). */
849 kIemNativeWhat_Var,
850 /** Temporary register, this is typically freed when a MC completes. */
851 kIemNativeWhat_Tmp,
852 /** Call argument w/o a variable mapping. This is free (via
853 * IEMNATIVE_CALL_VOLATILE_GREG_MASK) after the call is emitted. */
854 kIemNativeWhat_Arg,
855 /** Return status code.
856 * @todo not sure if we need this... */
857 kIemNativeWhat_rc,
858 /** The fixed pVCpu (PVMCPUCC) register.
859 * @todo consider offsetting this on amd64 to use negative offsets to access
860 * more members using 8-byte disp. */
861 kIemNativeWhat_pVCpuFixed,
862 /** The fixed pCtx (PCPUMCTX) register.
863 * @todo consider offsetting this on amd64 to use negative offsets to access
864 * more members using 8-byte disp. */
865 kIemNativeWhat_pCtxFixed,
866 /** Fixed temporary register. */
867 kIemNativeWhat_FixedTmp,
868#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
869 /** Shadow RIP for the delayed RIP updating debugging. */
870 kIemNativeWhat_PcShadow,
871#endif
872 /** Register reserved by the CPU or OS architecture. */
873 kIemNativeWhat_FixedReserved,
874 /** End of valid values. */
875 kIemNativeWhat_End
876} IEMNATIVEWHAT;
877
878/**
879 * Host general register entry.
880 *
881 * The actual allocation status is kept in IEMRECOMPILERSTATE::bmHstRegs.
882 *
883 * @todo Track immediate values in host registers similarlly to how we track the
884 * guest register shadow copies. For it to be real helpful, though,
885 * we probably need to know which will be reused and put them into
886 * non-volatile registers, otherwise it's going to be more or less
887 * restricted to an instruction or two.
888 */
889typedef struct IEMNATIVEHSTREG
890{
891 /** Set of guest registers this one shadows.
892 *
893 * Using a bitmap here so we can designate the same host register as a copy
894 * for more than one guest register. This is expected to be useful in
895 * situations where one value is copied to several registers in a sequence.
896 * If the mapping is 1:1, then we'd have to pick which side of a 'MOV SRC,DST'
897 * sequence we'd want to let this register follow to be a copy of and there
898 * will always be places where we'd be picking the wrong one.
899 */
900 uint64_t fGstRegShadows;
901 /** What is being kept in this register. */
902 IEMNATIVEWHAT enmWhat;
903 /** Variable index (packed) if holding a variable, otherwise UINT8_MAX. */
904 uint8_t idxVar;
905 /** Stack slot assigned by iemNativeVarSaveVolatileRegsPreHlpCall and freed
906 * by iemNativeVarRestoreVolatileRegsPostHlpCall. This is not valid outside
907 * that scope. */
908 uint8_t idxStackSlot;
909 /** Alignment padding. */
910 uint8_t abAlign[5];
911} IEMNATIVEHSTREG;
912
913
914/**
915 * Core state for the native recompiler, that is, things that needs careful
916 * handling when dealing with branches.
917 */
918typedef struct IEMNATIVECORESTATE
919{
920#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
921 /** The current instruction offset in bytes from when the guest program counter
922 * was updated last. Used for delaying the write to the guest context program counter
923 * as long as possible. */
924 uint32_t offPc;
925 /** Number of instructions where we could skip the updating. */
926 uint32_t cInstrPcUpdateSkipped;
927#endif
928 /** Allocation bitmap for aHstRegs. */
929 uint32_t bmHstRegs;
930
931 /** Bitmap marking which host register contains guest register shadow copies.
932 * This is used during register allocation to try preserve copies. */
933 uint32_t bmHstRegsWithGstShadow;
934 /** Bitmap marking valid entries in aidxGstRegShadows. */
935 uint64_t bmGstRegShadows;
936
937 union
938 {
939 /** Index of variable (unpacked) arguments, UINT8_MAX if not valid. */
940 uint8_t aidxArgVars[8];
941 /** For more efficient resetting. */
942 uint64_t u64ArgVars;
943 };
944
945 /** Allocation bitmap for the stack. */
946 uint32_t bmStack;
947 /** Allocation bitmap for aVars. */
948 uint32_t bmVars;
949
950 /** Maps a guest register to a host GPR (index by IEMNATIVEGSTREG).
951 * Entries are only valid if the corresponding bit in bmGstRegShadows is set.
952 * (A shadow copy of a guest register can only be held in a one host register,
953 * there are no duplicate copies or ambiguities like that). */
954 uint8_t aidxGstRegShadows[kIemNativeGstReg_End];
955
956 /** Host register allocation tracking. */
957 IEMNATIVEHSTREG aHstRegs[IEMNATIVE_HST_GREG_COUNT];
958
959 /** Variables and arguments. */
960 IEMNATIVEVAR aVars[9];
961} IEMNATIVECORESTATE;
962/** Pointer to core state. */
963typedef IEMNATIVECORESTATE *PIEMNATIVECORESTATE;
964/** Pointer to const core state. */
965typedef IEMNATIVECORESTATE const *PCIEMNATIVECORESTATE;
966
967/** @def IEMNATIVE_VAR_IDX_UNPACK
968 * @returns Index into IEMNATIVECORESTATE::aVars.
969 * @param a_idxVar Variable index w/ magic (in strict builds).
970 */
971/** @def IEMNATIVE_VAR_IDX_PACK
972 * @returns Variable index w/ magic (in strict builds).
973 * @param a_idxVar Index into IEMNATIVECORESTATE::aVars.
974 */
975#ifdef VBOX_STRICT
976# define IEMNATIVE_VAR_IDX_UNPACK(a_idxVar) ((a_idxVar) & IEMNATIVE_VAR_IDX_MASK)
977# define IEMNATIVE_VAR_IDX_PACK(a_idxVar) ((a_idxVar) | IEMNATIVE_VAR_IDX_MAGIC)
978# define IEMNATIVE_VAR_IDX_MAGIC UINT8_C(0xd0)
979# define IEMNATIVE_VAR_IDX_MAGIC_MASK UINT8_C(0xf0)
980# define IEMNATIVE_VAR_IDX_MASK UINT8_C(0x0f)
981#else
982# define IEMNATIVE_VAR_IDX_UNPACK(a_idxVar) (a_idxVar)
983# define IEMNATIVE_VAR_IDX_PACK(a_idxVar) (a_idxVar)
984#endif
985
986
987/**
988 * Conditional stack entry.
989 */
990typedef struct IEMNATIVECOND
991{
992 /** Set if we're in the "else" part, clear if we're in the "if" before it. */
993 bool fInElse;
994 /** The label for the IEM_MC_ELSE. */
995 uint32_t idxLabelElse;
996 /** The label for the IEM_MC_ENDIF. */
997 uint32_t idxLabelEndIf;
998 /** The initial state snapshot as the if-block starts executing. */
999 IEMNATIVECORESTATE InitialState;
1000 /** The state snapshot at the end of the if-block. */
1001 IEMNATIVECORESTATE IfFinalState;
1002} IEMNATIVECOND;
1003/** Pointer to a condition stack entry. */
1004typedef IEMNATIVECOND *PIEMNATIVECOND;
1005
1006
1007/**
1008 * Native recompiler state.
1009 */
1010typedef struct IEMRECOMPILERSTATE
1011{
1012 /** Size of the buffer that pbNativeRecompileBufR3 points to in
1013 * IEMNATIVEINSTR units. */
1014 uint32_t cInstrBufAlloc;
1015#ifdef VBOX_STRICT
1016 /** Strict: How far the last iemNativeInstrBufEnsure() checked. */
1017 uint32_t offInstrBufChecked;
1018#else
1019 uint32_t uPadding1; /* We don't keep track of the size here... */
1020#endif
1021 /** Fixed temporary code buffer for native recompilation. */
1022 PIEMNATIVEINSTR pInstrBuf;
1023
1024 /** Bitmaps with the label types used. */
1025 uint64_t bmLabelTypes;
1026 /** Actual number of labels in paLabels. */
1027 uint32_t cLabels;
1028 /** Max number of entries allowed in paLabels before reallocating it. */
1029 uint32_t cLabelsAlloc;
1030 /** Labels defined while recompiling (referenced by fixups). */
1031 PIEMNATIVELABEL paLabels;
1032 /** Array with indexes of unique labels (uData always 0). */
1033 uint32_t aidxUniqueLabels[kIemNativeLabelType_FirstWithMultipleInstances];
1034
1035 /** Actual number of fixups paFixups. */
1036 uint32_t cFixups;
1037 /** Max number of entries allowed in paFixups before reallocating it. */
1038 uint32_t cFixupsAlloc;
1039 /** Buffer used by the recompiler for recording fixups when generating code. */
1040 PIEMNATIVEFIXUP paFixups;
1041
1042#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
1043 /** Number of debug info entries allocated for pDbgInfo. */
1044 uint32_t cDbgInfoAlloc;
1045 uint32_t uPadding;
1046 /** Debug info. */
1047 PIEMTBDBG pDbgInfo;
1048#endif
1049
1050#ifdef IEMNATIVE_WITH_LIVENESS_ANALYSIS
1051 /** The current call index (liveness array and threaded calls in TB). */
1052 uint32_t idxCurCall;
1053 /** Number of liveness entries allocated. */
1054 uint32_t cLivenessEntriesAlloc;
1055 /** Liveness entries for all the calls in the TB begin recompiled.
1056 * The entry for idxCurCall contains the info for what the next call will
1057 * require wrt registers. (Which means the last entry is the initial liveness
1058 * state.) */
1059 PIEMLIVENESSENTRY paLivenessEntries;
1060#endif
1061
1062 /** The translation block being recompiled. */
1063 PCIEMTB pTbOrg;
1064 /** The VMCPU structure of the EMT. */
1065 PVMCPUCC pVCpu;
1066
1067 /** Condition sequence number (for generating unique labels). */
1068 uint16_t uCondSeqNo;
1069 /** Check IRQ seqeunce number (for generating unique labels). */
1070 uint16_t uCheckIrqSeqNo;
1071 /** TLB load sequence number (for generating unique labels). */
1072 uint16_t uTlbSeqNo;
1073 /** The current condition stack depth (aCondStack). */
1074 uint8_t cCondDepth;
1075
1076 /** The argument count + hidden regs from the IEM_MC_BEGIN statement. */
1077 uint8_t cArgs;
1078 /** The IEM_CIMPL_F_XXX flags from the IEM_MC_BEGIN statement. */
1079 uint32_t fCImpl;
1080 /** The IEM_MC_F_XXX flags from the IEM_MC_BEGIN statement. */
1081 uint32_t fMc;
1082 /** The expected IEMCPU::fExec value for the current call/instruction. */
1083 uint32_t fExec;
1084
1085 /** Core state requiring care with branches. */
1086 IEMNATIVECORESTATE Core;
1087
1088 /** The condition nesting stack. */
1089 IEMNATIVECOND aCondStack[2];
1090
1091#ifndef IEM_WITH_THROW_CATCH
1092 /** Pointer to the setjmp/longjmp buffer if we're not using C++ exceptions
1093 * for recompilation error handling. */
1094 jmp_buf JmpBuf;
1095#endif
1096} IEMRECOMPILERSTATE;
1097/** Pointer to a native recompiler state. */
1098typedef IEMRECOMPILERSTATE *PIEMRECOMPILERSTATE;
1099
1100
1101/** @def IEMNATIVE_TRY_SETJMP
1102 * Wrapper around setjmp / try, hiding all the ugly differences.
1103 *
1104 * @note Use with extreme care as this is a fragile macro.
1105 * @param a_pReNative The native recompile state.
1106 * @param a_rcTarget The variable that should receive the status code in case
1107 * of a longjmp/throw.
1108 */
1109/** @def IEMNATIVE_CATCH_LONGJMP_BEGIN
1110 * Start wrapper for catch / setjmp-else.
1111 *
1112 * This will set up a scope.
1113 *
1114 * @note Use with extreme care as this is a fragile macro.
1115 * @param a_pReNative The native recompile state.
1116 * @param a_rcTarget The variable that should receive the status code in case
1117 * of a longjmp/throw.
1118 */
1119/** @def IEMNATIVE_CATCH_LONGJMP_END
1120 * End wrapper for catch / setjmp-else.
1121 *
1122 * This will close the scope set up by IEMNATIVE_CATCH_LONGJMP_BEGIN and clean
1123 * up the state.
1124 *
1125 * @note Use with extreme care as this is a fragile macro.
1126 * @param a_pReNative The native recompile state.
1127 */
1128/** @def IEMNATIVE_DO_LONGJMP
1129 *
1130 * Wrapper around longjmp / throw.
1131 *
1132 * @param a_pReNative The native recompile state.
1133 * @param a_rc The status code jump back with / throw.
1134 */
1135#ifdef IEM_WITH_THROW_CATCH
1136# define IEMNATIVE_TRY_SETJMP(a_pReNative, a_rcTarget) \
1137 a_rcTarget = VINF_SUCCESS; \
1138 try
1139# define IEMNATIVE_CATCH_LONGJMP_BEGIN(a_pReNative, a_rcTarget) \
1140 catch (int rcThrown) \
1141 { \
1142 a_rcTarget = rcThrown
1143# define IEMNATIVE_CATCH_LONGJMP_END(a_pReNative) \
1144 } \
1145 ((void)0)
1146# define IEMNATIVE_DO_LONGJMP(a_pReNative, a_rc) throw int(a_rc)
1147#else /* !IEM_WITH_THROW_CATCH */
1148# define IEMNATIVE_TRY_SETJMP(a_pReNative, a_rcTarget) \
1149 if ((a_rcTarget = setjmp((a_pReNative)->JmpBuf)) == 0)
1150# define IEMNATIVE_CATCH_LONGJMP_BEGIN(a_pReNative, a_rcTarget) \
1151 else \
1152 { \
1153 ((void)0)
1154# define IEMNATIVE_CATCH_LONGJMP_END(a_pReNative) \
1155 }
1156# define IEMNATIVE_DO_LONGJMP(a_pReNative, a_rc) longjmp((a_pReNative)->JmpBuf, (a_rc))
1157#endif /* !IEM_WITH_THROW_CATCH */
1158
1159
1160/**
1161 * Native recompiler worker for a threaded function.
1162 *
1163 * @returns New code buffer offset; throws VBox status code in case of a failure.
1164 * @param pReNative The native recompiler state.
1165 * @param off The current code buffer offset.
1166 * @param pCallEntry The threaded call entry.
1167 *
1168 * @note This may throw/longjmp VBox status codes (int) to abort compilation, so no RT_NOEXCEPT!
1169 */
1170typedef uint32_t (VBOXCALL FNIEMNATIVERECOMPFUNC)(PIEMRECOMPILERSTATE pReNative, uint32_t off, PCIEMTHRDEDCALLENTRY pCallEntry);
1171/** Pointer to a native recompiler worker for a threaded function. */
1172typedef FNIEMNATIVERECOMPFUNC *PFNIEMNATIVERECOMPFUNC;
1173
1174/** Defines a native recompiler worker for a threaded function.
1175 * @see FNIEMNATIVERECOMPFUNC */
1176#define IEM_DECL_IEMNATIVERECOMPFUNC_DEF(a_Name) \
1177 uint32_t VBOXCALL a_Name(PIEMRECOMPILERSTATE pReNative, uint32_t off, PCIEMTHRDEDCALLENTRY pCallEntry)
1178
1179/** Prototypes a native recompiler function for a threaded function.
1180 * @see FNIEMNATIVERECOMPFUNC */
1181#define IEM_DECL_IEMNATIVERECOMPFUNC_PROTO(a_Name) FNIEMNATIVERECOMPFUNC a_Name
1182
1183
1184/**
1185 * Native recompiler liveness analysis worker for a threaded function.
1186 *
1187 * @param pCallEntry The threaded call entry.
1188 * @param pIncoming The incoming liveness state entry.
1189 * @param pOutgoing The outgoing liveness state entry.
1190 */
1191typedef DECLCALLBACKTYPE(void, FNIEMNATIVELIVENESSFUNC, (PCIEMTHRDEDCALLENTRY pCallEntry,
1192 PCIEMLIVENESSENTRY pIncoming, PIEMLIVENESSENTRY pOutgoing));
1193/** Pointer to a native recompiler liveness analysis worker for a threaded function. */
1194typedef FNIEMNATIVELIVENESSFUNC *PFNIEMNATIVELIVENESSFUNC;
1195
1196/** Defines a native recompiler liveness analysis worker for a threaded function.
1197 * @see FNIEMNATIVELIVENESSFUNC */
1198#define IEM_DECL_IEMNATIVELIVENESSFUNC_DEF(a_Name) \
1199 DECLCALLBACK(void) a_Name(PCIEMTHRDEDCALLENTRY pCallEntry, PCIEMLIVENESSENTRY pIncoming, PIEMLIVENESSENTRY pOutgoing)
1200
1201/** Prototypes a native recompiler liveness analysis function for a threaded function.
1202 * @see FNIEMNATIVELIVENESSFUNC */
1203#define IEM_DECL_IEMNATIVELIVENESSFUNC_PROTO(a_Name) FNIEMNATIVELIVENESSFUNC a_Name
1204
1205
1206/** Define a native recompiler helper function, safe to call from the TB code. */
1207#define IEM_DECL_NATIVE_HLP_DEF(a_RetType, a_Name, a_ArgList) \
1208 DECL_HIDDEN_THROW(a_RetType) VBOXCALL a_Name a_ArgList
1209/** Prototype a native recompiler helper function, safe to call from the TB code. */
1210#define IEM_DECL_NATIVE_HLP_PROTO(a_RetType, a_Name, a_ArgList) \
1211 DECL_HIDDEN_THROW(a_RetType) VBOXCALL a_Name a_ArgList
1212
1213
1214DECL_HIDDEN_THROW(uint32_t) iemNativeLabelCreate(PIEMRECOMPILERSTATE pReNative, IEMNATIVELABELTYPE enmType,
1215 uint32_t offWhere = UINT32_MAX, uint16_t uData = 0);
1216DECL_HIDDEN_THROW(void) iemNativeLabelDefine(PIEMRECOMPILERSTATE pReNative, uint32_t idxLabel, uint32_t offWhere);
1217DECL_HIDDEN_THROW(void) iemNativeAddFixup(PIEMRECOMPILERSTATE pReNative, uint32_t offWhere, uint32_t idxLabel,
1218 IEMNATIVEFIXUPTYPE enmType, int8_t offAddend = 0);
1219DECL_HIDDEN_THROW(PIEMNATIVEINSTR) iemNativeInstrBufEnsureSlow(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t cInstrReq);
1220
1221DECL_HIDDEN_THROW(uint8_t) iemNativeRegAllocTmp(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, bool fPreferVolatile = true);
1222DECL_HIDDEN_THROW(uint8_t) iemNativeRegAllocTmpEx(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, uint32_t fRegMask,
1223 bool fPreferVolatile = true);
1224DECL_HIDDEN_THROW(uint8_t) iemNativeRegAllocTmpImm(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, uint64_t uImm,
1225 bool fPreferVolatile = true);
1226DECL_HIDDEN_THROW(uint8_t) iemNativeRegAllocTmpForGuestReg(PIEMRECOMPILERSTATE pReNative, uint32_t *poff,
1227 IEMNATIVEGSTREG enmGstReg,
1228 IEMNATIVEGSTREGUSE enmIntendedUse = kIemNativeGstRegUse_ReadOnly,
1229 bool fNoVolatileRegs = false, bool fSkipLivenessAssert = false);
1230DECL_HIDDEN_THROW(uint8_t) iemNativeRegAllocTmpForGuestRegIfAlreadyPresent(PIEMRECOMPILERSTATE pReNative, uint32_t *poff,
1231 IEMNATIVEGSTREG enmGstReg);
1232
1233DECL_HIDDEN_THROW(uint32_t) iemNativeRegAllocArgs(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t cArgs);
1234DECL_HIDDEN_THROW(uint8_t) iemNativeRegAssignRc(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg);
1235DECLHIDDEN(void) iemNativeRegFree(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg) RT_NOEXCEPT;
1236DECLHIDDEN(void) iemNativeRegFreeTmp(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg) RT_NOEXCEPT;
1237DECLHIDDEN(void) iemNativeRegFreeTmpImm(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg) RT_NOEXCEPT;
1238DECLHIDDEN(void) iemNativeRegFreeVar(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg, bool fFlushShadows) RT_NOEXCEPT;
1239DECLHIDDEN(void) iemNativeRegFreeAndFlushMask(PIEMRECOMPILERSTATE pReNative, uint32_t fHstRegMask) RT_NOEXCEPT;
1240DECL_HIDDEN_THROW(uint32_t) iemNativeRegFlushPendingWrites(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint64_t fGstShwExept = 0);
1241DECL_HIDDEN_THROW(uint32_t) iemNativeRegMoveAndFreeAndFlushAtCall(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t cArgs,
1242 uint32_t fKeepVars = 0);
1243DECLHIDDEN(void) iemNativeRegFlushGuestShadows(PIEMRECOMPILERSTATE pReNative, uint64_t fGstRegs) RT_NOEXCEPT;
1244DECLHIDDEN(void) iemNativeRegFlushGuestShadowsByHostMask(PIEMRECOMPILERSTATE pReNative, uint32_t fHstRegs) RT_NOEXCEPT;
1245DECL_HIDDEN_THROW(uint32_t) iemNativeRegRestoreGuestShadowsInVolatileRegs(PIEMRECOMPILERSTATE pReNative, uint32_t off,
1246 uint32_t fHstRegsActiveShadows);
1247
1248DECL_HIDDEN_THROW(uint8_t) iemNativeVarGetStackSlot(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar);
1249DECL_HIDDEN_THROW(uint8_t) iemNativeVarRegisterAcquire(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar, uint32_t *poff,
1250 bool fInitialized = false, uint8_t idxRegPref = UINT8_MAX);
1251DECL_HIDDEN_THROW(uint8_t) iemNativeVarRegisterAcquireForGuestReg(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar,
1252 IEMNATIVEGSTREG enmGstReg, uint32_t *poff);
1253DECL_HIDDEN_THROW(uint32_t) iemNativeVarSaveVolatileRegsPreHlpCall(PIEMRECOMPILERSTATE pReNative, uint32_t off,
1254 uint32_t fHstRegsNotToSave);
1255DECL_HIDDEN_THROW(uint32_t) iemNativeVarRestoreVolatileRegsPostHlpCall(PIEMRECOMPILERSTATE pReNative, uint32_t off,
1256 uint32_t fHstRegsNotToSave);
1257
1258DECL_HIDDEN_THROW(uint32_t) iemNativeEmitLoadGprWithGstShadowReg(PIEMRECOMPILERSTATE pReNative, uint32_t off,
1259 uint8_t idxHstReg, IEMNATIVEGSTREG enmGstReg);
1260DECL_HIDDEN_THROW(uint32_t) iemNativeEmitCheckCallRetAndPassUp(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxInstr);
1261DECL_HIDDEN_THROW(uint32_t) iemNativeEmitCImplCall(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxInstr,
1262 uint64_t fGstShwFlush, uintptr_t pfnCImpl, uint8_t cbInstr, uint8_t cAddParams,
1263 uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
1264DECL_HIDDEN_THROW(uint32_t) iemNativeEmitThreadedCall(PIEMRECOMPILERSTATE pReNative, uint32_t off,
1265 PCIEMTHRDEDCALLENTRY pCallEntry);
1266
1267extern DECL_HIDDEN_DATA(const char * const) g_apszIemNativeHstRegNames[];
1268
1269
1270/**
1271 * Ensures that there is sufficient space in the instruction output buffer.
1272 *
1273 * This will reallocate the buffer if needed and allowed.
1274 *
1275 * @note Always use IEMNATIVE_ASSERT_INSTR_BUF_ENSURE when done to check the
1276 * allocation size.
1277 *
1278 * @returns Pointer to the instruction output buffer on success; throws VBox
1279 * status code on failure, so no need to check it.
1280 * @param pReNative The native recompile state.
1281 * @param off Current instruction offset. Works safely for UINT32_MAX
1282 * as well.
1283 * @param cInstrReq Number of instruction about to be added. It's okay to
1284 * overestimate this a bit.
1285 */
1286DECL_FORCE_INLINE_THROW(PIEMNATIVEINSTR)
1287iemNativeInstrBufEnsure(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t cInstrReq)
1288{
1289 uint64_t const offChecked = off + (uint64_t)cInstrReq; /** @todo may reconsider the need for UINT32_MAX safety... */
1290 if (RT_LIKELY(offChecked <= pReNative->cInstrBufAlloc))
1291 {
1292#ifdef VBOX_STRICT
1293 pReNative->offInstrBufChecked = offChecked;
1294#endif
1295 return pReNative->pInstrBuf;
1296 }
1297 return iemNativeInstrBufEnsureSlow(pReNative, off, cInstrReq);
1298}
1299
1300/**
1301 * Checks that we didn't exceed the space requested in the last
1302 * iemNativeInstrBufEnsure() call.
1303 */
1304#define IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(a_pReNative, a_off) \
1305 AssertMsg((a_off) <= (a_pReNative)->offInstrBufChecked, \
1306 ("off=%#x offInstrBufChecked=%#x\n", (a_off), (a_pReNative)->offInstrBufChecked))
1307
1308/**
1309 * Checks that a variable index is valid.
1310 */
1311#ifdef IEMNATIVE_VAR_IDX_MAGIC
1312# define IEMNATIVE_ASSERT_VAR_IDX(a_pReNative, a_idxVar) \
1313 AssertMsg( ((a_idxVar) & IEMNATIVE_VAR_IDX_MAGIC_MASK) == IEMNATIVE_VAR_IDX_MAGIC \
1314 && (unsigned)IEMNATIVE_VAR_IDX_UNPACK(a_idxVar) < RT_ELEMENTS((a_pReNative)->Core.aVars) \
1315 && ((a_pReNative)->Core.bmVars & RT_BIT_32(IEMNATIVE_VAR_IDX_UNPACK(a_idxVar))), \
1316 ("%s=%#x\n", #a_idxVar, a_idxVar))
1317#else
1318# define IEMNATIVE_ASSERT_VAR_IDX(a_pReNative, a_idxVar) \
1319 AssertMsg( (unsigned)(a_idxVar) < RT_ELEMENTS((a_pReNative)->Core.aVars) \
1320 && ((a_pReNative)->Core.bmVars & RT_BIT_32(a_idxVar)), ("%s=%d\n", #a_idxVar, a_idxVar))
1321#endif
1322
1323/**
1324 * Checks that a variable index is valid and that the variable is assigned the
1325 * correct argument number.
1326 * This also adds a RT_NOREF of a_idxVar.
1327 */
1328#ifdef IEMNATIVE_VAR_IDX_MAGIC
1329# define IEMNATIVE_ASSERT_ARG_VAR_IDX(a_pReNative, a_idxVar, a_uArgNo) do { \
1330 RT_NOREF_PV(a_idxVar); \
1331 AssertMsg( ((a_idxVar) & IEMNATIVE_VAR_IDX_MAGIC_MASK) == IEMNATIVE_VAR_IDX_MAGIC \
1332 && (unsigned)IEMNATIVE_VAR_IDX_UNPACK(a_idxVar) < RT_ELEMENTS((a_pReNative)->Core.aVars) \
1333 && ((a_pReNative)->Core.bmVars & RT_BIT_32(IEMNATIVE_VAR_IDX_UNPACK(a_idxVar))) \
1334 && (a_pReNative)->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(a_idxVar)].uArgNo == (a_uArgNo), \
1335 ("%s=%d; uArgNo=%d, expected %u\n", #a_idxVar, a_idxVar, \
1336 (a_pReNative)->Core.aVars[RT_MIN(IEMNATIVE_VAR_IDX_UNPACK(a_idxVar), \
1337 RT_ELEMENTS((a_pReNative)->Core.aVars)) - 1].uArgNo, \
1338 a_uArgNo)); \
1339 } while (0)
1340#else
1341# define IEMNATIVE_ASSERT_ARG_VAR_IDX(a_pReNative, a_idxVar, a_uArgNo) do { \
1342 RT_NOREF_PV(a_idxVar); \
1343 AssertMsg( (unsigned)(a_idxVar) < RT_ELEMENTS((a_pReNative)->Core.aVars) \
1344 && ((a_pReNative)->Core.bmVars & RT_BIT_32(a_idxVar))\
1345 && (a_pReNative)->Core.aVars[a_idxVar].uArgNo == (a_uArgNo) \
1346 , ("%s=%d; uArgNo=%d, expected %u\n", #a_idxVar, a_idxVar, \
1347 (a_pReNative)->Core.aVars[RT_MIN(a_idxVar, RT_ELEMENTS((a_pReNative)->Core.aVars)) - 1].uArgNo, a_uArgNo)); \
1348 } while (0)
1349#endif
1350
1351
1352/**
1353 * Checks that a variable has the expected size.
1354 */
1355#define IEMNATIVE_ASSERT_VAR_SIZE(a_pReNative, a_idxVar, a_cbVar) \
1356 AssertMsg((a_pReNative)->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(a_idxVar)].cbVar == (a_cbVar), \
1357 ("%s=%#x: cbVar=%#x, expected %#x!\n", #a_idxVar, a_idxVar, \
1358 (a_pReNative)->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(a_idxVar)].cbVar == (a_cbVar)))
1359
1360
1361/**
1362 * Calculates the stack address of a variable as a [r]BP displacement value.
1363 */
1364DECL_FORCE_INLINE(int32_t)
1365iemNativeStackCalcBpDisp(uint8_t idxStackSlot)
1366{
1367 Assert(idxStackSlot < IEMNATIVE_FRAME_VAR_SLOTS);
1368 return idxStackSlot * sizeof(uint64_t) + IEMNATIVE_FP_OFF_STACK_VARS;
1369}
1370
1371
1372/**
1373 * Releases the variable's register.
1374 *
1375 * The register must have been previously acquired calling
1376 * iemNativeVarRegisterAcquire(), iemNativeVarRegisterAcquireForGuestReg() or
1377 * iemNativeVarRegisterSetAndAcquire().
1378 */
1379DECL_INLINE_THROW(void) iemNativeVarRegisterRelease(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar)
1380{
1381 IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVar);
1382 Assert(pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].fRegAcquired);
1383 pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].fRegAcquired = false;
1384}
1385
1386/** @} */
1387
1388#endif /* !VMM_INCLUDED_SRC_include_IEMN8veRecompiler_h */
1389
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