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source: vbox/trunk/src/VBox/VMM/include/IEMMc.h@ 99354

最後變更 在這個檔案從99354是 99354,由 vboxsync 提交於 2 年 前

VMM/IEM: Mojo improvments for IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT. bugref:10369
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1/* $Id: IEMMc.h 99354 2023-04-08 00:37:37Z vboxsync $ */
2/** @file
3 * IEM - Interpreted Execution Manager - IEM_MC_XXX.
4 */
5
6/*
7 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.alldomusa.eu.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_IEMMc_h
29#define VMM_INCLUDED_SRC_include_IEMMc_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34
35/** @name "Microcode" macros.
36 *
37 * The idea is that we should be able to use the same code to interpret
38 * instructions as well as recompiler instructions. Thus this obfuscation.
39 *
40 * @{
41 */
42#define IEM_MC_BEGIN(a_cArgs, a_cLocals) {
43#define IEM_MC_END() }
44
45/** Internal macro. */
46#define IEM_MC_RETURN_ON_FAILURE(a_Expr) \
47 do \
48 { \
49 VBOXSTRICTRC rcStrict2 = a_Expr; \
50 if (rcStrict2 != VINF_SUCCESS) \
51 return rcStrict2; \
52 } while (0)
53
54
55/** Advances RIP, finishes the instruction and returns.
56 * This may include raising debug exceptions and such. */
57#define IEM_MC_ADVANCE_RIP_AND_FINISH() return iemRegAddToRipAndFinishingClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
58/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
59#define IEM_MC_REL_JMP_S8_AND_FINISH(a_i8) \
60 return iemRegRipRelativeJumpS8AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i8), pVCpu->iem.s.enmEffOpSize)
61/** Sets RIP (may trigger \#GP), finishes the instruction and returns.
62 * @note only usable in 16-bit op size mode. */
63#define IEM_MC_REL_JMP_S16_AND_FINISH(a_i16) \
64 return iemRegRipRelativeJumpS16AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i16))
65/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
66#define IEM_MC_REL_JMP_S32_AND_FINISH(a_i32) \
67 return iemRegRipRelativeJumpS32AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i32), pVCpu->iem.s.enmEffOpSize)
68/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
69#define IEM_MC_SET_RIP_U16_AND_FINISH(a_u16NewIP) return iemRegRipJumpU16AndFinishClearningRF((pVCpu), (a_u16NewIP))
70/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
71#define IEM_MC_SET_RIP_U32_AND_FINISH(a_u32NewIP) return iemRegRipJumpU32AndFinishClearningRF((pVCpu), (a_u32NewIP))
72/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
73#define IEM_MC_SET_RIP_U64_AND_FINISH(a_u64NewIP) return iemRegRipJumpU64AndFinishClearningRF((pVCpu), (a_u64NewIP))
74
75#define IEM_MC_RAISE_DIVIDE_ERROR() return iemRaiseDivideError(pVCpu)
76#define IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() \
77 do { \
78 if (RT_LIKELY(!(pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS)))) \
79 { /* probable */ } \
80 else return iemRaiseDeviceNotAvailable(pVCpu); \
81 } while (0)
82#define IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() \
83 do { \
84 if (RT_LIKELY(!((pVCpu->cpum.GstCtx.cr0 & (X86_CR0_MP | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_TS)))) \
85 { /* probable */ } \
86 else return iemRaiseDeviceNotAvailable(pVCpu); \
87 } while (0)
88#define IEM_MC_MAYBE_RAISE_FPU_XCPT() \
89 do { \
90 if (RT_LIKELY(!(pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES))) \
91 { /* probable */ } \
92 else return iemRaiseMathFault(pVCpu); \
93 } while (0)
94#define IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() \
95 do { \
96 /* Since none of the bits we compare from XCR0, CR4 and CR0 overlap, it can \
97 be reduced to a single compare branch in the more probably code path. */ \
98 if (RT_LIKELY( ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) \
99 | (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE) \
100 | (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS)) \
101 == (XSAVE_C_YMM | XSAVE_C_SSE | X86_CR4_OSXSAVE))) \
102 { /* probable */ } \
103 else if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
104 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE)) \
105 return iemRaiseUndefinedOpcode(pVCpu); \
106 else \
107 return iemRaiseDeviceNotAvailable(pVCpu); \
108 } while (0)
109AssertCompile(!((XSAVE_C_YMM | XSAVE_C_SSE) & X86_CR4_OSXSAVE));
110AssertCompile(!((XSAVE_C_YMM | XSAVE_C_SSE) & X86_CR0_TS));
111AssertCompile(!(X86_CR4_OSXSAVE & X86_CR0_TS));
112#define IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() \
113 do { \
114 /* Since the CR4 and CR0 bits doesn't overlap, it can be reduced to a
115 single compare branch in the more probable code path. */ \
116 if (RT_LIKELY( ( (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS)) \
117 | (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \
118 == X86_CR4_OSFXSR)) \
119 { /* likely */ } \
120 else if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
121 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \
122 return iemRaiseUndefinedOpcode(pVCpu); \
123 else \
124 return iemRaiseDeviceNotAvailable(pVCpu); \
125 } while (0)
126AssertCompile(!((X86_CR0_EM | X86_CR0_TS) & X86_CR4_OSFXSR));
127#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT() \
128 do { \
129 /* Since the two CR0 bits doesn't overlap with FSW.ES, this can be reduced to a
130 single compare branch in the more probable code path. */ \
131 if (RT_LIKELY(!( (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS)) \
132 | (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES)))) \
133 { /* probable */ } \
134 else if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
135 return iemRaiseUndefinedOpcode(pVCpu); \
136 else if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
137 return iemRaiseDeviceNotAvailable(pVCpu); \
138 else \
139 return iemRaiseMathFault(pVCpu); \
140 } while (0)
141AssertCompile(!((X86_CR0_EM | X86_CR0_TS) & X86_FSW_ES));
142#define IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO() \
143 do { \
144 if (RT_LIKELY(pVCpu->iem.s.uCpl == 0)) { /* probable */ } \
145 else return iemRaiseGeneralProtectionFault0(pVCpu); \
146 } while (0)
147#define IEM_MC_RAISE_GP0_IF_EFF_ADDR_UNALIGNED(a_EffAddr, a_cbAlign) \
148 do { \
149 if (!((a_EffAddr) & ((a_cbAlign) - 1))) { /* likely */ } \
150 else return iemRaiseGeneralProtectionFault0(pVCpu); \
151 } while (0)
152#define IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT() \
153 do { \
154 if (RT_LIKELY( pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT \
155 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_FSGSBASE))) \
156 { /* probable */ } \
157 else return iemRaiseUndefinedOpcode(pVCpu); \
158 } while (0)
159#define IEM_MC_MAYBE_RAISE_NON_CANONICAL_ADDR_GP0(a_u64Addr) \
160 do { \
161 if (RT_LIKELY(IEM_IS_CANONICAL(a_u64Addr))) { /* likely */ } \
162 else return iemRaiseGeneralProtectionFault0(pVCpu); \
163 } while (0)
164#define IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
165 do { \
166 if (RT_LIKELY(( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
167 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) == 0)) \
168 { /* probable */ } \
169 else \
170 { \
171 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT) \
172 return iemRaiseSimdFpException(pVCpu); \
173 return iemRaiseUndefinedOpcode(pVCpu); \
174 } \
175 } while (0)
176#define IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
177 do { \
178 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT)\
179 return iemRaiseSimdFpException(pVCpu); \
180 return iemRaiseUndefinedOpcode(pVCpu); \
181 } while (0)
182
183
184#define IEM_MC_LOCAL(a_Type, a_Name) a_Type a_Name
185#define IEM_MC_LOCAL_CONST(a_Type, a_Name, a_Value) a_Type const a_Name = (a_Value)
186#define IEM_MC_REF_LOCAL(a_pRefArg, a_Local) (a_pRefArg) = &(a_Local)
187#define IEM_MC_ARG(a_Type, a_Name, a_iArg) a_Type a_Name
188#define IEM_MC_ARG_CONST(a_Type, a_Name, a_Value, a_iArg) a_Type const a_Name = (a_Value)
189#define IEM_MC_ARG_LOCAL_REF(a_Type, a_Name, a_Local, a_iArg) a_Type const a_Name = &(a_Local)
190#define IEM_MC_ARG_LOCAL_EFLAGS(a_pName, a_Name, a_iArg) \
191 uint32_t a_Name; \
192 uint32_t *a_pName = &a_Name
193#define IEM_MC_COMMIT_EFLAGS(a_EFlags) \
194 do { pVCpu->cpum.GstCtx.eflags.u = (a_EFlags); Assert(pVCpu->cpum.GstCtx.eflags.u & X86_EFL_1); } while (0)
195
196#define IEM_MC_ASSIGN(a_VarOrArg, a_CVariableOrConst) (a_VarOrArg) = (a_CVariableOrConst)
197#define IEM_MC_ASSIGN_TO_SMALLER IEM_MC_ASSIGN
198#define IEM_MC_ASSIGN_U8_SX_U64(a_u64VarOrArg, a_u8CVariableOrConst) \
199 (a_u64VarOrArg) = (int8_t)(a_u8CVariableOrConst)
200#define IEM_MC_ASSIGN_U32_SX_U64(a_u64VarOrArg, a_u32CVariableOrConst) \
201 (a_u64VarOrArg) = (int32_t)(a_u32CVariableOrConst)
202
203#define IEM_MC_FETCH_GREG_U8(a_u8Dst, a_iGReg) (a_u8Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
204#define IEM_MC_FETCH_GREG_U8_ZX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
205#define IEM_MC_FETCH_GREG_U8_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
206#define IEM_MC_FETCH_GREG_U8_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
207#define IEM_MC_FETCH_GREG_U8_SX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
208#define IEM_MC_FETCH_GREG_U8_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
209#define IEM_MC_FETCH_GREG_U8_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
210#define IEM_MC_FETCH_GREG_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
211#define IEM_MC_FETCH_GREG_U16_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
212#define IEM_MC_FETCH_GREG_U16_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
213#define IEM_MC_FETCH_GREG_U16_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
214#define IEM_MC_FETCH_GREG_U16_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
215#define IEM_MC_FETCH_GREG_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
216#define IEM_MC_FETCH_GREG_U32_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
217#define IEM_MC_FETCH_GREG_U32_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int32_t)iemGRegFetchU32(pVCpu, (a_iGReg))
218#define IEM_MC_FETCH_GREG_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU64(pVCpu, (a_iGReg))
219#define IEM_MC_FETCH_GREG_U64_ZX_U64 IEM_MC_FETCH_GREG_U64
220#define IEM_MC_FETCH_SREG_U16(a_u16Dst, a_iSReg) do { \
221 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
222 (a_u16Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
223 } while (0)
224#define IEM_MC_FETCH_SREG_ZX_U32(a_u32Dst, a_iSReg) do { \
225 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
226 (a_u32Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
227 } while (0)
228#define IEM_MC_FETCH_SREG_ZX_U64(a_u64Dst, a_iSReg) do { \
229 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
230 (a_u64Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
231 } while (0)
232/** @todo IEM_MC_FETCH_SREG_BASE_U64 & IEM_MC_FETCH_SREG_BASE_U32 probably aren't worth it... */
233#define IEM_MC_FETCH_SREG_BASE_U64(a_u64Dst, a_iSReg) do { \
234 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
235 (a_u64Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
236 } while (0)
237#define IEM_MC_FETCH_SREG_BASE_U32(a_u32Dst, a_iSReg) do { \
238 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
239 (a_u32Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
240 } while (0)
241/** @note Not for IOPL or IF testing or modification. */
242#define IEM_MC_FETCH_EFLAGS(a_EFlags) (a_EFlags) = pVCpu->cpum.GstCtx.eflags.u
243#define IEM_MC_FETCH_EFLAGS_U8(a_EFlags) (a_EFlags) = (uint8_t)pVCpu->cpum.GstCtx.eflags.u
244#define IEM_MC_FETCH_FSW(a_u16Fsw) (a_u16Fsw) = pVCpu->cpum.GstCtx.XState.x87.FSW
245#define IEM_MC_FETCH_FCW(a_u16Fcw) (a_u16Fcw) = pVCpu->cpum.GstCtx.XState.x87.FCW
246
247#define IEM_MC_STORE_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) = (a_u8Value)
248#define IEM_MC_STORE_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) = (a_u16Value)
249#define IEM_MC_STORE_GREG_U32(a_iGReg, a_u32Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (uint32_t)(a_u32Value) /* clear high bits. */
250#define IEM_MC_STORE_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (a_u64Value)
251#define IEM_MC_STORE_GREG_I64(a_iGReg, a_i64Value) *iemGRegRefI64(pVCpu, (a_iGReg)) = (a_i64Value)
252#define IEM_MC_STORE_GREG_U8_CONST IEM_MC_STORE_GREG_U8
253#define IEM_MC_STORE_GREG_U16_CONST IEM_MC_STORE_GREG_U16
254#define IEM_MC_STORE_GREG_U32_CONST IEM_MC_STORE_GREG_U32
255#define IEM_MC_STORE_GREG_U64_CONST IEM_MC_STORE_GREG_U64
256#define IEM_MC_CLEAR_HIGH_GREG_U64(a_iGReg) *iemGRegRefU64(pVCpu, (a_iGReg)) &= UINT32_MAX
257#define IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(a_pu32Dst) do { (a_pu32Dst)[1] = 0; } while (0)
258/** @todo IEM_MC_STORE_SREG_BASE_U64 & IEM_MC_STORE_SREG_BASE_U32 aren't worth it... */
259#define IEM_MC_STORE_SREG_BASE_U64(a_iSReg, a_u64Value) do { \
260 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
261 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (a_u64Value); \
262 } while (0)
263#define IEM_MC_STORE_SREG_BASE_U32(a_iSReg, a_u32Value) do { \
264 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
265 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (uint32_t)(a_u32Value); /* clear high bits. */ \
266 } while (0)
267#define IEM_MC_STORE_FPUREG_R80_SRC_REF(a_iSt, a_pr80Src) \
268 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[a_iSt].r80 = *(a_pr80Src); } while (0)
269
270
271#define IEM_MC_REF_GREG_U8(a_pu8Dst, a_iGReg) (a_pu8Dst) = iemGRegRefU8( pVCpu, (a_iGReg))
272#define IEM_MC_REF_GREG_U16(a_pu16Dst, a_iGReg) (a_pu16Dst) = iemGRegRefU16(pVCpu, (a_iGReg))
273/** @todo User of IEM_MC_REF_GREG_U32 needs to clear the high bits on commit.
274 * Use IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF! */
275#define IEM_MC_REF_GREG_U32(a_pu32Dst, a_iGReg) (a_pu32Dst) = iemGRegRefU32(pVCpu, (a_iGReg))
276#define IEM_MC_REF_GREG_I32(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t *)iemGRegRefU32(pVCpu, (a_iGReg))
277#define IEM_MC_REF_GREG_I32_CONST(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t const *)iemGRegRefU32(pVCpu, (a_iGReg))
278#define IEM_MC_REF_GREG_U64(a_pu64Dst, a_iGReg) (a_pu64Dst) = iemGRegRefU64(pVCpu, (a_iGReg))
279#define IEM_MC_REF_GREG_I64(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t *)iemGRegRefU64(pVCpu, (a_iGReg))
280#define IEM_MC_REF_GREG_I64_CONST(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t const *)iemGRegRefU64(pVCpu, (a_iGReg))
281/** @note Not for IOPL or IF testing or modification.
282 * @note Must preserve any undefined bits, see CPUMX86EFLAGS! */
283#define IEM_MC_REF_EFLAGS(a_pEFlags) (a_pEFlags) = &pVCpu->cpum.GstCtx.eflags.uBoth
284#define IEM_MC_REF_MXCSR(a_pfMxcsr) (a_pfMxcsr) = &pVCpu->cpum.GstCtx.XState.x87.MXCSR
285
286#define IEM_MC_ADD_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) += (a_u8Value)
287#define IEM_MC_ADD_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) += (a_u16Value)
288#define IEM_MC_ADD_GREG_U32(a_iGReg, a_u32Value) \
289 do { \
290 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
291 *pu32Reg += (a_u32Value); \
292 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
293 } while (0)
294#define IEM_MC_ADD_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) += (a_u64Value)
295
296#define IEM_MC_SUB_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) -= (a_u8Value)
297#define IEM_MC_SUB_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) -= (a_u16Value)
298#define IEM_MC_SUB_GREG_U32(a_iGReg, a_u32Value) \
299 do { \
300 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
301 *pu32Reg -= (a_u32Value); \
302 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
303 } while (0)
304#define IEM_MC_SUB_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) -= (a_u64Value)
305#define IEM_MC_SUB_LOCAL_U16(a_u16Value, a_u16Const) do { (a_u16Value) -= a_u16Const; } while (0)
306
307#define IEM_MC_ADD_GREG_U8_TO_LOCAL(a_u8Value, a_iGReg) do { (a_u8Value) += iemGRegFetchU8( pVCpu, (a_iGReg)); } while (0)
308#define IEM_MC_ADD_GREG_U16_TO_LOCAL(a_u16Value, a_iGReg) do { (a_u16Value) += iemGRegFetchU16(pVCpu, (a_iGReg)); } while (0)
309#define IEM_MC_ADD_GREG_U32_TO_LOCAL(a_u32Value, a_iGReg) do { (a_u32Value) += iemGRegFetchU32(pVCpu, (a_iGReg)); } while (0)
310#define IEM_MC_ADD_GREG_U64_TO_LOCAL(a_u64Value, a_iGReg) do { (a_u64Value) += iemGRegFetchU64(pVCpu, (a_iGReg)); } while (0)
311#define IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR(a_EffAddr, a_i16) do { (a_EffAddr) += (a_i16); } while (0)
312#define IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR(a_EffAddr, a_i32) do { (a_EffAddr) += (a_i32); } while (0)
313#define IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR(a_EffAddr, a_i64) do { (a_EffAddr) += (a_i64); } while (0)
314
315#define IEM_MC_AND_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) &= (a_u8Mask); } while (0)
316#define IEM_MC_AND_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) &= (a_u16Mask); } while (0)
317#define IEM_MC_AND_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
318#define IEM_MC_AND_LOCAL_U64(a_u64Local, a_u64Mask) do { (a_u64Local) &= (a_u64Mask); } while (0)
319
320#define IEM_MC_AND_ARG_U16(a_u16Arg, a_u16Mask) do { (a_u16Arg) &= (a_u16Mask); } while (0)
321#define IEM_MC_AND_ARG_U32(a_u32Arg, a_u32Mask) do { (a_u32Arg) &= (a_u32Mask); } while (0)
322#define IEM_MC_AND_ARG_U64(a_u64Arg, a_u64Mask) do { (a_u64Arg) &= (a_u64Mask); } while (0)
323
324#define IEM_MC_OR_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) |= (a_u8Mask); } while (0)
325#define IEM_MC_OR_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) |= (a_u16Mask); } while (0)
326#define IEM_MC_OR_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
327
328#define IEM_MC_SAR_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) >>= (a_cShift); } while (0)
329#define IEM_MC_SAR_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) >>= (a_cShift); } while (0)
330#define IEM_MC_SAR_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) >>= (a_cShift); } while (0)
331
332#define IEM_MC_SHR_LOCAL_U8(a_u8Local, a_cShift) do { (a_u8Local) >>= (a_cShift); } while (0)
333
334#define IEM_MC_SHL_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) <<= (a_cShift); } while (0)
335#define IEM_MC_SHL_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) <<= (a_cShift); } while (0)
336#define IEM_MC_SHL_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) <<= (a_cShift); } while (0)
337
338#define IEM_MC_AND_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
339
340#define IEM_MC_OR_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
341
342#define IEM_MC_AND_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) &= (a_u8Value)
343#define IEM_MC_AND_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) &= (a_u16Value)
344#define IEM_MC_AND_GREG_U32(a_iGReg, a_u32Value) \
345 do { \
346 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
347 *pu32Reg &= (a_u32Value); \
348 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
349 } while (0)
350#define IEM_MC_AND_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) &= (a_u64Value)
351
352#define IEM_MC_OR_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) |= (a_u8Value)
353#define IEM_MC_OR_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) |= (a_u16Value)
354#define IEM_MC_OR_GREG_U32(a_iGReg, a_u32Value) \
355 do { \
356 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
357 *pu32Reg |= (a_u32Value); \
358 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
359 } while (0)
360#define IEM_MC_OR_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) |= (a_u64Value)
361
362#define IEM_MC_BSWAP_LOCAL_U16(a_u16Local) (a_u16Local) = RT_BSWAP_U16((a_u16Local));
363#define IEM_MC_BSWAP_LOCAL_U32(a_u32Local) (a_u32Local) = RT_BSWAP_U32((a_u32Local));
364#define IEM_MC_BSWAP_LOCAL_U64(a_u64Local) (a_u64Local) = RT_BSWAP_U64((a_u64Local));
365
366/** @note Not for IOPL or IF modification. */
367#define IEM_MC_SET_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u |= (a_fBit); } while (0)
368/** @note Not for IOPL or IF modification. */
369#define IEM_MC_CLEAR_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u &= ~(a_fBit); } while (0)
370/** @note Not for IOPL or IF modification. */
371#define IEM_MC_FLIP_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u ^= (a_fBit); } while (0)
372
373#define IEM_MC_CLEAR_FSW_EX() do { pVCpu->cpum.GstCtx.XState.x87.FSW &= X86_FSW_C_MASK | X86_FSW_TOP_MASK; } while (0)
374
375/** Switches the FPU state to MMX mode (FSW.TOS=0, FTW=0) if necessary. */
376#define IEM_MC_FPU_TO_MMX_MODE() do { \
377 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
378 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
379 pVCpu->cpum.GstCtx.XState.x87.FTW = 0xff; \
380 } while (0)
381
382/** Switches the FPU state from MMX mode (FSW.TOS=0, FTW=0xffff). */
383#define IEM_MC_FPU_FROM_MMX_MODE() do { \
384 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
385 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
386 pVCpu->cpum.GstCtx.XState.x87.FTW = 0; \
387 } while (0)
388
389#define IEM_MC_FETCH_MREG_U64(a_u64Value, a_iMReg) \
390 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx; } while (0)
391#define IEM_MC_FETCH_MREG_U32(a_u32Value, a_iMReg) \
392 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[0]; } while (0)
393#define IEM_MC_STORE_MREG_U64(a_iMReg, a_u64Value) do { \
394 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (a_u64Value); \
395 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
396 } while (0)
397#define IEM_MC_STORE_MREG_U32_ZX_U64(a_iMReg, a_u32Value) do { \
398 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (uint32_t)(a_u32Value); \
399 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
400 } while (0)
401#define IEM_MC_REF_MREG_U64(a_pu64Dst, a_iMReg) /** @todo need to set high word to 0xffff on commit (see IEM_MC_STORE_MREG_U64) */ \
402 (a_pu64Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
403#define IEM_MC_REF_MREG_U64_CONST(a_pu64Dst, a_iMReg) \
404 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
405#define IEM_MC_REF_MREG_U32_CONST(a_pu32Dst, a_iMReg) \
406 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
407#define IEM_MC_MODIFIED_MREG(a_iMReg) \
408 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; } while (0)
409#define IEM_MC_MODIFIED_MREG_BY_REF(a_pu64Dst) \
410 do { ((uint32_t *)(a_pu64Dst))[2] = 0xffff; } while (0)
411
412#define IEM_MC_CLEAR_XREG_U32_MASK(a_iXReg, a_bMask) \
413 do { if ((a_bMask) & (1 << 0)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0] = 0; \
414 if ((a_bMask) & (1 << 1)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[1] = 0; \
415 if ((a_bMask) & (1 << 2)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[2] = 0; \
416 if ((a_bMask) & (1 << 3)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[3] = 0; \
417 } while (0)
418#define IEM_MC_FETCH_XREG_U128(a_u128Value, a_iXReg) \
419 do { (a_u128Value).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
420 (a_u128Value).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
421 } while (0)
422#define IEM_MC_FETCH_XREG_XMM(a_XmmValue, a_iXReg) \
423 do { (a_XmmValue).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
424 (a_XmmValue).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
425 } while (0)
426#define IEM_MC_FETCH_XREG_U64(a_u64Value, a_iXReg, a_iQWord) \
427 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQWord)]; } while (0)
428#define IEM_MC_FETCH_XREG_U32(a_u32Value, a_iXReg, a_iDWord) \
429 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDWord)]; } while (0)
430#define IEM_MC_FETCH_XREG_U16(a_u16Value, a_iXReg, a_iWord) \
431 do { (a_u16Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au16[(a_iWord)]; } while (0)
432#define IEM_MC_FETCH_XREG_U8( a_u8Value, a_iXReg, a_iByte) \
433 do { (a_u8Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au16[(a_iByte)]; } while (0)
434#define IEM_MC_STORE_XREG_U128(a_iXReg, a_u128Value) \
435 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u128Value).au64[0]; \
436 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u128Value).au64[1]; \
437 } while (0)
438#define IEM_MC_STORE_XREG_XMM(a_iXReg, a_XmmValue) \
439 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_XmmValue).au64[0]; \
440 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_XmmValue).au64[1]; \
441 } while (0)
442#define IEM_MC_STORE_XREG_XMM_U32(a_iXReg, a_iDword, a_XmmValue) \
443 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDword)] = (a_XmmValue).au32[(a_iDword)]; } while (0)
444#define IEM_MC_STORE_XREG_XMM_U64(a_iXReg, a_iQword, a_XmmValue) \
445 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQword)] = (a_XmmValue).au64[(a_iQword)]; } while (0)
446#define IEM_MC_STORE_XREG_U64(a_iXReg, a_iQword, a_u64Value) \
447 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQword)] = (a_u64Value); } while (0)
448#define IEM_MC_STORE_XREG_U32(a_iXReg, a_iDword, a_u32Value) \
449 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDword)] = (a_u32Value); } while (0)
450#define IEM_MC_STORE_XREG_U16(a_iXReg, a_iWord, a_u16Value) \
451 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iWord)] = (a_u16Value); } while (0)
452#define IEM_MC_STORE_XREG_U8(a_iXReg, a_iByte, a_u8Value) \
453 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iByte)] = (a_u8Value); } while (0)
454
455#define IEM_MC_STORE_XREG_U64_ZX_U128(a_iXReg, a_u64Value) \
456 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u64Value); \
457 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
458 } while (0)
459
460#define IEM_MC_STORE_XREG_U32_U128(a_iXReg, a_iDwDst, a_u128Value, a_iDwSrc) \
461 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDwDst)] = (a_u128Value).au32[(a_iDwSrc)]; } while (0)
462#define IEM_MC_STORE_XREG_R32(a_iXReg, a_r32Value) \
463 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0] = (a_r32Value); } while (0)
464#define IEM_MC_STORE_XREG_R64(a_iXReg, a_r64Value) \
465 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0] = (a_r64Value); } while (0)
466#define IEM_MC_STORE_XREG_U32_ZX_U128(a_iXReg, a_u32Value) \
467 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (uint32_t)(a_u32Value); \
468 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
469 } while (0)
470#define IEM_MC_STORE_XREG_HI_U64(a_iXReg, a_u64Value) \
471 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u64Value); } while (0)
472#define IEM_MC_REF_XREG_U128(a_pu128Dst, a_iXReg) \
473 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
474#define IEM_MC_REF_XREG_U128_CONST(a_pu128Dst, a_iXReg) \
475 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
476#define IEM_MC_REF_XREG_XMM_CONST(a_pXmmDst, a_iXReg) \
477 (a_pXmmDst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)])
478#define IEM_MC_REF_XREG_U32_CONST(a_pu32Dst, a_iXReg) \
479 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0])
480#define IEM_MC_REF_XREG_U64_CONST(a_pu64Dst, a_iXReg) \
481 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0])
482#define IEM_MC_REF_XREG_R32_CONST(a_pr32Dst, a_iXReg) \
483 (a_pr32Dst) = ((RTFLOAT32U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0])
484#define IEM_MC_REF_XREG_R64_CONST(a_pr64Dst, a_iXReg) \
485 (a_pr64Dst) = ((RTFLOAT64U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0])
486#define IEM_MC_COPY_XREG_U128(a_iXRegDst, a_iXRegSrc) \
487 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[0] \
488 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[0]; \
489 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[1] \
490 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[1]; \
491 } while (0)
492
493#define IEM_MC_FETCH_YREG_U32(a_u32Dst, a_iYRegSrc) \
494 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
495 (a_u32Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au32[0]; \
496 } while (0)
497#define IEM_MC_FETCH_YREG_U64(a_u64Dst, a_iYRegSrc) \
498 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
499 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
500 } while (0)
501#define IEM_MC_FETCH_YREG_2ND_U64(a_u64Dst, a_iYRegSrc) \
502 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
503 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
504 } while (0)
505#define IEM_MC_FETCH_YREG_U128(a_u128Dst, a_iYRegSrc) \
506 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
507 (a_u128Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
508 (a_u128Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
509 } while (0)
510#define IEM_MC_FETCH_YREG_U256(a_u256Dst, a_iYRegSrc) \
511 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
512 (a_u256Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
513 (a_u256Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
514 (a_u256Dst).au64[2] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
515 (a_u256Dst).au64[3] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
516 } while (0)
517
518#define IEM_MC_INT_CLEAR_ZMM_256_UP(a_iXRegDst) do { /* For AVX512 and AVX1024 support. */ } while (0)
519#define IEM_MC_STORE_YREG_U32_ZX_VLMAX(a_iYRegDst, a_u32Src) \
520 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
521 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = (a_u32Src); \
522 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = 0; \
523 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
524 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
525 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
526 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
527 } while (0)
528#define IEM_MC_STORE_YREG_U64_ZX_VLMAX(a_iYRegDst, a_u64Src) \
529 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
530 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Src); \
531 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
532 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
533 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
534 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
535 } while (0)
536#define IEM_MC_STORE_YREG_U128_ZX_VLMAX(a_iYRegDst, a_u128Src) \
537 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
538 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u128Src).au64[0]; \
539 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u128Src).au64[1]; \
540 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
541 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
542 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
543 } while (0)
544#define IEM_MC_STORE_YREG_U256_ZX_VLMAX(a_iYRegDst, a_u256Src) \
545 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
546 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u256Src).au64[0]; \
547 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u256Src).au64[1]; \
548 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = (a_u256Src).au64[2]; \
549 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = (a_u256Src).au64[3]; \
550 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
551 } while (0)
552
553#define IEM_MC_REF_YREG_U128(a_pu128Dst, a_iYReg) \
554 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
555#define IEM_MC_REF_YREG_U128_CONST(a_pu128Dst, a_iYReg) \
556 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
557#define IEM_MC_REF_YREG_U64_CONST(a_pu64Dst, a_iYReg) \
558 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].au64[0])
559#define IEM_MC_CLEAR_YREG_128_UP(a_iYReg) \
560 do { uintptr_t const iYRegTmp = (a_iYReg); \
561 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[0] = 0; \
562 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[1] = 0; \
563 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegTmp); \
564 } while (0)
565
566#define IEM_MC_COPY_YREG_U256_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
567 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
568 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
569 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
570 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
571 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
572 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
573 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
574 } while (0)
575#define IEM_MC_COPY_YREG_U128_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
576 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
577 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
578 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
579 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
580 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
581 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
582 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
583 } while (0)
584#define IEM_MC_COPY_YREG_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
585 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
586 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
587 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
588 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
589 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
590 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
591 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
592 } while (0)
593
594#define IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(a_iYRegDst, a_iYRegSrc32, a_iYRegSrcHx) \
595 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
596 uintptr_t const iYRegSrc32Tmp = (a_iYRegSrc32); \
597 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
598 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc32Tmp].au32[0]; \
599 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au32[1]; \
600 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
601 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
602 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
603 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
604 } while (0)
605#define IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) \
606 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
607 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
608 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
609 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
610 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
611 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
612 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
613 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
614 } while (0)
615#define IEM_MC_MERGE_YREG_U64LO_U64LO_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
616 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
617 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
618 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
619 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
620 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
621 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
622 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
623 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
624 } while (0)
625#define IEM_MC_MERGE_YREG_U64HI_U64HI_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
626 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
627 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
628 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
629 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[1]; \
630 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
631 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
632 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
633 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
634 } while (0)
635#define IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX(a_iYRegDst, a_iYRegSrcHx, a_u64Local) \
636 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
637 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
638 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
639 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u64Local); \
640 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
641 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
642 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
643 } while (0)
644#define IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX(a_iYRegDst, a_u64Local, a_iYRegSrcHx) \
645 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
646 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
647 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Local); \
648 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
649 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
650 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
651 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
652 } while (0)
653
654#ifndef IEM_WITH_SETJMP
655# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
656 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem)))
657# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
658 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem16)))
659# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
660 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem32)))
661#else
662# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
663 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
664# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
665 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem16)))
666# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
667 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem32)))
668#endif
669
670#ifndef IEM_WITH_SETJMP
671# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
672 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem)))
673# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
674 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
675# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
676 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, (uint16_t *)&(a_i16Dst), (a_iSeg), (a_GCPtrMem)))
677#else
678# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
679 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
680# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
681 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
682# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
683 ((a_i16Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
684#endif
685
686#ifndef IEM_WITH_SETJMP
687# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
688 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem)))
689# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
690 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
691# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
692 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, (uint32_t *)&(a_i32Dst), (a_iSeg), (a_GCPtrMem)))
693#else
694# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
695 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
696# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
697 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
698# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
699 ((a_i32Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
700#endif
701
702#ifdef SOME_UNUSED_FUNCTION
703# define IEM_MC_FETCH_MEM_S32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
704 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataS32SxU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
705#endif
706
707#ifndef IEM_WITH_SETJMP
708# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
709 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
710# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
711 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
712# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
713 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64AlignedU128(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
714# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
715 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, (uint64_t *)&(a_i64Dst), (a_iSeg), (a_GCPtrMem)))
716#else
717# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
718 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
719# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
720 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
721# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
722 ((a_u64Dst) = iemMemFetchDataU64AlignedU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
723# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
724 ((a_i64Dst) = (int64_t)iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
725#endif
726
727#ifndef IEM_WITH_SETJMP
728# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
729 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_r32Dst).u, (a_iSeg), (a_GCPtrMem)))
730# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
731 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_r64Dst).u, (a_iSeg), (a_GCPtrMem)))
732# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
733 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataR80(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem)))
734# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
735 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataD80(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem)))
736#else
737# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
738 ((a_r32Dst).u = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
739# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
740 ((a_r64Dst).u = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
741# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
742 iemMemFetchDataR80Jmp(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem))
743# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
744 iemMemFetchDataD80Jmp(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem))
745#endif
746
747#ifndef IEM_WITH_SETJMP
748# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
749 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
750# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
751 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
752# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
753 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
754
755# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
756 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
757# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
758 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
759# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
760 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
761# define IEM_MC_FETCH_MEM_XMM_U32(a_XmmDst, a_iDWord, a_iSeg, a_GCPtrMem) \
762 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_XmmDst).au32[(a_iDWord)], (a_iSeg), (a_GCPtrMem)))
763# define IEM_MC_FETCH_MEM_XMM_U64(a_XmmDst, a_iQWord, a_iSeg, a_GCPtrMem) \
764 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_XmmDst).au64[(a_iQWord)], (a_iSeg), (a_GCPtrMem)))
765#else
766# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
767 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
768# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
769 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
770# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
771 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
772
773# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
774 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
775# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
776 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
777# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
778 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
779# define IEM_MC_FETCH_MEM_XMM_U32(a_XmmDst, a_iDWord, a_iSeg, a_GCPtrMem) \
780 (a_XmmDst).au32[(a_iDWord)] = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem))
781# define IEM_MC_FETCH_MEM_XMM_U64(a_XmmDst, a_iQWord, a_iSeg, a_GCPtrMem) \
782 (a_XmmDst).au64[(a_iQWord)] = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem))
783#endif
784
785#ifndef IEM_WITH_SETJMP
786# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
787 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
788# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
789 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
790# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
791 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
792
793# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
794 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
795# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
796 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
797# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
798 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
799#else
800# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
801 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
802# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
803 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
804# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
805 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
806
807# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
808 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
809# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
810 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
811# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
812 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
813#endif
814
815
816
817#ifndef IEM_WITH_SETJMP
818# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
819 do { \
820 uint8_t u8Tmp; \
821 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
822 (a_u16Dst) = u8Tmp; \
823 } while (0)
824# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
825 do { \
826 uint8_t u8Tmp; \
827 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
828 (a_u32Dst) = u8Tmp; \
829 } while (0)
830# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
831 do { \
832 uint8_t u8Tmp; \
833 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
834 (a_u64Dst) = u8Tmp; \
835 } while (0)
836# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
837 do { \
838 uint16_t u16Tmp; \
839 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
840 (a_u32Dst) = u16Tmp; \
841 } while (0)
842# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
843 do { \
844 uint16_t u16Tmp; \
845 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
846 (a_u64Dst) = u16Tmp; \
847 } while (0)
848# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
849 do { \
850 uint32_t u32Tmp; \
851 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
852 (a_u64Dst) = u32Tmp; \
853 } while (0)
854#else /* IEM_WITH_SETJMP */
855# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
856 ((a_u16Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
857# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
858 ((a_u32Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
859# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
860 ((a_u64Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
861# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
862 ((a_u32Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
863# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
864 ((a_u64Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
865# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
866 ((a_u64Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
867#endif /* IEM_WITH_SETJMP */
868
869#ifndef IEM_WITH_SETJMP
870# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
871 do { \
872 uint8_t u8Tmp; \
873 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
874 (a_u16Dst) = (int8_t)u8Tmp; \
875 } while (0)
876# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
877 do { \
878 uint8_t u8Tmp; \
879 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
880 (a_u32Dst) = (int8_t)u8Tmp; \
881 } while (0)
882# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
883 do { \
884 uint8_t u8Tmp; \
885 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
886 (a_u64Dst) = (int8_t)u8Tmp; \
887 } while (0)
888# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
889 do { \
890 uint16_t u16Tmp; \
891 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
892 (a_u32Dst) = (int16_t)u16Tmp; \
893 } while (0)
894# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
895 do { \
896 uint16_t u16Tmp; \
897 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
898 (a_u64Dst) = (int16_t)u16Tmp; \
899 } while (0)
900# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
901 do { \
902 uint32_t u32Tmp; \
903 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
904 (a_u64Dst) = (int32_t)u32Tmp; \
905 } while (0)
906#else /* IEM_WITH_SETJMP */
907# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
908 ((a_u16Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
909# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
910 ((a_u32Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
911# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
912 ((a_u64Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
913# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
914 ((a_u32Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
915# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
916 ((a_u64Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
917# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
918 ((a_u64Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
919#endif /* IEM_WITH_SETJMP */
920
921#ifndef IEM_WITH_SETJMP
922# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
923 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value)))
924# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
925 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value)))
926# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
927 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value)))
928# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
929 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value)))
930#else
931# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
932 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value))
933# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
934 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value))
935# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
936 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value))
937# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
938 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value))
939#endif
940
941#ifndef IEM_WITH_SETJMP
942# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
943 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C)))
944# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
945 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C)))
946# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
947 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C)))
948# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
949 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C)))
950#else
951# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
952 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C))
953# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
954 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C))
955# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
956 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C))
957# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
958 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C))
959#endif
960
961#define IEM_MC_STORE_MEM_I8_CONST_BY_REF( a_pi8Dst, a_i8C) *(a_pi8Dst) = (a_i8C)
962#define IEM_MC_STORE_MEM_I16_CONST_BY_REF(a_pi16Dst, a_i16C) *(a_pi16Dst) = (a_i16C)
963#define IEM_MC_STORE_MEM_I32_CONST_BY_REF(a_pi32Dst, a_i32C) *(a_pi32Dst) = (a_i32C)
964#define IEM_MC_STORE_MEM_I64_CONST_BY_REF(a_pi64Dst, a_i64C) *(a_pi64Dst) = (a_i64C)
965#define IEM_MC_STORE_MEM_NEG_QNAN_R32_BY_REF(a_pr32Dst) (a_pr32Dst)->u = UINT32_C(0xffc00000)
966#define IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF(a_pr64Dst) (a_pr64Dst)->u = UINT64_C(0xfff8000000000000)
967#define IEM_MC_STORE_MEM_NEG_QNAN_R80_BY_REF(a_pr80Dst) \
968 do { \
969 (a_pr80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
970 (a_pr80Dst)->au16[4] = UINT16_C(0xffff); \
971 } while (0)
972#define IEM_MC_STORE_MEM_INDEF_D80_BY_REF(a_pd80Dst) \
973 do { \
974 (a_pd80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
975 (a_pd80Dst)->au16[4] = UINT16_C(0xffff); \
976 } while (0)
977
978#ifndef IEM_WITH_SETJMP
979# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
980 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
981# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
982 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128AlignedSse(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
983#else
984# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
985 iemMemStoreDataU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
986# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
987 iemMemStoreDataU128AlignedSseJmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
988#endif
989
990#ifndef IEM_WITH_SETJMP
991# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
992 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
993# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
994 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256AlignedAvx(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
995#else
996# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
997 iemMemStoreDataU256Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
998# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
999 iemMemStoreDataU256AlignedAvxJmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
1000#endif
1001
1002
1003#define IEM_MC_PUSH_U16(a_u16Value) \
1004 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU16(pVCpu, (a_u16Value)))
1005#define IEM_MC_PUSH_U32(a_u32Value) \
1006 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32(pVCpu, (a_u32Value)))
1007#define IEM_MC_PUSH_U32_SREG(a_u32Value) \
1008 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32SReg(pVCpu, (a_u32Value)))
1009#define IEM_MC_PUSH_U64(a_u64Value) \
1010 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU64(pVCpu, (a_u64Value)))
1011
1012#define IEM_MC_POP_U16(a_pu16Value) \
1013 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU16(pVCpu, (a_pu16Value)))
1014#define IEM_MC_POP_U32(a_pu32Value) \
1015 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU32(pVCpu, (a_pu32Value)))
1016#define IEM_MC_POP_U64(a_pu64Value) \
1017 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU64(pVCpu, (a_pu64Value)))
1018
1019/** Maps guest memory for direct or bounce buffered access.
1020 * The purpose is to pass it to an operand implementation, thus the a_iArg.
1021 * @remarks May return.
1022 */
1023#define IEM_MC_MEM_MAP(a_pMem, a_fAccess, a_iSeg, a_GCPtrMem, a_iArg) \
1024 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pMem), sizeof(*(a_pMem)), (a_iSeg), \
1025 (a_GCPtrMem), (a_fAccess), sizeof(*(a_pMem)) - 1))
1026
1027/** Maps guest memory for direct or bounce buffered access.
1028 * The purpose is to pass it to an operand implementation, thus the a_iArg.
1029 * @remarks May return.
1030 */
1031#define IEM_MC_MEM_MAP_EX(a_pvMem, a_fAccess, a_cbMem, a_iSeg, a_GCPtrMem, a_cbAlign, a_iArg) \
1032 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pvMem), (a_cbMem), (a_iSeg), \
1033 (a_GCPtrMem), (a_fAccess), (a_cbAlign)))
1034
1035/** Commits the memory and unmaps the guest memory.
1036 * @remarks May return.
1037 */
1038#define IEM_MC_MEM_COMMIT_AND_UNMAP(a_pvMem, a_fAccess) \
1039 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess)))
1040
1041/** Commits the memory and unmaps the guest memory unless the FPU status word
1042 * indicates (@a a_u16FSW) and FPU control word indicates a pending exception
1043 * that would cause FLD not to store.
1044 *
1045 * The current understanding is that \#O, \#U, \#IA and \#IS will prevent a
1046 * store, while \#P will not.
1047 *
1048 * @remarks May in theory return - for now.
1049 */
1050#define IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(a_pvMem, a_fAccess, a_u16FSW) \
1051 do { \
1052 if ( !(a_u16FSW & X86_FSW_ES) \
1053 || !( (a_u16FSW & (X86_FSW_UE | X86_FSW_OE | X86_FSW_IE)) \
1054 & ~(pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_MASK_ALL) ) ) \
1055 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess))); \
1056 } while (0)
1057
1058/** Calculate efficient address from R/M. */
1059#ifndef IEM_WITH_SETJMP
1060# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
1061 IEM_MC_RETURN_ON_FAILURE(iemOpHlpCalcRmEffAddr(pVCpu, (bRm), (cbImm), &(a_GCPtrEff)))
1062#else
1063# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
1064 ((a_GCPtrEff) = iemOpHlpCalcRmEffAddrJmp(pVCpu, (bRm), (cbImm)))
1065#endif
1066
1067#define IEM_MC_CALL_VOID_AIMPL_0(a_pfn) (a_pfn)()
1068#define IEM_MC_CALL_VOID_AIMPL_1(a_pfn, a0) (a_pfn)((a0))
1069#define IEM_MC_CALL_VOID_AIMPL_2(a_pfn, a0, a1) (a_pfn)((a0), (a1))
1070#define IEM_MC_CALL_VOID_AIMPL_3(a_pfn, a0, a1, a2) (a_pfn)((a0), (a1), (a2))
1071#define IEM_MC_CALL_VOID_AIMPL_4(a_pfn, a0, a1, a2, a3) (a_pfn)((a0), (a1), (a2), (a3))
1072#define IEM_MC_CALL_AIMPL_3(a_rc, a_pfn, a0, a1, a2) (a_rc) = (a_pfn)((a0), (a1), (a2))
1073#define IEM_MC_CALL_AIMPL_4(a_rc, a_pfn, a0, a1, a2, a3) (a_rc) = (a_pfn)((a0), (a1), (a2), (a3))
1074
1075/**
1076 * Defers the rest of the instruction emulation to a C implementation routine
1077 * and returns, only taking the standard parameters.
1078 *
1079 * @param a_pfnCImpl The pointer to the C routine.
1080 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
1081 */
1082#define IEM_MC_CALL_CIMPL_0(a_pfnCImpl) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
1083
1084/**
1085 * Defers the rest of instruction emulation to a C implementation routine and
1086 * returns, taking one argument in addition to the standard ones.
1087 *
1088 * @param a_pfnCImpl The pointer to the C routine.
1089 * @param a0 The argument.
1090 */
1091#define IEM_MC_CALL_CIMPL_1(a_pfnCImpl, a0) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
1092
1093/**
1094 * Defers the rest of the instruction emulation to a C implementation routine
1095 * and returns, taking two arguments in addition to the standard ones.
1096 *
1097 * @param a_pfnCImpl The pointer to the C routine.
1098 * @param a0 The first extra argument.
1099 * @param a1 The second extra argument.
1100 */
1101#define IEM_MC_CALL_CIMPL_2(a_pfnCImpl, a0, a1) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
1102
1103/**
1104 * Defers the rest of the instruction emulation to a C implementation routine
1105 * and returns, taking three arguments in addition to the standard ones.
1106 *
1107 * @param a_pfnCImpl The pointer to the C routine.
1108 * @param a0 The first extra argument.
1109 * @param a1 The second extra argument.
1110 * @param a2 The third extra argument.
1111 */
1112#define IEM_MC_CALL_CIMPL_3(a_pfnCImpl, a0, a1, a2) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1113
1114/**
1115 * Defers the rest of the instruction emulation to a C implementation routine
1116 * and returns, taking four arguments in addition to the standard ones.
1117 *
1118 * @param a_pfnCImpl The pointer to the C routine.
1119 * @param a0 The first extra argument.
1120 * @param a1 The second extra argument.
1121 * @param a2 The third extra argument.
1122 * @param a3 The fourth extra argument.
1123 */
1124#define IEM_MC_CALL_CIMPL_4(a_pfnCImpl, a0, a1, a2, a3) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3)
1125
1126/**
1127 * Defers the rest of the instruction emulation to a C implementation routine
1128 * and returns, taking two arguments in addition to the standard ones.
1129 *
1130 * @param a_pfnCImpl The pointer to the C routine.
1131 * @param a0 The first extra argument.
1132 * @param a1 The second extra argument.
1133 * @param a2 The third extra argument.
1134 * @param a3 The fourth extra argument.
1135 * @param a4 The fifth extra argument.
1136 */
1137#define IEM_MC_CALL_CIMPL_5(a_pfnCImpl, a0, a1, a2, a3, a4) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3, a4)
1138
1139/**
1140 * Defers the entire instruction emulation to a C implementation routine and
1141 * returns, only taking the standard parameters.
1142 *
1143 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1144 *
1145 * @param a_pfnCImpl The pointer to the C routine.
1146 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
1147 */
1148#define IEM_MC_DEFER_TO_CIMPL_0(a_pfnCImpl) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
1149
1150/**
1151 * Defers the entire instruction emulation to a C implementation routine and
1152 * returns, taking one argument in addition to the standard ones.
1153 *
1154 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1155 *
1156 * @param a_pfnCImpl The pointer to the C routine.
1157 * @param a0 The argument.
1158 */
1159#define IEM_MC_DEFER_TO_CIMPL_1(a_pfnCImpl, a0) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
1160
1161/**
1162 * Defers the entire instruction emulation to a C implementation routine and
1163 * returns, taking two arguments in addition to the standard ones.
1164 *
1165 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1166 *
1167 * @param a_pfnCImpl The pointer to the C routine.
1168 * @param a0 The first extra argument.
1169 * @param a1 The second extra argument.
1170 */
1171#define IEM_MC_DEFER_TO_CIMPL_2(a_pfnCImpl, a0, a1) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
1172
1173/**
1174 * Defers the entire instruction emulation to a C implementation routine and
1175 * returns, taking three arguments in addition to the standard ones.
1176 *
1177 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1178 *
1179 * @param a_pfnCImpl The pointer to the C routine.
1180 * @param a0 The first extra argument.
1181 * @param a1 The second extra argument.
1182 * @param a2 The third extra argument.
1183 */
1184#define IEM_MC_DEFER_TO_CIMPL_3(a_pfnCImpl, a0, a1, a2) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1185
1186/**
1187 * Calls a FPU assembly implementation taking one visible argument.
1188 *
1189 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1190 * @param a0 The first extra argument.
1191 */
1192#define IEM_MC_CALL_FPU_AIMPL_1(a_pfnAImpl, a0) \
1193 do { \
1194 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0)); \
1195 } while (0)
1196
1197/**
1198 * Calls a FPU assembly implementation taking two visible arguments.
1199 *
1200 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1201 * @param a0 The first extra argument.
1202 * @param a1 The second extra argument.
1203 */
1204#define IEM_MC_CALL_FPU_AIMPL_2(a_pfnAImpl, a0, a1) \
1205 do { \
1206 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1207 } while (0)
1208
1209/**
1210 * Calls a FPU assembly implementation taking three visible arguments.
1211 *
1212 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1213 * @param a0 The first extra argument.
1214 * @param a1 The second extra argument.
1215 * @param a2 The third extra argument.
1216 */
1217#define IEM_MC_CALL_FPU_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1218 do { \
1219 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1220 } while (0)
1221
1222#define IEM_MC_SET_FPU_RESULT(a_FpuData, a_FSW, a_pr80Value) \
1223 do { \
1224 (a_FpuData).FSW = (a_FSW); \
1225 (a_FpuData).r80Result = *(a_pr80Value); \
1226 } while (0)
1227
1228/** Pushes FPU result onto the stack. */
1229#define IEM_MC_PUSH_FPU_RESULT(a_FpuData) \
1230 iemFpuPushResult(pVCpu, &a_FpuData)
1231/** Pushes FPU result onto the stack and sets the FPUDP. */
1232#define IEM_MC_PUSH_FPU_RESULT_MEM_OP(a_FpuData, a_iEffSeg, a_GCPtrEff) \
1233 iemFpuPushResultWithMemOp(pVCpu, &a_FpuData, a_iEffSeg, a_GCPtrEff)
1234
1235/** Replaces ST0 with value one and pushes value 2 onto the FPU stack. */
1236#define IEM_MC_PUSH_FPU_RESULT_TWO(a_FpuDataTwo) \
1237 iemFpuPushResultTwo(pVCpu, &a_FpuDataTwo)
1238
1239/** Stores FPU result in a stack register. */
1240#define IEM_MC_STORE_FPU_RESULT(a_FpuData, a_iStReg) \
1241 iemFpuStoreResult(pVCpu, &a_FpuData, a_iStReg)
1242/** Stores FPU result in a stack register and pops the stack. */
1243#define IEM_MC_STORE_FPU_RESULT_THEN_POP(a_FpuData, a_iStReg) \
1244 iemFpuStoreResultThenPop(pVCpu, &a_FpuData, a_iStReg)
1245/** Stores FPU result in a stack register and sets the FPUDP. */
1246#define IEM_MC_STORE_FPU_RESULT_MEM_OP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1247 iemFpuStoreResultWithMemOp(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1248/** Stores FPU result in a stack register, sets the FPUDP, and pops the
1249 * stack. */
1250#define IEM_MC_STORE_FPU_RESULT_WITH_MEM_OP_THEN_POP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1251 iemFpuStoreResultWithMemOpThenPop(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1252
1253/** Only update the FOP, FPUIP, and FPUCS. (For FNOP.) */
1254#define IEM_MC_UPDATE_FPU_OPCODE_IP() \
1255 iemFpuUpdateOpcodeAndIp(pVCpu)
1256/** Free a stack register (for FFREE and FFREEP). */
1257#define IEM_MC_FPU_STACK_FREE(a_iStReg) \
1258 iemFpuStackFree(pVCpu, a_iStReg)
1259/** Increment the FPU stack pointer. */
1260#define IEM_MC_FPU_STACK_INC_TOP() \
1261 iemFpuStackIncTop(pVCpu)
1262/** Decrement the FPU stack pointer. */
1263#define IEM_MC_FPU_STACK_DEC_TOP() \
1264 iemFpuStackDecTop(pVCpu)
1265
1266/** Updates the FSW, FOP, FPUIP, and FPUCS. */
1267#define IEM_MC_UPDATE_FSW(a_u16FSW) \
1268 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1269/** Updates the FSW with a constant value as well as FOP, FPUIP, and FPUCS. */
1270#define IEM_MC_UPDATE_FSW_CONST(a_u16FSW) \
1271 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1272/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP, and FPUDS. */
1273#define IEM_MC_UPDATE_FSW_WITH_MEM_OP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1274 iemFpuUpdateFSWWithMemOp(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1275/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack. */
1276#define IEM_MC_UPDATE_FSW_THEN_POP(a_u16FSW) \
1277 iemFpuUpdateFSWThenPop(pVCpu, a_u16FSW)
1278/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP and FPUDS, and then pops the
1279 * stack. */
1280#define IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1281 iemFpuUpdateFSWWithMemOpThenPop(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1282/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack twice. */
1283#define IEM_MC_UPDATE_FSW_THEN_POP_POP(a_u16FSW) \
1284 iemFpuUpdateFSWThenPopPop(pVCpu, a_u16FSW)
1285
1286/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. */
1287#define IEM_MC_FPU_STACK_UNDERFLOW(a_iStDst) \
1288 iemFpuStackUnderflow(pVCpu, a_iStDst)
1289/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1290 * stack. */
1291#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(a_iStDst) \
1292 iemFpuStackUnderflowThenPop(pVCpu, a_iStDst)
1293/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1294 * FPUDS. */
1295#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1296 iemFpuStackUnderflowWithMemOp(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1297/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1298 * FPUDS. Pops stack. */
1299#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1300 iemFpuStackUnderflowWithMemOpThenPop(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1301/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1302 * stack twice. */
1303#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP() \
1304 iemFpuStackUnderflowThenPopPop(pVCpu)
1305/** Raises a FPU stack underflow exception for an instruction pushing a result
1306 * value onto the stack. Sets FPUIP, FPUCS and FOP. */
1307#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW() \
1308 iemFpuStackPushUnderflow(pVCpu)
1309/** Raises a FPU stack underflow exception for an instruction pushing a result
1310 * value onto the stack and replacing ST0. Sets FPUIP, FPUCS and FOP. */
1311#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO() \
1312 iemFpuStackPushUnderflowTwo(pVCpu)
1313
1314/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1315 * FPUIP, FPUCS and FOP. */
1316#define IEM_MC_FPU_STACK_PUSH_OVERFLOW() \
1317 iemFpuStackPushOverflow(pVCpu)
1318/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1319 * FPUIP, FPUCS, FOP, FPUDP and FPUDS. */
1320#define IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(a_iEffSeg, a_GCPtrEff) \
1321 iemFpuStackPushOverflowWithMemOp(pVCpu, a_iEffSeg, a_GCPtrEff)
1322/** Prepares for using the FPU state.
1323 * Ensures that we can use the host FPU in the current context (RC+R0.
1324 * Ensures the guest FPU state in the CPUMCTX is up to date. */
1325#define IEM_MC_PREPARE_FPU_USAGE() iemFpuPrepareUsage(pVCpu)
1326/** Actualizes the guest FPU state so it can be accessed read-only fashion. */
1327#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ() iemFpuActualizeStateForRead(pVCpu)
1328/** Actualizes the guest FPU state so it can be accessed and modified. */
1329#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE() iemFpuActualizeStateForChange(pVCpu)
1330
1331/** Stores SSE SIMD result updating MXCSR. */
1332#define IEM_MC_STORE_SSE_RESULT(a_SseData, a_iXmmReg) \
1333 iemSseStoreResult(pVCpu, &a_SseData, a_iXmmReg)
1334/** Updates MXCSR. */
1335#define IEM_MC_SSE_UPDATE_MXCSR(a_fMxcsr) \
1336 iemSseUpdateMxcsr(pVCpu, a_fMxcsr)
1337
1338/** Prepares for using the SSE state.
1339 * Ensures that we can use the host SSE/FPU in the current context (RC+R0.
1340 * Ensures the guest SSE state in the CPUMCTX is up to date. */
1341#define IEM_MC_PREPARE_SSE_USAGE() iemFpuPrepareUsageSse(pVCpu)
1342/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1343#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ() iemFpuActualizeSseStateForRead(pVCpu)
1344/** Actualizes the guest XMM0..15 and MXCSR register state for read-write access. */
1345#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE() iemFpuActualizeSseStateForChange(pVCpu)
1346
1347/** Prepares for using the AVX state.
1348 * Ensures that we can use the host AVX/FPU in the current context (RC+R0.
1349 * Ensures the guest AVX state in the CPUMCTX is up to date.
1350 * @note This will include the AVX512 state too when support for it is added
1351 * due to the zero extending feature of VEX instruction. */
1352#define IEM_MC_PREPARE_AVX_USAGE() iemFpuPrepareUsageAvx(pVCpu)
1353/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1354#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ() iemFpuActualizeAvxStateForRead(pVCpu)
1355/** Actualizes the guest YMM0..15 and MXCSR register state for read-write access. */
1356#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE() iemFpuActualizeAvxStateForChange(pVCpu)
1357
1358/**
1359 * Calls a MMX assembly implementation taking two visible arguments.
1360 *
1361 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1362 * @param a0 The first extra argument.
1363 * @param a1 The second extra argument.
1364 */
1365#define IEM_MC_CALL_MMX_AIMPL_2(a_pfnAImpl, a0, a1) \
1366 do { \
1367 IEM_MC_PREPARE_FPU_USAGE(); \
1368 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1369 } while (0)
1370
1371/**
1372 * Calls a MMX assembly implementation taking three visible arguments.
1373 *
1374 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1375 * @param a0 The first extra argument.
1376 * @param a1 The second extra argument.
1377 * @param a2 The third extra argument.
1378 */
1379#define IEM_MC_CALL_MMX_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1380 do { \
1381 IEM_MC_PREPARE_FPU_USAGE(); \
1382 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1383 } while (0)
1384
1385
1386/**
1387 * Calls a SSE assembly implementation taking two visible arguments.
1388 *
1389 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1390 * @param a0 The first extra argument.
1391 * @param a1 The second extra argument.
1392 */
1393#define IEM_MC_CALL_SSE_AIMPL_2(a_pfnAImpl, a0, a1) \
1394 do { \
1395 IEM_MC_PREPARE_SSE_USAGE(); \
1396 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1397 } while (0)
1398
1399/**
1400 * Calls a SSE assembly implementation taking three visible arguments.
1401 *
1402 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1403 * @param a0 The first extra argument.
1404 * @param a1 The second extra argument.
1405 * @param a2 The third extra argument.
1406 */
1407#define IEM_MC_CALL_SSE_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1408 do { \
1409 IEM_MC_PREPARE_SSE_USAGE(); \
1410 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1411 } while (0)
1412
1413
1414/** Declares implicit arguments for IEM_MC_CALL_AVX_AIMPL_2,
1415 * IEM_MC_CALL_AVX_AIMPL_3, IEM_MC_CALL_AVX_AIMPL_4, ... */
1416#define IEM_MC_IMPLICIT_AVX_AIMPL_ARGS() \
1417 IEM_MC_ARG_CONST(PX86XSAVEAREA, pXState, &pVCpu->cpum.GstCtx.XState, 0)
1418
1419/**
1420 * Calls a AVX assembly implementation taking two visible arguments.
1421 *
1422 * There is one implicit zero'th argument, a pointer to the extended state.
1423 *
1424 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1425 * @param a1 The first extra argument.
1426 * @param a2 The second extra argument.
1427 */
1428#define IEM_MC_CALL_AVX_AIMPL_2(a_pfnAImpl, a1, a2) \
1429 do { \
1430 IEM_MC_PREPARE_AVX_USAGE(); \
1431 a_pfnAImpl(pXState, (a1), (a2)); \
1432 } while (0)
1433
1434/**
1435 * Calls a AVX assembly implementation taking three visible arguments.
1436 *
1437 * There is one implicit zero'th argument, a pointer to the extended state.
1438 *
1439 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1440 * @param a1 The first extra argument.
1441 * @param a2 The second extra argument.
1442 * @param a3 The third extra argument.
1443 */
1444#define IEM_MC_CALL_AVX_AIMPL_3(a_pfnAImpl, a1, a2, a3) \
1445 do { \
1446 IEM_MC_PREPARE_AVX_USAGE(); \
1447 a_pfnAImpl(pXState, (a1), (a2), (a3)); \
1448 } while (0)
1449
1450/** @note Not for IOPL or IF testing. */
1451#define IEM_MC_IF_EFL_BIT_SET(a_fBit) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) {
1452/** @note Not for IOPL or IF testing. */
1453#define IEM_MC_IF_EFL_BIT_NOT_SET(a_fBit) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit))) {
1454/** @note Not for IOPL or IF testing. */
1455#define IEM_MC_IF_EFL_ANY_BITS_SET(a_fBits) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBits)) {
1456/** @note Not for IOPL or IF testing. */
1457#define IEM_MC_IF_EFL_NO_BITS_SET(a_fBits) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBits))) {
1458/** @note Not for IOPL or IF testing. */
1459#define IEM_MC_IF_EFL_BITS_NE(a_fBit1, a_fBit2) \
1460 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1461 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1462/** @note Not for IOPL or IF testing. */
1463#define IEM_MC_IF_EFL_BITS_EQ(a_fBit1, a_fBit2) \
1464 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1465 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1466/** @note Not for IOPL or IF testing. */
1467#define IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(a_fBit, a_fBit1, a_fBit2) \
1468 if ( (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1469 || !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1470 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1471/** @note Not for IOPL or IF testing. */
1472#define IEM_MC_IF_EFL_BIT_NOT_SET_AND_BITS_EQ(a_fBit, a_fBit1, a_fBit2) \
1473 if ( !(pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1474 && !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1475 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1476#define IEM_MC_IF_CX_IS_NZ() if (pVCpu->cpum.GstCtx.cx != 0) {
1477#define IEM_MC_IF_ECX_IS_NZ() if (pVCpu->cpum.GstCtx.ecx != 0) {
1478#define IEM_MC_IF_RCX_IS_NZ() if (pVCpu->cpum.GstCtx.rcx != 0) {
1479/** @note Not for IOPL or IF testing. */
1480#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1481 if ( pVCpu->cpum.GstCtx.cx != 0 \
1482 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1483/** @note Not for IOPL or IF testing. */
1484#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1485 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1486 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1487/** @note Not for IOPL or IF testing. */
1488#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1489 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1490 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1491/** @note Not for IOPL or IF testing. */
1492#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1493 if ( pVCpu->cpum.GstCtx.cx != 0 \
1494 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1495/** @note Not for IOPL or IF testing. */
1496#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1497 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1498 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1499/** @note Not for IOPL or IF testing. */
1500#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1501 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1502 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1503#define IEM_MC_IF_LOCAL_IS_Z(a_Local) if ((a_Local) == 0) {
1504#define IEM_MC_IF_GREG_BIT_SET(a_iGReg, a_iBitNo) if (iemGRegFetchU64(pVCpu, (a_iGReg)) & RT_BIT_64(a_iBitNo)) {
1505
1506#define IEM_MC_REF_FPUREG(a_pr80Dst, a_iSt) \
1507 do { (a_pr80Dst) = &pVCpu->cpum.GstCtx.XState.x87.aRegs[X86_FSW_TOP_GET_ST(pVCpu->cpum.GstCtx.XState.x87.FSW, a_iSt)].r80; } while (0)
1508#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1509 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1510#define IEM_MC_IF_FPUREG_NOT_EMPTY(a_iSt) \
1511 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) == VINF_SUCCESS) {
1512#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1513 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1514#define IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(a_pr80Dst, a_iSt) \
1515 if (iemFpuStRegNotEmptyRef(pVCpu, (a_iSt), &(a_pr80Dst)) == VINF_SUCCESS) {
1516#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(a_pr80Dst0, a_iSt0, a_pr80Dst1, a_iSt1) \
1517 if (iemFpu2StRegsNotEmptyRef(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1), &(a_pr80Dst1)) == VINF_SUCCESS) {
1518#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(a_pr80Dst0, a_iSt0, a_iSt1) \
1519 if (iemFpu2StRegsNotEmptyRefFirst(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1)) == VINF_SUCCESS) {
1520#define IEM_MC_IF_FCW_IM() \
1521 if (pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_IM) {
1522#define IEM_MC_IF_MXCSR_XCPT_PENDING() \
1523 if (( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
1524 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) != 0) {
1525
1526#define IEM_MC_ELSE() } else {
1527#define IEM_MC_ENDIF() } do {} while (0)
1528
1529/** @} */
1530
1531#endif /* !VMM_INCLUDED_SRC_include_IEMMc_h */
1532
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