VirtualBox

source: vbox/trunk/src/VBox/VMM/include/IEMMc.h@ 99304

最後變更 在這個檔案從99304是 99304,由 vboxsync 提交於 2 年 前

VMM/IEM: More work on processing MC blocks, mainly related to reducing number of parameters for MC blocks in threaded function mode. bugref:10369
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1/* $Id: IEMMc.h 99304 2023-04-06 01:38:19Z vboxsync $ */
2/** @file
3 * IEM - Interpreted Execution Manager - IEM_MC_XXX.
4 */
5
6/*
7 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.alldomusa.eu.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_IEMMc_h
29#define VMM_INCLUDED_SRC_include_IEMMc_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34
35/** @name "Microcode" macros.
36 *
37 * The idea is that we should be able to use the same code to interpret
38 * instructions as well as recompiler instructions. Thus this obfuscation.
39 *
40 * @{
41 */
42#define IEM_MC_BEGIN(a_cArgs, a_cLocals) {
43#define IEM_MC_END() }
44
45/** Internal macro. */
46#define IEM_MC_RETURN_ON_FAILURE(a_Expr) \
47 do \
48 { \
49 VBOXSTRICTRC rcStrict2 = a_Expr; \
50 if (rcStrict2 != VINF_SUCCESS) \
51 return rcStrict2; \
52 } while (0)
53
54
55/** Advances RIP, finishes the instruction and returns.
56 * This may include raising debug exceptions and such. */
57#define IEM_MC_ADVANCE_RIP_AND_FINISH() return iemRegAddToRipAndFinishingClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
58/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
59#define IEM_MC_REL_JMP_S8_AND_FINISH(a_i8) \
60 return iemRegRipRelativeJumpS8AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i8), pVCpu->iem.s.enmEffOpSize)
61/** Sets RIP (may trigger \#GP), finishes the instruction and returns.
62 * @note only usable in 16-bit op size mode. */
63#define IEM_MC_REL_JMP_S16_AND_FINISH(a_i16) \
64 return iemRegRipRelativeJumpS16AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i16))
65/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
66#define IEM_MC_REL_JMP_S32_AND_FINISH(a_i32) \
67 return iemRegRipRelativeJumpS32AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i32), pVCpu->iem.s.enmEffOpSize)
68/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
69#define IEM_MC_SET_RIP_U16_AND_FINISH(a_u16NewIP) return iemRegRipJumpU16AndFinishClearningRF((pVCpu), (a_u16NewIP))
70/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
71#define IEM_MC_SET_RIP_U32_AND_FINISH(a_u32NewIP) return iemRegRipJumpU32AndFinishClearningRF((pVCpu), (a_u32NewIP))
72/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
73#define IEM_MC_SET_RIP_U64_AND_FINISH(a_u64NewIP) return iemRegRipJumpU64AndFinishClearningRF((pVCpu), (a_u64NewIP))
74
75#define IEM_MC_RAISE_DIVIDE_ERROR() return iemRaiseDivideError(pVCpu)
76#define IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() \
77 do { \
78 if (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS)) \
79 return iemRaiseDeviceNotAvailable(pVCpu); \
80 } while (0)
81#define IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() \
82 do { \
83 if ((pVCpu->cpum.GstCtx.cr0 & (X86_CR0_MP | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_TS)) \
84 return iemRaiseDeviceNotAvailable(pVCpu); \
85 } while (0)
86#define IEM_MC_MAYBE_RAISE_FPU_XCPT() \
87 do { \
88 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
89 return iemRaiseMathFault(pVCpu); \
90 } while (0)
91#define IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT() \
92 do { \
93 if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
94 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE) \
95 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx2) \
96 return iemRaiseUndefinedOpcode(pVCpu); \
97 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
98 return iemRaiseDeviceNotAvailable(pVCpu); \
99 } while (0)
100#define IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() \
101 do { \
102 if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
103 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE) \
104 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx) \
105 return iemRaiseUndefinedOpcode(pVCpu); \
106 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
107 return iemRaiseDeviceNotAvailable(pVCpu); \
108 } while (0)
109#define IEM_MC_MAYBE_RAISE_AESNI_RELATED_XCPT() \
110 do { \
111 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
112 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
113 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAesNi) \
114 return iemRaiseUndefinedOpcode(pVCpu); \
115 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
116 return iemRaiseDeviceNotAvailable(pVCpu); \
117 } while (0)
118#define IEM_MC_MAYBE_RAISE_SHA_RELATED_XCPT() \
119 do { \
120 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
121 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
122 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSha) \
123 return iemRaiseUndefinedOpcode(pVCpu); \
124 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
125 return iemRaiseDeviceNotAvailable(pVCpu); \
126 } while (0)
127#define IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT() \
128 do { \
129 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
130 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
131 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse42) \
132 return iemRaiseUndefinedOpcode(pVCpu); \
133 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
134 return iemRaiseDeviceNotAvailable(pVCpu); \
135 } while (0)
136#define IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT() \
137 do { \
138 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
139 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
140 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse41) \
141 return iemRaiseUndefinedOpcode(pVCpu); \
142 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
143 return iemRaiseDeviceNotAvailable(pVCpu); \
144 } while (0)
145#define IEM_MC_MAYBE_RAISE_SSSE3_RELATED_XCPT() \
146 do { \
147 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
148 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
149 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3) \
150 return iemRaiseUndefinedOpcode(pVCpu); \
151 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
152 return iemRaiseDeviceNotAvailable(pVCpu); \
153 } while (0)
154#define IEM_MC_MAYBE_RAISE_SSE3_RELATED_XCPT() \
155 do { \
156 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
157 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
158 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse3) \
159 return iemRaiseUndefinedOpcode(pVCpu); \
160 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
161 return iemRaiseDeviceNotAvailable(pVCpu); \
162 } while (0)
163#define IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT() \
164 do { \
165 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
166 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
167 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse2) \
168 return iemRaiseUndefinedOpcode(pVCpu); \
169 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
170 return iemRaiseDeviceNotAvailable(pVCpu); \
171 } while (0)
172#define IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() \
173 do { \
174 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
175 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
176 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse) \
177 return iemRaiseUndefinedOpcode(pVCpu); \
178 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
179 return iemRaiseDeviceNotAvailable(pVCpu); \
180 } while (0)
181#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT() \
182 do { \
183 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
184 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMmx) \
185 return iemRaiseUndefinedOpcode(pVCpu); \
186 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
187 return iemRaiseDeviceNotAvailable(pVCpu); \
188 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
189 return iemRaiseMathFault(pVCpu); \
190 } while (0)
191#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_EX(a_fSupported) \
192 do { \
193 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
194 || !(a_fSupported)) \
195 return iemRaiseUndefinedOpcode(pVCpu); \
196 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
197 return iemRaiseDeviceNotAvailable(pVCpu); \
198 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
199 return iemRaiseMathFault(pVCpu); \
200 } while (0)
201#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_CHECK_SSE_OR_MMXEXT() \
202 do { \
203 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
204 || ( !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse \
205 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAmdMmxExts) ) \
206 return iemRaiseUndefinedOpcode(pVCpu); \
207 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
208 return iemRaiseDeviceNotAvailable(pVCpu); \
209 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
210 return iemRaiseMathFault(pVCpu); \
211 } while (0)
212#define IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO() \
213 do { \
214 if (pVCpu->iem.s.uCpl != 0) \
215 return iemRaiseGeneralProtectionFault0(pVCpu); \
216 } while (0)
217#define IEM_MC_RAISE_GP0_IF_EFF_ADDR_UNALIGNED(a_EffAddr, a_cbAlign) \
218 do { \
219 if (!((a_EffAddr) & ((a_cbAlign) - 1))) { /* likely */ } \
220 else return iemRaiseGeneralProtectionFault0(pVCpu); \
221 } while (0)
222#define IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT() \
223 do { \
224 if ( pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT \
225 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFsGsBase \
226 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_FSGSBASE)) \
227 return iemRaiseUndefinedOpcode(pVCpu); \
228 } while (0)
229#define IEM_MC_MAYBE_RAISE_NON_CANONICAL_ADDR_GP0(a_u64Addr) \
230 do { \
231 if (!IEM_IS_CANONICAL(a_u64Addr)) \
232 return iemRaiseGeneralProtectionFault0(pVCpu); \
233 } while (0)
234#define IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
235 do { \
236 if (( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
237 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) != 0) \
238 { \
239 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT)\
240 return iemRaiseSimdFpException(pVCpu); \
241 else \
242 return iemRaiseUndefinedOpcode(pVCpu); \
243 } \
244 } while (0)
245#define IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
246 do { \
247 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT)\
248 return iemRaiseSimdFpException(pVCpu); \
249 else \
250 return iemRaiseUndefinedOpcode(pVCpu); \
251 } while (0)
252#define IEM_MC_MAYBE_RAISE_PCLMUL_RELATED_XCPT() \
253 do { \
254 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
255 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
256 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPclMul) \
257 return iemRaiseUndefinedOpcode(pVCpu); \
258 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
259 return iemRaiseDeviceNotAvailable(pVCpu); \
260 } while (0)
261
262
263#define IEM_MC_LOCAL(a_Type, a_Name) a_Type a_Name
264#define IEM_MC_LOCAL_CONST(a_Type, a_Name, a_Value) a_Type const a_Name = (a_Value)
265#define IEM_MC_REF_LOCAL(a_pRefArg, a_Local) (a_pRefArg) = &(a_Local)
266#define IEM_MC_ARG(a_Type, a_Name, a_iArg) a_Type a_Name
267#define IEM_MC_ARG_CONST(a_Type, a_Name, a_Value, a_iArg) a_Type const a_Name = (a_Value)
268#define IEM_MC_ARG_LOCAL_REF(a_Type, a_Name, a_Local, a_iArg) a_Type const a_Name = &(a_Local)
269#define IEM_MC_ARG_LOCAL_EFLAGS(a_pName, a_Name, a_iArg) \
270 uint32_t a_Name; \
271 uint32_t *a_pName = &a_Name
272#define IEM_MC_COMMIT_EFLAGS(a_EFlags) \
273 do { pVCpu->cpum.GstCtx.eflags.u = (a_EFlags); Assert(pVCpu->cpum.GstCtx.eflags.u & X86_EFL_1); } while (0)
274
275#define IEM_MC_ASSIGN(a_VarOrArg, a_CVariableOrConst) (a_VarOrArg) = (a_CVariableOrConst)
276#define IEM_MC_ASSIGN_TO_SMALLER IEM_MC_ASSIGN
277#define IEM_MC_ASSIGN_U8_SX_U64(a_u64VarOrArg, a_u8CVariableOrConst) \
278 (a_u64VarOrArg) = (int8_t)(a_u8CVariableOrConst)
279#define IEM_MC_ASSIGN_U32_SX_U64(a_u64VarOrArg, a_u32CVariableOrConst) \
280 (a_u64VarOrArg) = (int32_t)(a_u32CVariableOrConst)
281
282#define IEM_MC_FETCH_GREG_U8(a_u8Dst, a_iGReg) (a_u8Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
283#define IEM_MC_FETCH_GREG_U8_ZX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
284#define IEM_MC_FETCH_GREG_U8_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
285#define IEM_MC_FETCH_GREG_U8_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
286#define IEM_MC_FETCH_GREG_U8_SX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
287#define IEM_MC_FETCH_GREG_U8_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
288#define IEM_MC_FETCH_GREG_U8_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
289#define IEM_MC_FETCH_GREG_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
290#define IEM_MC_FETCH_GREG_U16_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
291#define IEM_MC_FETCH_GREG_U16_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
292#define IEM_MC_FETCH_GREG_U16_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
293#define IEM_MC_FETCH_GREG_U16_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
294#define IEM_MC_FETCH_GREG_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
295#define IEM_MC_FETCH_GREG_U32_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
296#define IEM_MC_FETCH_GREG_U32_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int32_t)iemGRegFetchU32(pVCpu, (a_iGReg))
297#define IEM_MC_FETCH_GREG_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU64(pVCpu, (a_iGReg))
298#define IEM_MC_FETCH_GREG_U64_ZX_U64 IEM_MC_FETCH_GREG_U64
299#define IEM_MC_FETCH_SREG_U16(a_u16Dst, a_iSReg) do { \
300 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
301 (a_u16Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
302 } while (0)
303#define IEM_MC_FETCH_SREG_ZX_U32(a_u32Dst, a_iSReg) do { \
304 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
305 (a_u32Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
306 } while (0)
307#define IEM_MC_FETCH_SREG_ZX_U64(a_u64Dst, a_iSReg) do { \
308 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
309 (a_u64Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
310 } while (0)
311/** @todo IEM_MC_FETCH_SREG_BASE_U64 & IEM_MC_FETCH_SREG_BASE_U32 probably aren't worth it... */
312#define IEM_MC_FETCH_SREG_BASE_U64(a_u64Dst, a_iSReg) do { \
313 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
314 (a_u64Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
315 } while (0)
316#define IEM_MC_FETCH_SREG_BASE_U32(a_u32Dst, a_iSReg) do { \
317 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
318 (a_u32Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
319 } while (0)
320/** @note Not for IOPL or IF testing or modification. */
321#define IEM_MC_FETCH_EFLAGS(a_EFlags) (a_EFlags) = pVCpu->cpum.GstCtx.eflags.u
322#define IEM_MC_FETCH_EFLAGS_U8(a_EFlags) (a_EFlags) = (uint8_t)pVCpu->cpum.GstCtx.eflags.u
323#define IEM_MC_FETCH_FSW(a_u16Fsw) (a_u16Fsw) = pVCpu->cpum.GstCtx.XState.x87.FSW
324#define IEM_MC_FETCH_FCW(a_u16Fcw) (a_u16Fcw) = pVCpu->cpum.GstCtx.XState.x87.FCW
325
326#define IEM_MC_STORE_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) = (a_u8Value)
327#define IEM_MC_STORE_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) = (a_u16Value)
328#define IEM_MC_STORE_GREG_U32(a_iGReg, a_u32Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (uint32_t)(a_u32Value) /* clear high bits. */
329#define IEM_MC_STORE_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (a_u64Value)
330#define IEM_MC_STORE_GREG_I64(a_iGReg, a_i64Value) *iemGRegRefI64(pVCpu, (a_iGReg)) = (a_i64Value)
331#define IEM_MC_STORE_GREG_U8_CONST IEM_MC_STORE_GREG_U8
332#define IEM_MC_STORE_GREG_U16_CONST IEM_MC_STORE_GREG_U16
333#define IEM_MC_STORE_GREG_U32_CONST IEM_MC_STORE_GREG_U32
334#define IEM_MC_STORE_GREG_U64_CONST IEM_MC_STORE_GREG_U64
335#define IEM_MC_CLEAR_HIGH_GREG_U64(a_iGReg) *iemGRegRefU64(pVCpu, (a_iGReg)) &= UINT32_MAX
336#define IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(a_pu32Dst) do { (a_pu32Dst)[1] = 0; } while (0)
337/** @todo IEM_MC_STORE_SREG_BASE_U64 & IEM_MC_STORE_SREG_BASE_U32 aren't worth it... */
338#define IEM_MC_STORE_SREG_BASE_U64(a_iSReg, a_u64Value) do { \
339 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
340 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (a_u64Value); \
341 } while (0)
342#define IEM_MC_STORE_SREG_BASE_U32(a_iSReg, a_u32Value) do { \
343 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
344 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (uint32_t)(a_u32Value); /* clear high bits. */ \
345 } while (0)
346#define IEM_MC_STORE_FPUREG_R80_SRC_REF(a_iSt, a_pr80Src) \
347 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[a_iSt].r80 = *(a_pr80Src); } while (0)
348
349
350#define IEM_MC_REF_GREG_U8(a_pu8Dst, a_iGReg) (a_pu8Dst) = iemGRegRefU8( pVCpu, (a_iGReg))
351#define IEM_MC_REF_GREG_U16(a_pu16Dst, a_iGReg) (a_pu16Dst) = iemGRegRefU16(pVCpu, (a_iGReg))
352/** @todo User of IEM_MC_REF_GREG_U32 needs to clear the high bits on commit.
353 * Use IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF! */
354#define IEM_MC_REF_GREG_U32(a_pu32Dst, a_iGReg) (a_pu32Dst) = iemGRegRefU32(pVCpu, (a_iGReg))
355#define IEM_MC_REF_GREG_I32(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t *)iemGRegRefU32(pVCpu, (a_iGReg))
356#define IEM_MC_REF_GREG_I32_CONST(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t const *)iemGRegRefU32(pVCpu, (a_iGReg))
357#define IEM_MC_REF_GREG_U64(a_pu64Dst, a_iGReg) (a_pu64Dst) = iemGRegRefU64(pVCpu, (a_iGReg))
358#define IEM_MC_REF_GREG_I64(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t *)iemGRegRefU64(pVCpu, (a_iGReg))
359#define IEM_MC_REF_GREG_I64_CONST(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t const *)iemGRegRefU64(pVCpu, (a_iGReg))
360/** @note Not for IOPL or IF testing or modification.
361 * @note Must preserve any undefined bits, see CPUMX86EFLAGS! */
362#define IEM_MC_REF_EFLAGS(a_pEFlags) (a_pEFlags) = &pVCpu->cpum.GstCtx.eflags.uBoth
363#define IEM_MC_REF_MXCSR(a_pfMxcsr) (a_pfMxcsr) = &pVCpu->cpum.GstCtx.XState.x87.MXCSR
364
365#define IEM_MC_ADD_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) += (a_u8Value)
366#define IEM_MC_ADD_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) += (a_u16Value)
367#define IEM_MC_ADD_GREG_U32(a_iGReg, a_u32Value) \
368 do { \
369 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
370 *pu32Reg += (a_u32Value); \
371 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
372 } while (0)
373#define IEM_MC_ADD_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) += (a_u64Value)
374
375#define IEM_MC_SUB_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) -= (a_u8Value)
376#define IEM_MC_SUB_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) -= (a_u16Value)
377#define IEM_MC_SUB_GREG_U32(a_iGReg, a_u32Value) \
378 do { \
379 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
380 *pu32Reg -= (a_u32Value); \
381 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
382 } while (0)
383#define IEM_MC_SUB_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) -= (a_u64Value)
384#define IEM_MC_SUB_LOCAL_U16(a_u16Value, a_u16Const) do { (a_u16Value) -= a_u16Const; } while (0)
385
386#define IEM_MC_ADD_GREG_U8_TO_LOCAL(a_u8Value, a_iGReg) do { (a_u8Value) += iemGRegFetchU8( pVCpu, (a_iGReg)); } while (0)
387#define IEM_MC_ADD_GREG_U16_TO_LOCAL(a_u16Value, a_iGReg) do { (a_u16Value) += iemGRegFetchU16(pVCpu, (a_iGReg)); } while (0)
388#define IEM_MC_ADD_GREG_U32_TO_LOCAL(a_u32Value, a_iGReg) do { (a_u32Value) += iemGRegFetchU32(pVCpu, (a_iGReg)); } while (0)
389#define IEM_MC_ADD_GREG_U64_TO_LOCAL(a_u64Value, a_iGReg) do { (a_u64Value) += iemGRegFetchU64(pVCpu, (a_iGReg)); } while (0)
390#define IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR(a_EffAddr, a_i16) do { (a_EffAddr) += (a_i16); } while (0)
391#define IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR(a_EffAddr, a_i32) do { (a_EffAddr) += (a_i32); } while (0)
392#define IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR(a_EffAddr, a_i64) do { (a_EffAddr) += (a_i64); } while (0)
393
394#define IEM_MC_AND_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) &= (a_u8Mask); } while (0)
395#define IEM_MC_AND_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) &= (a_u16Mask); } while (0)
396#define IEM_MC_AND_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
397#define IEM_MC_AND_LOCAL_U64(a_u64Local, a_u64Mask) do { (a_u64Local) &= (a_u64Mask); } while (0)
398
399#define IEM_MC_AND_ARG_U16(a_u16Arg, a_u16Mask) do { (a_u16Arg) &= (a_u16Mask); } while (0)
400#define IEM_MC_AND_ARG_U32(a_u32Arg, a_u32Mask) do { (a_u32Arg) &= (a_u32Mask); } while (0)
401#define IEM_MC_AND_ARG_U64(a_u64Arg, a_u64Mask) do { (a_u64Arg) &= (a_u64Mask); } while (0)
402
403#define IEM_MC_OR_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) |= (a_u8Mask); } while (0)
404#define IEM_MC_OR_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) |= (a_u16Mask); } while (0)
405#define IEM_MC_OR_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
406
407#define IEM_MC_SAR_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) >>= (a_cShift); } while (0)
408#define IEM_MC_SAR_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) >>= (a_cShift); } while (0)
409#define IEM_MC_SAR_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) >>= (a_cShift); } while (0)
410
411#define IEM_MC_SHR_LOCAL_U8(a_u8Local, a_cShift) do { (a_u8Local) >>= (a_cShift); } while (0)
412
413#define IEM_MC_SHL_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) <<= (a_cShift); } while (0)
414#define IEM_MC_SHL_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) <<= (a_cShift); } while (0)
415#define IEM_MC_SHL_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) <<= (a_cShift); } while (0)
416
417#define IEM_MC_AND_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
418
419#define IEM_MC_OR_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
420
421#define IEM_MC_AND_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) &= (a_u8Value)
422#define IEM_MC_AND_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) &= (a_u16Value)
423#define IEM_MC_AND_GREG_U32(a_iGReg, a_u32Value) \
424 do { \
425 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
426 *pu32Reg &= (a_u32Value); \
427 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
428 } while (0)
429#define IEM_MC_AND_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) &= (a_u64Value)
430
431#define IEM_MC_OR_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) |= (a_u8Value)
432#define IEM_MC_OR_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) |= (a_u16Value)
433#define IEM_MC_OR_GREG_U32(a_iGReg, a_u32Value) \
434 do { \
435 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
436 *pu32Reg |= (a_u32Value); \
437 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
438 } while (0)
439#define IEM_MC_OR_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) |= (a_u64Value)
440
441#define IEM_MC_BSWAP_LOCAL_U16(a_u16Local) (a_u16Local) = RT_BSWAP_U16((a_u16Local));
442#define IEM_MC_BSWAP_LOCAL_U32(a_u32Local) (a_u32Local) = RT_BSWAP_U32((a_u32Local));
443#define IEM_MC_BSWAP_LOCAL_U64(a_u64Local) (a_u64Local) = RT_BSWAP_U64((a_u64Local));
444
445/** @note Not for IOPL or IF modification. */
446#define IEM_MC_SET_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u |= (a_fBit); } while (0)
447/** @note Not for IOPL or IF modification. */
448#define IEM_MC_CLEAR_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u &= ~(a_fBit); } while (0)
449/** @note Not for IOPL or IF modification. */
450#define IEM_MC_FLIP_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u ^= (a_fBit); } while (0)
451
452#define IEM_MC_CLEAR_FSW_EX() do { pVCpu->cpum.GstCtx.XState.x87.FSW &= X86_FSW_C_MASK | X86_FSW_TOP_MASK; } while (0)
453
454/** Switches the FPU state to MMX mode (FSW.TOS=0, FTW=0) if necessary. */
455#define IEM_MC_FPU_TO_MMX_MODE() do { \
456 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
457 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
458 pVCpu->cpum.GstCtx.XState.x87.FTW = 0xff; \
459 } while (0)
460
461/** Switches the FPU state from MMX mode (FSW.TOS=0, FTW=0xffff). */
462#define IEM_MC_FPU_FROM_MMX_MODE() do { \
463 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
464 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
465 pVCpu->cpum.GstCtx.XState.x87.FTW = 0; \
466 } while (0)
467
468#define IEM_MC_FETCH_MREG_U64(a_u64Value, a_iMReg) \
469 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx; } while (0)
470#define IEM_MC_FETCH_MREG_U32(a_u32Value, a_iMReg) \
471 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[0]; } while (0)
472#define IEM_MC_STORE_MREG_U64(a_iMReg, a_u64Value) do { \
473 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (a_u64Value); \
474 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
475 } while (0)
476#define IEM_MC_STORE_MREG_U32_ZX_U64(a_iMReg, a_u32Value) do { \
477 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (uint32_t)(a_u32Value); \
478 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
479 } while (0)
480#define IEM_MC_REF_MREG_U64(a_pu64Dst, a_iMReg) /** @todo need to set high word to 0xffff on commit (see IEM_MC_STORE_MREG_U64) */ \
481 (a_pu64Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
482#define IEM_MC_REF_MREG_U64_CONST(a_pu64Dst, a_iMReg) \
483 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
484#define IEM_MC_REF_MREG_U32_CONST(a_pu32Dst, a_iMReg) \
485 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
486#define IEM_MC_MODIFIED_MREG(a_iMReg) \
487 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; } while (0)
488#define IEM_MC_MODIFIED_MREG_BY_REF(a_pu64Dst) \
489 do { ((uint32_t *)(a_pu64Dst))[2] = 0xffff; } while (0)
490
491#define IEM_MC_CLEAR_XREG_U32_MASK(a_iXReg, a_bMask) \
492 do { if ((a_bMask) & (1 << 0)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0] = 0; \
493 if ((a_bMask) & (1 << 1)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[1] = 0; \
494 if ((a_bMask) & (1 << 2)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[2] = 0; \
495 if ((a_bMask) & (1 << 3)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[3] = 0; \
496 } while (0)
497#define IEM_MC_FETCH_XREG_U128(a_u128Value, a_iXReg) \
498 do { (a_u128Value).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
499 (a_u128Value).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
500 } while (0)
501#define IEM_MC_FETCH_XREG_XMM(a_XmmValue, a_iXReg) \
502 do { (a_XmmValue).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
503 (a_XmmValue).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
504 } while (0)
505#define IEM_MC_FETCH_XREG_U64(a_u64Value, a_iXReg, a_iQWord) \
506 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQWord)]; } while (0)
507#define IEM_MC_FETCH_XREG_U32(a_u32Value, a_iXReg, a_iDWord) \
508 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDWord)]; } while (0)
509#define IEM_MC_FETCH_XREG_U16(a_u16Value, a_iXReg, a_iWord) \
510 do { (a_u16Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au16[(a_iWord)]; } while (0)
511#define IEM_MC_FETCH_XREG_U8( a_u8Value, a_iXReg, a_iByte) \
512 do { (a_u8Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au16[(a_iByte)]; } while (0)
513#define IEM_MC_STORE_XREG_U128(a_iXReg, a_u128Value) \
514 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u128Value).au64[0]; \
515 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u128Value).au64[1]; \
516 } while (0)
517#define IEM_MC_STORE_XREG_XMM(a_iXReg, a_XmmValue) \
518 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_XmmValue).au64[0]; \
519 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_XmmValue).au64[1]; \
520 } while (0)
521#define IEM_MC_STORE_XREG_XMM_U32(a_iXReg, a_iDword, a_XmmValue) \
522 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDword)] = (a_XmmValue).au32[(a_iDword)]; } while (0)
523#define IEM_MC_STORE_XREG_XMM_U64(a_iXReg, a_iQword, a_XmmValue) \
524 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQword)] = (a_XmmValue).au64[(a_iQword)]; } while (0)
525#define IEM_MC_STORE_XREG_U64(a_iXReg, a_iQword, a_u64Value) \
526 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQword)] = (a_u64Value); } while (0)
527#define IEM_MC_STORE_XREG_U32(a_iXReg, a_iDword, a_u32Value) \
528 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDword)] = (a_u32Value); } while (0)
529#define IEM_MC_STORE_XREG_U16(a_iXReg, a_iWord, a_u16Value) \
530 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iWord)] = (a_u16Value); } while (0)
531#define IEM_MC_STORE_XREG_U8(a_iXReg, a_iByte, a_u8Value) \
532 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iByte)] = (a_u8Value); } while (0)
533
534#define IEM_MC_STORE_XREG_U64_ZX_U128(a_iXReg, a_u64Value) \
535 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u64Value); \
536 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
537 } while (0)
538
539#define IEM_MC_STORE_XREG_U32_U128(a_iXReg, a_iDwDst, a_u128Value, a_iDwSrc) \
540 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDwDst)] = (a_u128Value).au32[(a_iDwSrc)]; } while (0)
541#define IEM_MC_STORE_XREG_R32(a_iXReg, a_r32Value) \
542 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0] = (a_r32Value); } while (0)
543#define IEM_MC_STORE_XREG_R64(a_iXReg, a_r64Value) \
544 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0] = (a_r64Value); } while (0)
545#define IEM_MC_STORE_XREG_U32_ZX_U128(a_iXReg, a_u32Value) \
546 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (uint32_t)(a_u32Value); \
547 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
548 } while (0)
549#define IEM_MC_STORE_XREG_HI_U64(a_iXReg, a_u64Value) \
550 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u64Value); } while (0)
551#define IEM_MC_REF_XREG_U128(a_pu128Dst, a_iXReg) \
552 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
553#define IEM_MC_REF_XREG_U128_CONST(a_pu128Dst, a_iXReg) \
554 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
555#define IEM_MC_REF_XREG_XMM_CONST(a_pXmmDst, a_iXReg) \
556 (a_pXmmDst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)])
557#define IEM_MC_REF_XREG_U32_CONST(a_pu32Dst, a_iXReg) \
558 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0])
559#define IEM_MC_REF_XREG_U64_CONST(a_pu64Dst, a_iXReg) \
560 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0])
561#define IEM_MC_REF_XREG_R32_CONST(a_pr32Dst, a_iXReg) \
562 (a_pr32Dst) = ((RTFLOAT32U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0])
563#define IEM_MC_REF_XREG_R64_CONST(a_pr64Dst, a_iXReg) \
564 (a_pr64Dst) = ((RTFLOAT64U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0])
565#define IEM_MC_COPY_XREG_U128(a_iXRegDst, a_iXRegSrc) \
566 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[0] \
567 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[0]; \
568 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[1] \
569 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[1]; \
570 } while (0)
571
572#define IEM_MC_FETCH_YREG_U32(a_u32Dst, a_iYRegSrc) \
573 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
574 (a_u32Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au32[0]; \
575 } while (0)
576#define IEM_MC_FETCH_YREG_U64(a_u64Dst, a_iYRegSrc) \
577 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
578 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
579 } while (0)
580#define IEM_MC_FETCH_YREG_2ND_U64(a_u64Dst, a_iYRegSrc) \
581 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
582 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
583 } while (0)
584#define IEM_MC_FETCH_YREG_U128(a_u128Dst, a_iYRegSrc) \
585 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
586 (a_u128Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
587 (a_u128Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
588 } while (0)
589#define IEM_MC_FETCH_YREG_U256(a_u256Dst, a_iYRegSrc) \
590 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
591 (a_u256Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
592 (a_u256Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
593 (a_u256Dst).au64[2] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
594 (a_u256Dst).au64[3] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
595 } while (0)
596
597#define IEM_MC_INT_CLEAR_ZMM_256_UP(a_iXRegDst) do { /* For AVX512 and AVX1024 support. */ } while (0)
598#define IEM_MC_STORE_YREG_U32_ZX_VLMAX(a_iYRegDst, a_u32Src) \
599 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
600 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = (a_u32Src); \
601 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = 0; \
602 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
603 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
604 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
605 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
606 } while (0)
607#define IEM_MC_STORE_YREG_U64_ZX_VLMAX(a_iYRegDst, a_u64Src) \
608 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
609 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Src); \
610 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
611 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
612 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
613 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
614 } while (0)
615#define IEM_MC_STORE_YREG_U128_ZX_VLMAX(a_iYRegDst, a_u128Src) \
616 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
617 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u128Src).au64[0]; \
618 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u128Src).au64[1]; \
619 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
620 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
621 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
622 } while (0)
623#define IEM_MC_STORE_YREG_U256_ZX_VLMAX(a_iYRegDst, a_u256Src) \
624 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
625 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u256Src).au64[0]; \
626 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u256Src).au64[1]; \
627 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = (a_u256Src).au64[2]; \
628 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = (a_u256Src).au64[3]; \
629 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
630 } while (0)
631
632#define IEM_MC_REF_YREG_U128(a_pu128Dst, a_iYReg) \
633 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
634#define IEM_MC_REF_YREG_U128_CONST(a_pu128Dst, a_iYReg) \
635 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
636#define IEM_MC_REF_YREG_U64_CONST(a_pu64Dst, a_iYReg) \
637 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].au64[0])
638#define IEM_MC_CLEAR_YREG_128_UP(a_iYReg) \
639 do { uintptr_t const iYRegTmp = (a_iYReg); \
640 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[0] = 0; \
641 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[1] = 0; \
642 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegTmp); \
643 } while (0)
644
645#define IEM_MC_COPY_YREG_U256_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
646 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
647 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
648 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
649 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
650 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
651 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
652 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
653 } while (0)
654#define IEM_MC_COPY_YREG_U128_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
655 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
656 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
657 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
658 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
659 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
660 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
661 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
662 } while (0)
663#define IEM_MC_COPY_YREG_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
664 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
665 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
666 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
667 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
668 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
669 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
670 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
671 } while (0)
672
673#define IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(a_iYRegDst, a_iYRegSrc32, a_iYRegSrcHx) \
674 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
675 uintptr_t const iYRegSrc32Tmp = (a_iYRegSrc32); \
676 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
677 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc32Tmp].au32[0]; \
678 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au32[1]; \
679 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
680 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
681 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
682 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
683 } while (0)
684#define IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) \
685 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
686 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
687 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
688 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
689 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
690 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
691 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
692 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
693 } while (0)
694#define IEM_MC_MERGE_YREG_U64LO_U64LO_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
695 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
696 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
697 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
698 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
699 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
700 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
701 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
702 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
703 } while (0)
704#define IEM_MC_MERGE_YREG_U64HI_U64HI_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
705 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
706 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
707 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
708 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[1]; \
709 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
710 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
711 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
712 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
713 } while (0)
714#define IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX(a_iYRegDst, a_iYRegSrcHx, a_u64Local) \
715 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
716 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
717 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
718 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u64Local); \
719 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
720 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
721 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
722 } while (0)
723#define IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX(a_iYRegDst, a_u64Local, a_iYRegSrcHx) \
724 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
725 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
726 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Local); \
727 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
728 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
729 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
730 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
731 } while (0)
732
733#ifndef IEM_WITH_SETJMP
734# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
735 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem)))
736# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
737 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem16)))
738# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
739 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem32)))
740#else
741# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
742 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
743# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
744 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem16)))
745# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
746 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem32)))
747#endif
748
749#ifndef IEM_WITH_SETJMP
750# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
751 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem)))
752# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
753 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
754# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
755 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, (uint16_t *)&(a_i16Dst), (a_iSeg), (a_GCPtrMem)))
756#else
757# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
758 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
759# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
760 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
761# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
762 ((a_i16Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
763#endif
764
765#ifndef IEM_WITH_SETJMP
766# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
767 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem)))
768# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
769 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
770# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
771 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, (uint32_t *)&(a_i32Dst), (a_iSeg), (a_GCPtrMem)))
772#else
773# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
774 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
775# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
776 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
777# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
778 ((a_i32Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
779#endif
780
781#ifdef SOME_UNUSED_FUNCTION
782# define IEM_MC_FETCH_MEM_S32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
783 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataS32SxU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
784#endif
785
786#ifndef IEM_WITH_SETJMP
787# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
788 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
789# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
790 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
791# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
792 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64AlignedU128(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
793# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
794 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, (uint64_t *)&(a_i64Dst), (a_iSeg), (a_GCPtrMem)))
795#else
796# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
797 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
798# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
799 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
800# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
801 ((a_u64Dst) = iemMemFetchDataU64AlignedU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
802# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
803 ((a_i64Dst) = (int64_t)iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
804#endif
805
806#ifndef IEM_WITH_SETJMP
807# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
808 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_r32Dst).u, (a_iSeg), (a_GCPtrMem)))
809# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
810 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_r64Dst).u, (a_iSeg), (a_GCPtrMem)))
811# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
812 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataR80(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem)))
813# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
814 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataD80(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem)))
815#else
816# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
817 ((a_r32Dst).u = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
818# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
819 ((a_r64Dst).u = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
820# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
821 iemMemFetchDataR80Jmp(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem))
822# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
823 iemMemFetchDataD80Jmp(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem))
824#endif
825
826#ifndef IEM_WITH_SETJMP
827# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
828 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
829# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
830 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
831# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
832 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
833
834# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
835 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
836# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
837 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
838# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
839 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
840# define IEM_MC_FETCH_MEM_XMM_U32(a_XmmDst, a_iDWord, a_iSeg, a_GCPtrMem) \
841 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_XmmDst).au32[(a_iDWord)], (a_iSeg), (a_GCPtrMem)))
842# define IEM_MC_FETCH_MEM_XMM_U64(a_XmmDst, a_iQWord, a_iSeg, a_GCPtrMem) \
843 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_XmmDst).au64[(a_iQWord)], (a_iSeg), (a_GCPtrMem)))
844#else
845# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
846 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
847# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
848 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
849# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
850 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
851
852# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
853 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
854# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
855 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
856# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
857 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
858# define IEM_MC_FETCH_MEM_XMM_U32(a_XmmDst, a_iDWord, a_iSeg, a_GCPtrMem) \
859 (a_XmmDst).au32[(a_iDWord)] = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem))
860# define IEM_MC_FETCH_MEM_XMM_U64(a_XmmDst, a_iQWord, a_iSeg, a_GCPtrMem) \
861 (a_XmmDst).au64[(a_iQWord)] = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem))
862#endif
863
864#ifndef IEM_WITH_SETJMP
865# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
866 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
867# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
868 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
869# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
870 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
871
872# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
873 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
874# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
875 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
876# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
877 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
878#else
879# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
880 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
881# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
882 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
883# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
884 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
885
886# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
887 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
888# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
889 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
890# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
891 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
892#endif
893
894
895
896#ifndef IEM_WITH_SETJMP
897# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
898 do { \
899 uint8_t u8Tmp; \
900 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
901 (a_u16Dst) = u8Tmp; \
902 } while (0)
903# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
904 do { \
905 uint8_t u8Tmp; \
906 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
907 (a_u32Dst) = u8Tmp; \
908 } while (0)
909# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
910 do { \
911 uint8_t u8Tmp; \
912 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
913 (a_u64Dst) = u8Tmp; \
914 } while (0)
915# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
916 do { \
917 uint16_t u16Tmp; \
918 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
919 (a_u32Dst) = u16Tmp; \
920 } while (0)
921# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
922 do { \
923 uint16_t u16Tmp; \
924 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
925 (a_u64Dst) = u16Tmp; \
926 } while (0)
927# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
928 do { \
929 uint32_t u32Tmp; \
930 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
931 (a_u64Dst) = u32Tmp; \
932 } while (0)
933#else /* IEM_WITH_SETJMP */
934# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
935 ((a_u16Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
936# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
937 ((a_u32Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
938# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
939 ((a_u64Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
940# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
941 ((a_u32Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
942# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
943 ((a_u64Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
944# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
945 ((a_u64Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
946#endif /* IEM_WITH_SETJMP */
947
948#ifndef IEM_WITH_SETJMP
949# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
950 do { \
951 uint8_t u8Tmp; \
952 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
953 (a_u16Dst) = (int8_t)u8Tmp; \
954 } while (0)
955# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
956 do { \
957 uint8_t u8Tmp; \
958 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
959 (a_u32Dst) = (int8_t)u8Tmp; \
960 } while (0)
961# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
962 do { \
963 uint8_t u8Tmp; \
964 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
965 (a_u64Dst) = (int8_t)u8Tmp; \
966 } while (0)
967# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
968 do { \
969 uint16_t u16Tmp; \
970 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
971 (a_u32Dst) = (int16_t)u16Tmp; \
972 } while (0)
973# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
974 do { \
975 uint16_t u16Tmp; \
976 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
977 (a_u64Dst) = (int16_t)u16Tmp; \
978 } while (0)
979# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
980 do { \
981 uint32_t u32Tmp; \
982 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
983 (a_u64Dst) = (int32_t)u32Tmp; \
984 } while (0)
985#else /* IEM_WITH_SETJMP */
986# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
987 ((a_u16Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
988# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
989 ((a_u32Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
990# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
991 ((a_u64Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
992# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
993 ((a_u32Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
994# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
995 ((a_u64Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
996# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
997 ((a_u64Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
998#endif /* IEM_WITH_SETJMP */
999
1000#ifndef IEM_WITH_SETJMP
1001# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
1002 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value)))
1003# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
1004 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value)))
1005# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
1006 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value)))
1007# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
1008 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value)))
1009#else
1010# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
1011 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value))
1012# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
1013 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value))
1014# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
1015 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value))
1016# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
1017 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value))
1018#endif
1019
1020#ifndef IEM_WITH_SETJMP
1021# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
1022 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C)))
1023# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
1024 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C)))
1025# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
1026 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C)))
1027# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
1028 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C)))
1029#else
1030# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
1031 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C))
1032# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
1033 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C))
1034# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
1035 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C))
1036# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
1037 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C))
1038#endif
1039
1040#define IEM_MC_STORE_MEM_I8_CONST_BY_REF( a_pi8Dst, a_i8C) *(a_pi8Dst) = (a_i8C)
1041#define IEM_MC_STORE_MEM_I16_CONST_BY_REF(a_pi16Dst, a_i16C) *(a_pi16Dst) = (a_i16C)
1042#define IEM_MC_STORE_MEM_I32_CONST_BY_REF(a_pi32Dst, a_i32C) *(a_pi32Dst) = (a_i32C)
1043#define IEM_MC_STORE_MEM_I64_CONST_BY_REF(a_pi64Dst, a_i64C) *(a_pi64Dst) = (a_i64C)
1044#define IEM_MC_STORE_MEM_NEG_QNAN_R32_BY_REF(a_pr32Dst) (a_pr32Dst)->u = UINT32_C(0xffc00000)
1045#define IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF(a_pr64Dst) (a_pr64Dst)->u = UINT64_C(0xfff8000000000000)
1046#define IEM_MC_STORE_MEM_NEG_QNAN_R80_BY_REF(a_pr80Dst) \
1047 do { \
1048 (a_pr80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
1049 (a_pr80Dst)->au16[4] = UINT16_C(0xffff); \
1050 } while (0)
1051#define IEM_MC_STORE_MEM_INDEF_D80_BY_REF(a_pd80Dst) \
1052 do { \
1053 (a_pd80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
1054 (a_pd80Dst)->au16[4] = UINT16_C(0xffff); \
1055 } while (0)
1056
1057#ifndef IEM_WITH_SETJMP
1058# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
1059 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
1060# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
1061 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128AlignedSse(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
1062#else
1063# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
1064 iemMemStoreDataU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
1065# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
1066 iemMemStoreDataU128AlignedSseJmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
1067#endif
1068
1069#ifndef IEM_WITH_SETJMP
1070# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
1071 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
1072# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
1073 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256AlignedAvx(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
1074#else
1075# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
1076 iemMemStoreDataU256Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
1077# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
1078 iemMemStoreDataU256AlignedAvxJmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
1079#endif
1080
1081
1082#define IEM_MC_PUSH_U16(a_u16Value) \
1083 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU16(pVCpu, (a_u16Value)))
1084#define IEM_MC_PUSH_U32(a_u32Value) \
1085 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32(pVCpu, (a_u32Value)))
1086#define IEM_MC_PUSH_U32_SREG(a_u32Value) \
1087 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32SReg(pVCpu, (a_u32Value)))
1088#define IEM_MC_PUSH_U64(a_u64Value) \
1089 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU64(pVCpu, (a_u64Value)))
1090
1091#define IEM_MC_POP_U16(a_pu16Value) \
1092 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU16(pVCpu, (a_pu16Value)))
1093#define IEM_MC_POP_U32(a_pu32Value) \
1094 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU32(pVCpu, (a_pu32Value)))
1095#define IEM_MC_POP_U64(a_pu64Value) \
1096 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU64(pVCpu, (a_pu64Value)))
1097
1098/** Maps guest memory for direct or bounce buffered access.
1099 * The purpose is to pass it to an operand implementation, thus the a_iArg.
1100 * @remarks May return.
1101 */
1102#define IEM_MC_MEM_MAP(a_pMem, a_fAccess, a_iSeg, a_GCPtrMem, a_iArg) \
1103 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pMem), sizeof(*(a_pMem)), (a_iSeg), \
1104 (a_GCPtrMem), (a_fAccess), sizeof(*(a_pMem)) - 1))
1105
1106/** Maps guest memory for direct or bounce buffered access.
1107 * The purpose is to pass it to an operand implementation, thus the a_iArg.
1108 * @remarks May return.
1109 */
1110#define IEM_MC_MEM_MAP_EX(a_pvMem, a_fAccess, a_cbMem, a_iSeg, a_GCPtrMem, a_cbAlign, a_iArg) \
1111 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pvMem), (a_cbMem), (a_iSeg), \
1112 (a_GCPtrMem), (a_fAccess), (a_cbAlign)))
1113
1114/** Commits the memory and unmaps the guest memory.
1115 * @remarks May return.
1116 */
1117#define IEM_MC_MEM_COMMIT_AND_UNMAP(a_pvMem, a_fAccess) \
1118 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess)))
1119
1120/** Commits the memory and unmaps the guest memory unless the FPU status word
1121 * indicates (@a a_u16FSW) and FPU control word indicates a pending exception
1122 * that would cause FLD not to store.
1123 *
1124 * The current understanding is that \#O, \#U, \#IA and \#IS will prevent a
1125 * store, while \#P will not.
1126 *
1127 * @remarks May in theory return - for now.
1128 */
1129#define IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(a_pvMem, a_fAccess, a_u16FSW) \
1130 do { \
1131 if ( !(a_u16FSW & X86_FSW_ES) \
1132 || !( (a_u16FSW & (X86_FSW_UE | X86_FSW_OE | X86_FSW_IE)) \
1133 & ~(pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_MASK_ALL) ) ) \
1134 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess))); \
1135 } while (0)
1136
1137/** Calculate efficient address from R/M. */
1138#ifndef IEM_WITH_SETJMP
1139# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
1140 IEM_MC_RETURN_ON_FAILURE(iemOpHlpCalcRmEffAddr(pVCpu, (bRm), (cbImm), &(a_GCPtrEff)))
1141#else
1142# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
1143 ((a_GCPtrEff) = iemOpHlpCalcRmEffAddrJmp(pVCpu, (bRm), (cbImm)))
1144#endif
1145
1146#define IEM_MC_CALL_VOID_AIMPL_0(a_pfn) (a_pfn)()
1147#define IEM_MC_CALL_VOID_AIMPL_1(a_pfn, a0) (a_pfn)((a0))
1148#define IEM_MC_CALL_VOID_AIMPL_2(a_pfn, a0, a1) (a_pfn)((a0), (a1))
1149#define IEM_MC_CALL_VOID_AIMPL_3(a_pfn, a0, a1, a2) (a_pfn)((a0), (a1), (a2))
1150#define IEM_MC_CALL_VOID_AIMPL_4(a_pfn, a0, a1, a2, a3) (a_pfn)((a0), (a1), (a2), (a3))
1151#define IEM_MC_CALL_AIMPL_3(a_rc, a_pfn, a0, a1, a2) (a_rc) = (a_pfn)((a0), (a1), (a2))
1152#define IEM_MC_CALL_AIMPL_4(a_rc, a_pfn, a0, a1, a2, a3) (a_rc) = (a_pfn)((a0), (a1), (a2), (a3))
1153
1154/**
1155 * Defers the rest of the instruction emulation to a C implementation routine
1156 * and returns, only taking the standard parameters.
1157 *
1158 * @param a_pfnCImpl The pointer to the C routine.
1159 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
1160 */
1161#define IEM_MC_CALL_CIMPL_0(a_pfnCImpl) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
1162
1163/**
1164 * Defers the rest of instruction emulation to a C implementation routine and
1165 * returns, taking one argument in addition to the standard ones.
1166 *
1167 * @param a_pfnCImpl The pointer to the C routine.
1168 * @param a0 The argument.
1169 */
1170#define IEM_MC_CALL_CIMPL_1(a_pfnCImpl, a0) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
1171
1172/**
1173 * Defers the rest of the instruction emulation to a C implementation routine
1174 * and returns, taking two arguments in addition to the standard ones.
1175 *
1176 * @param a_pfnCImpl The pointer to the C routine.
1177 * @param a0 The first extra argument.
1178 * @param a1 The second extra argument.
1179 */
1180#define IEM_MC_CALL_CIMPL_2(a_pfnCImpl, a0, a1) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
1181
1182/**
1183 * Defers the rest of the instruction emulation to a C implementation routine
1184 * and returns, taking three arguments in addition to the standard ones.
1185 *
1186 * @param a_pfnCImpl The pointer to the C routine.
1187 * @param a0 The first extra argument.
1188 * @param a1 The second extra argument.
1189 * @param a2 The third extra argument.
1190 */
1191#define IEM_MC_CALL_CIMPL_3(a_pfnCImpl, a0, a1, a2) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1192
1193/**
1194 * Defers the rest of the instruction emulation to a C implementation routine
1195 * and returns, taking four arguments in addition to the standard ones.
1196 *
1197 * @param a_pfnCImpl The pointer to the C routine.
1198 * @param a0 The first extra argument.
1199 * @param a1 The second extra argument.
1200 * @param a2 The third extra argument.
1201 * @param a3 The fourth extra argument.
1202 */
1203#define IEM_MC_CALL_CIMPL_4(a_pfnCImpl, a0, a1, a2, a3) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3)
1204
1205/**
1206 * Defers the rest of the instruction emulation to a C implementation routine
1207 * and returns, taking two arguments in addition to the standard ones.
1208 *
1209 * @param a_pfnCImpl The pointer to the C routine.
1210 * @param a0 The first extra argument.
1211 * @param a1 The second extra argument.
1212 * @param a2 The third extra argument.
1213 * @param a3 The fourth extra argument.
1214 * @param a4 The fifth extra argument.
1215 */
1216#define IEM_MC_CALL_CIMPL_5(a_pfnCImpl, a0, a1, a2, a3, a4) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3, a4)
1217
1218/**
1219 * Defers the entire instruction emulation to a C implementation routine and
1220 * returns, only taking the standard parameters.
1221 *
1222 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1223 *
1224 * @param a_pfnCImpl The pointer to the C routine.
1225 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
1226 */
1227#define IEM_MC_DEFER_TO_CIMPL_0(a_pfnCImpl) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
1228
1229/**
1230 * Defers the entire instruction emulation to a C implementation routine and
1231 * returns, taking one argument in addition to the standard ones.
1232 *
1233 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1234 *
1235 * @param a_pfnCImpl The pointer to the C routine.
1236 * @param a0 The argument.
1237 */
1238#define IEM_MC_DEFER_TO_CIMPL_1(a_pfnCImpl, a0) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
1239
1240/**
1241 * Defers the entire instruction emulation to a C implementation routine and
1242 * returns, taking two arguments in addition to the standard ones.
1243 *
1244 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1245 *
1246 * @param a_pfnCImpl The pointer to the C routine.
1247 * @param a0 The first extra argument.
1248 * @param a1 The second extra argument.
1249 */
1250#define IEM_MC_DEFER_TO_CIMPL_2(a_pfnCImpl, a0, a1) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
1251
1252/**
1253 * Defers the entire instruction emulation to a C implementation routine and
1254 * returns, taking three arguments in addition to the standard ones.
1255 *
1256 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1257 *
1258 * @param a_pfnCImpl The pointer to the C routine.
1259 * @param a0 The first extra argument.
1260 * @param a1 The second extra argument.
1261 * @param a2 The third extra argument.
1262 */
1263#define IEM_MC_DEFER_TO_CIMPL_3(a_pfnCImpl, a0, a1, a2) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1264
1265/**
1266 * Calls a FPU assembly implementation taking one visible argument.
1267 *
1268 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1269 * @param a0 The first extra argument.
1270 */
1271#define IEM_MC_CALL_FPU_AIMPL_1(a_pfnAImpl, a0) \
1272 do { \
1273 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0)); \
1274 } while (0)
1275
1276/**
1277 * Calls a FPU assembly implementation taking two visible arguments.
1278 *
1279 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1280 * @param a0 The first extra argument.
1281 * @param a1 The second extra argument.
1282 */
1283#define IEM_MC_CALL_FPU_AIMPL_2(a_pfnAImpl, a0, a1) \
1284 do { \
1285 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1286 } while (0)
1287
1288/**
1289 * Calls a FPU assembly implementation taking three visible arguments.
1290 *
1291 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1292 * @param a0 The first extra argument.
1293 * @param a1 The second extra argument.
1294 * @param a2 The third extra argument.
1295 */
1296#define IEM_MC_CALL_FPU_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1297 do { \
1298 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1299 } while (0)
1300
1301#define IEM_MC_SET_FPU_RESULT(a_FpuData, a_FSW, a_pr80Value) \
1302 do { \
1303 (a_FpuData).FSW = (a_FSW); \
1304 (a_FpuData).r80Result = *(a_pr80Value); \
1305 } while (0)
1306
1307/** Pushes FPU result onto the stack. */
1308#define IEM_MC_PUSH_FPU_RESULT(a_FpuData) \
1309 iemFpuPushResult(pVCpu, &a_FpuData)
1310/** Pushes FPU result onto the stack and sets the FPUDP. */
1311#define IEM_MC_PUSH_FPU_RESULT_MEM_OP(a_FpuData, a_iEffSeg, a_GCPtrEff) \
1312 iemFpuPushResultWithMemOp(pVCpu, &a_FpuData, a_iEffSeg, a_GCPtrEff)
1313
1314/** Replaces ST0 with value one and pushes value 2 onto the FPU stack. */
1315#define IEM_MC_PUSH_FPU_RESULT_TWO(a_FpuDataTwo) \
1316 iemFpuPushResultTwo(pVCpu, &a_FpuDataTwo)
1317
1318/** Stores FPU result in a stack register. */
1319#define IEM_MC_STORE_FPU_RESULT(a_FpuData, a_iStReg) \
1320 iemFpuStoreResult(pVCpu, &a_FpuData, a_iStReg)
1321/** Stores FPU result in a stack register and pops the stack. */
1322#define IEM_MC_STORE_FPU_RESULT_THEN_POP(a_FpuData, a_iStReg) \
1323 iemFpuStoreResultThenPop(pVCpu, &a_FpuData, a_iStReg)
1324/** Stores FPU result in a stack register and sets the FPUDP. */
1325#define IEM_MC_STORE_FPU_RESULT_MEM_OP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1326 iemFpuStoreResultWithMemOp(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1327/** Stores FPU result in a stack register, sets the FPUDP, and pops the
1328 * stack. */
1329#define IEM_MC_STORE_FPU_RESULT_WITH_MEM_OP_THEN_POP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1330 iemFpuStoreResultWithMemOpThenPop(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1331
1332/** Only update the FOP, FPUIP, and FPUCS. (For FNOP.) */
1333#define IEM_MC_UPDATE_FPU_OPCODE_IP() \
1334 iemFpuUpdateOpcodeAndIp(pVCpu)
1335/** Free a stack register (for FFREE and FFREEP). */
1336#define IEM_MC_FPU_STACK_FREE(a_iStReg) \
1337 iemFpuStackFree(pVCpu, a_iStReg)
1338/** Increment the FPU stack pointer. */
1339#define IEM_MC_FPU_STACK_INC_TOP() \
1340 iemFpuStackIncTop(pVCpu)
1341/** Decrement the FPU stack pointer. */
1342#define IEM_MC_FPU_STACK_DEC_TOP() \
1343 iemFpuStackDecTop(pVCpu)
1344
1345/** Updates the FSW, FOP, FPUIP, and FPUCS. */
1346#define IEM_MC_UPDATE_FSW(a_u16FSW) \
1347 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1348/** Updates the FSW with a constant value as well as FOP, FPUIP, and FPUCS. */
1349#define IEM_MC_UPDATE_FSW_CONST(a_u16FSW) \
1350 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1351/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP, and FPUDS. */
1352#define IEM_MC_UPDATE_FSW_WITH_MEM_OP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1353 iemFpuUpdateFSWWithMemOp(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1354/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack. */
1355#define IEM_MC_UPDATE_FSW_THEN_POP(a_u16FSW) \
1356 iemFpuUpdateFSWThenPop(pVCpu, a_u16FSW)
1357/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP and FPUDS, and then pops the
1358 * stack. */
1359#define IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1360 iemFpuUpdateFSWWithMemOpThenPop(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1361/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack twice. */
1362#define IEM_MC_UPDATE_FSW_THEN_POP_POP(a_u16FSW) \
1363 iemFpuUpdateFSWThenPopPop(pVCpu, a_u16FSW)
1364
1365/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. */
1366#define IEM_MC_FPU_STACK_UNDERFLOW(a_iStDst) \
1367 iemFpuStackUnderflow(pVCpu, a_iStDst)
1368/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1369 * stack. */
1370#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(a_iStDst) \
1371 iemFpuStackUnderflowThenPop(pVCpu, a_iStDst)
1372/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1373 * FPUDS. */
1374#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1375 iemFpuStackUnderflowWithMemOp(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1376/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1377 * FPUDS. Pops stack. */
1378#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1379 iemFpuStackUnderflowWithMemOpThenPop(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1380/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1381 * stack twice. */
1382#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP() \
1383 iemFpuStackUnderflowThenPopPop(pVCpu)
1384/** Raises a FPU stack underflow exception for an instruction pushing a result
1385 * value onto the stack. Sets FPUIP, FPUCS and FOP. */
1386#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW() \
1387 iemFpuStackPushUnderflow(pVCpu)
1388/** Raises a FPU stack underflow exception for an instruction pushing a result
1389 * value onto the stack and replacing ST0. Sets FPUIP, FPUCS and FOP. */
1390#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO() \
1391 iemFpuStackPushUnderflowTwo(pVCpu)
1392
1393/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1394 * FPUIP, FPUCS and FOP. */
1395#define IEM_MC_FPU_STACK_PUSH_OVERFLOW() \
1396 iemFpuStackPushOverflow(pVCpu)
1397/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1398 * FPUIP, FPUCS, FOP, FPUDP and FPUDS. */
1399#define IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(a_iEffSeg, a_GCPtrEff) \
1400 iemFpuStackPushOverflowWithMemOp(pVCpu, a_iEffSeg, a_GCPtrEff)
1401/** Prepares for using the FPU state.
1402 * Ensures that we can use the host FPU in the current context (RC+R0.
1403 * Ensures the guest FPU state in the CPUMCTX is up to date. */
1404#define IEM_MC_PREPARE_FPU_USAGE() iemFpuPrepareUsage(pVCpu)
1405/** Actualizes the guest FPU state so it can be accessed read-only fashion. */
1406#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ() iemFpuActualizeStateForRead(pVCpu)
1407/** Actualizes the guest FPU state so it can be accessed and modified. */
1408#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE() iemFpuActualizeStateForChange(pVCpu)
1409
1410/** Stores SSE SIMD result updating MXCSR. */
1411#define IEM_MC_STORE_SSE_RESULT(a_SseData, a_iXmmReg) \
1412 iemSseStoreResult(pVCpu, &a_SseData, a_iXmmReg)
1413/** Updates MXCSR. */
1414#define IEM_MC_SSE_UPDATE_MXCSR(a_fMxcsr) \
1415 iemSseUpdateMxcsr(pVCpu, a_fMxcsr)
1416
1417/** Prepares for using the SSE state.
1418 * Ensures that we can use the host SSE/FPU in the current context (RC+R0.
1419 * Ensures the guest SSE state in the CPUMCTX is up to date. */
1420#define IEM_MC_PREPARE_SSE_USAGE() iemFpuPrepareUsageSse(pVCpu)
1421/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1422#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ() iemFpuActualizeSseStateForRead(pVCpu)
1423/** Actualizes the guest XMM0..15 and MXCSR register state for read-write access. */
1424#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE() iemFpuActualizeSseStateForChange(pVCpu)
1425
1426/** Prepares for using the AVX state.
1427 * Ensures that we can use the host AVX/FPU in the current context (RC+R0.
1428 * Ensures the guest AVX state in the CPUMCTX is up to date.
1429 * @note This will include the AVX512 state too when support for it is added
1430 * due to the zero extending feature of VEX instruction. */
1431#define IEM_MC_PREPARE_AVX_USAGE() iemFpuPrepareUsageAvx(pVCpu)
1432/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1433#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ() iemFpuActualizeAvxStateForRead(pVCpu)
1434/** Actualizes the guest YMM0..15 and MXCSR register state for read-write access. */
1435#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE() iemFpuActualizeAvxStateForChange(pVCpu)
1436
1437/**
1438 * Calls a MMX assembly implementation taking two visible arguments.
1439 *
1440 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1441 * @param a0 The first extra argument.
1442 * @param a1 The second extra argument.
1443 */
1444#define IEM_MC_CALL_MMX_AIMPL_2(a_pfnAImpl, a0, a1) \
1445 do { \
1446 IEM_MC_PREPARE_FPU_USAGE(); \
1447 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1448 } while (0)
1449
1450/**
1451 * Calls a MMX assembly implementation taking three visible arguments.
1452 *
1453 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1454 * @param a0 The first extra argument.
1455 * @param a1 The second extra argument.
1456 * @param a2 The third extra argument.
1457 */
1458#define IEM_MC_CALL_MMX_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1459 do { \
1460 IEM_MC_PREPARE_FPU_USAGE(); \
1461 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1462 } while (0)
1463
1464
1465/**
1466 * Calls a SSE assembly implementation taking two visible arguments.
1467 *
1468 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1469 * @param a0 The first extra argument.
1470 * @param a1 The second extra argument.
1471 */
1472#define IEM_MC_CALL_SSE_AIMPL_2(a_pfnAImpl, a0, a1) \
1473 do { \
1474 IEM_MC_PREPARE_SSE_USAGE(); \
1475 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1476 } while (0)
1477
1478/**
1479 * Calls a SSE assembly implementation taking three visible arguments.
1480 *
1481 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1482 * @param a0 The first extra argument.
1483 * @param a1 The second extra argument.
1484 * @param a2 The third extra argument.
1485 */
1486#define IEM_MC_CALL_SSE_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1487 do { \
1488 IEM_MC_PREPARE_SSE_USAGE(); \
1489 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1490 } while (0)
1491
1492
1493/** Declares implicit arguments for IEM_MC_CALL_AVX_AIMPL_2,
1494 * IEM_MC_CALL_AVX_AIMPL_3, IEM_MC_CALL_AVX_AIMPL_4, ... */
1495#define IEM_MC_IMPLICIT_AVX_AIMPL_ARGS() \
1496 IEM_MC_ARG_CONST(PX86XSAVEAREA, pXState, &pVCpu->cpum.GstCtx.XState, 0)
1497
1498/**
1499 * Calls a AVX assembly implementation taking two visible arguments.
1500 *
1501 * There is one implicit zero'th argument, a pointer to the extended state.
1502 *
1503 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1504 * @param a1 The first extra argument.
1505 * @param a2 The second extra argument.
1506 */
1507#define IEM_MC_CALL_AVX_AIMPL_2(a_pfnAImpl, a1, a2) \
1508 do { \
1509 IEM_MC_PREPARE_AVX_USAGE(); \
1510 a_pfnAImpl(pXState, (a1), (a2)); \
1511 } while (0)
1512
1513/**
1514 * Calls a AVX assembly implementation taking three visible arguments.
1515 *
1516 * There is one implicit zero'th argument, a pointer to the extended state.
1517 *
1518 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1519 * @param a1 The first extra argument.
1520 * @param a2 The second extra argument.
1521 * @param a3 The third extra argument.
1522 */
1523#define IEM_MC_CALL_AVX_AIMPL_3(a_pfnAImpl, a1, a2, a3) \
1524 do { \
1525 IEM_MC_PREPARE_AVX_USAGE(); \
1526 a_pfnAImpl(pXState, (a1), (a2), (a3)); \
1527 } while (0)
1528
1529/** @note Not for IOPL or IF testing. */
1530#define IEM_MC_IF_EFL_BIT_SET(a_fBit) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) {
1531/** @note Not for IOPL or IF testing. */
1532#define IEM_MC_IF_EFL_BIT_NOT_SET(a_fBit) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit))) {
1533/** @note Not for IOPL or IF testing. */
1534#define IEM_MC_IF_EFL_ANY_BITS_SET(a_fBits) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBits)) {
1535/** @note Not for IOPL or IF testing. */
1536#define IEM_MC_IF_EFL_NO_BITS_SET(a_fBits) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBits))) {
1537/** @note Not for IOPL or IF testing. */
1538#define IEM_MC_IF_EFL_BITS_NE(a_fBit1, a_fBit2) \
1539 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1540 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1541/** @note Not for IOPL or IF testing. */
1542#define IEM_MC_IF_EFL_BITS_EQ(a_fBit1, a_fBit2) \
1543 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1544 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1545/** @note Not for IOPL or IF testing. */
1546#define IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(a_fBit, a_fBit1, a_fBit2) \
1547 if ( (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1548 || !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1549 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1550/** @note Not for IOPL or IF testing. */
1551#define IEM_MC_IF_EFL_BIT_NOT_SET_AND_BITS_EQ(a_fBit, a_fBit1, a_fBit2) \
1552 if ( !(pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1553 && !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1554 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1555#define IEM_MC_IF_CX_IS_NZ() if (pVCpu->cpum.GstCtx.cx != 0) {
1556#define IEM_MC_IF_ECX_IS_NZ() if (pVCpu->cpum.GstCtx.ecx != 0) {
1557#define IEM_MC_IF_RCX_IS_NZ() if (pVCpu->cpum.GstCtx.rcx != 0) {
1558/** @note Not for IOPL or IF testing. */
1559#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1560 if ( pVCpu->cpum.GstCtx.cx != 0 \
1561 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1562/** @note Not for IOPL or IF testing. */
1563#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1564 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1565 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1566/** @note Not for IOPL or IF testing. */
1567#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1568 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1569 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1570/** @note Not for IOPL or IF testing. */
1571#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1572 if ( pVCpu->cpum.GstCtx.cx != 0 \
1573 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1574/** @note Not for IOPL or IF testing. */
1575#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1576 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1577 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1578/** @note Not for IOPL or IF testing. */
1579#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1580 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1581 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1582#define IEM_MC_IF_LOCAL_IS_Z(a_Local) if ((a_Local) == 0) {
1583#define IEM_MC_IF_GREG_BIT_SET(a_iGReg, a_iBitNo) if (iemGRegFetchU64(pVCpu, (a_iGReg)) & RT_BIT_64(a_iBitNo)) {
1584
1585#define IEM_MC_REF_FPUREG(a_pr80Dst, a_iSt) \
1586 do { (a_pr80Dst) = &pVCpu->cpum.GstCtx.XState.x87.aRegs[X86_FSW_TOP_GET_ST(pVCpu->cpum.GstCtx.XState.x87.FSW, a_iSt)].r80; } while (0)
1587#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1588 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1589#define IEM_MC_IF_FPUREG_NOT_EMPTY(a_iSt) \
1590 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) == VINF_SUCCESS) {
1591#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1592 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1593#define IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(a_pr80Dst, a_iSt) \
1594 if (iemFpuStRegNotEmptyRef(pVCpu, (a_iSt), &(a_pr80Dst)) == VINF_SUCCESS) {
1595#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(a_pr80Dst0, a_iSt0, a_pr80Dst1, a_iSt1) \
1596 if (iemFpu2StRegsNotEmptyRef(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1), &(a_pr80Dst1)) == VINF_SUCCESS) {
1597#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(a_pr80Dst0, a_iSt0, a_iSt1) \
1598 if (iemFpu2StRegsNotEmptyRefFirst(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1)) == VINF_SUCCESS) {
1599#define IEM_MC_IF_FCW_IM() \
1600 if (pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_IM) {
1601#define IEM_MC_IF_MXCSR_XCPT_PENDING() \
1602 if (( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
1603 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) != 0) {
1604
1605#define IEM_MC_ELSE() } else {
1606#define IEM_MC_ENDIF() } do {} while (0)
1607
1608/** @} */
1609
1610#endif /* !VMM_INCLUDED_SRC_include_IEMMc_h */
1611
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