VirtualBox

source: vbox/trunk/src/VBox/VMM/include/IEMMc.h@ 101850

最後變更 在這個檔案從101850是 101850,由 vboxsync 提交於 17 月 前

VMM/IEM: Replaced all IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF use with IEM_MC_CLEAR_HIGH_GREG_U64 and removed the MC, as it forced argument variables to be used after IEM_MC_CALL_XXXX which made recompiling more complicated. bugref:10371
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1/* $Id: IEMMc.h 101850 2023-11-06 10:13:31Z vboxsync $ */
2/** @file
3 * IEM - Interpreted Execution Manager - IEM_MC_XXX.
4 */
5
6/*
7 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.alldomusa.eu.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_IEMMc_h
29#define VMM_INCLUDED_SRC_include_IEMMc_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34
35/** @name "Microcode" macros.
36 *
37 * The idea is that we should be able to use the same code to interpret
38 * instructions as well as recompiler instructions. Thus this obfuscation.
39 *
40 * @{
41 */
42
43#define IEM_MC_BEGIN(a_cArgs, a_cLocals, a_fMcFlags, a_fCImplFlags) {
44#define IEM_MC_END() }
45
46/** Internal macro. */
47#define IEM_MC_RETURN_ON_FAILURE(a_Expr) \
48 do \
49 { \
50 VBOXSTRICTRC rcStrict2 = a_Expr; \
51 if (rcStrict2 == VINF_SUCCESS) \
52 { /* likely */ } \
53 else \
54 return rcStrict2; \
55 } while (0)
56
57
58/** Advances RIP, finishes the instruction and returns.
59 * This may include raising debug exceptions and such. */
60#define IEM_MC_ADVANCE_RIP_AND_FINISH() return iemRegAddToRipAndFinishingClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
61/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
62#define IEM_MC_REL_JMP_S8_AND_FINISH(a_i8) \
63 return iemRegRipRelativeJumpS8AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i8), pVCpu->iem.s.enmEffOpSize)
64/** Sets RIP (may trigger \#GP), finishes the instruction and returns.
65 * @note only usable in 16-bit op size mode. */
66#define IEM_MC_REL_JMP_S16_AND_FINISH(a_i16) \
67 return iemRegRipRelativeJumpS16AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i16))
68/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
69#define IEM_MC_REL_JMP_S32_AND_FINISH(a_i32) \
70 return iemRegRipRelativeJumpS32AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i32), pVCpu->iem.s.enmEffOpSize)
71/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
72#define IEM_MC_SET_RIP_U16_AND_FINISH(a_u16NewIP) return iemRegRipJumpU16AndFinishClearningRF((pVCpu), (a_u16NewIP))
73/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
74#define IEM_MC_SET_RIP_U32_AND_FINISH(a_u32NewIP) return iemRegRipJumpU32AndFinishClearningRF((pVCpu), (a_u32NewIP))
75/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
76#define IEM_MC_SET_RIP_U64_AND_FINISH(a_u64NewIP) return iemRegRipJumpU64AndFinishClearningRF((pVCpu), (a_u64NewIP))
77
78#define IEM_MC_RAISE_DIVIDE_ERROR() return iemRaiseDivideError(pVCpu)
79#define IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() \
80 do { \
81 if (RT_LIKELY(!(pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS)))) \
82 { /* probable */ } \
83 else return iemRaiseDeviceNotAvailable(pVCpu); \
84 } while (0)
85#define IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() \
86 do { \
87 if (RT_LIKELY(!((pVCpu->cpum.GstCtx.cr0 & (X86_CR0_MP | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_TS)))) \
88 { /* probable */ } \
89 else return iemRaiseDeviceNotAvailable(pVCpu); \
90 } while (0)
91#define IEM_MC_MAYBE_RAISE_FPU_XCPT() \
92 do { \
93 if (RT_LIKELY(!(pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES))) \
94 { /* probable */ } \
95 else return iemRaiseMathFault(pVCpu); \
96 } while (0)
97#define IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() \
98 do { \
99 /* Since none of the bits we compare from XCR0, CR4 and CR0 overlap, it can \
100 be reduced to a single compare branch in the more probably code path. */ \
101 if (RT_LIKELY( ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) \
102 | (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE) \
103 | (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS)) \
104 == (XSAVE_C_YMM | XSAVE_C_SSE | X86_CR4_OSXSAVE))) \
105 { /* probable */ } \
106 else if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
107 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE)) \
108 return iemRaiseUndefinedOpcode(pVCpu); \
109 else \
110 return iemRaiseDeviceNotAvailable(pVCpu); \
111 } while (0)
112AssertCompile(!((XSAVE_C_YMM | XSAVE_C_SSE) & X86_CR4_OSXSAVE));
113AssertCompile(!((XSAVE_C_YMM | XSAVE_C_SSE) & X86_CR0_TS));
114AssertCompile(!(X86_CR4_OSXSAVE & X86_CR0_TS));
115#define IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() \
116 do { \
117 /* Since the CR4 and CR0 bits doesn't overlap, it can be reduced to a
118 single compare branch in the more probable code path. */ \
119 if (RT_LIKELY( ( (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS)) \
120 | (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \
121 == X86_CR4_OSFXSR)) \
122 { /* likely */ } \
123 else if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
124 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \
125 return iemRaiseUndefinedOpcode(pVCpu); \
126 else \
127 return iemRaiseDeviceNotAvailable(pVCpu); \
128 } while (0)
129AssertCompile(!((X86_CR0_EM | X86_CR0_TS) & X86_CR4_OSFXSR));
130#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT() \
131 do { \
132 /* Since the two CR0 bits doesn't overlap with FSW.ES, this can be reduced to a
133 single compare branch in the more probable code path. */ \
134 if (RT_LIKELY(!( (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS)) \
135 | (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES)))) \
136 { /* probable */ } \
137 else if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
138 return iemRaiseUndefinedOpcode(pVCpu); \
139 else if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
140 return iemRaiseDeviceNotAvailable(pVCpu); \
141 else \
142 return iemRaiseMathFault(pVCpu); \
143 } while (0)
144AssertCompile(!((X86_CR0_EM | X86_CR0_TS) & X86_FSW_ES));
145/** @todo recomp: this one is slightly problematic as the recompiler doesn't
146 * count the CPL into the TB key. However it is safe enough for now, as
147 * it calls iemRaiseGeneralProtectionFault0 directly so no calls will be
148 * emitted for it. */
149#define IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO() \
150 do { \
151 if (RT_LIKELY(IEM_GET_CPL(pVCpu) == 0)) { /* probable */ } \
152 else return iemRaiseGeneralProtectionFault0(pVCpu); \
153 } while (0)
154#define IEM_MC_RAISE_GP0_IF_EFF_ADDR_UNALIGNED(a_EffAddr, a_cbAlign) \
155 do { \
156 if (!((a_EffAddr) & ((a_cbAlign) - 1))) { /* likely */ } \
157 else return iemRaiseGeneralProtectionFault0(pVCpu); \
158 } while (0)
159#define IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT() \
160 do { \
161 if (RT_LIKELY( ((pVCpu->cpum.GstCtx.cr4 & X86_CR4_FSGSBASE) | IEM_GET_CPU_MODE(pVCpu)) \
162 == (X86_CR4_FSGSBASE | IEMMODE_64BIT))) \
163 { /* probable */ } \
164 else return iemRaiseUndefinedOpcode(pVCpu); \
165 } while (0)
166AssertCompile(X86_CR4_FSGSBASE > UINT8_MAX);
167#define IEM_MC_MAYBE_RAISE_NON_CANONICAL_ADDR_GP0(a_u64Addr) \
168 do { \
169 if (RT_LIKELY(IEM_IS_CANONICAL(a_u64Addr))) { /* likely */ } \
170 else return iemRaiseGeneralProtectionFault0(pVCpu); \
171 } while (0)
172#define IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
173 do { \
174 if (RT_LIKELY(( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
175 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) == 0)) \
176 { /* probable */ } \
177 else \
178 { \
179 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT) \
180 return iemRaiseSimdFpException(pVCpu); \
181 return iemRaiseUndefinedOpcode(pVCpu); \
182 } \
183 } while (0)
184#define IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
185 do { \
186 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT)\
187 return iemRaiseSimdFpException(pVCpu); \
188 return iemRaiseUndefinedOpcode(pVCpu); \
189 } while (0)
190
191
192#define IEM_MC_LOCAL(a_Type, a_Name) a_Type a_Name
193#define IEM_MC_LOCAL_CONST(a_Type, a_Name, a_Value) a_Type const a_Name = (a_Value)
194#define IEM_MC_REF_LOCAL(a_pRefArg, a_Local) (a_pRefArg) = &(a_Local)
195#define IEM_MC_ARG(a_Type, a_Name, a_iArg) a_Type a_Name
196#define IEM_MC_ARG_CONST(a_Type, a_Name, a_Value, a_iArg) a_Type const a_Name = (a_Value)
197#define IEM_MC_ARG_LOCAL_REF(a_Type, a_Name, a_Local, a_iArg) a_Type const a_Name = &(a_Local)
198/** @note IEMAllInstPython.py duplicates the expansion. */
199#define IEM_MC_ARG_LOCAL_EFLAGS(a_pName, a_Name, a_iArg) \
200 uint32_t a_Name; \
201 uint32_t *a_pName = &a_Name
202#define IEM_MC_COMMIT_EFLAGS(a_EFlags) \
203 do { pVCpu->cpum.GstCtx.eflags.u = (a_EFlags); Assert(pVCpu->cpum.GstCtx.eflags.u & X86_EFL_1); } while (0)
204
205#define IEM_MC_ASSIGN(a_VarOrArg, a_CVariableOrConst) (a_VarOrArg) = (a_CVariableOrConst)
206#define IEM_MC_ASSIGN_TO_SMALLER IEM_MC_ASSIGN
207#define IEM_MC_ASSIGN_U8_SX_U64(a_u64VarOrArg, a_u8CVariableOrConst) \
208 (a_u64VarOrArg) = (int8_t)(a_u8CVariableOrConst)
209#define IEM_MC_ASSIGN_U32_SX_U64(a_u64VarOrArg, a_u32CVariableOrConst) \
210 (a_u64VarOrArg) = (int32_t)(a_u32CVariableOrConst)
211
212#define IEM_MC_FETCH_GREG_U8(a_u8Dst, a_iGReg) (a_u8Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
213#define IEM_MC_FETCH_GREG_U8_ZX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
214#define IEM_MC_FETCH_GREG_U8_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
215#define IEM_MC_FETCH_GREG_U8_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
216#define IEM_MC_FETCH_GREG_U8_SX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
217#define IEM_MC_FETCH_GREG_U8_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
218#define IEM_MC_FETCH_GREG_U8_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
219#define IEM_MC_FETCH_GREG_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
220#define IEM_MC_FETCH_GREG_U16_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
221#define IEM_MC_FETCH_GREG_U16_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
222#define IEM_MC_FETCH_GREG_U16_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
223#define IEM_MC_FETCH_GREG_U16_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
224#define IEM_MC_FETCH_GREG_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
225#define IEM_MC_FETCH_GREG_U32_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
226#define IEM_MC_FETCH_GREG_U32_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int32_t)iemGRegFetchU32(pVCpu, (a_iGReg))
227#define IEM_MC_FETCH_GREG_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU64(pVCpu, (a_iGReg))
228#define IEM_MC_FETCH_GREG_U64_ZX_U64 IEM_MC_FETCH_GREG_U64
229#define IEM_MC_FETCH_SREG_U16(a_u16Dst, a_iSReg) do { \
230 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
231 (a_u16Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
232 } while (0)
233#define IEM_MC_FETCH_SREG_ZX_U32(a_u32Dst, a_iSReg) do { \
234 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
235 (a_u32Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
236 } while (0)
237#define IEM_MC_FETCH_SREG_ZX_U64(a_u64Dst, a_iSReg) do { \
238 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
239 (a_u64Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
240 } while (0)
241/** @todo IEM_MC_FETCH_SREG_BASE_U64 & IEM_MC_FETCH_SREG_BASE_U32 probably aren't worth it... */
242#define IEM_MC_FETCH_SREG_BASE_U64(a_u64Dst, a_iSReg) do { \
243 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
244 (a_u64Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
245 } while (0)
246#define IEM_MC_FETCH_SREG_BASE_U32(a_u32Dst, a_iSReg) do { \
247 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
248 (a_u32Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
249 } while (0)
250/** @note Not for IOPL or IF testing or modification. */
251#define IEM_MC_FETCH_EFLAGS(a_EFlags) (a_EFlags) = pVCpu->cpum.GstCtx.eflags.u
252#define IEM_MC_FETCH_EFLAGS_U8(a_EFlags) (a_EFlags) = (uint8_t)pVCpu->cpum.GstCtx.eflags.u
253#define IEM_MC_FETCH_FSW(a_u16Fsw) (a_u16Fsw) = pVCpu->cpum.GstCtx.XState.x87.FSW
254#define IEM_MC_FETCH_FCW(a_u16Fcw) (a_u16Fcw) = pVCpu->cpum.GstCtx.XState.x87.FCW
255
256#define IEM_MC_STORE_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) = (a_u8Value)
257#define IEM_MC_STORE_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) = (a_u16Value)
258#define IEM_MC_STORE_GREG_U32(a_iGReg, a_u32Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (uint32_t)(a_u32Value) /* clear high bits. */
259#define IEM_MC_STORE_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (a_u64Value)
260#define IEM_MC_STORE_GREG_I64(a_iGReg, a_i64Value) *iemGRegRefI64(pVCpu, (a_iGReg)) = (a_i64Value)
261#define IEM_MC_STORE_GREG_U8_CONST IEM_MC_STORE_GREG_U8
262#define IEM_MC_STORE_GREG_U16_CONST IEM_MC_STORE_GREG_U16
263#define IEM_MC_STORE_GREG_U32_CONST IEM_MC_STORE_GREG_U32
264#define IEM_MC_STORE_GREG_U64_CONST IEM_MC_STORE_GREG_U64
265#define IEM_MC_CLEAR_HIGH_GREG_U64(a_iGReg) *iemGRegRefU64(pVCpu, (a_iGReg)) &= UINT32_MAX
266/** @todo IEM_MC_STORE_SREG_BASE_U64 & IEM_MC_STORE_SREG_BASE_U32 aren't worth it... */
267#define IEM_MC_STORE_SREG_BASE_U64(a_iSReg, a_u64Value) do { \
268 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
269 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (a_u64Value); \
270 } while (0)
271#define IEM_MC_STORE_SREG_BASE_U32(a_iSReg, a_u32Value) do { \
272 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
273 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (uint32_t)(a_u32Value); /* clear high bits. */ \
274 } while (0)
275#define IEM_MC_STORE_FPUREG_R80_SRC_REF(a_iSt, a_pr80Src) \
276 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[a_iSt].r80 = *(a_pr80Src); } while (0)
277
278
279#define IEM_MC_REF_GREG_U8(a_pu8Dst, a_iGReg) (a_pu8Dst) = iemGRegRefU8( pVCpu, (a_iGReg))
280#define IEM_MC_REF_GREG_U8_CONST(a_pu8Dst, a_iGReg) (a_pu8Dst) = (uint8_t const *)iemGRegRefU8( pVCpu, (a_iGReg))
281#define IEM_MC_REF_GREG_U16(a_pu16Dst, a_iGReg) (a_pu16Dst) = iemGRegRefU16(pVCpu, (a_iGReg))
282#define IEM_MC_REF_GREG_U16_CONST(a_pu16Dst, a_iGReg) (a_pu16Dst) = (uint16_t const *)iemGRegRefU16(pVCpu, (a_iGReg))
283/** @todo User of IEM_MC_REF_GREG_U32 needs to clear the high bits on commit.
284 * Use IEM_MC_CLEAR_HIGH_GREG_U64! */
285#define IEM_MC_REF_GREG_U32(a_pu32Dst, a_iGReg) (a_pu32Dst) = iemGRegRefU32(pVCpu, (a_iGReg))
286#define IEM_MC_REF_GREG_U32_CONST(a_pu32Dst, a_iGReg) (a_pu32Dst) = (uint32_t const *)iemGRegRefU32(pVCpu, (a_iGReg))
287#define IEM_MC_REF_GREG_I32(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t *)iemGRegRefU32(pVCpu, (a_iGReg))
288#define IEM_MC_REF_GREG_I32_CONST(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t const *)iemGRegRefU32(pVCpu, (a_iGReg))
289#define IEM_MC_REF_GREG_U64(a_pu64Dst, a_iGReg) (a_pu64Dst) = iemGRegRefU64(pVCpu, (a_iGReg))
290#define IEM_MC_REF_GREG_U64_CONST(a_pu64Dst, a_iGReg) (a_pu64Dst) = (uint64_t const *)iemGRegRefU64(pVCpu, (a_iGReg))
291#define IEM_MC_REF_GREG_I64(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t *)iemGRegRefU64(pVCpu, (a_iGReg))
292#define IEM_MC_REF_GREG_I64_CONST(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t const *)iemGRegRefU64(pVCpu, (a_iGReg))
293/** @note Not for IOPL or IF testing or modification.
294 * @note Must preserve any undefined bits, see CPUMX86EFLAGS! */
295#define IEM_MC_REF_EFLAGS(a_pEFlags) (a_pEFlags) = &pVCpu->cpum.GstCtx.eflags.uBoth
296#define IEM_MC_REF_MXCSR(a_pfMxcsr) (a_pfMxcsr) = &pVCpu->cpum.GstCtx.XState.x87.MXCSR
297
298#define IEM_MC_ADD_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) += (a_u16Value)
299#define IEM_MC_ADD_GREG_U32(a_iGReg, a_u32Value) \
300 do { \
301 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
302 *pu32Reg += (a_u32Value); \
303 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
304 } while (0)
305#define IEM_MC_ADD_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) += (a_u64Value)
306
307#define IEM_MC_SUB_GREG_U16(a_iGReg, a_u8Const) *iemGRegRefU16(pVCpu, (a_iGReg)) -= (a_u8Const)
308#define IEM_MC_SUB_GREG_U32(a_iGReg, a_u8Const) \
309 do { \
310 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
311 *pu32Reg -= (a_u8Const); \
312 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
313 } while (0)
314#define IEM_MC_SUB_GREG_U64(a_iGReg, a_u8Const) *iemGRegRefU64(pVCpu, (a_iGReg)) -= (a_u8Const)
315#define IEM_MC_SUB_LOCAL_U16(a_u16Value, a_u16Const) do { (a_u16Value) -= a_u16Const; } while (0)
316
317#define IEM_MC_ADD_GREG_U8_TO_LOCAL(a_u8Value, a_iGReg) do { (a_u8Value) += iemGRegFetchU8( pVCpu, (a_iGReg)); } while (0)
318#define IEM_MC_ADD_GREG_U16_TO_LOCAL(a_u16Value, a_iGReg) do { (a_u16Value) += iemGRegFetchU16(pVCpu, (a_iGReg)); } while (0)
319#define IEM_MC_ADD_GREG_U32_TO_LOCAL(a_u32Value, a_iGReg) do { (a_u32Value) += iemGRegFetchU32(pVCpu, (a_iGReg)); } while (0)
320#define IEM_MC_ADD_GREG_U64_TO_LOCAL(a_u64Value, a_iGReg) do { (a_u64Value) += iemGRegFetchU64(pVCpu, (a_iGReg)); } while (0)
321#define IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR(a_EffAddr, a_i16) do { (a_EffAddr) += (a_i16); } while (0)
322#define IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR(a_EffAddr, a_i32) do { (a_EffAddr) += (a_i32); } while (0)
323#define IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR(a_EffAddr, a_i64) do { (a_EffAddr) += (a_i64); } while (0)
324
325#define IEM_MC_AND_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) &= (a_u8Mask); } while (0)
326#define IEM_MC_AND_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) &= (a_u16Mask); } while (0)
327#define IEM_MC_AND_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
328#define IEM_MC_AND_LOCAL_U64(a_u64Local, a_u64Mask) do { (a_u64Local) &= (a_u64Mask); } while (0)
329
330#define IEM_MC_AND_ARG_U16(a_u16Arg, a_u16Mask) do { (a_u16Arg) &= (a_u16Mask); } while (0)
331#define IEM_MC_AND_ARG_U32(a_u32Arg, a_u32Mask) do { (a_u32Arg) &= (a_u32Mask); } while (0)
332#define IEM_MC_AND_ARG_U64(a_u64Arg, a_u64Mask) do { (a_u64Arg) &= (a_u64Mask); } while (0)
333
334#define IEM_MC_OR_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) |= (a_u8Mask); } while (0)
335#define IEM_MC_OR_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) |= (a_u16Mask); } while (0)
336#define IEM_MC_OR_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
337
338#define IEM_MC_SAR_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) >>= (a_cShift); } while (0)
339#define IEM_MC_SAR_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) >>= (a_cShift); } while (0)
340#define IEM_MC_SAR_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) >>= (a_cShift); } while (0)
341
342#define IEM_MC_SHR_LOCAL_U8(a_u8Local, a_cShift) do { (a_u8Local) >>= (a_cShift); } while (0)
343
344#define IEM_MC_SHL_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) <<= (a_cShift); } while (0)
345#define IEM_MC_SHL_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) <<= (a_cShift); } while (0)
346#define IEM_MC_SHL_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) <<= (a_cShift); } while (0)
347
348#define IEM_MC_AND_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
349
350#define IEM_MC_OR_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
351
352#define IEM_MC_AND_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) &= (a_u8Value)
353#define IEM_MC_AND_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) &= (a_u16Value)
354#define IEM_MC_AND_GREG_U32(a_iGReg, a_u32Value) \
355 do { \
356 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
357 *pu32Reg &= (a_u32Value); \
358 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
359 } while (0)
360#define IEM_MC_AND_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) &= (a_u64Value)
361
362#define IEM_MC_OR_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) |= (a_u8Value)
363#define IEM_MC_OR_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) |= (a_u16Value)
364#define IEM_MC_OR_GREG_U32(a_iGReg, a_u32Value) \
365 do { \
366 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
367 *pu32Reg |= (a_u32Value); \
368 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
369 } while (0)
370#define IEM_MC_OR_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) |= (a_u64Value)
371
372#define IEM_MC_BSWAP_LOCAL_U16(a_u16Local) (a_u16Local) = RT_BSWAP_U16((a_u16Local));
373#define IEM_MC_BSWAP_LOCAL_U32(a_u32Local) (a_u32Local) = RT_BSWAP_U32((a_u32Local));
374#define IEM_MC_BSWAP_LOCAL_U64(a_u64Local) (a_u64Local) = RT_BSWAP_U64((a_u64Local));
375
376/** @note Not for IOPL or IF modification. */
377#define IEM_MC_SET_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u |= (a_fBit); } while (0)
378/** @note Not for IOPL or IF modification. */
379#define IEM_MC_CLEAR_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u &= ~(a_fBit); } while (0)
380/** @note Not for IOPL or IF modification. */
381#define IEM_MC_FLIP_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u ^= (a_fBit); } while (0)
382
383#define IEM_MC_CLEAR_FSW_EX() do { pVCpu->cpum.GstCtx.XState.x87.FSW &= X86_FSW_C_MASK | X86_FSW_TOP_MASK; } while (0)
384
385/** Switches the FPU state to MMX mode (FSW.TOS=0, FTW=0) if necessary. */
386#define IEM_MC_FPU_TO_MMX_MODE() do { \
387 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
388 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
389 pVCpu->cpum.GstCtx.XState.x87.FTW = 0xff; \
390 } while (0)
391
392/** Switches the FPU state from MMX mode (FSW.TOS=0, FTW=0xffff). */
393#define IEM_MC_FPU_FROM_MMX_MODE() do { \
394 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
395 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
396 pVCpu->cpum.GstCtx.XState.x87.FTW = 0; \
397 } while (0)
398
399#define IEM_MC_FETCH_MREG_U64(a_u64Value, a_iMReg) \
400 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx; } while (0)
401#define IEM_MC_FETCH_MREG_U32(a_u32Value, a_iMReg) \
402 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[0]; } while (0)
403#define IEM_MC_STORE_MREG_U64(a_iMReg, a_u64Value) do { \
404 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (a_u64Value); \
405 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
406 } while (0)
407#define IEM_MC_STORE_MREG_U32_ZX_U64(a_iMReg, a_u32Value) do { \
408 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (uint32_t)(a_u32Value); \
409 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
410 } while (0)
411#define IEM_MC_REF_MREG_U64(a_pu64Dst, a_iMReg) /** @todo need to set high word to 0xffff on commit (see IEM_MC_STORE_MREG_U64) */ \
412 (a_pu64Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
413#define IEM_MC_REF_MREG_U64_CONST(a_pu64Dst, a_iMReg) \
414 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
415#define IEM_MC_REF_MREG_U32_CONST(a_pu32Dst, a_iMReg) \
416 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
417#define IEM_MC_MODIFIED_MREG(a_iMReg) \
418 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; } while (0)
419#define IEM_MC_MODIFIED_MREG_BY_REF(a_pu64Dst) \
420 do { ((uint32_t *)(a_pu64Dst))[2] = 0xffff; } while (0)
421
422#define IEM_MC_CLEAR_XREG_U32_MASK(a_iXReg, a_bMask) \
423 do { if ((a_bMask) & (1 << 0)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0] = 0; \
424 if ((a_bMask) & (1 << 1)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[1] = 0; \
425 if ((a_bMask) & (1 << 2)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[2] = 0; \
426 if ((a_bMask) & (1 << 3)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[3] = 0; \
427 } while (0)
428#define IEM_MC_FETCH_XREG_U128(a_u128Value, a_iXReg) \
429 do { (a_u128Value).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
430 (a_u128Value).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
431 } while (0)
432#define IEM_MC_FETCH_XREG_XMM(a_XmmValue, a_iXReg) \
433 do { (a_XmmValue).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
434 (a_XmmValue).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
435 } while (0)
436#define IEM_MC_FETCH_XREG_U64(a_u64Value, a_iXReg, a_iQWord) \
437 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQWord)]; } while (0)
438#define IEM_MC_FETCH_XREG_U32(a_u32Value, a_iXReg, a_iDWord) \
439 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDWord)]; } while (0)
440#define IEM_MC_FETCH_XREG_U16(a_u16Value, a_iXReg, a_iWord) \
441 do { (a_u16Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au16[(a_iWord)]; } while (0)
442#define IEM_MC_FETCH_XREG_U8( a_u8Value, a_iXReg, a_iByte) \
443 do { (a_u8Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au16[(a_iByte)]; } while (0)
444#define IEM_MC_STORE_XREG_U128(a_iXReg, a_u128Value) \
445 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u128Value).au64[0]; \
446 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u128Value).au64[1]; \
447 } while (0)
448#define IEM_MC_STORE_XREG_XMM(a_iXReg, a_XmmValue) \
449 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_XmmValue).au64[0]; \
450 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_XmmValue).au64[1]; \
451 } while (0)
452#define IEM_MC_STORE_XREG_XMM_U32(a_iXReg, a_iDword, a_XmmValue) \
453 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDword)] = (a_XmmValue).au32[(a_iDword)]; } while (0)
454#define IEM_MC_STORE_XREG_XMM_U64(a_iXReg, a_iQword, a_XmmValue) \
455 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQword)] = (a_XmmValue).au64[(a_iQword)]; } while (0)
456#define IEM_MC_STORE_XREG_U64(a_iXReg, a_iQword, a_u64Value) \
457 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQword)] = (a_u64Value); } while (0)
458#define IEM_MC_STORE_XREG_U32(a_iXReg, a_iDword, a_u32Value) \
459 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDword)] = (a_u32Value); } while (0)
460#define IEM_MC_STORE_XREG_U16(a_iXReg, a_iWord, a_u16Value) \
461 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iWord)] = (a_u16Value); } while (0)
462#define IEM_MC_STORE_XREG_U8(a_iXReg, a_iByte, a_u8Value) \
463 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iByte)] = (a_u8Value); } while (0)
464
465#define IEM_MC_STORE_XREG_U64_ZX_U128(a_iXReg, a_u64Value) \
466 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u64Value); \
467 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
468 } while (0)
469
470#define IEM_MC_STORE_XREG_U32_U128(a_iXReg, a_iDwDst, a_u128Value, a_iDwSrc) \
471 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDwDst)] = (a_u128Value).au32[(a_iDwSrc)]; } while (0)
472#define IEM_MC_STORE_XREG_R32(a_iXReg, a_r32Value) \
473 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0] = (a_r32Value); } while (0)
474#define IEM_MC_STORE_XREG_R64(a_iXReg, a_r64Value) \
475 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0] = (a_r64Value); } while (0)
476#define IEM_MC_STORE_XREG_U32_ZX_U128(a_iXReg, a_u32Value) \
477 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (uint32_t)(a_u32Value); \
478 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
479 } while (0)
480#define IEM_MC_STORE_XREG_HI_U64(a_iXReg, a_u64Value) \
481 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u64Value); } while (0)
482
483#define IEM_MC_BROADCAST_XREG_U8_ZX_VLMAX(a_iXRegDst, a_u8Src) \
484 do { uintptr_t const iXRegDstTmp = (a_iXRegDst); \
485 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[0] = (a_u8Src); \
486 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[1] = (a_u8Src); \
487 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[2] = (a_u8Src); \
488 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[3] = (a_u8Src); \
489 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[4] = (a_u8Src); \
490 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[5] = (a_u8Src); \
491 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[6] = (a_u8Src); \
492 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[7] = (a_u8Src); \
493 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[8] = (a_u8Src); \
494 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[9] = (a_u8Src); \
495 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[10] = (a_u8Src); \
496 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[11] = (a_u8Src); \
497 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[12] = (a_u8Src); \
498 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[13] = (a_u8Src); \
499 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[14] = (a_u8Src); \
500 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[15] = (a_u8Src); \
501 IEM_MC_CLEAR_YREG_128_UP(iXRegDstTmp); \
502 } while (0)
503#define IEM_MC_BROADCAST_XREG_U16_ZX_VLMAX(a_iXRegDst, a_u16Src) \
504 do { uintptr_t const iXRegDstTmp = (a_iXRegDst); \
505 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au16[0] = (a_u16Src); \
506 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au16[1] = (a_u16Src); \
507 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au16[2] = (a_u16Src); \
508 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au16[3] = (a_u16Src); \
509 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au16[4] = (a_u16Src); \
510 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au16[5] = (a_u16Src); \
511 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au16[6] = (a_u16Src); \
512 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au16[7] = (a_u16Src); \
513 IEM_MC_CLEAR_YREG_128_UP(iXRegDstTmp); \
514 } while (0)
515#define IEM_MC_BROADCAST_XREG_U32_ZX_VLMAX(a_iXRegDst, a_u32Src) \
516 do { uintptr_t const iXRegDstTmp = (a_iXRegDst); \
517 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au32[0] = (a_u32Src); \
518 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au32[1] = (a_u32Src); \
519 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au32[2] = (a_u32Src); \
520 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au32[3] = (a_u32Src); \
521 IEM_MC_CLEAR_YREG_128_UP(iXRegDstTmp); \
522 } while (0)
523#define IEM_MC_BROADCAST_XREG_U64_ZX_VLMAX(a_iXRegDst, a_u64Src) \
524 do { uintptr_t const iXRegDstTmp = (a_iXRegDst); \
525 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au64[0] = (a_u64Src); \
526 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au64[1] = (a_u64Src); \
527 IEM_MC_CLEAR_YREG_128_UP(iXRegDstTmp); \
528 } while (0)
529
530#define IEM_MC_REF_XREG_U128(a_pu128Dst, a_iXReg) \
531 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
532#define IEM_MC_REF_XREG_U128_CONST(a_pu128Dst, a_iXReg) \
533 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
534#define IEM_MC_REF_XREG_XMM_CONST(a_pXmmDst, a_iXReg) \
535 (a_pXmmDst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)])
536#define IEM_MC_REF_XREG_U32_CONST(a_pu32Dst, a_iXReg) \
537 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0])
538#define IEM_MC_REF_XREG_U64_CONST(a_pu64Dst, a_iXReg) \
539 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0])
540#define IEM_MC_REF_XREG_R32_CONST(a_pr32Dst, a_iXReg) \
541 (a_pr32Dst) = ((RTFLOAT32U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0])
542#define IEM_MC_REF_XREG_R64_CONST(a_pr64Dst, a_iXReg) \
543 (a_pr64Dst) = ((RTFLOAT64U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0])
544#define IEM_MC_COPY_XREG_U128(a_iXRegDst, a_iXRegSrc) \
545 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[0] \
546 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[0]; \
547 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[1] \
548 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[1]; \
549 } while (0)
550
551#define IEM_MC_FETCH_YREG_U32(a_u32Dst, a_iYRegSrc) \
552 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
553 (a_u32Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au32[0]; \
554 } while (0)
555#define IEM_MC_FETCH_YREG_U64(a_u64Dst, a_iYRegSrc) \
556 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
557 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
558 } while (0)
559#define IEM_MC_FETCH_YREG_2ND_U64(a_u64Dst, a_iYRegSrc) \
560 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
561 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
562 } while (0)
563#define IEM_MC_FETCH_YREG_U128(a_u128Dst, a_iYRegSrc) \
564 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
565 (a_u128Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
566 (a_u128Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
567 } while (0)
568#define IEM_MC_FETCH_YREG_U256(a_u256Dst, a_iYRegSrc) \
569 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
570 (a_u256Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
571 (a_u256Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
572 (a_u256Dst).au64[2] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
573 (a_u256Dst).au64[3] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
574 } while (0)
575
576#define IEM_MC_STORE_YREG_U128(a_iYRegDst, a_iDQword, a_u128Value) \
577 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
578 if ((a_iDQword) == 0) \
579 { \
580 pVCpu->cpum.GstCtx.XState.x87.aXMM[(iYRegDstTmp)].au64[0] = (a_u128Value).au64[0]; \
581 pVCpu->cpum.GstCtx.XState.x87.aXMM[(iYRegDstTmp)].au64[1] = (a_u128Value).au64[1]; \
582 } \
583 else \
584 { \
585 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[(iYRegDstTmp)].au64[0] = (a_u128Value).au64[0]; \
586 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[(iYRegDstTmp)].au64[1] = (a_u128Value).au64[1]; \
587 } \
588 } while (0)
589
590#define IEM_MC_INT_CLEAR_ZMM_256_UP(a_iXRegDst) do { /* For AVX512 and AVX1024 support. */ } while (0)
591#define IEM_MC_STORE_YREG_U32_ZX_VLMAX(a_iYRegDst, a_u32Src) \
592 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
593 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = (a_u32Src); \
594 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = 0; \
595 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
596 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
597 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
598 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
599 } while (0)
600#define IEM_MC_STORE_YREG_U64_ZX_VLMAX(a_iYRegDst, a_u64Src) \
601 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
602 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Src); \
603 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
604 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
605 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
606 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
607 } while (0)
608#define IEM_MC_STORE_YREG_U128_ZX_VLMAX(a_iYRegDst, a_u128Src) \
609 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
610 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u128Src).au64[0]; \
611 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u128Src).au64[1]; \
612 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
613 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
614 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
615 } while (0)
616#define IEM_MC_STORE_YREG_U256_ZX_VLMAX(a_iYRegDst, a_u256Src) \
617 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
618 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u256Src).au64[0]; \
619 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u256Src).au64[1]; \
620 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = (a_u256Src).au64[2]; \
621 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = (a_u256Src).au64[3]; \
622 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
623 } while (0)
624
625#define IEM_MC_BROADCAST_YREG_U8_ZX_VLMAX(a_iYRegDst, a_u8Src) \
626 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
627 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[0] = (a_u8Src); \
628 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[1] = (a_u8Src); \
629 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[2] = (a_u8Src); \
630 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[3] = (a_u8Src); \
631 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[4] = (a_u8Src); \
632 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[5] = (a_u8Src); \
633 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[6] = (a_u8Src); \
634 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[7] = (a_u8Src); \
635 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[8] = (a_u8Src); \
636 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[9] = (a_u8Src); \
637 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[10] = (a_u8Src); \
638 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[11] = (a_u8Src); \
639 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[12] = (a_u8Src); \
640 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[13] = (a_u8Src); \
641 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[14] = (a_u8Src); \
642 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[15] = (a_u8Src); \
643 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[0] = (a_u8Src); \
644 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[1] = (a_u8Src); \
645 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[2] = (a_u8Src); \
646 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[3] = (a_u8Src); \
647 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[4] = (a_u8Src); \
648 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[5] = (a_u8Src); \
649 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[6] = (a_u8Src); \
650 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[7] = (a_u8Src); \
651 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[8] = (a_u8Src); \
652 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[9] = (a_u8Src); \
653 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[10] = (a_u8Src); \
654 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[11] = (a_u8Src); \
655 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[12] = (a_u8Src); \
656 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[13] = (a_u8Src); \
657 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[14] = (a_u8Src); \
658 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[15] = (a_u8Src); \
659 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
660 } while (0)
661#define IEM_MC_BROADCAST_YREG_U16_ZX_VLMAX(a_iYRegDst, a_u16Src) \
662 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
663 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au16[0] = (a_u16Src); \
664 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au16[1] = (a_u16Src); \
665 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au16[2] = (a_u16Src); \
666 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au16[3] = (a_u16Src); \
667 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au16[4] = (a_u16Src); \
668 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au16[5] = (a_u16Src); \
669 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au16[6] = (a_u16Src); \
670 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au16[7] = (a_u16Src); \
671 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au16[0] = (a_u16Src); \
672 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au16[1] = (a_u16Src); \
673 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au16[2] = (a_u16Src); \
674 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au16[3] = (a_u16Src); \
675 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au16[4] = (a_u16Src); \
676 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au16[5] = (a_u16Src); \
677 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au16[6] = (a_u16Src); \
678 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au16[7] = (a_u16Src); \
679 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
680 } while (0)
681#define IEM_MC_BROADCAST_YREG_U32_ZX_VLMAX(a_iYRegDst, a_u32Src) \
682 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
683 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = (a_u32Src); \
684 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = (a_u32Src); \
685 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[2] = (a_u32Src); \
686 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[3] = (a_u32Src); \
687 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au32[0] = (a_u32Src); \
688 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au32[1] = (a_u32Src); \
689 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au32[2] = (a_u32Src); \
690 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au32[3] = (a_u32Src); \
691 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
692 } while (0)
693#define IEM_MC_BROADCAST_YREG_U64_ZX_VLMAX(a_iYRegDst, a_u64Src) \
694 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
695 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Src); \
696 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u64Src); \
697 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = (a_u64Src); \
698 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = (a_u64Src); \
699 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
700 } while (0)
701#define IEM_MC_BROADCAST_YREG_U128_ZX_VLMAX(a_iYRegDst, a_u128Src) \
702 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
703 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u128Src).au64[0]; \
704 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u128Src).au64[1]; \
705 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = (a_u128Src).au64[0]; \
706 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = (a_u128Src).au64[1]; \
707 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
708 } while (0)
709
710#define IEM_MC_REF_YREG_U128(a_pu128Dst, a_iYReg) \
711 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
712#define IEM_MC_REF_YREG_U128_CONST(a_pu128Dst, a_iYReg) \
713 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
714#define IEM_MC_REF_YREG_U64_CONST(a_pu64Dst, a_iYReg) \
715 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].au64[0])
716#define IEM_MC_CLEAR_YREG_128_UP(a_iYReg) \
717 do { uintptr_t const iYRegTmp = (a_iYReg); \
718 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[0] = 0; \
719 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[1] = 0; \
720 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegTmp); \
721 } while (0)
722
723#define IEM_MC_COPY_YREG_U256_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
724 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
725 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
726 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
727 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
728 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
729 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
730 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
731 } while (0)
732#define IEM_MC_COPY_YREG_U128_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
733 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
734 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
735 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
736 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
737 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
738 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
739 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
740 } while (0)
741#define IEM_MC_COPY_YREG_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
742 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
743 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
744 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
745 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
746 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
747 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
748 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
749 } while (0)
750
751#define IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(a_iYRegDst, a_iYRegSrc32, a_iYRegSrcHx) \
752 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
753 uintptr_t const iYRegSrc32Tmp = (a_iYRegSrc32); \
754 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
755 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc32Tmp].au32[0]; \
756 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au32[1]; \
757 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
758 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
759 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
760 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
761 } while (0)
762#define IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) \
763 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
764 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
765 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
766 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
767 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
768 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
769 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
770 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
771 } while (0)
772#define IEM_MC_MERGE_YREG_U64LO_U64LO_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
773 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
774 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
775 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
776 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
777 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
778 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
779 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
780 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
781 } while (0)
782#define IEM_MC_MERGE_YREG_U64HI_U64HI_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
783 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
784 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
785 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
786 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[1]; \
787 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
788 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
789 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
790 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
791 } while (0)
792#define IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX(a_iYRegDst, a_iYRegSrcHx, a_u64Local) \
793 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
794 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
795 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
796 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u64Local); \
797 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
798 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
799 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
800 } while (0)
801#define IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX(a_iYRegDst, a_u64Local, a_iYRegSrcHx) \
802 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
803 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
804 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Local); \
805 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
806 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
807 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
808 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
809 } while (0)
810
811#ifndef IEM_WITH_SETJMP
812# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
813 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem)))
814# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
815 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem16)))
816# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
817 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem32)))
818#else
819# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
820 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
821# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
822 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem16)))
823# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
824 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem32)))
825
826# define IEM_MC_FETCH_MEM_FLAT_U8(a_u8Dst, a_GCPtrMem) \
827 ((a_u8Dst) = iemMemFlatFetchDataU8Jmp(pVCpu, (a_GCPtrMem)))
828# define IEM_MC_FETCH_MEM16_FLAT_U8(a_u8Dst, a_GCPtrMem16) \
829 ((a_u8Dst) = iemMemFlatFetchDataU8Jmp(pVCpu, (a_GCPtrMem16)))
830# define IEM_MC_FETCH_MEM32_FLAT_U8(a_u8Dst, a_GCPtrMem32) \
831 ((a_u8Dst) = iemMemFlatFetchDataU8Jmp(pVCpu, (a_GCPtrMem32)))
832#endif
833
834#ifndef IEM_WITH_SETJMP
835# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
836 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem)))
837# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
838 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
839# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
840 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, (uint16_t *)&(a_i16Dst), (a_iSeg), (a_GCPtrMem)))
841#else
842# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
843 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
844# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
845 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
846# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
847 ((a_i16Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
848
849# define IEM_MC_FETCH_MEM_FLAT_U16(a_u16Dst, a_GCPtrMem) \
850 ((a_u16Dst) = iemMemFlatFetchDataU16Jmp(pVCpu, (a_GCPtrMem)))
851# define IEM_MC_FETCH_MEM_FLAT_U16_DISP(a_u16Dst, a_GCPtrMem, a_offDisp) \
852 ((a_u16Dst) = iemMemFlatFetchDataU16Jmp(pVCpu, (a_GCPtrMem) + (a_offDisp)))
853# define IEM_MC_FETCH_MEM_FLAT_I16(a_i16Dst, a_GCPtrMem) \
854 ((a_i16Dst) = (int16_t)iemMemFlatFetchDataU16Jmp(pVCpu, (a_GCPtrMem)))
855#endif
856
857#ifndef IEM_WITH_SETJMP
858# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
859 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem)))
860# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
861 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
862# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
863 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, (uint32_t *)&(a_i32Dst), (a_iSeg), (a_GCPtrMem)))
864#else
865# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
866 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
867# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
868 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
869# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
870 ((a_i32Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
871
872# define IEM_MC_FETCH_MEM_FLAT_U32(a_u32Dst, a_GCPtrMem) \
873 ((a_u32Dst) = iemMemFlatFetchDataU32Jmp(pVCpu, (a_GCPtrMem)))
874# define IEM_MC_FETCH_MEM_FLAT_U32_DISP(a_u32Dst, a_GCPtrMem, a_offDisp) \
875 ((a_u32Dst) = iemMemFlatFetchDataU32Jmp(pVCpu, (a_GCPtrMem) + (a_offDisp)))
876# define IEM_MC_FETCH_MEM_FLAT_I32(a_i32Dst, a_GCPtrMem) \
877 ((a_i32Dst) = (int32_t)iemMemFlatFetchDataU32Jmp(pVCpu, (a_GCPtrMem)))
878#endif
879
880#ifdef SOME_UNUSED_FUNCTION
881# define IEM_MC_FETCH_MEM_S32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
882 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataS32SxU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
883#endif
884
885#ifndef IEM_WITH_SETJMP
886# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
887 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
888# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
889 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
890# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
891 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64AlignedU128(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
892# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
893 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, (uint64_t *)&(a_i64Dst), (a_iSeg), (a_GCPtrMem)))
894#else
895# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
896 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
897# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
898 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
899# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
900 ((a_u64Dst) = iemMemFetchDataU64AlignedU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
901# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
902 ((a_i64Dst) = (int64_t)iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
903
904# define IEM_MC_FETCH_MEM_FLAT_U64(a_u64Dst, a_GCPtrMem) \
905 ((a_u64Dst) = iemMemFlatFetchDataU64Jmp(pVCpu, (a_GCPtrMem)))
906# define IEM_MC_FETCH_MEM_FLAT_U64_DISP(a_u64Dst, a_GCPtrMem, a_offDisp) \
907 ((a_u64Dst) = iemMemFlatFetchDataU64Jmp(pVCpu, (a_GCPtrMem) + (a_offDisp)))
908# define IEM_MC_FETCH_MEM_FLAT_U64_ALIGN_U128(a_u64Dst, a_GCPtrMem) \
909 ((a_u64Dst) = iemMemFlatFetchDataU64AlignedU128Jmp(pVCpu, (a_GCPtrMem)))
910# define IEM_MC_FETCH_MEM_FLAT_I64(a_i64Dst, a_GCPtrMem) \
911 ((a_i64Dst) = (int64_t)iemMemFlatFetchDataU64Jmp(pVCpu, (a_GCPtrMem)))
912#endif
913
914#ifndef IEM_WITH_SETJMP
915# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
916 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_r32Dst).u, (a_iSeg), (a_GCPtrMem)))
917# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
918 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_r64Dst).u, (a_iSeg), (a_GCPtrMem)))
919# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
920 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataR80(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem)))
921# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
922 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataD80(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem)))
923#else
924# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
925 ((a_r32Dst).u = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
926# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
927 ((a_r64Dst).u = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
928# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
929 iemMemFetchDataR80Jmp(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem))
930# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
931 iemMemFetchDataD80Jmp(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem))
932
933# define IEM_MC_FETCH_MEM_FLAT_R32(a_r32Dst, a_GCPtrMem) \
934 ((a_r32Dst).u = iemMemFlatFetchDataU32Jmp(pVCpu, (a_GCPtrMem)))
935# define IEM_MC_FETCH_MEM_FLAT_R64(a_r64Dst, a_GCPtrMem) \
936 ((a_r64Dst).u = iemMemFlatFetchDataU64Jmp(pVCpu, (a_GCPtrMem)))
937# define IEM_MC_FETCH_MEM_FLAT_R80(a_r80Dst, a_GCPtrMem) \
938 iemMemFetchDataR80Jmp(pVCpu, &(a_r80Dst), UINT8_MAX, (a_GCPtrMem))
939# define IEM_MC_FETCH_MEM_FLAT_D80(a_d80Dst, a_GCPtrMem) \
940 iemMemFetchDataD80Jmp(pVCpu, &(a_d80Dst), UINT8_MAX, (a_GCPtrMem))
941#endif
942
943#ifndef IEM_WITH_SETJMP
944# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
945 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
946# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
947 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
948# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
949 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
950
951# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
952 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
953# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
954 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
955# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
956 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
957# define IEM_MC_FETCH_MEM_XMM_U32(a_XmmDst, a_iDWord, a_iSeg, a_GCPtrMem) \
958 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_XmmDst).au32[(a_iDWord)], (a_iSeg), (a_GCPtrMem)))
959# define IEM_MC_FETCH_MEM_XMM_U64(a_XmmDst, a_iQWord, a_iSeg, a_GCPtrMem) \
960 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_XmmDst).au64[(a_iQWord)], (a_iSeg), (a_GCPtrMem)))
961#else
962# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
963 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
964# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
965 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
966# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
967 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
968
969# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
970 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
971# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
972 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
973# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
974 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
975# define IEM_MC_FETCH_MEM_XMM_U32(a_XmmDst, a_iDWord, a_iSeg, a_GCPtrMem) \
976 (a_XmmDst).au32[(a_iDWord)] = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem))
977# define IEM_MC_FETCH_MEM_XMM_U64(a_XmmDst, a_iQWord, a_iSeg, a_GCPtrMem) \
978 (a_XmmDst).au64[(a_iQWord)] = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem))
979
980# define IEM_MC_FETCH_MEM_FLAT_U128(a_u128Dst, a_GCPtrMem) \
981 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), UINT8_MAX, (a_GCPtrMem))
982# define IEM_MC_FETCH_MEM_FLAT_U128_NO_AC(a_u128Dst, a_GCPtrMem) \
983 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), UINT8_MAX, (a_GCPtrMem))
984# define IEM_MC_FETCH_MEM_FLAT_U128_ALIGN_SSE(a_u128Dst, a_GCPtrMem) \
985 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_u128Dst), UINT8_MAX, (a_GCPtrMem))
986
987# define IEM_MC_FETCH_MEM_FLAT_XMM(a_XmmDst, a_GCPtrMem) \
988 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, UINT8_MAX, (a_GCPtrMem))
989# define IEM_MC_FETCH_MEM_FLAT_XMM_NO_AC(a_XmmDst, a_GCPtrMem) \
990 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, UINT8_MAX, (a_GCPtrMem))
991# define IEM_MC_FETCH_MEM_FLAT_XMM_ALIGN_SSE(a_XmmDst, a_GCPtrMem) \
992 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_XmmDst).uXmm, UINT8_MAX, (a_GCPtrMem))
993# define IEM_MC_FETCH_MEM_FLAT_XMM_U32(a_XmmDst, a_iDWord, a_GCPtrMem) \
994 (a_XmmDst).au32[(a_iDWord)] = iemMemFlatFetchDataU32Jmp(pVCpu, (a_GCPtrMem))
995# define IEM_MC_FETCH_MEM_FLAT_XMM_U64(a_XmmDst, a_iQWord, a_GCPtrMem) \
996 (a_XmmDst).au64[(a_iQWord)] = iemMemFetchDataU64Jmp(pVCpu, UINT8_MAX, (a_GCPtrMem))
997#endif
998
999#ifndef IEM_WITH_SETJMP
1000# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
1001 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
1002# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
1003 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
1004# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
1005 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
1006
1007# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
1008 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
1009# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
1010 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
1011# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
1012 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
1013#else
1014# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
1015 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
1016# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
1017 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
1018# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
1019 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
1020
1021# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
1022 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
1023# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
1024 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
1025# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
1026 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
1027
1028# define IEM_MC_FETCH_MEM_FLAT_U256(a_u256Dst, a_GCPtrMem) \
1029 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), UINT8_MAX, (a_GCPtrMem))
1030# define IEM_MC_FETCH_MEM_FLAT_U256_NO_AC(a_u256Dst, a_GCPtrMem) \
1031 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), UINT8_MAX, (a_GCPtrMem))
1032# define IEM_MC_FETCH_MEM_FLAT_U256_ALIGN_AVX(a_u256Dst, a_GCPtrMem) \
1033 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_u256Dst), UINT8_MAX, (a_GCPtrMem))
1034
1035# define IEM_MC_FETCH_MEM_FLAT_YMM(a_YmmDst, a_GCPtrMem) \
1036 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, UINT8_MAX, (a_GCPtrMem))
1037# define IEM_MC_FETCH_MEM_FLAT_YMM_NO_AC(a_YmmDst, a_GCPtrMem) \
1038 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, UINT8_MAX, (a_GCPtrMem))
1039# define IEM_MC_FETCH_MEM_FLAT_YMM_ALIGN_AVX(a_YmmDst, a_GCPtrMem) \
1040 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_YmmDst).ymm, UINT8_MAX, (a_GCPtrMem))
1041#endif
1042
1043
1044
1045#ifndef IEM_WITH_SETJMP
1046# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
1047 do { \
1048 uint8_t u8Tmp; \
1049 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
1050 (a_u16Dst) = u8Tmp; \
1051 } while (0)
1052# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
1053 do { \
1054 uint8_t u8Tmp; \
1055 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
1056 (a_u32Dst) = u8Tmp; \
1057 } while (0)
1058# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
1059 do { \
1060 uint8_t u8Tmp; \
1061 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
1062 (a_u64Dst) = u8Tmp; \
1063 } while (0)
1064# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
1065 do { \
1066 uint16_t u16Tmp; \
1067 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
1068 (a_u32Dst) = u16Tmp; \
1069 } while (0)
1070# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
1071 do { \
1072 uint16_t u16Tmp; \
1073 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
1074 (a_u64Dst) = u16Tmp; \
1075 } while (0)
1076# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
1077 do { \
1078 uint32_t u32Tmp; \
1079 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
1080 (a_u64Dst) = u32Tmp; \
1081 } while (0)
1082#else /* IEM_WITH_SETJMP */
1083# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
1084 ((a_u16Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1085# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
1086 ((a_u32Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1087# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
1088 ((a_u64Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1089# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
1090 ((a_u32Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1091# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
1092 ((a_u64Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1093# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
1094 ((a_u64Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1095
1096# define IEM_MC_FETCH_MEM_FLAT_U8_ZX_U16(a_u16Dst, a_GCPtrMem) \
1097 ((a_u16Dst) = iemMemFlatFetchDataU8Jmp(pVCpu, (a_GCPtrMem)))
1098# define IEM_MC_FETCH_MEM_FLAT_U8_ZX_U32(a_u32Dst, a_GCPtrMem) \
1099 ((a_u32Dst) = iemMemFlatFetchDataU8Jmp(pVCpu, (a_GCPtrMem)))
1100# define IEM_MC_FETCH_MEM_FLAT_U8_ZX_U64(a_u64Dst, a_GCPtrMem) \
1101 ((a_u64Dst) = iemMemFlatFetchDataU8Jmp(pVCpu, (a_GCPtrMem)))
1102# define IEM_MC_FETCH_MEM_FLAT_U16_ZX_U32(a_u32Dst, a_GCPtrMem) \
1103 ((a_u32Dst) = iemMemFlatFetchDataU16Jmp(pVCpu, (a_GCPtrMem)))
1104# define IEM_MC_FETCH_MEM_FLAT_U16_ZX_U64(a_u64Dst, a_GCPtrMem) \
1105 ((a_u64Dst) = iemMemFlatFetchDataU16Jmp(pVCpu, (a_GCPtrMem)))
1106# define IEM_MC_FETCH_MEM_FLAT_U32_ZX_U64(a_u64Dst, a_GCPtrMem) \
1107 ((a_u64Dst) = iemMemFlatFetchDataU32Jmp(pVCpu, (a_GCPtrMem)))
1108#endif /* IEM_WITH_SETJMP */
1109
1110#ifndef IEM_WITH_SETJMP
1111# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
1112 do { \
1113 uint8_t u8Tmp; \
1114 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
1115 (a_u16Dst) = (int8_t)u8Tmp; \
1116 } while (0)
1117# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
1118 do { \
1119 uint8_t u8Tmp; \
1120 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
1121 (a_u32Dst) = (int8_t)u8Tmp; \
1122 } while (0)
1123# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
1124 do { \
1125 uint8_t u8Tmp; \
1126 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
1127 (a_u64Dst) = (int8_t)u8Tmp; \
1128 } while (0)
1129# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
1130 do { \
1131 uint16_t u16Tmp; \
1132 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
1133 (a_u32Dst) = (int16_t)u16Tmp; \
1134 } while (0)
1135# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
1136 do { \
1137 uint16_t u16Tmp; \
1138 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
1139 (a_u64Dst) = (int16_t)u16Tmp; \
1140 } while (0)
1141# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
1142 do { \
1143 uint32_t u32Tmp; \
1144 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
1145 (a_u64Dst) = (int32_t)u32Tmp; \
1146 } while (0)
1147#else /* IEM_WITH_SETJMP */
1148# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
1149 ((a_u16Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1150# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
1151 ((a_u32Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1152# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
1153 ((a_u64Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1154# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
1155 ((a_u32Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1156# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
1157 ((a_u64Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1158# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
1159 ((a_u64Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1160
1161# define IEM_MC_FETCH_MEM_FLAT_U8_SX_U16(a_u16Dst, a_GCPtrMem) \
1162 ((a_u16Dst) = (int8_t)iemMemFlatFetchDataU8Jmp(pVCpu, (a_GCPtrMem)))
1163# define IEM_MC_FETCH_MEM_FLAT_U8_SX_U32(a_u32Dst, a_GCPtrMem) \
1164 ((a_u32Dst) = (int8_t)iemMemFlatFetchDataU8Jmp(pVCpu, (a_GCPtrMem)))
1165# define IEM_MC_FETCH_MEM_FLAT_U8_SX_U64(a_u64Dst, a_GCPtrMem) \
1166 ((a_u64Dst) = (int8_t)iemMemFlatFetchDataU8Jmp(pVCpu, (a_GCPtrMem)))
1167# define IEM_MC_FETCH_MEM_FLAT_U16_SX_U32(a_u32Dst, a_GCPtrMem) \
1168 ((a_u32Dst) = (int16_t)iemMemFlatFetchDataU16Jmp(pVCpu, (a_GCPtrMem)))
1169# define IEM_MC_FETCH_MEM_FLAT_U16_SX_U64(a_u64Dst, a_GCPtrMem) \
1170 ((a_u64Dst) = (int16_t)iemMemFlatFetchDataU16Jmp(pVCpu, (a_GCPtrMem)))
1171# define IEM_MC_FETCH_MEM_FLAT_U32_SX_U64(a_u64Dst, a_GCPtrMem) \
1172 ((a_u64Dst) = (int32_t)iemMemFlatFetchDataU32Jmp(pVCpu, (a_GCPtrMem)))
1173#endif /* IEM_WITH_SETJMP */
1174
1175#ifndef IEM_WITH_SETJMP
1176# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
1177 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value)))
1178# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
1179 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value)))
1180# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
1181 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value)))
1182# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
1183 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value)))
1184#else
1185# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
1186 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value))
1187# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
1188 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value))
1189# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
1190 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value))
1191# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
1192 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value))
1193
1194# define IEM_MC_STORE_MEM_FLAT_U8(a_GCPtrMem, a_u8Value) \
1195 iemMemFlatStoreDataU8Jmp(pVCpu, (a_GCPtrMem), (a_u8Value))
1196# define IEM_MC_STORE_MEM_FLAT_U16(a_GCPtrMem, a_u16Value) \
1197 iemMemFlatStoreDataU16Jmp(pVCpu, (a_GCPtrMem), (a_u16Value))
1198# define IEM_MC_STORE_MEM_FLAT_U32(a_GCPtrMem, a_u32Value) \
1199 iemMemFlatStoreDataU32Jmp(pVCpu, (a_GCPtrMem), (a_u32Value))
1200# define IEM_MC_STORE_MEM_FLAT_U64(a_GCPtrMem, a_u64Value) \
1201 iemMemFlatStoreDataU64Jmp(pVCpu, (a_GCPtrMem), (a_u64Value))
1202#endif
1203
1204#ifndef IEM_WITH_SETJMP
1205# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
1206 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C)))
1207# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
1208 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C)))
1209# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
1210 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C)))
1211# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
1212 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C)))
1213#else
1214# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
1215 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C))
1216# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
1217 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C))
1218# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
1219 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C))
1220# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
1221 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C))
1222
1223# define IEM_MC_STORE_MEM_FLAT_U8_CONST(a_GCPtrMem, a_u8C) \
1224 iemMemFlatStoreDataU8Jmp(pVCpu, (a_GCPtrMem), (a_u8C))
1225# define IEM_MC_STORE_MEM_FLAT_U16_CONST(a_GCPtrMem, a_u16C) \
1226 iemMemFlatStoreDataU16Jmp(pVCpu, (a_GCPtrMem), (a_u16C))
1227# define IEM_MC_STORE_MEM_FLAT_U32_CONST(a_GCPtrMem, a_u32C) \
1228 iemMemFlatStoreDataU32Jmp(pVCpu, (a_GCPtrMem), (a_u32C))
1229# define IEM_MC_STORE_MEM_FLAT_U64_CONST(a_GCPtrMem, a_u64C) \
1230 iemMemFlatStoreDataU64Jmp(pVCpu, (a_GCPtrMem), (a_u64C))
1231#endif
1232
1233#define IEM_MC_STORE_MEM_I8_CONST_BY_REF( a_pi8Dst, a_i8C) *(a_pi8Dst) = (a_i8C)
1234#define IEM_MC_STORE_MEM_I16_CONST_BY_REF(a_pi16Dst, a_i16C) *(a_pi16Dst) = (a_i16C)
1235#define IEM_MC_STORE_MEM_I32_CONST_BY_REF(a_pi32Dst, a_i32C) *(a_pi32Dst) = (a_i32C)
1236#define IEM_MC_STORE_MEM_I64_CONST_BY_REF(a_pi64Dst, a_i64C) *(a_pi64Dst) = (a_i64C)
1237#define IEM_MC_STORE_MEM_NEG_QNAN_R32_BY_REF(a_pr32Dst) (a_pr32Dst)->u = UINT32_C(0xffc00000)
1238#define IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF(a_pr64Dst) (a_pr64Dst)->u = UINT64_C(0xfff8000000000000)
1239#define IEM_MC_STORE_MEM_NEG_QNAN_R80_BY_REF(a_pr80Dst) \
1240 do { \
1241 (a_pr80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
1242 (a_pr80Dst)->au16[4] = UINT16_C(0xffff); \
1243 } while (0)
1244#define IEM_MC_STORE_MEM_INDEF_D80_BY_REF(a_pd80Dst) \
1245 do { \
1246 (a_pd80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
1247 (a_pd80Dst)->au16[4] = UINT16_C(0xffff); \
1248 } while (0)
1249
1250#ifndef IEM_WITH_SETJMP
1251# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
1252 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
1253# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
1254 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128AlignedSse(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
1255#else
1256# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
1257 iemMemStoreDataU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
1258# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
1259 iemMemStoreDataU128AlignedSseJmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
1260
1261# define IEM_MC_STORE_MEM_FLAT_U128(a_GCPtrMem, a_u128Value) \
1262 iemMemStoreDataU128Jmp(pVCpu, UINT8_MAX, (a_GCPtrMem), (a_u128Value))
1263# define IEM_MC_STORE_MEM_FLAT_U128_ALIGN_SSE(a_GCPtrMem, a_u128Value) \
1264 iemMemStoreDataU128AlignedSseJmp(pVCpu, UINT8_MAX, (a_GCPtrMem), (a_u128Value))
1265#endif
1266
1267#ifndef IEM_WITH_SETJMP
1268# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
1269 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
1270# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
1271 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256AlignedAvx(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
1272#else
1273# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
1274 iemMemStoreDataU256Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
1275# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
1276 iemMemStoreDataU256AlignedAvxJmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
1277
1278# define IEM_MC_STORE_MEM_FLAT_U256(a_GCPtrMem, a_u256Value) \
1279 iemMemStoreDataU256Jmp(pVCpu, UINT8_MAX, (a_GCPtrMem), &(a_u256Value))
1280# define IEM_MC_STORE_MEM_FLAT_U256_ALIGN_AVX(a_GCPtrMem, a_u256Value) \
1281 iemMemStoreDataU256AlignedAvxJmp(pVCpu, UINT8_MAX, (a_GCPtrMem), &(a_u256Value))
1282#endif
1283
1284/* Regular stack push and pop: */
1285#ifndef IEM_WITH_SETJMP
1286# define IEM_MC_PUSH_U16(a_u16Value) IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU16(pVCpu, (a_u16Value)))
1287# define IEM_MC_PUSH_U32(a_u32Value) IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32(pVCpu, (a_u32Value)))
1288# define IEM_MC_PUSH_U32_SREG(a_uSegVal) IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32SReg(pVCpu, (a_uSegVal)))
1289# define IEM_MC_PUSH_U64(a_u64Value) IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU64(pVCpu, (a_u64Value)))
1290
1291# define IEM_MC_POP_U16(a_pu16Value) IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU16(pVCpu, (a_pu16Value)))
1292# define IEM_MC_POP_U32(a_pu32Value) IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU32(pVCpu, (a_pu32Value)))
1293# define IEM_MC_POP_U64(a_pu64Value) IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU64(pVCpu, (a_pu64Value)))
1294#else
1295# define IEM_MC_PUSH_U16(a_u16Value) iemMemStackPushU16Jmp(pVCpu, (a_u16Value))
1296# define IEM_MC_PUSH_U32(a_u32Value) iemMemStackPushU32Jmp(pVCpu, (a_u32Value))
1297# define IEM_MC_PUSH_U32_SREG(a_uSegVal) iemMemStackPushU32SRegJmp(pVCpu, (a_uSegVal))
1298# define IEM_MC_PUSH_U64(a_u64Value) iemMemStackPushU64Jmp(pVCpu, (a_u64Value))
1299
1300# define IEM_MC_POP_U16(a_pu16Value) (*(a_pu16Value) = iemMemStackPopU16Jmp(pVCpu))
1301# define IEM_MC_POP_U32(a_pu32Value) (*(a_pu32Value) = iemMemStackPopU32Jmp(pVCpu))
1302# define IEM_MC_POP_U64(a_pu64Value) (*(a_pu64Value) = iemMemStackPopU64Jmp(pVCpu))
1303#endif
1304
1305/* 32-bit flat stack push and pop: */
1306#ifndef IEM_WITH_SETJMP
1307# define IEM_MC_FLAT32_PUSH_U16(a_u16Value) IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU16(pVCpu, (a_u16Value)))
1308# define IEM_MC_FLAT32_PUSH_U32(a_u32Value) IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32(pVCpu, (a_u32Value)))
1309# define IEM_MC_FLAT32_PUSH_U32_SREG(a_uSegVal) IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32SReg(pVCpu, (a_uSegVal)))
1310
1311# define IEM_MC_FLAT32_POP_U16(a_pu16Value) IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU16(pVCpu, (a_pu16Value)))
1312# define IEM_MC_FLAT32_POP_U32(a_pu32Value) IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU32(pVCpu, (a_pu32Value)))
1313#else
1314# define IEM_MC_FLAT32_PUSH_U16(a_u16Value) iemMemFlat32StackPushU16Jmp(pVCpu, (a_u16Value))
1315# define IEM_MC_FLAT32_PUSH_U32(a_u32Value) iemMemFlat32StackPushU32Jmp(pVCpu, (a_u32Value))
1316# define IEM_MC_FLAT32_PUSH_U32_SREG(a_uSegVal) iemMemFlat32StackPushU32SRegJmp(pVCpu, (a_uSegVal))
1317
1318# define IEM_MC_FLAT32_POP_U16(a_pu16Value) (*(a_pu16Value) = iemMemFlat32StackPopU16Jmp(pVCpu))
1319# define IEM_MC_FLAT32_POP_U32(a_pu32Value) (*(a_pu32Value) = iemMemFlat32StackPopU32Jmp(pVCpu))
1320#endif
1321
1322/* 64-bit flat stack push and pop: */
1323#ifndef IEM_WITH_SETJMP
1324# define IEM_MC_FLAT64_PUSH_U16(a_u16Value) IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU16(pVCpu, (a_u16Value)))
1325# define IEM_MC_FLAT64_PUSH_U64(a_u64Value) IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU64(pVCpu, (a_u64Value)))
1326
1327# define IEM_MC_FLAT64_POP_U16(a_pu16Value) IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU16(pVCpu, (a_pu16Value)))
1328# define IEM_MC_FLAT64_POP_U64(a_pu64Value) IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU64(pVCpu, (a_pu64Value)))
1329#else
1330# define IEM_MC_FLAT64_PUSH_U16(a_u16Value) iemMemFlat64StackPushU16Jmp(pVCpu, (a_u16Value))
1331# define IEM_MC_FLAT64_PUSH_U64(a_u64Value) iemMemFlat64StackPushU64Jmp(pVCpu, (a_u64Value))
1332
1333# define IEM_MC_FLAT64_POP_U16(a_pu16Value) (*(a_pu16Value) = iemMemFlat64StackPopU16Jmp(pVCpu))
1334# define IEM_MC_FLAT64_POP_U64(a_pu64Value) (*(a_pu64Value) = iemMemFlat64StackPopU64Jmp(pVCpu))
1335#endif
1336
1337
1338/** Maps guest memory for direct or bounce buffered access.
1339 * The purpose is to pass it to an operand implementation, thus the a_iArg.
1340 * @remarks May return.
1341 * @deprecated
1342 */
1343#define IEM_MC_MEM_MAP(a_pMem, a_fAccess, a_iSeg, a_GCPtrMem, a_iArg) \
1344 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pMem), sizeof(*(a_pMem)), (a_iSeg), \
1345 (a_GCPtrMem), (a_fAccess), sizeof(*(a_pMem)) - 1))
1346
1347/** Flat variant of IEM_MC_MEM_MAP.
1348 * @deprecated
1349 */
1350#define IEM_MC_MEM_FLAT_MAP(a_pMem, a_fAccess, a_GCPtrMem, a_iArg) \
1351 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pMem), sizeof(*(a_pMem)), UINT8_MAX, \
1352 (a_GCPtrMem), (a_fAccess), sizeof(*(a_pMem)) - 1))
1353
1354/** Maps guest memory for direct or bounce buffered access.
1355 * The purpose is to pass it to an operand implementation, thus the a_iArg.
1356 * @remarks May return.
1357 * @deprecated
1358 */
1359#define IEM_MC_MEM_MAP_EX(a_pvMem, a_fAccess, a_cbMem, a_iSeg, a_GCPtrMem, a_cbAlign, a_iArg) \
1360 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pvMem), (a_cbMem), (a_iSeg), \
1361 (a_GCPtrMem), (a_fAccess), (a_cbAlign)))
1362
1363/** Flat variant of IEM_MC_MEM_MAP_EX.
1364 * @deprecated
1365 */
1366#define IEM_MC_MEM_FLAT_MAP_EX(a_pvMem, a_fAccess, a_cbMem, a_GCPtrMem, a_cbAlign, a_iArg) \
1367 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pvMem), (a_cbMem), UINT8_MAX, \
1368 (a_GCPtrMem), (a_fAccess), (a_cbAlign)))
1369
1370/** Commits the memory and unmaps the guest memory.
1371 * @remarks May return.
1372 * @deprecated
1373 */
1374#define IEM_MC_MEM_COMMIT_AND_UNMAP(a_pvMem, a_fAccess) \
1375 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess)))
1376
1377
1378/* 8-bit */
1379
1380/**
1381 * Maps guest memory for byte read+write direct (or bounce) buffer acccess.
1382 *
1383 * @param[out] a_pu8Mem Where to return the pointer to the mapping.
1384 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1385 * @param[in] a_iSeg The segment register to access via. No UINT8_MAX!
1386 * @param[in] a_GCPtrMem The memory address.
1387 * @remarks Will return/long jump on errors.
1388 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RW
1389 */
1390#ifndef IEM_WITH_SETJMP
1391# define IEM_MC_MEM_MAP_U8_RW(a_pu8Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) do { \
1392 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu8Mem), sizeof(uint8_t), (a_iSeg), \
1393 (a_GCPtrMem), IEM_ACCESS_DATA_RW, 0)); \
1394 a_bUnmapInfo = 1 | ((IEM_ACCESS_TYPE_READ | IEM_ACCESS_TYPE_WRITE) << 4); \
1395 } while (0)
1396#else
1397# define IEM_MC_MEM_MAP_U8_RW(a_pu8Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1398 (a_pu8Mem) = iemMemMapDataU8RwJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
1399#endif
1400
1401/**
1402 * Maps guest memory for byte writeonly direct (or bounce) buffer acccess.
1403 *
1404 * @param[out] a_pu8Mem Where to return the pointer to the mapping.
1405 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1406 * @param[in] a_iSeg The segment register to access via. No UINT8_MAX!
1407 * @param[in] a_GCPtrMem The memory address.
1408 * @remarks Will return/long jump on errors.
1409 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_WO
1410 */
1411#ifndef IEM_WITH_SETJMP
1412# define IEM_MC_MEM_MAP_U8_WO(a_pu8Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) do { \
1413 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu8Mem), sizeof(uint8_t), (a_iSeg), \
1414 (a_GCPtrMem), IEM_ACCESS_DATA_W, 0)); \
1415 a_bUnmapInfo = 1 | (IEM_ACCESS_TYPE_WRITE << 4); \
1416 } while (0)
1417#else
1418# define IEM_MC_MEM_MAP_U8_WO(a_pu8Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1419 (a_pu8Mem) = iemMemMapDataU8WoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
1420#endif
1421
1422/**
1423 * Maps guest memory for byte readonly direct (or bounce) buffer acccess.
1424 *
1425 * @param[out] a_pu8Mem Where to return the pointer to the mapping.
1426 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1427 * @param[in] a_iSeg The segment register to access via. No UINT8_MAX!
1428 * @param[in] a_GCPtrMem The memory address.
1429 * @remarks Will return/long jump on errors.
1430 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RO
1431 */
1432#ifndef IEM_WITH_SETJMP
1433# define IEM_MC_MEM_MAP_U8_RO(a_pu8Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) do { \
1434 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu8Mem), sizeof(uint8_t), (a_iSeg), \
1435 (a_GCPtrMem), IEM_ACCESS_DATA_R, 0)); \
1436 a_bUnmapInfo = 1 | (IEM_ACCESS_TYPE_READ << 4); \
1437 } while (0)
1438#else
1439# define IEM_MC_MEM_MAP_U8_RO(a_pu8Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1440 (a_pu8Mem) = iemMemMapDataU8RoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
1441#endif
1442
1443/**
1444 * Maps guest memory for byte read+write direct (or bounce) buffer acccess, flat
1445 * address variant.
1446 *
1447 * @param[out] a_pu8Mem Where to return the pointer to the mapping.
1448 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1449 * @param[in] a_GCPtrMem The memory address.
1450 * @remarks Will return/long jump on errors.
1451 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RW
1452 */
1453#ifndef IEM_WITH_SETJMP
1454# define IEM_MC_MEM_FLAT_MAP_U8_RW(a_pu8Mem, a_bUnmapInfo, a_GCPtrMem) do { \
1455 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu8Mem), sizeof(uint8_t), UINT8_MAX, \
1456 (a_GCPtrMem), IEM_ACCESS_DATA_RW, 0)); \
1457 a_bUnmapInfo = 1 | ((IEM_ACCESS_TYPE_READ | IEM_ACCESS_TYPE_WRITE) << 4); \
1458 } while (0)
1459#else
1460# define IEM_MC_MEM_FLAT_MAP_U8_RW(a_pu8Mem, a_bUnmapInfo, a_GCPtrMem) \
1461 (a_pu8Mem) = iemMemFlatMapDataU8RwJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
1462#endif
1463
1464/**
1465 * Maps guest memory for byte writeonly direct (or bounce) buffer acccess, flat
1466 * address variant.
1467 *
1468 * @param[out] a_pu8Mem Where to return the pointer to the mapping.
1469 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1470 * @param[in] a_GCPtrMem The memory address.
1471 * @remarks Will return/long jump on errors.
1472 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_WO
1473 */
1474#ifndef IEM_WITH_SETJMP
1475# define IEM_MC_MEM_FLAT_MAP_U8_WO(a_pu8Mem, a_bUnmapInfo, a_GCPtrMem) do { \
1476 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu8Mem), sizeof(uint8_t), UINT8_MAX, \
1477 (a_GCPtrMem), IEM_ACCESS_DATA_W, 0)); \
1478 a_bUnmapInfo = 1 | (IEM_ACCESS_TYPE_WRITE << 4); \
1479 } while (0)
1480#else
1481# define IEM_MC_MEM_FLAT_MAP_U8_WO(a_pu8Mem, a_bUnmapInfo, a_GCPtrMem) \
1482 (a_pu8Mem) = iemMemFlatMapDataU8WoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
1483#endif
1484
1485/**
1486 * Maps guest memory for byte readonly direct (or bounce) buffer acccess, flat
1487 * address variant.
1488 *
1489 * @param[out] a_pu8Mem Where to return the pointer to the mapping.
1490 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1491 * @param[in] a_GCPtrMem The memory address.
1492 * @remarks Will return/long jump on errors.
1493 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RO
1494 */
1495#ifndef IEM_WITH_SETJMP
1496# define IEM_MC_MEM_FLAT_MAP_U8_RO(a_pu8Mem, a_bUnmapInfo, a_GCPtrMem) do { \
1497 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu8Mem), sizeof(uint8_t), UINT8_MAX, \
1498 (a_GCPtrMem), IEM_ACCESS_DATA_R, 0)); \
1499 a_bUnmapInfo = 1 | (IEM_ACCESS_TYPE_READ << 4); \
1500 } while (0)
1501#else
1502# define IEM_MC_MEM_FLAT_MAP_U8_RO(a_pu8Mem, a_bUnmapInfo, a_GCPtrMem) \
1503 (a_pu8Mem) = iemMemFlatMapDataU8RoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
1504#endif
1505
1506
1507/* 16-bit */
1508
1509/**
1510 * Maps guest memory for word read+write direct (or bounce) buffer acccess.
1511 *
1512 * @param[out] a_pu16Mem Where to return the pointer to the mapping.
1513 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1514 * @param[in] a_iSeg The segment register to access via. No UINT8_MAX!
1515 * @param[in] a_GCPtrMem The memory address.
1516 * @remarks Will return/long jump on errors.
1517 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RW
1518 */
1519#ifndef IEM_WITH_SETJMP
1520# define IEM_MC_MEM_MAP_U16_RW(a_pu16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) do { \
1521 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu16Mem), sizeof(uint16_t), (a_iSeg), \
1522 (a_GCPtrMem), IEM_ACCESS_DATA_RW, sizeof(uint16_t) - 1)); \
1523 a_bUnmapInfo = 1 | ((IEM_ACCESS_TYPE_READ | IEM_ACCESS_TYPE_WRITE) << 4); \
1524 } while (0)
1525#else
1526# define IEM_MC_MEM_MAP_U16_RW(a_pu16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1527 (a_pu16Mem) = iemMemMapDataU16RwJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
1528#endif
1529
1530/**
1531 * Maps guest memory for word writeonly direct (or bounce) buffer acccess.
1532 *
1533 * @param[out] a_pu16Mem Where to return the pointer to the mapping.
1534 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1535 * @param[in] a_iSeg The segment register to access via. No UINT8_MAX!
1536 * @param[in] a_GCPtrMem The memory address.
1537 * @remarks Will return/long jump on errors.
1538 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_WO
1539 */
1540#ifndef IEM_WITH_SETJMP
1541# define IEM_MC_MEM_MAP_U16_WO(a_pu16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) do { \
1542 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu16Mem), sizeof(uint16_t), (a_iSeg), \
1543 (a_GCPtrMem), IEM_ACCESS_DATA_W, sizeof(uint16_t) - 1)); \
1544 a_bUnmapInfo = 1 | (IEM_ACCESS_TYPE_WRITE << 4); \
1545 } while (0)
1546#else
1547# define IEM_MC_MEM_MAP_U16_WO(a_pu16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1548 (a_pu16Mem) = iemMemMapDataU16WoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
1549#endif
1550
1551/**
1552 * Maps guest memory for word readonly direct (or bounce) buffer acccess.
1553 *
1554 * @param[out] a_pu16Mem Where to return the pointer to the mapping.
1555 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1556 * @param[in] a_iSeg The segment register to access via. No UINT8_MAX!
1557 * @param[in] a_GCPtrMem The memory address.
1558 * @remarks Will return/long jump on errors.
1559 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RO
1560 */
1561#ifndef IEM_WITH_SETJMP
1562# define IEM_MC_MEM_MAP_U16_RO(a_pu16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) do { \
1563 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu16Mem), sizeof(uint16_t), (a_iSeg), \
1564 (a_GCPtrMem), IEM_ACCESS_DATA_R, sizeof(uint16_t) - 1)); \
1565 a_bUnmapInfo = 1 | (IEM_ACCESS_TYPE_READ << 4); \
1566 } while (0)
1567#else
1568# define IEM_MC_MEM_MAP_U16_RO(a_pu16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1569 (a_pu16Mem) = iemMemMapDataU16RoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
1570#endif
1571
1572/**
1573 * Maps guest memory for word read+write direct (or bounce) buffer acccess, flat
1574 * address variant.
1575 *
1576 * @param[out] a_pu16Mem Where to return the pointer to the mapping.
1577 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1578 * @param[in] a_GCPtrMem The memory address.
1579 * @remarks Will return/long jump on errors.
1580 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RW
1581 */
1582#ifndef IEM_WITH_SETJMP
1583# define IEM_MC_MEM_FLAT_MAP_U16_RW(a_pu16Mem, a_bUnmapInfo, a_GCPtrMem) do { \
1584 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu16Mem), sizeof(uint16_t), UINT8_MAX, \
1585 (a_GCPtrMem), IEM_ACCESS_DATA_RW, sizeof(uint16_t) - 1)); \
1586 a_bUnmapInfo = 1 | ((IEM_ACCESS_TYPE_READ | IEM_ACCESS_TYPE_WRITE) << 4); \
1587 } while (0)
1588#else
1589# define IEM_MC_MEM_FLAT_MAP_U16_RW(a_pu16Mem, a_bUnmapInfo, a_GCPtrMem) \
1590 (a_pu16Mem) = iemMemFlatMapDataU16RwJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
1591#endif
1592
1593/**
1594 * Maps guest memory for word writeonly direct (or bounce) buffer acccess, flat
1595 * address variant.
1596 *
1597 * @param[out] a_pu16Mem Where to return the pointer to the mapping.
1598 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1599 * @param[in] a_GCPtrMem The memory address.
1600 * @remarks Will return/long jump on errors.
1601 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_WO
1602 */
1603#ifndef IEM_WITH_SETJMP
1604# define IEM_MC_MEM_FLAT_MAP_U16_WO(a_pu16Mem, a_bUnmapInfo, a_GCPtrMem) do { \
1605 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu16Mem), sizeof(uint16_t), UINT8_MAX, \
1606 (a_GCPtrMem), IEM_ACCESS_DATA_W, sizeof(uint16_t) - 1)); \
1607 a_bUnmapInfo = 1 | (IEM_ACCESS_TYPE_WRITE << 4); \
1608 } while (0)
1609#else
1610# define IEM_MC_MEM_FLAT_MAP_U16_WO(a_pu16Mem, a_bUnmapInfo, a_GCPtrMem) \
1611 (a_pu16Mem) = iemMemFlatMapDataU16WoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
1612#endif
1613
1614/**
1615 * Maps guest memory for word readonly direct (or bounce) buffer acccess, flat
1616 * address variant.
1617 *
1618 * @param[out] a_pu16Mem Where to return the pointer to the mapping.
1619 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1620 * @param[in] a_GCPtrMem The memory address.
1621 * @remarks Will return/long jump on errors.
1622 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RO
1623 */
1624#ifndef IEM_WITH_SETJMP
1625# define IEM_MC_MEM_FLAT_MAP_U16_RO(a_pu16Mem, a_bUnmapInfo, a_GCPtrMem) do { \
1626 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu16Mem), sizeof(uint16_t), UINT8_MAX, \
1627 (a_GCPtrMem), IEM_ACCESS_DATA_R, sizeof(uint16_t) - 1)); \
1628 a_bUnmapInfo = 1 | (IEM_ACCESS_TYPE_READ << 4); \
1629 } while (0)
1630#else
1631# define IEM_MC_MEM_FLAT_MAP_U16_RO(a_pu16Mem, a_bUnmapInfo, a_GCPtrMem) \
1632 (a_pu16Mem) = iemMemFlatMapDataU16RoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
1633#endif
1634
1635
1636/* 32-bit */
1637
1638/**
1639 * Maps guest memory for dword read+write direct (or bounce) buffer acccess.
1640 *
1641 * @param[out] a_pu32Mem Where to return the pointer to the mapping.
1642 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1643 * @param[in] a_iSeg The segment register to access via. No UINT8_MAX!
1644 * @param[in] a_GCPtrMem The memory address.
1645 * @remarks Will return/long jump on errors.
1646 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RW
1647 */
1648#ifndef IEM_WITH_SETJMP
1649# define IEM_MC_MEM_MAP_U32_RW(a_pu32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) do { \
1650 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu32Mem), sizeof(uint32_t), (a_iSeg), \
1651 (a_GCPtrMem), IEM_ACCESS_DATA_RW, sizeof(uint32_t) - 1)); \
1652 a_bUnmapInfo = 1 | ((IEM_ACCESS_TYPE_READ | IEM_ACCESS_TYPE_WRITE) << 4); \
1653 } while (0)
1654#else
1655# define IEM_MC_MEM_MAP_U32_RW(a_pu32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1656 (a_pu32Mem) = iemMemMapDataU32RwJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
1657#endif
1658
1659/**
1660 * Maps guest memory for dword writeonly direct (or bounce) buffer acccess.
1661 *
1662 * @param[out] a_pu32Mem Where to return the pointer to the mapping.
1663 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1664 * @param[in] a_iSeg The segment register to access via. No UINT8_MAX!
1665 * @param[in] a_GCPtrMem The memory address.
1666 * @remarks Will return/long jump on errors.
1667 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_WO
1668 */
1669#ifndef IEM_WITH_SETJMP
1670# define IEM_MC_MEM_MAP_U32_WO(a_pu32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) do { \
1671 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu32Mem), sizeof(uint32_t), (a_iSeg), \
1672 (a_GCPtrMem), IEM_ACCESS_DATA_W, sizeof(uint32_t) - 1)); \
1673 a_bUnmapInfo = 1 | (IEM_ACCESS_TYPE_WRITE << 4); \
1674 } while (0)
1675#else
1676# define IEM_MC_MEM_MAP_U32_WO(a_pu32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1677 (a_pu32Mem) = iemMemMapDataU32WoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
1678#endif
1679
1680/**
1681 * Maps guest memory for dword readonly direct (or bounce) buffer acccess.
1682 *
1683 * @param[out] a_pu32Mem Where to return the pointer to the mapping.
1684 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1685 * @param[in] a_iSeg The segment register to access via. No UINT8_MAX!
1686 * @param[in] a_GCPtrMem The memory address.
1687 * @remarks Will return/long jump on errors.
1688 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RO
1689 */
1690#ifndef IEM_WITH_SETJMP
1691# define IEM_MC_MEM_MAP_U32_RO(a_pu32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) do { \
1692 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu32Mem), sizeof(uint32_t), (a_iSeg), \
1693 (a_GCPtrMem), IEM_ACCESS_DATA_R, sizeof(uint32_t) - 1)); \
1694 a_bUnmapInfo = 1 | (IEM_ACCESS_TYPE_READ << 4); \
1695 } while (0)
1696#else
1697# define IEM_MC_MEM_MAP_U32_RO(a_pu32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1698 (a_pu32Mem) = iemMemMapDataU32RoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
1699#endif
1700
1701/**
1702 * Maps guest memory for dword read+write direct (or bounce) buffer acccess,
1703 * flat address variant.
1704 *
1705 * @param[out] a_pu32Mem Where to return the pointer to the mapping.
1706 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1707 * @param[in] a_GCPtrMem The memory address.
1708 * @remarks Will return/long jump on errors.
1709 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RW
1710 */
1711#ifndef IEM_WITH_SETJMP
1712# define IEM_MC_MEM_FLAT_MAP_U32_RW(a_pu32Mem, a_bUnmapInfo, a_GCPtrMem) do { \
1713 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu32Mem), sizeof(uint32_t), UINT8_MAX, \
1714 (a_GCPtrMem), IEM_ACCESS_DATA_RW, sizeof(uint32_t) - 1)); \
1715 a_bUnmapInfo = 1 | ((IEM_ACCESS_TYPE_READ | IEM_ACCESS_TYPE_WRITE) << 4); \
1716 } while (0)
1717#else
1718# define IEM_MC_MEM_FLAT_MAP_U32_RW(a_pu32Mem, a_bUnmapInfo, a_GCPtrMem) \
1719 (a_pu32Mem) = iemMemFlatMapDataU32RwJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
1720#endif
1721
1722/**
1723 * Maps guest memory for dword writeonly direct (or bounce) buffer acccess, flat
1724 * address variant.
1725 *
1726 * @param[out] a_pu32Mem Where to return the pointer to the mapping.
1727 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1728 * @param[in] a_GCPtrMem The memory address.
1729 * @remarks Will return/long jump on errors.
1730 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_WO
1731 */
1732#ifndef IEM_WITH_SETJMP
1733# define IEM_MC_MEM_FLAT_MAP_U32_WO(a_pu32Mem, a_bUnmapInfo, a_GCPtrMem) do { \
1734 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu32Mem), sizeof(uint32_t), UINT8_MAX, \
1735 (a_GCPtrMem), IEM_ACCESS_DATA_W, sizeof(uint32_t) - 1)); \
1736 a_bUnmapInfo = 1 | (IEM_ACCESS_TYPE_WRITE << 4); \
1737 } while (0)
1738#else
1739# define IEM_MC_MEM_FLAT_MAP_U32_WO(a_pu32Mem, a_bUnmapInfo, a_GCPtrMem) \
1740 (a_pu32Mem) = iemMemFlatMapDataU32WoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
1741#endif
1742
1743/**
1744 * Maps guest memory for dword readonly direct (or bounce) buffer acccess, flat
1745 * address variant.
1746 *
1747 * @param[out] a_pu32Mem Where to return the pointer to the mapping.
1748 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1749 * @param[in] a_GCPtrMem The memory address.
1750 * @remarks Will return/long jump on errors.
1751 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RO
1752 */
1753#ifndef IEM_WITH_SETJMP
1754# define IEM_MC_MEM_FLAT_MAP_U32_RO(a_pu32Mem, a_bUnmapInfo, a_GCPtrMem) do { \
1755 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu32Mem), sizeof(uint32_t), UINT8_MAX, \
1756 (a_GCPtrMem), IEM_ACCESS_DATA_R, sizeof(uint32_t) - 1)); \
1757 a_bUnmapInfo = 1 | (IEM_ACCESS_TYPE_READ << 4); \
1758 } while (0)
1759#else
1760# define IEM_MC_MEM_FLAT_MAP_U32_RO(a_pu32Mem, a_bUnmapInfo, a_GCPtrMem) \
1761 (a_pu32Mem) = iemMemFlatMapDataU32RoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
1762#endif
1763
1764
1765/* 64-bit */
1766
1767/**
1768 * Maps guest memory for qword read+write direct (or bounce) buffer acccess.
1769 *
1770 * @param[out] a_pu64Mem Where to return the pointer to the mapping.
1771 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1772 * @param[in] a_iSeg The segment register to access via. No UINT8_MAX!
1773 * @param[in] a_GCPtrMem The memory address.
1774 * @remarks Will return/long jump on errors.
1775 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RW
1776 */
1777#ifndef IEM_WITH_SETJMP
1778# define IEM_MC_MEM_MAP_U64_RW(a_pu64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) do { \
1779 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu64Mem), sizeof(uint64_t), (a_iSeg), \
1780 (a_GCPtrMem), IEM_ACCESS_DATA_RW, sizeof(uint64_t) - 1)); \
1781 a_bUnmapInfo = 1 | ((IEM_ACCESS_TYPE_READ | IEM_ACCESS_TYPE_WRITE) << 4); \
1782 } while (0)
1783#else
1784# define IEM_MC_MEM_MAP_U64_RW(a_pu64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1785 (a_pu64Mem) = iemMemMapDataU64RwJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
1786#endif
1787
1788/**
1789 * Maps guest memory for qword writeonly direct (or bounce) buffer acccess.
1790 *
1791 * @param[out] a_pu64Mem Where to return the pointer to the mapping.
1792 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1793 * @param[in] a_iSeg The segment register to access via. No UINT8_MAX!
1794 * @param[in] a_GCPtrMem The memory address.
1795 * @remarks Will return/long jump on errors.
1796 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_WO
1797 */
1798#ifndef IEM_WITH_SETJMP
1799# define IEM_MC_MEM_MAP_U64_WO(a_pu64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) do { \
1800 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu64Mem), sizeof(uint64_t), (a_iSeg), \
1801 (a_GCPtrMem), IEM_ACCESS_DATA_W, sizeof(uint64_t) - 1)); \
1802 a_bUnmapInfo = 1 | (IEM_ACCESS_TYPE_WRITE << 4); \
1803 } while (0)
1804#else
1805# define IEM_MC_MEM_MAP_U64_WO(a_pu64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1806 (a_pu64Mem) = iemMemMapDataU64WoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
1807#endif
1808
1809/**
1810 * Maps guest memory for qword readonly direct (or bounce) buffer acccess.
1811 *
1812 * @param[out] a_pu64Mem Where to return the pointer to the mapping.
1813 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1814 * @param[in] a_iSeg The segment register to access via. No UINT8_MAX!
1815 * @param[in] a_GCPtrMem The memory address.
1816 * @remarks Will return/long jump on errors.
1817 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RO
1818 */
1819#ifndef IEM_WITH_SETJMP
1820# define IEM_MC_MEM_MAP_U64_RO(a_pu64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) do { \
1821 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu64Mem), sizeof(uint64_t), (a_iSeg), \
1822 (a_GCPtrMem), IEM_ACCESS_DATA_R, sizeof(uint64_t) - 1)); \
1823 a_bUnmapInfo = 1 | (IEM_ACCESS_TYPE_READ << 4); \
1824 } while (0)
1825#else
1826# define IEM_MC_MEM_MAP_U64_RO(a_pu64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1827 (a_pu64Mem) = iemMemMapDataU64RoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
1828#endif
1829
1830/**
1831 * Maps guest memory for qword read+write direct (or bounce) buffer acccess,
1832 * flat address variant.
1833 *
1834 * @param[out] a_pu64Mem Where to return the pointer to the mapping.
1835 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1836 * @param[in] a_GCPtrMem The memory address.
1837 * @remarks Will return/long jump on errors.
1838 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RW
1839 */
1840#ifndef IEM_WITH_SETJMP
1841# define IEM_MC_MEM_FLAT_MAP_U64_RW(a_pu64Mem, a_bUnmapInfo, a_GCPtrMem) do { \
1842 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu64Mem), sizeof(uint64_t), UINT8_MAX, \
1843 (a_GCPtrMem), IEM_ACCESS_DATA_RW, sizeof(uint64_t) - 1)); \
1844 a_bUnmapInfo = 1 | ((IEM_ACCESS_TYPE_READ | IEM_ACCESS_TYPE_WRITE) << 4); \
1845 } while (0)
1846#else
1847# define IEM_MC_MEM_FLAT_MAP_U64_RW(a_pu64Mem, a_bUnmapInfo, a_GCPtrMem) \
1848 (a_pu64Mem) = iemMemFlatMapDataU64RwJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
1849#endif
1850
1851/**
1852 * Maps guest memory for qword writeonly direct (or bounce) buffer acccess, flat
1853 * address variant.
1854 *
1855 * @param[out] a_pu64Mem Where to return the pointer to the mapping.
1856 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1857 * @param[in] a_GCPtrMem The memory address.
1858 * @remarks Will return/long jump on errors.
1859 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_WO
1860 */
1861#ifndef IEM_WITH_SETJMP
1862# define IEM_MC_MEM_FLAT_MAP_U64_WO(a_pu64Mem, a_bUnmapInfo, a_GCPtrMem) do { \
1863 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu64Mem), sizeof(uint64_t), UINT8_MAX, \
1864 (a_GCPtrMem), IEM_ACCESS_DATA_W, sizeof(uint64_t) - 1)); \
1865 a_bUnmapInfo = 1 | (IEM_ACCESS_TYPE_WRITE << 4); \
1866 } while (0)
1867#else
1868# define IEM_MC_MEM_FLAT_MAP_U64_WO(a_pu64Mem, a_bUnmapInfo, a_GCPtrMem) \
1869 (a_pu64Mem) = iemMemFlatMapDataU64WoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
1870#endif
1871
1872/**
1873 * Maps guest memory for qword readonly direct (or bounce) buffer acccess, flat
1874 * address variant.
1875 *
1876 * @param[out] a_pu64Mem Where to return the pointer to the mapping.
1877 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1878 * @param[in] a_GCPtrMem The memory address.
1879 * @remarks Will return/long jump on errors.
1880 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RO
1881 */
1882#ifndef IEM_WITH_SETJMP
1883# define IEM_MC_MEM_FLAT_MAP_U64_RO(a_pu64Mem, a_bUnmapInfo, a_GCPtrMem) do { \
1884 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu64Mem), sizeof(uint64_t), UINT8_MAX, \
1885 (a_GCPtrMem), IEM_ACCESS_DATA_R, sizeof(uint64_t) - 1)); \
1886 a_bUnmapInfo = 1 | (IEM_ACCESS_TYPE_READ << 4); \
1887 } while (0)
1888#else
1889# define IEM_MC_MEM_FLAT_MAP_U64_RO(a_pu64Mem, a_bUnmapInfo, a_GCPtrMem) \
1890 (a_pu64Mem) = iemMemFlatMapDataU64RoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
1891#endif
1892
1893
1894/* commit + unmap */
1895
1896/** Commits the memory and unmaps guest memory previously mapped RW.
1897 * @remarks May return.
1898 */
1899#ifndef IEM_WITH_SETJMP
1900# define IEM_MC_MEM_COMMIT_AND_UNMAP_RW(a_pvMem, a_bMapInfo) do { \
1901 RT_NOREF_PV(a_bMapInfo); Assert(a_bMapInfo == (1 | ((IEM_ACCESS_TYPE_READ | IEM_ACCESS_TYPE_WRITE) << 4)) ); \
1902 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), IEM_ACCESS_DATA_RW)); \
1903 } while (0)
1904#else
1905# define IEM_MC_MEM_COMMIT_AND_UNMAP_RW(a_pvMem, a_bMapInfo) \
1906 iemMemCommitAndUnmapRwJmp(pVCpu, (a_pvMem), (a_bMapInfo))
1907#endif
1908
1909/** Commits the memory and unmaps guest memory previously mapped W.
1910 * @remarks May return.
1911 */
1912#ifndef IEM_WITH_SETJMP
1913# define IEM_MC_MEM_COMMIT_AND_UNMAP_WO(a_pvMem, a_bMapInfo) do { \
1914 RT_NOREF_PV(a_bMapInfo); Assert(a_bMapInfo == (1 | (IEM_ACCESS_TYPE_WRITE << 4)) ); \
1915 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), IEM_ACCESS_DATA_W)); \
1916 } while (0)
1917#else
1918# define IEM_MC_MEM_COMMIT_AND_UNMAP_WO(a_pvMem, a_bMapInfo) \
1919 iemMemCommitAndUnmapWoJmp(pVCpu, (a_pvMem), (a_bMapInfo))
1920#endif
1921
1922/** Commits the memory and unmaps guest memory previously mapped R.
1923 * @remarks May return.
1924 */
1925#ifndef IEM_WITH_SETJMP
1926# define IEM_MC_MEM_COMMIT_AND_UNMAP_RO(a_pvMem, a_bMapInfo) do { \
1927 RT_NOREF_PV(a_bMapInfo); Assert(a_bMapInfo == (1 | (IEM_ACCESS_TYPE_READ << 4)) ); \
1928 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (void *)(a_pvMem), IEM_ACCESS_DATA_R)); \
1929 } while (0)
1930#else
1931# define IEM_MC_MEM_COMMIT_AND_UNMAP_RO(a_pvMem, a_bMapInfo) \
1932 iemMemCommitAndUnmapRoJmp(pVCpu, (a_pvMem), (a_bMapInfo))
1933#endif
1934
1935
1936/** Commits the memory and unmaps the guest memory unless the FPU status word
1937 * indicates (@a a_u16FSW) and FPU control word indicates a pending exception
1938 * that would cause FLD not to store.
1939 *
1940 * The current understanding is that \#O, \#U, \#IA and \#IS will prevent a
1941 * store, while \#P will not.
1942 *
1943 * @remarks May in theory return - for now.
1944 */
1945#define IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(a_pvMem, a_fAccess, a_u16FSW) \
1946 do { \
1947 if ( !(a_u16FSW & X86_FSW_ES) \
1948 || !( (a_u16FSW & (X86_FSW_UE | X86_FSW_OE | X86_FSW_IE)) \
1949 & ~(pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_MASK_ALL) ) ) \
1950 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess))); \
1951 } while (0)
1952
1953
1954
1955/** Calculate efficient address from R/M. */
1956#ifndef IEM_WITH_SETJMP
1957# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, a_bRm, a_cbImmAndRspOffset) \
1958 IEM_MC_RETURN_ON_FAILURE(iemOpHlpCalcRmEffAddr(pVCpu, (a_bRm), (a_cbImmAndRspOffset), &(a_GCPtrEff)))
1959#else
1960# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, a_bRm, a_cbImmAndRspOffset) \
1961 ((a_GCPtrEff) = iemOpHlpCalcRmEffAddrJmp(pVCpu, (a_bRm), (a_cbImmAndRspOffset)))
1962#endif
1963
1964#define IEM_MC_CALL_VOID_AIMPL_0(a_pfn) (a_pfn)()
1965#define IEM_MC_CALL_VOID_AIMPL_1(a_pfn, a0) (a_pfn)((a0))
1966#define IEM_MC_CALL_VOID_AIMPL_2(a_pfn, a0, a1) (a_pfn)((a0), (a1))
1967#define IEM_MC_CALL_VOID_AIMPL_3(a_pfn, a0, a1, a2) (a_pfn)((a0), (a1), (a2))
1968#define IEM_MC_CALL_VOID_AIMPL_4(a_pfn, a0, a1, a2, a3) (a_pfn)((a0), (a1), (a2), (a3))
1969#define IEM_MC_CALL_AIMPL_3(a_rc, a_pfn, a0, a1, a2) (a_rc) = (a_pfn)((a0), (a1), (a2))
1970#define IEM_MC_CALL_AIMPL_4(a_rc, a_pfn, a0, a1, a2, a3) (a_rc) = (a_pfn)((a0), (a1), (a2), (a3))
1971
1972
1973/** @def IEM_MC_CALL_CIMPL_HLP_RET
1974 * Helper macro for check that all important IEM_CIMPL_F_XXX bits are set.
1975 */
1976#ifdef VBOX_STRICT
1977#define IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, a_CallExpr) \
1978 do { \
1979 uint8_t const cbInstr = IEM_GET_INSTR_LEN(pVCpu); /* may be flushed */ \
1980 uint16_t const uCsBefore = pVCpu->cpum.GstCtx.cs.Sel; \
1981 uint64_t const uRipBefore = pVCpu->cpum.GstCtx.rip; \
1982 uint32_t const fEflBefore = pVCpu->cpum.GstCtx.eflags.u; \
1983 uint32_t const fExecBefore = pVCpu->iem.s.fExec; \
1984 VBOXSTRICTRC const rcStrictHlp = a_CallExpr; \
1985 if (rcStrictHlp == VINF_SUCCESS) \
1986 { \
1987 AssertMsg( ((a_fFlags) & IEM_CIMPL_F_BRANCH_ANY) \
1988 || ( uRipBefore + cbInstr == pVCpu->cpum.GstCtx.rip \
1989 && uCsBefore == pVCpu->cpum.GstCtx.cs.Sel) \
1990 || ( ((a_fFlags) & IEM_CIMPL_F_REP) \
1991 && uRipBefore == pVCpu->cpum.GstCtx.rip \
1992 && uCsBefore == pVCpu->cpum.GstCtx.cs.Sel), \
1993 ("CS:RIP=%04x:%08RX64 + %x -> %04x:%08RX64, expected %04x:%08RX64\n", uCsBefore, uRipBefore, cbInstr, \
1994 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, uCsBefore, uRipBefore + cbInstr)); \
1995 if ((a_fFlags) & IEM_CIMPL_F_RFLAGS) \
1996 { /* No need to check fEflBefore */ Assert(!((a_fFlags) & IEM_CIMPL_F_STATUS_FLAGS)); } \
1997 else if ((a_fFlags) & IEM_CIMPL_F_STATUS_FLAGS) \
1998 AssertMsg( (pVCpu->cpum.GstCtx.eflags.u & ~(X86_EFL_STATUS_BITS | X86_EFL_RF)) \
1999 == (fEflBefore & ~(X86_EFL_STATUS_BITS | X86_EFL_RF)), \
2000 ("EFL=%#RX32 -> %#RX32\n", fEflBefore, pVCpu->cpum.GstCtx.eflags.u)); \
2001 else \
2002 AssertMsg( (pVCpu->cpum.GstCtx.eflags.u & ~(X86_EFL_RF)) \
2003 == (fEflBefore & ~(X86_EFL_RF)), \
2004 ("EFL=%#RX32 -> %#RX32\n", fEflBefore, pVCpu->cpum.GstCtx.eflags.u)); \
2005 if (!((a_fFlags) & IEM_CIMPL_F_MODE)) \
2006 { \
2007 uint32_t fExecRecalc = iemCalcExecFlags(pVCpu) | (pVCpu->iem.s.fExec & IEM_F_USER_OPTS); \
2008 AssertMsg( fExecBefore == fExecRecalc \
2009 /* in case ES, DS or SS was external initially (happens alot with HM): */ \
2010 || ( fExecBefore == (fExecRecalc & ~IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK) \
2011 && (fExecRecalc & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT), \
2012 ("fExec=%#x -> %#x (diff %#x)\n", fExecBefore, fExecRecalc, fExecBefore ^ fExecRecalc)); \
2013 } \
2014 } \
2015 return rcStrictHlp; \
2016 } while (0)
2017#else
2018# define IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, a_CallExpr) return a_CallExpr
2019#endif
2020
2021/**
2022 * Defers the rest of the instruction emulation to a C implementation routine
2023 * and returns, only taking the standard parameters.
2024 *
2025 * @param a_fFlags IEM_CIMPL_F_XXX.
2026 * @param a_pfnCImpl The pointer to the C routine.
2027 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
2028 */
2029#define IEM_MC_CALL_CIMPL_0(a_fFlags, a_pfnCImpl) \
2030 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu)))
2031
2032/**
2033 * Defers the rest of instruction emulation to a C implementation routine and
2034 * returns, taking one argument in addition to the standard ones.
2035 *
2036 * @param a_fFlags IEM_CIMPL_F_XXX.
2037 * @param a_pfnCImpl The pointer to the C routine.
2038 * @param a0 The argument.
2039 */
2040#define IEM_MC_CALL_CIMPL_1(a_fFlags, a_pfnCImpl, a0) \
2041 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0))
2042
2043/**
2044 * Defers the rest of the instruction emulation to a C implementation routine
2045 * and returns, taking two arguments in addition to the standard ones.
2046 *
2047 * @param a_fFlags IEM_CIMPL_F_XXX.
2048 * @param a_pfnCImpl The pointer to the C routine.
2049 * @param a0 The first extra argument.
2050 * @param a1 The second extra argument.
2051 */
2052#define IEM_MC_CALL_CIMPL_2(a_fFlags, a_pfnCImpl, a0, a1) \
2053 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1))
2054
2055/**
2056 * Defers the rest of the instruction emulation to a C implementation routine
2057 * and returns, taking three arguments in addition to the standard ones.
2058 *
2059 * @param a_fFlags IEM_CIMPL_F_XXX.
2060 * @param a_pfnCImpl The pointer to the C routine.
2061 * @param a0 The first extra argument.
2062 * @param a1 The second extra argument.
2063 * @param a2 The third extra argument.
2064 */
2065#define IEM_MC_CALL_CIMPL_3(a_fFlags, a_pfnCImpl, a0, a1, a2) \
2066 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2))
2067
2068/**
2069 * Defers the rest of the instruction emulation to a C implementation routine
2070 * and returns, taking four arguments in addition to the standard ones.
2071 *
2072 * @param a_fFlags IEM_CIMPL_F_XXX.
2073 * @param a_pfnCImpl The pointer to the C routine.
2074 * @param a0 The first extra argument.
2075 * @param a1 The second extra argument.
2076 * @param a2 The third extra argument.
2077 * @param a3 The fourth extra argument.
2078 */
2079#define IEM_MC_CALL_CIMPL_4(a_fFlags, a_pfnCImpl, a0, a1, a2, a3) \
2080 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3))
2081
2082/**
2083 * Defers the rest of the instruction emulation to a C implementation routine
2084 * and returns, taking two arguments in addition to the standard ones.
2085 *
2086 * @param a_fFlags IEM_CIMPL_F_XXX.
2087 * @param a_pfnCImpl The pointer to the C routine.
2088 * @param a0 The first extra argument.
2089 * @param a1 The second extra argument.
2090 * @param a2 The third extra argument.
2091 * @param a3 The fourth extra argument.
2092 * @param a4 The fifth extra argument.
2093 */
2094#define IEM_MC_CALL_CIMPL_5(a_fFlags, a_pfnCImpl, a0, a1, a2, a3, a4) \
2095 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3, a4))
2096
2097/**
2098 * Defers the entire instruction emulation to a C implementation routine and
2099 * returns, only taking the standard parameters.
2100 *
2101 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
2102 *
2103 * @param a_fFlags IEM_CIMPL_F_XXX.
2104 * @param a_pfnCImpl The pointer to the C routine.
2105 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
2106 */
2107#define IEM_MC_DEFER_TO_CIMPL_0_RET(a_fFlags, a_pfnCImpl) \
2108 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu)))
2109
2110/**
2111 * Defers the entire instruction emulation to a C implementation routine and
2112 * returns, taking one argument in addition to the standard ones.
2113 *
2114 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
2115 *
2116 * @param a_fFlags IEM_CIMPL_F_XXX.
2117 * @param a_pfnCImpl The pointer to the C routine.
2118 * @param a0 The argument.
2119 */
2120#define IEM_MC_DEFER_TO_CIMPL_1_RET(a_fFlags, a_pfnCImpl, a0) \
2121 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0))
2122
2123/**
2124 * Defers the entire instruction emulation to a C implementation routine and
2125 * returns, taking two arguments in addition to the standard ones.
2126 *
2127 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
2128 *
2129 * @param a_fFlags IEM_CIMPL_F_XXX.
2130 * @param a_pfnCImpl The pointer to the C routine.
2131 * @param a0 The first extra argument.
2132 * @param a1 The second extra argument.
2133 */
2134#define IEM_MC_DEFER_TO_CIMPL_2_RET(a_fFlags, a_pfnCImpl, a0, a1) \
2135 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1))
2136
2137/**
2138 * Defers the entire instruction emulation to a C implementation routine and
2139 * returns, taking three arguments in addition to the standard ones.
2140 *
2141 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
2142 *
2143 * @param a_fFlags IEM_CIMPL_F_XXX.
2144 * @param a_pfnCImpl The pointer to the C routine.
2145 * @param a0 The first extra argument.
2146 * @param a1 The second extra argument.
2147 * @param a2 The third extra argument.
2148 */
2149#define IEM_MC_DEFER_TO_CIMPL_3_RET(a_fFlags, a_pfnCImpl, a0, a1, a2) \
2150 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2))
2151
2152
2153/**
2154 * Calls a FPU assembly implementation taking one visible argument.
2155 *
2156 * @param a_pfnAImpl Pointer to the assembly FPU routine.
2157 * @param a0 The first extra argument.
2158 */
2159#define IEM_MC_CALL_FPU_AIMPL_1(a_pfnAImpl, a0) \
2160 do { \
2161 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0)); \
2162 } while (0)
2163
2164/**
2165 * Calls a FPU assembly implementation taking two visible arguments.
2166 *
2167 * @param a_pfnAImpl Pointer to the assembly FPU routine.
2168 * @param a0 The first extra argument.
2169 * @param a1 The second extra argument.
2170 */
2171#define IEM_MC_CALL_FPU_AIMPL_2(a_pfnAImpl, a0, a1) \
2172 do { \
2173 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
2174 } while (0)
2175
2176/**
2177 * Calls a FPU assembly implementation taking three visible arguments.
2178 *
2179 * @param a_pfnAImpl Pointer to the assembly FPU routine.
2180 * @param a0 The first extra argument.
2181 * @param a1 The second extra argument.
2182 * @param a2 The third extra argument.
2183 */
2184#define IEM_MC_CALL_FPU_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
2185 do { \
2186 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
2187 } while (0)
2188
2189#define IEM_MC_SET_FPU_RESULT(a_FpuData, a_FSW, a_pr80Value) \
2190 do { \
2191 (a_FpuData).FSW = (a_FSW); \
2192 (a_FpuData).r80Result = *(a_pr80Value); \
2193 } while (0)
2194
2195/** Pushes FPU result onto the stack. */
2196#define IEM_MC_PUSH_FPU_RESULT(a_FpuData, a_uFpuOpcode) \
2197 iemFpuPushResult(pVCpu, &a_FpuData, a_uFpuOpcode)
2198/** Pushes FPU result onto the stack and sets the FPUDP. */
2199#define IEM_MC_PUSH_FPU_RESULT_MEM_OP(a_FpuData, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode) \
2200 iemFpuPushResultWithMemOp(pVCpu, &a_FpuData, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode)
2201
2202/** Replaces ST0 with value one and pushes value 2 onto the FPU stack. */
2203#define IEM_MC_PUSH_FPU_RESULT_TWO(a_FpuDataTwo, a_uFpuOpcode) \
2204 iemFpuPushResultTwo(pVCpu, &a_FpuDataTwo, a_uFpuOpcode)
2205
2206/** Stores FPU result in a stack register. */
2207#define IEM_MC_STORE_FPU_RESULT(a_FpuData, a_iStReg, a_uFpuOpcode) \
2208 iemFpuStoreResult(pVCpu, &a_FpuData, a_iStReg, a_uFpuOpcode)
2209/** Stores FPU result in a stack register and pops the stack. */
2210#define IEM_MC_STORE_FPU_RESULT_THEN_POP(a_FpuData, a_iStReg, a_uFpuOpcode) \
2211 iemFpuStoreResultThenPop(pVCpu, &a_FpuData, a_iStReg, a_uFpuOpcode)
2212/** Stores FPU result in a stack register and sets the FPUDP. */
2213#define IEM_MC_STORE_FPU_RESULT_MEM_OP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode) \
2214 iemFpuStoreResultWithMemOp(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode)
2215/** Stores FPU result in a stack register, sets the FPUDP, and pops the
2216 * stack. */
2217#define IEM_MC_STORE_FPU_RESULT_WITH_MEM_OP_THEN_POP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode) \
2218 iemFpuStoreResultWithMemOpThenPop(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode)
2219
2220/** Only update the FOP, FPUIP, and FPUCS. (For FNOP.) */
2221#define IEM_MC_UPDATE_FPU_OPCODE_IP(a_uFpuOpcode) \
2222 iemFpuUpdateOpcodeAndIp(pVCpu, a_uFpuOpcode)
2223/** Free a stack register (for FFREE and FFREEP). */
2224#define IEM_MC_FPU_STACK_FREE(a_iStReg) \
2225 iemFpuStackFree(pVCpu, a_iStReg)
2226/** Increment the FPU stack pointer. */
2227#define IEM_MC_FPU_STACK_INC_TOP() \
2228 iemFpuStackIncTop(pVCpu)
2229/** Decrement the FPU stack pointer. */
2230#define IEM_MC_FPU_STACK_DEC_TOP() \
2231 iemFpuStackDecTop(pVCpu)
2232
2233/** Updates the FSW, FOP, FPUIP, and FPUCS. */
2234#define IEM_MC_UPDATE_FSW(a_u16FSW, a_uFpuOpcode) \
2235 iemFpuUpdateFSW(pVCpu, a_u16FSW, a_uFpuOpcode)
2236/** Updates the FSW with a constant value as well as FOP, FPUIP, and FPUCS. */
2237#define IEM_MC_UPDATE_FSW_CONST(a_u16FSW, a_uFpuOpcode) \
2238 iemFpuUpdateFSW(pVCpu, a_u16FSW, a_uFpuOpcode)
2239/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP, and FPUDS. */
2240#define IEM_MC_UPDATE_FSW_WITH_MEM_OP(a_u16FSW, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode) \
2241 iemFpuUpdateFSWWithMemOp(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode)
2242/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack. */
2243#define IEM_MC_UPDATE_FSW_THEN_POP(a_u16FSW, a_uFpuOpcode) \
2244 iemFpuUpdateFSWThenPop(pVCpu, a_u16FSW, a_uFpuOpcode)
2245/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP and FPUDS, and then pops the
2246 * stack. */
2247#define IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(a_u16FSW, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode) \
2248 iemFpuUpdateFSWWithMemOpThenPop(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode)
2249/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack twice. */
2250#define IEM_MC_UPDATE_FSW_THEN_POP_POP(a_u16FSW, a_uFpuOpcode) \
2251 iemFpuUpdateFSWThenPopPop(pVCpu, a_u16FSW, a_uFpuOpcode)
2252
2253/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. */
2254#define IEM_MC_FPU_STACK_UNDERFLOW(a_iStDst, a_uFpuOpcode) \
2255 iemFpuStackUnderflow(pVCpu, a_iStDst, a_uFpuOpcode)
2256/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
2257 * stack. */
2258#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(a_iStDst, a_uFpuOpcode) \
2259 iemFpuStackUnderflowThenPop(pVCpu, a_iStDst, a_uFpuOpcode)
2260/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
2261 * FPUDS. */
2262#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(a_iStDst, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode) \
2263 iemFpuStackUnderflowWithMemOp(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode)
2264/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
2265 * FPUDS. Pops stack. */
2266#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(a_iStDst, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode) \
2267 iemFpuStackUnderflowWithMemOpThenPop(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode)
2268/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
2269 * stack twice. */
2270#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP(a_uFpuOpcode) \
2271 iemFpuStackUnderflowThenPopPop(pVCpu, a_uFpuOpcode)
2272/** Raises a FPU stack underflow exception for an instruction pushing a result
2273 * value onto the stack. Sets FPUIP, FPUCS and FOP. */
2274#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW(a_uFpuOpcode) \
2275 iemFpuStackPushUnderflow(pVCpu, a_uFpuOpcode)
2276/** Raises a FPU stack underflow exception for an instruction pushing a result
2277 * value onto the stack and replacing ST0. Sets FPUIP, FPUCS and FOP. */
2278#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO(a_uFpuOpcode) \
2279 iemFpuStackPushUnderflowTwo(pVCpu, a_uFpuOpcode)
2280
2281/** Raises a FPU stack overflow exception as part of a push attempt. Sets
2282 * FPUIP, FPUCS and FOP. */
2283#define IEM_MC_FPU_STACK_PUSH_OVERFLOW(a_uFpuOpcode) \
2284 iemFpuStackPushOverflow(pVCpu, a_uFpuOpcode)
2285/** Raises a FPU stack overflow exception as part of a push attempt. Sets
2286 * FPUIP, FPUCS, FOP, FPUDP and FPUDS. */
2287#define IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(a_iEffSeg, a_GCPtrEff, a_uFpuOpcode) \
2288 iemFpuStackPushOverflowWithMemOp(pVCpu, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode)
2289/** Prepares for using the FPU state.
2290 * Ensures that we can use the host FPU in the current context (RC+R0.
2291 * Ensures the guest FPU state in the CPUMCTX is up to date. */
2292#define IEM_MC_PREPARE_FPU_USAGE() iemFpuPrepareUsage(pVCpu)
2293/** Actualizes the guest FPU state so it can be accessed read-only fashion. */
2294#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ() iemFpuActualizeStateForRead(pVCpu)
2295/** Actualizes the guest FPU state so it can be accessed and modified. */
2296#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE() iemFpuActualizeStateForChange(pVCpu)
2297
2298/** Stores SSE SIMD result updating MXCSR. */
2299#define IEM_MC_STORE_SSE_RESULT(a_SseData, a_iXmmReg) \
2300 iemSseStoreResult(pVCpu, &a_SseData, a_iXmmReg)
2301/** Updates MXCSR. */
2302#define IEM_MC_SSE_UPDATE_MXCSR(a_fMxcsr) \
2303 iemSseUpdateMxcsr(pVCpu, a_fMxcsr)
2304
2305/** Prepares for using the SSE state.
2306 * Ensures that we can use the host SSE/FPU in the current context (RC+R0.
2307 * Ensures the guest SSE state in the CPUMCTX is up to date. */
2308#define IEM_MC_PREPARE_SSE_USAGE() iemFpuPrepareUsageSse(pVCpu)
2309/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
2310#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ() iemFpuActualizeSseStateForRead(pVCpu)
2311/** Actualizes the guest XMM0..15 and MXCSR register state for read-write access. */
2312#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE() iemFpuActualizeSseStateForChange(pVCpu)
2313
2314/** Prepares for using the AVX state.
2315 * Ensures that we can use the host AVX/FPU in the current context (RC+R0.
2316 * Ensures the guest AVX state in the CPUMCTX is up to date.
2317 * @note This will include the AVX512 state too when support for it is added
2318 * due to the zero extending feature of VEX instruction. */
2319#define IEM_MC_PREPARE_AVX_USAGE() iemFpuPrepareUsageAvx(pVCpu)
2320/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
2321#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ() iemFpuActualizeAvxStateForRead(pVCpu)
2322/** Actualizes the guest YMM0..15 and MXCSR register state for read-write access. */
2323#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE() iemFpuActualizeAvxStateForChange(pVCpu)
2324
2325/**
2326 * Calls a MMX assembly implementation taking two visible arguments.
2327 *
2328 * @param a_pfnAImpl Pointer to the assembly MMX routine.
2329 * @param a0 The first extra argument.
2330 * @param a1 The second extra argument.
2331 */
2332#define IEM_MC_CALL_MMX_AIMPL_2(a_pfnAImpl, a0, a1) \
2333 do { \
2334 IEM_MC_PREPARE_FPU_USAGE(); \
2335 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
2336 } while (0)
2337
2338/**
2339 * Calls a MMX assembly implementation taking three visible arguments.
2340 *
2341 * @param a_pfnAImpl Pointer to the assembly MMX routine.
2342 * @param a0 The first extra argument.
2343 * @param a1 The second extra argument.
2344 * @param a2 The third extra argument.
2345 */
2346#define IEM_MC_CALL_MMX_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
2347 do { \
2348 IEM_MC_PREPARE_FPU_USAGE(); \
2349 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
2350 } while (0)
2351
2352
2353/**
2354 * Calls a SSE assembly implementation taking two visible arguments.
2355 *
2356 * @param a_pfnAImpl Pointer to the assembly SSE routine.
2357 * @param a0 The first extra argument.
2358 * @param a1 The second extra argument.
2359 */
2360#define IEM_MC_CALL_SSE_AIMPL_2(a_pfnAImpl, a0, a1) \
2361 do { \
2362 IEM_MC_PREPARE_SSE_USAGE(); \
2363 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
2364 } while (0)
2365
2366/**
2367 * Calls a SSE assembly implementation taking three visible arguments.
2368 *
2369 * @param a_pfnAImpl Pointer to the assembly SSE routine.
2370 * @param a0 The first extra argument.
2371 * @param a1 The second extra argument.
2372 * @param a2 The third extra argument.
2373 */
2374#define IEM_MC_CALL_SSE_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
2375 do { \
2376 IEM_MC_PREPARE_SSE_USAGE(); \
2377 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
2378 } while (0)
2379
2380
2381/** Declares implicit arguments for IEM_MC_CALL_AVX_AIMPL_2,
2382 * IEM_MC_CALL_AVX_AIMPL_3, IEM_MC_CALL_AVX_AIMPL_4, ...
2383 * @note IEMAllInstPython.py duplicates the expansion. */
2384#define IEM_MC_IMPLICIT_AVX_AIMPL_ARGS() \
2385 IEM_MC_ARG_CONST(PX86XSAVEAREA, pXState, &pVCpu->cpum.GstCtx.XState, 0)
2386
2387/**
2388 * Calls a AVX assembly implementation taking two visible arguments.
2389 *
2390 * There is one implicit zero'th argument, a pointer to the extended state.
2391 *
2392 * @param a_pfnAImpl Pointer to the assembly AVX routine.
2393 * @param a1 The first extra argument.
2394 * @param a2 The second extra argument.
2395 */
2396#define IEM_MC_CALL_AVX_AIMPL_2(a_pfnAImpl, a1, a2) \
2397 do { \
2398 IEM_MC_PREPARE_AVX_USAGE(); \
2399 a_pfnAImpl(pXState, (a1), (a2)); \
2400 } while (0)
2401
2402/**
2403 * Calls a AVX assembly implementation taking three visible arguments.
2404 *
2405 * There is one implicit zero'th argument, a pointer to the extended state.
2406 *
2407 * @param a_pfnAImpl Pointer to the assembly AVX routine.
2408 * @param a1 The first extra argument.
2409 * @param a2 The second extra argument.
2410 * @param a3 The third extra argument.
2411 */
2412#define IEM_MC_CALL_AVX_AIMPL_3(a_pfnAImpl, a1, a2, a3) \
2413 do { \
2414 IEM_MC_PREPARE_AVX_USAGE(); \
2415 a_pfnAImpl(pXState, (a1), (a2), (a3)); \
2416 } while (0)
2417
2418/** @note Not for IOPL or IF testing. */
2419#define IEM_MC_IF_EFL_BIT_SET(a_fBit) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) {
2420/** @note Not for IOPL or IF testing. */
2421#define IEM_MC_IF_EFL_BIT_NOT_SET(a_fBit) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit))) {
2422/** @note Not for IOPL or IF testing. */
2423#define IEM_MC_IF_EFL_ANY_BITS_SET(a_fBits) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBits)) {
2424/** @note Not for IOPL or IF testing. */
2425#define IEM_MC_IF_EFL_NO_BITS_SET(a_fBits) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBits))) {
2426/** @note Not for IOPL or IF testing. */
2427#define IEM_MC_IF_EFL_BITS_NE(a_fBit1, a_fBit2) \
2428 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
2429 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
2430/** @note Not for IOPL or IF testing. */
2431#define IEM_MC_IF_EFL_BITS_EQ(a_fBit1, a_fBit2) \
2432 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
2433 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
2434/** @note Not for IOPL or IF testing. */
2435#define IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(a_fBit, a_fBit1, a_fBit2) \
2436 if ( (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
2437 || !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
2438 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
2439/** @note Not for IOPL or IF testing. */
2440#define IEM_MC_IF_EFL_BIT_NOT_SET_AND_BITS_EQ(a_fBit, a_fBit1, a_fBit2) \
2441 if ( !(pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
2442 && !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
2443 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
2444#define IEM_MC_IF_CX_IS_NZ() if (pVCpu->cpum.GstCtx.cx != 0) {
2445#define IEM_MC_IF_ECX_IS_NZ() if (pVCpu->cpum.GstCtx.ecx != 0) {
2446#define IEM_MC_IF_RCX_IS_NZ() if (pVCpu->cpum.GstCtx.rcx != 0) {
2447/** @note Not for IOPL or IF testing. */
2448#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
2449 if ( pVCpu->cpum.GstCtx.cx != 0 \
2450 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
2451/** @note Not for IOPL or IF testing. */
2452#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
2453 if ( pVCpu->cpum.GstCtx.ecx != 0 \
2454 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
2455/** @note Not for IOPL or IF testing. */
2456#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
2457 if ( pVCpu->cpum.GstCtx.rcx != 0 \
2458 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
2459/** @note Not for IOPL or IF testing. */
2460#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
2461 if ( pVCpu->cpum.GstCtx.cx != 0 \
2462 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
2463/** @note Not for IOPL or IF testing. */
2464#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
2465 if ( pVCpu->cpum.GstCtx.ecx != 0 \
2466 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
2467/** @note Not for IOPL or IF testing. */
2468#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
2469 if ( pVCpu->cpum.GstCtx.rcx != 0 \
2470 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
2471#define IEM_MC_IF_LOCAL_IS_Z(a_Local) if ((a_Local) == 0) {
2472#define IEM_MC_IF_GREG_BIT_SET(a_iGReg, a_iBitNo) if (iemGRegFetchU64(pVCpu, (a_iGReg)) & RT_BIT_64(a_iBitNo)) {
2473
2474#define IEM_MC_REF_FPUREG(a_pr80Dst, a_iSt) \
2475 do { (a_pr80Dst) = &pVCpu->cpum.GstCtx.XState.x87.aRegs[a_iSt].r80; } while (0)
2476#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
2477 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
2478#define IEM_MC_IF_FPUREG_NOT_EMPTY(a_iSt) \
2479 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) == VINF_SUCCESS) {
2480#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
2481 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
2482#define IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(a_pr80Dst, a_iSt) \
2483 if (iemFpuStRegNotEmptyRef(pVCpu, (a_iSt), &(a_pr80Dst)) == VINF_SUCCESS) {
2484#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(a_pr80Dst0, a_iSt0, a_pr80Dst1, a_iSt1) \
2485 if (iemFpu2StRegsNotEmptyRef(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1), &(a_pr80Dst1)) == VINF_SUCCESS) {
2486#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(a_pr80Dst0, a_iSt0, a_iSt1) \
2487 if (iemFpu2StRegsNotEmptyRefFirst(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1)) == VINF_SUCCESS) {
2488#define IEM_MC_IF_FCW_IM() \
2489 if (pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_IM) {
2490#define IEM_MC_IF_MXCSR_XCPT_PENDING() \
2491 if (( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
2492 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) != 0) {
2493
2494#define IEM_MC_ELSE() } else {
2495#define IEM_MC_ENDIF() } do {} while (0)
2496
2497/** @} */
2498
2499#endif /* !VMM_INCLUDED_SRC_include_IEMMc_h */
2500
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