IEMInternal.h@ 105664

最後變更在這個檔案從105664是 105664,由 vboxsync 提交於 7 月前
VMM/IEM: Implement vgather[dq]p[sd], vpgather[dq][dq] instruction decoding, dispatch & emulation, bugref:9898 VMM/IEM: Fix disassembly metadata for vpsllvq, vpsrlvq instructions VMM/IEM: Adds MVx VSIB operand handling VMM/IEM: Adds iemMemFetchDataU32NoAc(), iemMemFetchDataU64NoAc() unaligned memory fetchers
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1	/* $Id: IEMInternal.h 105664 2024-08-14 08:47:13Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.alldomusa.eu.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
29	#define VMM_INCLUDED_SRC_include_IEMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#ifndef RT_IN_ASSEMBLER
35	# include <VBox/vmm/cpum.h>
36	# include <VBox/vmm/iem.h>
37	# include <VBox/vmm/pgm.h>
38	# include <VBox/vmm/stam.h>
39	# include <VBox/param.h>
40
41	# include <iprt/setjmp-without-sigmask.h>
42	# include <iprt/list.h>
43	#endif /* !RT_IN_ASSEMBLER */
44
45
46	RT_C_DECLS_BEGIN
47
48
49	/** @defgroup grp_iem_int Internals
50	* @ingroup grp_iem
51	* @internal
52	* @{
53	*/
54
55	/* Make doxygen happy w/o overcomplicating the #if checks. */
56	#ifdef DOXYGEN_RUNNING
57	# define IEM_WITH_THROW_CATCH
58	# define VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
59	#endif
60
61	/** For expanding symbol in slickedit and other products tagging and
62	* crossreferencing IEM symbols. */
63	#ifndef IEM_STATIC
64	# define IEM_STATIC static
65	#endif
66
67	/** @def IEM_WITH_SETJMP
68	* Enables alternative status code handling using setjmps.
69	*
70	* This adds a bit of expense via the setjmp() call since it saves all the
71	* non-volatile registers. However, it eliminates return code checks and allows
72	* for more optimal return value passing (return regs instead of stack buffer).
73	*/
74	#if defined(DOXYGEN_RUNNING) \|\| defined(RT_OS_WINDOWS) \|\| 1
75	# define IEM_WITH_SETJMP
76	#endif
77
78	/** @def IEM_WITH_THROW_CATCH
79	* Enables using C++ throw/catch as an alternative to setjmp/longjmp in user
80	* mode code when IEM_WITH_SETJMP is in effect.
81	*
82	* With GCC 11.3.1 and code TLB on linux, using throw/catch instead of
83	* setjmp/long resulted in bs2-test-1 running 3.00% faster and all but on test
84	* result value improving by more than 1%. (Best out of three.)
85	*
86	* With Visual C++ 2019 and code TLB on windows, using throw/catch instead of
87	* setjmp/long resulted in bs2-test-1 running 3.68% faster and all but some of
88	* the MMIO and CPUID tests ran noticeably faster. Variation is greater than on
89	* Linux, but it should be quite a bit faster for normal code.
90	*/
91	#if defined(__cplusplus) && defined(IEM_WITH_SETJMP) && defined(IN_RING3) && (defined(__GNUC__) \|\| defined(_MSC_VER)) /* ASM-NOINC-START */
92	# define IEM_WITH_THROW_CATCH
93	#endif /ASM-NOINC-END/
94
95	/** @def IEMNATIVE_WITH_DELAYED_PC_UPDATING
96	* Enables the delayed PC updating optimization (see @bugref{10373}).
97	*/
98	#if defined(DOXYGEN_RUNNING) \|\| 1
99	# define IEMNATIVE_WITH_DELAYED_PC_UPDATING
100	#endif
101
102	/** Enables the SIMD register allocator @bugref{10614}. */
103	#if defined(DOXYGEN_RUNNING) \|\| 1
104	# define IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
105	#endif
106	/** Enables access to even callee saved registers. */
107	//# define IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS
108
109	#if defined(DOXYGEN_RUNNING) \|\| 1
110	/** @def IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
111	* Delay the writeback or dirty registers as long as possible. */
112	# define IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
113	#endif
114
115	/** @def IEM_WITH_TLB_STATISTICS
116	* Enables all TLB statistics. */
117	#if defined(VBOX_WITH_STATISTICS) \|\| defined(DOXYGEN_RUNNING)
118	# define IEM_WITH_TLB_STATISTICS
119	#endif
120
121	/** @def IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS
122	* Enable this to use native emitters for certain SIMD FP operations. */
123	#if 1 \|\| defined(DOXYGEN_RUNNING)
124	# define IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS
125	#endif
126
127	/** @def VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
128	* Enables a quicker alternative to throw/longjmp for IEM_DO_LONGJMP when
129	* executing native translation blocks.
130	*
131	* This exploits the fact that we save all non-volatile registers in the TB
132	* prologue and thus just need to do the same as the TB epilogue to get the
133	* effect of a longjmp/throw. Since MSC marks XMM6 thru XMM15 as
134	* non-volatile (and does something even more crazy for ARM), this probably
135	* won't work reliably on Windows. */
136	#ifdef RT_ARCH_ARM64
137	# ifndef RT_OS_WINDOWS
138	# define VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
139	# endif
140	#endif
141	/* ASM-NOINC-START */
142	#ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
143	# if !defined(IN_RING3) \
144	\|\| !defined(VBOX_WITH_IEM_RECOMPILER) \
145	\|\| !defined(VBOX_WITH_IEM_NATIVE_RECOMPILER)
146	# undef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
147	# elif defined(RT_OS_WINDOWS)
148	# pragma message("VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP is not safe to use on windows")
149	# endif
150	#endif
151
152
153	/** @def IEM_DO_LONGJMP
154	*
155	* Wrapper around longjmp / throw.
156	*
157	* @param a_pVCpu The CPU handle.
158	* @param a_rc The status code jump back with / throw.
159	*/
160	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
161	# ifdef IEM_WITH_THROW_CATCH
162	# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
163	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) do { \
164	if ((a_pVCpu)->iem.s.pvTbFramePointerR3) \
165	iemNativeTbLongJmp((a_pVCpu)->iem.s.pvTbFramePointerR3, (a_rc)); \
166	throw int(a_rc); \
167	} while (0)
168	# else
169	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) throw int(a_rc)
170	# endif
171	# else
172	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
173	# endif
174	#endif
175
176	/** For use with IEM function that may do a longjmp (when enabled).
177	*
178	* Visual C++ has trouble longjmp'ing from/over functions with the noexcept
179	* attribute. So, we indicate that function that may be part of a longjmp may
180	* throw "exceptions" and that the compiler should definitely not generate and
181	* std::terminate calling unwind code.
182	*
183	* Here is one example of this ending in std::terminate:
184	* @code{.txt}
185	00 00000041`cadfda10 00007ffc`5d5a1f9f ucrtbase!abort+0x4e
186	01 00000041`cadfda40 00007ffc`57af229a ucrtbase!terminate+0x1f
187	02 00000041`cadfda70 00007ffb`eec91030 VCRUNTIME140!__std_terminate+0xa [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\ehhelpers.cpp @ 192]
188	03 00000041`cadfdaa0 00007ffb`eec92c6d VCRUNTIME140_1!_CallSettingFrame+0x20 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\handlers.asm @ 50]
189	04 00000041`cadfdad0 00007ffb`eec93ae5 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToState+0x241 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 1085]
190	05 00000041`cadfdc00 00007ffb`eec92258 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToEmptyState+0x2d [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 218]
191	06 00000041`cadfdc30 00007ffb`eec940e9 VCRUNTIME140_1!__InternalCxxFrameHandler<__FrameHandler4>+0x194 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 304]
192	07 00000041`cadfdcd0 00007ffc`5f9f249f VCRUNTIME140_1!__CxxFrameHandler4+0xa9 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 290]
193	08 00000041`cadfdd40 00007ffc`5f980939 ntdll!RtlpExecuteHandlerForUnwind+0xf
194	09 00000041`cadfdd70 00007ffc`5f9a0edd ntdll!RtlUnwindEx+0x339
195	0a 00000041`cadfe490 00007ffc`57aff976 ntdll!RtlUnwind+0xcd
196	0b 00000041`cadfea00 00007ffb`e1b5de01 VCRUNTIME140!__longjmp_internal+0xe6 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\longjmp.asm @ 140]
197	0c (Inline Function) --------`-------- VBoxVMM!iemOpcodeGetNextU8SlowJmp+0x95 [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 1155]
198	0d 00000041`cadfea50 00007ffb`e1b60f6b VBoxVMM!iemOpcodeGetNextU8Jmp+0xc1 [L:\vbox-intern\src\VBox\VMM\include\IEMInline.h @ 402]
199	0e 00000041`cadfea90 00007ffb`e1cc6201 VBoxVMM!IEMExecForExits+0xdb [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 10185]
200	0f 00000041`cadfec70 00007ffb`e1d0df8d VBoxVMM!EMHistoryExec+0x4f1 [L:\vbox-intern\src\VBox\VMM\VMMAll\EMAll.cpp @ 452]
201	10 00000041`cadfed60 00007ffb`e1d0d4c0 VBoxVMM!nemR3WinHandleExitCpuId+0x79d [L:\vbox-intern\src\VBox\VMM\VMMAll\NEMAllNativeTemplate-win.cpp.h @ 1829] @encode
202	@endcode
203	*
204	* @see https://developercommunity.visualstudio.com/t/fragile-behavior-of-longjmp-called-from-noexcept-f/1532859
205	*/
206	#if defined(IEM_WITH_SETJMP) && (defined(_MSC_VER) \|\| defined(IEM_WITH_THROW_CATCH))
207	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT_EX(false)
208	#else
209	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT
210	#endif
211	/* ASM-NOINC-END */
212
213	#define IEM_IMPLEMENTS_TASKSWITCH
214
215	/** @def IEM_WITH_3DNOW
216	* Includes the 3DNow decoding. */
217	#if !defined(IEM_WITH_3DNOW) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
218	# ifndef IEM_WITHOUT_3DNOW
219	# define IEM_WITH_3DNOW
220	# endif
221	#endif
222
223	/** @def IEM_WITH_THREE_0F_38
224	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
225	#if !defined(IEM_WITH_THREE_0F_38) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
226	# ifndef IEM_WITHOUT_THREE_0F_38
227	# define IEM_WITH_THREE_0F_38
228	# endif
229	#endif
230
231	/** @def IEM_WITH_THREE_0F_3A
232	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
233	#if !defined(IEM_WITH_THREE_0F_3A) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
234	# ifndef IEM_WITHOUT_THREE_0F_3A
235	# define IEM_WITH_THREE_0F_3A
236	# endif
237	#endif
238
239	/** @def IEM_WITH_VEX
240	* Includes the VEX decoding. */
241	#if !defined(IEM_WITH_VEX) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
242	# ifndef IEM_WITHOUT_VEX
243	# define IEM_WITH_VEX
244	# endif
245	#endif
246
247	/** @def IEM_CFG_TARGET_CPU
248	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
249	*
250	* By default we allow this to be configured by the user via the
251	* CPUM/GuestCpuName config string, but this comes at a slight cost during
252	* decoding. So, for applications of this code where there is no need to
253	* be dynamic wrt target CPU, just modify this define.
254	*/
255	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
256	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
257	#endif
258
259	//#define IEM_WITH_CODE_TLB // - work in progress
260	//#define IEM_WITH_DATA_TLB // - work in progress
261
262
263	/** @def IEM_USE_UNALIGNED_DATA_ACCESS
264	* Use unaligned accesses instead of elaborate byte assembly. */
265	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(DOXYGEN_RUNNING) /ASM-NOINC/
266	# define IEM_USE_UNALIGNED_DATA_ACCESS
267	#endif /ASM-NOINC/
268
269	//#define IEM_LOG_MEMORY_WRITES
270
271
272
273	#ifndef RT_IN_ASSEMBLER /* ASM-NOINC-START - the rest of the file */
274
275	# if !defined(IEM_WITHOUT_INSTRUCTION_STATS) && !defined(DOXYGEN_RUNNING)
276	/** Instruction statistics. */
277	typedef struct IEMINSTRSTATS
278	{
279	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
280	# include "IEMInstructionStatisticsTmpl.h"
281	# undef IEM_DO_INSTR_STAT
282	} IEMINSTRSTATS;
283	#else
284	struct IEMINSTRSTATS;
285	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
286	#endif
287	/** Pointer to IEM instruction statistics. */
288	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
289
290
291	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
292	* @{ */
293	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
294	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
295	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
296	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
297	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
298	/** Selects the right variant from a_aArray.
299	* pVCpu is implicit in the caller context. */
300	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
301	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
302	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
303	* be used because the host CPU does not support the operation. */
304	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
305	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
306	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
307	* array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
308	* into the two.
309	* @sa IEM_SELECT_NATIVE_OR_FALLBACK */
310	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
311	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
312	(a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
313	#else
314	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
315	(a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
316	#endif
317	/** @} */
318
319	/**
320	* Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
321	* indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
322	*
323	* On non-x86 hosts, this will shortcut to the fallback w/o checking the
324	* indicator.
325	*
326	* @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
327	*/
328	#if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
329	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
330	(g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
331	#else
332	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
333	#endif
334
335
336	/**
337	* Branch types.
338	*/
339	typedef enum IEMBRANCH
340	{
341	IEMBRANCH_JUMP = 1,
342	IEMBRANCH_CALL,
343	IEMBRANCH_TRAP,
344	IEMBRANCH_SOFTWARE_INT,
345	IEMBRANCH_HARDWARE_INT
346	} IEMBRANCH;
347	AssertCompileSize(IEMBRANCH, 4);
348
349
350	/**
351	* INT instruction types.
352	*/
353	typedef enum IEMINT
354	{
355	/** INT n instruction (opcode 0xcd imm). */
356	IEMINT_INTN = 0,
357	/** Single byte INT3 instruction (opcode 0xcc). */
358	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
359	/** Single byte INTO instruction (opcode 0xce). */
360	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
361	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
362	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
363	} IEMINT;
364	AssertCompileSize(IEMINT, 4);
365
366
367	/**
368	* A FPU result.
369	*/
370	typedef struct IEMFPURESULT
371	{
372	/** The output value. */
373	RTFLOAT80U r80Result;
374	/** The output status. */
375	uint16_t FSW;
376	} IEMFPURESULT;
377	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
378	/** Pointer to a FPU result. */
379	typedef IEMFPURESULT *PIEMFPURESULT;
380	/** Pointer to a const FPU result. */
381	typedef IEMFPURESULT const *PCIEMFPURESULT;
382
383
384	/**
385	* A FPU result consisting of two output values and FSW.
386	*/
387	typedef struct IEMFPURESULTTWO
388	{
389	/** The first output value. */
390	RTFLOAT80U r80Result1;
391	/** The output status. */
392	uint16_t FSW;
393	/** The second output value. */
394	RTFLOAT80U r80Result2;
395	} IEMFPURESULTTWO;
396	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
397	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
398	/** Pointer to a FPU result consisting of two output values and FSW. */
399	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
400	/** Pointer to a const FPU result consisting of two output values and FSW. */
401	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
402
403
404	/**
405	* IEM TLB entry.
406	*
407	* Lookup assembly:
408	* @code{.asm}
409	; Calculate tag.
410	mov rax, [VA]
411	shl rax, 16
412	shr rax, 16 + X86_PAGE_SHIFT
413	or rax, [uTlbRevision]
414
415	; Do indexing.
416	movzx ecx, al
417	lea rcx, [pTlbEntries + rcx]
418
419	; Check tag.
420	cmp [rcx + IEMTLBENTRY.uTag], rax
421	jne .TlbMiss
422
423	; Check access.
424	mov rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
425	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
426	cmp rax, [uTlbPhysRev]
427	jne .TlbMiss
428
429	; Calc address and we're done.
430	mov eax, X86_PAGE_OFFSET_MASK
431	and eax, [VA]
432	or rax, [rcx + IEMTLBENTRY.pMappingR3]
433	%ifdef VBOX_WITH_STATISTICS
434	inc qword [cTlbHits]
435	%endif
436	jmp .Done
437
438	.TlbMiss:
439	mov r8d, ACCESS_FLAGS
440	mov rdx, [VA]
441	mov rcx, [pVCpu]
442	call iemTlbTypeMiss
443	.Done:
444
445	@endcode
446	*
447	*/
448	typedef struct IEMTLBENTRY
449	{
450	/** The TLB entry tag.
451	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
452	* is ASSUMING a virtual address width of 48 bits.
453	*
454	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
455	*
456	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
457	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
458	* revision wraps around though, the tags needs to be zeroed.
459	*
460	* @note Try use SHRD instruction? After seeing
461	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
462	*
463	* @todo This will need to be reorganized for 57-bit wide virtual address and
464	* PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
465	* have to move the TLB entry versioning entirely to the
466	* fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
467	* 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
468	* consumed by PCID and ASID (12 + 6 = 18).
469	*/
470	uint64_t uTag;
471	/** Access flags and physical TLB revision.
472	*
473	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
474	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
475	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
476	* - Bit 3 - pgm phys/virt - not directly writable.
477	* - Bit 4 - pgm phys page - not directly readable.
478	* - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
479	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
480	* - Bit 7 - tlb entry - pMappingR3 member not valid.
481	* - Bits 63 thru 8 are used for the physical TLB revision number.
482	*
483	* We're using complemented bit meanings here because it makes it easy to check
484	* whether special action is required. For instance a user mode write access
485	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
486	* non-zero result would mean special handling needed because either it wasn't
487	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
488	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
489	* need to check any PTE flag.
490	*/
491	uint64_t fFlagsAndPhysRev;
492	/** The guest physical page address. */
493	uint64_t GCPhys;
494	/** Pointer to the ring-3 mapping. */
495	R3PTRTYPE(uint8_t *) pbMappingR3;
496	#if HC_ARCH_BITS == 32
497	uint32_t u32Padding1;
498	#endif
499	} IEMTLBENTRY;
500	AssertCompileSize(IEMTLBENTRY, 32);
501	/** Pointer to an IEM TLB entry. */
502	typedef IEMTLBENTRY *PIEMTLBENTRY;
503	/** Pointer to a const IEM TLB entry. */
504	typedef IEMTLBENTRY const *PCIEMTLBENTRY;
505
506	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
507	* @{ */
508	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
509	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
510	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
511	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
512	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
513	#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /*< Phys tables: Not accessed (need to be marked accessed). /
514	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
515	#define IEMTLBE_F_PT_LARGE_PAGE RT_BIT_64(7) /*< Page tables: Large 2 or 4 MiB page (for flushing). /
516	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(8) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
517	#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(9) /*< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). /
518	#define IEMTLBE_F_PG_CODE_PAGE RT_BIT_64(10) /*< Phys page: Code page. /
519	#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffff800) /*< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR /
520	/** @} */
521	AssertCompile(PGMIEMGCPHYS2PTR_F_NO_WRITE == IEMTLBE_F_PG_NO_WRITE);
522	AssertCompile(PGMIEMGCPHYS2PTR_F_NO_READ == IEMTLBE_F_PG_NO_READ);
523	AssertCompile(PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 == IEMTLBE_F_NO_MAPPINGR3);
524	AssertCompile(PGMIEMGCPHYS2PTR_F_UNASSIGNED == IEMTLBE_F_PG_UNASSIGNED);
525	AssertCompile(PGMIEMGCPHYS2PTR_F_CODE_PAGE == IEMTLBE_F_PG_CODE_PAGE);
526	AssertCompile(PGM_WALKINFO_BIG_PAGE == IEMTLBE_F_PT_LARGE_PAGE);
527	/** The bits set by PGMPhysIemGCPhys2PtrNoLock. */
528	#define IEMTLBE_GCPHYS2PTR_MASK ( PGMIEMGCPHYS2PTR_F_NO_WRITE \
529	\| PGMIEMGCPHYS2PTR_F_NO_READ \
530	\| PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 \
531	\| PGMIEMGCPHYS2PTR_F_UNASSIGNED \
532	\| PGMIEMGCPHYS2PTR_F_CODE_PAGE \
533	\| IEMTLBE_F_PHYS_REV )
534
535
536	/** The TLB size (power of two).
537	* We initially chose 256 because that way we can obtain the result directly
538	* from a 8-bit register without an additional AND instruction.
539	* See also @bugref{10687}. */
540	#if defined(RT_ARCH_AMD64)
541	# define IEMTLB_ENTRY_COUNT 256
542	# define IEMTLB_ENTRY_COUNT_AS_POWER_OF_TWO 8
543	#else
544	# define IEMTLB_ENTRY_COUNT 8192
545	# define IEMTLB_ENTRY_COUNT_AS_POWER_OF_TWO 13
546	#endif
547	AssertCompile(RT_BIT_32(IEMTLB_ENTRY_COUNT_AS_POWER_OF_TWO) == IEMTLB_ENTRY_COUNT);
548
549	/** TLB slot format spec (assumes uint32_t or unsigned value). */
550	#if IEMTLB_ENTRY_COUNT <= 0x100 / 2
551	# define IEMTLB_SLOT_FMT "%02x"
552	#elif IEMTLB_ENTRY_COUNT <= 0x1000 / 2
553	# define IEMTLB_SLOT_FMT "%03x"
554	#elif IEMTLB_ENTRY_COUNT <= 0x10000 / 2
555	# define IEMTLB_SLOT_FMT "%04x"
556	#else
557	# define IEMTLB_SLOT_FMT "%05x"
558	#endif
559
560	/** Enable the large page bitmap TLB optimization.
561	*
562	* The idea here is to avoid scanning the full 32 KB (2MB pages, 2*512 TLB
563	* entries) or 64 KB (4MB pages, 2*1024 TLB entries) worth of TLB entries during
564	* invlpg when large pages are used, and instead just scan 128 or 256 bytes of
565	* the bmLargePage bitmap to determin which TLB entires that might be containing
566	* large pages and actually require checking.
567	*
568	* There is a good posibility of false positives since we currently don't clear
569	* the bitmap when flushing the TLB, but it should help reduce the workload when
570	* the large pages aren't fully loaded into the TLB in their entirity...
571	*/
572	#define IEMTLB_WITH_LARGE_PAGE_BITMAP
573
574	/**
575	* An IEM TLB.
576	*
577	* We've got two of these, one for data and one for instructions.
578	*/
579	typedef struct IEMTLB
580	{
581	/** The non-global TLB revision.
582	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
583	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
584	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
585	* (The revision zero indicates an invalid TLB entry.)
586	*
587	* The initial value is choosen to cause an early wraparound. */
588	uint64_t uTlbRevision;
589	/** The TLB physical address revision - shadow of PGM variable.
590	*
591	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
592	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
593	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
594	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
595	*
596	* The initial value is choosen to cause an early wraparound.
597	*
598	* @note This is placed between the two TLB revisions because we
599	* load it in pair with one or the other on arm64. */
600	uint64_t volatile uTlbPhysRev;
601	/** The global TLB revision.
602	* Same as uTlbRevision, but only increased for global flushes. */
603	uint64_t uTlbRevisionGlobal;
604
605	/** Large page tag range.
606	*
607	* This is used to avoid scanning a large page's worth of TLB entries for each
608	* INVLPG instruction, and only to do so iff we've loaded any and when the
609	* address is in this range. This is kept up to date when we loading new TLB
610	* entries.
611	*/
612	struct LARGEPAGERANGE
613	{
614	/** The lowest large page address tag, UINT64_MAX if none. */
615	uint64_t uFirstTag;
616	/** The highest large page address tag (with offset mask part set), 0 if none. */
617	uint64_t uLastTag;
618	}
619	/** Large page range for non-global pages. */
620	NonGlobalLargePageRange,
621	/** Large page range for global pages. */
622	GlobalLargePageRange;
623	/** Number of non-global entries for large pages loaded since last TLB flush. */
624	uint32_t cTlbNonGlobalLargePageCurLoads;
625	/** Number of global entries for large pages loaded since last TLB flush. */
626	uint32_t cTlbGlobalLargePageCurLoads;
627
628	/* Statistics: */
629
630	/** TLB hits in IEMAll.cpp code (IEM_WITH_TLB_STATISTICS only; both).
631	* @note For the data TLB this is only used in iemMemMap and and for direct (i.e.
632	* not via safe read/write path) calls to iemMemMapJmp. */
633	uint64_t cTlbCoreHits;
634	/** Safe read/write TLB hits in iemMemMapJmp (IEM_WITH_TLB_STATISTICS
635	* only; data tlb only). */
636	uint64_t cTlbSafeHits;
637	/** TLB hits in IEMAllMemRWTmplInline.cpp.h (data + IEM_WITH_TLB_STATISTICS only). */
638	uint64_t cTlbInlineCodeHits;
639
640	/** TLB misses in IEMAll.cpp code (both).
641	* @note For the data TLB this is only used in iemMemMap and for direct (i.e.
642	* not via safe read/write path) calls to iemMemMapJmp. So,
643	* for the data TLB this more like 'other misses', while for the code
644	* TLB is all misses. */
645	uint64_t cTlbCoreMisses;
646	/** Subset of cTlbCoreMisses that results in PTE.G=1 loads (odd entries). */
647	uint64_t cTlbCoreGlobalLoads;
648	/** Safe read/write TLB misses in iemMemMapJmp (so data only). */
649	uint64_t cTlbSafeMisses;
650	/** Subset of cTlbSafeMisses that results in PTE.G=1 loads (odd entries). */
651	uint64_t cTlbSafeGlobalLoads;
652	/** Safe read path taken (data only). */
653	uint64_t cTlbSafeReadPath;
654	/** Safe write path taken (data only). */
655	uint64_t cTlbSafeWritePath;
656
657	/** @name Details for native code TLB misses.
658	* @note These counts are included in the above counters (cTlbSafeReadPath,
659	* cTlbSafeWritePath, cTlbInlineCodeHits).
660	* @{ */
661	/** TLB misses in native code due to tag mismatch. */
662	STAMCOUNTER cTlbNativeMissTag;
663	/** TLB misses in native code due to flags or physical revision mismatch. */
664	STAMCOUNTER cTlbNativeMissFlagsAndPhysRev;
665	/** TLB misses in native code due to misaligned access. */
666	STAMCOUNTER cTlbNativeMissAlignment;
667	/** TLB misses in native code due to cross page access. */
668	uint32_t cTlbNativeMissCrossPage;
669	/** TLB misses in native code due to non-canonical address. */
670	uint32_t cTlbNativeMissNonCanonical;
671	/** @} */
672
673	/** Slow read path (code only). */
674	uint32_t cTlbSlowCodeReadPath;
675
676	/** Regular TLB flush count. */
677	uint32_t cTlsFlushes;
678	/** Global TLB flush count. */
679	uint32_t cTlsGlobalFlushes;
680	/** Revision rollovers. */
681	uint32_t cTlbRevisionRollovers;
682	/** Physical revision flushes. */
683	uint32_t cTlbPhysRevFlushes;
684	/** Physical revision rollovers. */
685	uint32_t cTlbPhysRevRollovers;
686
687	/** Number of INVLPG (and similar) operations. */
688	uint32_t cTlbInvlPg;
689	/** Subset of cTlbInvlPg that involved non-global large pages. */
690	uint32_t cTlbInvlPgLargeNonGlobal;
691	/** Subset of cTlbInvlPg that involved global large pages. */
692	uint32_t cTlbInvlPgLargeGlobal;
693
694	uint32_t au32Padding[13];
695
696	/** The TLB entries.
697	* Even entries are for PTE.G=0 and uses uTlbRevision.
698	* Odd entries are for PTE.G=1 and uses uTlbRevisionGlobal. */
699	IEMTLBENTRY aEntries[IEMTLB_ENTRY_COUNT * 2];
700	#ifdef IEMTLB_WITH_LARGE_PAGE_BITMAP
701	/** Bitmap tracking TLB entries for large pages.
702	* This duplicates IEMTLBE_F_PT_LARGE_PAGE for each TLB entry. */
703	uint64_t bmLargePage[IEMTLB_ENTRY_COUNT * 2 / 64];
704	#endif
705	} IEMTLB;
706	AssertCompileSizeAlignment(IEMTLB, 64);
707	#ifdef IEMTLB_WITH_LARGE_PAGE_BITMAP
708	AssertCompile(IEMTLB_ENTRY_COUNT >= 32 /* bmLargePage ASSUMPTION */);
709	#endif
710	/** The width (in bits) of the address portion of the TLB tag. */
711	#define IEMTLB_TAG_ADDR_WIDTH 36
712	/** IEMTLB::uTlbRevision increment. */
713	#define IEMTLB_REVISION_INCR RT_BIT_64(IEMTLB_TAG_ADDR_WIDTH)
714	/** IEMTLB::uTlbRevision mask. */
715	#define IEMTLB_REVISION_MASK (~(RT_BIT_64(IEMTLB_TAG_ADDR_WIDTH) - 1))
716
717	/** IEMTLB::uTlbPhysRev increment.
718	* @sa IEMTLBE_F_PHYS_REV */
719	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(11)
720	AssertCompile(IEMTLBE_F_PHYS_REV == ~(IEMTLB_PHYS_REV_INCR - 1U));
721
722	/**
723	* Calculates the TLB tag for a virtual address but without TLB revision.
724	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
725	* @param a_GCPtr The virtual address. Must be RTGCPTR or same size or
726	* the clearing of the top 16 bits won't work (if 32-bit
727	* we'll end up with mostly zeros).
728	*/
729	#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
730	/**
731	* Converts a TLB tag value into a even TLB index.
732	* @returns Index into IEMTLB::aEntries.
733	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
734	*/
735	#if IEMTLB_ENTRY_COUNT == 256
736	# define IEMTLB_TAG_TO_EVEN_INDEX(a_uTag) ( (uint8_t)(a_uTag) * 2U )
737	#else
738	# define IEMTLB_TAG_TO_EVEN_INDEX(a_uTag) ( ((a_uTag) & (IEMTLB_ENTRY_COUNT - 1U)) * 2U )
739	AssertCompile(RT_IS_POWER_OF_TWO(IEMTLB_ENTRY_COUNT));
740	#endif
741	/**
742	* Converts a TLB tag value into an even TLB index.
743	* @returns Pointer into IEMTLB::aEntries corresponding to .
744	* @param a_pTlb The TLB.
745	* @param a_uTag Value returned by IEMTLB_CALC_TAG or
746	* IEMTLB_CALC_TAG_NO_REV.
747	*/
748	#define IEMTLB_TAG_TO_EVEN_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_EVEN_INDEX(a_uTag)] )
749
750	/** Converts a GC address to an even TLB index. */
751	#define IEMTLB_ADDR_TO_EVEN_INDEX(a_GCPtr) IEMTLB_TAG_TO_EVEN_INDEX(IEMTLB_CALC_TAG_NO_REV(a_GCPtr))
752
753
754	/** @def IEM_WITH_TLB_TRACE
755	* Enables the TLB tracing.
756	* Adjust buffer size in IEMR3Init. */
757	#if defined(DOXYGEN_RUNNING) \|\| 0
758	# define IEM_WITH_TLB_TRACE
759	#endif
760
761	#ifdef IEM_WITH_TLB_TRACE
762
763	/** TLB trace entry types. */
764	typedef enum : uint8_t
765	{
766	kIemTlbTraceType_Invalid,
767	kIemTlbTraceType_InvlPg,
768	kIemTlbTraceType_EvictSlot,
769	kIemTlbTraceType_LargeEvictSlot,
770	kIemTlbTraceType_LargeScan,
771	kIemTlbTraceType_Flush,
772	kIemTlbTraceType_FlushGlobal,
773	kIemTlbTraceType_Load,
774	kIemTlbTraceType_LoadGlobal,
775	kIemTlbTraceType_Load_Cr0,
776	kIemTlbTraceType_Load_Cr3,
777	kIemTlbTraceType_Load_Cr4,
778	kIemTlbTraceType_Load_Efer,
779	kIemTlbTraceType_Irq,
780	kIemTlbTraceType_Xcpt,
781	kIemTlbTraceType_IRet,
782	kIemTlbTraceType_Tb_Compile,
783	kIemTlbTraceType_Tb_Exec_Threaded,
784	kIemTlbTraceType_Tb_Exec_Native,
785	kIemTlbTraceType_User0,
786	kIemTlbTraceType_User1,
787	kIemTlbTraceType_User2,
788	kIemTlbTraceType_User3,
789	} IEMTLBTRACETYPE;
790
791	/** TLB trace entry. */
792	typedef struct IEMTLBTRACEENTRY
793	{
794	/** The flattened RIP for the event. */
795	uint64_t rip;
796	/** The event type. */
797	IEMTLBTRACETYPE enmType;
798	/** Byte parameter - typically used as 'bool fDataTlb'. */
799	uint8_t bParam;
800	/** 16-bit parameter value. */
801	uint16_t u16Param;
802	/** 32-bit parameter value. */
803	uint32_t u32Param;
804	/** 64-bit parameter value. */
805	uint64_t u64Param;
806	/** 64-bit parameter value. */
807	uint64_t u64Param2;
808	} IEMTLBTRACEENTRY;
809	AssertCompileSize(IEMTLBTRACEENTRY, 32);
810	/** Pointer to a TLB trace entry. */
811	typedef IEMTLBTRACEENTRY *PIEMTLBTRACEENTRY;
812	/** Pointer to a const TLB trace entry. */
813	typedef IEMTLBTRACEENTRY const *PCIEMTLBTRACEENTRY;
814	#endif /* !IEM_WITH_TLB_TRACE */
815
816	#if defined(IEM_WITH_TLB_TRACE) && defined(IN_RING3)
817	# define IEMTLBTRACE_INVLPG(a_pVCpu, a_GCPtr) \
818	iemTlbTrace(a_pVCpu, kIemTlbTraceType_InvlPg, a_GCPtr)
819	# define IEMTLBTRACE_EVICT_SLOT(a_pVCpu, a_GCPtrTag, a_GCPhys, a_idxSlot, a_fDataTlb) \
820	iemTlbTrace(a_pVCpu, kIemTlbTraceType_EvictSlot, a_GCPtrTag, a_GCPhys, a_fDataTlb, a_idxSlot)
821	# define IEMTLBTRACE_LARGE_EVICT_SLOT(a_pVCpu, a_GCPtrTag, a_GCPhys, a_idxSlot, a_fDataTlb) \
822	iemTlbTrace(a_pVCpu, kIemTlbTraceType_LargeEvictSlot, a_GCPtrTag, a_GCPhys, a_fDataTlb, a_idxSlot)
823	# define IEMTLBTRACE_LARGE_SCAN(a_pVCpu, a_fGlobal, a_fNonGlobal, a_fDataTlb) \
824	iemTlbTrace(a_pVCpu, kIemTlbTraceType_LargeScan, 0, 0, a_fDataTlb, (uint8_t)a_fGlobal \| ((uint8_t)a_fNonGlobal << 1))
825	# define IEMTLBTRACE_FLUSH(a_pVCpu, a_uRev, a_fDataTlb) \
826	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Flush, a_uRev, 0, a_fDataTlb)
827	# define IEMTLBTRACE_FLUSH_GLOBAL(a_pVCpu, a_uRev, a_uGRev, a_fDataTlb) \
828	iemTlbTrace(a_pVCpu, kIemTlbTraceType_FlushGlobal, a_uRev, a_uGRev, a_fDataTlb)
829	# define IEMTLBTRACE_LOAD(a_pVCpu, a_GCPtr, a_GCPhys, a_fTlb, a_fDataTlb) \
830	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Load, a_GCPtr, a_GCPhys, a_fDataTlb, a_fTlb)
831	# define IEMTLBTRACE_LOAD_GLOBAL(a_pVCpu, a_GCPtr, a_GCPhys, a_fTlb, a_fDataTlb) \
832	iemTlbTrace(a_pVCpu, kIemTlbTraceType_LoadGlobal, a_GCPtr, a_GCPhys, a_fDataTlb, a_fTlb)
833	#else
834	# define IEMTLBTRACE_INVLPG(a_pVCpu, a_GCPtr) do { } while (0)
835	# define IEMTLBTRACE_EVICT_SLOT(a_pVCpu, a_GCPtrTag, a_GCPhys, a_idxSlot, a_fDataTlb) do { } while (0)
836	# define IEMTLBTRACE_LARGE_EVICT_SLOT(a_pVCpu, a_GCPtrTag, a_GCPhys, a_idxSlot, a_fDataTlb) do { } while (0)
837	# define IEMTLBTRACE_LARGE_SCAN(a_pVCpu, a_fGlobal, a_fNonGlobal, a_fDataTlb) do { } while (0)
838	# define IEMTLBTRACE_FLUSH(a_pVCpu, a_uRev, a_fDataTlb) do { } while (0)
839	# define IEMTLBTRACE_FLUSH_GLOBAL(a_pVCpu, a_uRev, a_uGRev, a_fDataTlb) do { } while (0)
840	# define IEMTLBTRACE_LOAD(a_pVCpu, a_GCPtr, a_GCPhys, a_fTlb, a_fDataTlb) do { } while (0)
841	# define IEMTLBTRACE_LOAD_GLOBAL(a_pVCpu, a_GCPtr, a_GCPhys, a_fTlb, a_fDataTlb) do { } while (0)
842	#endif
843
844	#if defined(IEM_WITH_TLB_TRACE) && defined(IN_RING3) && 1
845	# define IEMTLBTRACE_LOAD_CR0(a_pVCpu, a_uNew, a_uOld) iemTlbTrace(a_pVCpu, kIemTlbTraceType_Load_Cr0, a_uNew, a_uOld)
846	# define IEMTLBTRACE_LOAD_CR3(a_pVCpu, a_uNew, a_uOld) iemTlbTrace(a_pVCpu, kIemTlbTraceType_Load_Cr3, a_uNew, a_uOld)
847	# define IEMTLBTRACE_LOAD_CR4(a_pVCpu, a_uNew, a_uOld) iemTlbTrace(a_pVCpu, kIemTlbTraceType_Load_Cr4, a_uNew, a_uOld)
848	# define IEMTLBTRACE_LOAD_EFER(a_pVCpu, a_uNew, a_uOld) iemTlbTrace(a_pVCpu, kIemTlbTraceType_Load_Efer, a_uNew, a_uOld)
849	#else
850	# define IEMTLBTRACE_LOAD_CR0(a_pVCpu, a_uNew, a_uOld) do { } while (0)
851	# define IEMTLBTRACE_LOAD_CR3(a_pVCpu, a_uNew, a_uOld) do { } while (0)
852	# define IEMTLBTRACE_LOAD_CR4(a_pVCpu, a_uNew, a_uOld) do { } while (0)
853	# define IEMTLBTRACE_LOAD_EFER(a_pVCpu, a_uNew, a_uOld) do { } while (0)
854	#endif
855
856	#if defined(IEM_WITH_TLB_TRACE) && defined(IN_RING3) && 1
857	# define IEMTLBTRACE_IRQ(a_pVCpu, a_uVector, a_fFlags, a_fEFlags) \
858	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Irq, a_fEFlags, 0, a_uVector, a_fFlags)
859	# define IEMTLBTRACE_XCPT(a_pVCpu, a_uVector, a_uErr, a_uCr2, a_fFlags) \
860	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Xcpt, a_uErr, a_uCr2, a_uVector, a_fFlags)
861	# define IEMTLBTRACE_IRET(a_pVCpu, a_uRetCs, a_uRetRip, a_fEFlags) \
862	iemTlbTrace(a_pVCpu, kIemTlbTraceType_IRet, a_uRetRip, a_fEFlags, 0, a_uRetCs)
863	#else
864	# define IEMTLBTRACE_IRQ(a_pVCpu, a_uVector, a_fFlags, a_fEFlags) do { } while (0)
865	# define IEMTLBTRACE_XCPT(a_pVCpu, a_uVector, a_uErr, a_uCr2, a_fFlags) do { } while (0)
866	# define IEMTLBTRACE_IRET(a_pVCpu, a_uRetCs, a_uRetRip, a_fEFlags) do { } while (0)
867	#endif
868
869	#if defined(IEM_WITH_TLB_TRACE) && defined(IN_RING3) && 1
870	# define IEMTLBTRACE_TB_COMPILE(a_pVCpu, a_GCPhysPc) \
871	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Tb_Compile, a_GCPhysPc)
872	# define IEMTLBTRACE_TB_EXEC_THRD(a_pVCpu, a_pTb) \
873	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Tb_Exec_Threaded, (a_pTb)->GCPhysPc, (uintptr_t)a_pTb, 0, (a_pTb)->cUsed)
874	# define IEMTLBTRACE_TB_EXEC_N8VE(a_pVCpu, a_pTb) \
875	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Tb_Exec_Native, (a_pTb)->GCPhysPc, (uintptr_t)a_pTb, 0, (a_pTb)->cUsed)
876	#else
877	# define IEMTLBTRACE_TB_COMPILE(a_pVCpu, a_GCPhysPc) do { } while (0)
878	# define IEMTLBTRACE_TB_EXEC_THRD(a_pVCpu, a_pTb) do { } while (0)
879	# define IEMTLBTRACE_TB_EXEC_N8VE(a_pVCpu, a_pTb) do { } while (0)
880	#endif
881
882	#if defined(IEM_WITH_TLB_TRACE) && defined(IN_RING3) && 1
883	# define IEMTLBTRACE_USER0(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) \
884	iemTlbTrace(a_pVCpu, kIemTlbTraceType_User0, a_u64Param1, a_u64Param2, a_bParam, a_u32Param)
885	# define IEMTLBTRACE_USER1(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) \
886	iemTlbTrace(a_pVCpu, kIemTlbTraceType_User1, a_u64Param1, a_u64Param2, a_bParam, a_u32Param)
887	# define IEMTLBTRACE_USER2(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) \
888	iemTlbTrace(a_pVCpu, kIemTlbTraceType_User2, a_u64Param1, a_u64Param2, a_bParam, a_u32Param)
889	# define IEMTLBTRACE_USER3(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) \
890	iemTlbTrace(a_pVCpu, kIemTlbTraceType_User3, a_u64Param1, a_u64Param2, a_bParam, a_u32Param)
891	#else
892	# define IEMTLBTRACE_USER0(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) do { } while (0)
893	# define IEMTLBTRACE_USER1(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) do { } while (0)
894	# define IEMTLBTRACE_USER2(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) do { } while (0)
895	# define IEMTLBTRACE_USER3(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) do { } while (0)
896	#endif
897
898
899	/** @name IEM_MC_F_XXX - MC block flags/clues.
900	* @todo Merge with IEM_CIMPL_F_XXX
901	* @{ */
902	#define IEM_MC_F_ONLY_8086 RT_BIT_32(0)
903	#define IEM_MC_F_MIN_186 RT_BIT_32(1)
904	#define IEM_MC_F_MIN_286 RT_BIT_32(2)
905	#define IEM_MC_F_NOT_286_OR_OLDER IEM_MC_F_MIN_386
906	#define IEM_MC_F_MIN_386 RT_BIT_32(3)
907	#define IEM_MC_F_MIN_486 RT_BIT_32(4)
908	#define IEM_MC_F_MIN_PENTIUM RT_BIT_32(5)
909	#define IEM_MC_F_MIN_PENTIUM_II IEM_MC_F_MIN_PENTIUM
910	#define IEM_MC_F_MIN_CORE IEM_MC_F_MIN_PENTIUM
911	#define IEM_MC_F_64BIT RT_BIT_32(6)
912	#define IEM_MC_F_NOT_64BIT RT_BIT_32(7)
913	/** This is set by IEMAllN8vePython.py to indicate a variation without the
914	* flags-clearing-and-checking, when there is also a variation with that.
915	* @note Do not use this manully, it's only for python and for testing in
916	* the native recompiler! */
917	#define IEM_MC_F_WITHOUT_FLAGS RT_BIT_32(8)
918	/** @} */
919
920	/** @name IEM_CIMPL_F_XXX - State change clues for CIMPL calls.
921	*
922	* These clues are mainly for the recompiler, so that it can emit correct code.
923	*
924	* They are processed by the python script and which also automatically
925	* calculates flags for MC blocks based on the statements, extending the use of
926	* these flags to describe MC block behavior to the recompiler core. The python
927	* script pass the flags to the IEM_MC2_END_EMIT_CALLS macro, but mainly for
928	* error checking purposes. The script emits the necessary fEndTb = true and
929	* similar statements as this reduces compile time a tiny bit.
930	*
931	* @{ */
932	/** Flag set if direct branch, clear if absolute or indirect. */
933	#define IEM_CIMPL_F_BRANCH_DIRECT RT_BIT_32(0)
934	/** Flag set if indirect branch, clear if direct or relative.
935	* This is also used for all system control transfers (SYSCALL, SYSRET, INT, ++)
936	* as well as for return instructions (RET, IRET, RETF). */
937	#define IEM_CIMPL_F_BRANCH_INDIRECT RT_BIT_32(1)
938	/** Flag set if relative branch, clear if absolute or indirect. */
939	#define IEM_CIMPL_F_BRANCH_RELATIVE RT_BIT_32(2)
940	/** Flag set if conditional branch, clear if unconditional. */
941	#define IEM_CIMPL_F_BRANCH_CONDITIONAL RT_BIT_32(3)
942	/** Flag set if it's a far branch (changes CS). */
943	#define IEM_CIMPL_F_BRANCH_FAR RT_BIT_32(4)
944	/** Convenience: Testing any kind of branch. */
945	#define IEM_CIMPL_F_BRANCH_ANY (IEM_CIMPL_F_BRANCH_DIRECT \| IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_RELATIVE)
946
947	/** Execution flags may change (IEMCPU::fExec). */
948	#define IEM_CIMPL_F_MODE RT_BIT_32(5)
949	/** May change significant portions of RFLAGS. */
950	#define IEM_CIMPL_F_RFLAGS RT_BIT_32(6)
951	/** May change the status bits (X86_EFL_STATUS_BITS) in RFLAGS. */
952	#define IEM_CIMPL_F_STATUS_FLAGS RT_BIT_32(7)
953	/** May trigger interrupt shadowing. */
954	#define IEM_CIMPL_F_INHIBIT_SHADOW RT_BIT_32(8)
955	/** May enable interrupts, so recheck IRQ immediately afterwards executing
956	* the instruction. */
957	#define IEM_CIMPL_F_CHECK_IRQ_AFTER RT_BIT_32(9)
958	/** May disable interrupts, so recheck IRQ immediately before executing the
959	* instruction. */
960	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE RT_BIT_32(10)
961	/** Convenience: Check for IRQ both before and after an instruction. */
962	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE_AND_AFTER (IEM_CIMPL_F_CHECK_IRQ_BEFORE \| IEM_CIMPL_F_CHECK_IRQ_AFTER)
963	/** May trigger a VM exit (treated like IEM_CIMPL_F_MODE atm). */
964	#define IEM_CIMPL_F_VMEXIT RT_BIT_32(11)
965	/** May modify FPU state.
966	* @todo Not sure if this is useful yet. */
967	#define IEM_CIMPL_F_FPU RT_BIT_32(12)
968	/** REP prefixed instruction which may yield before updating PC.
969	* @todo Not sure if this is useful, REP functions now return non-zero
970	* status if they don't update the PC. */
971	#define IEM_CIMPL_F_REP RT_BIT_32(13)
972	/** I/O instruction.
973	* @todo Not sure if this is useful yet. */
974	#define IEM_CIMPL_F_IO RT_BIT_32(14)
975	/** Force end of TB after the instruction. */
976	#define IEM_CIMPL_F_END_TB RT_BIT_32(15)
977	/** Flag set if a branch may also modify the stack (push/pop return address). */
978	#define IEM_CIMPL_F_BRANCH_STACK RT_BIT_32(16)
979	/** Flag set if a branch may also modify the stack (push/pop return address)
980	* and switch it (load/restore SS:RSP). */
981	#define IEM_CIMPL_F_BRANCH_STACK_FAR RT_BIT_32(17)
982	/** Convenience: Raise exception (technically unnecessary, since it shouldn't return VINF_SUCCESS). */
983	#define IEM_CIMPL_F_XCPT \
984	(IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_FAR \| IEM_CIMPL_F_BRANCH_STACK_FAR \
985	\| IEM_CIMPL_F_MODE \| IEM_CIMPL_F_RFLAGS \| IEM_CIMPL_F_VMEXIT)
986
987	/** The block calls a C-implementation instruction function with two implicit arguments.
988	* Mutually exclusive with IEM_CIMPL_F_CALLS_AIMPL and
989	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
990	* @note The python scripts will add this if missing. */
991	#define IEM_CIMPL_F_CALLS_CIMPL RT_BIT_32(18)
992	/** The block calls an ASM-implementation instruction function.
993	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL and
994	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
995	* @note The python scripts will add this if missing. */
996	#define IEM_CIMPL_F_CALLS_AIMPL RT_BIT_32(19)
997	/** The block calls an ASM-implementation instruction function with an implicit
998	* X86FXSTATE pointer argument.
999	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL, IEM_CIMPL_F_CALLS_AIMPL and
1000	* IEM_CIMPL_F_CALLS_AIMPL_WITH_XSTATE.
1001	* @note The python scripts will add this if missing. */
1002	#define IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE RT_BIT_32(20)
1003	/** The block calls an ASM-implementation instruction function with an implicit
1004	* X86XSAVEAREA pointer argument.
1005	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL, IEM_CIMPL_F_CALLS_AIMPL and
1006	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
1007	* @note No different from IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE, so same value.
1008	* @note The python scripts will add this if missing. */
1009	#define IEM_CIMPL_F_CALLS_AIMPL_WITH_XSTATE IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE
1010	/** @} */
1011
1012
1013	/** @name IEM_F_XXX - Execution mode flags (IEMCPU::fExec, IEMTB::fFlags).
1014	*
1015	* These flags are set when entering IEM and adjusted as code is executed, such
1016	* that they will always contain the current values as instructions are
1017	* finished.
1018	*
1019	* In recompiled execution mode, (most of) these flags are included in the
1020	* translation block selection key and stored in IEMTB::fFlags alongside the
1021	* IEMTB_F_XXX flags. The latter flags uses bits 31 thru 24, which are all zero
1022	* in IEMCPU::fExec.
1023	*
1024	* @{ */
1025	/** Mode: The block target mode mask. */
1026	#define IEM_F_MODE_MASK UINT32_C(0x0000001f)
1027	/** Mode: The IEMMODE part of the IEMTB_F_MODE_MASK value. */
1028	#define IEM_F_MODE_CPUMODE_MASK UINT32_C(0x00000003)
1029	/** X86 Mode: Bit used to indicating pre-386 CPU in 16-bit mode (for eliminating
1030	* conditional in EIP/IP updating), and flat wide open CS, SS, DS, and ES in
1031	* 32-bit mode (for simplifying most memory accesses). */
1032	#define IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK UINT32_C(0x00000004)
1033	/** X86 Mode: Bit indicating protected mode, real mode (or SMM) when not set. */
1034	#define IEM_F_MODE_X86_PROT_MASK UINT32_C(0x00000008)
1035	/** X86 Mode: Bit used to indicate virtual 8086 mode (only 16-bit). */
1036	#define IEM_F_MODE_X86_V86_MASK UINT32_C(0x00000010)
1037
1038	/** X86 Mode: 16-bit on 386 or later. */
1039	#define IEM_F_MODE_X86_16BIT UINT32_C(0x00000000)
1040	/** X86 Mode: 80286, 80186 and 8086/88 targetting blocks (EIP update opt). */
1041	#define IEM_F_MODE_X86_16BIT_PRE_386 UINT32_C(0x00000004)
1042	/** X86 Mode: 16-bit protected mode on 386 or later. */
1043	#define IEM_F_MODE_X86_16BIT_PROT UINT32_C(0x00000008)
1044	/** X86 Mode: 16-bit protected mode on 386 or later. */
1045	#define IEM_F_MODE_X86_16BIT_PROT_PRE_386 UINT32_C(0x0000000c)
1046	/** X86 Mode: 16-bit virtual 8086 protected mode (on 386 or later). */
1047	#define IEM_F_MODE_X86_16BIT_PROT_V86 UINT32_C(0x00000018)
1048
1049	/** X86 Mode: 32-bit on 386 or later. */
1050	#define IEM_F_MODE_X86_32BIT UINT32_C(0x00000001)
1051	/** X86 Mode: 32-bit mode with wide open flat CS, SS, DS and ES. */
1052	#define IEM_F_MODE_X86_32BIT_FLAT UINT32_C(0x00000005)
1053	/** X86 Mode: 32-bit protected mode. */
1054	#define IEM_F_MODE_X86_32BIT_PROT UINT32_C(0x00000009)
1055	/** X86 Mode: 32-bit protected mode with wide open flat CS, SS, DS and ES. */
1056	#define IEM_F_MODE_X86_32BIT_PROT_FLAT UINT32_C(0x0000000d)
1057
1058	/** X86 Mode: 64-bit (includes protected, but not the flat bit). */
1059	#define IEM_F_MODE_X86_64BIT UINT32_C(0x0000000a)
1060
1061	/** X86 Mode: Checks if @a a_fExec represent a FLAT mode. */
1062	#define IEM_F_MODE_X86_IS_FLAT(a_fExec) ( ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_64BIT \
1063	\|\| ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_PROT_FLAT \
1064	\|\| ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_FLAT)
1065
1066	/** Bypass access handlers when set. */
1067	#define IEM_F_BYPASS_HANDLERS UINT32_C(0x00010000)
1068	/** Have pending hardware instruction breakpoints. */
1069	#define IEM_F_PENDING_BRK_INSTR UINT32_C(0x00020000)
1070	/** Have pending hardware data breakpoints. */
1071	#define IEM_F_PENDING_BRK_DATA UINT32_C(0x00040000)
1072
1073	/** X86: Have pending hardware I/O breakpoints. */
1074	#define IEM_F_PENDING_BRK_X86_IO UINT32_C(0x00000400)
1075	/** X86: Disregard the lock prefix (implied or not) when set. */
1076	#define IEM_F_X86_DISREGARD_LOCK UINT32_C(0x00000800)
1077
1078	/** Pending breakpoint mask (what iemCalcExecDbgFlags works out). */
1079	#define IEM_F_PENDING_BRK_MASK (IEM_F_PENDING_BRK_INSTR \| IEM_F_PENDING_BRK_DATA \| IEM_F_PENDING_BRK_X86_IO)
1080
1081	/** Caller configurable options. */
1082	#define IEM_F_USER_OPTS (IEM_F_BYPASS_HANDLERS \| IEM_F_X86_DISREGARD_LOCK)
1083
1084	/** X86: The current protection level (CPL) shift factor. */
1085	#define IEM_F_X86_CPL_SHIFT 8
1086	/** X86: The current protection level (CPL) mask. */
1087	#define IEM_F_X86_CPL_MASK UINT32_C(0x00000300)
1088	/** X86: The current protection level (CPL) shifted mask. */
1089	#define IEM_F_X86_CPL_SMASK UINT32_C(0x00000003)
1090
1091	/** X86: Alignment checks enabled (CR0.AM=1 & EFLAGS.AC=1). */
1092	#define IEM_F_X86_AC UINT32_C(0x00080000)
1093
1094	/** X86 execution context.
1095	* The IEM_F_X86_CTX_XXX values are individual flags that can be combined (with
1096	* the exception of IEM_F_X86_CTX_NORMAL). This allows running VMs from SMM
1097	* mode. */
1098	#define IEM_F_X86_CTX_MASK UINT32_C(0x0000f000)
1099	/** X86 context: Plain regular execution context. */
1100	#define IEM_F_X86_CTX_NORMAL UINT32_C(0x00000000)
1101	/** X86 context: VT-x enabled. */
1102	#define IEM_F_X86_CTX_VMX UINT32_C(0x00001000)
1103	/** X86 context: AMD-V enabled. */
1104	#define IEM_F_X86_CTX_SVM UINT32_C(0x00002000)
1105	/** X86 context: In AMD-V or VT-x guest mode. */
1106	#define IEM_F_X86_CTX_IN_GUEST UINT32_C(0x00004000)
1107	/** X86 context: System management mode (SMM). */
1108	#define IEM_F_X86_CTX_SMM UINT32_C(0x00008000)
1109
1110	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
1111	* iemRegFinishClearingRF() most for most situations (CPUMCTX_DBG_HIT_DRX_MASK
1112	* and CPUMCTX_DBG_DBGF_MASK are covered by the IEM_F_PENDING_BRK_XXX bits
1113	* alread). */
1114
1115	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
1116	* iemRegFinishClearingRF() most for most situations
1117	* (CPUMCTX_DBG_HIT_DRX_MASK and CPUMCTX_DBG_DBGF_MASK are covered by
1118	* the IEM_F_PENDING_BRK_XXX bits alread). */
1119
1120	/** @} */
1121
1122
1123	/** @name IEMTB_F_XXX - Translation block flags (IEMTB::fFlags).
1124	*
1125	* Extends the IEM_F_XXX flags (subject to IEMTB_F_IEM_F_MASK) to make up the
1126	* translation block flags. The combined flag mask (subject to
1127	* IEMTB_F_KEY_MASK) is used as part of the lookup key for translation blocks.
1128	*
1129	* @{ */
1130	/** Mask of IEM_F_XXX flags included in IEMTB_F_XXX. */
1131	#define IEMTB_F_IEM_F_MASK UINT32_C(0x00ffffff)
1132
1133	/** Type: The block type mask. */
1134	#define IEMTB_F_TYPE_MASK UINT32_C(0x03000000)
1135	/** Type: Purly threaded recompiler (via tables). */
1136	#define IEMTB_F_TYPE_THREADED UINT32_C(0x01000000)
1137	/** Type: Native recompilation. */
1138	#define IEMTB_F_TYPE_NATIVE UINT32_C(0x02000000)
1139
1140	/** Set when we're starting the block in an "interrupt shadow".
1141	* We don't need to distingish between the two types of this mask, thus the one.
1142	* @see CPUMCTX_INHIBIT_SHADOW, CPUMIsInInterruptShadow() */
1143	#define IEMTB_F_INHIBIT_SHADOW UINT32_C(0x04000000)
1144	/** Set when we're currently inhibiting NMIs
1145	* @see CPUMCTX_INHIBIT_NMI, CPUMAreInterruptsInhibitedByNmi() */
1146	#define IEMTB_F_INHIBIT_NMI UINT32_C(0x08000000)
1147
1148	/** Checks that EIP/IP is wihin CS.LIM before each instruction. Used when
1149	* we're close the limit before starting a TB, as determined by
1150	* iemGetTbFlagsForCurrentPc(). */
1151	#define IEMTB_F_CS_LIM_CHECKS UINT32_C(0x10000000)
1152
1153	/** Mask of the IEMTB_F_XXX flags that are part of the TB lookup key.
1154	*
1155	* @note We skip all of IEM_F_X86_CTX_MASK, with the exception of SMM (which we
1156	* don't implement), because we don't currently generate any context
1157	* specific code - that's all handled in CIMPL functions.
1158	*
1159	* For the threaded recompiler we don't generate any CPL specific code
1160	* either, but the native recompiler does for memory access (saves getting
1161	* the CPL from fExec and turning it into IEMTLBE_F_PT_NO_USER).
1162	* Since most OSes will not share code between rings, this shouldn't
1163	* have any real effect on TB/memory/recompiling load.
1164	*/
1165	#define IEMTB_F_KEY_MASK ((UINT32_MAX & ~(IEM_F_X86_CTX_MASK \| IEMTB_F_TYPE_MASK)) \| IEM_F_X86_CTX_SMM)
1166	/** @} */
1167
1168	AssertCompile( (IEM_F_MODE_X86_16BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
1169	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1170	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_PROT_MASK));
1171	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_V86_MASK));
1172	AssertCompile( (IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
1173	AssertCompile( IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
1174	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_PROT_MASK));
1175	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
1176	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
1177	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1178	AssertCompile( IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
1179	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_V86_MASK));
1180	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
1181	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
1182	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_PROT_MASK);
1183	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
1184	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_PROT_MASK);
1185	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1186	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_V86_MASK);
1187
1188	AssertCompile( (IEM_F_MODE_X86_32BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
1189	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1190	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_PROT_MASK));
1191	AssertCompile( (IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
1192	AssertCompile( IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
1193	AssertCompile(!(IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_PROT_MASK));
1194	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
1195	AssertCompile(!(IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1196	AssertCompile( IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
1197	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
1198	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
1199	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_PROT_MASK);
1200
1201	AssertCompile( (IEM_F_MODE_X86_64BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT);
1202	AssertCompile( IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_PROT_MASK);
1203	AssertCompile(!(IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1204
1205	/** Native instruction type for use with the native code generator.
1206	* This is a byte (uint8_t) for x86 and amd64 and uint32_t for the other(s). */
1207	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
1208	typedef uint8_t IEMNATIVEINSTR;
1209	#else
1210	typedef uint32_t IEMNATIVEINSTR;
1211	#endif
1212	/** Pointer to a native instruction unit. */
1213	typedef IEMNATIVEINSTR *PIEMNATIVEINSTR;
1214	/** Pointer to a const native instruction unit. */
1215	typedef IEMNATIVEINSTR const *PCIEMNATIVEINSTR;
1216
1217	/**
1218	* A call for the threaded call table.
1219	*/
1220	typedef struct IEMTHRDEDCALLENTRY
1221	{
1222	/** The function to call (IEMTHREADEDFUNCS). */
1223	uint16_t enmFunction;
1224
1225	/** Instruction number in the TB (for statistics). */
1226	uint8_t idxInstr;
1227	/** The opcode length. */
1228	uint8_t cbOpcode;
1229	/** Offset into IEMTB::pabOpcodes. */
1230	uint16_t offOpcode;
1231
1232	/** TB lookup table index (7 bits) and large size (1 bits).
1233	*
1234	* The default size is 1 entry, but for indirect calls and returns we set the
1235	* top bit and allocate 4 (IEM_TB_LOOKUP_TAB_LARGE_SIZE) entries. The large
1236	* tables uses RIP for selecting the entry to use, as it is assumed a hash table
1237	* lookup isn't that slow compared to sequentially trying out 4 TBs.
1238	*
1239	* By default lookup table entry 0 for a TB is reserved as a fallback for
1240	* calltable entries w/o explicit entreis, so this member will be non-zero if
1241	* there is a lookup entry associated with this call.
1242	*
1243	* @sa IEM_TB_LOOKUP_TAB_GET_SIZE, IEM_TB_LOOKUP_TAB_GET_IDX
1244	*/
1245	uint8_t uTbLookup;
1246
1247	/** Unused atm. */
1248	uint8_t uUnused0;
1249
1250	/** Generic parameters. */
1251	uint64_t auParams[3];
1252	} IEMTHRDEDCALLENTRY;
1253	AssertCompileSize(IEMTHRDEDCALLENTRY, sizeof(uint64_t) * 4);
1254	/** Pointer to a threaded call entry. */
1255	typedef struct IEMTHRDEDCALLENTRY *PIEMTHRDEDCALLENTRY;
1256	/** Pointer to a const threaded call entry. */
1257	typedef IEMTHRDEDCALLENTRY const *PCIEMTHRDEDCALLENTRY;
1258
1259	/** The number of TB lookup table entries for a large allocation
1260	* (IEMTHRDEDCALLENTRY::uTbLookup bit 7 set). */
1261	#define IEM_TB_LOOKUP_TAB_LARGE_SIZE 4
1262	/** Get the lookup table size from IEMTHRDEDCALLENTRY::uTbLookup. */
1263	#define IEM_TB_LOOKUP_TAB_GET_SIZE(a_uTbLookup) (!((a_uTbLookup) & 0x80) ? 1 : IEM_TB_LOOKUP_TAB_LARGE_SIZE)
1264	/** Get the first lookup table index from IEMTHRDEDCALLENTRY::uTbLookup. */
1265	#define IEM_TB_LOOKUP_TAB_GET_IDX(a_uTbLookup) ((a_uTbLookup) & 0x7f)
1266	/** Get the lookup table index from IEMTHRDEDCALLENTRY::uTbLookup and RIP. */
1267	#define IEM_TB_LOOKUP_TAB_GET_IDX_WITH_RIP(a_uTbLookup, a_Rip) \
1268	(!((a_uTbLookup) & 0x80) ? (a_uTbLookup) & 0x7f : ((a_uTbLookup) & 0x7f) + ((a_Rip) & (IEM_TB_LOOKUP_TAB_LARGE_SIZE - 1)) )
1269
1270	/** Make a IEMTHRDEDCALLENTRY::uTbLookup value. */
1271	#define IEM_TB_LOOKUP_TAB_MAKE(a_idxTable, a_fLarge) ((a_idxTable) \| ((a_fLarge) ? 0x80 : 0))
1272
1273	/**
1274	* Native IEM TB 'function' typedef.
1275	*
1276	* This will throw/longjmp on occation.
1277	*
1278	* @note AMD64 doesn't have that many non-volatile registers and does sport
1279	* 32-bit address displacments, so we don't need pCtx.
1280	*
1281	* On ARM64 pCtx allows us to directly address the whole register
1282	* context without requiring a separate indexing register holding the
1283	* offset. This saves an instruction loading the offset for each guest
1284	* CPU context access, at the cost of a non-volatile register.
1285	* Fortunately, ARM64 has quite a lot more registers.
1286	*/
1287	typedef
1288	#ifdef RT_ARCH_AMD64
1289	int FNIEMTBNATIVE(PVMCPUCC pVCpu)
1290	#else
1291	int FNIEMTBNATIVE(PVMCPUCC pVCpu, PCPUMCTX pCtx)
1292	#endif
1293	#if RT_CPLUSPLUS_PREREQ(201700)
1294	IEM_NOEXCEPT_MAY_LONGJMP
1295	#endif
1296	;
1297	/** Pointer to a native IEM TB entry point function.
1298	* This will throw/longjmp on occation. */
1299	typedef FNIEMTBNATIVE *PFNIEMTBNATIVE;
1300
1301
1302	/**
1303	* Translation block debug info entry type.
1304	*/
1305	typedef enum IEMTBDBGENTRYTYPE
1306	{
1307	kIemTbDbgEntryType_Invalid = 0,
1308	/** The entry is for marking a native code position.
1309	* Entries following this all apply to this position. */
1310	kIemTbDbgEntryType_NativeOffset,
1311	/** The entry is for a new guest instruction. */
1312	kIemTbDbgEntryType_GuestInstruction,
1313	/** Marks the start of a threaded call. */
1314	kIemTbDbgEntryType_ThreadedCall,
1315	/** Marks the location of a label. */
1316	kIemTbDbgEntryType_Label,
1317	/** Info about a host register shadowing a guest register. */
1318	kIemTbDbgEntryType_GuestRegShadowing,
1319	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1320	/** Info about a host SIMD register shadowing a guest SIMD register. */
1321	kIemTbDbgEntryType_GuestSimdRegShadowing,
1322	#endif
1323	#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
1324	/** Info about a delayed RIP update. */
1325	kIemTbDbgEntryType_DelayedPcUpdate,
1326	#endif
1327	#if defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK) \|\| defined(IEMNATIVE_WITH_SIMD_REG_ALLOCATOR)
1328	/** Info about a shadowed guest register becoming dirty. */
1329	kIemTbDbgEntryType_GuestRegDirty,
1330	/** Info about register writeback/flush oepration. */
1331	kIemTbDbgEntryType_GuestRegWriteback,
1332	#endif
1333	kIemTbDbgEntryType_End
1334	} IEMTBDBGENTRYTYPE;
1335
1336	/**
1337	* Translation block debug info entry.
1338	*/
1339	typedef union IEMTBDBGENTRY
1340	{
1341	/** Plain 32-bit view. */
1342	uint32_t u;
1343
1344	/** Generic view for getting at the type field. */
1345	struct
1346	{
1347	/** IEMTBDBGENTRYTYPE */
1348	uint32_t uType : 4;
1349	uint32_t uTypeSpecific : 28;
1350	} Gen;
1351
1352	struct
1353	{
1354	/** kIemTbDbgEntryType_ThreadedCall1. */
1355	uint32_t uType : 4;
1356	/** Native code offset. */
1357	uint32_t offNative : 28;
1358	} NativeOffset;
1359
1360	struct
1361	{
1362	/** kIemTbDbgEntryType_GuestInstruction. */
1363	uint32_t uType : 4;
1364	uint32_t uUnused : 4;
1365	/** The IEM_F_XXX flags. */
1366	uint32_t fExec : 24;
1367	} GuestInstruction;
1368
1369	struct
1370	{
1371	/* kIemTbDbgEntryType_ThreadedCall. */
1372	uint32_t uType : 4;
1373	/** Set if the call was recompiled to native code, clear if just calling
1374	* threaded function. */
1375	uint32_t fRecompiled : 1;
1376	uint32_t uUnused : 11;
1377	/** The threaded call number (IEMTHREADEDFUNCS). */
1378	uint32_t enmCall : 16;
1379	} ThreadedCall;
1380
1381	struct
1382	{
1383	/* kIemTbDbgEntryType_Label. */
1384	uint32_t uType : 4;
1385	uint32_t uUnused : 4;
1386	/** The label type (IEMNATIVELABELTYPE). */
1387	uint32_t enmLabel : 8;
1388	/** The label data. */
1389	uint32_t uData : 16;
1390	} Label;
1391
1392	struct
1393	{
1394	/* kIemTbDbgEntryType_GuestRegShadowing. */
1395	uint32_t uType : 4;
1396	uint32_t uUnused : 4;
1397	/** The guest register being shadowed (IEMNATIVEGSTREG). */
1398	uint32_t idxGstReg : 8;
1399	/** The host new register number, UINT8_MAX if dropped. */
1400	uint32_t idxHstReg : 8;
1401	/** The previous host register number, UINT8_MAX if new. */
1402	uint32_t idxHstRegPrev : 8;
1403	} GuestRegShadowing;
1404
1405	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1406	struct
1407	{
1408	/* kIemTbDbgEntryType_GuestSimdRegShadowing. */
1409	uint32_t uType : 4;
1410	uint32_t uUnused : 4;
1411	/** The guest register being shadowed (IEMNATIVEGSTSIMDREG). */
1412	uint32_t idxGstSimdReg : 8;
1413	/** The host new register number, UINT8_MAX if dropped. */
1414	uint32_t idxHstSimdReg : 8;
1415	/** The previous host register number, UINT8_MAX if new. */
1416	uint32_t idxHstSimdRegPrev : 8;
1417	} GuestSimdRegShadowing;
1418	#endif
1419
1420	#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
1421	struct
1422	{
1423	/* kIemTbDbgEntryType_DelayedPcUpdate. */
1424	uint32_t uType : 4;
1425	/* The instruction offset added to the program counter. */
1426	uint32_t offPc : 14;
1427	/** Number of instructions skipped. */
1428	uint32_t cInstrSkipped : 14;
1429	} DelayedPcUpdate;
1430	#endif
1431
1432	#if defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK) \|\| defined(IEMNATIVE_WITH_SIMD_REG_ALLOCATOR)
1433	struct
1434	{
1435	/* kIemTbDbgEntryType_GuestRegDirty. */
1436	uint32_t uType : 4;
1437	uint32_t uUnused : 11;
1438	/** Flag whether this is about a SIMD (true) or general (false) register. */
1439	uint32_t fSimdReg : 1;
1440	/** The guest register index being marked as dirty. */
1441	uint32_t idxGstReg : 8;
1442	/** The host register number this register is shadowed in .*/
1443	uint32_t idxHstReg : 8;
1444	} GuestRegDirty;
1445
1446	struct
1447	{
1448	/* kIemTbDbgEntryType_GuestRegWriteback. */
1449	uint32_t uType : 4;
1450	/** Flag whether this is about a SIMD (true) or general (false) register flush. */
1451	uint32_t fSimdReg : 1;
1452	/** The mask shift. */
1453	uint32_t cShift : 2;
1454	/** The guest register mask being written back. */
1455	uint32_t fGstReg : 25;
1456	} GuestRegWriteback;
1457	#endif
1458
1459	} IEMTBDBGENTRY;
1460	AssertCompileSize(IEMTBDBGENTRY, sizeof(uint32_t));
1461	/** Pointer to a debug info entry. */
1462	typedef IEMTBDBGENTRY *PIEMTBDBGENTRY;
1463	/** Pointer to a const debug info entry. */
1464	typedef IEMTBDBGENTRY const *PCIEMTBDBGENTRY;
1465
1466	/**
1467	* Translation block debug info.
1468	*/
1469	typedef struct IEMTBDBG
1470	{
1471	/** Number of entries in aEntries. */
1472	uint32_t cEntries;
1473	/** The offset of the last kIemTbDbgEntryType_NativeOffset record. */
1474	uint32_t offNativeLast;
1475	/** Debug info entries. */
1476	RT_FLEXIBLE_ARRAY_EXTENSION
1477	IEMTBDBGENTRY aEntries[RT_FLEXIBLE_ARRAY];
1478	} IEMTBDBG;
1479	/** Pointer to TB debug info. */
1480	typedef IEMTBDBG *PIEMTBDBG;
1481	/** Pointer to const TB debug info. */
1482	typedef IEMTBDBG const *PCIEMTBDBG;
1483
1484
1485	/**
1486	* Translation block.
1487	*
1488	* The current plan is to just keep TBs and associated lookup hash table private
1489	* to each VCpu as that simplifies TB removal greatly (no races) and generally
1490	* avoids using expensive atomic primitives for updating lists and stuff.
1491	*/
1492	#pragma pack(2) /* to prevent the Thrd structure from being padded unnecessarily */
1493	typedef struct IEMTB
1494	{
1495	/** Next block with the same hash table entry. */
1496	struct IEMTB *pNext;
1497	/** Usage counter. */
1498	uint32_t cUsed;
1499	/** The IEMCPU::msRecompilerPollNow last time it was used. */
1500	uint32_t msLastUsed;
1501
1502	/** @name What uniquely identifies the block.
1503	* @{ */
1504	RTGCPHYS GCPhysPc;
1505	/** IEMTB_F_XXX (i.e. IEM_F_XXX ++). */
1506	uint32_t fFlags;
1507	union
1508	{
1509	struct
1510	{
1511	/*< Relevant CS X86DESCATTR_XXX bits. /
1512	uint16_t fAttr;
1513	} x86;
1514	};
1515	/** @} */
1516
1517	/** Number of opcode ranges. */
1518	uint8_t cRanges;
1519	/** Statistics: Number of instructions in the block. */
1520	uint8_t cInstructions;
1521
1522	/** Type specific info. */
1523	union
1524	{
1525	struct
1526	{
1527	/** The call sequence table. */
1528	PIEMTHRDEDCALLENTRY paCalls;
1529	/** Number of calls in paCalls. */
1530	uint16_t cCalls;
1531	/** Number of calls allocated. */
1532	uint16_t cAllocated;
1533	} Thrd;
1534	struct
1535	{
1536	/** The native instructions (PFNIEMTBNATIVE). */
1537	PIEMNATIVEINSTR paInstructions;
1538	/** Number of instructions pointed to by paInstructions. */
1539	uint32_t cInstructions;
1540	} Native;
1541	/** Generic view for zeroing when freeing. */
1542	struct
1543	{
1544	uintptr_t uPtr;
1545	uint32_t uData;
1546	} Gen;
1547	};
1548
1549	/** The allocation chunk this TB belongs to. */
1550	uint8_t idxAllocChunk;
1551	/** The number of entries in the lookup table.
1552	* Because we're out of space, the TB lookup table is located before the
1553	* opcodes pointed to by pabOpcodes. */
1554	uint8_t cTbLookupEntries;
1555
1556	/** Number of bytes of opcodes stored in pabOpcodes.
1557	* @todo this field isn't really needed, aRanges keeps the actual info. */
1558	uint16_t cbOpcodes;
1559	/** Pointer to the opcode bytes this block was recompiled from.
1560	* This also points to the TB lookup table, which starts cTbLookupEntries
1561	* entries before the opcodes (we don't have room atm for another point). */
1562	uint8_t *pabOpcodes;
1563
1564	/** Debug info if enabled.
1565	* This is only generated by the native recompiler. */
1566	PIEMTBDBG pDbgInfo;
1567
1568	/* --- 64 byte cache line end --- */
1569
1570	/** Opcode ranges.
1571	*
1572	* The opcode checkers and maybe TLB loading functions will use this to figure
1573	* out what to do. The parameter will specify an entry and the opcode offset to
1574	* start at and the minimum number of bytes to verify (instruction length).
1575	*
1576	* When VT-x and AMD-V looks up the opcode bytes for an exitting instruction,
1577	* they'll first translate RIP (+ cbInstr - 1) to a physical address using the
1578	* code TLB (must have a valid entry for that address) and scan the ranges to
1579	* locate the corresponding opcodes. Probably.
1580	*/
1581	struct IEMTBOPCODERANGE
1582	{
1583	/** Offset within pabOpcodes. */
1584	uint16_t offOpcodes;
1585	/** Number of bytes. */
1586	uint16_t cbOpcodes;
1587	/** The page offset. */
1588	RT_GCC_EXTENSION
1589	uint16_t offPhysPage : 12;
1590	/** Unused bits. */
1591	RT_GCC_EXTENSION
1592	uint16_t u2Unused : 2;
1593	/** Index into GCPhysPc + aGCPhysPages for the physical page address. */
1594	RT_GCC_EXTENSION
1595	uint16_t idxPhysPage : 2;
1596	} aRanges[8];
1597
1598	/** Physical pages that this TB covers.
1599	* The GCPhysPc w/o page offset is element zero, so starting here with 1. */
1600	RTGCPHYS aGCPhysPages[2];
1601	} IEMTB;
1602	#pragma pack()
1603	AssertCompileMemberAlignment(IEMTB, GCPhysPc, sizeof(RTGCPHYS));
1604	AssertCompileMemberAlignment(IEMTB, Thrd, sizeof(void *));
1605	AssertCompileMemberAlignment(IEMTB, pabOpcodes, sizeof(void *));
1606	AssertCompileMemberAlignment(IEMTB, pDbgInfo, sizeof(void *));
1607	AssertCompileMemberAlignment(IEMTB, aGCPhysPages, sizeof(RTGCPHYS));
1608	AssertCompileMemberOffset(IEMTB, aRanges, 64);
1609	AssertCompileMemberSize(IEMTB, aRanges[0], 6);
1610	#if 1
1611	AssertCompileSize(IEMTB, 128);
1612	# define IEMTB_SIZE_IS_POWER_OF_TWO /*< The IEMTB size is a power of two. /
1613	#else
1614	AssertCompileSize(IEMTB, 168);
1615	# undef IEMTB_SIZE_IS_POWER_OF_TWO
1616	#endif
1617
1618	/** Pointer to a translation block. */
1619	typedef IEMTB *PIEMTB;
1620	/** Pointer to a const translation block. */
1621	typedef IEMTB const *PCIEMTB;
1622
1623	/** Gets address of the given TB lookup table entry. */
1624	#define IEMTB_GET_TB_LOOKUP_TAB_ENTRY(a_pTb, a_idx) \
1625	((PIEMTB )&(a_pTb)->pabOpcodes[-(int)((a_pTb)->cTbLookupEntries - (a_idx)) sizeof(PIEMTB)])
1626
1627	/**
1628	* Gets the physical address for a TB opcode range.
1629	*/
1630	DECL_FORCE_INLINE(RTGCPHYS) iemTbGetRangePhysPageAddr(PCIEMTB pTb, uint8_t idxRange)
1631	{
1632	Assert(idxRange < RT_MIN(pTb->cRanges, RT_ELEMENTS(pTb->aRanges)));
1633	uint8_t const idxPage = pTb->aRanges[idxRange].idxPhysPage;
1634	Assert(idxPage <= RT_ELEMENTS(pTb->aGCPhysPages));
1635	if (idxPage == 0)
1636	return pTb->GCPhysPc & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
1637	Assert(!(pTb->aGCPhysPages[idxPage - 1] & GUEST_PAGE_OFFSET_MASK));
1638	return pTb->aGCPhysPages[idxPage - 1];
1639	}
1640
1641
1642	/**
1643	* A chunk of memory in the TB allocator.
1644	*/
1645	typedef struct IEMTBCHUNK
1646	{
1647	/** Pointer to the translation blocks in this chunk. */
1648	PIEMTB paTbs;
1649	#ifdef IN_RING0
1650	/** Allocation handle. */
1651	RTR0MEMOBJ hMemObj;
1652	#endif
1653	} IEMTBCHUNK;
1654
1655	/**
1656	* A per-CPU translation block allocator.
1657	*
1658	* Because of how the IEMTBCACHE uses the lower 6 bits of the TB address to keep
1659	* the length of the collision list, and of course also for cache line alignment
1660	* reasons, the TBs must be allocated with at least 64-byte alignment.
1661	* Memory is there therefore allocated using one of the page aligned allocators.
1662	*
1663	*
1664	* To avoid wasting too much memory, it is allocated piecemeal as needed,
1665	* in chunks (IEMTBCHUNK) of 2 MiB or more. The TB has an 8-bit chunk index
1666	* that enables us to quickly calculate the allocation bitmap position when
1667	* freeing the translation block.
1668	*/
1669	typedef struct IEMTBALLOCATOR
1670	{
1671	/** Magic value (IEMTBALLOCATOR_MAGIC). */
1672	uint32_t uMagic;
1673
1674	#ifdef IEMTB_SIZE_IS_POWER_OF_TWO
1675	/** Mask corresponding to cTbsPerChunk - 1. */
1676	uint32_t fChunkMask;
1677	/** Shift count corresponding to cTbsPerChunk. */
1678	uint8_t cChunkShift;
1679	#else
1680	uint32_t uUnused;
1681	uint8_t bUnused;
1682	#endif
1683	/** Number of chunks we're allowed to allocate. */
1684	uint8_t cMaxChunks;
1685	/** Number of chunks currently populated. */
1686	uint16_t cAllocatedChunks;
1687	/** Number of translation blocks per chunk. */
1688	uint32_t cTbsPerChunk;
1689	/** Chunk size. */
1690	uint32_t cbPerChunk;
1691
1692	/** The maximum number of TBs. */
1693	uint32_t cMaxTbs;
1694	/** Total number of TBs in the populated chunks.
1695	* (cAllocatedChunks * cTbsPerChunk) */
1696	uint32_t cTotalTbs;
1697	/** The current number of TBs in use.
1698	* The number of free TBs: cAllocatedTbs - cInUseTbs; */
1699	uint32_t cInUseTbs;
1700	/** Statistics: Number of the cInUseTbs that are native ones. */
1701	uint32_t cNativeTbs;
1702	/** Statistics: Number of the cInUseTbs that are threaded ones. */
1703	uint32_t cThreadedTbs;
1704
1705	/** Where to start pruning TBs from when we're out.
1706	* See iemTbAllocatorAllocSlow for details. */
1707	uint32_t iPruneFrom;
1708	/** Where to start pruning native TBs from when we're out of executable memory.
1709	* See iemTbAllocatorFreeupNativeSpace for details. */
1710	uint32_t iPruneNativeFrom;
1711	uint64_t u64Padding;
1712
1713	/** Statistics: Number of TB allocation calls. */
1714	STAMCOUNTER StatAllocs;
1715	/** Statistics: Number of TB free calls. */
1716	STAMCOUNTER StatFrees;
1717	/** Statistics: Time spend pruning. */
1718	STAMPROFILE StatPrune;
1719	/** Statistics: Time spend pruning native TBs. */
1720	STAMPROFILE StatPruneNative;
1721
1722	/** The delayed free list (see iemTbAlloctorScheduleForFree). */
1723	PIEMTB pDelayedFreeHead;
1724	/* Head of the list of free TBs. */
1725	PIEMTB pTbsFreeHead;
1726
1727	/** Allocation chunks. */
1728	IEMTBCHUNK aChunks[256];
1729	} IEMTBALLOCATOR;
1730	/** Pointer to a TB allocator. */
1731	typedef struct IEMTBALLOCATOR *PIEMTBALLOCATOR;
1732
1733	/** Magic value for the TB allocator (Emmet Harley Cohen). */
1734	#define IEMTBALLOCATOR_MAGIC UINT32_C(0x19900525)
1735
1736
1737	/**
1738	* A per-CPU translation block cache (hash table).
1739	*
1740	* The hash table is allocated once during IEM initialization and size double
1741	* the max TB count, rounded up to the nearest power of two (so we can use and
1742	* AND mask rather than a rest division when hashing).
1743	*/
1744	typedef struct IEMTBCACHE
1745	{
1746	/** Magic value (IEMTBCACHE_MAGIC). */
1747	uint32_t uMagic;
1748	/** Size of the hash table. This is a power of two. */
1749	uint32_t cHash;
1750	/** The mask corresponding to cHash. */
1751	uint32_t uHashMask;
1752	uint32_t uPadding;
1753
1754	/** @name Statistics
1755	* @{ */
1756	/** Number of collisions ever. */
1757	STAMCOUNTER cCollisions;
1758
1759	/** Statistics: Number of TB lookup misses. */
1760	STAMCOUNTER cLookupMisses;
1761	/** Statistics: Number of TB lookup hits via hash table (debug only). */
1762	STAMCOUNTER cLookupHits;
1763	/** Statistics: Number of TB lookup hits via TB associated lookup table (debug only). */
1764	STAMCOUNTER cLookupHitsViaTbLookupTable;
1765	STAMCOUNTER auPadding2[2];
1766	/** Statistics: Collision list length pruning. */
1767	STAMPROFILE StatPrune;
1768	/** @} */
1769
1770	/** The hash table itself.
1771	* @note The lower 6 bits of the pointer is used for keeping the collision
1772	* list length, so we can take action when it grows too long.
1773	* This works because TBs are allocated using a 64 byte (or
1774	* higher) alignment from page aligned chunks of memory, so the lower
1775	* 6 bits of the address will always be zero.
1776	* See IEMTBCACHE_PTR_COUNT_MASK, IEMTBCACHE_PTR_MAKE and friends.
1777	*/
1778	RT_FLEXIBLE_ARRAY_EXTENSION
1779	PIEMTB apHash[RT_FLEXIBLE_ARRAY];
1780	} IEMTBCACHE;
1781	/** Pointer to a per-CPU translation block cahce. */
1782	typedef IEMTBCACHE *PIEMTBCACHE;
1783
1784	/** Magic value for IEMTBCACHE (Johnny O'Neal). */
1785	#define IEMTBCACHE_MAGIC UINT32_C(0x19561010)
1786
1787	/** The collision count mask for IEMTBCACHE::apHash entries. */
1788	#define IEMTBCACHE_PTR_COUNT_MASK ((uintptr_t)0x3f)
1789	/** The max collision count for IEMTBCACHE::apHash entries before pruning. */
1790	#define IEMTBCACHE_PTR_MAX_COUNT ((uintptr_t)0x30)
1791	/** Combine a TB pointer and a collision list length into a value for an
1792	* IEMTBCACHE::apHash entry. */
1793	#define IEMTBCACHE_PTR_MAKE(a_pTb, a_cCount) (PIEMTB)((uintptr_t)(a_pTb) \| (a_cCount))
1794	/** Combine a TB pointer and a collision list length into a value for an
1795	* IEMTBCACHE::apHash entry. */
1796	#define IEMTBCACHE_PTR_GET_TB(a_pHashEntry) (PIEMTB)((uintptr_t)(a_pHashEntry) & ~IEMTBCACHE_PTR_COUNT_MASK)
1797	/** Combine a TB pointer and a collision list length into a value for an
1798	* IEMTBCACHE::apHash entry. */
1799	#define IEMTBCACHE_PTR_GET_COUNT(a_pHashEntry) ((uintptr_t)(a_pHashEntry) & IEMTBCACHE_PTR_COUNT_MASK)
1800
1801	/**
1802	* Calculates the hash table slot for a TB from physical PC address and TB flags.
1803	*/
1804	#define IEMTBCACHE_HASH(a_paCache, a_fTbFlags, a_GCPhysPc) \
1805	IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, (a_fTbFlags) & IEMTB_F_KEY_MASK, a_GCPhysPc)
1806
1807	/**
1808	* Calculates the hash table slot for a TB from physical PC address and TB
1809	* flags, ASSUMING the caller has applied IEMTB_F_KEY_MASK to @a a_fTbFlags.
1810	*/
1811	#define IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, a_fTbFlags, a_GCPhysPc) \
1812	(((uint32_t)(a_GCPhysPc) ^ (a_fTbFlags)) & (a_paCache)->uHashMask)
1813
1814
1815	/** @name IEMBRANCHED_F_XXX - Branched indicator (IEMCPU::fTbBranched).
1816	*
1817	* These flags parallels the main IEM_CIMPL_F_BRANCH_XXX flags.
1818	*
1819	* @{ */
1820	/** Value if no branching happened recently. */
1821	#define IEMBRANCHED_F_NO UINT8_C(0x00)
1822	/** Flag set if direct branch, clear if absolute or indirect. */
1823	#define IEMBRANCHED_F_DIRECT UINT8_C(0x01)
1824	/** Flag set if indirect branch, clear if direct or relative. */
1825	#define IEMBRANCHED_F_INDIRECT UINT8_C(0x02)
1826	/** Flag set if relative branch, clear if absolute or indirect. */
1827	#define IEMBRANCHED_F_RELATIVE UINT8_C(0x04)
1828	/** Flag set if conditional branch, clear if unconditional. */
1829	#define IEMBRANCHED_F_CONDITIONAL UINT8_C(0x08)
1830	/** Flag set if it's a far branch. */
1831	#define IEMBRANCHED_F_FAR UINT8_C(0x10)
1832	/** Flag set if the stack pointer is modified. */
1833	#define IEMBRANCHED_F_STACK UINT8_C(0x20)
1834	/** Flag set if the stack pointer and (maybe) the stack segment are modified. */
1835	#define IEMBRANCHED_F_STACK_FAR UINT8_C(0x40)
1836	/** Flag set (by IEM_MC_REL_JMP_XXX) if it's a zero bytes relative jump. */
1837	#define IEMBRANCHED_F_ZERO UINT8_C(0x80)
1838	/** @} */
1839
1840
1841	/**
1842	* The per-CPU IEM state.
1843	*/
1844	typedef struct IEMCPU
1845	{
1846	/** Info status code that needs to be propagated to the IEM caller.
1847	* This cannot be passed internally, as it would complicate all success
1848	* checks within the interpreter making the code larger and almost impossible
1849	* to get right. Instead, we'll store status codes to pass on here. Each
1850	* source of these codes will perform appropriate sanity checks. */
1851	int32_t rcPassUp; /* 0x00 */
1852	/** Execution flag, IEM_F_XXX. */
1853	uint32_t fExec; /* 0x04 */
1854
1855	/** @name Decoder state.
1856	* @{ */
1857	#ifdef IEM_WITH_CODE_TLB
1858	/** The offset of the next instruction byte. */
1859	uint32_t offInstrNextByte; /* 0x08 */
1860	/** The number of bytes available at pbInstrBuf for the current instruction.
1861	* This takes the max opcode length into account so that doesn't need to be
1862	* checked separately. */
1863	uint32_t cbInstrBuf; /* 0x0c */
1864	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
1865	* This can be NULL if the page isn't mappable for some reason, in which
1866	* case we'll do fallback stuff.
1867	*
1868	* If we're executing an instruction from a user specified buffer,
1869	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
1870	* aligned pointer but pointer to the user data.
1871	*
1872	* For instructions crossing pages, this will start on the first page and be
1873	* advanced to the next page by the time we've decoded the instruction. This
1874	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
1875	*/
1876	uint8_t const pbInstrBuf; / 0x10 */
1877	# if ARCH_BITS == 32
1878	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
1879	# endif
1880	/** The program counter corresponding to pbInstrBuf.
1881	* This is set to a non-canonical address when we need to invalidate it. */
1882	uint64_t uInstrBufPc; /* 0x18 */
1883	/** The guest physical address corresponding to pbInstrBuf. */
1884	RTGCPHYS GCPhysInstrBuf; /* 0x20 */
1885	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
1886	* This takes the CS segment limit into account.
1887	* @note Set to zero when the code TLB is flushed to trigger TLB reload. */
1888	uint16_t cbInstrBufTotal; /* 0x28 */
1889	/** Offset into pbInstrBuf of the first byte of the current instruction.
1890	* Can be negative to efficiently handle cross page instructions. */
1891	int16_t offCurInstrStart; /* 0x2a */
1892
1893	# ifndef IEM_WITH_OPAQUE_DECODER_STATE
1894	/** The prefix mask (IEM_OP_PRF_XXX). */
1895	uint32_t fPrefixes; /* 0x2c */
1896	/** The extra REX ModR/M register field bit (REX.R << 3). */
1897	uint8_t uRexReg; /* 0x30 */
1898	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1899	* (REX.B << 3). */
1900	uint8_t uRexB; /* 0x31 */
1901	/** The extra REX SIB index field bit (REX.X << 3). */
1902	uint8_t uRexIndex; /* 0x32 */
1903
1904	/** The effective segment register (X86_SREG_XXX). */
1905	uint8_t iEffSeg; /* 0x33 */
1906
1907	/** The offset of the ModR/M byte relative to the start of the instruction. */
1908	uint8_t offModRm; /* 0x34 */
1909
1910	# ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
1911	/** The current offset into abOpcode. */
1912	uint8_t offOpcode; /* 0x35 */
1913	# else
1914	uint8_t bUnused; /* 0x35 */
1915	# endif
1916	# else /* IEM_WITH_OPAQUE_DECODER_STATE */
1917	uint8_t abOpaqueDecoderPart1[0x36 - 0x2c];
1918	# endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1919
1920	#else /* !IEM_WITH_CODE_TLB */
1921	# ifndef IEM_WITH_OPAQUE_DECODER_STATE
1922	/** The size of what has currently been fetched into abOpcode. */
1923	uint8_t cbOpcode; /* 0x08 */
1924	/** The current offset into abOpcode. */
1925	uint8_t offOpcode; /* 0x09 */
1926	/** The offset of the ModR/M byte relative to the start of the instruction. */
1927	uint8_t offModRm; /* 0x0a */
1928
1929	/** The effective segment register (X86_SREG_XXX). */
1930	uint8_t iEffSeg; /* 0x0b */
1931
1932	/** The prefix mask (IEM_OP_PRF_XXX). */
1933	uint32_t fPrefixes; /* 0x0c */
1934	/** The extra REX ModR/M register field bit (REX.R << 3). */
1935	uint8_t uRexReg; /* 0x10 */
1936	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1937	* (REX.B << 3). */
1938	uint8_t uRexB; /* 0x11 */
1939	/** The extra REX SIB index field bit (REX.X << 3). */
1940	uint8_t uRexIndex; /* 0x12 */
1941
1942	# else /* IEM_WITH_OPAQUE_DECODER_STATE */
1943	uint8_t abOpaqueDecoderPart1[0x13 - 0x08];
1944	# endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1945	#endif /* !IEM_WITH_CODE_TLB */
1946
1947	#ifndef IEM_WITH_OPAQUE_DECODER_STATE
1948	/** The effective operand mode. */
1949	IEMMODE enmEffOpSize; /* 0x36, 0x13 */
1950	/** The default addressing mode. */
1951	IEMMODE enmDefAddrMode; /* 0x37, 0x14 */
1952	/** The effective addressing mode. */
1953	IEMMODE enmEffAddrMode; /* 0x38, 0x15 */
1954	/** The default operand mode. */
1955	IEMMODE enmDefOpSize; /* 0x39, 0x16 */
1956
1957	/** Prefix index (VEX.pp) for two byte and three byte tables. */
1958	uint8_t idxPrefix; /* 0x3a, 0x17 */
1959	/** 3rd VEX/EVEX/XOP register.
1960	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
1961	uint8_t uVex3rdReg; /* 0x3b, 0x18 */
1962	/** The VEX/EVEX/XOP length field. */
1963	uint8_t uVexLength; /* 0x3c, 0x19 */
1964	/** Additional EVEX stuff. */
1965	uint8_t fEvexStuff; /* 0x3d, 0x1a */
1966
1967	# ifndef IEM_WITH_CODE_TLB
1968	/** Explicit alignment padding. */
1969	uint8_t abAlignment2a[1]; /* 0x1b */
1970	# endif
1971	/** The FPU opcode (FOP). */
1972	uint16_t uFpuOpcode; /* 0x3e, 0x1c */
1973	# ifndef IEM_WITH_CODE_TLB
1974	/** Explicit alignment padding. */
1975	uint8_t abAlignment2b[2]; /* 0x1e */
1976	# endif
1977
1978	/** The opcode bytes. */
1979	uint8_t abOpcode[15]; /* 0x40, 0x20 */
1980	/** Explicit alignment padding. */
1981	# ifdef IEM_WITH_CODE_TLB
1982	//uint8_t abAlignment2c[0x4f - 0x4f]; /* 0x4f */
1983	# else
1984	uint8_t abAlignment2c[0x4f - 0x2f]; /* 0x2f */
1985	# endif
1986
1987	#else /* IEM_WITH_OPAQUE_DECODER_STATE */
1988	# ifdef IEM_WITH_CODE_TLB
1989	uint8_t abOpaqueDecoderPart2[0x4f - 0x36];
1990	# else
1991	uint8_t abOpaqueDecoderPart2[0x4f - 0x13];
1992	# endif
1993	#endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1994	/** @} */
1995
1996
1997	/** The number of active guest memory mappings. */
1998	uint8_t cActiveMappings; /* 0x4f, 0x4f */
1999
2000	/** Records for tracking guest memory mappings. */
2001	struct
2002	{
2003	/** The address of the mapped bytes. */
2004	R3R0PTRTYPE(void *) pv;
2005	/** The access flags (IEM_ACCESS_XXX).
2006	* IEM_ACCESS_INVALID if the entry is unused. */
2007	uint32_t fAccess;
2008	#if HC_ARCH_BITS == 64
2009	uint32_t u32Alignment4; /*< Alignment padding. /
2010	#endif
2011	} aMemMappings[3]; /* 0x50 LB 0x30 */
2012
2013	/** Locking records for the mapped memory. */
2014	union
2015	{
2016	PGMPAGEMAPLOCK Lock;
2017	uint64_t au64Padding[2];
2018	} aMemMappingLocks[3]; /* 0x80 LB 0x30 */
2019
2020	/** Bounce buffer info.
2021	* This runs in parallel to aMemMappings. */
2022	struct
2023	{
2024	/** The physical address of the first byte. */
2025	RTGCPHYS GCPhysFirst;
2026	/** The physical address of the second page. */
2027	RTGCPHYS GCPhysSecond;
2028	/** The number of bytes in the first page. */
2029	uint16_t cbFirst;
2030	/** The number of bytes in the second page. */
2031	uint16_t cbSecond;
2032	/** Whether it's unassigned memory. */
2033	bool fUnassigned;
2034	/** Explicit alignment padding. */
2035	bool afAlignment5[3];
2036	} aMemBbMappings[3]; /* 0xb0 LB 0x48 */
2037
2038	/** The flags of the current exception / interrupt. */
2039	uint32_t fCurXcpt; /* 0xf8 */
2040	/** The current exception / interrupt. */
2041	uint8_t uCurXcpt; /* 0xfc */
2042	/** Exception / interrupt recursion depth. */
2043	int8_t cXcptRecursions; /* 0xfb */
2044
2045	/** The next unused mapping index.
2046	* @todo try find room for this up with cActiveMappings. */
2047	uint8_t iNextMapping; /* 0xfd */
2048	uint8_t abAlignment7[1];
2049
2050	/** Bounce buffer storage.
2051	* This runs in parallel to aMemMappings and aMemBbMappings. */
2052	struct
2053	{
2054	uint8_t ab[512];
2055	} aBounceBuffers[3]; /* 0x100 LB 0x600 */
2056
2057
2058	/** Pointer set jump buffer - ring-3 context. */
2059	R3PTRTYPE(jmp_buf *) pJmpBufR3;
2060	/** Pointer set jump buffer - ring-0 context. */
2061	R0PTRTYPE(jmp_buf *) pJmpBufR0;
2062
2063	/** @todo Should move this near @a fCurXcpt later. */
2064	/** The CR2 for the current exception / interrupt. */
2065	uint64_t uCurXcptCr2;
2066	/** The error code for the current exception / interrupt. */
2067	uint32_t uCurXcptErr;
2068
2069	/** @name Statistics
2070	* @{ */
2071	/** The number of instructions we've executed. */
2072	uint32_t cInstructions;
2073	/** The number of potential exits. */
2074	uint32_t cPotentialExits;
2075	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
2076	* This may contain uncommitted writes. */
2077	uint32_t cbWritten;
2078	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
2079	uint32_t cRetInstrNotImplemented;
2080	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
2081	uint32_t cRetAspectNotImplemented;
2082	/** Counts informational statuses returned (other than VINF_SUCCESS). */
2083	uint32_t cRetInfStatuses;
2084	/** Counts other error statuses returned. */
2085	uint32_t cRetErrStatuses;
2086	/** Number of times rcPassUp has been used. */
2087	uint32_t cRetPassUpStatus;
2088	/** Number of times RZ left with instruction commit pending for ring-3. */
2089	uint32_t cPendingCommit;
2090	/** Number of misaligned (host sense) atomic instruction accesses. */
2091	uint32_t cMisalignedAtomics;
2092	/** Number of long jumps. */
2093	uint32_t cLongJumps;
2094	/** @} */
2095
2096	/** @name Target CPU information.
2097	* @{ */
2098	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
2099	/** The target CPU. */
2100	uint8_t uTargetCpu;
2101	#else
2102	uint8_t bTargetCpuPadding;
2103	#endif
2104	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
2105	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
2106	* native host support and the 2nd for when there is.
2107	*
2108	* The two values are typically indexed by a g_CpumHostFeatures bit.
2109	*
2110	* This is for instance used for the BSF & BSR instructions where AMD and
2111	* Intel CPUs produce different EFLAGS. */
2112	uint8_t aidxTargetCpuEflFlavour[2];
2113
2114	/** The CPU vendor. */
2115	CPUMCPUVENDOR enmCpuVendor;
2116	/** @} */
2117
2118	/** @name Host CPU information.
2119	* @{ */
2120	/** The CPU vendor. */
2121	CPUMCPUVENDOR enmHostCpuVendor;
2122	/** @} */
2123
2124	/** Counts RDMSR \#GP(0) LogRel(). */
2125	uint8_t cLogRelRdMsr;
2126	/** Counts WRMSR \#GP(0) LogRel(). */
2127	uint8_t cLogRelWrMsr;
2128	/** Alignment padding. */
2129	uint8_t abAlignment9[42];
2130
2131	/** @name Recompilation
2132	* @{ */
2133	/** Pointer to the current translation block.
2134	* This can either be one being executed or one being compiled. */
2135	R3PTRTYPE(PIEMTB) pCurTbR3;
2136	#ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
2137	/** Frame pointer for the last native TB to execute. */
2138	R3PTRTYPE(void *) pvTbFramePointerR3;
2139	#else
2140	R3PTRTYPE(void *) pvUnusedR3;
2141	#endif
2142	#ifdef IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS
2143	/** The saved host floating point control register (MXCSR on x86, FPCR on arm64)
2144	* needing restore when the TB finished, IEMNATIVE_SIMD_FP_CTRL_REG_NOT_MODIFIED indicates the TB
2145	* didn't modify it so we don't need to restore it. */
2146	# ifdef RT_ARCH_AMD64
2147	uint32_t uRegFpCtrl;
2148	/** Temporary copy of MXCSR for stmxcsr/ldmxcsr (so we don't have to fiddle with stack pointers). */
2149	uint32_t uRegMxcsrTmp;
2150	# elif defined(RT_ARCH_ARM64)
2151	uint64_t uRegFpCtrl;
2152	# else
2153	# error "Port me"
2154	# endif
2155	#else
2156	uint64_t u64Unused;
2157	#endif
2158	/** Fixed TB used for threaded recompilation.
2159	* This is allocated once with maxed-out sizes and re-used afterwards. */
2160	R3PTRTYPE(PIEMTB) pThrdCompileTbR3;
2161	/** Pointer to the ring-3 TB cache for this EMT. */
2162	R3PTRTYPE(PIEMTBCACHE) pTbCacheR3;
2163	/** Pointer to the ring-3 TB lookup entry.
2164	* This either points to pTbLookupEntryDummyR3 or an actually lookuptable
2165	* entry, thus it can always safely be used w/o NULL checking. */
2166	R3PTRTYPE(PIEMTB *) ppTbLookupEntryR3;
2167	/** The PC (RIP) at the start of pCurTbR3/pCurTbR0.
2168	* The TBs are based on physical addresses, so this is needed to correleated
2169	* RIP to opcode bytes stored in the TB (AMD-V / VT-x). */
2170	uint64_t uCurTbStartPc;
2171	/** Number of threaded TBs executed. */
2172	uint64_t cTbExecThreaded;
2173	/** Number of native TBs executed. */
2174	uint64_t cTbExecNative;
2175	/** Whether we need to check the opcode bytes for the current instruction.
2176	* This is set by a previous instruction if it modified memory or similar. */
2177	bool fTbCheckOpcodes;
2178	/** Indicates whether and how we just branched - IEMBRANCHED_F_XXX. */
2179	uint8_t fTbBranched;
2180	/** Set when GCPhysInstrBuf is updated because of a page crossing. */
2181	bool fTbCrossedPage;
2182	/** Whether to end the current TB. */
2183	bool fEndTb;
2184	/** Number of instructions before we need emit an IRQ check call again.
2185	* This helps making sure we don't execute too long w/o checking for
2186	* interrupts and immediately following instructions that may enable
2187	* interrupts (e.g. POPF, IRET, STI). With STI an additional hack is
2188	* required to make sure we check following the next instruction as well, see
2189	* fTbCurInstrIsSti. */
2190	uint8_t cInstrTillIrqCheck;
2191	/** Indicates that the current instruction is an STI. This is set by the
2192	* iemCImpl_sti code and subsequently cleared by the recompiler. */
2193	bool fTbCurInstrIsSti;
2194	/** The size of the IEMTB::pabOpcodes allocation in pThrdCompileTbR3. */
2195	uint16_t cbOpcodesAllocated;
2196	/** The current instruction number in a native TB.
2197	* This is set by code that may trigger an unexpected TB exit (throw/longjmp)
2198	* and will be picked up by the TB execution loop. Only used when
2199	* IEMNATIVE_WITH_INSTRUCTION_COUNTING is defined. */
2200	uint8_t idxTbCurInstr;
2201	/** Spaced reserved for recompiler data / alignment. */
2202	bool afRecompilerStuff1[3];
2203	/** The virtual sync time at the last timer poll call. */
2204	uint32_t msRecompilerPollNow;
2205	/** The IEMTB::cUsed value when to attempt native recompilation of a TB. */
2206	uint32_t uTbNativeRecompileAtUsedCount;
2207	/** The IEM_CIMPL_F_XXX mask for the current instruction. */
2208	uint32_t fTbCurInstr;
2209	/** The IEM_CIMPL_F_XXX mask for the previous instruction. */
2210	uint32_t fTbPrevInstr;
2211	/** Strict: Tracking skipped EFLAGS calculations. Any bits set here are
2212	* currently not up to date in EFLAGS. */
2213	uint32_t fSkippingEFlags;
2214	/** Previous GCPhysInstrBuf value - only valid if fTbCrossedPage is set. */
2215	RTGCPHYS GCPhysInstrBufPrev;
2216	/** Pointer to the ring-3 TB allocator for this EMT. */
2217	R3PTRTYPE(PIEMTBALLOCATOR) pTbAllocatorR3;
2218	/** Pointer to the ring-3 executable memory allocator for this EMT. */
2219	R3PTRTYPE(struct IEMEXECMEMALLOCATOR *) pExecMemAllocatorR3;
2220	/** Pointer to the native recompiler state for ring-3. */
2221	R3PTRTYPE(struct IEMRECOMPILERSTATE *) pNativeRecompilerStateR3;
2222	/** Dummy entry for ppTbLookupEntryR3. */
2223	R3PTRTYPE(PIEMTB) pTbLookupEntryDummyR3;
2224
2225	/** Dummy TLB entry used for accesses to pages with databreakpoints. */
2226	IEMTLBENTRY DataBreakpointTlbe;
2227
2228	/** Threaded TB statistics: Times TB execution was broken off before reaching the end. */
2229	STAMCOUNTER StatTbThreadedExecBreaks;
2230	/** Statistics: Times BltIn_CheckIrq breaks out of the TB. */
2231	STAMCOUNTER StatCheckIrqBreaks;
2232	/** Statistics: Times BltIn_CheckMode breaks out of the TB. */
2233	STAMCOUNTER StatCheckModeBreaks;
2234	/** Threaded TB statistics: Times execution break on call with lookup entries. */
2235	STAMCOUNTER StatTbThreadedExecBreaksWithLookup;
2236	/** Threaded TB statistics: Times execution break on call without lookup entries. */
2237	STAMCOUNTER StatTbThreadedExecBreaksWithoutLookup;
2238	/** Statistics: Times a post jump target check missed and had to find new TB. */
2239	STAMCOUNTER StatCheckBranchMisses;
2240	/** Statistics: Times a jump or page crossing required a TB with CS.LIM checking. */
2241	STAMCOUNTER StatCheckNeedCsLimChecking;
2242	/** Statistics: Times a loop was detected within a TB.. */
2243	STAMCOUNTER StatTbLoopInTbDetected;
2244	/** Exec memory allocator statistics: Number of times allocaintg executable memory failed. */
2245	STAMCOUNTER StatNativeExecMemInstrBufAllocFailed;
2246	/** Native TB statistics: Number of fully recompiled TBs. */
2247	STAMCOUNTER StatNativeFullyRecompiledTbs;
2248	/** TB statistics: Number of instructions per TB. */
2249	STAMPROFILE StatTbInstr;
2250	/** TB statistics: Number of TB lookup table entries per TB. */
2251	STAMPROFILE StatTbLookupEntries;
2252	/** Threaded TB statistics: Number of calls per TB. */
2253	STAMPROFILE StatTbThreadedCalls;
2254	/** Native TB statistics: Native code size per TB. */
2255	STAMPROFILE StatTbNativeCode;
2256	/** Native TB statistics: Profiling native recompilation. */
2257	STAMPROFILE StatNativeRecompilation;
2258	/** Native TB statistics: Number of calls per TB that were recompiled properly. */
2259	STAMPROFILE StatNativeCallsRecompiled;
2260	/** Native TB statistics: Number of threaded calls per TB that weren't recompiled. */
2261	STAMPROFILE StatNativeCallsThreaded;
2262	/** Native recompiled execution: TLB hits for data fetches. */
2263	STAMCOUNTER StatNativeTlbHitsForFetch;
2264	/** Native recompiled execution: TLB hits for data stores. */
2265	STAMCOUNTER StatNativeTlbHitsForStore;
2266	/** Native recompiled execution: TLB hits for stack accesses. */
2267	STAMCOUNTER StatNativeTlbHitsForStack;
2268	/** Native recompiled execution: TLB hits for mapped accesses. */
2269	STAMCOUNTER StatNativeTlbHitsForMapped;
2270	/** Native recompiled execution: Code TLB misses for new page. */
2271	STAMCOUNTER StatNativeCodeTlbMissesNewPage;
2272	/** Native recompiled execution: Code TLB hits for new page. */
2273	STAMCOUNTER StatNativeCodeTlbHitsForNewPage;
2274	/** Native recompiled execution: Code TLB misses for new page with offset. */
2275	STAMCOUNTER StatNativeCodeTlbMissesNewPageWithOffset;
2276	/** Native recompiled execution: Code TLB hits for new page with offset. */
2277	STAMCOUNTER StatNativeCodeTlbHitsForNewPageWithOffset;
2278
2279	/** Native recompiler: Number of calls to iemNativeRegAllocFindFree. */
2280	STAMCOUNTER StatNativeRegFindFree;
2281	/** Native recompiler: Number of times iemNativeRegAllocFindFree needed
2282	* to free a variable. */
2283	STAMCOUNTER StatNativeRegFindFreeVar;
2284	/** Native recompiler: Number of times iemNativeRegAllocFindFree did
2285	* not need to free any variables. */
2286	STAMCOUNTER StatNativeRegFindFreeNoVar;
2287	/** Native recompiler: Liveness info freed shadowed guest registers in
2288	* iemNativeRegAllocFindFree. */
2289	STAMCOUNTER StatNativeRegFindFreeLivenessUnshadowed;
2290	/** Native recompiler: Liveness info helped with the allocation in
2291	* iemNativeRegAllocFindFree. */
2292	STAMCOUNTER StatNativeRegFindFreeLivenessHelped;
2293
2294	/** Native recompiler: Number of times status flags calc has been skipped. */
2295	STAMCOUNTER StatNativeEflSkippedArithmetic;
2296	/** Native recompiler: Number of times status flags calc has been skipped. */
2297	STAMCOUNTER StatNativeEflSkippedLogical;
2298
2299	/** Native recompiler: Number of opportunities to skip EFLAGS.CF updating. */
2300	STAMCOUNTER StatNativeLivenessEflCfSkippable;
2301	/** Native recompiler: Number of opportunities to skip EFLAGS.PF updating. */
2302	STAMCOUNTER StatNativeLivenessEflPfSkippable;
2303	/** Native recompiler: Number of opportunities to skip EFLAGS.AF updating. */
2304	STAMCOUNTER StatNativeLivenessEflAfSkippable;
2305	/** Native recompiler: Number of opportunities to skip EFLAGS.ZF updating. */
2306	STAMCOUNTER StatNativeLivenessEflZfSkippable;
2307	/** Native recompiler: Number of opportunities to skip EFLAGS.SF updating. */
2308	STAMCOUNTER StatNativeLivenessEflSfSkippable;
2309	/** Native recompiler: Number of opportunities to skip EFLAGS.OF updating. */
2310	STAMCOUNTER StatNativeLivenessEflOfSkippable;
2311	/** Native recompiler: Number of required EFLAGS.CF updates. */
2312	STAMCOUNTER StatNativeLivenessEflCfRequired;
2313	/** Native recompiler: Number of required EFLAGS.PF updates. */
2314	STAMCOUNTER StatNativeLivenessEflPfRequired;
2315	/** Native recompiler: Number of required EFLAGS.AF updates. */
2316	STAMCOUNTER StatNativeLivenessEflAfRequired;
2317	/** Native recompiler: Number of required EFLAGS.ZF updates. */
2318	STAMCOUNTER StatNativeLivenessEflZfRequired;
2319	/** Native recompiler: Number of required EFLAGS.SF updates. */
2320	STAMCOUNTER StatNativeLivenessEflSfRequired;
2321	/** Native recompiler: Number of required EFLAGS.OF updates. */
2322	STAMCOUNTER StatNativeLivenessEflOfRequired;
2323	/** Native recompiler: Number of potentially delayable EFLAGS.CF updates. */
2324	STAMCOUNTER StatNativeLivenessEflCfDelayable;
2325	/** Native recompiler: Number of potentially delayable EFLAGS.PF updates. */
2326	STAMCOUNTER StatNativeLivenessEflPfDelayable;
2327	/** Native recompiler: Number of potentially delayable EFLAGS.AF updates. */
2328	STAMCOUNTER StatNativeLivenessEflAfDelayable;
2329	/** Native recompiler: Number of potentially delayable EFLAGS.ZF updates. */
2330	STAMCOUNTER StatNativeLivenessEflZfDelayable;
2331	/** Native recompiler: Number of potentially delayable EFLAGS.SF updates. */
2332	STAMCOUNTER StatNativeLivenessEflSfDelayable;
2333	/** Native recompiler: Number of potentially delayable EFLAGS.OF updates. */
2334	STAMCOUNTER StatNativeLivenessEflOfDelayable;
2335
2336	/** Native recompiler: Number of potential PC updates in total. */
2337	STAMCOUNTER StatNativePcUpdateTotal;
2338	/** Native recompiler: Number of PC updates which could be delayed. */
2339	STAMCOUNTER StatNativePcUpdateDelayed;
2340
2341	//#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
2342	/** Native recompiler: Number of calls to iemNativeSimdRegAllocFindFree. */
2343	STAMCOUNTER StatNativeSimdRegFindFree;
2344	/** Native recompiler: Number of times iemNativeSimdRegAllocFindFree needed
2345	* to free a variable. */
2346	STAMCOUNTER StatNativeSimdRegFindFreeVar;
2347	/** Native recompiler: Number of times iemNativeSimdRegAllocFindFree did
2348	* not need to free any variables. */
2349	STAMCOUNTER StatNativeSimdRegFindFreeNoVar;
2350	/** Native recompiler: Liveness info freed shadowed guest registers in
2351	* iemNativeSimdRegAllocFindFree. */
2352	STAMCOUNTER StatNativeSimdRegFindFreeLivenessUnshadowed;
2353	/** Native recompiler: Liveness info helped with the allocation in
2354	* iemNativeSimdRegAllocFindFree. */
2355	STAMCOUNTER StatNativeSimdRegFindFreeLivenessHelped;
2356
2357	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks. */
2358	STAMCOUNTER StatNativeMaybeDeviceNotAvailXcptCheckPotential;
2359	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() checks. */
2360	STAMCOUNTER StatNativeMaybeWaitDeviceNotAvailXcptCheckPotential;
2361	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks. */
2362	STAMCOUNTER StatNativeMaybeSseXcptCheckPotential;
2363	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks. */
2364	STAMCOUNTER StatNativeMaybeAvxXcptCheckPotential;
2365
2366	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks omitted. */
2367	STAMCOUNTER StatNativeMaybeDeviceNotAvailXcptCheckOmitted;
2368	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() checks omitted. */
2369	STAMCOUNTER StatNativeMaybeWaitDeviceNotAvailXcptCheckOmitted;
2370	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks omitted. */
2371	STAMCOUNTER StatNativeMaybeSseXcptCheckOmitted;
2372	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks omitted. */
2373	STAMCOUNTER StatNativeMaybeAvxXcptCheckOmitted;
2374	//#endif
2375
2376	/** Native recompiler: The TB finished executing completely without jumping to a an exit label.
2377	* Not availabe in release builds. */
2378	STAMCOUNTER StatNativeTbFinished;
2379	/** Native recompiler: The TB finished executing jumping to the ReturnBreak label. */
2380	STAMCOUNTER StatNativeTbExitReturnBreak;
2381	/** Native recompiler: The TB finished executing jumping to the ReturnBreakFF label. */
2382	STAMCOUNTER StatNativeTbExitReturnBreakFF;
2383	/** Native recompiler: The TB finished executing jumping to the ReturnWithFlags label. */
2384	STAMCOUNTER StatNativeTbExitReturnWithFlags;
2385	/** Native recompiler: The TB finished executing with other non-zero status. */
2386	STAMCOUNTER StatNativeTbExitReturnOtherStatus;
2387	/** Native recompiler: The TB finished executing via throw / long jump. */
2388	STAMCOUNTER StatNativeTbExitLongJump;
2389	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2390	* label, but directly jumped to the next TB, scenario \#1 w/o IRQ checks. */
2391	STAMCOUNTER StatNativeTbExitDirectLinking1NoIrq;
2392	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2393	* label, but directly jumped to the next TB, scenario \#1 with IRQ checks. */
2394	STAMCOUNTER StatNativeTbExitDirectLinking1Irq;
2395	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2396	* label, but directly jumped to the next TB, scenario \#1 w/o IRQ checks. */
2397	STAMCOUNTER StatNativeTbExitDirectLinking2NoIrq;
2398	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2399	* label, but directly jumped to the next TB, scenario \#2 with IRQ checks. */
2400	STAMCOUNTER StatNativeTbExitDirectLinking2Irq;
2401
2402	/** Native recompiler: The TB finished executing jumping to the RaiseDe label. */
2403	STAMCOUNTER StatNativeTbExitRaiseDe;
2404	/** Native recompiler: The TB finished executing jumping to the RaiseUd label. */
2405	STAMCOUNTER StatNativeTbExitRaiseUd;
2406	/** Native recompiler: The TB finished executing jumping to the RaiseSseRelated label. */
2407	STAMCOUNTER StatNativeTbExitRaiseSseRelated;
2408	/** Native recompiler: The TB finished executing jumping to the RaiseAvxRelated label. */
2409	STAMCOUNTER StatNativeTbExitRaiseAvxRelated;
2410	/** Native recompiler: The TB finished executing jumping to the RaiseSseAvxFpRelated label. */
2411	STAMCOUNTER StatNativeTbExitRaiseSseAvxFpRelated;
2412	/** Native recompiler: The TB finished executing jumping to the RaiseNm label. */
2413	STAMCOUNTER StatNativeTbExitRaiseNm;
2414	/** Native recompiler: The TB finished executing jumping to the RaiseGp0 label. */
2415	STAMCOUNTER StatNativeTbExitRaiseGp0;
2416	/** Native recompiler: The TB finished executing jumping to the RaiseMf label. */
2417	STAMCOUNTER StatNativeTbExitRaiseMf;
2418	/** Native recompiler: The TB finished executing jumping to the RaiseXf label. */
2419	STAMCOUNTER StatNativeTbExitRaiseXf;
2420	/** Native recompiler: The TB finished executing jumping to the ObsoleteTb label. */
2421	STAMCOUNTER StatNativeTbExitObsoleteTb;
2422
2423	/** Native recompiler: Failure situations with direct linking scenario \#1.
2424	* Counter with StatNativeTbExitReturnBreak. Not in release builds.
2425	* @{ */
2426	STAMCOUNTER StatNativeTbExitDirectLinking1NoTb;
2427	STAMCOUNTER StatNativeTbExitDirectLinking1MismatchGCPhysPc;
2428	STAMCOUNTER StatNativeTbExitDirectLinking1MismatchFlags;
2429	STAMCOUNTER StatNativeTbExitDirectLinking1PendingIrq;
2430	/** @} */
2431
2432	/** Native recompiler: Failure situations with direct linking scenario \#2.
2433	* Counter with StatNativeTbExitReturnBreak. Not in release builds.
2434	* @{ */
2435	STAMCOUNTER StatNativeTbExitDirectLinking2NoTb;
2436	STAMCOUNTER StatNativeTbExitDirectLinking2MismatchGCPhysPc;
2437	STAMCOUNTER StatNativeTbExitDirectLinking2MismatchFlags;
2438	STAMCOUNTER StatNativeTbExitDirectLinking2PendingIrq;
2439	/** @} */
2440
2441	/** iemMemMap and iemMemMapJmp statistics.
2442	* @{ */
2443	STAMCOUNTER StatMemMapJmp;
2444	STAMCOUNTER StatMemMapNoJmp;
2445	STAMCOUNTER StatMemBounceBufferCrossPage;
2446	STAMCOUNTER StatMemBounceBufferMapPhys;
2447	/** @} */
2448
2449	#ifdef IEM_WITH_TLB_TRACE
2450	uint64_t au64Padding[2];
2451	#else
2452	uint64_t au64Padding[4];
2453	#endif
2454	/** @} */
2455
2456	#ifdef IEM_WITH_TLB_TRACE
2457	/** The end (next) trace entry. */
2458	uint32_t idxTlbTraceEntry;
2459	/** Number of trace entries allocated expressed as a power of two. */
2460	uint32_t cTlbTraceEntriesShift;
2461	/** The trace entries. */
2462	PIEMTLBTRACEENTRY paTlbTraceEntries;
2463	#endif
2464
2465	/** Data TLB.
2466	* @remarks Must be 64-byte aligned. */
2467	IEMTLB DataTlb;
2468	/** Instruction TLB.
2469	* @remarks Must be 64-byte aligned. */
2470	IEMTLB CodeTlb;
2471
2472	/** Exception statistics. */
2473	STAMCOUNTER aStatXcpts[32];
2474	/** Interrupt statistics. */
2475	uint32_t aStatInts[256];
2476
2477	#if defined(VBOX_WITH_STATISTICS) && !defined(DOXYGEN_RUNNING) && !defined(IEM_WITHOUT_INSTRUCTION_STATS)
2478	/** Instruction statistics for ring-0/raw-mode. */
2479	IEMINSTRSTATS StatsRZ;
2480	/** Instruction statistics for ring-3. */
2481	IEMINSTRSTATS StatsR3;
2482	# ifdef VBOX_WITH_IEM_RECOMPILER
2483	/** Statistics per threaded function call.
2484	* Updated by both the threaded and native recompilers. */
2485	uint32_t acThreadedFuncStats[0x6000 /24576/];
2486	# endif
2487	#endif
2488	} IEMCPU;
2489	AssertCompileMemberOffset(IEMCPU, cActiveMappings, 0x4f);
2490	AssertCompileMemberAlignment(IEMCPU, aMemMappings, 16);
2491	AssertCompileMemberAlignment(IEMCPU, aMemMappingLocks, 16);
2492	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 64);
2493	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
2494	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
2495
2496	/** Pointer to the per-CPU IEM state. */
2497	typedef IEMCPU *PIEMCPU;
2498	/** Pointer to the const per-CPU IEM state. */
2499	typedef IEMCPU const *PCIEMCPU;
2500
2501	/** @def IEMNATIVE_SIMD_FP_CTRL_REG_NOT_MODIFIED
2502	* Value indicating the TB didn't modified the floating point control register.
2503	* @note Neither FPCR nor MXCSR accept this as a valid value (MXCSR is not fully populated,
2504	* FPCR has the upper 32-bit reserved), so this is safe. */
2505	#if defined(IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS) \|\| defined(DOXYGEN_RUNNING)
2506	# ifdef RT_ARCH_AMD64
2507	# define IEMNATIVE_SIMD_FP_CTRL_REG_NOT_MODIFIED UINT32_MAX
2508	# elif defined(RT_ARCH_ARM64)
2509	# define IEMNATIVE_SIMD_FP_CTRL_REG_NOT_MODIFIED UINT64_MAX
2510	# else
2511	# error "Port me"
2512	# endif
2513	#endif
2514
2515	/** @def IEM_GET_CTX
2516	* Gets the guest CPU context for the calling EMT.
2517	* @returns PCPUMCTX
2518	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2519	*/
2520	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
2521
2522	/** @def IEM_CTX_ASSERT
2523	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
2524	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2525	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
2526	*/
2527	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) \
2528	AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
2529	("fExtrn=%#RX64 & fExtrnMbz=%#RX64 -> %#RX64\n", \
2530	(a_pVCpu)->cpum.GstCtx.fExtrn, (a_fExtrnMbz), (a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz) ))
2531
2532	/** @def IEM_CTX_IMPORT_RET
2533	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2534	*
2535	* Will call the keep to import the bits as needed.
2536	*
2537	* Returns on import failure.
2538	*
2539	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2540	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2541	*/
2542	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
2543	do { \
2544	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2545	{ /* likely */ } \
2546	else \
2547	{ \
2548	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2549	AssertRCReturn(rcCtxImport, rcCtxImport); \
2550	} \
2551	} while (0)
2552
2553	/** @def IEM_CTX_IMPORT_NORET
2554	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2555	*
2556	* Will call the keep to import the bits as needed.
2557	*
2558	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2559	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2560	*/
2561	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
2562	do { \
2563	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2564	{ /* likely */ } \
2565	else \
2566	{ \
2567	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2568	AssertLogRelRC(rcCtxImport); \
2569	} \
2570	} while (0)
2571
2572	/** @def IEM_CTX_IMPORT_JMP
2573	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2574	*
2575	* Will call the keep to import the bits as needed.
2576	*
2577	* Jumps on import failure.
2578	*
2579	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2580	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2581	*/
2582	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
2583	do { \
2584	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2585	{ /* likely */ } \
2586	else \
2587	{ \
2588	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2589	AssertRCStmt(rcCtxImport, IEM_DO_LONGJMP(pVCpu, rcCtxImport)); \
2590	} \
2591	} while (0)
2592
2593
2594
2595	/** @def IEM_GET_TARGET_CPU
2596	* Gets the current IEMTARGETCPU value.
2597	* @returns IEMTARGETCPU value.
2598	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2599	*/
2600	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
2601	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
2602	#else
2603	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
2604	#endif
2605
2606	/** @def IEM_GET_INSTR_LEN
2607	* Gets the instruction length. */
2608	#ifdef IEM_WITH_CODE_TLB
2609	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
2610	#else
2611	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
2612	#endif
2613
2614	/** @def IEM_TRY_SETJMP
2615	* Wrapper around setjmp / try, hiding all the ugly differences.
2616	*
2617	* @note Use with extreme care as this is a fragile macro.
2618	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2619	* @param a_rcTarget The variable that should receive the status code in case
2620	* of a longjmp/throw.
2621	*/
2622	/** @def IEM_TRY_SETJMP_AGAIN
2623	* For when setjmp / try is used again in the same variable scope as a previous
2624	* IEM_TRY_SETJMP invocation.
2625	*/
2626	/** @def IEM_CATCH_LONGJMP_BEGIN
2627	* Start wrapper for catch / setjmp-else.
2628	*
2629	* This will set up a scope.
2630	*
2631	* @note Use with extreme care as this is a fragile macro.
2632	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2633	* @param a_rcTarget The variable that should receive the status code in case
2634	* of a longjmp/throw.
2635	*/
2636	/** @def IEM_CATCH_LONGJMP_END
2637	* End wrapper for catch / setjmp-else.
2638	*
2639	* This will close the scope set up by IEM_CATCH_LONGJMP_BEGIN and clean up the
2640	* state.
2641	*
2642	* @note Use with extreme care as this is a fragile macro.
2643	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2644	*/
2645	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
2646	# ifdef IEM_WITH_THROW_CATCH
2647	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
2648	a_rcTarget = VINF_SUCCESS; \
2649	try
2650	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
2651	IEM_TRY_SETJMP(a_pVCpu, a_rcTarget)
2652	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
2653	catch (int rcThrown) \
2654	{ \
2655	a_rcTarget = rcThrown
2656	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
2657	} \
2658	((void)0)
2659	# else /* !IEM_WITH_THROW_CATCH */
2660	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
2661	jmp_buf JmpBuf; \
2662	jmp_buf * volatile pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
2663	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
2664	if ((rcStrict = setjmp(JmpBuf)) == 0)
2665	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
2666	pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
2667	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
2668	if ((rcStrict = setjmp(JmpBuf)) == 0)
2669	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
2670	else \
2671	{ \
2672	((void)0)
2673	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
2674	} \
2675	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = pSavedJmpBuf
2676	# endif /* !IEM_WITH_THROW_CATCH */
2677	#endif /* IEM_WITH_SETJMP */
2678
2679
2680	/**
2681	* Shared per-VM IEM data.
2682	*/
2683	typedef struct IEM
2684	{
2685	/** The VMX APIC-access page handler type. */
2686	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
2687	#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
2688	/** Set if the CPUID host call functionality is enabled. */
2689	bool fCpuIdHostCall;
2690	#endif
2691	} IEM;
2692
2693
2694
2695	/** @name IEM_ACCESS_XXX - Access details.
2696	* @{ */
2697	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
2698	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
2699	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
2700	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
2701	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
2702	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
2703	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
2704	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
2705	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
2706	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
2707	/** The writes are partial, so if initialize the bounce buffer with the
2708	* orignal RAM content. */
2709	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
2710	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
2711	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
2712	/** Bounce buffer with ring-3 write pending, first page. */
2713	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
2714	/** Bounce buffer with ring-3 write pending, second page. */
2715	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
2716	/** Not locked, accessed via the TLB. */
2717	#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
2718	/** Atomic access.
2719	* This enables special alignment checks and the VINF_EM_EMULATE_SPLIT_LOCK
2720	* fallback for misaligned stuff. See @bugref{10547}. */
2721	#define IEM_ACCESS_ATOMIC UINT32_C(0x00002000)
2722	/** Valid bit mask. */
2723	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00003fff)
2724	/** Shift count for the TLB flags (upper word). */
2725	#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
2726
2727	/** Atomic read+write data alias. */
2728	#define IEM_ACCESS_DATA_ATOMIC (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA \| IEM_ACCESS_ATOMIC)
2729	/** Read+write data alias. */
2730	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
2731	/** Write data alias. */
2732	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
2733	/** Read data alias. */
2734	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
2735	/** Instruction fetch alias. */
2736	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
2737	/** Stack write alias. */
2738	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
2739	/** Stack read alias. */
2740	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
2741	/** Stack read+write alias. */
2742	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
2743	/** Read system table alias. */
2744	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
2745	/** Read+write system table alias. */
2746	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
2747	/** @} */
2748
2749	/** @name Prefix constants (IEMCPU::fPrefixes)
2750	* @{ */
2751	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
2752	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
2753	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
2754	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
2755	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
2756	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
2757	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
2758
2759	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
2760	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
2761	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
2762
2763	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
2764	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
2765	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
2766
2767	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
2768	#define IEM_OP_PRF_REX_B RT_BIT_32(25) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
2769	#define IEM_OP_PRF_REX_X RT_BIT_32(26) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
2770	#define IEM_OP_PRF_REX_R RT_BIT_32(27) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
2771	/** Mask with all the REX prefix flags.
2772	* This is generally for use when needing to undo the REX prefixes when they
2773	* are followed legacy prefixes and therefore does not immediately preceed
2774	* the first opcode byte.
2775	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
2776	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
2777
2778	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
2779	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
2780	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
2781	/** @} */
2782
2783	/** @name IEMOPFORM_XXX - Opcode forms
2784	* @note These are ORed together with IEMOPHINT_XXX.
2785	* @{ */
2786	/** ModR/M: reg, r/m */
2787	#define IEMOPFORM_RM 0
2788	/** ModR/M: reg, r/m (register) */
2789	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
2790	/** ModR/M: reg, r/m (memory) */
2791	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
2792	/** ModR/M: reg, r/m, imm */
2793	#define IEMOPFORM_RMI 1
2794	/** ModR/M: reg, r/m (register), imm */
2795	#define IEMOPFORM_RMI_REG (IEMOPFORM_RMI \| IEMOPFORM_MOD3)
2796	/** ModR/M: reg, r/m (memory), imm */
2797	#define IEMOPFORM_RMI_MEM (IEMOPFORM_RMI \| IEMOPFORM_NOT_MOD3)
2798	/** ModR/M: reg, r/m, xmm0 */
2799	#define IEMOPFORM_RM0 2
2800	/** ModR/M: reg, r/m (register), xmm0 */
2801	#define IEMOPFORM_RM0_REG (IEMOPFORM_RM0 \| IEMOPFORM_MOD3)
2802	/** ModR/M: reg, r/m (memory), xmm0 */
2803	#define IEMOPFORM_RM0_MEM (IEMOPFORM_RM0 \| IEMOPFORM_NOT_MOD3)
2804	/** ModR/M: r/m, reg */
2805	#define IEMOPFORM_MR 3
2806	/** ModR/M: r/m (register), reg */
2807	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
2808	/** ModR/M: r/m (memory), reg */
2809	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
2810	/** ModR/M: r/m, reg, imm */
2811	#define IEMOPFORM_MRI 4
2812	/** ModR/M: r/m (register), reg, imm */
2813	#define IEMOPFORM_MRI_REG (IEMOPFORM_MRI \| IEMOPFORM_MOD3)
2814	/** ModR/M: r/m (memory), reg, imm */
2815	#define IEMOPFORM_MRI_MEM (IEMOPFORM_MRI \| IEMOPFORM_NOT_MOD3)
2816	/** ModR/M: r/m only */
2817	#define IEMOPFORM_M 5
2818	/** ModR/M: r/m only (register). */
2819	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
2820	/** ModR/M: r/m only (memory). */
2821	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
2822	/** ModR/M: r/m, imm */
2823	#define IEMOPFORM_MI 6
2824	/** ModR/M: r/m (register), imm */
2825	#define IEMOPFORM_MI_REG (IEMOPFORM_MI \| IEMOPFORM_MOD3)
2826	/** ModR/M: r/m (memory), imm */
2827	#define IEMOPFORM_MI_MEM (IEMOPFORM_MI \| IEMOPFORM_NOT_MOD3)
2828	/** ModR/M: r/m, 1 (shift and rotate instructions) */
2829	#define IEMOPFORM_M1 7
2830	/** ModR/M: r/m (register), 1. */
2831	#define IEMOPFORM_M1_REG (IEMOPFORM_M1 \| IEMOPFORM_MOD3)
2832	/** ModR/M: r/m (memory), 1. */
2833	#define IEMOPFORM_M1_MEM (IEMOPFORM_M1 \| IEMOPFORM_NOT_MOD3)
2834	/** ModR/M: r/m, CL (shift and rotate instructions)
2835	* @todo This should just've been a generic fixed register. But the python
2836	* code doesn't needs more convincing. */
2837	#define IEMOPFORM_M_CL 8
2838	/** ModR/M: r/m (register), CL. */
2839	#define IEMOPFORM_M_CL_REG (IEMOPFORM_M_CL \| IEMOPFORM_MOD3)
2840	/** ModR/M: r/m (memory), CL. */
2841	#define IEMOPFORM_M_CL_MEM (IEMOPFORM_M_CL \| IEMOPFORM_NOT_MOD3)
2842	/** ModR/M: reg only */
2843	#define IEMOPFORM_R 9
2844
2845	/** VEX+ModR/M: reg, r/m */
2846	#define IEMOPFORM_VEX_RM 16
2847	/** VEX+ModR/M: reg, r/m (register) */
2848	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
2849	/** VEX+ModR/M: reg, r/m (memory) */
2850	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
2851	/** VEX+ModR/M: r/m, reg */
2852	#define IEMOPFORM_VEX_MR 17
2853	/** VEX+ModR/M: r/m (register), reg */
2854	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
2855	/** VEX+ModR/M: r/m (memory), reg */
2856	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
2857	/** VEX+ModR/M: r/m, reg, imm8 */
2858	#define IEMOPFORM_VEX_MRI 18
2859	/** VEX+ModR/M: r/m (register), reg, imm8 */
2860	#define IEMOPFORM_VEX_MRI_REG (IEMOPFORM_VEX_MRI \| IEMOPFORM_MOD3)
2861	/** VEX+ModR/M: r/m (memory), reg, imm8 */
2862	#define IEMOPFORM_VEX_MRI_MEM (IEMOPFORM_VEX_MRI \| IEMOPFORM_NOT_MOD3)
2863	/** VEX+ModR/M: r/m only */
2864	#define IEMOPFORM_VEX_M 19
2865	/** VEX+ModR/M: r/m only (register). */
2866	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
2867	/** VEX+ModR/M: r/m only (memory). */
2868	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
2869	/** VEX+ModR/M: reg only */
2870	#define IEMOPFORM_VEX_R 20
2871	/** VEX+ModR/M: reg, vvvv, r/m */
2872	#define IEMOPFORM_VEX_RVM 21
2873	/** VEX+ModR/M: reg, vvvv, r/m (register). */
2874	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
2875	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
2876	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
2877	/** VEX+ModR/M: reg, vvvv, r/m, imm */
2878	#define IEMOPFORM_VEX_RVMI 22
2879	/** VEX+ModR/M: reg, vvvv, r/m (register), imm. */
2880	#define IEMOPFORM_VEX_RVMI_REG (IEMOPFORM_VEX_RVMI \| IEMOPFORM_MOD3)
2881	/** VEX+ModR/M: reg, vvvv, r/m (memory), imm. */
2882	#define IEMOPFORM_VEX_RVMI_MEM (IEMOPFORM_VEX_RVMI \| IEMOPFORM_NOT_MOD3)
2883	/** VEX+ModR/M: reg, vvvv, r/m, imm(reg) */
2884	#define IEMOPFORM_VEX_RVMR 23
2885	/** VEX+ModR/M: reg, vvvv, r/m (register), imm(reg). */
2886	#define IEMOPFORM_VEX_RVMR_REG (IEMOPFORM_VEX_RVMI \| IEMOPFORM_MOD3)
2887	/** VEX+ModR/M: reg, vvvv, r/m (memory), imm(reg). */
2888	#define IEMOPFORM_VEX_RVMR_MEM (IEMOPFORM_VEX_RVMI \| IEMOPFORM_NOT_MOD3)
2889	/** VEX+ModR/M: reg, r/m, vvvv */
2890	#define IEMOPFORM_VEX_RMV 24
2891	/** VEX+ModR/M: reg, r/m, vvvv (register). */
2892	#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV \| IEMOPFORM_MOD3)
2893	/** VEX+ModR/M: reg, r/m, vvvv (memory). */
2894	#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV \| IEMOPFORM_NOT_MOD3)
2895	/** VEX+ModR/M: reg, r/m, imm8 */
2896	#define IEMOPFORM_VEX_RMI 25
2897	/** VEX+ModR/M: reg, r/m, imm8 (register). */
2898	#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI \| IEMOPFORM_MOD3)
2899	/** VEX+ModR/M: reg, r/m, imm8 (memory). */
2900	#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI \| IEMOPFORM_NOT_MOD3)
2901	/** VEX+ModR/M: r/m, vvvv, reg */
2902	#define IEMOPFORM_VEX_MVR 26
2903	/** VEX+ModR/M: r/m, vvvv, reg (register) */
2904	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
2905	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
2906	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
2907	/** VEX+ModR/M+/n: vvvv, r/m */
2908	#define IEMOPFORM_VEX_VM 27
2909	/** VEX+ModR/M+/n: vvvv, r/m (register) */
2910	#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM \| IEMOPFORM_MOD3)
2911	/** VEX+ModR/M+/n: vvvv, r/m (memory) */
2912	#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM \| IEMOPFORM_NOT_MOD3)
2913	/** VEX+ModR/M+/n: vvvv, r/m, imm8 */
2914	#define IEMOPFORM_VEX_VMI 28
2915	/** VEX+ModR/M+/n: vvvv, r/m, imm8 (register) */
2916	#define IEMOPFORM_VEX_VMI_REG (IEMOPFORM_VEX_VMI \| IEMOPFORM_MOD3)
2917	/** VEX+ModR/M+/n: vvvv, r/m, imm8 (memory) */
2918	#define IEMOPFORM_VEX_VMI_MEM (IEMOPFORM_VEX_VMI \| IEMOPFORM_NOT_MOD3)
2919
2920	/** Fixed register instruction, no R/M. */
2921	#define IEMOPFORM_FIXED 32
2922
2923	/** The r/m is a register. */
2924	#define IEMOPFORM_MOD3 RT_BIT_32(8)
2925	/** The r/m is a memory access. */
2926	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
2927	/** @} */
2928
2929	/** @name IEMOPHINT_XXX - Additional Opcode Hints
2930	* @note These are ORed together with IEMOPFORM_XXX.
2931	* @{ */
2932	/** Ignores the operand size prefix (66h). */
2933	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
2934	/** Ignores REX.W (aka WIG). */
2935	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
2936	/** Both the operand size prefixes (66h + REX.W) are ignored. */
2937	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
2938	/** Allowed with the lock prefix. */
2939	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
2940	/** The VEX.L value is ignored (aka LIG). */
2941	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
2942	/** The VEX.L value must be zero (i.e. 128-bit width only). */
2943	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
2944	/** The VEX.L value must be one (i.e. 256-bit width only). */
2945	#define IEMOPHINT_VEX_L_ONE RT_BIT_32(14)
2946	/** The VEX.V value must be zero. */
2947	#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(15)
2948	/** The REX.W/VEX.V value must be zero. */
2949	#define IEMOPHINT_REX_W_ZERO RT_BIT_32(16)
2950	#define IEMOPHINT_VEX_W_ZERO IEMOPHINT_REX_W_ZERO
2951	/** The REX.W/VEX.V value must be one. */
2952	#define IEMOPHINT_REX_W_ONE RT_BIT_32(17)
2953	#define IEMOPHINT_VEX_W_ONE IEMOPHINT_REX_W_ONE
2954
2955	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
2956	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
2957	/** @} */
2958
2959	/**
2960	* Possible hardware task switch sources.
2961	*/
2962	typedef enum IEMTASKSWITCH
2963	{
2964	/** Task switch caused by an interrupt/exception. */
2965	IEMTASKSWITCH_INT_XCPT = 1,
2966	/** Task switch caused by a far CALL. */
2967	IEMTASKSWITCH_CALL,
2968	/** Task switch caused by a far JMP. */
2969	IEMTASKSWITCH_JUMP,
2970	/** Task switch caused by an IRET. */
2971	IEMTASKSWITCH_IRET
2972	} IEMTASKSWITCH;
2973	AssertCompileSize(IEMTASKSWITCH, 4);
2974
2975	/**
2976	* Possible CrX load (write) sources.
2977	*/
2978	typedef enum IEMACCESSCRX
2979	{
2980	/** CrX access caused by 'mov crX' instruction. */
2981	IEMACCESSCRX_MOV_CRX,
2982	/** CrX (CR0) write caused by 'lmsw' instruction. */
2983	IEMACCESSCRX_LMSW,
2984	/** CrX (CR0) write caused by 'clts' instruction. */
2985	IEMACCESSCRX_CLTS,
2986	/** CrX (CR0) read caused by 'smsw' instruction. */
2987	IEMACCESSCRX_SMSW
2988	} IEMACCESSCRX;
2989
2990	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2991	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
2992	*
2993	* These flags provide further context to SLAT page-walk failures that could not be
2994	* determined by PGM (e.g, PGM is not privy to memory access permissions).
2995	*
2996	* @{
2997	*/
2998	/** Translating a nested-guest linear address failed accessing a nested-guest
2999	* physical address. */
3000	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
3001	/** Translating a nested-guest linear address failed accessing a
3002	* paging-structure entry or updating accessed/dirty bits. */
3003	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
3004	/** @} */
3005
3006	DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
3007	# ifndef IN_RING3
3008	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
3009	# endif
3010	#endif
3011
3012	/**
3013	* Indicates to the verifier that the given flag set is undefined.
3014	*
3015	* Can be invoked again to add more flags.
3016	*
3017	* This is a NOOP if the verifier isn't compiled in.
3018	*
3019	* @note We're temporarily keeping this until code is converted to new
3020	* disassembler style opcode handling.
3021	*/
3022	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
3023
3024
3025	/** @def IEM_DECL_IMPL_TYPE
3026	* For typedef'ing an instruction implementation function.
3027	*
3028	* @param a_RetType The return type.
3029	* @param a_Name The name of the type.
3030	* @param a_ArgList The argument list enclosed in parentheses.
3031	*/
3032
3033	/** @def IEM_DECL_IMPL_DEF
3034	* For defining an instruction implementation function.
3035	*
3036	* @param a_RetType The return type.
3037	* @param a_Name The name of the type.
3038	* @param a_ArgList The argument list enclosed in parentheses.
3039	*/
3040
3041	#if defined(__GNUC__) && defined(RT_ARCH_X86)
3042	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
3043	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
3044	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
3045	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
3046	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
3047	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
3048
3049	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
3050	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
3051	a_RetType (__fastcall a_Name) a_ArgList
3052	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
3053	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
3054	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
3055	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
3056
3057	#elif __cplusplus >= 201700 /* P0012R1 support */
3058	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
3059	a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
3060	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
3061	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
3062	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
3063	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
3064
3065	#else
3066	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
3067	a_RetType (VBOXCALL a_Name) a_ArgList
3068	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
3069	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
3070	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
3071	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
3072
3073	#endif
3074
3075	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
3076	RT_C_DECLS_BEGIN
3077	extern uint8_t const g_afParity[256];
3078	RT_C_DECLS_END
3079
3080
3081	/** @name Arithmetic assignment operations on bytes (binary).
3082	* @{ */
3083	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU8, (uint32_t fEFlagsIn, uint8_t *pu8Dst, uint8_t u8Src));
3084	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
3085	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
3086	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
3087	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
3088	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
3089	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
3090	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
3091	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
3092	/** @} */
3093
3094	/** @name Arithmetic assignment operations on words (binary).
3095	* @{ */
3096	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU16, (uint32_t fEFlagsIn, uint16_t *pu16Dst, uint16_t u16Src));
3097	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
3098	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
3099	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
3100	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
3101	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
3102	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
3103	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
3104	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
3105	/** @} */
3106
3107
3108	/** @name Arithmetic assignment operations on double words (binary).
3109	* @{ */
3110	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU32, (uint32_t fEFlagsIn, uint32_t *pu32Dst, uint32_t u32Src));
3111	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
3112	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
3113	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
3114	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
3115	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
3116	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
3117	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
3118	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
3119	FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
3120	FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
3121	FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
3122	/** @} */
3123
3124	/** @name Arithmetic assignment operations on quad words (binary).
3125	* @{ */
3126	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU64, (uint32_t fEFlagsIn, uint64_t *pu64Dst, uint64_t u64Src));
3127	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
3128	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
3129	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
3130	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
3131	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
3132	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
3133	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
3134	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
3135	FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
3136	FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
3137	FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
3138	/** @} */
3139
3140	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU8, (uint32_t fEFlagsIn, uint8_t const *pu8Dst, uint8_t u8Src));
3141	typedef FNIEMAIMPLBINROU8 *PFNIEMAIMPLBINROU8;
3142	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU16,(uint32_t fEFlagsIn, uint16_t const *pu16Dst, uint16_t u16Src));
3143	typedef FNIEMAIMPLBINROU16 *PFNIEMAIMPLBINROU16;
3144	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU32,(uint32_t fEFlagsIn, uint32_t const *pu32Dst, uint32_t u32Src));
3145	typedef FNIEMAIMPLBINROU32 *PFNIEMAIMPLBINROU32;
3146	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU64,(uint32_t fEFlagsIn, uint64_t const *pu64Dst, uint64_t u64Src));
3147	typedef FNIEMAIMPLBINROU64 *PFNIEMAIMPLBINROU64;
3148
3149	/** @name Compare operations (thrown in with the binary ops).
3150	* @{ */
3151	FNIEMAIMPLBINROU8 iemAImpl_cmp_u8;
3152	FNIEMAIMPLBINROU16 iemAImpl_cmp_u16;
3153	FNIEMAIMPLBINROU32 iemAImpl_cmp_u32;
3154	FNIEMAIMPLBINROU64 iemAImpl_cmp_u64;
3155	/** @} */
3156
3157	/** @name Test operations (thrown in with the binary ops).
3158	* @{ */
3159	FNIEMAIMPLBINROU8 iemAImpl_test_u8;
3160	FNIEMAIMPLBINROU16 iemAImpl_test_u16;
3161	FNIEMAIMPLBINROU32 iemAImpl_test_u32;
3162	FNIEMAIMPLBINROU64 iemAImpl_test_u64;
3163	/** @} */
3164
3165	/** @name Bit operations operations (thrown in with the binary ops).
3166	* @{ */
3167	FNIEMAIMPLBINROU16 iemAImpl_bt_u16;
3168	FNIEMAIMPLBINROU32 iemAImpl_bt_u32;
3169	FNIEMAIMPLBINROU64 iemAImpl_bt_u64;
3170	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
3171	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
3172	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
3173	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
3174	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
3175	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
3176	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
3177	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
3178	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
3179	/** @} */
3180
3181	/** @name Arithmetic three operand operations on double words (binary).
3182	* @{ */
3183	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t pEFlags));
3184	typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
3185	FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
3186	FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
3187	FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
3188	/** @} */
3189
3190	/** @name Arithmetic three operand operations on quad words (binary).
3191	* @{ */
3192	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t pEFlags));
3193	typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
3194	FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
3195	FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
3196	FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
3197	/** @} */
3198
3199	/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
3200	* @{ */
3201	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
3202	typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
3203	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
3204	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
3205	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
3206	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
3207	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
3208	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
3209	/** @} */
3210
3211	/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
3212	* @{ */
3213	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
3214	typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
3215	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
3216	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
3217	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
3218	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
3219	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
3220	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
3221	/** @} */
3222
3223	/** @name MULX 32-bit and 64-bit.
3224	* @{ */
3225	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t puDst1, uint32_t puDst2, uint32_t uSrc1, uint32_t uSrc2));
3226	typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
3227	FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
3228
3229	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t puDst1, uint64_t puDst2, uint64_t uSrc1, uint64_t uSrc2));
3230	typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
3231	FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
3232	/** @} */
3233
3234
3235	/** @name Exchange memory with register operations.
3236	* @{ */
3237	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
3238	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
3239	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
3240	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
3241	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
3242	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
3243	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
3244	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
3245	/** @} */
3246
3247	/** @name Exchange and add operations.
3248	* @{ */
3249	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
3250	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
3251	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
3252	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
3253	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
3254	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
3255	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
3256	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
3257	/** @} */
3258
3259	/** @name Compare and exchange.
3260	* @{ */
3261	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
3262	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
3263	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
3264	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
3265	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
3266	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
3267	#if ARCH_BITS == 32
3268	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
3269	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
3270	#else
3271	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
3272	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
3273	#endif
3274	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
3275	uint32_t *pEFlags));
3276	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
3277	uint32_t *pEFlags));
3278	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
3279	uint32_t *pEFlags));
3280	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
3281	uint32_t *pEFlags));
3282	#ifndef RT_ARCH_ARM64
3283	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
3284	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
3285	#endif
3286	/** @} */
3287
3288	/** @name Memory ordering
3289	* @{ */
3290	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
3291	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
3292	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
3293	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
3294	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
3295	#ifndef RT_ARCH_ARM64
3296	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
3297	#endif
3298	/** @} */
3299
3300	/** @name Double precision shifts
3301	* @{ */
3302	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
3303	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
3304	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
3305	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
3306	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
3307	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
3308	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
3309	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
3310	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
3311	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
3312	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
3313	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
3314	/** @} */
3315
3316
3317	/** @name Bit search operations (thrown in with the binary ops).
3318	* @{ */
3319	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
3320	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
3321	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
3322	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
3323	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
3324	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
3325	FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
3326	FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
3327	FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
3328	FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
3329	FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
3330	FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
3331	FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
3332	FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
3333	FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
3334	/** @} */
3335
3336	/** @name Signed multiplication operations (thrown in with the binary ops).
3337	* @{ */
3338	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
3339	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
3340	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
3341	/** @} */
3342
3343	/** @name Arithmetic assignment operations on bytes (unary).
3344	* @{ */
3345	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
3346	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
3347	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
3348	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
3349	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
3350	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
3351	/** @} */
3352
3353	/** @name Arithmetic assignment operations on words (unary).
3354	* @{ */
3355	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
3356	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
3357	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
3358	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
3359	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
3360	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
3361	/** @} */
3362
3363	/** @name Arithmetic assignment operations on double words (unary).
3364	* @{ */
3365	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
3366	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
3367	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
3368	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
3369	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
3370	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
3371	/** @} */
3372
3373	/** @name Arithmetic assignment operations on quad words (unary).
3374	* @{ */
3375	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
3376	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
3377	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
3378	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
3379	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
3380	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
3381	/** @} */
3382
3383
3384	/** @name Shift operations on bytes (Group 2).
3385	* @{ */
3386	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU8,(uint32_t fEFlagsIn, uint8_t *pu8Dst, uint8_t cShift));
3387	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
3388	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
3389	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
3390	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
3391	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
3392	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
3393	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
3394	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
3395	/** @} */
3396
3397	/** @name Shift operations on words (Group 2).
3398	* @{ */
3399	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU16,(uint32_t fEFlagsIn, uint16_t *pu16Dst, uint8_t cShift));
3400	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
3401	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
3402	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
3403	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
3404	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
3405	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
3406	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
3407	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
3408	/** @} */
3409
3410	/** @name Shift operations on double words (Group 2).
3411	* @{ */
3412	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU32,(uint32_t fEFlagsIn, uint32_t *pu32Dst, uint8_t cShift));
3413	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
3414	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
3415	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
3416	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
3417	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
3418	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
3419	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
3420	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
3421	/** @} */
3422
3423	/** @name Shift operations on words (Group 2).
3424	* @{ */
3425	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU64,(uint32_t fEFlagsIn, uint64_t *pu64Dst, uint8_t cShift));
3426	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
3427	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
3428	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
3429	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
3430	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
3431	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
3432	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
3433	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
3434	/** @} */
3435
3436	/** @name Multiplication and division operations.
3437	* @{ */
3438	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
3439	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
3440	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
3441	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
3442	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
3443	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
3444
3445	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
3446	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
3447	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
3448	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
3449	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
3450	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
3451
3452	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
3453	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
3454	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
3455	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
3456	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
3457	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
3458
3459	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
3460	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
3461	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
3462	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
3463	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
3464	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
3465	/** @} */
3466
3467	/** @name Byte Swap.
3468	* @{ */
3469	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
3470	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
3471	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
3472	/** @} */
3473
3474	/** @name Misc.
3475	* @{ */
3476	FNIEMAIMPLBINU16 iemAImpl_arpl;
3477	/** @} */
3478
3479	/** @name RDRAND and RDSEED
3480	* @{ */
3481	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU16,(uint16_t puDst, uint32_t pEFlags));
3482	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU32,(uint32_t puDst, uint32_t pEFlags));
3483	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU64,(uint64_t puDst, uint32_t pEFlags));
3484	typedef FNIEMAIMPLRDRANDSEEDU16 *PFNIEMAIMPLRDRANDSEEDU16;
3485	typedef FNIEMAIMPLRDRANDSEEDU32 *PFNIEMAIMPLRDRANDSEEDU32;
3486	typedef FNIEMAIMPLRDRANDSEEDU64 *PFNIEMAIMPLRDRANDSEEDU64;
3487
3488	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdrand_u16, iemAImpl_rdrand_u16_fallback;
3489	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdrand_u32, iemAImpl_rdrand_u32_fallback;
3490	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdrand_u64, iemAImpl_rdrand_u64_fallback;
3491	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdseed_u16, iemAImpl_rdseed_u16_fallback;
3492	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdseed_u32, iemAImpl_rdseed_u32_fallback;
3493	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdseed_u64, iemAImpl_rdseed_u64_fallback;
3494	/** @} */
3495
3496	/** @name ADOX and ADCX
3497	* @{ */
3498	FNIEMAIMPLBINU32 iemAImpl_adcx_u32, iemAImpl_adcx_u32_fallback;
3499	FNIEMAIMPLBINU64 iemAImpl_adcx_u64, iemAImpl_adcx_u64_fallback;
3500	FNIEMAIMPLBINU32 iemAImpl_adox_u32, iemAImpl_adox_u32_fallback;
3501	FNIEMAIMPLBINU64 iemAImpl_adox_u64, iemAImpl_adox_u64_fallback;
3502	/** @} */
3503
3504	/** @name FPU operations taking a 32-bit float argument
3505	* @{ */
3506	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3507	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
3508	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
3509
3510	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3511	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
3512	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
3513
3514	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
3515	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
3516	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
3517	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
3518	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
3519	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
3520	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
3521
3522	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
3523	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3524	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
3525	/** @} */
3526
3527	/** @name FPU operations taking a 64-bit float argument
3528	* @{ */
3529	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3530	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
3531	typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
3532
3533	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3534	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
3535	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
3536
3537	FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
3538	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
3539	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
3540	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
3541	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
3542	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
3543	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
3544
3545	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
3546	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3547	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
3548	/** @} */
3549
3550	/** @name FPU operations taking a 80-bit float argument
3551	* @{ */
3552	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3553	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3554	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
3555	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
3556	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
3557	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
3558	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
3559	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
3560	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
3561	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
3562	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
3563	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
3564
3565	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
3566	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
3567	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
3568
3569	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3570	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3571	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
3572	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
3573	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
3574
3575	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
3576	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3577	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
3578	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
3579	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
3580
3581	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
3582	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
3583	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
3584	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
3585	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
3586	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
3587	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
3588	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
3589	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
3590
3591	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
3592	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
3593	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
3594	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
3595
3596	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
3597	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
3598	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
3599	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
3600	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
3601	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
3602	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
3603	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
3604	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
3605
3606	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
3607	PCRTFLOAT80U pr80Val));
3608	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
3609	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
3610	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
3611	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
3612
3613	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
3614	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3615	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
3616
3617	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
3618	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3619	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
3620
3621	/** @} */
3622
3623	/** @name FPU operations taking a 16-bit signed integer argument
3624	* @{ */
3625	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3626	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
3627	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
3628	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3629	int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
3630	typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
3631
3632	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
3633	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
3634	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
3635	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
3636	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
3637	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
3638
3639	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3640	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
3641	typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
3642	FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
3643
3644	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
3645	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
3646	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
3647	/** @} */
3648
3649	/** @name FPU operations taking a 32-bit signed integer argument
3650	* @{ */
3651	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3652	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
3653	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
3654	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3655	int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
3656	typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
3657
3658	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
3659	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
3660	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
3661	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
3662	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
3663	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
3664
3665	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3666	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
3667	typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
3668	FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
3669
3670	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
3671	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
3672	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
3673	/** @} */
3674
3675	/** @name FPU operations taking a 64-bit signed integer argument
3676	* @{ */
3677	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3678	int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
3679	typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
3680
3681	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
3682	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
3683	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
3684	/** @} */
3685
3686
3687	/** Temporary type representing a 256-bit vector register. */
3688	typedef struct { uint64_t au64[4]; } IEMVMM256;
3689	/** Temporary type pointing to a 256-bit vector register. */
3690	typedef IEMVMM256 *PIEMVMM256;
3691	/** Temporary type pointing to a const 256-bit vector register. */
3692	typedef IEMVMM256 *PCIEMVMM256;
3693
3694
3695	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
3696	* @{ */
3697	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t puDst, uint64_t const puSrc));
3698	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
3699	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF2U128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
3700	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
3701	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF2U256,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86YMMREG puSrc));
3702	typedef FNIEMAIMPLMEDIAF2U256 *PFNIEMAIMPLMEDIAF2U256;
3703	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF3U128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3704	typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
3705	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF3U256,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
3706	typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
3707	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t puDst, uint64_t const puSrc));
3708	typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
3709	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
3710	typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
3711	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
3712	typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
3713	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
3714	typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
3715	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256,(PRTUINT256U puDst, PCRTUINT256U puSrc));
3716	typedef FNIEMAIMPLMEDIAOPTF2U256 *PFNIEMAIMPLMEDIAOPTF2U256;
3717	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
3718	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
3719	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
3720	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
3721	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddb_u64, iemAImpl_paddsb_u64, iemAImpl_paddusb_u64;
3722	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddw_u64, iemAImpl_paddsw_u64, iemAImpl_paddusw_u64;
3723	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddd_u64;
3724	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddq_u64;
3725	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubb_u64, iemAImpl_psubsb_u64, iemAImpl_psubusb_u64;
3726	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubw_u64, iemAImpl_psubsw_u64, iemAImpl_psubusw_u64;
3727	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubd_u64;
3728	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubq_u64;
3729	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmaddwd_u64, iemAImpl_pmaddwd_u64_fallback;
3730	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmullw_u64, iemAImpl_pmulhw_u64;
3731	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pminub_u64, iemAImpl_pmaxub_u64;
3732	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pminsw_u64, iemAImpl_pmaxsw_u64;
3733	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsb_u64, iemAImpl_pabsb_u64_fallback;
3734	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsw_u64, iemAImpl_pabsw_u64_fallback;
3735	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsd_u64, iemAImpl_pabsd_u64_fallback;
3736	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignb_u64, iemAImpl_psignb_u64_fallback;
3737	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignw_u64, iemAImpl_psignw_u64_fallback;
3738	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignd_u64, iemAImpl_psignd_u64_fallback;
3739	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddw_u64, iemAImpl_phaddw_u64_fallback;
3740	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddd_u64, iemAImpl_phaddd_u64_fallback;
3741	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubw_u64, iemAImpl_phsubw_u64_fallback;
3742	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubd_u64, iemAImpl_phsubd_u64_fallback;
3743	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddsw_u64, iemAImpl_phaddsw_u64_fallback;
3744	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubsw_u64, iemAImpl_phsubsw_u64_fallback;
3745	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmaddubsw_u64, iemAImpl_pmaddubsw_u64_fallback;
3746	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhrsw_u64, iemAImpl_pmulhrsw_u64_fallback;
3747	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmuludq_u64;
3748	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllw_u64, iemAImpl_psrlw_u64, iemAImpl_psraw_u64;
3749	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pslld_u64, iemAImpl_psrld_u64, iemAImpl_psrad_u64;
3750	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllq_u64, iemAImpl_psrlq_u64;
3751	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packsswb_u64, iemAImpl_packuswb_u64;
3752	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packssdw_u64;
3753	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhuw_u64;
3754	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pavgb_u64, iemAImpl_pavgw_u64;
3755	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psadbw_u64;
3756
3757	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
3758	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
3759	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
3760	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
3761	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
3762	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
3763	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddb_u128, iemAImpl_paddsb_u128, iemAImpl_paddusb_u128;
3764	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddw_u128, iemAImpl_paddsw_u128, iemAImpl_paddusw_u128;
3765	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddd_u128;
3766	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddq_u128;
3767	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubb_u128, iemAImpl_psubsb_u128, iemAImpl_psubusb_u128;
3768	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubw_u128, iemAImpl_psubsw_u128, iemAImpl_psubusw_u128;
3769	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubd_u128;
3770	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubq_u128;
3771	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmullw_u128, iemAImpl_pmullw_u128_fallback;
3772	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhw_u128;
3773	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback;
3774	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddwd_u128, iemAImpl_pmaddwd_u128_fallback;
3775	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminub_u128;
3776	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback;
3777	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback;
3778	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback;
3779	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback;
3780	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsw_u128, iemAImpl_pminsw_u128_fallback;
3781	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxub_u128;
3782	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback;
3783	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback;
3784	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback;
3785	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsw_u128;
3786	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback;
3787	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback;
3788	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback;
3789	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback;
3790	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback;
3791	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback;
3792	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback;
3793	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback;
3794	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback;
3795	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback;
3796	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback;
3797	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback;
3798	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback;
3799	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback;
3800	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback;
3801	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuludq_u128;
3802	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddwd_u128, iemAImpl_pmaddwd_u128_fallback;
3803	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packsswb_u128, iemAImpl_packuswb_u128;
3804	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packssdw_u128, iemAImpl_packusdw_u128;
3805	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllw_u128, iemAImpl_psrlw_u128, iemAImpl_psraw_u128;
3806	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pslld_u128, iemAImpl_psrld_u128, iemAImpl_psrad_u128;
3807	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllq_u128, iemAImpl_psrlq_u128;
3808	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhuw_u128;
3809	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pavgb_u128, iemAImpl_pavgw_u128;
3810	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psadbw_u128;
3811	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback;
3812	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpcklps_u128, iemAImpl_unpcklpd_u128;
3813	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpckhps_u128, iemAImpl_unpckhpd_u128;
3814	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback;
3815
3816	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
3817	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
3818	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
3819	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
3820	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
3821	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
3822	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
3823	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
3824	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
3825	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
3826	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
3827	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
3828	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
3829	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
3830	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
3831	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
3832	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
3833	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
3834	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
3835	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
3836	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
3837	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminub_u128, iemAImpl_vpminub_u128_fallback;
3838	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminuw_u128, iemAImpl_vpminuw_u128_fallback;
3839	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminud_u128, iemAImpl_vpminud_u128_fallback;
3840	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsb_u128, iemAImpl_vpminsb_u128_fallback;
3841	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsw_u128, iemAImpl_vpminsw_u128_fallback;
3842	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsd_u128, iemAImpl_vpminsd_u128_fallback;
3843	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxub_u128, iemAImpl_vpmaxub_u128_fallback;
3844	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxuw_u128, iemAImpl_vpmaxuw_u128_fallback;
3845	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxud_u128, iemAImpl_vpmaxud_u128_fallback;
3846	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsb_u128, iemAImpl_vpmaxsb_u128_fallback;
3847	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsw_u128, iemAImpl_vpmaxsw_u128_fallback;
3848	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsd_u128, iemAImpl_vpmaxsd_u128_fallback;
3849	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpacksswb_u128, iemAImpl_vpacksswb_u128_fallback;
3850	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackssdw_u128, iemAImpl_vpackssdw_u128_fallback;
3851	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackuswb_u128, iemAImpl_vpackuswb_u128_fallback;
3852	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackusdw_u128, iemAImpl_vpackusdw_u128_fallback;
3853	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmullw_u128, iemAImpl_vpmullw_u128_fallback;
3854	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulld_u128, iemAImpl_vpmulld_u128_fallback;
3855	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhw_u128, iemAImpl_vpmulhw_u128_fallback;
3856	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhuw_u128, iemAImpl_vpmulhuw_u128_fallback;
3857	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgb_u128, iemAImpl_vpavgb_u128_fallback;
3858	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgw_u128, iemAImpl_vpavgw_u128_fallback;
3859	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignb_u128, iemAImpl_vpsignb_u128_fallback;
3860	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignw_u128, iemAImpl_vpsignw_u128_fallback;
3861	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignd_u128, iemAImpl_vpsignd_u128_fallback;
3862	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddw_u128, iemAImpl_vphaddw_u128_fallback;
3863	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddd_u128, iemAImpl_vphaddd_u128_fallback;
3864	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubw_u128, iemAImpl_vphsubw_u128_fallback;
3865	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubd_u128, iemAImpl_vphsubd_u128_fallback;
3866	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddsw_u128, iemAImpl_vphaddsw_u128_fallback;
3867	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubsw_u128, iemAImpl_vphsubsw_u128_fallback;
3868	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddubsw_u128, iemAImpl_vpmaddubsw_u128_fallback;
3869	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhrsw_u128, iemAImpl_vpmulhrsw_u128_fallback;
3870	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsadbw_u128, iemAImpl_vpsadbw_u128_fallback;
3871	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuldq_u128, iemAImpl_vpmuldq_u128_fallback;
3872	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuludq_u128, iemAImpl_vpmuludq_u128_fallback;
3873	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsb_u128, iemAImpl_vpsubsb_u128_fallback;
3874	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsw_u128, iemAImpl_vpsubsw_u128_fallback;
3875	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusb_u128, iemAImpl_vpsubusb_u128_fallback;
3876	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusw_u128, iemAImpl_vpsubusw_u128_fallback;
3877	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusb_u128, iemAImpl_vpaddusb_u128_fallback;
3878	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusw_u128, iemAImpl_vpaddusw_u128_fallback;
3879	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsb_u128, iemAImpl_vpaddsb_u128_fallback;
3880	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsw_u128, iemAImpl_vpaddsw_u128_fallback;
3881	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllw_u128, iemAImpl_vpsllw_u128_fallback;
3882	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpslld_u128, iemAImpl_vpslld_u128_fallback;
3883	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllq_u128, iemAImpl_vpsllq_u128_fallback;
3884	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsraw_u128, iemAImpl_vpsraw_u128_fallback;
3885	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrad_u128, iemAImpl_vpsrad_u128_fallback;
3886	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlw_u128, iemAImpl_vpsrlw_u128_fallback;
3887	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrld_u128, iemAImpl_vpsrld_u128_fallback;
3888	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlq_u128, iemAImpl_vpsrlq_u128_fallback;
3889	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddwd_u128, iemAImpl_vpmaddwd_u128_fallback;
3890
3891	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback;
3892	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsw_u128, iemAImpl_vpabsd_u128_fallback;
3893	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsd_u128, iemAImpl_vpabsw_u128_fallback;
3894	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback;
3895
3896	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
3897	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
3898	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
3899	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
3900	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
3901	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
3902	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
3903	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
3904	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
3905	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
3906	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
3907	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
3908	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
3909	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
3910	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
3911	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
3912	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
3913	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
3914	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
3915	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
3916	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
3917	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminub_u256, iemAImpl_vpminub_u256_fallback;
3918	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminuw_u256, iemAImpl_vpminuw_u256_fallback;
3919	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminud_u256, iemAImpl_vpminud_u256_fallback;
3920	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsb_u256, iemAImpl_vpminsb_u256_fallback;
3921	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsw_u256, iemAImpl_vpminsw_u256_fallback;
3922	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsd_u256, iemAImpl_vpminsd_u256_fallback;
3923	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxub_u256, iemAImpl_vpmaxub_u256_fallback;
3924	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxuw_u256, iemAImpl_vpmaxuw_u256_fallback;
3925	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxud_u256, iemAImpl_vpmaxud_u256_fallback;
3926	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsb_u256, iemAImpl_vpmaxsb_u256_fallback;
3927	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsw_u256, iemAImpl_vpmaxsw_u256_fallback;
3928	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsd_u256, iemAImpl_vpmaxsd_u256_fallback;
3929	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpacksswb_u256, iemAImpl_vpacksswb_u256_fallback;
3930	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackssdw_u256, iemAImpl_vpackssdw_u256_fallback;
3931	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackuswb_u256, iemAImpl_vpackuswb_u256_fallback;
3932	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackusdw_u256, iemAImpl_vpackusdw_u256_fallback;
3933	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmullw_u256, iemAImpl_vpmullw_u256_fallback;
3934	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulld_u256, iemAImpl_vpmulld_u256_fallback;
3935	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhw_u256, iemAImpl_vpmulhw_u256_fallback;
3936	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhuw_u256, iemAImpl_vpmulhuw_u256_fallback;
3937	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgb_u256, iemAImpl_vpavgb_u256_fallback;
3938	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgw_u256, iemAImpl_vpavgw_u256_fallback;
3939	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignb_u256, iemAImpl_vpsignb_u256_fallback;
3940	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignw_u256, iemAImpl_vpsignw_u256_fallback;
3941	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignd_u256, iemAImpl_vpsignd_u256_fallback;
3942	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddw_u256, iemAImpl_vphaddw_u256_fallback;
3943	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddd_u256, iemAImpl_vphaddd_u256_fallback;
3944	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubw_u256, iemAImpl_vphsubw_u256_fallback;
3945	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubd_u256, iemAImpl_vphsubd_u256_fallback;
3946	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddsw_u256, iemAImpl_vphaddsw_u256_fallback;
3947	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubsw_u256, iemAImpl_vphsubsw_u256_fallback;
3948	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddubsw_u256, iemAImpl_vpmaddubsw_u256_fallback;
3949	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhrsw_u256, iemAImpl_vpmulhrsw_u256_fallback;
3950	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsadbw_u256, iemAImpl_vpsadbw_u256_fallback;
3951	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuldq_u256, iemAImpl_vpmuldq_u256_fallback;
3952	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuludq_u256, iemAImpl_vpmuludq_u256_fallback;
3953	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsb_u256, iemAImpl_vpsubsb_u256_fallback;
3954	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsw_u256, iemAImpl_vpsubsw_u256_fallback;
3955	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusb_u256, iemAImpl_vpsubusb_u256_fallback;
3956	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusw_u256, iemAImpl_vpsubusw_u256_fallback;
3957	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusb_u256, iemAImpl_vpaddusb_u256_fallback;
3958	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusw_u256, iemAImpl_vpaddusw_u256_fallback;
3959	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsb_u256, iemAImpl_vpaddsb_u256_fallback;
3960	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsw_u256, iemAImpl_vpaddsw_u256_fallback;
3961	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllw_u256, iemAImpl_vpsllw_u256_fallback;
3962	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpslld_u256, iemAImpl_vpslld_u256_fallback;
3963	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllq_u256, iemAImpl_vpsllq_u256_fallback;
3964	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsraw_u256, iemAImpl_vpsraw_u256_fallback;
3965	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrad_u256, iemAImpl_vpsrad_u256_fallback;
3966	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlw_u256, iemAImpl_vpsrlw_u256_fallback;
3967	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrld_u256, iemAImpl_vpsrld_u256_fallback;
3968	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlq_u256, iemAImpl_vpsrlq_u256_fallback;
3969	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddwd_u256, iemAImpl_vpmaddwd_u256_fallback;
3970	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermps_u256, iemAImpl_vpermps_u256_fallback;
3971	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermd_u256, iemAImpl_vpermd_u256_fallback;
3972
3973	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback;
3974	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsw_u256, iemAImpl_vpabsw_u256_fallback;
3975	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsd_u256, iemAImpl_vpabsd_u256_fallback;
3976	/** @} */
3977
3978	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
3979	* @{ */
3980	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
3981	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
3982	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
3983	iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
3984	iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
3985	iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback,
3986	iemAImpl_vunpcklps_u128, iemAImpl_vunpcklps_u128_fallback,
3987	iemAImpl_vunpcklpd_u128, iemAImpl_vunpcklpd_u128_fallback,
3988	iemAImpl_vunpckhps_u128, iemAImpl_vunpckhps_u128_fallback,
3989	iemAImpl_vunpckhpd_u128, iemAImpl_vunpckhpd_u128_fallback;
3990
3991	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
3992	iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
3993	iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
3994	iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback,
3995	iemAImpl_vunpcklps_u256, iemAImpl_vunpcklps_u256_fallback,
3996	iemAImpl_vunpcklpd_u256, iemAImpl_vunpcklpd_u256_fallback,
3997	iemAImpl_vunpckhps_u256, iemAImpl_vunpckhps_u256_fallback,
3998	iemAImpl_vunpckhpd_u256, iemAImpl_vunpckhpd_u256_fallback;
3999	/** @} */
4000
4001	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
4002	* @{ */
4003	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
4004	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
4005	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
4006	iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
4007	iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
4008	iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
4009	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
4010	iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
4011	iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
4012	iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
4013	/** @} */
4014
4015	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
4016	* @{ */
4017	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
4018	typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
4019	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
4020	typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
4021	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t puDst, uint64_t const puSrc, uint8_t bEvil));
4022	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
4023	#ifndef IEM_WITHOUT_ASSEMBLY
4024	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
4025	#endif
4026	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
4027	/** @} */
4028
4029	/** @name Media (SSE/MMX/AVX) operation: Shift Immediate Stuff (evil)
4030	* @{ */
4031	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU64,(uint64_t *puDst, uint8_t bShift));
4032	typedef FNIEMAIMPLMEDIAPSHIFTU64 *PFNIEMAIMPLMEDIAPSHIFTU64;
4033	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU128,(PRTUINT128U puDst, uint8_t bShift));
4034	typedef FNIEMAIMPLMEDIAPSHIFTU128 *PFNIEMAIMPLMEDIAPSHIFTU128;
4035	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU256,(PRTUINT256U puDst, uint8_t bShift));
4036	typedef FNIEMAIMPLMEDIAPSHIFTU256 *PFNIEMAIMPLMEDIAPSHIFTU256;
4037	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psllw_imm_u64, iemAImpl_pslld_imm_u64, iemAImpl_psllq_imm_u64;
4038	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psrlw_imm_u64, iemAImpl_psrld_imm_u64, iemAImpl_psrlq_imm_u64;
4039	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psraw_imm_u64, iemAImpl_psrad_imm_u64;
4040	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psllw_imm_u128, iemAImpl_pslld_imm_u128, iemAImpl_psllq_imm_u128;
4041	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psrlw_imm_u128, iemAImpl_psrld_imm_u128, iemAImpl_psrlq_imm_u128;
4042	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psraw_imm_u128, iemAImpl_psrad_imm_u128;
4043	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_pslldq_imm_u128, iemAImpl_psrldq_imm_u128;
4044	/** @} */
4045
4046	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
4047	* @{ */
4048	IEM_DECL_IMPL_DEF(void, iemAImpl_maskmovq_u64,(uint64_t puMem, uint64_t const puSrc, uint64_t const *puMsk));
4049	IEM_DECL_IMPL_DEF(void, iemAImpl_maskmovdqu_u128,(PRTUINT128U puMem, PCRTUINT128U puSrc, PCRTUINT128U puMsk));
4050	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t pu64Dst, uint64_t const puSrc));
4051	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
4052	#ifndef IEM_WITHOUT_ASSEMBLY
4053	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
4054	#endif
4055	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
4056	/** @} */
4057
4058	/** @name Media (SSE/MMX/AVX) operations: Variable Blend Packed Bytes/R32/R64.
4059	* @{ */
4060	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puMask));
4061	typedef FNIEMAIMPLBLENDU128 *PFNIEMAIMPLBLENDU128;
4062	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, PCRTUINT128U puMask));
4063	typedef FNIEMAIMPLAVXBLENDU128 *PFNIEMAIMPLAVXBLENDU128;
4064	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, PCRTUINT256U puMask));
4065	typedef FNIEMAIMPLAVXBLENDU256 *PFNIEMAIMPLAVXBLENDU256;
4066
4067	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128;
4068	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128_fallback;
4069	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128;
4070	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128_fallback;
4071	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256;
4072	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256_fallback;
4073
4074	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128;
4075	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128_fallback;
4076	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128;
4077	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128_fallback;
4078	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256;
4079	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256_fallback;
4080
4081	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128;
4082	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128_fallback;
4083	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128;
4084	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128_fallback;
4085	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256;
4086	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256_fallback;
4087	/** @} */
4088
4089
4090	/** @name Media (SSE/MMX/AVX) operation: Sort this later
4091	* @{ */
4092	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
4093	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
4094	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4095	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4096	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4097
4098	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
4099	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
4100	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
4101	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4102	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4103
4104	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
4105	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
4106	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
4107	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4108	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4109
4110	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
4111	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
4112	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4113	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4114	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4115
4116	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
4117	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
4118	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
4119	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4120	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4121
4122	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
4123	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
4124	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4125	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4126	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4127
4128	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
4129	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
4130	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4131	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4132	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4133
4134	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
4135	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
4136	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
4137	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4138	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4139
4140	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
4141	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
4142	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
4143	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4144	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4145
4146	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
4147	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
4148	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4149	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4150	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4151
4152	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
4153	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
4154	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
4155	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4156	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4157
4158	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
4159	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
4160	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4161	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4162	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4163
4164	IEM_DECL_IMPL_DEF(void, iemAImpl_shufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
4165	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
4166	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
4167	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
4168	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
4169
4170	IEM_DECL_IMPL_DEF(void, iemAImpl_shufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
4171	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
4172	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
4173	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
4174	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
4175
4176	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
4177	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64_fallback,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
4178
4179	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4180	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4181	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4182	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
4183	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
4184
4185	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4186	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4187	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4188	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
4189	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
4190
4191
4192	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
4193	typedef FNIEMAIMPLMEDIAOPTF2U128IMM8 *PFNIEMAIMPLMEDIAOPTF2U128IMM8;
4194	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
4195	typedef FNIEMAIMPLMEDIAOPTF2U256IMM8 *PFNIEMAIMPLMEDIAOPTF2U256IMM8;
4196	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
4197	typedef FNIEMAIMPLMEDIAOPTF3U128IMM8 *PFNIEMAIMPLMEDIAOPTF3U128IMM8;
4198	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
4199	typedef FNIEMAIMPLMEDIAOPTF3U256IMM8 *PFNIEMAIMPLMEDIAOPTF3U256IMM8;
4200
4201	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback;
4202	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback;
4203	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback;
4204	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback;
4205
4206	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpalignr_u128, iemAImpl_vpalignr_u128_fallback;
4207	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendw_u128, iemAImpl_vpblendw_u128_fallback;
4208	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendd_u128, iemAImpl_vpblendd_u128_fallback;
4209	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendps_u128, iemAImpl_vblendps_u128_fallback;
4210	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendpd_u128, iemAImpl_vblendpd_u128_fallback;
4211
4212	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpalignr_u256, iemAImpl_vpalignr_u256_fallback;
4213	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendw_u256, iemAImpl_vpblendw_u256_fallback;
4214	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendd_u256, iemAImpl_vpblendd_u256_fallback;
4215	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendps_u256, iemAImpl_vblendps_u256_fallback;
4216	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendpd_u256, iemAImpl_vblendpd_u256_fallback;
4217	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2i128_u256, iemAImpl_vperm2i128_u256_fallback;
4218	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2f128_u256, iemAImpl_vperm2f128_u256_fallback;
4219
4220	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesimc_u128, iemAImpl_aesimc_u128_fallback;
4221	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenc_u128, iemAImpl_aesenc_u128_fallback;
4222	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenclast_u128, iemAImpl_aesenclast_u128_fallback;
4223	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdec_u128, iemAImpl_aesdec_u128_fallback;
4224	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdeclast_u128, iemAImpl_aesdeclast_u128_fallback;
4225
4226	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesimc_u128, iemAImpl_vaesimc_u128_fallback;
4227	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vaesenc_u128, iemAImpl_vaesenc_u128_fallback;
4228	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vaesenclast_u128, iemAImpl_vaesenclast_u128_fallback;
4229	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vaesdec_u128, iemAImpl_vaesdec_u128_fallback;
4230	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vaesdeclast_u128, iemAImpl_vaesdeclast_u128_fallback;
4231
4232	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback;
4233
4234	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vaeskeygenassist_u128, iemAImpl_vaeskeygenassist_u128_fallback;
4235
4236	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1nexte_u128, iemAImpl_sha1nexte_u128_fallback;
4237	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg1_u128, iemAImpl_sha1msg1_u128_fallback;
4238	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg2_u128, iemAImpl_sha1msg2_u128_fallback;
4239	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg1_u128, iemAImpl_sha256msg1_u128_fallback;
4240	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg2_u128, iemAImpl_sha256msg2_u128_fallback;
4241	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_sha1rnds4_u128, iemAImpl_sha1rnds4_u128_fallback;
4242	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
4243	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
4244
4245	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermq_u256, iemAImpl_vpermq_u256_fallback;
4246	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermpd_u256, iemAImpl_vpermpd_u256_fallback;
4247
4248	typedef struct IEMPCMPISTRXSRC
4249	{
4250	RTUINT128U uSrc1;
4251	RTUINT128U uSrc2;
4252	} IEMPCMPISTRXSRC;
4253	typedef IEMPCMPISTRXSRC *PIEMPCMPISTRXSRC;
4254	typedef const IEMPCMPISTRXSRC *PCIEMPCMPISTRXSRC;
4255
4256	typedef struct IEMPCMPESTRXSRC
4257	{
4258	RTUINT128U uSrc1;
4259	RTUINT128U uSrc2;
4260	uint64_t u64Rax;
4261	uint64_t u64Rdx;
4262	} IEMPCMPESTRXSRC;
4263	typedef IEMPCMPESTRXSRC *PIEMPCMPESTRXSRC;
4264	typedef const IEMPCMPESTRXSRC *PCIEMPCMPESTRXSRC;
4265
4266	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLPCMPISTRIU128IMM8,(uint32_t *pEFlags, PCRTUINT128U pSrc1, PCRTUINT128U pSrc2, uint8_t bEvil));
4267	typedef FNIEMAIMPLPCMPISTRIU128IMM8 *PFNIEMAIMPLPCMPISTRIU128IMM8;
4268	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
4269	typedef FNIEMAIMPLPCMPESTRIU128IMM8 *PFNIEMAIMPLPCMPESTRIU128IMM8;
4270
4271	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
4272	typedef FNIEMAIMPLPCMPISTRMU128IMM8 *PFNIEMAIMPLPCMPISTRMU128IMM8;
4273	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
4274	typedef FNIEMAIMPLPCMPESTRMU128IMM8 *PFNIEMAIMPLPCMPESTRMU128IMM8;
4275
4276	FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_pcmpistri_u128, iemAImpl_pcmpistri_u128_fallback;
4277	FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_pcmpestri_u128, iemAImpl_pcmpestri_u128_fallback;
4278	FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_pcmpistrm_u128, iemAImpl_pcmpistrm_u128_fallback;
4279	FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_pcmpestrm_u128, iemAImpl_pcmpestrm_u128_fallback;
4280	FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_vpcmpistri_u128, iemAImpl_vpcmpistri_u128_fallback;
4281	FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_vpcmpestri_u128, iemAImpl_vpcmpestri_u128_fallback;
4282	FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_vpcmpistrm_u128, iemAImpl_vpcmpistrm_u128_fallback;
4283	FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_vpcmpestrm_u128, iemAImpl_vpcmpestrm_u128_fallback;
4284
4285
4286	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pclmulqdq_u128, iemAImpl_pclmulqdq_u128_fallback;
4287	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback;
4288
4289	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_mpsadbw_u128, iemAImpl_mpsadbw_u128_fallback;
4290	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vmpsadbw_u128, iemAImpl_vmpsadbw_u128_fallback;
4291	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vmpsadbw_u256, iemAImpl_vmpsadbw_u256_fallback;
4292
4293	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsllw_imm_u128, iemAImpl_vpsllw_imm_u128_fallback;
4294	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsllw_imm_u256, iemAImpl_vpsllw_imm_u256_fallback;
4295	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpslld_imm_u128, iemAImpl_vpslld_imm_u128_fallback;
4296	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpslld_imm_u256, iemAImpl_vpslld_imm_u256_fallback;
4297	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsllq_imm_u128, iemAImpl_vpsllq_imm_u128_fallback;
4298	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsllq_imm_u256, iemAImpl_vpsllq_imm_u256_fallback;
4299	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4300	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4301	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4302	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4303
4304	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsraw_imm_u128, iemAImpl_vpsraw_imm_u128_fallback;
4305	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsraw_imm_u256, iemAImpl_vpsraw_imm_u256_fallback;
4306	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrad_imm_u128, iemAImpl_vpsrad_imm_u128_fallback;
4307	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrad_imm_u256, iemAImpl_vpsrad_imm_u256_fallback;
4308
4309	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrlw_imm_u128, iemAImpl_vpsrlw_imm_u128_fallback;
4310	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrlw_imm_u256, iemAImpl_vpsrlw_imm_u256_fallback;
4311	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrld_imm_u128, iemAImpl_vpsrld_imm_u128_fallback;
4312	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrld_imm_u256, iemAImpl_vpsrld_imm_u256_fallback;
4313	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrlq_imm_u128, iemAImpl_vpsrlq_imm_u128_fallback;
4314	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrlq_imm_u256, iemAImpl_vpsrlq_imm_u256_fallback;
4315	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4316	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4317	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4318	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4319
4320	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpermilps_u128, iemAImpl_vpermilps_u128_fallback;
4321	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vpermilps_imm_u128, iemAImpl_vpermilps_imm_u128_fallback;
4322	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermilps_u256, iemAImpl_vpermilps_u256_fallback;
4323	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermilps_imm_u256, iemAImpl_vpermilps_imm_u256_fallback;
4324
4325	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpermilpd_u128, iemAImpl_vpermilpd_u128_fallback;
4326	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vpermilpd_imm_u128, iemAImpl_vpermilpd_imm_u128_fallback;
4327	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermilpd_u256, iemAImpl_vpermilpd_u256_fallback;
4328	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermilpd_imm_u256, iemAImpl_vpermilpd_imm_u256_fallback;
4329
4330	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllvd_u128, iemAImpl_vpsllvd_u128_fallback;
4331	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllvd_u256, iemAImpl_vpsllvd_u256_fallback;
4332	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllvq_u128, iemAImpl_vpsllvq_u128_fallback;
4333	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllvq_u256, iemAImpl_vpsllvq_u256_fallback;
4334	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsravd_u128, iemAImpl_vpsravd_u128_fallback;
4335	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsravd_u256, iemAImpl_vpsravd_u256_fallback;
4336	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlvd_u128, iemAImpl_vpsrlvd_u128_fallback;
4337	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlvd_u256, iemAImpl_vpsrlvd_u256_fallback;
4338	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlvq_u128, iemAImpl_vpsrlvq_u128_fallback;
4339	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlvq_u256, iemAImpl_vpsrlvq_u256_fallback;
4340	/** @} */
4341
4342	/** @name Media Odds and Ends
4343	* @{ */
4344	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
4345	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
4346	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
4347	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
4348	FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
4349	FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
4350	FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
4351	FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
4352
4353	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
4354	typedef FNIEMAIMPLF2EFL128 *PFNIEMAIMPLF2EFL128;
4355	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
4356	typedef FNIEMAIMPLF2EFL256 *PFNIEMAIMPLF2EFL256;
4357	FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
4358	FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
4359	FNIEMAIMPLF2EFL128 iemAImpl_vtestps_u128, iemAImpl_vtestps_u128_fallback;
4360	FNIEMAIMPLF2EFL256 iemAImpl_vtestps_u256, iemAImpl_vtestps_u256_fallback;
4361	FNIEMAIMPLF2EFL128 iemAImpl_vtestpd_u128, iemAImpl_vtestpd_u128_fallback;
4362	FNIEMAIMPLF2EFL256 iemAImpl_vtestpd_u256, iemAImpl_vtestpd_u256_fallback;
4363
4364	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32U64,(uint32_t uMxCsrIn, int32_t pi32Dst, const uint64_t pu64Src)); /* pu64Src is a double precision floating point. */
4365	typedef FNIEMAIMPLSSEF2I32U64 *PFNIEMAIMPLSSEF2I32U64;
4366	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64U64,(uint32_t uMxCsrIn, int64_t pi64Dst, const uint64_t pu64Src)); /* pu64Src is a double precision floating point. */
4367	typedef FNIEMAIMPLSSEF2I64U64 *PFNIEMAIMPLSSEF2I64U64;
4368	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32U32,(uint32_t uMxCsrIn, int32_t pi32Dst, const uint32_t pu32Src)); /* pu32Src is a single precision floating point. */
4369	typedef FNIEMAIMPLSSEF2I32U32 *PFNIEMAIMPLSSEF2I32U32;
4370	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64U32,(uint32_t uMxCsrIn, int64_t pi64Dst, const uint32_t pu32Src)); /* pu32Src is a single precision floating point. */
4371	typedef FNIEMAIMPLSSEF2I64U32 *PFNIEMAIMPLSSEF2I64U32;
4372	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32R32,(uint32_t uMxCsrIn, int32_t *pi32Dst, PCRTFLOAT32U pr32Src));
4373	typedef FNIEMAIMPLSSEF2I32R32 *PFNIEMAIMPLSSEF2I32R32;
4374	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64R32,(uint32_t uMxCsrIn, int64_t *pi64Dst, PCRTFLOAT32U pr32Src));
4375	typedef FNIEMAIMPLSSEF2I64R32 *PFNIEMAIMPLSSEF2I64R32;
4376	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32R64,(uint32_t uMxCsrIn, int32_t *pi32Dst, PCRTFLOAT64U pr64Src));
4377	typedef FNIEMAIMPLSSEF2I32R64 *PFNIEMAIMPLSSEF2I32R64;
4378	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64R64,(uint32_t uMxCsrIn, int64_t *pi64Dst, PCRTFLOAT64U pr64Src));
4379	typedef FNIEMAIMPLSSEF2I64R64 *PFNIEMAIMPLSSEF2I64R64;
4380
4381	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvttsd2si_i32_r64;
4382	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvtsd2si_i32_r64;
4383
4384	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvttsd2si_i64_r64;
4385	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvtsd2si_i64_r64;
4386
4387	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvttss2si_i32_r32;
4388	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvtss2si_i32_r32;
4389
4390	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvttss2si_i64_r32;
4391	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvtss2si_i64_r32;
4392
4393	FNIEMAIMPLSSEF2I32R32 iemAImpl_vcvttss2si_i32_r32, iemAImpl_vcvttss2si_i32_r32_fallback;
4394	FNIEMAIMPLSSEF2I64R32 iemAImpl_vcvttss2si_i64_r32, iemAImpl_vcvttss2si_i64_r32_fallback;
4395	FNIEMAIMPLSSEF2I32R32 iemAImpl_vcvtss2si_i32_r32, iemAImpl_vcvtss2si_i32_r32_fallback;
4396	FNIEMAIMPLSSEF2I64R32 iemAImpl_vcvtss2si_i64_r32, iemAImpl_vcvtss2si_i64_r32_fallback;
4397
4398	FNIEMAIMPLSSEF2I32R64 iemAImpl_vcvttss2si_i32_r64, iemAImpl_vcvttss2si_i32_r64_fallback;
4399	FNIEMAIMPLSSEF2I64R64 iemAImpl_vcvttss2si_i64_r64, iemAImpl_vcvttss2si_i64_r64_fallback;
4400	FNIEMAIMPLSSEF2I32R64 iemAImpl_vcvtss2si_i32_r64, iemAImpl_vcvtss2si_i32_r64_fallback;
4401	FNIEMAIMPLSSEF2I64R64 iemAImpl_vcvtss2si_i64_r64, iemAImpl_vcvtss2si_i64_r64_fallback;
4402
4403	FNIEMAIMPLSSEF2I32R32 iemAImpl_vcvttsd2si_i32_r32, iemAImpl_vcvttsd2si_i32_r32_fallback;
4404	FNIEMAIMPLSSEF2I64R32 iemAImpl_vcvttsd2si_i64_r32, iemAImpl_vcvttsd2si_i64_r32_fallback;
4405	FNIEMAIMPLSSEF2I32R32 iemAImpl_vcvtsd2si_i32_r32, iemAImpl_vcvtsd2si_i32_r32_fallback;
4406	FNIEMAIMPLSSEF2I64R32 iemAImpl_vcvtsd2si_i64_r32, iemAImpl_vcvtsd2si_i64_r32_fallback;
4407
4408	FNIEMAIMPLSSEF2I32R64 iemAImpl_vcvttsd2si_i32_r64, iemAImpl_vcvttsd2si_i32_r64_fallback;
4409	FNIEMAIMPLSSEF2I64R64 iemAImpl_vcvttsd2si_i64_r64, iemAImpl_vcvttsd2si_i64_r64_fallback;
4410	FNIEMAIMPLSSEF2I32R64 iemAImpl_vcvtsd2si_i32_r64, iemAImpl_vcvtsd2si_i32_r64_fallback;
4411	FNIEMAIMPLSSEF2I64R64 iemAImpl_vcvtsd2si_i64_r64, iemAImpl_vcvtsd2si_i64_r64_fallback;
4412
4413	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R32I32,(uint32_t uMxCsrIn, PRTFLOAT32U pr32Dst, const int32_t *pi32Src));
4414	typedef FNIEMAIMPLSSEF2R32I32 *PFNIEMAIMPLSSEF2R32I32;
4415	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R32I64,(uint32_t uMxCsrIn, PRTFLOAT32U pr32Dst, const int64_t *pi64Src));
4416	typedef FNIEMAIMPLSSEF2R32I64 *PFNIEMAIMPLSSEF2R32I64;
4417
4418	FNIEMAIMPLSSEF2R32I32 iemAImpl_cvtsi2ss_r32_i32;
4419	FNIEMAIMPLSSEF2R32I64 iemAImpl_cvtsi2ss_r32_i64;
4420
4421	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLAVXF3XMMI32,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc, const int32_t *pi32Src));
4422	typedef FNIEMAIMPLAVXF3XMMI32 *PFNIEMAIMPLAVXF3XMMI32;
4423	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLAVXF3XMMI64,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc, const int64_t *pi64Src));
4424	typedef FNIEMAIMPLAVXF3XMMI64 *PFNIEMAIMPLAVXF3XMMI64;
4425
4426	FNIEMAIMPLAVXF3XMMI32 iemAImpl_vcvtsi2ss_u128_i32, iemAImpl_vcvtsi2ss_u128_i32_fallback;
4427	FNIEMAIMPLAVXF3XMMI64 iemAImpl_vcvtsi2ss_u128_i64, iemAImpl_vcvtsi2ss_u128_i64_fallback;
4428
4429
4430	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R64I32,(uint32_t uMxCsrIn, PRTFLOAT64U pr64Dst, const int32_t *pi32Src));
4431	typedef FNIEMAIMPLSSEF2R64I32 *PFNIEMAIMPLSSEF2R64I32;
4432	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R64I64,(uint32_t uMxCsrIn, PRTFLOAT64U pr64Dst, const int64_t *pi64Src));
4433	typedef FNIEMAIMPLSSEF2R64I64 *PFNIEMAIMPLSSEF2R64I64;
4434
4435	FNIEMAIMPLSSEF2R64I32 iemAImpl_cvtsi2sd_r64_i32;
4436	FNIEMAIMPLSSEF2R64I64 iemAImpl_cvtsi2sd_r64_i64;
4437
4438	FNIEMAIMPLAVXF3XMMI32 iemAImpl_vcvtsi2sd_u128_i32, iemAImpl_vcvtsi2sd_u128_i32_fallback;
4439	FNIEMAIMPLAVXF3XMMI64 iemAImpl_vcvtsi2sd_u128_i64, iemAImpl_vcvtsi2sd_u128_i64_fallback;
4440
4441	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtps2pd_u128_u64,(uint32_t uMxCsrIn, PX86XMMREG puDst, const uint64_t pu64Src)); / Actually two single precision floating point values. */
4442	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtps2pd_u128_u64_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, const uint64_t pu64Src)); / Actually two single precision floating point values. */
4443	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtps2pd_u256_u128,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86XMMREG puSrc));
4444	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtps2pd_u256_u128_fallback,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86XMMREG puSrc));
4445
4446
4447	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtdq2pd_u128_u64,(uint32_t uMxCsrIn, PX86XMMREG puDst, const uint64_t pu64Src)); / Actually two single precision floating point values. */
4448	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtdq2pd_u128_u64_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, const uint64_t pu64Src)); / Actually two single precision floating point values. */
4449	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtdq2pd_u256_u128,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86XMMREG puSrc));
4450	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtdq2pd_u256_u128_fallback,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86XMMREG puSrc));
4451
4452
4453	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLF2EFLMXCSRR32R32,(uint32_t uMxCsrIn, uint32_t *pfEFlags, RTFLOAT32U uSrc1, RTFLOAT32U uSrc2));
4454	typedef FNIEMAIMPLF2EFLMXCSRR32R32 *PFNIEMAIMPLF2EFLMXCSRR32R32;
4455
4456	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLF2EFLMXCSRR64R64,(uint32_t uMxCsrIn, uint32_t *pfEFlags, RTFLOAT64U uSrc1, RTFLOAT64U uSrc2));
4457	typedef FNIEMAIMPLF2EFLMXCSRR64R64 *PFNIEMAIMPLF2EFLMXCSRR64R64;
4458
4459	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_ucomiss_u128;
4460	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback;
4461
4462	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_ucomisd_u128;
4463	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback;
4464
4465	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_comiss_u128;
4466	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback;
4467
4468	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_comisd_u128;
4469	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback;
4470
4471
4472	typedef struct IEMMEDIAF2XMMSRC
4473	{
4474	X86XMMREG uSrc1;
4475	X86XMMREG uSrc2;
4476	} IEMMEDIAF2XMMSRC;
4477	typedef IEMMEDIAF2XMMSRC *PIEMMEDIAF2XMMSRC;
4478	typedef const IEMMEDIAF2XMMSRC *PCIEMMEDIAF2XMMSRC;
4479
4480
4481	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF3XMMIMM8,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC puSrc, uint8_t bEvil));
4482	typedef FNIEMAIMPLMEDIAF3XMMIMM8 *PFNIEMAIMPLMEDIAF3XMMIMM8;
4483
4484
4485	typedef struct IEMMEDIAF2YMMSRC
4486	{
4487	X86YMMREG uSrc1;
4488	X86YMMREG uSrc2;
4489	} IEMMEDIAF2YMMSRC;
4490	typedef IEMMEDIAF2YMMSRC *PIEMMEDIAF2YMMSRC;
4491	typedef const IEMMEDIAF2YMMSRC *PCIEMMEDIAF2YMMSRC;
4492
4493
4494	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF3YMMIMM8,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCIEMMEDIAF2YMMSRC puSrc, uint8_t bEvil));
4495	typedef FNIEMAIMPLMEDIAF3YMMIMM8 *PFNIEMAIMPLMEDIAF3YMMIMM8;
4496
4497
4498	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_cmpps_u128;
4499	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_cmppd_u128;
4500	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_cmpss_u128;
4501	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_cmpsd_u128;
4502
4503	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vcmpps_u128, iemAImpl_vcmpps_u128_fallback;
4504	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vcmppd_u128, iemAImpl_vcmppd_u128_fallback;
4505	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vcmpss_u128, iemAImpl_vcmpss_u128_fallback;
4506	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vcmpsd_u128, iemAImpl_vcmpsd_u128_fallback;
4507
4508	FNIEMAIMPLMEDIAF3YMMIMM8 iemAImpl_vcmpps_u256, iemAImpl_vcmpps_u256_fallback;
4509	FNIEMAIMPLMEDIAF3YMMIMM8 iemAImpl_vcmppd_u256, iemAImpl_vcmppd_u256_fallback;
4510
4511	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_roundss_u128;
4512	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_roundsd_u128;
4513
4514	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_dpps_u128, iemAImpl_dpps_u128_fallback;
4515	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_dppd_u128, iemAImpl_dppd_u128_fallback;
4516
4517
4518	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF2U128IMM8,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc, uint8_t bEvil));
4519	typedef FNIEMAIMPLMEDIAF2U128IMM8 *PFNIEMAIMPLMEDIAF2U128IMM8;
4520
4521
4522	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF2U256IMM8,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86YMMREG puSrc, uint8_t bEvil));
4523	typedef FNIEMAIMPLMEDIAF2U256IMM8 *PFNIEMAIMPLMEDIAF2U256IMM8;
4524
4525
4526	FNIEMAIMPLMEDIAF2U128IMM8 iemAImpl_roundps_u128, iemAImpl_roundps_u128_fallback;
4527	FNIEMAIMPLMEDIAF2U128IMM8 iemAImpl_roundpd_u128, iemAImpl_roundpd_u128_fallback;
4528
4529	FNIEMAIMPLMEDIAF2U128IMM8 iemAImpl_vroundps_u128, iemAImpl_vroundps_u128_fallback;
4530	FNIEMAIMPLMEDIAF2U128IMM8 iemAImpl_vroundpd_u128, iemAImpl_vroundpd_u128_fallback;
4531
4532	FNIEMAIMPLMEDIAF2U256IMM8 iemAImpl_vroundps_u256, iemAImpl_vroundps_u256_fallback;
4533	FNIEMAIMPLMEDIAF2U256IMM8 iemAImpl_vroundpd_u256, iemAImpl_vroundpd_u256_fallback;
4534
4535	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vroundss_u128, iemAImpl_vroundss_u128_fallback;
4536	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vroundsd_u128, iemAImpl_vroundsd_u128_fallback;
4537
4538	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vdpps_u128, iemAImpl_vdpps_u128_fallback;
4539	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vdppd_u128, iemAImpl_vdppd_u128_fallback;
4540
4541	FNIEMAIMPLMEDIAF3YMMIMM8 iemAImpl_vdpps_u256, iemAImpl_vdpps_u256_fallback;
4542
4543
4544	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU64U128,(uint32_t fMxCsrIn, uint64_t *pu64Dst, PCX86XMMREG pSrc));
4545	typedef FNIEMAIMPLMXCSRU64U128 *PFNIEMAIMPLMXCSRU64U128;
4546
4547	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvtpd2pi_u128;
4548	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvttpd2pi_u128;
4549
4550	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU128U64,(uint32_t fMxCsrIn, PX86XMMREG pDst, uint64_t u64Src));
4551	typedef FNIEMAIMPLMXCSRU128U64 *PFNIEMAIMPLMXCSRU128U64;
4552
4553	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2ps_u128;
4554	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2pd_u128;
4555
4556	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU64U64,(uint32_t fMxCsrIn, uint64_t *pu64Dst, uint64_t u64Src));
4557	typedef FNIEMAIMPLMXCSRU64U64 *PFNIEMAIMPLMXCSRU64U64;
4558
4559	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvtps2pi_u128;
4560	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvttps2pi_u128;
4561
4562	/** @} */
4563
4564
4565	/** @name Function tables.
4566	* @{
4567	*/
4568
4569	/**
4570	* Function table for a binary operator providing implementation based on
4571	* operand size.
4572	*/
4573	typedef struct IEMOPBINSIZES
4574	{
4575	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
4576	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
4577	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
4578	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
4579	} IEMOPBINSIZES;
4580	/** Pointer to a binary operator function table. */
4581	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
4582
4583
4584	/**
4585	* Function table for a unary operator providing implementation based on
4586	* operand size.
4587	*/
4588	typedef struct IEMOPUNARYSIZES
4589	{
4590	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
4591	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
4592	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
4593	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
4594	} IEMOPUNARYSIZES;
4595	/** Pointer to a unary operator function table. */
4596	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
4597
4598
4599	/**
4600	* Function table for a shift operator providing implementation based on
4601	* operand size.
4602	*/
4603	typedef struct IEMOPSHIFTSIZES
4604	{
4605	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
4606	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
4607	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
4608	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
4609	} IEMOPSHIFTSIZES;
4610	/** Pointer to a shift operator function table. */
4611	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
4612
4613
4614	/**
4615	* Function table for a multiplication or division operation.
4616	*/
4617	typedef struct IEMOPMULDIVSIZES
4618	{
4619	PFNIEMAIMPLMULDIVU8 pfnU8;
4620	PFNIEMAIMPLMULDIVU16 pfnU16;
4621	PFNIEMAIMPLMULDIVU32 pfnU32;
4622	PFNIEMAIMPLMULDIVU64 pfnU64;
4623	} IEMOPMULDIVSIZES;
4624	/** Pointer to a multiplication or division operation function table. */
4625	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
4626
4627
4628	/**
4629	* Function table for a double precision shift operator providing implementation
4630	* based on operand size.
4631	*/
4632	typedef struct IEMOPSHIFTDBLSIZES
4633	{
4634	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
4635	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
4636	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
4637	} IEMOPSHIFTDBLSIZES;
4638	/** Pointer to a double precision shift function table. */
4639	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
4640
4641
4642	/**
4643	* Function table for media instruction taking two full sized media source
4644	* registers and one full sized destination register (AVX).
4645	*/
4646	typedef struct IEMOPMEDIAF3
4647	{
4648	PFNIEMAIMPLMEDIAF3U128 pfnU128;
4649	PFNIEMAIMPLMEDIAF3U256 pfnU256;
4650	} IEMOPMEDIAF3;
4651	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4652	typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
4653
4654	/** @def IEMOPMEDIAF3_INIT_VARS_EX
4655	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4656	* given functions as initializers. For use in AVX functions where a pair of
4657	* functions are only used once and the function table need not be public. */
4658	#ifndef TST_IEM_CHECK_MC
4659	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4660	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4661	static IEMOPMEDIAF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4662	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4663	# else
4664	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4665	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4666	# endif
4667	#else
4668	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4669	#endif
4670	/** @def IEMOPMEDIAF3_INIT_VARS
4671	* Generate AVX function tables for the @a a_InstrNm instruction.
4672	* @sa IEMOPMEDIAF3_INIT_VARS_EX */
4673	#define IEMOPMEDIAF3_INIT_VARS(a_InstrNm) \
4674	IEMOPMEDIAF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4675	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4676
4677
4678	/**
4679	* Function table for media instruction taking one full sized media source
4680	* registers and one full sized destination register (AVX).
4681	*/
4682	typedef struct IEMOPMEDIAF2
4683	{
4684	PFNIEMAIMPLMEDIAF2U128 pfnU128;
4685	PFNIEMAIMPLMEDIAF2U256 pfnU256;
4686	} IEMOPMEDIAF2;
4687	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4688	typedef IEMOPMEDIAF2 const *PCIEMOPMEDIAF2;
4689
4690	/** @def IEMOPMEDIAF2_INIT_VARS_EX
4691	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4692	* given functions as initializers. For use in AVX functions where a pair of
4693	* functions are only used once and the function table need not be public. */
4694	#ifndef TST_IEM_CHECK_MC
4695	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4696	# define IEMOPMEDIAF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4697	static IEMOPMEDIAF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4698	static IEMOPMEDIAF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4699	# else
4700	# define IEMOPMEDIAF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4701	static IEMOPMEDIAF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4702	# endif
4703	#else
4704	# define IEMOPMEDIAF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4705	#endif
4706	/** @def IEMOPMEDIAF2_INIT_VARS
4707	* Generate AVX function tables for the @a a_InstrNm instruction.
4708	* @sa IEMOPMEDIAF2_INIT_VARS_EX */
4709	#define IEMOPMEDIAF2_INIT_VARS(a_InstrNm) \
4710	IEMOPMEDIAF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4711	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4712
4713
4714	/**
4715	* Function table for media instruction taking two full sized media source
4716	* registers and one full sized destination register, but no additional state
4717	* (AVX).
4718	*/
4719	typedef struct IEMOPMEDIAOPTF3
4720	{
4721	PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
4722	PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
4723	} IEMOPMEDIAOPTF3;
4724	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4725	typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
4726
4727	/** @def IEMOPMEDIAOPTF3_INIT_VARS_EX
4728	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4729	* given functions as initializers. For use in AVX functions where a pair of
4730	* functions are only used once and the function table need not be public. */
4731	#ifndef TST_IEM_CHECK_MC
4732	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4733	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4734	static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4735	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4736	# else
4737	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4738	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4739	# endif
4740	#else
4741	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4742	#endif
4743	/** @def IEMOPMEDIAOPTF3_INIT_VARS
4744	* Generate AVX function tables for the @a a_InstrNm instruction.
4745	* @sa IEMOPMEDIAOPTF3_INIT_VARS_EX */
4746	#define IEMOPMEDIAOPTF3_INIT_VARS(a_InstrNm) \
4747	IEMOPMEDIAOPTF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4748	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4749
4750	/**
4751	* Function table for media instruction taking one full sized media source
4752	* registers and one full sized destination register, but no additional state
4753	* (AVX).
4754	*/
4755	typedef struct IEMOPMEDIAOPTF2
4756	{
4757	PFNIEMAIMPLMEDIAOPTF2U128 pfnU128;
4758	PFNIEMAIMPLMEDIAOPTF2U256 pfnU256;
4759	} IEMOPMEDIAOPTF2;
4760	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4761	typedef IEMOPMEDIAOPTF2 const *PCIEMOPMEDIAOPTF2;
4762
4763	/** @def IEMOPMEDIAOPTF2_INIT_VARS_EX
4764	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4765	* given functions as initializers. For use in AVX functions where a pair of
4766	* functions are only used once and the function table need not be public. */
4767	#ifndef TST_IEM_CHECK_MC
4768	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4769	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4770	static IEMOPMEDIAOPTF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4771	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4772	# else
4773	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4774	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4775	# endif
4776	#else
4777	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4778	#endif
4779	/** @def IEMOPMEDIAOPTF2_INIT_VARS
4780	* Generate AVX function tables for the @a a_InstrNm instruction.
4781	* @sa IEMOPMEDIAOPTF2_INIT_VARS_EX */
4782	#define IEMOPMEDIAOPTF2_INIT_VARS(a_InstrNm) \
4783	IEMOPMEDIAOPTF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4784	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4785
4786
4787	/**
4788	* Function table for media instruction taking one full sized media source
4789	* register and one full sized destination register and an 8-bit immediate (AVX).
4790	*/
4791	typedef struct IEMOPMEDIAF2IMM8
4792	{
4793	PFNIEMAIMPLMEDIAF2U128IMM8 pfnU128;
4794	PFNIEMAIMPLMEDIAF2U256IMM8 pfnU256;
4795	} IEMOPMEDIAF2IMM8;
4796	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4797	typedef IEMOPMEDIAF2IMM8 const *PCIEMOPMEDIAF2IMM8;
4798
4799	/** @def IEMOPMEDIAF2IMM8_INIT_VARS_EX
4800	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4801	* given functions as initializers. For use in AVX functions where a pair of
4802	* functions are only used once and the function table need not be public. */
4803	#ifndef TST_IEM_CHECK_MC
4804	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4805	# define IEMOPMEDIAF2IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4806	static IEMOPMEDIAF2IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4807	static IEMOPMEDIAF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4808	# else
4809	# define IEMOPMEDIAF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4810	static IEMOPMEDIAF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4811	# endif
4812	#else
4813	# define IEMOPMEDIAF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4814	#endif
4815	/** @def IEMOPMEDIAF2IMM8_INIT_VARS
4816	* Generate AVX function tables for the @a a_InstrNm instruction.
4817	* @sa IEMOPMEDIAF2IMM8_INIT_VARS_EX */
4818	#define IEMOPMEDIAF2IMM8_INIT_VARS(a_InstrNm) \
4819	IEMOPMEDIAF2IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4820	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4821
4822
4823	/**
4824	* Function table for media instruction taking one full sized media source
4825	* register and one full sized destination register and an 8-bit immediate, but no additional state
4826	* (AVX).
4827	*/
4828	typedef struct IEMOPMEDIAOPTF2IMM8
4829	{
4830	PFNIEMAIMPLMEDIAOPTF2U128IMM8 pfnU128;
4831	PFNIEMAIMPLMEDIAOPTF2U256IMM8 pfnU256;
4832	} IEMOPMEDIAOPTF2IMM8;
4833	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4834	typedef IEMOPMEDIAOPTF2IMM8 const *PCIEMOPMEDIAOPTF2IMM8;
4835
4836	/** @def IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX
4837	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4838	* given functions as initializers. For use in AVX functions where a pair of
4839	* functions are only used once and the function table need not be public. */
4840	#ifndef TST_IEM_CHECK_MC
4841	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4842	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4843	static IEMOPMEDIAOPTF2IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4844	static IEMOPMEDIAOPTF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4845	# else
4846	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4847	static IEMOPMEDIAOPTF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4848	# endif
4849	#else
4850	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4851	#endif
4852	/** @def IEMOPMEDIAOPTF2IMM8_INIT_VARS
4853	* Generate AVX function tables for the @a a_InstrNm instruction.
4854	* @sa IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX */
4855	#define IEMOPMEDIAOPTF2IMM8_INIT_VARS(a_InstrNm) \
4856	IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u256),\
4857	RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u256_fallback))
4858
4859	/**
4860	* Function table for media instruction taking two full sized media source
4861	* registers and one full sized destination register and an 8-bit immediate, but no additional state
4862	* (AVX).
4863	*/
4864	typedef struct IEMOPMEDIAOPTF3IMM8
4865	{
4866	PFNIEMAIMPLMEDIAOPTF3U128IMM8 pfnU128;
4867	PFNIEMAIMPLMEDIAOPTF3U256IMM8 pfnU256;
4868	} IEMOPMEDIAOPTF3IMM8;
4869	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4870	typedef IEMOPMEDIAOPTF3IMM8 const *PCIEMOPMEDIAOPTF3IMM8;
4871
4872	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX
4873	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4874	* given functions as initializers. For use in AVX functions where a pair of
4875	* functions are only used once and the function table need not be public. */
4876	#ifndef TST_IEM_CHECK_MC
4877	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4878	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4879	static IEMOPMEDIAOPTF3IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4880	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4881	# else
4882	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4883	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4884	# endif
4885	#else
4886	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4887	#endif
4888	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS
4889	* Generate AVX function tables for the @a a_InstrNm instruction.
4890	* @sa IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX */
4891	#define IEMOPMEDIAOPTF3IMM8_INIT_VARS(a_InstrNm) \
4892	IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4893	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4894	/** @} */
4895
4896
4897	/**
4898	* Function table for blend type instruction taking three full sized media source
4899	* registers and one full sized destination register, but no additional state
4900	* (AVX).
4901	*/
4902	typedef struct IEMOPBLENDOP
4903	{
4904	PFNIEMAIMPLAVXBLENDU128 pfnU128;
4905	PFNIEMAIMPLAVXBLENDU256 pfnU256;
4906	} IEMOPBLENDOP;
4907	/** Pointer to a media operation function table for 4 full sized ops (AVX). */
4908	typedef IEMOPBLENDOP const *PCIEMOPBLENDOP;
4909
4910	/** @def IEMOPBLENDOP_INIT_VARS_EX
4911	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4912	* given functions as initializers. For use in AVX functions where a pair of
4913	* functions are only used once and the function table need not be public. */
4914	#ifndef TST_IEM_CHECK_MC
4915	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4916	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4917	static IEMOPBLENDOP const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4918	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4919	# else
4920	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4921	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4922	# endif
4923	#else
4924	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4925	#endif
4926	/** @def IEMOPBLENDOP_INIT_VARS
4927	* Generate AVX function tables for the @a a_InstrNm instruction.
4928	* @sa IEMOPBLENDOP_INIT_VARS_EX */
4929	#define IEMOPBLENDOP_INIT_VARS(a_InstrNm) \
4930	IEMOPBLENDOP_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4931	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4932
4933
4934	/** @name SSE/AVX single/double precision floating point operations.
4935	* @{ */
4936	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
4937	typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128;
4938	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128R32,(uint32_t uMxCsrIn, PX86XMMREG Result, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
4939	typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32;
4940	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128R64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
4941	typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64;
4942
4943	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
4944	typedef FNIEMAIMPLFPAVXF3U128 *PFNIEMAIMPLFPAVXF3U128;
4945	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128R32,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
4946	typedef FNIEMAIMPLFPAVXF3U128R32 *PFNIEMAIMPLFPAVXF3U128R32;
4947	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128R64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
4948	typedef FNIEMAIMPLFPAVXF3U128R64 *PFNIEMAIMPLFPAVXF3U128R64;
4949
4950	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U256,(uint32_t uMxCsrIn, PX86YMMREG pResult, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
4951	typedef FNIEMAIMPLFPAVXF3U256 *PFNIEMAIMPLFPAVXF3U256;
4952
4953	FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
4954	FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
4955	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
4956	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
4957	FNIEMAIMPLFPSSEF2U128 iemAImpl_subps_u128;
4958	FNIEMAIMPLFPSSEF2U128 iemAImpl_subpd_u128;
4959	FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
4960	FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
4961	FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
4962	FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
4963	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxps_u128;
4964	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxpd_u128;
4965	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddps_u128;
4966	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddpd_u128;
4967	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubps_u128;
4968	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubpd_u128;
4969	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtps_u128;
4970	FNIEMAIMPLFPSSEF2U128 iemAImpl_rsqrtps_u128;
4971	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtpd_u128;
4972	FNIEMAIMPLFPSSEF2U128 iemAImpl_rcpps_u128;
4973	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubps_u128;
4974	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubpd_u128;
4975
4976	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2ps_u128;
4977	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_cvtps2pd_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, uint64_t const *pu64Src));
4978
4979	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2ps_u128;
4980	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2dq_u128;
4981	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttps2dq_u128;
4982	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttpd2dq_u128;
4983	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2pd_u128;
4984	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2dq_u128;
4985
4986	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_addss_u128_r32;
4987	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_addsd_u128_r64;
4988	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_mulss_u128_r32;
4989	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_mulsd_u128_r64;
4990	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_subss_u128_r32;
4991	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_subsd_u128_r64;
4992	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_minss_u128_r32;
4993	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_minsd_u128_r64;
4994	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_divss_u128_r32;
4995	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_divsd_u128_r64;
4996	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_maxss_u128_r32;
4997	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_maxsd_u128_r64;
4998	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_cvtss2sd_u128_r32;
4999	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_cvtsd2ss_u128_r64;
5000	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_sqrtss_u128_r32;
5001	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_sqrtsd_u128_r64;
5002	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rsqrtss_u128_r32;
5003	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rcpss_u128_r32;
5004
5005	FNIEMAIMPLMEDIAF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
5006	FNIEMAIMPLMEDIAF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
5007	FNIEMAIMPLMEDIAF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
5008	FNIEMAIMPLMEDIAF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
5009	FNIEMAIMPLMEDIAF3U128 iemAImpl_vsubps_u128, iemAImpl_vsubps_u128_fallback;
5010	FNIEMAIMPLMEDIAF3U128 iemAImpl_vsubpd_u128, iemAImpl_vsubpd_u128_fallback;
5011	FNIEMAIMPLMEDIAF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
5012	FNIEMAIMPLMEDIAF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
5013	FNIEMAIMPLMEDIAF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
5014	FNIEMAIMPLMEDIAF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
5015	FNIEMAIMPLMEDIAF3U128 iemAImpl_vmaxps_u128, iemAImpl_vmaxps_u128_fallback;
5016	FNIEMAIMPLMEDIAF3U128 iemAImpl_vmaxpd_u128, iemAImpl_vmaxpd_u128_fallback;
5017	FNIEMAIMPLMEDIAF3U128 iemAImpl_vhaddps_u128, iemAImpl_vhaddps_u128_fallback;
5018	FNIEMAIMPLMEDIAF3U128 iemAImpl_vhaddpd_u128, iemAImpl_vhaddpd_u128_fallback;
5019	FNIEMAIMPLMEDIAF3U128 iemAImpl_vhsubps_u128, iemAImpl_vhsubps_u128_fallback;
5020	FNIEMAIMPLMEDIAF3U128 iemAImpl_vhsubpd_u128, iemAImpl_vhsubpd_u128_fallback;
5021	FNIEMAIMPLMEDIAF2U128 iemAImpl_vsqrtps_u128, iemAImpl_vsqrtps_u128_fallback;
5022	FNIEMAIMPLMEDIAF2U128 iemAImpl_vsqrtpd_u128, iemAImpl_vsqrtpd_u128_fallback;
5023	FNIEMAIMPLMEDIAF2U128 iemAImpl_vrsqrtps_u128, iemAImpl_vrsqrtps_u128_fallback;
5024	FNIEMAIMPLMEDIAF2U128 iemAImpl_vrcpps_u128, iemAImpl_vrcpps_u128_fallback;
5025	FNIEMAIMPLMEDIAF3U128 iemAImpl_vaddsubps_u128, iemAImpl_vaddsubps_u128_fallback;
5026	FNIEMAIMPLMEDIAF3U128 iemAImpl_vaddsubpd_u128, iemAImpl_vaddsubpd_u128_fallback;
5027	FNIEMAIMPLMEDIAF2U128 iemAImpl_vcvtdq2ps_u128, iemAImpl_vcvtdq2ps_u128_fallback;
5028	FNIEMAIMPLMEDIAF2U128 iemAImpl_vcvtps2dq_u128, iemAImpl_vcvtps2dq_u128_fallback;
5029	FNIEMAIMPLMEDIAF2U128 iemAImpl_vcvttps2dq_u128, iemAImpl_vcvttps2dq_u128_fallback;
5030	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2ps_u128_u128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
5031	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2ps_u128_u128_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
5032	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvttpd2dq_u128_u128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
5033	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvttpd2dq_u128_u128_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
5034	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2dq_u128_u128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
5035	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2dq_u128_u128_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
5036
5037
5038	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback;
5039	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback;
5040	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback;
5041	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback;
5042	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback;
5043	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback;
5044	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback;
5045	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback;
5046	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback;
5047	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback;
5048	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmaxss_u128_r32, iemAImpl_vmaxss_u128_r32_fallback;
5049	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmaxsd_u128_r64, iemAImpl_vmaxsd_u128_r64_fallback;
5050	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsqrtss_u128_r32, iemAImpl_vsqrtss_u128_r32_fallback;
5051	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsqrtsd_u128_r64, iemAImpl_vsqrtsd_u128_r64_fallback;
5052	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vrsqrtss_u128_r32, iemAImpl_vrsqrtss_u128_r32_fallback;
5053	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vrcpss_u128_r32, iemAImpl_vrcpss_u128_r32_fallback;
5054	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vcvtss2sd_u128_r32, iemAImpl_vcvtss2sd_u128_r32_fallback;
5055	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vcvtsd2ss_u128_r64, iemAImpl_vcvtsd2ss_u128_r64_fallback;
5056
5057
5058	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
5059	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
5060	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
5061	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
5062	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubps_u256, iemAImpl_vsubps_u256_fallback;
5063	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubpd_u256, iemAImpl_vsubpd_u256_fallback;
5064	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
5065	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
5066	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
5067	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
5068	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxps_u256, iemAImpl_vmaxps_u256_fallback;
5069	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxpd_u256, iemAImpl_vmaxpd_u256_fallback;
5070	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddps_u256, iemAImpl_vhaddps_u256_fallback;
5071	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddpd_u256, iemAImpl_vhaddpd_u256_fallback;
5072	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubps_u256, iemAImpl_vhsubps_u256_fallback;
5073	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubpd_u256, iemAImpl_vhsubpd_u256_fallback;
5074	FNIEMAIMPLMEDIAF3U256 iemAImpl_vaddsubps_u256, iemAImpl_vaddsubps_u256_fallback;
5075	FNIEMAIMPLMEDIAF3U256 iemAImpl_vaddsubpd_u256, iemAImpl_vaddsubpd_u256_fallback;
5076	FNIEMAIMPLMEDIAF2U256 iemAImpl_vsqrtps_u256, iemAImpl_vsqrtps_u256_fallback;
5077	FNIEMAIMPLMEDIAF2U256 iemAImpl_vsqrtpd_u256, iemAImpl_vsqrtpd_u256_fallback;
5078	FNIEMAIMPLMEDIAF2U256 iemAImpl_vrsqrtps_u256, iemAImpl_vrsqrtps_u256_fallback;
5079	FNIEMAIMPLMEDIAF2U256 iemAImpl_vrcpps_u256, iemAImpl_vrcpps_u256_fallback;
5080	FNIEMAIMPLMEDIAF2U256 iemAImpl_vcvtdq2ps_u256, iemAImpl_vcvtdq2ps_u256_fallback;
5081	FNIEMAIMPLMEDIAF2U256 iemAImpl_vcvtps2dq_u256, iemAImpl_vcvtps2dq_u256_fallback;
5082	FNIEMAIMPLMEDIAF2U256 iemAImpl_vcvttps2dq_u256, iemAImpl_vcvttps2dq_u256_fallback;
5083	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2ps_u128_u256,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5084	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2ps_u128_u256_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5085	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvttpd2dq_u128_u256,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5086	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvttpd2dq_u128_u256_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5087	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2dq_u128_u256,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5088	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2dq_u128_u256_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5089	/** @} */
5090
5091	/** @name C instruction implementations for anything slightly complicated.
5092	* @{ */
5093
5094	/**
5095	* For typedef'ing or declaring a C instruction implementation function taking
5096	* no extra arguments.
5097	*
5098	* @param a_Name The name of the type.
5099	*/
5100	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
5101	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
5102	/**
5103	* For defining a C instruction implementation function taking no extra
5104	* arguments.
5105	*
5106	* @param a_Name The name of the function
5107	*/
5108	# define IEM_CIMPL_DEF_0(a_Name) \
5109	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
5110	/**
5111	* Prototype version of IEM_CIMPL_DEF_0.
5112	*/
5113	# define IEM_CIMPL_PROTO_0(a_Name) \
5114	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
5115	/**
5116	* For calling a C instruction implementation function taking no extra
5117	* arguments.
5118	*
5119	* This special call macro adds default arguments to the call and allow us to
5120	* change these later.
5121	*
5122	* @param a_fn The name of the function.
5123	*/
5124	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
5125
5126	/** Type for a C instruction implementation function taking no extra
5127	* arguments. */
5128	typedef IEM_CIMPL_DECL_TYPE_0(FNIEMCIMPL0);
5129	/** Function pointer type for a C instruction implementation function taking
5130	* no extra arguments. */
5131	typedef FNIEMCIMPL0 *PFNIEMCIMPL0;
5132
5133	/**
5134	* For typedef'ing or declaring a C instruction implementation function taking
5135	* one extra argument.
5136	*
5137	* @param a_Name The name of the type.
5138	* @param a_Type0 The argument type.
5139	* @param a_Arg0 The argument name.
5140	*/
5141	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
5142	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
5143	/**
5144	* For defining a C instruction implementation function taking one extra
5145	* argument.
5146	*
5147	* @param a_Name The name of the function
5148	* @param a_Type0 The argument type.
5149	* @param a_Arg0 The argument name.
5150	*/
5151	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
5152	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
5153	/**
5154	* Prototype version of IEM_CIMPL_DEF_1.
5155	*/
5156	# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
5157	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
5158	/**
5159	* For calling a C instruction implementation function taking one extra
5160	* argument.
5161	*
5162	* This special call macro adds default arguments to the call and allow us to
5163	* change these later.
5164	*
5165	* @param a_fn The name of the function.
5166	* @param a0 The name of the 1st argument.
5167	*/
5168	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
5169
5170	/**
5171	* For typedef'ing or declaring a C instruction implementation function taking
5172	* two extra arguments.
5173	*
5174	* @param a_Name The name of the type.
5175	* @param a_Type0 The type of the 1st argument
5176	* @param a_Arg0 The name of the 1st argument.
5177	* @param a_Type1 The type of the 2nd argument.
5178	* @param a_Arg1 The name of the 2nd argument.
5179	*/
5180	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
5181	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
5182	/**
5183	* For defining a C instruction implementation function taking two extra
5184	* arguments.
5185	*
5186	* @param a_Name The name of the function.
5187	* @param a_Type0 The type of the 1st argument
5188	* @param a_Arg0 The name of the 1st argument.
5189	* @param a_Type1 The type of the 2nd argument.
5190	* @param a_Arg1 The name of the 2nd argument.
5191	*/
5192	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
5193	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
5194	/**
5195	* Prototype version of IEM_CIMPL_DEF_2.
5196	*/
5197	# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
5198	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
5199	/**
5200	* For calling a C instruction implementation function taking two extra
5201	* arguments.
5202	*
5203	* This special call macro adds default arguments to the call and allow us to
5204	* change these later.
5205	*
5206	* @param a_fn The name of the function.
5207	* @param a0 The name of the 1st argument.
5208	* @param a1 The name of the 2nd argument.
5209	*/
5210	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
5211
5212	/**
5213	* For typedef'ing or declaring a C instruction implementation function taking
5214	* three extra arguments.
5215	*
5216	* @param a_Name The name of the type.
5217	* @param a_Type0 The type of the 1st argument
5218	* @param a_Arg0 The name of the 1st argument.
5219	* @param a_Type1 The type of the 2nd argument.
5220	* @param a_Arg1 The name of the 2nd argument.
5221	* @param a_Type2 The type of the 3rd argument.
5222	* @param a_Arg2 The name of the 3rd argument.
5223	*/
5224	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
5225	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
5226	/**
5227	* For defining a C instruction implementation function taking three extra
5228	* arguments.
5229	*
5230	* @param a_Name The name of the function.
5231	* @param a_Type0 The type of the 1st argument
5232	* @param a_Arg0 The name of the 1st argument.
5233	* @param a_Type1 The type of the 2nd argument.
5234	* @param a_Arg1 The name of the 2nd argument.
5235	* @param a_Type2 The type of the 3rd argument.
5236	* @param a_Arg2 The name of the 3rd argument.
5237	*/
5238	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
5239	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
5240	/**
5241	* Prototype version of IEM_CIMPL_DEF_3.
5242	*/
5243	# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
5244	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
5245	/**
5246	* For calling a C instruction implementation function taking three extra
5247	* arguments.
5248	*
5249	* This special call macro adds default arguments to the call and allow us to
5250	* change these later.
5251	*
5252	* @param a_fn The name of the function.
5253	* @param a0 The name of the 1st argument.
5254	* @param a1 The name of the 2nd argument.
5255	* @param a2 The name of the 3rd argument.
5256	*/
5257	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
5258
5259
5260	/**
5261	* For typedef'ing or declaring a C instruction implementation function taking
5262	* four extra arguments.
5263	*
5264	* @param a_Name The name of the type.
5265	* @param a_Type0 The type of the 1st argument
5266	* @param a_Arg0 The name of the 1st argument.
5267	* @param a_Type1 The type of the 2nd argument.
5268	* @param a_Arg1 The name of the 2nd argument.
5269	* @param a_Type2 The type of the 3rd argument.
5270	* @param a_Arg2 The name of the 3rd argument.
5271	* @param a_Type3 The type of the 4th argument.
5272	* @param a_Arg3 The name of the 4th argument.
5273	*/
5274	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
5275	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
5276	/**
5277	* For defining a C instruction implementation function taking four extra
5278	* arguments.
5279	*
5280	* @param a_Name The name of the function.
5281	* @param a_Type0 The type of the 1st argument
5282	* @param a_Arg0 The name of the 1st argument.
5283	* @param a_Type1 The type of the 2nd argument.
5284	* @param a_Arg1 The name of the 2nd argument.
5285	* @param a_Type2 The type of the 3rd argument.
5286	* @param a_Arg2 The name of the 3rd argument.
5287	* @param a_Type3 The type of the 4th argument.
5288	* @param a_Arg3 The name of the 4th argument.
5289	*/
5290	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
5291	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
5292	a_Type2 a_Arg2, a_Type3 a_Arg3))
5293	/**
5294	* Prototype version of IEM_CIMPL_DEF_4.
5295	*/
5296	# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
5297	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
5298	a_Type2 a_Arg2, a_Type3 a_Arg3))
5299	/**
5300	* For calling a C instruction implementation function taking four extra
5301	* arguments.
5302	*
5303	* This special call macro adds default arguments to the call and allow us to
5304	* change these later.
5305	*
5306	* @param a_fn The name of the function.
5307	* @param a0 The name of the 1st argument.
5308	* @param a1 The name of the 2nd argument.
5309	* @param a2 The name of the 3rd argument.
5310	* @param a3 The name of the 4th argument.
5311	*/
5312	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
5313
5314
5315	/**
5316	* For typedef'ing or declaring a C instruction implementation function taking
5317	* five extra arguments.
5318	*
5319	* @param a_Name The name of the type.
5320	* @param a_Type0 The type of the 1st argument
5321	* @param a_Arg0 The name of the 1st argument.
5322	* @param a_Type1 The type of the 2nd argument.
5323	* @param a_Arg1 The name of the 2nd argument.
5324	* @param a_Type2 The type of the 3rd argument.
5325	* @param a_Arg2 The name of the 3rd argument.
5326	* @param a_Type3 The type of the 4th argument.
5327	* @param a_Arg3 The name of the 4th argument.
5328	* @param a_Type4 The type of the 5th argument.
5329	* @param a_Arg4 The name of the 5th argument.
5330	*/
5331	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
5332	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
5333	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
5334	a_Type3 a_Arg3, a_Type4 a_Arg4))
5335	/**
5336	* For defining a C instruction implementation function taking five extra
5337	* arguments.
5338	*
5339	* @param a_Name The name of the function.
5340	* @param a_Type0 The type of the 1st argument
5341	* @param a_Arg0 The name of the 1st argument.
5342	* @param a_Type1 The type of the 2nd argument.
5343	* @param a_Arg1 The name of the 2nd argument.
5344	* @param a_Type2 The type of the 3rd argument.
5345	* @param a_Arg2 The name of the 3rd argument.
5346	* @param a_Type3 The type of the 4th argument.
5347	* @param a_Arg3 The name of the 4th argument.
5348	* @param a_Type4 The type of the 5th argument.
5349	* @param a_Arg4 The name of the 5th argument.
5350	*/
5351	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
5352	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
5353	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
5354	/**
5355	* Prototype version of IEM_CIMPL_DEF_5.
5356	*/
5357	# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
5358	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
5359	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
5360	/**
5361	* For calling a C instruction implementation function taking five extra
5362	* arguments.
5363	*
5364	* This special call macro adds default arguments to the call and allow us to
5365	* change these later.
5366	*
5367	* @param a_fn The name of the function.
5368	* @param a0 The name of the 1st argument.
5369	* @param a1 The name of the 2nd argument.
5370	* @param a2 The name of the 3rd argument.
5371	* @param a3 The name of the 4th argument.
5372	* @param a4 The name of the 5th argument.
5373	*/
5374	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
5375
5376	/** @} */
5377
5378
5379	/** @name Opcode Decoder Function Types.
5380	* @{ */
5381
5382	/** @typedef PFNIEMOP
5383	* Pointer to an opcode decoder function.
5384	*/
5385
5386	/** @def FNIEMOP_DEF
5387	* Define an opcode decoder function.
5388	*
5389	* We're using macors for this so that adding and removing parameters as well as
5390	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
5391	*
5392	* @param a_Name The function name.
5393	*/
5394
5395	/** @typedef PFNIEMOPRM
5396	* Pointer to an opcode decoder function with RM byte.
5397	*/
5398
5399	/** @def FNIEMOPRM_DEF
5400	* Define an opcode decoder function with RM byte.
5401	*
5402	* We're using macors for this so that adding and removing parameters as well as
5403	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
5404	*
5405	* @param a_Name The function name.
5406	*/
5407
5408	#if defined(__GNUC__) && defined(RT_ARCH_X86)
5409	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
5410	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
5411	# define FNIEMOP_DEF(a_Name) \
5412	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
5413	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
5414	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
5415	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
5416	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
5417
5418	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
5419	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
5420	typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
5421	# define FNIEMOP_DEF(a_Name) \
5422	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
5423	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
5424	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
5425	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
5426	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
5427
5428	#elif defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
5429	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
5430	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
5431	# define FNIEMOP_DEF(a_Name) \
5432	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
5433	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
5434	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
5435	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
5436	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
5437
5438	#else
5439	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
5440	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
5441	# define FNIEMOP_DEF(a_Name) \
5442	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
5443	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
5444	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
5445	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
5446	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
5447
5448	#endif
5449	#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
5450
5451	/**
5452	* Call an opcode decoder function.
5453	*
5454	* We're using macors for this so that adding and removing parameters can be
5455	* done as we please. See FNIEMOP_DEF.
5456	*/
5457	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
5458
5459	/**
5460	* Call a common opcode decoder function taking one extra argument.
5461	*
5462	* We're using macors for this so that adding and removing parameters can be
5463	* done as we please. See FNIEMOP_DEF_1.
5464	*/
5465	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
5466
5467	/**
5468	* Call a common opcode decoder function taking one extra argument.
5469	*
5470	* We're using macors for this so that adding and removing parameters can be
5471	* done as we please. See FNIEMOP_DEF_1.
5472	*/
5473	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
5474	/** @} */
5475
5476
5477	/** @name Misc Helpers
5478	* @{ */
5479
5480	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
5481	* due to GCC lacking knowledge about the value range of a switch. */
5482	#if RT_CPLUSPLUS_PREREQ(202000)
5483	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: [[unlikely]] AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
5484	#else
5485	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
5486	#endif
5487
5488	/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
5489	#if RT_CPLUSPLUS_PREREQ(202000)
5490	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: [[unlikely]] AssertFailedReturn(a_RetValue)
5491	#else
5492	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
5493	#endif
5494
5495	/**
5496	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
5497	* occation.
5498	*/
5499	#ifdef LOG_ENABLED
5500	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
5501	do { \
5502	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
5503	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
5504	} while (0)
5505	#else
5506	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
5507	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
5508	#endif
5509
5510	/**
5511	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
5512	* occation using the supplied logger statement.
5513	*
5514	* @param a_LoggerArgs What to log on failure.
5515	*/
5516	#ifdef LOG_ENABLED
5517	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
5518	do { \
5519	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
5520	/LogFunc(a_LoggerArgs);/ \
5521	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
5522	} while (0)
5523	#else
5524	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
5525	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
5526	#endif
5527
5528	/**
5529	* Gets the CPU mode (from fExec) as a IEMMODE value.
5530	*
5531	* @returns IEMMODE
5532	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5533	*/
5534	#define IEM_GET_CPU_MODE(a_pVCpu) ((a_pVCpu)->iem.s.fExec & IEM_F_MODE_CPUMODE_MASK)
5535
5536	/**
5537	* Check if we're currently executing in real or virtual 8086 mode.
5538	*
5539	* @returns @c true if it is, @c false if not.
5540	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5541	*/
5542	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (( ((a_pVCpu)->iem.s.fExec ^ IEM_F_MODE_X86_PROT_MASK) \
5543	& (IEM_F_MODE_X86_V86_MASK \| IEM_F_MODE_X86_PROT_MASK)) != 0)
5544
5545	/**
5546	* Check if we're currently executing in virtual 8086 mode.
5547	*
5548	* @returns @c true if it is, @c false if not.
5549	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5550	*/
5551	#define IEM_IS_V86_MODE(a_pVCpu) (((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_V86_MASK) != 0)
5552
5553	/**
5554	* Check if we're currently executing in long mode.
5555	*
5556	* @returns @c true if it is, @c false if not.
5557	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5558	*/
5559	#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
5560
5561	/**
5562	* Check if we're currently executing in a 16-bit code segment.
5563	*
5564	* @returns @c true if it is, @c false if not.
5565	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5566	*/
5567	#define IEM_IS_16BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_16BIT)
5568
5569	/**
5570	* Check if we're currently executing in a 32-bit code segment.
5571	*
5572	* @returns @c true if it is, @c false if not.
5573	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5574	*/
5575	#define IEM_IS_32BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_32BIT)
5576
5577	/**
5578	* Check if we're currently executing in a 64-bit code segment.
5579	*
5580	* @returns @c true if it is, @c false if not.
5581	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5582	*/
5583	#define IEM_IS_64BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_64BIT)
5584
5585	/**
5586	* Check if we're currently executing in real mode.
5587	*
5588	* @returns @c true if it is, @c false if not.
5589	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5590	*/
5591	#define IEM_IS_REAL_MODE(a_pVCpu) (!((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_PROT_MASK))
5592
5593	/**
5594	* Gets the current protection level (CPL).
5595	*
5596	* @returns 0..3
5597	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5598	*/
5599	#define IEM_GET_CPL(a_pVCpu) (((a_pVCpu)->iem.s.fExec >> IEM_F_X86_CPL_SHIFT) & IEM_F_X86_CPL_SMASK)
5600
5601	/**
5602	* Sets the current protection level (CPL).
5603	*
5604	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5605	*/
5606	#define IEM_SET_CPL(a_pVCpu, a_uCpl) \
5607	do { (a_pVCpu)->iem.s.fExec = ((a_pVCpu)->iem.s.fExec & ~IEM_F_X86_CPL_MASK) \| ((a_uCpl) << IEM_F_X86_CPL_SHIFT); } while (0)
5608
5609	/**
5610	* Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
5611	* @returns PCCPUMFEATURES
5612	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5613	*/
5614	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
5615
5616	/**
5617	* Returns a (const) pointer to the CPUMFEATURES for the host CPU.
5618	* @returns PCCPUMFEATURES
5619	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5620	*/
5621	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
5622
5623	/**
5624	* Evaluates to true if we're presenting an Intel CPU to the guest.
5625	*/
5626	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
5627
5628	/**
5629	* Evaluates to true if we're presenting an AMD CPU to the guest.
5630	*/
5631	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD \|\| (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
5632
5633	/**
5634	* Check if the address is canonical.
5635	*/
5636	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
5637
5638	/** Checks if the ModR/M byte is in register mode or not. */
5639	#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
5640	/** Checks if the ModR/M byte is in memory mode or not. */
5641	#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
5642
5643	/**
5644	* Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
5645	*
5646	* For use during decoding.
5647	*/
5648	#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| (a_pVCpu)->iem.s.uRexReg )
5649	/**
5650	* Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
5651	*
5652	* For use during decoding.
5653	*/
5654	#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) \| (a_pVCpu)->iem.s.uRexB )
5655
5656	/**
5657	* Gets the register (reg) part of a ModR/M encoding, without REX.R.
5658	*
5659	* For use during decoding.
5660	*/
5661	#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
5662	/**
5663	* Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
5664	*
5665	* For use during decoding.
5666	*/
5667	#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
5668
5669	/**
5670	* Gets the register (reg) part of a ModR/M encoding as an extended 8-bit
5671	* register index, with REX.R added in.
5672	*
5673	* For use during decoding.
5674	*
5675	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
5676	*/
5677	#define IEM_GET_MODRM_REG_EX8(a_pVCpu, a_bRm) \
5678	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
5679	\|\| !((a_bRm) & (4 << X86_MODRM_REG_SHIFT)) /* IEM_GET_MODRM_REG(pVCpu, a_bRm) < 4 */ \
5680	? IEM_GET_MODRM_REG(pVCpu, a_bRm) : (((a_bRm) >> X86_MODRM_REG_SHIFT) & 3) \| 16)
5681	/**
5682	* Gets the r/m part of a ModR/M encoding as an extended 8-bit register index,
5683	* with REX.B added in.
5684	*
5685	* For use during decoding.
5686	*
5687	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
5688	*/
5689	#define IEM_GET_MODRM_RM_EX8(a_pVCpu, a_bRm) \
5690	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
5691	\|\| !((a_bRm) & 4) /* IEM_GET_MODRM_RM(pVCpu, a_bRm) < 4 */ \
5692	? IEM_GET_MODRM_RM(pVCpu, a_bRm) : ((a_bRm) & 3) \| 16)
5693
5694	/**
5695	* Combines the prefix REX and ModR/M byte for passing to
5696	* iemOpHlpCalcRmEffAddrThreadedAddr64().
5697	*
5698	* @returns The ModRM byte but with bit 3 set to REX.B and bit 4 to REX.X.
5699	* The two bits are part of the REG sub-field, which isn't needed in
5700	* iemOpHlpCalcRmEffAddrThreadedAddr64().
5701	*
5702	* For use during decoding/recompiling.
5703	*/
5704	#define IEM_GET_MODRM_EX(a_pVCpu, a_bRm) \
5705	( ((a_bRm) & ~X86_MODRM_REG_MASK) \
5706	\| (uint8_t)( (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X)) >> (25 - 3) ) )
5707	AssertCompile(IEM_OP_PRF_REX_B == RT_BIT_32(25));
5708	AssertCompile(IEM_OP_PRF_REX_X == RT_BIT_32(26));
5709
5710	/**
5711	* Gets the effective VEX.VVVV value.
5712	*
5713	* The 4th bit is ignored if not 64-bit code.
5714	* @returns effective V-register value.
5715	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5716	*/
5717	#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
5718	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
5719
5720
5721	/**
5722	* Gets the register (reg) part of a the special 4th register byte used by
5723	* vblendvps and vblendvpd.
5724	*
5725	* For use during decoding.
5726	*/
5727	#define IEM_GET_IMM8_REG(a_pVCpu, a_bRegImm8) \
5728	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_bRegImm8) >> 4 : ((a_bRegImm8) >> 4) & 7)
5729
5730
5731	/**
5732	* Checks if we're executing inside an AMD-V or VT-x guest.
5733	*/
5734	#if defined(VBOX_WITH_NESTED_HWVIRT_VMX) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
5735	# define IEM_IS_IN_GUEST(a_pVCpu) RT_BOOL((a_pVCpu)->iem.s.fExec & IEM_F_X86_CTX_IN_GUEST)
5736	#else
5737	# define IEM_IS_IN_GUEST(a_pVCpu) false
5738	#endif
5739
5740
5741	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5742
5743	/**
5744	* Check if the guest has entered VMX root operation.
5745	*/
5746	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
5747
5748	/**
5749	* Check if the guest has entered VMX non-root operation.
5750	*/
5751	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) ( ((a_pVCpu)->iem.s.fExec & (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST)) \
5752	== (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST) )
5753
5754	/**
5755	* Check if the nested-guest has the given Pin-based VM-execution control set.
5756	*/
5757	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) (CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
5758
5759	/**
5760	* Check if the nested-guest has the given Processor-based VM-execution control set.
5761	*/
5762	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) (CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
5763
5764	/**
5765	* Check if the nested-guest has the given Secondary Processor-based VM-execution
5766	* control set.
5767	*/
5768	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) (CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
5769
5770	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
5771	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
5772
5773	/** Whether a shadow VMCS is present for the given VCPU. */
5774	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
5775
5776	/** Gets the VMXON region pointer. */
5777	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
5778
5779	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
5780	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
5781
5782	/** Whether a current VMCS is present for the given VCPU. */
5783	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
5784
5785	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
5786	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
5787	do \
5788	{ \
5789	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
5790	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
5791	} while (0)
5792
5793	/** Clears any current VMCS for the given VCPU. */
5794	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
5795	do \
5796	{ \
5797	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
5798	} while (0)
5799
5800	/**
5801	* Invokes the VMX VM-exit handler for an instruction intercept.
5802	*/
5803	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
5804	do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
5805
5806	/**
5807	* Invokes the VMX VM-exit handler for an instruction intercept where the
5808	* instruction provides additional VM-exit information.
5809	*/
5810	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
5811	do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
5812
5813	/**
5814	* Invokes the VMX VM-exit handler for a task switch.
5815	*/
5816	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
5817	do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
5818
5819	/**
5820	* Invokes the VMX VM-exit handler for MWAIT.
5821	*/
5822	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
5823	do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
5824
5825	/**
5826	* Invokes the VMX VM-exit handler for EPT faults.
5827	*/
5828	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
5829	do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
5830
5831	/**
5832	* Invokes the VMX VM-exit handler.
5833	*/
5834	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
5835	do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
5836
5837	#else
5838	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
5839	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
5840	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
5841	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
5842	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
5843	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5844	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5845	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5846	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5847	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5848	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
5849
5850	#endif
5851
5852	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5853	/**
5854	* Checks if we're executing a guest using AMD-V.
5855	*/
5856	# define IEM_SVM_IS_IN_GUEST(a_pVCpu) ( (a_pVCpu->iem.s.fExec & (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST)) \
5857	== (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST))
5858	/**
5859	* Check if an SVM control/instruction intercept is set.
5860	*/
5861	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
5862	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
5863
5864	/**
5865	* Check if an SVM read CRx intercept is set.
5866	*/
5867	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
5868	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
5869
5870	/**
5871	* Check if an SVM write CRx intercept is set.
5872	*/
5873	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
5874	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
5875
5876	/**
5877	* Check if an SVM read DRx intercept is set.
5878	*/
5879	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
5880	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
5881
5882	/**
5883	* Check if an SVM write DRx intercept is set.
5884	*/
5885	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
5886	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
5887
5888	/**
5889	* Check if an SVM exception intercept is set.
5890	*/
5891	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
5892	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
5893
5894	/**
5895	* Invokes the SVM \#VMEXIT handler for the nested-guest.
5896	*/
5897	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
5898	do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
5899
5900	/**
5901	* Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
5902	* corresponding decode assist information.
5903	*/
5904	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
5905	do \
5906	{ \
5907	uint64_t uExitInfo1; \
5908	if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
5909	&& (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
5910	uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK \| ((a_iGReg) & 7); \
5911	else \
5912	uExitInfo1 = 0; \
5913	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
5914	} while (0)
5915
5916	/** Check and handles SVM nested-guest instruction intercept and updates
5917	* NRIP if needed.
5918	*/
5919	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
5920	do \
5921	{ \
5922	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
5923	{ \
5924	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
5925	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
5926	} \
5927	} while (0)
5928
5929	/** Checks and handles SVM nested-guest CR0 read intercept. */
5930	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
5931	do \
5932	{ \
5933	if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
5934	{ /* probably likely */ } \
5935	else \
5936	{ \
5937	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
5938	IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
5939	} \
5940	} while (0)
5941
5942	/**
5943	* Updates the NextRIP (NRI) field in the nested-guest VMCB.
5944	*/
5945	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) \
5946	do { \
5947	if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
5948	CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_cbInstr)); \
5949	} while (0)
5950
5951	#else
5952	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
5953	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
5954	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
5955	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
5956	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
5957	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
5958	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
5959	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
5960	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, \
5961	a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
5962	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
5963	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) do { } while (0)
5964
5965	#endif
5966
5967	/** @} */
5968
5969	uint32_t iemCalcExecDbgFlagsSlow(PVMCPUCC pVCpu);
5970	VBOXSTRICTRC iemExecInjectPendingTrap(PVMCPUCC pVCpu);
5971
5972
5973	/**
5974	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
5975	*/
5976	typedef union IEMSELDESC
5977	{
5978	/** The legacy view. */
5979	X86DESC Legacy;
5980	/** The long mode view. */
5981	X86DESC64 Long;
5982	} IEMSELDESC;
5983	/** Pointer to a selector descriptor table entry. */
5984	typedef IEMSELDESC *PIEMSELDESC;
5985
5986	/** @name Raising Exceptions.
5987	* @{ */
5988	VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
5989	uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
5990
5991	VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
5992	uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
5993	#ifdef IEM_WITH_SETJMP
5994	DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
5995	uint32_t fFlags, uint16_t uErr, uint64_t uCr2) IEM_NOEXCEPT_MAY_LONGJMP;
5996	#endif
5997	VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
5998	#ifdef IEM_WITH_SETJMP
5999	DECL_NO_RETURN(void) iemRaiseDivideErrorJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6000	#endif
6001	VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
6002	VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
6003	VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
6004	#ifdef IEM_WITH_SETJMP
6005	DECL_NO_RETURN(void) iemRaiseUndefinedOpcodeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6006	#endif
6007	VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
6008	#ifdef IEM_WITH_SETJMP
6009	DECL_NO_RETURN(void) iemRaiseDeviceNotAvailableJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6010	#endif
6011	VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
6012	VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
6013	VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
6014	VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
6015	/VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;/
6016	VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
6017	VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
6018	VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
6019	VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
6020	VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
6021	VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
6022	#ifdef IEM_WITH_SETJMP
6023	DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6024	#endif
6025	VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
6026	VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
6027	VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
6028	#ifdef IEM_WITH_SETJMP
6029	DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
6030	#endif
6031	VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
6032	#ifdef IEM_WITH_SETJMP
6033	DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) IEM_NOEXCEPT_MAY_LONGJMP;
6034	#endif
6035	VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
6036	#ifdef IEM_WITH_SETJMP
6037	DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
6038	#endif
6039	VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) RT_NOEXCEPT;
6040	#ifdef IEM_WITH_SETJMP
6041	DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) IEM_NOEXCEPT_MAY_LONGJMP;
6042	#endif
6043	VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
6044	#ifdef IEM_WITH_SETJMP
6045	DECL_NO_RETURN(void) iemRaiseMathFaultJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6046	#endif
6047	VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu) RT_NOEXCEPT;
6048	#ifdef IEM_WITH_SETJMP
6049	DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6050	#endif
6051	VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
6052	#ifdef IEM_WITH_SETJMP
6053	DECL_NO_RETURN(void) iemRaiseSimdFpExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6054	#endif
6055
6056	void iemLogSyscallRealModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
6057	void iemLogSyscallProtModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
6058
6059	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
6060	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
6061	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
6062
6063	/**
6064	* Macro for calling iemCImplRaiseDivideError().
6065	*
6066	* This is for things that will _always_ decode to an \#DE, taking the
6067	* recompiler into consideration and everything.
6068	*
6069	* @return Strict VBox status code.
6070	*/
6071	#define IEMOP_RAISE_DIVIDE_ERROR_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseDivideError)
6072
6073	/**
6074	* Macro for calling iemCImplRaiseInvalidLockPrefix().
6075	*
6076	* This is for things that will _always_ decode to an \#UD, taking the
6077	* recompiler into consideration and everything.
6078	*
6079	* @return Strict VBox status code.
6080	*/
6081	#define IEMOP_RAISE_INVALID_LOCK_PREFIX_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidLockPrefix)
6082
6083	/**
6084	* Macro for calling iemCImplRaiseInvalidOpcode() for decode/static \#UDs.
6085	*
6086	* This is for things that will _always_ decode to an \#UD, taking the
6087	* recompiler into consideration and everything.
6088	*
6089	* @return Strict VBox status code.
6090	*/
6091	#define IEMOP_RAISE_INVALID_OPCODE_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
6092
6093	/**
6094	* Macro for calling iemCImplRaiseInvalidOpcode() for runtime-style \#UDs.
6095	*
6096	* Using this macro means you've got _buggy_ _code_ and are doing things that
6097	* belongs exclusively in IEMAllCImpl.cpp during decoding.
6098	*
6099	* @return Strict VBox status code.
6100	* @see IEMOP_RAISE_INVALID_OPCODE_RET
6101	*/
6102	#define IEMOP_RAISE_INVALID_OPCODE_RUNTIME_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
6103
6104	/** @} */
6105
6106	/** @name Register Access.
6107	* @{ */
6108	VBOXSTRICTRC iemRegRipRelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
6109	IEMMODE enmEffOpSize) RT_NOEXCEPT;
6110	VBOXSTRICTRC iemRegRipRelativeJumpS16AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int16_t offNextInstr) RT_NOEXCEPT;
6111	VBOXSTRICTRC iemRegRipRelativeJumpS32AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int32_t offNextInstr,
6112	IEMMODE enmEffOpSize) RT_NOEXCEPT;
6113	/** @} */
6114
6115	/** @name FPU access and helpers.
6116	* @{ */
6117	void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
6118	void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6119	void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
6120	void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
6121	void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
6122	void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
6123	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6124	void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
6125	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6126	void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
6127	void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
6128	void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
6129	void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6130	void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
6131	void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6132	void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
6133	void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6134	void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
6135	void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6136	void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
6137	void iemFpuStackPushUnderflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
6138	void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
6139	void iemFpuStackPushOverflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
6140	void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6141	/** @} */
6142
6143	/** @name SSE+AVX SIMD access and helpers.
6144	* @{ */
6145	void iemSseUpdateMxcsr(PVMCPUCC pVCpu, uint32_t fMxcsr) RT_NOEXCEPT;
6146	/** @} */
6147
6148	/** @name Memory access.
6149	* @{ */
6150
6151	/** Report a \#GP instead of \#AC and do not restrict to ring-3 */
6152	#define IEM_MEMMAP_F_ALIGN_GP RT_BIT_32(16)
6153	/** SSE access that should report a \#GP instead of \#AC, unless MXCSR.MM=1
6154	* when it works like normal \#AC. Always used with IEM_MEMMAP_F_ALIGN_GP. */
6155	#define IEM_MEMMAP_F_ALIGN_SSE RT_BIT_32(17)
6156	/** If \#AC is applicable, raise it. Always used with IEM_MEMMAP_F_ALIGN_GP.
6157	* Users include FXSAVE & FXRSTOR. */
6158	#define IEM_MEMMAP_F_ALIGN_GP_OR_AC RT_BIT_32(18)
6159
6160	VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void *ppvMem, uint8_t pbUnmapInfo, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
6161	uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
6162	VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
6163	#ifndef IN_RING3
6164	VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
6165	#endif
6166	void iemMemRollbackAndUnmap(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
6167	void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
6168	VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
6169	VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
6170	VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t cbAccess, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
6171
6172	void iemOpcodeFlushLight(PVMCPUCC pVCpu, uint8_t cbInstr);
6173	void iemOpcodeFlushHeavy(PVMCPUCC pVCpu, uint8_t cbInstr);
6174	#ifdef IEM_WITH_CODE_TLB
6175	void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) IEM_NOEXCEPT_MAY_LONGJMP;
6176	#else
6177	VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
6178	#endif
6179	#ifdef IEM_WITH_SETJMP
6180	uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6181	uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6182	uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6183	uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6184	#else
6185	VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
6186	VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
6187	VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
6188	VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
6189	VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
6190	VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
6191	VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
6192	VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
6193	VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
6194	VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
6195	VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
6196	#endif
6197
6198	VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6199	VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6200	VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6201	VBOXSTRICTRC iemMemFetchDataU32NoAc(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6202	VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6203	VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6204	VBOXSTRICTRC iemMemFetchDataU64NoAc(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6205	VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6206	VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6207	VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6208	VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6209	VBOXSTRICTRC iemMemFetchDataU128NoAc(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6210	VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6211	VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6212	VBOXSTRICTRC iemMemFetchDataU256NoAc(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6213	VBOXSTRICTRC iemMemFetchDataU256AlignedAvx(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6214	VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
6215	RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
6216	#ifdef IEM_WITH_SETJMP
6217	uint8_t iemMemFetchDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6218	uint16_t iemMemFetchDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6219	uint32_t iemMemFetchDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6220	uint32_t iemMemFetchDataU32NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6221	uint32_t iemMemFlatFetchDataU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6222	uint64_t iemMemFetchDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6223	uint64_t iemMemFetchDataU64NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6224	uint64_t iemMemFetchDataU64AlignedU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6225	void iemMemFetchDataR80SafeJmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6226	void iemMemFetchDataD80SafeJmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6227	void iemMemFetchDataU128SafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6228	void iemMemFetchDataU128NoAcSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6229	void iemMemFetchDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6230	void iemMemFetchDataU256SafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6231	void iemMemFetchDataU256NoAcSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6232	void iemMemFetchDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6233	# if 0 /* these are inlined now */
6234	uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6235	uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6236	uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6237	uint32_t iemMemFlatFetchDataU32Jmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6238	uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6239	uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6240	void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6241	void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6242	void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6243	void iemMemFetchDataU128NoAcJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6244	void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6245	void iemMemFetchDataU256NoAcJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6246	void iemMemFetchDataU256AlignedAvxJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6247	# endif
6248	void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6249	#endif
6250
6251	VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6252	VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6253	VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6254	VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6255	VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
6256
6257	VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
6258	VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
6259	VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
6260	VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
6261	VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
6262	VBOXSTRICTRC iemMemStoreDataU128NoAc(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
6263	VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
6264	VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
6265	VBOXSTRICTRC iemMemStoreDataU256NoAc(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
6266	VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
6267	VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6268	#ifdef IEM_WITH_SETJMP
6269	void iemMemStoreDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
6270	void iemMemStoreDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
6271	void iemMemStoreDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
6272	void iemMemStoreDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
6273	void iemMemStoreDataU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
6274	void iemMemStoreDataU128NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U pu128Value) IEM_NOEXCEPT_MAY_LONGJMP;
6275	void iemMemStoreDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U pu128Value) IEM_NOEXCEPT_MAY_LONGJMP;
6276	void iemMemStoreDataU256SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
6277	void iemMemStoreDataU256NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
6278	void iemMemStoreDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
6279	void iemMemStoreDataR80SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTFLOAT80U pr80Value) IEM_NOEXCEPT_MAY_LONGJMP;
6280	void iemMemStoreDataD80SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTPBCD80U pd80Value) IEM_NOEXCEPT_MAY_LONGJMP;
6281	#if 0
6282	void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
6283	void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
6284	void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
6285	void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
6286	void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
6287	void iemMemStoreDataNoAcU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
6288	void iemMemStoreDataU256NoAcJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
6289	void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
6290	#endif
6291	void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
6292	void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
6293	#endif
6294
6295	#ifdef IEM_WITH_SETJMP
6296	uint8_t iemMemMapDataU8RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6297	uint8_t iemMemMapDataU8AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6298	uint8_t iemMemMapDataU8WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6299	uint8_t const iemMemMapDataU8RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6300	uint16_t iemMemMapDataU16RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6301	uint16_t iemMemMapDataU16AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6302	uint16_t iemMemMapDataU16WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6303	uint16_t const iemMemMapDataU16RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6304	uint32_t iemMemMapDataU32RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6305	uint32_t iemMemMapDataU32AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6306	uint32_t iemMemMapDataU32WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6307	uint32_t const iemMemMapDataU32RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6308	uint64_t iemMemMapDataU64RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6309	uint64_t iemMemMapDataU64AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6310	uint64_t iemMemMapDataU64WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6311	uint64_t const iemMemMapDataU64RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6312	PRTFLOAT80U iemMemMapDataR80RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6313	PRTFLOAT80U iemMemMapDataR80WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6314	PCRTFLOAT80U iemMemMapDataR80RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6315	PRTPBCD80U iemMemMapDataD80RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6316	PRTPBCD80U iemMemMapDataD80WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6317	PCRTPBCD80U iemMemMapDataD80RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6318	PRTUINT128U iemMemMapDataU128RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6319	PRTUINT128U iemMemMapDataU128AtSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6320	PRTUINT128U iemMemMapDataU128WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6321	PCRTUINT128U iemMemMapDataU128RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6322
6323	void iemMemCommitAndUnmapJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
6324	void iemMemCommitAndUnmapRwSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
6325	void iemMemCommitAndUnmapAtSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
6326	void iemMemCommitAndUnmapWoSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
6327	void iemMemCommitAndUnmapRoSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
6328	void iemMemRollbackAndUnmapWoSafe(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
6329	#endif
6330
6331	VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
6332	void *ppvMem, uint8_t pbUnmapInfo, uint64_t *puNewRsp) RT_NOEXCEPT;
6333	VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, uint8_t bUnmapInfo, uint64_t uNewRsp) RT_NOEXCEPT;
6334	VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
6335	VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
6336	VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
6337	VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6338	VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6339	VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6340	VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
6341	VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
6342	void const *ppvMem, uint8_t pbUnmapInfo, uint64_t *puNewRsp) RT_NOEXCEPT;
6343	VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t off, size_t cbMem,
6344	void const *ppvMem, uint8_t pbUnmapInfo, uint64_t uCurNewRsp) RT_NOEXCEPT;
6345	VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
6346	VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
6347	VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
6348	VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
6349	VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6350	VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6351	VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6352
6353	#ifdef IEM_WITH_SETJMP
6354	void iemMemStackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6355	void iemMemStackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6356	void iemMemStackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6357	void iemMemStackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6358	void iemMemStackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6359	void iemMemStackPopGRegU32SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6360	void iemMemStackPopGRegU64SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6361
6362	void iemMemFlat32StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6363	void iemMemFlat32StackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6364	void iemMemFlat32StackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6365	void iemMemFlat32StackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6366	void iemMemFlat32StackPopGRegU32SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6367
6368	void iemMemFlat64StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6369	void iemMemFlat64StackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6370	void iemMemFlat64StackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6371	void iemMemFlat64StackPopGRegU64SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6372
6373	void iemMemStoreStackU16SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6374	void iemMemStoreStackU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6375	void iemMemStoreStackU32SRegSafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6376	void iemMemStoreStackU64SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6377
6378	uint16_t iemMemFetchStackU16SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6379	uint32_t iemMemFetchStackU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6380	uint64_t iemMemFetchStackU64SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6381
6382	#endif
6383
6384	/** @} */
6385
6386	/** @name IEMAllCImpl.cpp
6387	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
6388	* @{ */
6389	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem16, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6390	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem32, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6391	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem64, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6392	IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
6393	IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
6394	IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
6395	IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
6396	IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
6397	IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
6398	IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
6399	IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
6400	typedef IEM_CIMPL_DECL_TYPE_3(FNIEMCIMPLFARBRANCH, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
6401	typedef FNIEMCIMPLFARBRANCH *PFNIEMCIMPLFARBRANCH;
6402	IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
6403	IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
6404	IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
6405	IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
6406	IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
6407	IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
6408	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
6409	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
6410	IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
6411	IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
6412	IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
6413	IEM_CIMPL_PROTO_0(iemCImpl_syscall);
6414	IEM_CIMPL_PROTO_1(iemCImpl_sysret, IEMMODE, enmEffOpSize);
6415	IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
6416	IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
6417	IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
6418	IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
6419	IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
6420	IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
6421	IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
6422	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
6423	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
6424	IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
6425	IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6426	IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
6427	IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6428	IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
6429	IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
6430	IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6431	IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
6432	IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
6433	IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6434	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
6435	IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
6436	IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6437	IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
6438	IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
6439	IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
6440	IEM_CIMPL_PROTO_0(iemCImpl_clts);
6441	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
6442	IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
6443	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
6444	IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
6445	IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
6446	IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
6447	IEM_CIMPL_PROTO_0(iemCImpl_invd);
6448	IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
6449	IEM_CIMPL_PROTO_0(iemCImpl_rsm);
6450	IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
6451	IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
6452	IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
6453	IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
6454	IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
6455	IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
6456	IEM_CIMPL_PROTO_2(iemCImpl_in_eAX_DX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
6457	IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
6458	IEM_CIMPL_PROTO_2(iemCImpl_out_DX_eAX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
6459	IEM_CIMPL_PROTO_0(iemCImpl_cli);
6460	IEM_CIMPL_PROTO_0(iemCImpl_sti);
6461	IEM_CIMPL_PROTO_0(iemCImpl_hlt);
6462	IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
6463	IEM_CIMPL_PROTO_0(iemCImpl_mwait);
6464	IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
6465	IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
6466	IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
6467	IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
6468	IEM_CIMPL_PROTO_0(iemCImpl_daa);
6469	IEM_CIMPL_PROTO_0(iemCImpl_das);
6470	IEM_CIMPL_PROTO_0(iemCImpl_aaa);
6471	IEM_CIMPL_PROTO_0(iemCImpl_aas);
6472	IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
6473	IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
6474	IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
6475	IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
6476	IEM_CIMPL_PROTO_5(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
6477	PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags, uint8_t, bUnmapInfo);
6478	IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6479	IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
6480	IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
6481	IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
6482	IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
6483	IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
6484	IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6485	IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6486	IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6487	IEM_CIMPL_PROTO_2(iemCImpl_vldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6488	IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6489	IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6490	IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6491	IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6492	IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
6493	IEM_CIMPL_PROTO_2(iemCImpl_fxch_underflow, uint8_t, iStReg, uint16_t, uFpuOpcode);
6494	IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, bool, fUCmp, uint32_t, uPopAndFpuOpcode);
6495	IEM_CIMPL_PROTO_2(iemCImpl_rdseed, uint8_t, iReg, IEMMODE, enmEffOpSize);
6496	IEM_CIMPL_PROTO_2(iemCImpl_rdrand, uint8_t, iReg, IEMMODE, enmEffOpSize);
6497	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6498	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6499	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6500	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6501	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6502	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6503	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6504	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6505	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6506	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6507	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6508	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6509	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6510	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6511	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6512	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6513	IEM_CIMPL_PROTO_2(iemCImpl_vpgather_worker_xx, uint32_t, u32PackedArgs, uint32_t, u32Disp);
6514
6515	/** @} */
6516
6517	/** @name IEMAllCImplStrInstr.cpp.h
6518	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
6519	* -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
6520	* @{ */
6521	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
6522	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
6523	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
6524	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
6525	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
6526	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
6527	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
6528	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
6529	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
6530	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6531	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6532
6533	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
6534	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
6535	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
6536	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
6537	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
6538	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
6539	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
6540	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
6541	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
6542	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6543	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6544
6545	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
6546	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
6547	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
6548	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
6549	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
6550	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
6551	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
6552	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
6553	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
6554	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6555	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6556
6557
6558	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
6559	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
6560	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
6561	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
6562	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
6563	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
6564	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
6565	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
6566	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
6567	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6568	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6569
6570	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
6571	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
6572	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
6573	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
6574	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
6575	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
6576	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
6577	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
6578	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
6579	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6580	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6581
6582	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
6583	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
6584	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
6585	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
6586	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
6587	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
6588	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
6589	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
6590	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
6591	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6592	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6593
6594	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
6595	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
6596	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
6597	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
6598	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
6599	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
6600	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
6601	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
6602	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
6603	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6604	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6605
6606
6607	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
6608	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
6609	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
6610	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
6611	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
6612	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
6613	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
6614	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
6615	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
6616	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6617	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6618
6619	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
6620	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
6621	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
6622	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
6623	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
6624	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
6625	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
6626	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
6627	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
6628	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6629	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6630
6631	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
6632	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
6633	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
6634	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
6635	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
6636	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
6637	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
6638	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
6639	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
6640	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6641	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6642
6643	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
6644	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
6645	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
6646	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
6647	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
6648	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
6649	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
6650	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
6651	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
6652	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6653	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6654	/** @} */
6655
6656	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6657	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
6658	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
6659	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
6660	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
6661	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
6662	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
6663	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALKFAST pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
6664	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
6665	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
6666	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
6667	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
6668	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
6669	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
6670	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6671	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6672	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6673	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6674	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6675	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6676	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
6677	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
6678	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
6679	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
6680	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
6681	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
6682	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
6683	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
6684	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
6685	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
6686	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
6687	IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
6688	IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
6689	IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
6690	IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
6691	IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6692	IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6693	IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6694	IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
6695	IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
6696	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
6697	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint64_t *, pu32Dst, uint32_t, u32VmcsField);
6698	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
6699	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
6700	IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
6701	IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
6702	IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
6703	#endif
6704
6705	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
6706	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
6707	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
6708	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
6709	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
6710	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite, uint8_t cbInstr) RT_NOEXCEPT;
6711	IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
6712	IEM_CIMPL_PROTO_0(iemCImpl_vmload);
6713	IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
6714	IEM_CIMPL_PROTO_0(iemCImpl_clgi);
6715	IEM_CIMPL_PROTO_0(iemCImpl_stgi);
6716	IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
6717	IEM_CIMPL_PROTO_0(iemCImpl_skinit);
6718	IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
6719	#endif
6720
6721	IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
6722	IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
6723	IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
6724
6725	extern const PFNIEMOP g_apfnIemInterpretOnlyOneByteMap[256];
6726	extern const PFNIEMOP g_apfnIemInterpretOnlyTwoByteMap[1024];
6727	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f3a[1024];
6728	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f38[1024];
6729	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap1[1024];
6730	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap2[1024];
6731	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap3[1024];
6732
6733	/*
6734	* Recompiler related stuff.
6735	*/
6736	extern const PFNIEMOP g_apfnIemThreadedRecompilerOneByteMap[256];
6737	extern const PFNIEMOP g_apfnIemThreadedRecompilerTwoByteMap[1024];
6738	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f3a[1024];
6739	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f38[1024];
6740	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap1[1024];
6741	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap2[1024];
6742	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap3[1024];
6743
6744	DECLCALLBACK(int) iemTbInit(PVMCC pVM, uint32_t cInitialTbs, uint32_t cMaxTbs,
6745	uint64_t cbInitialExec, uint64_t cbMaxExec, uint32_t cbChunkExec);
6746	void iemThreadedTbObsolete(PVMCPUCC pVCpu, PIEMTB pTb, bool fSafeToFree);
6747	DECLHIDDEN(void) iemTbAllocatorFree(PVMCPUCC pVCpu, PIEMTB pTb);
6748	void iemTbAllocatorProcessDelayedFrees(PVMCPUCC pVCpu, PIEMTBALLOCATOR pTbAllocator);
6749	void iemTbAllocatorFreeupNativeSpace(PVMCPUCC pVCpu, uint32_t cNeededInstrs);
6750	DECLHIDDEN(const char ) iemTbFlagsToString(uint32_t fFlags, char pszBuf, size_t cbBuf) RT_NOEXCEPT;
6751	DECLHIDDEN(void) iemThreadedDisassembleTb(PCIEMTB pTb, PCDBGFINFOHLP pHlp) RT_NOEXCEPT;
6752
6753
6754	/** @todo FNIEMTHREADEDFUNC and friends may need more work... */
6755	#if defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
6756	typedef VBOXSTRICTRC /__attribute__((__nothrow__))/ FNIEMTHREADEDFUNC(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
6757	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
6758	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
6759	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
6760	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
6761	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
6762
6763	#else
6764	typedef VBOXSTRICTRC (FNIEMTHREADEDFUNC)(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
6765	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
6766	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
6767	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
6768	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
6769	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
6770	#endif
6771
6772
6773	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_Nop);
6774	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_LogCpuState);
6775
6776	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_DeferToCImpl0);
6777
6778	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckIrq);
6779	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckMode);
6780	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckHwInstrBps);
6781	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLim);
6782
6783	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodes);
6784	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodes);
6785	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesConsiderCsLim);
6786
6787	/* Branching: */
6788	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndPcAndOpcodes);
6789	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodes);
6790	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodesConsiderCsLim);
6791
6792	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesLoadingTlb);
6793	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlb);
6794	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlbConsiderCsLim);
6795
6796	/* Natural page crossing: */
6797	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesAcrossPageLoadingTlb);
6798	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlb);
6799	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlbConsiderCsLim);
6800
6801	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNextPageLoadingTlb);
6802	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlb);
6803	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlbConsiderCsLim);
6804
6805	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNewPageLoadingTlb);
6806	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlb);
6807	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlbConsiderCsLim);
6808
6809	bool iemThreadedCompileEmitIrqCheckBefore(PVMCPUCC pVCpu, PIEMTB pTb);
6810	bool iemThreadedCompileBeginEmitCallsComplications(PVMCPUCC pVCpu, PIEMTB pTb);
6811
6812	/* Native recompiler public bits: */
6813
6814	DECLHIDDEN(PIEMTB) iemNativeRecompile(PVMCPUCC pVCpu, PIEMTB pTb) RT_NOEXCEPT;
6815	DECLHIDDEN(void) iemNativeDisassembleTb(PVMCPU pVCpu, PCIEMTB pTb, PCDBGFINFOHLP pHlp) RT_NOEXCEPT;
6816	int iemExecMemAllocatorInit(PVMCPU pVCpu, uint64_t cbMax, uint64_t cbInitial, uint32_t cbChunk) RT_NOEXCEPT;
6817	DECLHIDDEN(PIEMNATIVEINSTR) iemExecMemAllocatorAlloc(PVMCPU pVCpu, uint32_t cbReq, PIEMTB pTb, PIEMNATIVEINSTR *ppaExec,
6818	struct IEMNATIVEPERCHUNKCTX const **ppChunkCtx) RT_NOEXCEPT;
6819	DECLHIDDEN(PIEMNATIVEINSTR) iemExecMemAllocatorAllocFromChunk(PVMCPU pVCpu, uint32_t idxChunk, uint32_t cbReq,
6820	PIEMNATIVEINSTR *ppaExec);
6821	DECLHIDDEN(void) iemExecMemAllocatorReadyForUse(PVMCPUCC pVCpu, void *pv, size_t cb) RT_NOEXCEPT;
6822	void iemExecMemAllocatorFree(PVMCPU pVCpu, void *pv, size_t cb) RT_NOEXCEPT;
6823	DECLASM(DECL_NO_RETURN(void)) iemNativeTbLongJmp(void *pvFramePointer, int rc) RT_NOEXCEPT;
6824	DECLHIDDEN(struct IEMNATIVEPERCHUNKCTX const *) iemExecMemGetTbChunkCtx(PVMCPU pVCpu, PCIEMTB pTb);
6825	DECLHIDDEN(struct IEMNATIVEPERCHUNKCTX const *) iemNativeRecompileAttachExecMemChunkCtx(PVMCPU pVCpu, uint32_t idxChunk);
6826
6827	/** Packed 32-bit argument for iemCImpl_vpgather_worker_xx. */
6828	typedef union IEMGATHERARGS
6829	{
6830	/** Integer view. */
6831	uint32_t u;
6832	/** Bitfield view. */
6833	struct
6834	{
6835	uint32_t iYRegDst : 4; /*< 0 - XMM or YMM register number (destination) /
6836	uint32_t iYRegIdc : 4; /*< 4 - XMM or YMM register number (indices) /
6837	uint32_t iYRegMsk : 4; /*< 8 - XMM or YMM register number (mask) /
6838	uint32_t iGRegBase : 4; /*< 12 - general register number (base ptr) /
6839	uint32_t iScale : 2; /*< 16 - scale factor (1/2/4/8) /
6840	uint32_t enmEffOpSize : 2; /*< 18 - operand size (16/32/64/--) /
6841	uint32_t enmEffAddrMode : 2; /*< 20 - addressing mode (16/32/64/--) /
6842	uint32_t iEffSeg : 3; /*< 22 - effective segment (ES/CS/SS/DS/FS/GS) /
6843	uint32_t fVex256 : 1; /*< 25 - overall instruction width (128/256 bits) /
6844	uint32_t fIdxQword : 1; /*< 26 - individual index width (4/8 bytes) /
6845	uint32_t fValQword : 1; /*< 27 - individual value width (4/8 bytes) /
6846	} s;
6847	} IEMGATHERARGS;
6848	AssertCompileSize(IEMGATHERARGS, sizeof(uint32_t));
6849
6850	#endif /* !RT_IN_ASSEMBLER - ASM-NOINC-END */
6851
6852
6853	/** @} */
6854
6855	RT_C_DECLS_END
6856
6857	/* ASM-INC: %include "IEMInternalStruct.mac" */
6858
6859	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
6860

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