IEMInternal.h@ 105579

最後變更在這個檔案從105579是 105579,由 vboxsync 提交於 8 月前
VMM/IEM: Fixed another bug in the large page TLB invalidation code which caused it to only evict half of the pages. More TLB tracing event work. bugref:10727
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1	/* $Id: IEMInternal.h 105579 2024-08-02 21:10:41Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.alldomusa.eu.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
29	#define VMM_INCLUDED_SRC_include_IEMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#ifndef RT_IN_ASSEMBLER
35	# include <VBox/vmm/cpum.h>
36	# include <VBox/vmm/iem.h>
37	# include <VBox/vmm/pgm.h>
38	# include <VBox/vmm/stam.h>
39	# include <VBox/param.h>
40
41	# include <iprt/setjmp-without-sigmask.h>
42	# include <iprt/list.h>
43	#endif /* !RT_IN_ASSEMBLER */
44
45
46	RT_C_DECLS_BEGIN
47
48
49	/** @defgroup grp_iem_int Internals
50	* @ingroup grp_iem
51	* @internal
52	* @{
53	*/
54
55	/* Make doxygen happy w/o overcomplicating the #if checks. */
56	#ifdef DOXYGEN_RUNNING
57	# define IEM_WITH_THROW_CATCH
58	# define VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
59	#endif
60
61	/** For expanding symbol in slickedit and other products tagging and
62	* crossreferencing IEM symbols. */
63	#ifndef IEM_STATIC
64	# define IEM_STATIC static
65	#endif
66
67	/** @def IEM_WITH_SETJMP
68	* Enables alternative status code handling using setjmps.
69	*
70	* This adds a bit of expense via the setjmp() call since it saves all the
71	* non-volatile registers. However, it eliminates return code checks and allows
72	* for more optimal return value passing (return regs instead of stack buffer).
73	*/
74	#if defined(DOXYGEN_RUNNING) \|\| defined(RT_OS_WINDOWS) \|\| 1
75	# define IEM_WITH_SETJMP
76	#endif
77
78	/** @def IEM_WITH_THROW_CATCH
79	* Enables using C++ throw/catch as an alternative to setjmp/longjmp in user
80	* mode code when IEM_WITH_SETJMP is in effect.
81	*
82	* With GCC 11.3.1 and code TLB on linux, using throw/catch instead of
83	* setjmp/long resulted in bs2-test-1 running 3.00% faster and all but on test
84	* result value improving by more than 1%. (Best out of three.)
85	*
86	* With Visual C++ 2019 and code TLB on windows, using throw/catch instead of
87	* setjmp/long resulted in bs2-test-1 running 3.68% faster and all but some of
88	* the MMIO and CPUID tests ran noticeably faster. Variation is greater than on
89	* Linux, but it should be quite a bit faster for normal code.
90	*/
91	#if defined(__cplusplus) && defined(IEM_WITH_SETJMP) && defined(IN_RING3) && (defined(__GNUC__) \|\| defined(_MSC_VER)) /* ASM-NOINC-START */
92	# define IEM_WITH_THROW_CATCH
93	#endif /ASM-NOINC-END/
94
95	/** @def IEMNATIVE_WITH_DELAYED_PC_UPDATING
96	* Enables the delayed PC updating optimization (see @bugref{10373}).
97	*/
98	#if defined(DOXYGEN_RUNNING) \|\| 1
99	# define IEMNATIVE_WITH_DELAYED_PC_UPDATING
100	#endif
101
102	/** Enables the SIMD register allocator @bugref{10614}. */
103	#if defined(DOXYGEN_RUNNING) \|\| 1
104	# define IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
105	#endif
106	/** Enables access to even callee saved registers. */
107	//# define IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS
108
109	#if defined(DOXYGEN_RUNNING) \|\| 1
110	/** @def IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
111	* Delay the writeback or dirty registers as long as possible. */
112	# define IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
113	#endif
114
115	/** @def IEM_WITH_TLB_STATISTICS
116	* Enables all TLB statistics. */
117	#if defined(VBOX_WITH_STATISTICS) \|\| defined(DOXYGEN_RUNNING)
118	# define IEM_WITH_TLB_STATISTICS
119	#endif
120
121	/** @def IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS
122	* Enable this to use native emitters for certain SIMD FP operations. */
123	#if 1 \|\| defined(DOXYGEN_RUNNING)
124	# define IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS
125	#endif
126
127	/** @def VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
128	* Enables a quicker alternative to throw/longjmp for IEM_DO_LONGJMP when
129	* executing native translation blocks.
130	*
131	* This exploits the fact that we save all non-volatile registers in the TB
132	* prologue and thus just need to do the same as the TB epilogue to get the
133	* effect of a longjmp/throw. Since MSC marks XMM6 thru XMM15 as
134	* non-volatile (and does something even more crazy for ARM), this probably
135	* won't work reliably on Windows. */
136	#ifdef RT_ARCH_ARM64
137	# ifndef RT_OS_WINDOWS
138	# define VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
139	# endif
140	#endif
141	/* ASM-NOINC-START */
142	#ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
143	# if !defined(IN_RING3) \
144	\|\| !defined(VBOX_WITH_IEM_RECOMPILER) \
145	\|\| !defined(VBOX_WITH_IEM_NATIVE_RECOMPILER)
146	# undef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
147	# elif defined(RT_OS_WINDOWS)
148	# pragma message("VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP is not safe to use on windows")
149	# endif
150	#endif
151
152
153	/** @def IEM_DO_LONGJMP
154	*
155	* Wrapper around longjmp / throw.
156	*
157	* @param a_pVCpu The CPU handle.
158	* @param a_rc The status code jump back with / throw.
159	*/
160	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
161	# ifdef IEM_WITH_THROW_CATCH
162	# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
163	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) do { \
164	if ((a_pVCpu)->iem.s.pvTbFramePointerR3) \
165	iemNativeTbLongJmp((a_pVCpu)->iem.s.pvTbFramePointerR3, (a_rc)); \
166	throw int(a_rc); \
167	} while (0)
168	# else
169	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) throw int(a_rc)
170	# endif
171	# else
172	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
173	# endif
174	#endif
175
176	/** For use with IEM function that may do a longjmp (when enabled).
177	*
178	* Visual C++ has trouble longjmp'ing from/over functions with the noexcept
179	* attribute. So, we indicate that function that may be part of a longjmp may
180	* throw "exceptions" and that the compiler should definitely not generate and
181	* std::terminate calling unwind code.
182	*
183	* Here is one example of this ending in std::terminate:
184	* @code{.txt}
185	00 00000041`cadfda10 00007ffc`5d5a1f9f ucrtbase!abort+0x4e
186	01 00000041`cadfda40 00007ffc`57af229a ucrtbase!terminate+0x1f
187	02 00000041`cadfda70 00007ffb`eec91030 VCRUNTIME140!__std_terminate+0xa [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\ehhelpers.cpp @ 192]
188	03 00000041`cadfdaa0 00007ffb`eec92c6d VCRUNTIME140_1!_CallSettingFrame+0x20 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\handlers.asm @ 50]
189	04 00000041`cadfdad0 00007ffb`eec93ae5 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToState+0x241 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 1085]
190	05 00000041`cadfdc00 00007ffb`eec92258 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToEmptyState+0x2d [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 218]
191	06 00000041`cadfdc30 00007ffb`eec940e9 VCRUNTIME140_1!__InternalCxxFrameHandler<__FrameHandler4>+0x194 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 304]
192	07 00000041`cadfdcd0 00007ffc`5f9f249f VCRUNTIME140_1!__CxxFrameHandler4+0xa9 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 290]
193	08 00000041`cadfdd40 00007ffc`5f980939 ntdll!RtlpExecuteHandlerForUnwind+0xf
194	09 00000041`cadfdd70 00007ffc`5f9a0edd ntdll!RtlUnwindEx+0x339
195	0a 00000041`cadfe490 00007ffc`57aff976 ntdll!RtlUnwind+0xcd
196	0b 00000041`cadfea00 00007ffb`e1b5de01 VCRUNTIME140!__longjmp_internal+0xe6 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\longjmp.asm @ 140]
197	0c (Inline Function) --------`-------- VBoxVMM!iemOpcodeGetNextU8SlowJmp+0x95 [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 1155]
198	0d 00000041`cadfea50 00007ffb`e1b60f6b VBoxVMM!iemOpcodeGetNextU8Jmp+0xc1 [L:\vbox-intern\src\VBox\VMM\include\IEMInline.h @ 402]
199	0e 00000041`cadfea90 00007ffb`e1cc6201 VBoxVMM!IEMExecForExits+0xdb [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 10185]
200	0f 00000041`cadfec70 00007ffb`e1d0df8d VBoxVMM!EMHistoryExec+0x4f1 [L:\vbox-intern\src\VBox\VMM\VMMAll\EMAll.cpp @ 452]
201	10 00000041`cadfed60 00007ffb`e1d0d4c0 VBoxVMM!nemR3WinHandleExitCpuId+0x79d [L:\vbox-intern\src\VBox\VMM\VMMAll\NEMAllNativeTemplate-win.cpp.h @ 1829] @encode
202	@endcode
203	*
204	* @see https://developercommunity.visualstudio.com/t/fragile-behavior-of-longjmp-called-from-noexcept-f/1532859
205	*/
206	#if defined(IEM_WITH_SETJMP) && (defined(_MSC_VER) \|\| defined(IEM_WITH_THROW_CATCH))
207	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT_EX(false)
208	#else
209	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT
210	#endif
211	/* ASM-NOINC-END */
212
213	#define IEM_IMPLEMENTS_TASKSWITCH
214
215	/** @def IEM_WITH_3DNOW
216	* Includes the 3DNow decoding. */
217	#if !defined(IEM_WITH_3DNOW) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
218	# ifndef IEM_WITHOUT_3DNOW
219	# define IEM_WITH_3DNOW
220	# endif
221	#endif
222
223	/** @def IEM_WITH_THREE_0F_38
224	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
225	#if !defined(IEM_WITH_THREE_0F_38) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
226	# ifndef IEM_WITHOUT_THREE_0F_38
227	# define IEM_WITH_THREE_0F_38
228	# endif
229	#endif
230
231	/** @def IEM_WITH_THREE_0F_3A
232	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
233	#if !defined(IEM_WITH_THREE_0F_3A) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
234	# ifndef IEM_WITHOUT_THREE_0F_3A
235	# define IEM_WITH_THREE_0F_3A
236	# endif
237	#endif
238
239	/** @def IEM_WITH_VEX
240	* Includes the VEX decoding. */
241	#if !defined(IEM_WITH_VEX) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
242	# ifndef IEM_WITHOUT_VEX
243	# define IEM_WITH_VEX
244	# endif
245	#endif
246
247	/** @def IEM_CFG_TARGET_CPU
248	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
249	*
250	* By default we allow this to be configured by the user via the
251	* CPUM/GuestCpuName config string, but this comes at a slight cost during
252	* decoding. So, for applications of this code where there is no need to
253	* be dynamic wrt target CPU, just modify this define.
254	*/
255	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
256	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
257	#endif
258
259	//#define IEM_WITH_CODE_TLB // - work in progress
260	//#define IEM_WITH_DATA_TLB // - work in progress
261
262
263	/** @def IEM_USE_UNALIGNED_DATA_ACCESS
264	* Use unaligned accesses instead of elaborate byte assembly. */
265	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(DOXYGEN_RUNNING) /ASM-NOINC/
266	# define IEM_USE_UNALIGNED_DATA_ACCESS
267	#endif /ASM-NOINC/
268
269	//#define IEM_LOG_MEMORY_WRITES
270
271
272
273	#ifndef RT_IN_ASSEMBLER /* ASM-NOINC-START - the rest of the file */
274
275	# if !defined(IEM_WITHOUT_INSTRUCTION_STATS) && !defined(DOXYGEN_RUNNING)
276	/** Instruction statistics. */
277	typedef struct IEMINSTRSTATS
278	{
279	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
280	# include "IEMInstructionStatisticsTmpl.h"
281	# undef IEM_DO_INSTR_STAT
282	} IEMINSTRSTATS;
283	#else
284	struct IEMINSTRSTATS;
285	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
286	#endif
287	/** Pointer to IEM instruction statistics. */
288	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
289
290
291	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
292	* @{ */
293	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
294	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
295	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
296	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
297	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
298	/** Selects the right variant from a_aArray.
299	* pVCpu is implicit in the caller context. */
300	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
301	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
302	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
303	* be used because the host CPU does not support the operation. */
304	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
305	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
306	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
307	* array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
308	* into the two.
309	* @sa IEM_SELECT_NATIVE_OR_FALLBACK */
310	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
311	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
312	(a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
313	#else
314	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
315	(a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
316	#endif
317	/** @} */
318
319	/**
320	* Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
321	* indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
322	*
323	* On non-x86 hosts, this will shortcut to the fallback w/o checking the
324	* indicator.
325	*
326	* @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
327	*/
328	#if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
329	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
330	(g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
331	#else
332	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
333	#endif
334
335
336	/**
337	* Branch types.
338	*/
339	typedef enum IEMBRANCH
340	{
341	IEMBRANCH_JUMP = 1,
342	IEMBRANCH_CALL,
343	IEMBRANCH_TRAP,
344	IEMBRANCH_SOFTWARE_INT,
345	IEMBRANCH_HARDWARE_INT
346	} IEMBRANCH;
347	AssertCompileSize(IEMBRANCH, 4);
348
349
350	/**
351	* INT instruction types.
352	*/
353	typedef enum IEMINT
354	{
355	/** INT n instruction (opcode 0xcd imm). */
356	IEMINT_INTN = 0,
357	/** Single byte INT3 instruction (opcode 0xcc). */
358	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
359	/** Single byte INTO instruction (opcode 0xce). */
360	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
361	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
362	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
363	} IEMINT;
364	AssertCompileSize(IEMINT, 4);
365
366
367	/**
368	* A FPU result.
369	*/
370	typedef struct IEMFPURESULT
371	{
372	/** The output value. */
373	RTFLOAT80U r80Result;
374	/** The output status. */
375	uint16_t FSW;
376	} IEMFPURESULT;
377	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
378	/** Pointer to a FPU result. */
379	typedef IEMFPURESULT *PIEMFPURESULT;
380	/** Pointer to a const FPU result. */
381	typedef IEMFPURESULT const *PCIEMFPURESULT;
382
383
384	/**
385	* A FPU result consisting of two output values and FSW.
386	*/
387	typedef struct IEMFPURESULTTWO
388	{
389	/** The first output value. */
390	RTFLOAT80U r80Result1;
391	/** The output status. */
392	uint16_t FSW;
393	/** The second output value. */
394	RTFLOAT80U r80Result2;
395	} IEMFPURESULTTWO;
396	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
397	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
398	/** Pointer to a FPU result consisting of two output values and FSW. */
399	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
400	/** Pointer to a const FPU result consisting of two output values and FSW. */
401	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
402
403
404	/**
405	* IEM TLB entry.
406	*
407	* Lookup assembly:
408	* @code{.asm}
409	; Calculate tag.
410	mov rax, [VA]
411	shl rax, 16
412	shr rax, 16 + X86_PAGE_SHIFT
413	or rax, [uTlbRevision]
414
415	; Do indexing.
416	movzx ecx, al
417	lea rcx, [pTlbEntries + rcx]
418
419	; Check tag.
420	cmp [rcx + IEMTLBENTRY.uTag], rax
421	jne .TlbMiss
422
423	; Check access.
424	mov rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
425	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
426	cmp rax, [uTlbPhysRev]
427	jne .TlbMiss
428
429	; Calc address and we're done.
430	mov eax, X86_PAGE_OFFSET_MASK
431	and eax, [VA]
432	or rax, [rcx + IEMTLBENTRY.pMappingR3]
433	%ifdef VBOX_WITH_STATISTICS
434	inc qword [cTlbHits]
435	%endif
436	jmp .Done
437
438	.TlbMiss:
439	mov r8d, ACCESS_FLAGS
440	mov rdx, [VA]
441	mov rcx, [pVCpu]
442	call iemTlbTypeMiss
443	.Done:
444
445	@endcode
446	*
447	*/
448	typedef struct IEMTLBENTRY
449	{
450	/** The TLB entry tag.
451	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
452	* is ASSUMING a virtual address width of 48 bits.
453	*
454	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
455	*
456	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
457	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
458	* revision wraps around though, the tags needs to be zeroed.
459	*
460	* @note Try use SHRD instruction? After seeing
461	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
462	*
463	* @todo This will need to be reorganized for 57-bit wide virtual address and
464	* PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
465	* have to move the TLB entry versioning entirely to the
466	* fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
467	* 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
468	* consumed by PCID and ASID (12 + 6 = 18).
469	*/
470	uint64_t uTag;
471	/** Access flags and physical TLB revision.
472	*
473	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
474	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
475	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
476	* - Bit 3 - pgm phys/virt - not directly writable.
477	* - Bit 4 - pgm phys page - not directly readable.
478	* - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
479	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
480	* - Bit 7 - tlb entry - pMappingR3 member not valid.
481	* - Bits 63 thru 8 are used for the physical TLB revision number.
482	*
483	* We're using complemented bit meanings here because it makes it easy to check
484	* whether special action is required. For instance a user mode write access
485	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
486	* non-zero result would mean special handling needed because either it wasn't
487	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
488	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
489	* need to check any PTE flag.
490	*/
491	uint64_t fFlagsAndPhysRev;
492	/** The guest physical page address. */
493	uint64_t GCPhys;
494	/** Pointer to the ring-3 mapping. */
495	R3PTRTYPE(uint8_t *) pbMappingR3;
496	#if HC_ARCH_BITS == 32
497	uint32_t u32Padding1;
498	#endif
499	} IEMTLBENTRY;
500	AssertCompileSize(IEMTLBENTRY, 32);
501	/** Pointer to an IEM TLB entry. */
502	typedef IEMTLBENTRY *PIEMTLBENTRY;
503	/** Pointer to a const IEM TLB entry. */
504	typedef IEMTLBENTRY const *PCIEMTLBENTRY;
505
506	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
507	* @{ */
508	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
509	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
510	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
511	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
512	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
513	#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /*< Phys tables: Not accessed (need to be marked accessed). /
514	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
515	#define IEMTLBE_F_PT_LARGE_PAGE RT_BIT_64(7) /*< Page tables: Large 2 or 4 MiB page (for flushing). /
516	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(8) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
517	#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(9) /*< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). /
518	#define IEMTLBE_F_PG_CODE_PAGE RT_BIT_64(10) /*< Phys page: Code page. /
519	#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffff800) /*< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR /
520	/** @} */
521	AssertCompile(PGMIEMGCPHYS2PTR_F_NO_WRITE == IEMTLBE_F_PG_NO_WRITE);
522	AssertCompile(PGMIEMGCPHYS2PTR_F_NO_READ == IEMTLBE_F_PG_NO_READ);
523	AssertCompile(PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 == IEMTLBE_F_NO_MAPPINGR3);
524	AssertCompile(PGMIEMGCPHYS2PTR_F_UNASSIGNED == IEMTLBE_F_PG_UNASSIGNED);
525	AssertCompile(PGMIEMGCPHYS2PTR_F_CODE_PAGE == IEMTLBE_F_PG_CODE_PAGE);
526	AssertCompile(PGM_WALKINFO_BIG_PAGE == IEMTLBE_F_PT_LARGE_PAGE);
527	/** The bits set by PGMPhysIemGCPhys2PtrNoLock. */
528	#define IEMTLBE_GCPHYS2PTR_MASK ( PGMIEMGCPHYS2PTR_F_NO_WRITE \
529	\| PGMIEMGCPHYS2PTR_F_NO_READ \
530	\| PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 \
531	\| PGMIEMGCPHYS2PTR_F_UNASSIGNED \
532	\| PGMIEMGCPHYS2PTR_F_CODE_PAGE \
533	\| IEMTLBE_F_PHYS_REV )
534
535
536	/** The TLB size (power of two).
537	* We initially chose 256 because that way we can obtain the result directly
538	* from a 8-bit register without an additional AND instruction.
539	* See also @bugref{10687}. */
540	#if defined(RT_ARCH_AMD64)
541	# define IEMTLB_ENTRY_COUNT 256
542	# define IEMTLB_ENTRY_COUNT_AS_POWER_OF_TWO 8
543	#else
544	# define IEMTLB_ENTRY_COUNT 8192
545	# define IEMTLB_ENTRY_COUNT_AS_POWER_OF_TWO 13
546	#endif
547	AssertCompile(RT_BIT_32(IEMTLB_ENTRY_COUNT_AS_POWER_OF_TWO) == IEMTLB_ENTRY_COUNT);
548
549	/** TLB slot format spec (assumes uint32_t or unsigned value). */
550	#if IEMTLB_ENTRY_COUNT <= 0x100 / 2
551	# define IEMTLB_SLOT_FMT "%02x"
552	#elif IEMTLB_ENTRY_COUNT <= 0x1000 / 2
553	# define IEMTLB_SLOT_FMT "%03x"
554	#elif IEMTLB_ENTRY_COUNT <= 0x10000 / 2
555	# define IEMTLB_SLOT_FMT "%04x"
556	#else
557	# define IEMTLB_SLOT_FMT "%05x"
558	#endif
559
560
561	/**
562	* An IEM TLB.
563	*
564	* We've got two of these, one for data and one for instructions.
565	*/
566	typedef struct IEMTLB
567	{
568	/** The non-global TLB revision.
569	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
570	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
571	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
572	* (The revision zero indicates an invalid TLB entry.)
573	*
574	* The initial value is choosen to cause an early wraparound. */
575	uint64_t uTlbRevision;
576	/** The TLB physical address revision - shadow of PGM variable.
577	*
578	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
579	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
580	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
581	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
582	*
583	* The initial value is choosen to cause an early wraparound.
584	*
585	* @note This is placed between the two TLB revisions because we
586	* load it in pair with one or the other on arm64. */
587	uint64_t volatile uTlbPhysRev;
588	/** The global TLB revision.
589	* Same as uTlbRevision, but only increased for global flushes. */
590	uint64_t uTlbRevisionGlobal;
591
592	/** Large page tag range.
593	*
594	* This is used to avoid scanning a large page's worth of TLB entries for each
595	* INVLPG instruction, and only to do so iff we've loaded any and when the
596	* address is in this range. This is kept up to date when we loading new TLB
597	* entries.
598	*/
599	struct LARGEPAGERANGE
600	{
601	/** The lowest large page address tag, UINT64_MAX if none. */
602	uint64_t uFirstTag;
603	/** The highest large page address tag (with offset mask part set), 0 if none. */
604	uint64_t uLastTag;
605	}
606	/** Large page range for non-global pages. */
607	NonGlobalLargePageRange,
608	/** Large page range for global pages. */
609	GlobalLargePageRange;
610	/** Number of non-global entries for large pages loaded since last TLB flush. */
611	uint32_t cTlbNonGlobalLargePageCurLoads;
612	/** Number of global entries for large pages loaded since last TLB flush. */
613	uint32_t cTlbGlobalLargePageCurLoads;
614
615	/* Statistics: */
616
617	/** TLB hits in IEMAll.cpp code (IEM_WITH_TLB_STATISTICS only; both).
618	* @note For the data TLB this is only used in iemMemMap and and for direct (i.e.
619	* not via safe read/write path) calls to iemMemMapJmp. */
620	uint64_t cTlbCoreHits;
621	/** Safe read/write TLB hits in iemMemMapJmp (IEM_WITH_TLB_STATISTICS
622	* only; data tlb only). */
623	uint64_t cTlbSafeHits;
624	/** TLB hits in IEMAllMemRWTmplInline.cpp.h (data + IEM_WITH_TLB_STATISTICS only). */
625	uint64_t cTlbInlineCodeHits;
626
627	/** TLB misses in IEMAll.cpp code (both).
628	* @note For the data TLB this is only used in iemMemMap and for direct (i.e.
629	* not via safe read/write path) calls to iemMemMapJmp. So,
630	* for the data TLB this more like 'other misses', while for the code
631	* TLB is all misses. */
632	uint64_t cTlbCoreMisses;
633	/** Subset of cTlbCoreMisses that results in PTE.G=1 loads (odd entries). */
634	uint64_t cTlbCoreGlobalLoads;
635	/** Safe read/write TLB misses in iemMemMapJmp (so data only). */
636	uint64_t cTlbSafeMisses;
637	/** Subset of cTlbSafeMisses that results in PTE.G=1 loads (odd entries). */
638	uint64_t cTlbSafeGlobalLoads;
639	/** Safe read path taken (data only). */
640	uint64_t cTlbSafeReadPath;
641	/** Safe write path taken (data only). */
642	uint64_t cTlbSafeWritePath;
643
644	/** @name Details for native code TLB misses.
645	* @note These counts are included in the above counters (cTlbSafeReadPath,
646	* cTlbSafeWritePath, cTlbInlineCodeHits).
647	* @{ */
648	/** TLB misses in native code due to tag mismatch. */
649	STAMCOUNTER cTlbNativeMissTag;
650	/** TLB misses in native code due to flags or physical revision mismatch. */
651	STAMCOUNTER cTlbNativeMissFlagsAndPhysRev;
652	/** TLB misses in native code due to misaligned access. */
653	STAMCOUNTER cTlbNativeMissAlignment;
654	/** TLB misses in native code due to cross page access. */
655	uint32_t cTlbNativeMissCrossPage;
656	/** TLB misses in native code due to non-canonical address. */
657	uint32_t cTlbNativeMissNonCanonical;
658	/** @} */
659
660	/** Slow read path (code only). */
661	uint32_t cTlbSlowCodeReadPath;
662
663	/** Regular TLB flush count. */
664	uint32_t cTlsFlushes;
665	/** Global TLB flush count. */
666	uint32_t cTlsGlobalFlushes;
667	/** Revision rollovers. */
668	uint32_t cTlbRevisionRollovers;
669	/** Physical revision flushes. */
670	uint32_t cTlbPhysRevFlushes;
671	/** Physical revision rollovers. */
672	uint32_t cTlbPhysRevRollovers;
673
674	/uint32_t au32Padding[2];/
675
676	/** The TLB entries.
677	* Even entries are for PTE.G=0 and uses uTlbRevision.
678	* Odd entries are for PTE.G=1 and uses uTlbRevisionGlobal. */
679	IEMTLBENTRY aEntries[IEMTLB_ENTRY_COUNT * 2];
680	} IEMTLB;
681	AssertCompileSizeAlignment(IEMTLB, 64);
682	/** The width (in bits) of the address portion of the TLB tag. */
683	#define IEMTLB_TAG_ADDR_WIDTH 36
684	/** IEMTLB::uTlbRevision increment. */
685	#define IEMTLB_REVISION_INCR RT_BIT_64(IEMTLB_TAG_ADDR_WIDTH)
686	/** IEMTLB::uTlbRevision mask. */
687	#define IEMTLB_REVISION_MASK (~(RT_BIT_64(IEMTLB_TAG_ADDR_WIDTH) - 1))
688
689	/** IEMTLB::uTlbPhysRev increment.
690	* @sa IEMTLBE_F_PHYS_REV */
691	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(11)
692	AssertCompile(IEMTLBE_F_PHYS_REV == ~(IEMTLB_PHYS_REV_INCR - 1U));
693
694	/**
695	* Calculates the TLB tag for a virtual address but without TLB revision.
696	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
697	* @param a_GCPtr The virtual address. Must be RTGCPTR or same size or
698	* the clearing of the top 16 bits won't work (if 32-bit
699	* we'll end up with mostly zeros).
700	*/
701	#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
702	/**
703	* Converts a TLB tag value into a even TLB index.
704	* @returns Index into IEMTLB::aEntries.
705	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
706	*/
707	#if IEMTLB_ENTRY_COUNT == 256
708	# define IEMTLB_TAG_TO_EVEN_INDEX(a_uTag) ( (uint8_t)(a_uTag) * 2U )
709	#else
710	# define IEMTLB_TAG_TO_EVEN_INDEX(a_uTag) ( ((a_uTag) & (IEMTLB_ENTRY_COUNT - 1U)) * 2U )
711	AssertCompile(RT_IS_POWER_OF_TWO(IEMTLB_ENTRY_COUNT));
712	#endif
713	/**
714	* Converts a TLB tag value into an even TLB index.
715	* @returns Pointer into IEMTLB::aEntries corresponding to .
716	* @param a_pTlb The TLB.
717	* @param a_uTag Value returned by IEMTLB_CALC_TAG or
718	* IEMTLB_CALC_TAG_NO_REV.
719	*/
720	#define IEMTLB_TAG_TO_EVEN_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_EVEN_INDEX(a_uTag)] )
721
722	/** Converts a GC address to an even TLB index. */
723	#define IEMTLB_ADDR_TO_EVEN_INDEX(a_GCPtr) IEMTLB_TAG_TO_EVEN_INDEX(IEMTLB_CALC_TAG_NO_REV(a_GCPtr))
724
725
726	/** @def IEM_WITH_TLB_TRACE
727	* Enables the TLB tracing.
728	* Adjust buffer size in IEMR3Init. */
729	#if defined(DOXYGEN_RUNNING) \|\| 0
730	# define IEM_WITH_TLB_TRACE
731	#endif
732
733	#ifdef IEM_WITH_TLB_TRACE
734
735	/** TLB trace entry types. */
736	typedef enum : uint8_t
737	{
738	kIemTlbTraceType_Invalid,
739	kIemTlbTraceType_InvlPg,
740	kIemTlbTraceType_EvictSlot,
741	kIemTlbTraceType_LargeEvictSlot,
742	kIemTlbTraceType_LargeScan,
743	kIemTlbTraceType_Flush,
744	kIemTlbTraceType_FlushGlobal,
745	kIemTlbTraceType_Load,
746	kIemTlbTraceType_LoadGlobal,
747	kIemTlbTraceType_Load_Cr0,
748	kIemTlbTraceType_Load_Cr3,
749	kIemTlbTraceType_Load_Cr4,
750	kIemTlbTraceType_Load_Efer,
751	kIemTlbTraceType_Irq,
752	kIemTlbTraceType_Xcpt,
753	kIemTlbTraceType_IRet,
754	kIemTlbTraceType_Tb_Compile,
755	kIemTlbTraceType_Tb_Exec_Threaded,
756	kIemTlbTraceType_Tb_Exec_Native,
757	kIemTlbTraceType_User0,
758	kIemTlbTraceType_User1,
759	kIemTlbTraceType_User2,
760	kIemTlbTraceType_User3,
761	} IEMTLBTRACETYPE;
762
763	/** TLB trace entry. */
764	typedef struct IEMTLBTRACEENTRY
765	{
766	/** The flattened RIP for the event. */
767	uint64_t rip;
768	/** The event type. */
769	IEMTLBTRACETYPE enmType;
770	/** Byte parameter - typically used as 'bool fDataTlb'. */
771	uint8_t bParam;
772	/** 16-bit parameter value. */
773	uint16_t u16Param;
774	/** 32-bit parameter value. */
775	uint32_t u32Param;
776	/** 64-bit parameter value. */
777	uint64_t u64Param;
778	/** 64-bit parameter value. */
779	uint64_t u64Param2;
780	} IEMTLBTRACEENTRY;
781	AssertCompileSize(IEMTLBTRACEENTRY, 32);
782	/** Pointer to a TLB trace entry. */
783	typedef IEMTLBTRACEENTRY *PIEMTLBTRACEENTRY;
784	/** Pointer to a const TLB trace entry. */
785	typedef IEMTLBTRACEENTRY const *PCIEMTLBTRACEENTRY;
786	#endif /* !IEM_WITH_TLB_TRACE */
787
788	#if defined(IEM_WITH_TLB_TRACE) && defined(IN_RING3)
789	# define IEMTLBTRACE_INVLPG(a_pVCpu, a_GCPtr) \
790	iemTlbTrace(a_pVCpu, kIemTlbTraceType_InvlPg, a_GCPtr)
791	# define IEMTLBTRACE_EVICT_SLOT(a_pVCpu, a_GCPtrTag, a_GCPhys, a_idxSlot, a_fDataTlb) \
792	iemTlbTrace(a_pVCpu, kIemTlbTraceType_EvictSlot, a_GCPtrTag, a_GCPhys, a_fDataTlb, a_idxSlot)
793	# define IEMTLBTRACE_LARGE_EVICT_SLOT(a_pVCpu, a_GCPtrTag, a_GCPhys, a_idxSlot, a_fDataTlb) \
794	iemTlbTrace(a_pVCpu, kIemTlbTraceType_LargeEvictSlot, a_GCPtrTag, a_GCPhys, a_fDataTlb, a_idxSlot)
795	# define IEMTLBTRACE_LARGE_SCAN(a_pVCpu, a_fGlobal, a_fNonGlobal, a_fDataTlb) \
796	iemTlbTrace(a_pVCpu, kIemTlbTraceType_LargeScan, 0, 0, a_fDataTlb, (uint8_t)a_fGlobal \| ((uint8_t)a_fNonGlobal << 1))
797	# define IEMTLBTRACE_FLUSH(a_pVCpu, a_uRev, a_fDataTlb) \
798	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Flush, a_uRev, 0, a_fDataTlb)
799	# define IEMTLBTRACE_FLUSH_GLOBAL(a_pVCpu, a_uRev, a_uGRev, a_fDataTlb) \
800	iemTlbTrace(a_pVCpu, kIemTlbTraceType_FlushGlobal, a_uRev, a_uGRev, a_fDataTlb)
801	# define IEMTLBTRACE_LOAD(a_pVCpu, a_GCPtr, a_GCPhys, a_fTlb, a_fDataTlb) \
802	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Load, a_GCPtr, a_GCPhys, a_fDataTlb, a_fTlb)
803	# define IEMTLBTRACE_LOAD_GLOBAL(a_pVCpu, a_GCPtr, a_GCPhys, a_fTlb, a_fDataTlb) \
804	iemTlbTrace(a_pVCpu, kIemTlbTraceType_LoadGlobal, a_GCPtr, a_GCPhys, a_fDataTlb, a_fTlb)
805	#else
806	# define IEMTLBTRACE_INVLPG(a_pVCpu, a_GCPtr) do { } while (0)
807	# define IEMTLBTRACE_EVICT_SLOT(a_pVCpu, a_GCPtrTag, a_GCPhys, a_idxSlot, a_fDataTlb) do { } while (0)
808	# define IEMTLBTRACE_LARGE_EVICT_SLOT(a_pVCpu, a_GCPtrTag, a_GCPhys, a_idxSlot, a_fDataTlb) do { } while (0)
809	# define IEMTLBTRACE_LARGE_SCAN(a_pVCpu, a_fGlobal, a_fNonGlobal, a_fDataTlb) do { } while (0)
810	# define IEMTLBTRACE_FLUSH(a_pVCpu, a_uRev, a_fDataTlb) do { } while (0)
811	# define IEMTLBTRACE_FLUSH_GLOBAL(a_pVCpu, a_uRev, a_uGRev, a_fDataTlb) do { } while (0)
812	# define IEMTLBTRACE_LOAD(a_pVCpu, a_GCPtr, a_GCPhys, a_fTlb, a_fDataTlb) do { } while (0)
813	# define IEMTLBTRACE_LOAD_GLOBAL(a_pVCpu, a_GCPtr, a_GCPhys, a_fTlb, a_fDataTlb) do { } while (0)
814	#endif
815
816	#if defined(IEM_WITH_TLB_TRACE) && defined(IN_RING3) && 1
817	# define IEMTLBTRACE_LOAD_CR0(a_pVCpu, a_uNew, a_uOld) iemTlbTrace(a_pVCpu, kIemTlbTraceType_Load_Cr0, a_uNew, a_uOld)
818	# define IEMTLBTRACE_LOAD_CR3(a_pVCpu, a_uNew, a_uOld) iemTlbTrace(a_pVCpu, kIemTlbTraceType_Load_Cr3, a_uNew, a_uOld)
819	# define IEMTLBTRACE_LOAD_CR4(a_pVCpu, a_uNew, a_uOld) iemTlbTrace(a_pVCpu, kIemTlbTraceType_Load_Cr4, a_uNew, a_uOld)
820	# define IEMTLBTRACE_LOAD_EFER(a_pVCpu, a_uNew, a_uOld) iemTlbTrace(a_pVCpu, kIemTlbTraceType_Load_Efer, a_uNew, a_uOld)
821	#else
822	# define IEMTLBTRACE_LOAD_CR0(a_pVCpu, a_uNew, a_uOld) do { } while (0)
823	# define IEMTLBTRACE_LOAD_CR3(a_pVCpu, a_uNew, a_uOld) do { } while (0)
824	# define IEMTLBTRACE_LOAD_CR4(a_pVCpu, a_uNew, a_uOld) do { } while (0)
825	# define IEMTLBTRACE_LOAD_EFER(a_pVCpu, a_uNew, a_uOld) do { } while (0)
826	#endif
827
828	#if defined(IEM_WITH_TLB_TRACE) && defined(IN_RING3) && 1
829	# define IEMTLBTRACE_IRQ(a_pVCpu, a_uVector, a_fFlags, a_fEFlags) \
830	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Irq, a_fEFlags, 0, a_uVector, a_fFlags)
831	# define IEMTLBTRACE_XCPT(a_pVCpu, a_uVector, a_uErr, a_uCr2, a_fFlags) \
832	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Xcpt, a_uErr, a_uCr2, a_uVector, a_fFlags)
833	# define IEMTLBTRACE_IRET(a_pVCpu, a_uRetCs, a_uRetRip, a_fEFlags) \
834	iemTlbTrace(a_pVCpu, kIemTlbTraceType_IRet, a_uRetRip, a_fEFlags, 0, a_uRetCs)
835	#else
836	# define IEMTLBTRACE_IRQ(a_pVCpu, a_uVector, a_fFlags, a_fEFlags) do { } while (0)
837	# define IEMTLBTRACE_XCPT(a_pVCpu, a_uVector, a_uErr, a_uCr2, a_fFlags) do { } while (0)
838	# define IEMTLBTRACE_IRET(a_pVCpu, a_uRetCs, a_uRetRip, a_fEFlags) do { } while (0)
839	#endif
840
841	#if defined(IEM_WITH_TLB_TRACE) && defined(IN_RING3) && 1
842	# define IEMTLBTRACE_TB_COMPILE(a_pVCpu, a_GCPhysPc) \
843	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Tb_Compile, a_GCPhysPc)
844	# define IEMTLBTRACE_TB_EXEC_THRD(a_pVCpu, a_pTb) \
845	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Tb_Exec_Threaded, (a_pTb)->GCPhysPc, (uintptr_t)a_pTb, 0, (a_pTb)->cUsed)
846	# define IEMTLBTRACE_TB_EXEC_N8VE(a_pVCpu, a_pTb) \
847	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Tb_Exec_Native, (a_pTb)->GCPhysPc, (uintptr_t)a_pTb, 0, (a_pTb)->cUsed)
848	#else
849	# define IEMTLBTRACE_TB_COMPILE(a_pVCpu, a_GCPhysPc) do { } while (0)
850	# define IEMTLBTRACE_TB_EXEC_THRD(a_pVCpu, a_pTb) do { } while (0)
851	# define IEMTLBTRACE_TB_EXEC_N8VE(a_pVCpu, a_pTb) do { } while (0)
852	#endif
853
854	#if defined(IEM_WITH_TLB_TRACE) && defined(IN_RING3) && 1
855	# define IEMTLBTRACE_USER0(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) \
856	iemTlbTrace(a_pVCpu, kIemTlbTraceType_User0, a_u64Param1, a_u64Param2, a_bParam, a_u32Param)
857	# define IEMTLBTRACE_USER1(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) \
858	iemTlbTrace(a_pVCpu, kIemTlbTraceType_User1, a_u64Param1, a_u64Param2, a_bParam, a_u32Param)
859	# define IEMTLBTRACE_USER2(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) \
860	iemTlbTrace(a_pVCpu, kIemTlbTraceType_User2, a_u64Param1, a_u64Param2, a_bParam, a_u32Param)
861	# define IEMTLBTRACE_USER3(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) \
862	iemTlbTrace(a_pVCpu, kIemTlbTraceType_User3, a_u64Param1, a_u64Param2, a_bParam, a_u32Param)
863	#else
864	# define IEMTLBTRACE_USER1(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) do { } while (0)
865	# define IEMTLBTRACE_USER2(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) do { } while (0)
866	# define IEMTLBTRACE_USER3(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) do { } while (0)
867	# define IEMTLBTRACE_USER4(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) do { } while (0)
868	#endif
869
870
871	/** @name IEM_MC_F_XXX - MC block flags/clues.
872	* @todo Merge with IEM_CIMPL_F_XXX
873	* @{ */
874	#define IEM_MC_F_ONLY_8086 RT_BIT_32(0)
875	#define IEM_MC_F_MIN_186 RT_BIT_32(1)
876	#define IEM_MC_F_MIN_286 RT_BIT_32(2)
877	#define IEM_MC_F_NOT_286_OR_OLDER IEM_MC_F_MIN_386
878	#define IEM_MC_F_MIN_386 RT_BIT_32(3)
879	#define IEM_MC_F_MIN_486 RT_BIT_32(4)
880	#define IEM_MC_F_MIN_PENTIUM RT_BIT_32(5)
881	#define IEM_MC_F_MIN_PENTIUM_II IEM_MC_F_MIN_PENTIUM
882	#define IEM_MC_F_MIN_CORE IEM_MC_F_MIN_PENTIUM
883	#define IEM_MC_F_64BIT RT_BIT_32(6)
884	#define IEM_MC_F_NOT_64BIT RT_BIT_32(7)
885	/** This is set by IEMAllN8vePython.py to indicate a variation without the
886	* flags-clearing-and-checking, when there is also a variation with that.
887	* @note Do not use this manully, it's only for python and for testing in
888	* the native recompiler! */
889	#define IEM_MC_F_WITHOUT_FLAGS RT_BIT_32(8)
890	/** @} */
891
892	/** @name IEM_CIMPL_F_XXX - State change clues for CIMPL calls.
893	*
894	* These clues are mainly for the recompiler, so that it can emit correct code.
895	*
896	* They are processed by the python script and which also automatically
897	* calculates flags for MC blocks based on the statements, extending the use of
898	* these flags to describe MC block behavior to the recompiler core. The python
899	* script pass the flags to the IEM_MC2_END_EMIT_CALLS macro, but mainly for
900	* error checking purposes. The script emits the necessary fEndTb = true and
901	* similar statements as this reduces compile time a tiny bit.
902	*
903	* @{ */
904	/** Flag set if direct branch, clear if absolute or indirect. */
905	#define IEM_CIMPL_F_BRANCH_DIRECT RT_BIT_32(0)
906	/** Flag set if indirect branch, clear if direct or relative.
907	* This is also used for all system control transfers (SYSCALL, SYSRET, INT, ++)
908	* as well as for return instructions (RET, IRET, RETF). */
909	#define IEM_CIMPL_F_BRANCH_INDIRECT RT_BIT_32(1)
910	/** Flag set if relative branch, clear if absolute or indirect. */
911	#define IEM_CIMPL_F_BRANCH_RELATIVE RT_BIT_32(2)
912	/** Flag set if conditional branch, clear if unconditional. */
913	#define IEM_CIMPL_F_BRANCH_CONDITIONAL RT_BIT_32(3)
914	/** Flag set if it's a far branch (changes CS). */
915	#define IEM_CIMPL_F_BRANCH_FAR RT_BIT_32(4)
916	/** Convenience: Testing any kind of branch. */
917	#define IEM_CIMPL_F_BRANCH_ANY (IEM_CIMPL_F_BRANCH_DIRECT \| IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_RELATIVE)
918
919	/** Execution flags may change (IEMCPU::fExec). */
920	#define IEM_CIMPL_F_MODE RT_BIT_32(5)
921	/** May change significant portions of RFLAGS. */
922	#define IEM_CIMPL_F_RFLAGS RT_BIT_32(6)
923	/** May change the status bits (X86_EFL_STATUS_BITS) in RFLAGS. */
924	#define IEM_CIMPL_F_STATUS_FLAGS RT_BIT_32(7)
925	/** May trigger interrupt shadowing. */
926	#define IEM_CIMPL_F_INHIBIT_SHADOW RT_BIT_32(8)
927	/** May enable interrupts, so recheck IRQ immediately afterwards executing
928	* the instruction. */
929	#define IEM_CIMPL_F_CHECK_IRQ_AFTER RT_BIT_32(9)
930	/** May disable interrupts, so recheck IRQ immediately before executing the
931	* instruction. */
932	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE RT_BIT_32(10)
933	/** Convenience: Check for IRQ both before and after an instruction. */
934	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE_AND_AFTER (IEM_CIMPL_F_CHECK_IRQ_BEFORE \| IEM_CIMPL_F_CHECK_IRQ_AFTER)
935	/** May trigger a VM exit (treated like IEM_CIMPL_F_MODE atm). */
936	#define IEM_CIMPL_F_VMEXIT RT_BIT_32(11)
937	/** May modify FPU state.
938	* @todo Not sure if this is useful yet. */
939	#define IEM_CIMPL_F_FPU RT_BIT_32(12)
940	/** REP prefixed instruction which may yield before updating PC.
941	* @todo Not sure if this is useful, REP functions now return non-zero
942	* status if they don't update the PC. */
943	#define IEM_CIMPL_F_REP RT_BIT_32(13)
944	/** I/O instruction.
945	* @todo Not sure if this is useful yet. */
946	#define IEM_CIMPL_F_IO RT_BIT_32(14)
947	/** Force end of TB after the instruction. */
948	#define IEM_CIMPL_F_END_TB RT_BIT_32(15)
949	/** Flag set if a branch may also modify the stack (push/pop return address). */
950	#define IEM_CIMPL_F_BRANCH_STACK RT_BIT_32(16)
951	/** Flag set if a branch may also modify the stack (push/pop return address)
952	* and switch it (load/restore SS:RSP). */
953	#define IEM_CIMPL_F_BRANCH_STACK_FAR RT_BIT_32(17)
954	/** Convenience: Raise exception (technically unnecessary, since it shouldn't return VINF_SUCCESS). */
955	#define IEM_CIMPL_F_XCPT \
956	(IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_FAR \| IEM_CIMPL_F_BRANCH_STACK_FAR \
957	\| IEM_CIMPL_F_MODE \| IEM_CIMPL_F_RFLAGS \| IEM_CIMPL_F_VMEXIT)
958
959	/** The block calls a C-implementation instruction function with two implicit arguments.
960	* Mutually exclusive with IEM_CIMPL_F_CALLS_AIMPL and
961	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
962	* @note The python scripts will add this if missing. */
963	#define IEM_CIMPL_F_CALLS_CIMPL RT_BIT_32(18)
964	/** The block calls an ASM-implementation instruction function.
965	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL and
966	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
967	* @note The python scripts will add this if missing. */
968	#define IEM_CIMPL_F_CALLS_AIMPL RT_BIT_32(19)
969	/** The block calls an ASM-implementation instruction function with an implicit
970	* X86FXSTATE pointer argument.
971	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL, IEM_CIMPL_F_CALLS_AIMPL and
972	* IEM_CIMPL_F_CALLS_AIMPL_WITH_XSTATE.
973	* @note The python scripts will add this if missing. */
974	#define IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE RT_BIT_32(20)
975	/** The block calls an ASM-implementation instruction function with an implicit
976	* X86XSAVEAREA pointer argument.
977	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL, IEM_CIMPL_F_CALLS_AIMPL and
978	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
979	* @note No different from IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE, so same value.
980	* @note The python scripts will add this if missing. */
981	#define IEM_CIMPL_F_CALLS_AIMPL_WITH_XSTATE IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE
982	/** @} */
983
984
985	/** @name IEM_F_XXX - Execution mode flags (IEMCPU::fExec, IEMTB::fFlags).
986	*
987	* These flags are set when entering IEM and adjusted as code is executed, such
988	* that they will always contain the current values as instructions are
989	* finished.
990	*
991	* In recompiled execution mode, (most of) these flags are included in the
992	* translation block selection key and stored in IEMTB::fFlags alongside the
993	* IEMTB_F_XXX flags. The latter flags uses bits 31 thru 24, which are all zero
994	* in IEMCPU::fExec.
995	*
996	* @{ */
997	/** Mode: The block target mode mask. */
998	#define IEM_F_MODE_MASK UINT32_C(0x0000001f)
999	/** Mode: The IEMMODE part of the IEMTB_F_MODE_MASK value. */
1000	#define IEM_F_MODE_CPUMODE_MASK UINT32_C(0x00000003)
1001	/** X86 Mode: Bit used to indicating pre-386 CPU in 16-bit mode (for eliminating
1002	* conditional in EIP/IP updating), and flat wide open CS, SS, DS, and ES in
1003	* 32-bit mode (for simplifying most memory accesses). */
1004	#define IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK UINT32_C(0x00000004)
1005	/** X86 Mode: Bit indicating protected mode, real mode (or SMM) when not set. */
1006	#define IEM_F_MODE_X86_PROT_MASK UINT32_C(0x00000008)
1007	/** X86 Mode: Bit used to indicate virtual 8086 mode (only 16-bit). */
1008	#define IEM_F_MODE_X86_V86_MASK UINT32_C(0x00000010)
1009
1010	/** X86 Mode: 16-bit on 386 or later. */
1011	#define IEM_F_MODE_X86_16BIT UINT32_C(0x00000000)
1012	/** X86 Mode: 80286, 80186 and 8086/88 targetting blocks (EIP update opt). */
1013	#define IEM_F_MODE_X86_16BIT_PRE_386 UINT32_C(0x00000004)
1014	/** X86 Mode: 16-bit protected mode on 386 or later. */
1015	#define IEM_F_MODE_X86_16BIT_PROT UINT32_C(0x00000008)
1016	/** X86 Mode: 16-bit protected mode on 386 or later. */
1017	#define IEM_F_MODE_X86_16BIT_PROT_PRE_386 UINT32_C(0x0000000c)
1018	/** X86 Mode: 16-bit virtual 8086 protected mode (on 386 or later). */
1019	#define IEM_F_MODE_X86_16BIT_PROT_V86 UINT32_C(0x00000018)
1020
1021	/** X86 Mode: 32-bit on 386 or later. */
1022	#define IEM_F_MODE_X86_32BIT UINT32_C(0x00000001)
1023	/** X86 Mode: 32-bit mode with wide open flat CS, SS, DS and ES. */
1024	#define IEM_F_MODE_X86_32BIT_FLAT UINT32_C(0x00000005)
1025	/** X86 Mode: 32-bit protected mode. */
1026	#define IEM_F_MODE_X86_32BIT_PROT UINT32_C(0x00000009)
1027	/** X86 Mode: 32-bit protected mode with wide open flat CS, SS, DS and ES. */
1028	#define IEM_F_MODE_X86_32BIT_PROT_FLAT UINT32_C(0x0000000d)
1029
1030	/** X86 Mode: 64-bit (includes protected, but not the flat bit). */
1031	#define IEM_F_MODE_X86_64BIT UINT32_C(0x0000000a)
1032
1033	/** X86 Mode: Checks if @a a_fExec represent a FLAT mode. */
1034	#define IEM_F_MODE_X86_IS_FLAT(a_fExec) ( ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_64BIT \
1035	\|\| ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_PROT_FLAT \
1036	\|\| ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_FLAT)
1037
1038	/** Bypass access handlers when set. */
1039	#define IEM_F_BYPASS_HANDLERS UINT32_C(0x00010000)
1040	/** Have pending hardware instruction breakpoints. */
1041	#define IEM_F_PENDING_BRK_INSTR UINT32_C(0x00020000)
1042	/** Have pending hardware data breakpoints. */
1043	#define IEM_F_PENDING_BRK_DATA UINT32_C(0x00040000)
1044
1045	/** X86: Have pending hardware I/O breakpoints. */
1046	#define IEM_F_PENDING_BRK_X86_IO UINT32_C(0x00000400)
1047	/** X86: Disregard the lock prefix (implied or not) when set. */
1048	#define IEM_F_X86_DISREGARD_LOCK UINT32_C(0x00000800)
1049
1050	/** Pending breakpoint mask (what iemCalcExecDbgFlags works out). */
1051	#define IEM_F_PENDING_BRK_MASK (IEM_F_PENDING_BRK_INSTR \| IEM_F_PENDING_BRK_DATA \| IEM_F_PENDING_BRK_X86_IO)
1052
1053	/** Caller configurable options. */
1054	#define IEM_F_USER_OPTS (IEM_F_BYPASS_HANDLERS \| IEM_F_X86_DISREGARD_LOCK)
1055
1056	/** X86: The current protection level (CPL) shift factor. */
1057	#define IEM_F_X86_CPL_SHIFT 8
1058	/** X86: The current protection level (CPL) mask. */
1059	#define IEM_F_X86_CPL_MASK UINT32_C(0x00000300)
1060	/** X86: The current protection level (CPL) shifted mask. */
1061	#define IEM_F_X86_CPL_SMASK UINT32_C(0x00000003)
1062
1063	/** X86: Alignment checks enabled (CR0.AM=1 & EFLAGS.AC=1). */
1064	#define IEM_F_X86_AC UINT32_C(0x00080000)
1065
1066	/** X86 execution context.
1067	* The IEM_F_X86_CTX_XXX values are individual flags that can be combined (with
1068	* the exception of IEM_F_X86_CTX_NORMAL). This allows running VMs from SMM
1069	* mode. */
1070	#define IEM_F_X86_CTX_MASK UINT32_C(0x0000f000)
1071	/** X86 context: Plain regular execution context. */
1072	#define IEM_F_X86_CTX_NORMAL UINT32_C(0x00000000)
1073	/** X86 context: VT-x enabled. */
1074	#define IEM_F_X86_CTX_VMX UINT32_C(0x00001000)
1075	/** X86 context: AMD-V enabled. */
1076	#define IEM_F_X86_CTX_SVM UINT32_C(0x00002000)
1077	/** X86 context: In AMD-V or VT-x guest mode. */
1078	#define IEM_F_X86_CTX_IN_GUEST UINT32_C(0x00004000)
1079	/** X86 context: System management mode (SMM). */
1080	#define IEM_F_X86_CTX_SMM UINT32_C(0x00008000)
1081
1082	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
1083	* iemRegFinishClearingRF() most for most situations (CPUMCTX_DBG_HIT_DRX_MASK
1084	* and CPUMCTX_DBG_DBGF_MASK are covered by the IEM_F_PENDING_BRK_XXX bits
1085	* alread). */
1086
1087	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
1088	* iemRegFinishClearingRF() most for most situations
1089	* (CPUMCTX_DBG_HIT_DRX_MASK and CPUMCTX_DBG_DBGF_MASK are covered by
1090	* the IEM_F_PENDING_BRK_XXX bits alread). */
1091
1092	/** @} */
1093
1094
1095	/** @name IEMTB_F_XXX - Translation block flags (IEMTB::fFlags).
1096	*
1097	* Extends the IEM_F_XXX flags (subject to IEMTB_F_IEM_F_MASK) to make up the
1098	* translation block flags. The combined flag mask (subject to
1099	* IEMTB_F_KEY_MASK) is used as part of the lookup key for translation blocks.
1100	*
1101	* @{ */
1102	/** Mask of IEM_F_XXX flags included in IEMTB_F_XXX. */
1103	#define IEMTB_F_IEM_F_MASK UINT32_C(0x00ffffff)
1104
1105	/** Type: The block type mask. */
1106	#define IEMTB_F_TYPE_MASK UINT32_C(0x03000000)
1107	/** Type: Purly threaded recompiler (via tables). */
1108	#define IEMTB_F_TYPE_THREADED UINT32_C(0x01000000)
1109	/** Type: Native recompilation. */
1110	#define IEMTB_F_TYPE_NATIVE UINT32_C(0x02000000)
1111
1112	/** Set when we're starting the block in an "interrupt shadow".
1113	* We don't need to distingish between the two types of this mask, thus the one.
1114	* @see CPUMCTX_INHIBIT_SHADOW, CPUMIsInInterruptShadow() */
1115	#define IEMTB_F_INHIBIT_SHADOW UINT32_C(0x04000000)
1116	/** Set when we're currently inhibiting NMIs
1117	* @see CPUMCTX_INHIBIT_NMI, CPUMAreInterruptsInhibitedByNmi() */
1118	#define IEMTB_F_INHIBIT_NMI UINT32_C(0x08000000)
1119
1120	/** Checks that EIP/IP is wihin CS.LIM before each instruction. Used when
1121	* we're close the limit before starting a TB, as determined by
1122	* iemGetTbFlagsForCurrentPc(). */
1123	#define IEMTB_F_CS_LIM_CHECKS UINT32_C(0x10000000)
1124
1125	/** Mask of the IEMTB_F_XXX flags that are part of the TB lookup key.
1126	*
1127	* @note We skip all of IEM_F_X86_CTX_MASK, with the exception of SMM (which we
1128	* don't implement), because we don't currently generate any context
1129	* specific code - that's all handled in CIMPL functions.
1130	*
1131	* For the threaded recompiler we don't generate any CPL specific code
1132	* either, but the native recompiler does for memory access (saves getting
1133	* the CPL from fExec and turning it into IEMTLBE_F_PT_NO_USER).
1134	* Since most OSes will not share code between rings, this shouldn't
1135	* have any real effect on TB/memory/recompiling load.
1136	*/
1137	#define IEMTB_F_KEY_MASK ((UINT32_MAX & ~(IEM_F_X86_CTX_MASK \| IEMTB_F_TYPE_MASK)) \| IEM_F_X86_CTX_SMM)
1138	/** @} */
1139
1140	AssertCompile( (IEM_F_MODE_X86_16BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
1141	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1142	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_PROT_MASK));
1143	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_V86_MASK));
1144	AssertCompile( (IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
1145	AssertCompile( IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
1146	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_PROT_MASK));
1147	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
1148	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
1149	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1150	AssertCompile( IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
1151	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_V86_MASK));
1152	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
1153	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
1154	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_PROT_MASK);
1155	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
1156	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_PROT_MASK);
1157	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1158	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_V86_MASK);
1159
1160	AssertCompile( (IEM_F_MODE_X86_32BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
1161	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1162	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_PROT_MASK));
1163	AssertCompile( (IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
1164	AssertCompile( IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
1165	AssertCompile(!(IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_PROT_MASK));
1166	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
1167	AssertCompile(!(IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1168	AssertCompile( IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
1169	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
1170	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
1171	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_PROT_MASK);
1172
1173	AssertCompile( (IEM_F_MODE_X86_64BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT);
1174	AssertCompile( IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_PROT_MASK);
1175	AssertCompile(!(IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1176
1177	/** Native instruction type for use with the native code generator.
1178	* This is a byte (uint8_t) for x86 and amd64 and uint32_t for the other(s). */
1179	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
1180	typedef uint8_t IEMNATIVEINSTR;
1181	#else
1182	typedef uint32_t IEMNATIVEINSTR;
1183	#endif
1184	/** Pointer to a native instruction unit. */
1185	typedef IEMNATIVEINSTR *PIEMNATIVEINSTR;
1186	/** Pointer to a const native instruction unit. */
1187	typedef IEMNATIVEINSTR const *PCIEMNATIVEINSTR;
1188
1189	/**
1190	* A call for the threaded call table.
1191	*/
1192	typedef struct IEMTHRDEDCALLENTRY
1193	{
1194	/** The function to call (IEMTHREADEDFUNCS). */
1195	uint16_t enmFunction;
1196
1197	/** Instruction number in the TB (for statistics). */
1198	uint8_t idxInstr;
1199	/** The opcode length. */
1200	uint8_t cbOpcode;
1201	/** Offset into IEMTB::pabOpcodes. */
1202	uint16_t offOpcode;
1203
1204	/** TB lookup table index (7 bits) and large size (1 bits).
1205	*
1206	* The default size is 1 entry, but for indirect calls and returns we set the
1207	* top bit and allocate 4 (IEM_TB_LOOKUP_TAB_LARGE_SIZE) entries. The large
1208	* tables uses RIP for selecting the entry to use, as it is assumed a hash table
1209	* lookup isn't that slow compared to sequentially trying out 4 TBs.
1210	*
1211	* By default lookup table entry 0 for a TB is reserved as a fallback for
1212	* calltable entries w/o explicit entreis, so this member will be non-zero if
1213	* there is a lookup entry associated with this call.
1214	*
1215	* @sa IEM_TB_LOOKUP_TAB_GET_SIZE, IEM_TB_LOOKUP_TAB_GET_IDX
1216	*/
1217	uint8_t uTbLookup;
1218
1219	/** Unused atm. */
1220	uint8_t uUnused0;
1221
1222	/** Generic parameters. */
1223	uint64_t auParams[3];
1224	} IEMTHRDEDCALLENTRY;
1225	AssertCompileSize(IEMTHRDEDCALLENTRY, sizeof(uint64_t) * 4);
1226	/** Pointer to a threaded call entry. */
1227	typedef struct IEMTHRDEDCALLENTRY *PIEMTHRDEDCALLENTRY;
1228	/** Pointer to a const threaded call entry. */
1229	typedef IEMTHRDEDCALLENTRY const *PCIEMTHRDEDCALLENTRY;
1230
1231	/** The number of TB lookup table entries for a large allocation
1232	* (IEMTHRDEDCALLENTRY::uTbLookup bit 7 set). */
1233	#define IEM_TB_LOOKUP_TAB_LARGE_SIZE 4
1234	/** Get the lookup table size from IEMTHRDEDCALLENTRY::uTbLookup. */
1235	#define IEM_TB_LOOKUP_TAB_GET_SIZE(a_uTbLookup) (!((a_uTbLookup) & 0x80) ? 1 : IEM_TB_LOOKUP_TAB_LARGE_SIZE)
1236	/** Get the first lookup table index from IEMTHRDEDCALLENTRY::uTbLookup. */
1237	#define IEM_TB_LOOKUP_TAB_GET_IDX(a_uTbLookup) ((a_uTbLookup) & 0x7f)
1238	/** Get the lookup table index from IEMTHRDEDCALLENTRY::uTbLookup and RIP. */
1239	#define IEM_TB_LOOKUP_TAB_GET_IDX_WITH_RIP(a_uTbLookup, a_Rip) \
1240	(!((a_uTbLookup) & 0x80) ? (a_uTbLookup) & 0x7f : ((a_uTbLookup) & 0x7f) + ((a_Rip) & (IEM_TB_LOOKUP_TAB_LARGE_SIZE - 1)) )
1241
1242	/** Make a IEMTHRDEDCALLENTRY::uTbLookup value. */
1243	#define IEM_TB_LOOKUP_TAB_MAKE(a_idxTable, a_fLarge) ((a_idxTable) \| ((a_fLarge) ? 0x80 : 0))
1244
1245	/**
1246	* Native IEM TB 'function' typedef.
1247	*
1248	* This will throw/longjmp on occation.
1249	*
1250	* @note AMD64 doesn't have that many non-volatile registers and does sport
1251	* 32-bit address displacments, so we don't need pCtx.
1252	*
1253	* On ARM64 pCtx allows us to directly address the whole register
1254	* context without requiring a separate indexing register holding the
1255	* offset. This saves an instruction loading the offset for each guest
1256	* CPU context access, at the cost of a non-volatile register.
1257	* Fortunately, ARM64 has quite a lot more registers.
1258	*/
1259	typedef
1260	#ifdef RT_ARCH_AMD64
1261	int FNIEMTBNATIVE(PVMCPUCC pVCpu)
1262	#else
1263	int FNIEMTBNATIVE(PVMCPUCC pVCpu, PCPUMCTX pCtx)
1264	#endif
1265	#if RT_CPLUSPLUS_PREREQ(201700)
1266	IEM_NOEXCEPT_MAY_LONGJMP
1267	#endif
1268	;
1269	/** Pointer to a native IEM TB entry point function.
1270	* This will throw/longjmp on occation. */
1271	typedef FNIEMTBNATIVE *PFNIEMTBNATIVE;
1272
1273
1274	/**
1275	* Translation block debug info entry type.
1276	*/
1277	typedef enum IEMTBDBGENTRYTYPE
1278	{
1279	kIemTbDbgEntryType_Invalid = 0,
1280	/** The entry is for marking a native code position.
1281	* Entries following this all apply to this position. */
1282	kIemTbDbgEntryType_NativeOffset,
1283	/** The entry is for a new guest instruction. */
1284	kIemTbDbgEntryType_GuestInstruction,
1285	/** Marks the start of a threaded call. */
1286	kIemTbDbgEntryType_ThreadedCall,
1287	/** Marks the location of a label. */
1288	kIemTbDbgEntryType_Label,
1289	/** Info about a host register shadowing a guest register. */
1290	kIemTbDbgEntryType_GuestRegShadowing,
1291	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1292	/** Info about a host SIMD register shadowing a guest SIMD register. */
1293	kIemTbDbgEntryType_GuestSimdRegShadowing,
1294	#endif
1295	#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
1296	/** Info about a delayed RIP update. */
1297	kIemTbDbgEntryType_DelayedPcUpdate,
1298	#endif
1299	#if defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK) \|\| defined(IEMNATIVE_WITH_SIMD_REG_ALLOCATOR)
1300	/** Info about a shadowed guest register becoming dirty. */
1301	kIemTbDbgEntryType_GuestRegDirty,
1302	/** Info about register writeback/flush oepration. */
1303	kIemTbDbgEntryType_GuestRegWriteback,
1304	#endif
1305	kIemTbDbgEntryType_End
1306	} IEMTBDBGENTRYTYPE;
1307
1308	/**
1309	* Translation block debug info entry.
1310	*/
1311	typedef union IEMTBDBGENTRY
1312	{
1313	/** Plain 32-bit view. */
1314	uint32_t u;
1315
1316	/** Generic view for getting at the type field. */
1317	struct
1318	{
1319	/** IEMTBDBGENTRYTYPE */
1320	uint32_t uType : 4;
1321	uint32_t uTypeSpecific : 28;
1322	} Gen;
1323
1324	struct
1325	{
1326	/** kIemTbDbgEntryType_ThreadedCall1. */
1327	uint32_t uType : 4;
1328	/** Native code offset. */
1329	uint32_t offNative : 28;
1330	} NativeOffset;
1331
1332	struct
1333	{
1334	/** kIemTbDbgEntryType_GuestInstruction. */
1335	uint32_t uType : 4;
1336	uint32_t uUnused : 4;
1337	/** The IEM_F_XXX flags. */
1338	uint32_t fExec : 24;
1339	} GuestInstruction;
1340
1341	struct
1342	{
1343	/* kIemTbDbgEntryType_ThreadedCall. */
1344	uint32_t uType : 4;
1345	/** Set if the call was recompiled to native code, clear if just calling
1346	* threaded function. */
1347	uint32_t fRecompiled : 1;
1348	uint32_t uUnused : 11;
1349	/** The threaded call number (IEMTHREADEDFUNCS). */
1350	uint32_t enmCall : 16;
1351	} ThreadedCall;
1352
1353	struct
1354	{
1355	/* kIemTbDbgEntryType_Label. */
1356	uint32_t uType : 4;
1357	uint32_t uUnused : 4;
1358	/** The label type (IEMNATIVELABELTYPE). */
1359	uint32_t enmLabel : 8;
1360	/** The label data. */
1361	uint32_t uData : 16;
1362	} Label;
1363
1364	struct
1365	{
1366	/* kIemTbDbgEntryType_GuestRegShadowing. */
1367	uint32_t uType : 4;
1368	uint32_t uUnused : 4;
1369	/** The guest register being shadowed (IEMNATIVEGSTREG). */
1370	uint32_t idxGstReg : 8;
1371	/** The host new register number, UINT8_MAX if dropped. */
1372	uint32_t idxHstReg : 8;
1373	/** The previous host register number, UINT8_MAX if new. */
1374	uint32_t idxHstRegPrev : 8;
1375	} GuestRegShadowing;
1376
1377	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1378	struct
1379	{
1380	/* kIemTbDbgEntryType_GuestSimdRegShadowing. */
1381	uint32_t uType : 4;
1382	uint32_t uUnused : 4;
1383	/** The guest register being shadowed (IEMNATIVEGSTSIMDREG). */
1384	uint32_t idxGstSimdReg : 8;
1385	/** The host new register number, UINT8_MAX if dropped. */
1386	uint32_t idxHstSimdReg : 8;
1387	/** The previous host register number, UINT8_MAX if new. */
1388	uint32_t idxHstSimdRegPrev : 8;
1389	} GuestSimdRegShadowing;
1390	#endif
1391
1392	#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
1393	struct
1394	{
1395	/* kIemTbDbgEntryType_DelayedPcUpdate. */
1396	uint32_t uType : 4;
1397	/* The instruction offset added to the program counter. */
1398	uint32_t offPc : 14;
1399	/** Number of instructions skipped. */
1400	uint32_t cInstrSkipped : 14;
1401	} DelayedPcUpdate;
1402	#endif
1403
1404	#if defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK) \|\| defined(IEMNATIVE_WITH_SIMD_REG_ALLOCATOR)
1405	struct
1406	{
1407	/* kIemTbDbgEntryType_GuestRegDirty. */
1408	uint32_t uType : 4;
1409	uint32_t uUnused : 11;
1410	/** Flag whether this is about a SIMD (true) or general (false) register. */
1411	uint32_t fSimdReg : 1;
1412	/** The guest register index being marked as dirty. */
1413	uint32_t idxGstReg : 8;
1414	/** The host register number this register is shadowed in .*/
1415	uint32_t idxHstReg : 8;
1416	} GuestRegDirty;
1417
1418	struct
1419	{
1420	/* kIemTbDbgEntryType_GuestRegWriteback. */
1421	uint32_t uType : 4;
1422	/** Flag whether this is about a SIMD (true) or general (false) register flush. */
1423	uint32_t fSimdReg : 1;
1424	/** The mask shift. */
1425	uint32_t cShift : 2;
1426	/** The guest register mask being written back. */
1427	uint32_t fGstReg : 25;
1428	} GuestRegWriteback;
1429	#endif
1430
1431	} IEMTBDBGENTRY;
1432	AssertCompileSize(IEMTBDBGENTRY, sizeof(uint32_t));
1433	/** Pointer to a debug info entry. */
1434	typedef IEMTBDBGENTRY *PIEMTBDBGENTRY;
1435	/** Pointer to a const debug info entry. */
1436	typedef IEMTBDBGENTRY const *PCIEMTBDBGENTRY;
1437
1438	/**
1439	* Translation block debug info.
1440	*/
1441	typedef struct IEMTBDBG
1442	{
1443	/** Number of entries in aEntries. */
1444	uint32_t cEntries;
1445	/** The offset of the last kIemTbDbgEntryType_NativeOffset record. */
1446	uint32_t offNativeLast;
1447	/** Debug info entries. */
1448	RT_FLEXIBLE_ARRAY_EXTENSION
1449	IEMTBDBGENTRY aEntries[RT_FLEXIBLE_ARRAY];
1450	} IEMTBDBG;
1451	/** Pointer to TB debug info. */
1452	typedef IEMTBDBG *PIEMTBDBG;
1453	/** Pointer to const TB debug info. */
1454	typedef IEMTBDBG const *PCIEMTBDBG;
1455
1456
1457	/**
1458	* Translation block.
1459	*
1460	* The current plan is to just keep TBs and associated lookup hash table private
1461	* to each VCpu as that simplifies TB removal greatly (no races) and generally
1462	* avoids using expensive atomic primitives for updating lists and stuff.
1463	*/
1464	#pragma pack(2) /* to prevent the Thrd structure from being padded unnecessarily */
1465	typedef struct IEMTB
1466	{
1467	/** Next block with the same hash table entry. */
1468	struct IEMTB *pNext;
1469	/** Usage counter. */
1470	uint32_t cUsed;
1471	/** The IEMCPU::msRecompilerPollNow last time it was used. */
1472	uint32_t msLastUsed;
1473
1474	/** @name What uniquely identifies the block.
1475	* @{ */
1476	RTGCPHYS GCPhysPc;
1477	/** IEMTB_F_XXX (i.e. IEM_F_XXX ++). */
1478	uint32_t fFlags;
1479	union
1480	{
1481	struct
1482	{
1483	/*< Relevant CS X86DESCATTR_XXX bits. /
1484	uint16_t fAttr;
1485	} x86;
1486	};
1487	/** @} */
1488
1489	/** Number of opcode ranges. */
1490	uint8_t cRanges;
1491	/** Statistics: Number of instructions in the block. */
1492	uint8_t cInstructions;
1493
1494	/** Type specific info. */
1495	union
1496	{
1497	struct
1498	{
1499	/** The call sequence table. */
1500	PIEMTHRDEDCALLENTRY paCalls;
1501	/** Number of calls in paCalls. */
1502	uint16_t cCalls;
1503	/** Number of calls allocated. */
1504	uint16_t cAllocated;
1505	} Thrd;
1506	struct
1507	{
1508	/** The native instructions (PFNIEMTBNATIVE). */
1509	PIEMNATIVEINSTR paInstructions;
1510	/** Number of instructions pointed to by paInstructions. */
1511	uint32_t cInstructions;
1512	} Native;
1513	/** Generic view for zeroing when freeing. */
1514	struct
1515	{
1516	uintptr_t uPtr;
1517	uint32_t uData;
1518	} Gen;
1519	};
1520
1521	/** The allocation chunk this TB belongs to. */
1522	uint8_t idxAllocChunk;
1523	/** The number of entries in the lookup table.
1524	* Because we're out of space, the TB lookup table is located before the
1525	* opcodes pointed to by pabOpcodes. */
1526	uint8_t cTbLookupEntries;
1527
1528	/** Number of bytes of opcodes stored in pabOpcodes.
1529	* @todo this field isn't really needed, aRanges keeps the actual info. */
1530	uint16_t cbOpcodes;
1531	/** Pointer to the opcode bytes this block was recompiled from.
1532	* This also points to the TB lookup table, which starts cTbLookupEntries
1533	* entries before the opcodes (we don't have room atm for another point). */
1534	uint8_t *pabOpcodes;
1535
1536	/** Debug info if enabled.
1537	* This is only generated by the native recompiler. */
1538	PIEMTBDBG pDbgInfo;
1539
1540	/* --- 64 byte cache line end --- */
1541
1542	/** Opcode ranges.
1543	*
1544	* The opcode checkers and maybe TLB loading functions will use this to figure
1545	* out what to do. The parameter will specify an entry and the opcode offset to
1546	* start at and the minimum number of bytes to verify (instruction length).
1547	*
1548	* When VT-x and AMD-V looks up the opcode bytes for an exitting instruction,
1549	* they'll first translate RIP (+ cbInstr - 1) to a physical address using the
1550	* code TLB (must have a valid entry for that address) and scan the ranges to
1551	* locate the corresponding opcodes. Probably.
1552	*/
1553	struct IEMTBOPCODERANGE
1554	{
1555	/** Offset within pabOpcodes. */
1556	uint16_t offOpcodes;
1557	/** Number of bytes. */
1558	uint16_t cbOpcodes;
1559	/** The page offset. */
1560	RT_GCC_EXTENSION
1561	uint16_t offPhysPage : 12;
1562	/** Unused bits. */
1563	RT_GCC_EXTENSION
1564	uint16_t u2Unused : 2;
1565	/** Index into GCPhysPc + aGCPhysPages for the physical page address. */
1566	RT_GCC_EXTENSION
1567	uint16_t idxPhysPage : 2;
1568	} aRanges[8];
1569
1570	/** Physical pages that this TB covers.
1571	* The GCPhysPc w/o page offset is element zero, so starting here with 1. */
1572	RTGCPHYS aGCPhysPages[2];
1573	} IEMTB;
1574	#pragma pack()
1575	AssertCompileMemberAlignment(IEMTB, GCPhysPc, sizeof(RTGCPHYS));
1576	AssertCompileMemberAlignment(IEMTB, Thrd, sizeof(void *));
1577	AssertCompileMemberAlignment(IEMTB, pabOpcodes, sizeof(void *));
1578	AssertCompileMemberAlignment(IEMTB, pDbgInfo, sizeof(void *));
1579	AssertCompileMemberAlignment(IEMTB, aGCPhysPages, sizeof(RTGCPHYS));
1580	AssertCompileMemberOffset(IEMTB, aRanges, 64);
1581	AssertCompileMemberSize(IEMTB, aRanges[0], 6);
1582	#if 1
1583	AssertCompileSize(IEMTB, 128);
1584	# define IEMTB_SIZE_IS_POWER_OF_TWO /*< The IEMTB size is a power of two. /
1585	#else
1586	AssertCompileSize(IEMTB, 168);
1587	# undef IEMTB_SIZE_IS_POWER_OF_TWO
1588	#endif
1589
1590	/** Pointer to a translation block. */
1591	typedef IEMTB *PIEMTB;
1592	/** Pointer to a const translation block. */
1593	typedef IEMTB const *PCIEMTB;
1594
1595	/** Gets address of the given TB lookup table entry. */
1596	#define IEMTB_GET_TB_LOOKUP_TAB_ENTRY(a_pTb, a_idx) \
1597	((PIEMTB )&(a_pTb)->pabOpcodes[-(int)((a_pTb)->cTbLookupEntries - (a_idx)) sizeof(PIEMTB)])
1598
1599	/**
1600	* Gets the physical address for a TB opcode range.
1601	*/
1602	DECL_FORCE_INLINE(RTGCPHYS) iemTbGetRangePhysPageAddr(PCIEMTB pTb, uint8_t idxRange)
1603	{
1604	Assert(idxRange < RT_MIN(pTb->cRanges, RT_ELEMENTS(pTb->aRanges)));
1605	uint8_t const idxPage = pTb->aRanges[idxRange].idxPhysPage;
1606	Assert(idxPage <= RT_ELEMENTS(pTb->aGCPhysPages));
1607	if (idxPage == 0)
1608	return pTb->GCPhysPc & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
1609	Assert(!(pTb->aGCPhysPages[idxPage - 1] & GUEST_PAGE_OFFSET_MASK));
1610	return pTb->aGCPhysPages[idxPage - 1];
1611	}
1612
1613
1614	/**
1615	* A chunk of memory in the TB allocator.
1616	*/
1617	typedef struct IEMTBCHUNK
1618	{
1619	/** Pointer to the translation blocks in this chunk. */
1620	PIEMTB paTbs;
1621	#ifdef IN_RING0
1622	/** Allocation handle. */
1623	RTR0MEMOBJ hMemObj;
1624	#endif
1625	} IEMTBCHUNK;
1626
1627	/**
1628	* A per-CPU translation block allocator.
1629	*
1630	* Because of how the IEMTBCACHE uses the lower 6 bits of the TB address to keep
1631	* the length of the collision list, and of course also for cache line alignment
1632	* reasons, the TBs must be allocated with at least 64-byte alignment.
1633	* Memory is there therefore allocated using one of the page aligned allocators.
1634	*
1635	*
1636	* To avoid wasting too much memory, it is allocated piecemeal as needed,
1637	* in chunks (IEMTBCHUNK) of 2 MiB or more. The TB has an 8-bit chunk index
1638	* that enables us to quickly calculate the allocation bitmap position when
1639	* freeing the translation block.
1640	*/
1641	typedef struct IEMTBALLOCATOR
1642	{
1643	/** Magic value (IEMTBALLOCATOR_MAGIC). */
1644	uint32_t uMagic;
1645
1646	#ifdef IEMTB_SIZE_IS_POWER_OF_TWO
1647	/** Mask corresponding to cTbsPerChunk - 1. */
1648	uint32_t fChunkMask;
1649	/** Shift count corresponding to cTbsPerChunk. */
1650	uint8_t cChunkShift;
1651	#else
1652	uint32_t uUnused;
1653	uint8_t bUnused;
1654	#endif
1655	/** Number of chunks we're allowed to allocate. */
1656	uint8_t cMaxChunks;
1657	/** Number of chunks currently populated. */
1658	uint16_t cAllocatedChunks;
1659	/** Number of translation blocks per chunk. */
1660	uint32_t cTbsPerChunk;
1661	/** Chunk size. */
1662	uint32_t cbPerChunk;
1663
1664	/** The maximum number of TBs. */
1665	uint32_t cMaxTbs;
1666	/** Total number of TBs in the populated chunks.
1667	* (cAllocatedChunks * cTbsPerChunk) */
1668	uint32_t cTotalTbs;
1669	/** The current number of TBs in use.
1670	* The number of free TBs: cAllocatedTbs - cInUseTbs; */
1671	uint32_t cInUseTbs;
1672	/** Statistics: Number of the cInUseTbs that are native ones. */
1673	uint32_t cNativeTbs;
1674	/** Statistics: Number of the cInUseTbs that are threaded ones. */
1675	uint32_t cThreadedTbs;
1676
1677	/** Where to start pruning TBs from when we're out.
1678	* See iemTbAllocatorAllocSlow for details. */
1679	uint32_t iPruneFrom;
1680	/** Where to start pruning native TBs from when we're out of executable memory.
1681	* See iemTbAllocatorFreeupNativeSpace for details. */
1682	uint32_t iPruneNativeFrom;
1683	uint64_t u64Padding;
1684
1685	/** Statistics: Number of TB allocation calls. */
1686	STAMCOUNTER StatAllocs;
1687	/** Statistics: Number of TB free calls. */
1688	STAMCOUNTER StatFrees;
1689	/** Statistics: Time spend pruning. */
1690	STAMPROFILE StatPrune;
1691	/** Statistics: Time spend pruning native TBs. */
1692	STAMPROFILE StatPruneNative;
1693
1694	/** The delayed free list (see iemTbAlloctorScheduleForFree). */
1695	PIEMTB pDelayedFreeHead;
1696	/* Head of the list of free TBs. */
1697	PIEMTB pTbsFreeHead;
1698
1699	/** Allocation chunks. */
1700	IEMTBCHUNK aChunks[256];
1701	} IEMTBALLOCATOR;
1702	/** Pointer to a TB allocator. */
1703	typedef struct IEMTBALLOCATOR *PIEMTBALLOCATOR;
1704
1705	/** Magic value for the TB allocator (Emmet Harley Cohen). */
1706	#define IEMTBALLOCATOR_MAGIC UINT32_C(0x19900525)
1707
1708
1709	/**
1710	* A per-CPU translation block cache (hash table).
1711	*
1712	* The hash table is allocated once during IEM initialization and size double
1713	* the max TB count, rounded up to the nearest power of two (so we can use and
1714	* AND mask rather than a rest division when hashing).
1715	*/
1716	typedef struct IEMTBCACHE
1717	{
1718	/** Magic value (IEMTBCACHE_MAGIC). */
1719	uint32_t uMagic;
1720	/** Size of the hash table. This is a power of two. */
1721	uint32_t cHash;
1722	/** The mask corresponding to cHash. */
1723	uint32_t uHashMask;
1724	uint32_t uPadding;
1725
1726	/** @name Statistics
1727	* @{ */
1728	/** Number of collisions ever. */
1729	STAMCOUNTER cCollisions;
1730
1731	/** Statistics: Number of TB lookup misses. */
1732	STAMCOUNTER cLookupMisses;
1733	/** Statistics: Number of TB lookup hits via hash table (debug only). */
1734	STAMCOUNTER cLookupHits;
1735	/** Statistics: Number of TB lookup hits via TB associated lookup table (debug only). */
1736	STAMCOUNTER cLookupHitsViaTbLookupTable;
1737	STAMCOUNTER auPadding2[2];
1738	/** Statistics: Collision list length pruning. */
1739	STAMPROFILE StatPrune;
1740	/** @} */
1741
1742	/** The hash table itself.
1743	* @note The lower 6 bits of the pointer is used for keeping the collision
1744	* list length, so we can take action when it grows too long.
1745	* This works because TBs are allocated using a 64 byte (or
1746	* higher) alignment from page aligned chunks of memory, so the lower
1747	* 6 bits of the address will always be zero.
1748	* See IEMTBCACHE_PTR_COUNT_MASK, IEMTBCACHE_PTR_MAKE and friends.
1749	*/
1750	RT_FLEXIBLE_ARRAY_EXTENSION
1751	PIEMTB apHash[RT_FLEXIBLE_ARRAY];
1752	} IEMTBCACHE;
1753	/** Pointer to a per-CPU translation block cahce. */
1754	typedef IEMTBCACHE *PIEMTBCACHE;
1755
1756	/** Magic value for IEMTBCACHE (Johnny O'Neal). */
1757	#define IEMTBCACHE_MAGIC UINT32_C(0x19561010)
1758
1759	/** The collision count mask for IEMTBCACHE::apHash entries. */
1760	#define IEMTBCACHE_PTR_COUNT_MASK ((uintptr_t)0x3f)
1761	/** The max collision count for IEMTBCACHE::apHash entries before pruning. */
1762	#define IEMTBCACHE_PTR_MAX_COUNT ((uintptr_t)0x30)
1763	/** Combine a TB pointer and a collision list length into a value for an
1764	* IEMTBCACHE::apHash entry. */
1765	#define IEMTBCACHE_PTR_MAKE(a_pTb, a_cCount) (PIEMTB)((uintptr_t)(a_pTb) \| (a_cCount))
1766	/** Combine a TB pointer and a collision list length into a value for an
1767	* IEMTBCACHE::apHash entry. */
1768	#define IEMTBCACHE_PTR_GET_TB(a_pHashEntry) (PIEMTB)((uintptr_t)(a_pHashEntry) & ~IEMTBCACHE_PTR_COUNT_MASK)
1769	/** Combine a TB pointer and a collision list length into a value for an
1770	* IEMTBCACHE::apHash entry. */
1771	#define IEMTBCACHE_PTR_GET_COUNT(a_pHashEntry) ((uintptr_t)(a_pHashEntry) & IEMTBCACHE_PTR_COUNT_MASK)
1772
1773	/**
1774	* Calculates the hash table slot for a TB from physical PC address and TB flags.
1775	*/
1776	#define IEMTBCACHE_HASH(a_paCache, a_fTbFlags, a_GCPhysPc) \
1777	IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, (a_fTbFlags) & IEMTB_F_KEY_MASK, a_GCPhysPc)
1778
1779	/**
1780	* Calculates the hash table slot for a TB from physical PC address and TB
1781	* flags, ASSUMING the caller has applied IEMTB_F_KEY_MASK to @a a_fTbFlags.
1782	*/
1783	#define IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, a_fTbFlags, a_GCPhysPc) \
1784	(((uint32_t)(a_GCPhysPc) ^ (a_fTbFlags)) & (a_paCache)->uHashMask)
1785
1786
1787	/** @name IEMBRANCHED_F_XXX - Branched indicator (IEMCPU::fTbBranched).
1788	*
1789	* These flags parallels the main IEM_CIMPL_F_BRANCH_XXX flags.
1790	*
1791	* @{ */
1792	/** Value if no branching happened recently. */
1793	#define IEMBRANCHED_F_NO UINT8_C(0x00)
1794	/** Flag set if direct branch, clear if absolute or indirect. */
1795	#define IEMBRANCHED_F_DIRECT UINT8_C(0x01)
1796	/** Flag set if indirect branch, clear if direct or relative. */
1797	#define IEMBRANCHED_F_INDIRECT UINT8_C(0x02)
1798	/** Flag set if relative branch, clear if absolute or indirect. */
1799	#define IEMBRANCHED_F_RELATIVE UINT8_C(0x04)
1800	/** Flag set if conditional branch, clear if unconditional. */
1801	#define IEMBRANCHED_F_CONDITIONAL UINT8_C(0x08)
1802	/** Flag set if it's a far branch. */
1803	#define IEMBRANCHED_F_FAR UINT8_C(0x10)
1804	/** Flag set if the stack pointer is modified. */
1805	#define IEMBRANCHED_F_STACK UINT8_C(0x20)
1806	/** Flag set if the stack pointer and (maybe) the stack segment are modified. */
1807	#define IEMBRANCHED_F_STACK_FAR UINT8_C(0x40)
1808	/** Flag set (by IEM_MC_REL_JMP_XXX) if it's a zero bytes relative jump. */
1809	#define IEMBRANCHED_F_ZERO UINT8_C(0x80)
1810	/** @} */
1811
1812
1813	/**
1814	* The per-CPU IEM state.
1815	*/
1816	typedef struct IEMCPU
1817	{
1818	/** Info status code that needs to be propagated to the IEM caller.
1819	* This cannot be passed internally, as it would complicate all success
1820	* checks within the interpreter making the code larger and almost impossible
1821	* to get right. Instead, we'll store status codes to pass on here. Each
1822	* source of these codes will perform appropriate sanity checks. */
1823	int32_t rcPassUp; /* 0x00 */
1824	/** Execution flag, IEM_F_XXX. */
1825	uint32_t fExec; /* 0x04 */
1826
1827	/** @name Decoder state.
1828	* @{ */
1829	#ifdef IEM_WITH_CODE_TLB
1830	/** The offset of the next instruction byte. */
1831	uint32_t offInstrNextByte; /* 0x08 */
1832	/** The number of bytes available at pbInstrBuf for the current instruction.
1833	* This takes the max opcode length into account so that doesn't need to be
1834	* checked separately. */
1835	uint32_t cbInstrBuf; /* 0x0c */
1836	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
1837	* This can be NULL if the page isn't mappable for some reason, in which
1838	* case we'll do fallback stuff.
1839	*
1840	* If we're executing an instruction from a user specified buffer,
1841	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
1842	* aligned pointer but pointer to the user data.
1843	*
1844	* For instructions crossing pages, this will start on the first page and be
1845	* advanced to the next page by the time we've decoded the instruction. This
1846	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
1847	*/
1848	uint8_t const pbInstrBuf; / 0x10 */
1849	# if ARCH_BITS == 32
1850	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
1851	# endif
1852	/** The program counter corresponding to pbInstrBuf.
1853	* This is set to a non-canonical address when we need to invalidate it. */
1854	uint64_t uInstrBufPc; /* 0x18 */
1855	/** The guest physical address corresponding to pbInstrBuf. */
1856	RTGCPHYS GCPhysInstrBuf; /* 0x20 */
1857	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
1858	* This takes the CS segment limit into account.
1859	* @note Set to zero when the code TLB is flushed to trigger TLB reload. */
1860	uint16_t cbInstrBufTotal; /* 0x28 */
1861	/** Offset into pbInstrBuf of the first byte of the current instruction.
1862	* Can be negative to efficiently handle cross page instructions. */
1863	int16_t offCurInstrStart; /* 0x2a */
1864
1865	# ifndef IEM_WITH_OPAQUE_DECODER_STATE
1866	/** The prefix mask (IEM_OP_PRF_XXX). */
1867	uint32_t fPrefixes; /* 0x2c */
1868	/** The extra REX ModR/M register field bit (REX.R << 3). */
1869	uint8_t uRexReg; /* 0x30 */
1870	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1871	* (REX.B << 3). */
1872	uint8_t uRexB; /* 0x31 */
1873	/** The extra REX SIB index field bit (REX.X << 3). */
1874	uint8_t uRexIndex; /* 0x32 */
1875
1876	/** The effective segment register (X86_SREG_XXX). */
1877	uint8_t iEffSeg; /* 0x33 */
1878
1879	/** The offset of the ModR/M byte relative to the start of the instruction. */
1880	uint8_t offModRm; /* 0x34 */
1881
1882	# ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
1883	/** The current offset into abOpcode. */
1884	uint8_t offOpcode; /* 0x35 */
1885	# else
1886	uint8_t bUnused; /* 0x35 */
1887	# endif
1888	# else /* IEM_WITH_OPAQUE_DECODER_STATE */
1889	uint8_t abOpaqueDecoderPart1[0x36 - 0x2c];
1890	# endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1891
1892	#else /* !IEM_WITH_CODE_TLB */
1893	# ifndef IEM_WITH_OPAQUE_DECODER_STATE
1894	/** The size of what has currently been fetched into abOpcode. */
1895	uint8_t cbOpcode; /* 0x08 */
1896	/** The current offset into abOpcode. */
1897	uint8_t offOpcode; /* 0x09 */
1898	/** The offset of the ModR/M byte relative to the start of the instruction. */
1899	uint8_t offModRm; /* 0x0a */
1900
1901	/** The effective segment register (X86_SREG_XXX). */
1902	uint8_t iEffSeg; /* 0x0b */
1903
1904	/** The prefix mask (IEM_OP_PRF_XXX). */
1905	uint32_t fPrefixes; /* 0x0c */
1906	/** The extra REX ModR/M register field bit (REX.R << 3). */
1907	uint8_t uRexReg; /* 0x10 */
1908	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1909	* (REX.B << 3). */
1910	uint8_t uRexB; /* 0x11 */
1911	/** The extra REX SIB index field bit (REX.X << 3). */
1912	uint8_t uRexIndex; /* 0x12 */
1913
1914	# else /* IEM_WITH_OPAQUE_DECODER_STATE */
1915	uint8_t abOpaqueDecoderPart1[0x13 - 0x08];
1916	# endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1917	#endif /* !IEM_WITH_CODE_TLB */
1918
1919	#ifndef IEM_WITH_OPAQUE_DECODER_STATE
1920	/** The effective operand mode. */
1921	IEMMODE enmEffOpSize; /* 0x36, 0x13 */
1922	/** The default addressing mode. */
1923	IEMMODE enmDefAddrMode; /* 0x37, 0x14 */
1924	/** The effective addressing mode. */
1925	IEMMODE enmEffAddrMode; /* 0x38, 0x15 */
1926	/** The default operand mode. */
1927	IEMMODE enmDefOpSize; /* 0x39, 0x16 */
1928
1929	/** Prefix index (VEX.pp) for two byte and three byte tables. */
1930	uint8_t idxPrefix; /* 0x3a, 0x17 */
1931	/** 3rd VEX/EVEX/XOP register.
1932	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
1933	uint8_t uVex3rdReg; /* 0x3b, 0x18 */
1934	/** The VEX/EVEX/XOP length field. */
1935	uint8_t uVexLength; /* 0x3c, 0x19 */
1936	/** Additional EVEX stuff. */
1937	uint8_t fEvexStuff; /* 0x3d, 0x1a */
1938
1939	# ifndef IEM_WITH_CODE_TLB
1940	/** Explicit alignment padding. */
1941	uint8_t abAlignment2a[1]; /* 0x1b */
1942	# endif
1943	/** The FPU opcode (FOP). */
1944	uint16_t uFpuOpcode; /* 0x3e, 0x1c */
1945	# ifndef IEM_WITH_CODE_TLB
1946	/** Explicit alignment padding. */
1947	uint8_t abAlignment2b[2]; /* 0x1e */
1948	# endif
1949
1950	/** The opcode bytes. */
1951	uint8_t abOpcode[15]; /* 0x40, 0x20 */
1952	/** Explicit alignment padding. */
1953	# ifdef IEM_WITH_CODE_TLB
1954	//uint8_t abAlignment2c[0x4f - 0x4f]; /* 0x4f */
1955	# else
1956	uint8_t abAlignment2c[0x4f - 0x2f]; /* 0x2f */
1957	# endif
1958
1959	#else /* IEM_WITH_OPAQUE_DECODER_STATE */
1960	# ifdef IEM_WITH_CODE_TLB
1961	uint8_t abOpaqueDecoderPart2[0x4f - 0x36];
1962	# else
1963	uint8_t abOpaqueDecoderPart2[0x4f - 0x13];
1964	# endif
1965	#endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1966	/** @} */
1967
1968
1969	/** The number of active guest memory mappings. */
1970	uint8_t cActiveMappings; /* 0x4f, 0x4f */
1971
1972	/** Records for tracking guest memory mappings. */
1973	struct
1974	{
1975	/** The address of the mapped bytes. */
1976	R3R0PTRTYPE(void *) pv;
1977	/** The access flags (IEM_ACCESS_XXX).
1978	* IEM_ACCESS_INVALID if the entry is unused. */
1979	uint32_t fAccess;
1980	#if HC_ARCH_BITS == 64
1981	uint32_t u32Alignment4; /*< Alignment padding. /
1982	#endif
1983	} aMemMappings[3]; /* 0x50 LB 0x30 */
1984
1985	/** Locking records for the mapped memory. */
1986	union
1987	{
1988	PGMPAGEMAPLOCK Lock;
1989	uint64_t au64Padding[2];
1990	} aMemMappingLocks[3]; /* 0x80 LB 0x30 */
1991
1992	/** Bounce buffer info.
1993	* This runs in parallel to aMemMappings. */
1994	struct
1995	{
1996	/** The physical address of the first byte. */
1997	RTGCPHYS GCPhysFirst;
1998	/** The physical address of the second page. */
1999	RTGCPHYS GCPhysSecond;
2000	/** The number of bytes in the first page. */
2001	uint16_t cbFirst;
2002	/** The number of bytes in the second page. */
2003	uint16_t cbSecond;
2004	/** Whether it's unassigned memory. */
2005	bool fUnassigned;
2006	/** Explicit alignment padding. */
2007	bool afAlignment5[3];
2008	} aMemBbMappings[3]; /* 0xb0 LB 0x48 */
2009
2010	/** The flags of the current exception / interrupt. */
2011	uint32_t fCurXcpt; /* 0xf8 */
2012	/** The current exception / interrupt. */
2013	uint8_t uCurXcpt; /* 0xfc */
2014	/** Exception / interrupt recursion depth. */
2015	int8_t cXcptRecursions; /* 0xfb */
2016
2017	/** The next unused mapping index.
2018	* @todo try find room for this up with cActiveMappings. */
2019	uint8_t iNextMapping; /* 0xfd */
2020	uint8_t abAlignment7[1];
2021
2022	/** Bounce buffer storage.
2023	* This runs in parallel to aMemMappings and aMemBbMappings. */
2024	struct
2025	{
2026	uint8_t ab[512];
2027	} aBounceBuffers[3]; /* 0x100 LB 0x600 */
2028
2029
2030	/** Pointer set jump buffer - ring-3 context. */
2031	R3PTRTYPE(jmp_buf *) pJmpBufR3;
2032	/** Pointer set jump buffer - ring-0 context. */
2033	R0PTRTYPE(jmp_buf *) pJmpBufR0;
2034
2035	/** @todo Should move this near @a fCurXcpt later. */
2036	/** The CR2 for the current exception / interrupt. */
2037	uint64_t uCurXcptCr2;
2038	/** The error code for the current exception / interrupt. */
2039	uint32_t uCurXcptErr;
2040
2041	/** @name Statistics
2042	* @{ */
2043	/** The number of instructions we've executed. */
2044	uint32_t cInstructions;
2045	/** The number of potential exits. */
2046	uint32_t cPotentialExits;
2047	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
2048	* This may contain uncommitted writes. */
2049	uint32_t cbWritten;
2050	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
2051	uint32_t cRetInstrNotImplemented;
2052	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
2053	uint32_t cRetAspectNotImplemented;
2054	/** Counts informational statuses returned (other than VINF_SUCCESS). */
2055	uint32_t cRetInfStatuses;
2056	/** Counts other error statuses returned. */
2057	uint32_t cRetErrStatuses;
2058	/** Number of times rcPassUp has been used. */
2059	uint32_t cRetPassUpStatus;
2060	/** Number of times RZ left with instruction commit pending for ring-3. */
2061	uint32_t cPendingCommit;
2062	/** Number of misaligned (host sense) atomic instruction accesses. */
2063	uint32_t cMisalignedAtomics;
2064	/** Number of long jumps. */
2065	uint32_t cLongJumps;
2066	/** @} */
2067
2068	/** @name Target CPU information.
2069	* @{ */
2070	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
2071	/** The target CPU. */
2072	uint8_t uTargetCpu;
2073	#else
2074	uint8_t bTargetCpuPadding;
2075	#endif
2076	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
2077	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
2078	* native host support and the 2nd for when there is.
2079	*
2080	* The two values are typically indexed by a g_CpumHostFeatures bit.
2081	*
2082	* This is for instance used for the BSF & BSR instructions where AMD and
2083	* Intel CPUs produce different EFLAGS. */
2084	uint8_t aidxTargetCpuEflFlavour[2];
2085
2086	/** The CPU vendor. */
2087	CPUMCPUVENDOR enmCpuVendor;
2088	/** @} */
2089
2090	/** @name Host CPU information.
2091	* @{ */
2092	/** The CPU vendor. */
2093	CPUMCPUVENDOR enmHostCpuVendor;
2094	/** @} */
2095
2096	/** Counts RDMSR \#GP(0) LogRel(). */
2097	uint8_t cLogRelRdMsr;
2098	/** Counts WRMSR \#GP(0) LogRel(). */
2099	uint8_t cLogRelWrMsr;
2100	/** Alignment padding. */
2101	uint8_t abAlignment9[42];
2102
2103	/** @name Recompilation
2104	* @{ */
2105	/** Pointer to the current translation block.
2106	* This can either be one being executed or one being compiled. */
2107	R3PTRTYPE(PIEMTB) pCurTbR3;
2108	#ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
2109	/** Frame pointer for the last native TB to execute. */
2110	R3PTRTYPE(void *) pvTbFramePointerR3;
2111	#else
2112	R3PTRTYPE(void *) pvUnusedR3;
2113	#endif
2114	#ifdef IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS
2115	/** The saved host floating point control register (MXCSR on x86, FPCR on arm64)
2116	* needing restore when the TB finished, IEMNATIVE_SIMD_FP_CTRL_REG_NOT_MODIFIED indicates the TB
2117	* didn't modify it so we don't need to restore it. */
2118	# ifdef RT_ARCH_AMD64
2119	uint32_t uRegFpCtrl;
2120	/** Temporary copy of MXCSR for stmxcsr/ldmxcsr (so we don't have to fiddle with stack pointers). */
2121	uint32_t uRegMxcsrTmp;
2122	# elif defined(RT_ARCH_ARM64)
2123	uint64_t uRegFpCtrl;
2124	# else
2125	# error "Port me"
2126	# endif
2127	#else
2128	uint64_t u64Unused;
2129	#endif
2130	/** Fixed TB used for threaded recompilation.
2131	* This is allocated once with maxed-out sizes and re-used afterwards. */
2132	R3PTRTYPE(PIEMTB) pThrdCompileTbR3;
2133	/** Pointer to the ring-3 TB cache for this EMT. */
2134	R3PTRTYPE(PIEMTBCACHE) pTbCacheR3;
2135	/** Pointer to the ring-3 TB lookup entry.
2136	* This either points to pTbLookupEntryDummyR3 or an actually lookuptable
2137	* entry, thus it can always safely be used w/o NULL checking. */
2138	R3PTRTYPE(PIEMTB *) ppTbLookupEntryR3;
2139	/** The PC (RIP) at the start of pCurTbR3/pCurTbR0.
2140	* The TBs are based on physical addresses, so this is needed to correleated
2141	* RIP to opcode bytes stored in the TB (AMD-V / VT-x). */
2142	uint64_t uCurTbStartPc;
2143	/** Number of threaded TBs executed. */
2144	uint64_t cTbExecThreaded;
2145	/** Number of native TBs executed. */
2146	uint64_t cTbExecNative;
2147	/** Whether we need to check the opcode bytes for the current instruction.
2148	* This is set by a previous instruction if it modified memory or similar. */
2149	bool fTbCheckOpcodes;
2150	/** Indicates whether and how we just branched - IEMBRANCHED_F_XXX. */
2151	uint8_t fTbBranched;
2152	/** Set when GCPhysInstrBuf is updated because of a page crossing. */
2153	bool fTbCrossedPage;
2154	/** Whether to end the current TB. */
2155	bool fEndTb;
2156	/** Number of instructions before we need emit an IRQ check call again.
2157	* This helps making sure we don't execute too long w/o checking for
2158	* interrupts and immediately following instructions that may enable
2159	* interrupts (e.g. POPF, IRET, STI). With STI an additional hack is
2160	* required to make sure we check following the next instruction as well, see
2161	* fTbCurInstrIsSti. */
2162	uint8_t cInstrTillIrqCheck;
2163	/** Indicates that the current instruction is an STI. This is set by the
2164	* iemCImpl_sti code and subsequently cleared by the recompiler. */
2165	bool fTbCurInstrIsSti;
2166	/** The size of the IEMTB::pabOpcodes allocation in pThrdCompileTbR3. */
2167	uint16_t cbOpcodesAllocated;
2168	/** The current instruction number in a native TB.
2169	* This is set by code that may trigger an unexpected TB exit (throw/longjmp)
2170	* and will be picked up by the TB execution loop. Only used when
2171	* IEMNATIVE_WITH_INSTRUCTION_COUNTING is defined. */
2172	uint8_t idxTbCurInstr;
2173	/** Spaced reserved for recompiler data / alignment. */
2174	bool afRecompilerStuff1[3];
2175	/** The virtual sync time at the last timer poll call. */
2176	uint32_t msRecompilerPollNow;
2177	/** The IEMTB::cUsed value when to attempt native recompilation of a TB. */
2178	uint32_t uTbNativeRecompileAtUsedCount;
2179	/** The IEM_CIMPL_F_XXX mask for the current instruction. */
2180	uint32_t fTbCurInstr;
2181	/** The IEM_CIMPL_F_XXX mask for the previous instruction. */
2182	uint32_t fTbPrevInstr;
2183	/** Strict: Tracking skipped EFLAGS calculations. Any bits set here are
2184	* currently not up to date in EFLAGS. */
2185	uint32_t fSkippingEFlags;
2186	/** Previous GCPhysInstrBuf value - only valid if fTbCrossedPage is set. */
2187	RTGCPHYS GCPhysInstrBufPrev;
2188	/** Pointer to the ring-3 TB allocator for this EMT. */
2189	R3PTRTYPE(PIEMTBALLOCATOR) pTbAllocatorR3;
2190	/** Pointer to the ring-3 executable memory allocator for this EMT. */
2191	R3PTRTYPE(struct IEMEXECMEMALLOCATOR *) pExecMemAllocatorR3;
2192	/** Pointer to the native recompiler state for ring-3. */
2193	R3PTRTYPE(struct IEMRECOMPILERSTATE *) pNativeRecompilerStateR3;
2194	/** Dummy entry for ppTbLookupEntryR3. */
2195	R3PTRTYPE(PIEMTB) pTbLookupEntryDummyR3;
2196
2197	/** Dummy TLB entry used for accesses to pages with databreakpoints. */
2198	IEMTLBENTRY DataBreakpointTlbe;
2199
2200	/** Threaded TB statistics: Times TB execution was broken off before reaching the end. */
2201	STAMCOUNTER StatTbThreadedExecBreaks;
2202	/** Statistics: Times BltIn_CheckIrq breaks out of the TB. */
2203	STAMCOUNTER StatCheckIrqBreaks;
2204	/** Statistics: Times BltIn_CheckMode breaks out of the TB. */
2205	STAMCOUNTER StatCheckModeBreaks;
2206	/** Threaded TB statistics: Times execution break on call with lookup entries. */
2207	STAMCOUNTER StatTbThreadedExecBreaksWithLookup;
2208	/** Threaded TB statistics: Times execution break on call without lookup entries. */
2209	STAMCOUNTER StatTbThreadedExecBreaksWithoutLookup;
2210	/** Statistics: Times a post jump target check missed and had to find new TB. */
2211	STAMCOUNTER StatCheckBranchMisses;
2212	/** Statistics: Times a jump or page crossing required a TB with CS.LIM checking. */
2213	STAMCOUNTER StatCheckNeedCsLimChecking;
2214	/** Statistics: Times a loop was detected within a TB.. */
2215	STAMCOUNTER StatTbLoopInTbDetected;
2216	/** Exec memory allocator statistics: Number of times allocaintg executable memory failed. */
2217	STAMCOUNTER StatNativeExecMemInstrBufAllocFailed;
2218	/** Native TB statistics: Number of fully recompiled TBs. */
2219	STAMCOUNTER StatNativeFullyRecompiledTbs;
2220	/** TB statistics: Number of instructions per TB. */
2221	STAMPROFILE StatTbInstr;
2222	/** TB statistics: Number of TB lookup table entries per TB. */
2223	STAMPROFILE StatTbLookupEntries;
2224	/** Threaded TB statistics: Number of calls per TB. */
2225	STAMPROFILE StatTbThreadedCalls;
2226	/** Native TB statistics: Native code size per TB. */
2227	STAMPROFILE StatTbNativeCode;
2228	/** Native TB statistics: Profiling native recompilation. */
2229	STAMPROFILE StatNativeRecompilation;
2230	/** Native TB statistics: Number of calls per TB that were recompiled properly. */
2231	STAMPROFILE StatNativeCallsRecompiled;
2232	/** Native TB statistics: Number of threaded calls per TB that weren't recompiled. */
2233	STAMPROFILE StatNativeCallsThreaded;
2234	/** Native recompiled execution: TLB hits for data fetches. */
2235	STAMCOUNTER StatNativeTlbHitsForFetch;
2236	/** Native recompiled execution: TLB hits for data stores. */
2237	STAMCOUNTER StatNativeTlbHitsForStore;
2238	/** Native recompiled execution: TLB hits for stack accesses. */
2239	STAMCOUNTER StatNativeTlbHitsForStack;
2240	/** Native recompiled execution: TLB hits for mapped accesses. */
2241	STAMCOUNTER StatNativeTlbHitsForMapped;
2242	/** Native recompiled execution: Code TLB misses for new page. */
2243	STAMCOUNTER StatNativeCodeTlbMissesNewPage;
2244	/** Native recompiled execution: Code TLB hits for new page. */
2245	STAMCOUNTER StatNativeCodeTlbHitsForNewPage;
2246	/** Native recompiled execution: Code TLB misses for new page with offset. */
2247	STAMCOUNTER StatNativeCodeTlbMissesNewPageWithOffset;
2248	/** Native recompiled execution: Code TLB hits for new page with offset. */
2249	STAMCOUNTER StatNativeCodeTlbHitsForNewPageWithOffset;
2250
2251	/** Native recompiler: Number of calls to iemNativeRegAllocFindFree. */
2252	STAMCOUNTER StatNativeRegFindFree;
2253	/** Native recompiler: Number of times iemNativeRegAllocFindFree needed
2254	* to free a variable. */
2255	STAMCOUNTER StatNativeRegFindFreeVar;
2256	/** Native recompiler: Number of times iemNativeRegAllocFindFree did
2257	* not need to free any variables. */
2258	STAMCOUNTER StatNativeRegFindFreeNoVar;
2259	/** Native recompiler: Liveness info freed shadowed guest registers in
2260	* iemNativeRegAllocFindFree. */
2261	STAMCOUNTER StatNativeRegFindFreeLivenessUnshadowed;
2262	/** Native recompiler: Liveness info helped with the allocation in
2263	* iemNativeRegAllocFindFree. */
2264	STAMCOUNTER StatNativeRegFindFreeLivenessHelped;
2265
2266	/** Native recompiler: Number of times status flags calc has been skipped. */
2267	STAMCOUNTER StatNativeEflSkippedArithmetic;
2268	/** Native recompiler: Number of times status flags calc has been skipped. */
2269	STAMCOUNTER StatNativeEflSkippedLogical;
2270
2271	/** Native recompiler: Number of opportunities to skip EFLAGS.CF updating. */
2272	STAMCOUNTER StatNativeLivenessEflCfSkippable;
2273	/** Native recompiler: Number of opportunities to skip EFLAGS.PF updating. */
2274	STAMCOUNTER StatNativeLivenessEflPfSkippable;
2275	/** Native recompiler: Number of opportunities to skip EFLAGS.AF updating. */
2276	STAMCOUNTER StatNativeLivenessEflAfSkippable;
2277	/** Native recompiler: Number of opportunities to skip EFLAGS.ZF updating. */
2278	STAMCOUNTER StatNativeLivenessEflZfSkippable;
2279	/** Native recompiler: Number of opportunities to skip EFLAGS.SF updating. */
2280	STAMCOUNTER StatNativeLivenessEflSfSkippable;
2281	/** Native recompiler: Number of opportunities to skip EFLAGS.OF updating. */
2282	STAMCOUNTER StatNativeLivenessEflOfSkippable;
2283	/** Native recompiler: Number of required EFLAGS.CF updates. */
2284	STAMCOUNTER StatNativeLivenessEflCfRequired;
2285	/** Native recompiler: Number of required EFLAGS.PF updates. */
2286	STAMCOUNTER StatNativeLivenessEflPfRequired;
2287	/** Native recompiler: Number of required EFLAGS.AF updates. */
2288	STAMCOUNTER StatNativeLivenessEflAfRequired;
2289	/** Native recompiler: Number of required EFLAGS.ZF updates. */
2290	STAMCOUNTER StatNativeLivenessEflZfRequired;
2291	/** Native recompiler: Number of required EFLAGS.SF updates. */
2292	STAMCOUNTER StatNativeLivenessEflSfRequired;
2293	/** Native recompiler: Number of required EFLAGS.OF updates. */
2294	STAMCOUNTER StatNativeLivenessEflOfRequired;
2295	/** Native recompiler: Number of potentially delayable EFLAGS.CF updates. */
2296	STAMCOUNTER StatNativeLivenessEflCfDelayable;
2297	/** Native recompiler: Number of potentially delayable EFLAGS.PF updates. */
2298	STAMCOUNTER StatNativeLivenessEflPfDelayable;
2299	/** Native recompiler: Number of potentially delayable EFLAGS.AF updates. */
2300	STAMCOUNTER StatNativeLivenessEflAfDelayable;
2301	/** Native recompiler: Number of potentially delayable EFLAGS.ZF updates. */
2302	STAMCOUNTER StatNativeLivenessEflZfDelayable;
2303	/** Native recompiler: Number of potentially delayable EFLAGS.SF updates. */
2304	STAMCOUNTER StatNativeLivenessEflSfDelayable;
2305	/** Native recompiler: Number of potentially delayable EFLAGS.OF updates. */
2306	STAMCOUNTER StatNativeLivenessEflOfDelayable;
2307
2308	/** Native recompiler: Number of potential PC updates in total. */
2309	STAMCOUNTER StatNativePcUpdateTotal;
2310	/** Native recompiler: Number of PC updates which could be delayed. */
2311	STAMCOUNTER StatNativePcUpdateDelayed;
2312
2313	//#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
2314	/** Native recompiler: Number of calls to iemNativeSimdRegAllocFindFree. */
2315	STAMCOUNTER StatNativeSimdRegFindFree;
2316	/** Native recompiler: Number of times iemNativeSimdRegAllocFindFree needed
2317	* to free a variable. */
2318	STAMCOUNTER StatNativeSimdRegFindFreeVar;
2319	/** Native recompiler: Number of times iemNativeSimdRegAllocFindFree did
2320	* not need to free any variables. */
2321	STAMCOUNTER StatNativeSimdRegFindFreeNoVar;
2322	/** Native recompiler: Liveness info freed shadowed guest registers in
2323	* iemNativeSimdRegAllocFindFree. */
2324	STAMCOUNTER StatNativeSimdRegFindFreeLivenessUnshadowed;
2325	/** Native recompiler: Liveness info helped with the allocation in
2326	* iemNativeSimdRegAllocFindFree. */
2327	STAMCOUNTER StatNativeSimdRegFindFreeLivenessHelped;
2328
2329	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks. */
2330	STAMCOUNTER StatNativeMaybeDeviceNotAvailXcptCheckPotential;
2331	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() checks. */
2332	STAMCOUNTER StatNativeMaybeWaitDeviceNotAvailXcptCheckPotential;
2333	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks. */
2334	STAMCOUNTER StatNativeMaybeSseXcptCheckPotential;
2335	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks. */
2336	STAMCOUNTER StatNativeMaybeAvxXcptCheckPotential;
2337
2338	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks omitted. */
2339	STAMCOUNTER StatNativeMaybeDeviceNotAvailXcptCheckOmitted;
2340	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() checks omitted. */
2341	STAMCOUNTER StatNativeMaybeWaitDeviceNotAvailXcptCheckOmitted;
2342	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks omitted. */
2343	STAMCOUNTER StatNativeMaybeSseXcptCheckOmitted;
2344	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks omitted. */
2345	STAMCOUNTER StatNativeMaybeAvxXcptCheckOmitted;
2346	//#endif
2347
2348	/** Native recompiler: The TB finished executing completely without jumping to a an exit label.
2349	* Not availabe in release builds. */
2350	STAMCOUNTER StatNativeTbFinished;
2351	/** Native recompiler: The TB finished executing jumping to the ReturnBreak label. */
2352	STAMCOUNTER StatNativeTbExitReturnBreak;
2353	/** Native recompiler: The TB finished executing jumping to the ReturnBreakFF label. */
2354	STAMCOUNTER StatNativeTbExitReturnBreakFF;
2355	/** Native recompiler: The TB finished executing jumping to the ReturnWithFlags label. */
2356	STAMCOUNTER StatNativeTbExitReturnWithFlags;
2357	/** Native recompiler: The TB finished executing with other non-zero status. */
2358	STAMCOUNTER StatNativeTbExitReturnOtherStatus;
2359	/** Native recompiler: The TB finished executing via throw / long jump. */
2360	STAMCOUNTER StatNativeTbExitLongJump;
2361	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2362	* label, but directly jumped to the next TB, scenario \#1 w/o IRQ checks. */
2363	STAMCOUNTER StatNativeTbExitDirectLinking1NoIrq;
2364	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2365	* label, but directly jumped to the next TB, scenario \#1 with IRQ checks. */
2366	STAMCOUNTER StatNativeTbExitDirectLinking1Irq;
2367	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2368	* label, but directly jumped to the next TB, scenario \#1 w/o IRQ checks. */
2369	STAMCOUNTER StatNativeTbExitDirectLinking2NoIrq;
2370	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2371	* label, but directly jumped to the next TB, scenario \#2 with IRQ checks. */
2372	STAMCOUNTER StatNativeTbExitDirectLinking2Irq;
2373
2374	/** Native recompiler: The TB finished executing jumping to the RaiseDe label. */
2375	STAMCOUNTER StatNativeTbExitRaiseDe;
2376	/** Native recompiler: The TB finished executing jumping to the RaiseUd label. */
2377	STAMCOUNTER StatNativeTbExitRaiseUd;
2378	/** Native recompiler: The TB finished executing jumping to the RaiseSseRelated label. */
2379	STAMCOUNTER StatNativeTbExitRaiseSseRelated;
2380	/** Native recompiler: The TB finished executing jumping to the RaiseAvxRelated label. */
2381	STAMCOUNTER StatNativeTbExitRaiseAvxRelated;
2382	/** Native recompiler: The TB finished executing jumping to the RaiseSseAvxFpRelated label. */
2383	STAMCOUNTER StatNativeTbExitRaiseSseAvxFpRelated;
2384	/** Native recompiler: The TB finished executing jumping to the RaiseNm label. */
2385	STAMCOUNTER StatNativeTbExitRaiseNm;
2386	/** Native recompiler: The TB finished executing jumping to the RaiseGp0 label. */
2387	STAMCOUNTER StatNativeTbExitRaiseGp0;
2388	/** Native recompiler: The TB finished executing jumping to the RaiseMf label. */
2389	STAMCOUNTER StatNativeTbExitRaiseMf;
2390	/** Native recompiler: The TB finished executing jumping to the RaiseXf label. */
2391	STAMCOUNTER StatNativeTbExitRaiseXf;
2392	/** Native recompiler: The TB finished executing jumping to the ObsoleteTb label. */
2393	STAMCOUNTER StatNativeTbExitObsoleteTb;
2394
2395	/** Native recompiler: Failure situations with direct linking scenario \#1.
2396	* Counter with StatNativeTbExitReturnBreak. Not in release builds.
2397	* @{ */
2398	STAMCOUNTER StatNativeTbExitDirectLinking1NoTb;
2399	STAMCOUNTER StatNativeTbExitDirectLinking1MismatchGCPhysPc;
2400	STAMCOUNTER StatNativeTbExitDirectLinking1MismatchFlags;
2401	STAMCOUNTER StatNativeTbExitDirectLinking1PendingIrq;
2402	/** @} */
2403
2404	/** Native recompiler: Failure situations with direct linking scenario \#2.
2405	* Counter with StatNativeTbExitReturnBreak. Not in release builds.
2406	* @{ */
2407	STAMCOUNTER StatNativeTbExitDirectLinking2NoTb;
2408	STAMCOUNTER StatNativeTbExitDirectLinking2MismatchGCPhysPc;
2409	STAMCOUNTER StatNativeTbExitDirectLinking2MismatchFlags;
2410	STAMCOUNTER StatNativeTbExitDirectLinking2PendingIrq;
2411	/** @} */
2412
2413	/** iemMemMap and iemMemMapJmp statistics.
2414	* @{ */
2415	STAMCOUNTER StatMemMapJmp;
2416	STAMCOUNTER StatMemMapNoJmp;
2417	STAMCOUNTER StatMemBounceBufferCrossPage;
2418	STAMCOUNTER StatMemBounceBufferMapPhys;
2419	/** @} */
2420
2421	#ifdef IEM_WITH_TLB_TRACE
2422	uint64_t au64Padding[2];
2423	#else
2424	uint64_t au64Padding[4];
2425	#endif
2426	/** @} */
2427
2428	#ifdef IEM_WITH_TLB_TRACE
2429	/** The end (next) trace entry. */
2430	uint32_t idxTlbTraceEntry;
2431	/** Number of trace entries allocated expressed as a power of two. */
2432	uint32_t cTlbTraceEntriesShift;
2433	/** The trace entries. */
2434	PIEMTLBTRACEENTRY paTlbTraceEntries;
2435	#endif
2436
2437	/** Data TLB.
2438	* @remarks Must be 64-byte aligned. */
2439	IEMTLB DataTlb;
2440	/** Instruction TLB.
2441	* @remarks Must be 64-byte aligned. */
2442	IEMTLB CodeTlb;
2443
2444	/** Exception statistics. */
2445	STAMCOUNTER aStatXcpts[32];
2446	/** Interrupt statistics. */
2447	uint32_t aStatInts[256];
2448
2449	#if defined(VBOX_WITH_STATISTICS) && !defined(DOXYGEN_RUNNING) && !defined(IEM_WITHOUT_INSTRUCTION_STATS)
2450	/** Instruction statistics for ring-0/raw-mode. */
2451	IEMINSTRSTATS StatsRZ;
2452	/** Instruction statistics for ring-3. */
2453	IEMINSTRSTATS StatsR3;
2454	# ifdef VBOX_WITH_IEM_RECOMPILER
2455	/** Statistics per threaded function call.
2456	* Updated by both the threaded and native recompilers. */
2457	uint32_t acThreadedFuncStats[0x6000 /24576/];
2458	# endif
2459	#endif
2460	} IEMCPU;
2461	AssertCompileMemberOffset(IEMCPU, cActiveMappings, 0x4f);
2462	AssertCompileMemberAlignment(IEMCPU, aMemMappings, 16);
2463	AssertCompileMemberAlignment(IEMCPU, aMemMappingLocks, 16);
2464	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 64);
2465	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
2466	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
2467
2468	/** Pointer to the per-CPU IEM state. */
2469	typedef IEMCPU *PIEMCPU;
2470	/** Pointer to the const per-CPU IEM state. */
2471	typedef IEMCPU const *PCIEMCPU;
2472
2473	/** @def IEMNATIVE_SIMD_FP_CTRL_REG_NOT_MODIFIED
2474	* Value indicating the TB didn't modified the floating point control register.
2475	* @note Neither FPCR nor MXCSR accept this as a valid value (MXCSR is not fully populated,
2476	* FPCR has the upper 32-bit reserved), so this is safe. */
2477	#if defined(IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS) \|\| defined(DOXYGEN_RUNNING)
2478	# ifdef RT_ARCH_AMD64
2479	# define IEMNATIVE_SIMD_FP_CTRL_REG_NOT_MODIFIED UINT32_MAX
2480	# elif defined(RT_ARCH_ARM64)
2481	# define IEMNATIVE_SIMD_FP_CTRL_REG_NOT_MODIFIED UINT64_MAX
2482	# else
2483	# error "Port me"
2484	# endif
2485	#endif
2486
2487	/** @def IEM_GET_CTX
2488	* Gets the guest CPU context for the calling EMT.
2489	* @returns PCPUMCTX
2490	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2491	*/
2492	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
2493
2494	/** @def IEM_CTX_ASSERT
2495	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
2496	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2497	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
2498	*/
2499	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) \
2500	AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
2501	("fExtrn=%#RX64 & fExtrnMbz=%#RX64 -> %#RX64\n", \
2502	(a_pVCpu)->cpum.GstCtx.fExtrn, (a_fExtrnMbz), (a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz) ))
2503
2504	/** @def IEM_CTX_IMPORT_RET
2505	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2506	*
2507	* Will call the keep to import the bits as needed.
2508	*
2509	* Returns on import failure.
2510	*
2511	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2512	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2513	*/
2514	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
2515	do { \
2516	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2517	{ /* likely */ } \
2518	else \
2519	{ \
2520	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2521	AssertRCReturn(rcCtxImport, rcCtxImport); \
2522	} \
2523	} while (0)
2524
2525	/** @def IEM_CTX_IMPORT_NORET
2526	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2527	*
2528	* Will call the keep to import the bits as needed.
2529	*
2530	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2531	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2532	*/
2533	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
2534	do { \
2535	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2536	{ /* likely */ } \
2537	else \
2538	{ \
2539	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2540	AssertLogRelRC(rcCtxImport); \
2541	} \
2542	} while (0)
2543
2544	/** @def IEM_CTX_IMPORT_JMP
2545	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2546	*
2547	* Will call the keep to import the bits as needed.
2548	*
2549	* Jumps on import failure.
2550	*
2551	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2552	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2553	*/
2554	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
2555	do { \
2556	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2557	{ /* likely */ } \
2558	else \
2559	{ \
2560	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2561	AssertRCStmt(rcCtxImport, IEM_DO_LONGJMP(pVCpu, rcCtxImport)); \
2562	} \
2563	} while (0)
2564
2565
2566
2567	/** @def IEM_GET_TARGET_CPU
2568	* Gets the current IEMTARGETCPU value.
2569	* @returns IEMTARGETCPU value.
2570	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2571	*/
2572	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
2573	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
2574	#else
2575	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
2576	#endif
2577
2578	/** @def IEM_GET_INSTR_LEN
2579	* Gets the instruction length. */
2580	#ifdef IEM_WITH_CODE_TLB
2581	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
2582	#else
2583	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
2584	#endif
2585
2586	/** @def IEM_TRY_SETJMP
2587	* Wrapper around setjmp / try, hiding all the ugly differences.
2588	*
2589	* @note Use with extreme care as this is a fragile macro.
2590	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2591	* @param a_rcTarget The variable that should receive the status code in case
2592	* of a longjmp/throw.
2593	*/
2594	/** @def IEM_TRY_SETJMP_AGAIN
2595	* For when setjmp / try is used again in the same variable scope as a previous
2596	* IEM_TRY_SETJMP invocation.
2597	*/
2598	/** @def IEM_CATCH_LONGJMP_BEGIN
2599	* Start wrapper for catch / setjmp-else.
2600	*
2601	* This will set up a scope.
2602	*
2603	* @note Use with extreme care as this is a fragile macro.
2604	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2605	* @param a_rcTarget The variable that should receive the status code in case
2606	* of a longjmp/throw.
2607	*/
2608	/** @def IEM_CATCH_LONGJMP_END
2609	* End wrapper for catch / setjmp-else.
2610	*
2611	* This will close the scope set up by IEM_CATCH_LONGJMP_BEGIN and clean up the
2612	* state.
2613	*
2614	* @note Use with extreme care as this is a fragile macro.
2615	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2616	*/
2617	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
2618	# ifdef IEM_WITH_THROW_CATCH
2619	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
2620	a_rcTarget = VINF_SUCCESS; \
2621	try
2622	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
2623	IEM_TRY_SETJMP(a_pVCpu, a_rcTarget)
2624	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
2625	catch (int rcThrown) \
2626	{ \
2627	a_rcTarget = rcThrown
2628	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
2629	} \
2630	((void)0)
2631	# else /* !IEM_WITH_THROW_CATCH */
2632	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
2633	jmp_buf JmpBuf; \
2634	jmp_buf * volatile pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
2635	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
2636	if ((rcStrict = setjmp(JmpBuf)) == 0)
2637	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
2638	pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
2639	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
2640	if ((rcStrict = setjmp(JmpBuf)) == 0)
2641	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
2642	else \
2643	{ \
2644	((void)0)
2645	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
2646	} \
2647	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = pSavedJmpBuf
2648	# endif /* !IEM_WITH_THROW_CATCH */
2649	#endif /* IEM_WITH_SETJMP */
2650
2651
2652	/**
2653	* Shared per-VM IEM data.
2654	*/
2655	typedef struct IEM
2656	{
2657	/** The VMX APIC-access page handler type. */
2658	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
2659	#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
2660	/** Set if the CPUID host call functionality is enabled. */
2661	bool fCpuIdHostCall;
2662	#endif
2663	} IEM;
2664
2665
2666
2667	/** @name IEM_ACCESS_XXX - Access details.
2668	* @{ */
2669	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
2670	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
2671	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
2672	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
2673	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
2674	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
2675	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
2676	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
2677	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
2678	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
2679	/** The writes are partial, so if initialize the bounce buffer with the
2680	* orignal RAM content. */
2681	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
2682	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
2683	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
2684	/** Bounce buffer with ring-3 write pending, first page. */
2685	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
2686	/** Bounce buffer with ring-3 write pending, second page. */
2687	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
2688	/** Not locked, accessed via the TLB. */
2689	#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
2690	/** Atomic access.
2691	* This enables special alignment checks and the VINF_EM_EMULATE_SPLIT_LOCK
2692	* fallback for misaligned stuff. See @bugref{10547}. */
2693	#define IEM_ACCESS_ATOMIC UINT32_C(0x00002000)
2694	/** Valid bit mask. */
2695	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00003fff)
2696	/** Shift count for the TLB flags (upper word). */
2697	#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
2698
2699	/** Atomic read+write data alias. */
2700	#define IEM_ACCESS_DATA_ATOMIC (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA \| IEM_ACCESS_ATOMIC)
2701	/** Read+write data alias. */
2702	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
2703	/** Write data alias. */
2704	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
2705	/** Read data alias. */
2706	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
2707	/** Instruction fetch alias. */
2708	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
2709	/** Stack write alias. */
2710	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
2711	/** Stack read alias. */
2712	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
2713	/** Stack read+write alias. */
2714	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
2715	/** Read system table alias. */
2716	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
2717	/** Read+write system table alias. */
2718	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
2719	/** @} */
2720
2721	/** @name Prefix constants (IEMCPU::fPrefixes)
2722	* @{ */
2723	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
2724	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
2725	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
2726	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
2727	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
2728	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
2729	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
2730
2731	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
2732	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
2733	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
2734
2735	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
2736	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
2737	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
2738
2739	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
2740	#define IEM_OP_PRF_REX_B RT_BIT_32(25) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
2741	#define IEM_OP_PRF_REX_X RT_BIT_32(26) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
2742	#define IEM_OP_PRF_REX_R RT_BIT_32(27) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
2743	/** Mask with all the REX prefix flags.
2744	* This is generally for use when needing to undo the REX prefixes when they
2745	* are followed legacy prefixes and therefore does not immediately preceed
2746	* the first opcode byte.
2747	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
2748	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
2749
2750	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
2751	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
2752	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
2753	/** @} */
2754
2755	/** @name IEMOPFORM_XXX - Opcode forms
2756	* @note These are ORed together with IEMOPHINT_XXX.
2757	* @{ */
2758	/** ModR/M: reg, r/m */
2759	#define IEMOPFORM_RM 0
2760	/** ModR/M: reg, r/m (register) */
2761	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
2762	/** ModR/M: reg, r/m (memory) */
2763	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
2764	/** ModR/M: reg, r/m, imm */
2765	#define IEMOPFORM_RMI 1
2766	/** ModR/M: reg, r/m (register), imm */
2767	#define IEMOPFORM_RMI_REG (IEMOPFORM_RMI \| IEMOPFORM_MOD3)
2768	/** ModR/M: reg, r/m (memory), imm */
2769	#define IEMOPFORM_RMI_MEM (IEMOPFORM_RMI \| IEMOPFORM_NOT_MOD3)
2770	/** ModR/M: reg, r/m, xmm0 */
2771	#define IEMOPFORM_RM0 2
2772	/** ModR/M: reg, r/m (register), xmm0 */
2773	#define IEMOPFORM_RM0_REG (IEMOPFORM_RM0 \| IEMOPFORM_MOD3)
2774	/** ModR/M: reg, r/m (memory), xmm0 */
2775	#define IEMOPFORM_RM0_MEM (IEMOPFORM_RM0 \| IEMOPFORM_NOT_MOD3)
2776	/** ModR/M: r/m, reg */
2777	#define IEMOPFORM_MR 3
2778	/** ModR/M: r/m (register), reg */
2779	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
2780	/** ModR/M: r/m (memory), reg */
2781	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
2782	/** ModR/M: r/m, reg, imm */
2783	#define IEMOPFORM_MRI 4
2784	/** ModR/M: r/m (register), reg, imm */
2785	#define IEMOPFORM_MRI_REG (IEMOPFORM_MRI \| IEMOPFORM_MOD3)
2786	/** ModR/M: r/m (memory), reg, imm */
2787	#define IEMOPFORM_MRI_MEM (IEMOPFORM_MRI \| IEMOPFORM_NOT_MOD3)
2788	/** ModR/M: r/m only */
2789	#define IEMOPFORM_M 5
2790	/** ModR/M: r/m only (register). */
2791	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
2792	/** ModR/M: r/m only (memory). */
2793	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
2794	/** ModR/M: r/m, imm */
2795	#define IEMOPFORM_MI 6
2796	/** ModR/M: r/m (register), imm */
2797	#define IEMOPFORM_MI_REG (IEMOPFORM_MI \| IEMOPFORM_MOD3)
2798	/** ModR/M: r/m (memory), imm */
2799	#define IEMOPFORM_MI_MEM (IEMOPFORM_MI \| IEMOPFORM_NOT_MOD3)
2800	/** ModR/M: r/m, 1 (shift and rotate instructions) */
2801	#define IEMOPFORM_M1 7
2802	/** ModR/M: r/m (register), 1. */
2803	#define IEMOPFORM_M1_REG (IEMOPFORM_M1 \| IEMOPFORM_MOD3)
2804	/** ModR/M: r/m (memory), 1. */
2805	#define IEMOPFORM_M1_MEM (IEMOPFORM_M1 \| IEMOPFORM_NOT_MOD3)
2806	/** ModR/M: r/m, CL (shift and rotate instructions)
2807	* @todo This should just've been a generic fixed register. But the python
2808	* code doesn't needs more convincing. */
2809	#define IEMOPFORM_M_CL 8
2810	/** ModR/M: r/m (register), CL. */
2811	#define IEMOPFORM_M_CL_REG (IEMOPFORM_M_CL \| IEMOPFORM_MOD3)
2812	/** ModR/M: r/m (memory), CL. */
2813	#define IEMOPFORM_M_CL_MEM (IEMOPFORM_M_CL \| IEMOPFORM_NOT_MOD3)
2814	/** ModR/M: reg only */
2815	#define IEMOPFORM_R 9
2816
2817	/** VEX+ModR/M: reg, r/m */
2818	#define IEMOPFORM_VEX_RM 16
2819	/** VEX+ModR/M: reg, r/m (register) */
2820	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
2821	/** VEX+ModR/M: reg, r/m (memory) */
2822	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
2823	/** VEX+ModR/M: r/m, reg */
2824	#define IEMOPFORM_VEX_MR 17
2825	/** VEX+ModR/M: r/m (register), reg */
2826	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
2827	/** VEX+ModR/M: r/m (memory), reg */
2828	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
2829	/** VEX+ModR/M: r/m, reg, imm8 */
2830	#define IEMOPFORM_VEX_MRI 18
2831	/** VEX+ModR/M: r/m (register), reg, imm8 */
2832	#define IEMOPFORM_VEX_MRI_REG (IEMOPFORM_VEX_MRI \| IEMOPFORM_MOD3)
2833	/** VEX+ModR/M: r/m (memory), reg, imm8 */
2834	#define IEMOPFORM_VEX_MRI_MEM (IEMOPFORM_VEX_MRI \| IEMOPFORM_NOT_MOD3)
2835	/** VEX+ModR/M: r/m only */
2836	#define IEMOPFORM_VEX_M 19
2837	/** VEX+ModR/M: r/m only (register). */
2838	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
2839	/** VEX+ModR/M: r/m only (memory). */
2840	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
2841	/** VEX+ModR/M: reg only */
2842	#define IEMOPFORM_VEX_R 20
2843	/** VEX+ModR/M: reg, vvvv, r/m */
2844	#define IEMOPFORM_VEX_RVM 21
2845	/** VEX+ModR/M: reg, vvvv, r/m (register). */
2846	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
2847	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
2848	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
2849	/** VEX+ModR/M: reg, vvvv, r/m, imm */
2850	#define IEMOPFORM_VEX_RVMI 22
2851	/** VEX+ModR/M: reg, vvvv, r/m (register), imm. */
2852	#define IEMOPFORM_VEX_RVMI_REG (IEMOPFORM_VEX_RVMI \| IEMOPFORM_MOD3)
2853	/** VEX+ModR/M: reg, vvvv, r/m (memory), imm. */
2854	#define IEMOPFORM_VEX_RVMI_MEM (IEMOPFORM_VEX_RVMI \| IEMOPFORM_NOT_MOD3)
2855	/** VEX+ModR/M: reg, vvvv, r/m, imm(reg) */
2856	#define IEMOPFORM_VEX_RVMR 23
2857	/** VEX+ModR/M: reg, vvvv, r/m (register), imm(reg). */
2858	#define IEMOPFORM_VEX_RVMR_REG (IEMOPFORM_VEX_RVMI \| IEMOPFORM_MOD3)
2859	/** VEX+ModR/M: reg, vvvv, r/m (memory), imm(reg). */
2860	#define IEMOPFORM_VEX_RVMR_MEM (IEMOPFORM_VEX_RVMI \| IEMOPFORM_NOT_MOD3)
2861	/** VEX+ModR/M: reg, r/m, vvvv */
2862	#define IEMOPFORM_VEX_RMV 24
2863	/** VEX+ModR/M: reg, r/m, vvvv (register). */
2864	#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV \| IEMOPFORM_MOD3)
2865	/** VEX+ModR/M: reg, r/m, vvvv (memory). */
2866	#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV \| IEMOPFORM_NOT_MOD3)
2867	/** VEX+ModR/M: reg, r/m, imm8 */
2868	#define IEMOPFORM_VEX_RMI 25
2869	/** VEX+ModR/M: reg, r/m, imm8 (register). */
2870	#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI \| IEMOPFORM_MOD3)
2871	/** VEX+ModR/M: reg, r/m, imm8 (memory). */
2872	#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI \| IEMOPFORM_NOT_MOD3)
2873	/** VEX+ModR/M: r/m, vvvv, reg */
2874	#define IEMOPFORM_VEX_MVR 26
2875	/** VEX+ModR/M: r/m, vvvv, reg (register) */
2876	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
2877	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
2878	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
2879	/** VEX+ModR/M+/n: vvvv, r/m */
2880	#define IEMOPFORM_VEX_VM 27
2881	/** VEX+ModR/M+/n: vvvv, r/m (register) */
2882	#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM \| IEMOPFORM_MOD3)
2883	/** VEX+ModR/M+/n: vvvv, r/m (memory) */
2884	#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM \| IEMOPFORM_NOT_MOD3)
2885	/** VEX+ModR/M+/n: vvvv, r/m, imm8 */
2886	#define IEMOPFORM_VEX_VMI 28
2887	/** VEX+ModR/M+/n: vvvv, r/m, imm8 (register) */
2888	#define IEMOPFORM_VEX_VMI_REG (IEMOPFORM_VEX_VMI \| IEMOPFORM_MOD3)
2889	/** VEX+ModR/M+/n: vvvv, r/m, imm8 (memory) */
2890	#define IEMOPFORM_VEX_VMI_MEM (IEMOPFORM_VEX_VMI \| IEMOPFORM_NOT_MOD3)
2891
2892	/** Fixed register instruction, no R/M. */
2893	#define IEMOPFORM_FIXED 32
2894
2895	/** The r/m is a register. */
2896	#define IEMOPFORM_MOD3 RT_BIT_32(8)
2897	/** The r/m is a memory access. */
2898	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
2899	/** @} */
2900
2901	/** @name IEMOPHINT_XXX - Additional Opcode Hints
2902	* @note These are ORed together with IEMOPFORM_XXX.
2903	* @{ */
2904	/** Ignores the operand size prefix (66h). */
2905	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
2906	/** Ignores REX.W (aka WIG). */
2907	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
2908	/** Both the operand size prefixes (66h + REX.W) are ignored. */
2909	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
2910	/** Allowed with the lock prefix. */
2911	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
2912	/** The VEX.L value is ignored (aka LIG). */
2913	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
2914	/** The VEX.L value must be zero (i.e. 128-bit width only). */
2915	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
2916	/** The VEX.L value must be one (i.e. 256-bit width only). */
2917	#define IEMOPHINT_VEX_L_ONE RT_BIT_32(14)
2918	/** The VEX.V value must be zero. */
2919	#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(15)
2920	/** The REX.W/VEX.V value must be zero. */
2921	#define IEMOPHINT_REX_W_ZERO RT_BIT_32(16)
2922	#define IEMOPHINT_VEX_W_ZERO IEMOPHINT_REX_W_ZERO
2923	/** The REX.W/VEX.V value must be one. */
2924	#define IEMOPHINT_REX_W_ONE RT_BIT_32(17)
2925	#define IEMOPHINT_VEX_W_ONE IEMOPHINT_REX_W_ONE
2926
2927	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
2928	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
2929	/** @} */
2930
2931	/**
2932	* Possible hardware task switch sources.
2933	*/
2934	typedef enum IEMTASKSWITCH
2935	{
2936	/** Task switch caused by an interrupt/exception. */
2937	IEMTASKSWITCH_INT_XCPT = 1,
2938	/** Task switch caused by a far CALL. */
2939	IEMTASKSWITCH_CALL,
2940	/** Task switch caused by a far JMP. */
2941	IEMTASKSWITCH_JUMP,
2942	/** Task switch caused by an IRET. */
2943	IEMTASKSWITCH_IRET
2944	} IEMTASKSWITCH;
2945	AssertCompileSize(IEMTASKSWITCH, 4);
2946
2947	/**
2948	* Possible CrX load (write) sources.
2949	*/
2950	typedef enum IEMACCESSCRX
2951	{
2952	/** CrX access caused by 'mov crX' instruction. */
2953	IEMACCESSCRX_MOV_CRX,
2954	/** CrX (CR0) write caused by 'lmsw' instruction. */
2955	IEMACCESSCRX_LMSW,
2956	/** CrX (CR0) write caused by 'clts' instruction. */
2957	IEMACCESSCRX_CLTS,
2958	/** CrX (CR0) read caused by 'smsw' instruction. */
2959	IEMACCESSCRX_SMSW
2960	} IEMACCESSCRX;
2961
2962	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2963	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
2964	*
2965	* These flags provide further context to SLAT page-walk failures that could not be
2966	* determined by PGM (e.g, PGM is not privy to memory access permissions).
2967	*
2968	* @{
2969	*/
2970	/** Translating a nested-guest linear address failed accessing a nested-guest
2971	* physical address. */
2972	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
2973	/** Translating a nested-guest linear address failed accessing a
2974	* paging-structure entry or updating accessed/dirty bits. */
2975	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
2976	/** @} */
2977
2978	DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
2979	# ifndef IN_RING3
2980	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
2981	# endif
2982	#endif
2983
2984	/**
2985	* Indicates to the verifier that the given flag set is undefined.
2986	*
2987	* Can be invoked again to add more flags.
2988	*
2989	* This is a NOOP if the verifier isn't compiled in.
2990	*
2991	* @note We're temporarily keeping this until code is converted to new
2992	* disassembler style opcode handling.
2993	*/
2994	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
2995
2996
2997	/** @def IEM_DECL_IMPL_TYPE
2998	* For typedef'ing an instruction implementation function.
2999	*
3000	* @param a_RetType The return type.
3001	* @param a_Name The name of the type.
3002	* @param a_ArgList The argument list enclosed in parentheses.
3003	*/
3004
3005	/** @def IEM_DECL_IMPL_DEF
3006	* For defining an instruction implementation function.
3007	*
3008	* @param a_RetType The return type.
3009	* @param a_Name The name of the type.
3010	* @param a_ArgList The argument list enclosed in parentheses.
3011	*/
3012
3013	#if defined(__GNUC__) && defined(RT_ARCH_X86)
3014	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
3015	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
3016	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
3017	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
3018	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
3019	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
3020
3021	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
3022	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
3023	a_RetType (__fastcall a_Name) a_ArgList
3024	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
3025	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
3026	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
3027	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
3028
3029	#elif __cplusplus >= 201700 /* P0012R1 support */
3030	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
3031	a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
3032	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
3033	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
3034	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
3035	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
3036
3037	#else
3038	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
3039	a_RetType (VBOXCALL a_Name) a_ArgList
3040	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
3041	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
3042	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
3043	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
3044
3045	#endif
3046
3047	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
3048	RT_C_DECLS_BEGIN
3049	extern uint8_t const g_afParity[256];
3050	RT_C_DECLS_END
3051
3052
3053	/** @name Arithmetic assignment operations on bytes (binary).
3054	* @{ */
3055	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU8, (uint32_t fEFlagsIn, uint8_t *pu8Dst, uint8_t u8Src));
3056	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
3057	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
3058	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
3059	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
3060	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
3061	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
3062	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
3063	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
3064	/** @} */
3065
3066	/** @name Arithmetic assignment operations on words (binary).
3067	* @{ */
3068	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU16, (uint32_t fEFlagsIn, uint16_t *pu16Dst, uint16_t u16Src));
3069	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
3070	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
3071	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
3072	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
3073	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
3074	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
3075	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
3076	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
3077	/** @} */
3078
3079
3080	/** @name Arithmetic assignment operations on double words (binary).
3081	* @{ */
3082	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU32, (uint32_t fEFlagsIn, uint32_t *pu32Dst, uint32_t u32Src));
3083	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
3084	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
3085	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
3086	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
3087	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
3088	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
3089	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
3090	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
3091	FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
3092	FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
3093	FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
3094	/** @} */
3095
3096	/** @name Arithmetic assignment operations on quad words (binary).
3097	* @{ */
3098	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU64, (uint32_t fEFlagsIn, uint64_t *pu64Dst, uint64_t u64Src));
3099	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
3100	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
3101	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
3102	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
3103	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
3104	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
3105	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
3106	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
3107	FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
3108	FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
3109	FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
3110	/** @} */
3111
3112	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU8, (uint32_t fEFlagsIn, uint8_t const *pu8Dst, uint8_t u8Src));
3113	typedef FNIEMAIMPLBINROU8 *PFNIEMAIMPLBINROU8;
3114	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU16,(uint32_t fEFlagsIn, uint16_t const *pu16Dst, uint16_t u16Src));
3115	typedef FNIEMAIMPLBINROU16 *PFNIEMAIMPLBINROU16;
3116	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU32,(uint32_t fEFlagsIn, uint32_t const *pu32Dst, uint32_t u32Src));
3117	typedef FNIEMAIMPLBINROU32 *PFNIEMAIMPLBINROU32;
3118	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU64,(uint32_t fEFlagsIn, uint64_t const *pu64Dst, uint64_t u64Src));
3119	typedef FNIEMAIMPLBINROU64 *PFNIEMAIMPLBINROU64;
3120
3121	/** @name Compare operations (thrown in with the binary ops).
3122	* @{ */
3123	FNIEMAIMPLBINROU8 iemAImpl_cmp_u8;
3124	FNIEMAIMPLBINROU16 iemAImpl_cmp_u16;
3125	FNIEMAIMPLBINROU32 iemAImpl_cmp_u32;
3126	FNIEMAIMPLBINROU64 iemAImpl_cmp_u64;
3127	/** @} */
3128
3129	/** @name Test operations (thrown in with the binary ops).
3130	* @{ */
3131	FNIEMAIMPLBINROU8 iemAImpl_test_u8;
3132	FNIEMAIMPLBINROU16 iemAImpl_test_u16;
3133	FNIEMAIMPLBINROU32 iemAImpl_test_u32;
3134	FNIEMAIMPLBINROU64 iemAImpl_test_u64;
3135	/** @} */
3136
3137	/** @name Bit operations operations (thrown in with the binary ops).
3138	* @{ */
3139	FNIEMAIMPLBINROU16 iemAImpl_bt_u16;
3140	FNIEMAIMPLBINROU32 iemAImpl_bt_u32;
3141	FNIEMAIMPLBINROU64 iemAImpl_bt_u64;
3142	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
3143	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
3144	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
3145	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
3146	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
3147	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
3148	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
3149	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
3150	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
3151	/** @} */
3152
3153	/** @name Arithmetic three operand operations on double words (binary).
3154	* @{ */
3155	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t pEFlags));
3156	typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
3157	FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
3158	FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
3159	FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
3160	/** @} */
3161
3162	/** @name Arithmetic three operand operations on quad words (binary).
3163	* @{ */
3164	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t pEFlags));
3165	typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
3166	FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
3167	FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
3168	FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
3169	/** @} */
3170
3171	/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
3172	* @{ */
3173	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
3174	typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
3175	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
3176	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
3177	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
3178	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
3179	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
3180	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
3181	/** @} */
3182
3183	/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
3184	* @{ */
3185	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
3186	typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
3187	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
3188	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
3189	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
3190	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
3191	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
3192	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
3193	/** @} */
3194
3195	/** @name MULX 32-bit and 64-bit.
3196	* @{ */
3197	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t puDst1, uint32_t puDst2, uint32_t uSrc1, uint32_t uSrc2));
3198	typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
3199	FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
3200
3201	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t puDst1, uint64_t puDst2, uint64_t uSrc1, uint64_t uSrc2));
3202	typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
3203	FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
3204	/** @} */
3205
3206
3207	/** @name Exchange memory with register operations.
3208	* @{ */
3209	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
3210	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
3211	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
3212	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
3213	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
3214	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
3215	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
3216	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
3217	/** @} */
3218
3219	/** @name Exchange and add operations.
3220	* @{ */
3221	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
3222	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
3223	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
3224	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
3225	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
3226	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
3227	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
3228	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
3229	/** @} */
3230
3231	/** @name Compare and exchange.
3232	* @{ */
3233	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
3234	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
3235	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
3236	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
3237	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
3238	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
3239	#if ARCH_BITS == 32
3240	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
3241	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
3242	#else
3243	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
3244	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
3245	#endif
3246	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
3247	uint32_t *pEFlags));
3248	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
3249	uint32_t *pEFlags));
3250	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
3251	uint32_t *pEFlags));
3252	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
3253	uint32_t *pEFlags));
3254	#ifndef RT_ARCH_ARM64
3255	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
3256	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
3257	#endif
3258	/** @} */
3259
3260	/** @name Memory ordering
3261	* @{ */
3262	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
3263	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
3264	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
3265	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
3266	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
3267	#ifndef RT_ARCH_ARM64
3268	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
3269	#endif
3270	/** @} */
3271
3272	/** @name Double precision shifts
3273	* @{ */
3274	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
3275	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
3276	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
3277	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
3278	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
3279	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
3280	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
3281	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
3282	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
3283	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
3284	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
3285	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
3286	/** @} */
3287
3288
3289	/** @name Bit search operations (thrown in with the binary ops).
3290	* @{ */
3291	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
3292	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
3293	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
3294	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
3295	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
3296	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
3297	FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
3298	FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
3299	FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
3300	FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
3301	FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
3302	FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
3303	FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
3304	FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
3305	FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
3306	/** @} */
3307
3308	/** @name Signed multiplication operations (thrown in with the binary ops).
3309	* @{ */
3310	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
3311	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
3312	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
3313	/** @} */
3314
3315	/** @name Arithmetic assignment operations on bytes (unary).
3316	* @{ */
3317	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
3318	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
3319	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
3320	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
3321	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
3322	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
3323	/** @} */
3324
3325	/** @name Arithmetic assignment operations on words (unary).
3326	* @{ */
3327	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
3328	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
3329	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
3330	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
3331	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
3332	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
3333	/** @} */
3334
3335	/** @name Arithmetic assignment operations on double words (unary).
3336	* @{ */
3337	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
3338	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
3339	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
3340	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
3341	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
3342	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
3343	/** @} */
3344
3345	/** @name Arithmetic assignment operations on quad words (unary).
3346	* @{ */
3347	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
3348	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
3349	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
3350	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
3351	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
3352	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
3353	/** @} */
3354
3355
3356	/** @name Shift operations on bytes (Group 2).
3357	* @{ */
3358	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU8,(uint32_t fEFlagsIn, uint8_t *pu8Dst, uint8_t cShift));
3359	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
3360	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
3361	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
3362	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
3363	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
3364	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
3365	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
3366	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
3367	/** @} */
3368
3369	/** @name Shift operations on words (Group 2).
3370	* @{ */
3371	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU16,(uint32_t fEFlagsIn, uint16_t *pu16Dst, uint8_t cShift));
3372	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
3373	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
3374	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
3375	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
3376	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
3377	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
3378	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
3379	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
3380	/** @} */
3381
3382	/** @name Shift operations on double words (Group 2).
3383	* @{ */
3384	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU32,(uint32_t fEFlagsIn, uint32_t *pu32Dst, uint8_t cShift));
3385	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
3386	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
3387	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
3388	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
3389	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
3390	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
3391	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
3392	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
3393	/** @} */
3394
3395	/** @name Shift operations on words (Group 2).
3396	* @{ */
3397	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU64,(uint32_t fEFlagsIn, uint64_t *pu64Dst, uint8_t cShift));
3398	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
3399	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
3400	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
3401	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
3402	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
3403	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
3404	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
3405	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
3406	/** @} */
3407
3408	/** @name Multiplication and division operations.
3409	* @{ */
3410	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
3411	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
3412	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
3413	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
3414	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
3415	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
3416
3417	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
3418	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
3419	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
3420	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
3421	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
3422	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
3423
3424	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
3425	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
3426	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
3427	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
3428	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
3429	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
3430
3431	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
3432	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
3433	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
3434	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
3435	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
3436	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
3437	/** @} */
3438
3439	/** @name Byte Swap.
3440	* @{ */
3441	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
3442	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
3443	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
3444	/** @} */
3445
3446	/** @name Misc.
3447	* @{ */
3448	FNIEMAIMPLBINU16 iemAImpl_arpl;
3449	/** @} */
3450
3451	/** @name RDRAND and RDSEED
3452	* @{ */
3453	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU16,(uint16_t puDst, uint32_t pEFlags));
3454	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU32,(uint32_t puDst, uint32_t pEFlags));
3455	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU64,(uint64_t puDst, uint32_t pEFlags));
3456	typedef FNIEMAIMPLRDRANDSEEDU16 *PFNIEMAIMPLRDRANDSEEDU16;
3457	typedef FNIEMAIMPLRDRANDSEEDU32 *PFNIEMAIMPLRDRANDSEEDU32;
3458	typedef FNIEMAIMPLRDRANDSEEDU64 *PFNIEMAIMPLRDRANDSEEDU64;
3459
3460	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdrand_u16, iemAImpl_rdrand_u16_fallback;
3461	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdrand_u32, iemAImpl_rdrand_u32_fallback;
3462	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdrand_u64, iemAImpl_rdrand_u64_fallback;
3463	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdseed_u16, iemAImpl_rdseed_u16_fallback;
3464	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdseed_u32, iemAImpl_rdseed_u32_fallback;
3465	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdseed_u64, iemAImpl_rdseed_u64_fallback;
3466	/** @} */
3467
3468	/** @name ADOX and ADCX
3469	* @{ */
3470	FNIEMAIMPLBINU32 iemAImpl_adcx_u32, iemAImpl_adcx_u32_fallback;
3471	FNIEMAIMPLBINU64 iemAImpl_adcx_u64, iemAImpl_adcx_u64_fallback;
3472	FNIEMAIMPLBINU32 iemAImpl_adox_u32, iemAImpl_adox_u32_fallback;
3473	FNIEMAIMPLBINU64 iemAImpl_adox_u64, iemAImpl_adox_u64_fallback;
3474	/** @} */
3475
3476	/** @name FPU operations taking a 32-bit float argument
3477	* @{ */
3478	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3479	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
3480	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
3481
3482	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3483	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
3484	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
3485
3486	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
3487	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
3488	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
3489	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
3490	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
3491	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
3492	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
3493
3494	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
3495	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3496	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
3497	/** @} */
3498
3499	/** @name FPU operations taking a 64-bit float argument
3500	* @{ */
3501	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3502	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
3503	typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
3504
3505	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3506	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
3507	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
3508
3509	FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
3510	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
3511	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
3512	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
3513	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
3514	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
3515	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
3516
3517	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
3518	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3519	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
3520	/** @} */
3521
3522	/** @name FPU operations taking a 80-bit float argument
3523	* @{ */
3524	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3525	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3526	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
3527	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
3528	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
3529	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
3530	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
3531	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
3532	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
3533	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
3534	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
3535	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
3536
3537	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
3538	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
3539	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
3540
3541	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3542	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3543	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
3544	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
3545	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
3546
3547	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
3548	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3549	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
3550	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
3551	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
3552
3553	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
3554	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
3555	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
3556	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
3557	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
3558	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
3559	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
3560	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
3561	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
3562
3563	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
3564	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
3565	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
3566	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
3567
3568	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
3569	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
3570	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
3571	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
3572	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
3573	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
3574	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
3575	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
3576	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
3577
3578	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
3579	PCRTFLOAT80U pr80Val));
3580	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
3581	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
3582	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
3583	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
3584
3585	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
3586	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3587	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
3588
3589	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
3590	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3591	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
3592
3593	/** @} */
3594
3595	/** @name FPU operations taking a 16-bit signed integer argument
3596	* @{ */
3597	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3598	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
3599	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
3600	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3601	int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
3602	typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
3603
3604	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
3605	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
3606	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
3607	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
3608	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
3609	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
3610
3611	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3612	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
3613	typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
3614	FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
3615
3616	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
3617	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
3618	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
3619	/** @} */
3620
3621	/** @name FPU operations taking a 32-bit signed integer argument
3622	* @{ */
3623	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3624	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
3625	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
3626	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3627	int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
3628	typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
3629
3630	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
3631	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
3632	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
3633	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
3634	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
3635	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
3636
3637	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3638	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
3639	typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
3640	FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
3641
3642	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
3643	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
3644	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
3645	/** @} */
3646
3647	/** @name FPU operations taking a 64-bit signed integer argument
3648	* @{ */
3649	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3650	int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
3651	typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
3652
3653	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
3654	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
3655	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
3656	/** @} */
3657
3658
3659	/** Temporary type representing a 256-bit vector register. */
3660	typedef struct { uint64_t au64[4]; } IEMVMM256;
3661	/** Temporary type pointing to a 256-bit vector register. */
3662	typedef IEMVMM256 *PIEMVMM256;
3663	/** Temporary type pointing to a const 256-bit vector register. */
3664	typedef IEMVMM256 *PCIEMVMM256;
3665
3666
3667	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
3668	* @{ */
3669	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t puDst, uint64_t const puSrc));
3670	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
3671	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF2U128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
3672	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
3673	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF2U256,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86YMMREG puSrc));
3674	typedef FNIEMAIMPLMEDIAF2U256 *PFNIEMAIMPLMEDIAF2U256;
3675	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF3U128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3676	typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
3677	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF3U256,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
3678	typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
3679	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t puDst, uint64_t const puSrc));
3680	typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
3681	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
3682	typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
3683	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
3684	typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
3685	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
3686	typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
3687	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256,(PRTUINT256U puDst, PCRTUINT256U puSrc));
3688	typedef FNIEMAIMPLMEDIAOPTF2U256 *PFNIEMAIMPLMEDIAOPTF2U256;
3689	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
3690	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
3691	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
3692	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
3693	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddb_u64, iemAImpl_paddsb_u64, iemAImpl_paddusb_u64;
3694	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddw_u64, iemAImpl_paddsw_u64, iemAImpl_paddusw_u64;
3695	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddd_u64;
3696	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddq_u64;
3697	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubb_u64, iemAImpl_psubsb_u64, iemAImpl_psubusb_u64;
3698	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubw_u64, iemAImpl_psubsw_u64, iemAImpl_psubusw_u64;
3699	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubd_u64;
3700	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubq_u64;
3701	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmaddwd_u64, iemAImpl_pmaddwd_u64_fallback;
3702	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmullw_u64, iemAImpl_pmulhw_u64;
3703	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pminub_u64, iemAImpl_pmaxub_u64;
3704	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pminsw_u64, iemAImpl_pmaxsw_u64;
3705	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsb_u64, iemAImpl_pabsb_u64_fallback;
3706	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsw_u64, iemAImpl_pabsw_u64_fallback;
3707	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsd_u64, iemAImpl_pabsd_u64_fallback;
3708	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignb_u64, iemAImpl_psignb_u64_fallback;
3709	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignw_u64, iemAImpl_psignw_u64_fallback;
3710	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignd_u64, iemAImpl_psignd_u64_fallback;
3711	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddw_u64, iemAImpl_phaddw_u64_fallback;
3712	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddd_u64, iemAImpl_phaddd_u64_fallback;
3713	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubw_u64, iemAImpl_phsubw_u64_fallback;
3714	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubd_u64, iemAImpl_phsubd_u64_fallback;
3715	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddsw_u64, iemAImpl_phaddsw_u64_fallback;
3716	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubsw_u64, iemAImpl_phsubsw_u64_fallback;
3717	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmaddubsw_u64, iemAImpl_pmaddubsw_u64_fallback;
3718	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhrsw_u64, iemAImpl_pmulhrsw_u64_fallback;
3719	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmuludq_u64;
3720	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllw_u64, iemAImpl_psrlw_u64, iemAImpl_psraw_u64;
3721	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pslld_u64, iemAImpl_psrld_u64, iemAImpl_psrad_u64;
3722	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllq_u64, iemAImpl_psrlq_u64;
3723	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packsswb_u64, iemAImpl_packuswb_u64;
3724	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packssdw_u64;
3725	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhuw_u64;
3726	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pavgb_u64, iemAImpl_pavgw_u64;
3727	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psadbw_u64;
3728
3729	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
3730	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
3731	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
3732	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
3733	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
3734	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
3735	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddb_u128, iemAImpl_paddsb_u128, iemAImpl_paddusb_u128;
3736	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddw_u128, iemAImpl_paddsw_u128, iemAImpl_paddusw_u128;
3737	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddd_u128;
3738	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddq_u128;
3739	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubb_u128, iemAImpl_psubsb_u128, iemAImpl_psubusb_u128;
3740	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubw_u128, iemAImpl_psubsw_u128, iemAImpl_psubusw_u128;
3741	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubd_u128;
3742	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubq_u128;
3743	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmullw_u128, iemAImpl_pmullw_u128_fallback;
3744	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhw_u128;
3745	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback;
3746	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddwd_u128, iemAImpl_pmaddwd_u128_fallback;
3747	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminub_u128;
3748	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback;
3749	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback;
3750	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback;
3751	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback;
3752	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsw_u128, iemAImpl_pminsw_u128_fallback;
3753	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxub_u128;
3754	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback;
3755	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback;
3756	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback;
3757	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsw_u128;
3758	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback;
3759	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback;
3760	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback;
3761	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback;
3762	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback;
3763	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback;
3764	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback;
3765	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback;
3766	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback;
3767	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback;
3768	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback;
3769	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback;
3770	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback;
3771	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback;
3772	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback;
3773	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuludq_u128;
3774	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddwd_u128, iemAImpl_pmaddwd_u128_fallback;
3775	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packsswb_u128, iemAImpl_packuswb_u128;
3776	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packssdw_u128, iemAImpl_packusdw_u128;
3777	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllw_u128, iemAImpl_psrlw_u128, iemAImpl_psraw_u128;
3778	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pslld_u128, iemAImpl_psrld_u128, iemAImpl_psrad_u128;
3779	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllq_u128, iemAImpl_psrlq_u128;
3780	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhuw_u128;
3781	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pavgb_u128, iemAImpl_pavgw_u128;
3782	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psadbw_u128;
3783	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback;
3784	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpcklps_u128, iemAImpl_unpcklpd_u128;
3785	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpckhps_u128, iemAImpl_unpckhpd_u128;
3786	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback;
3787
3788	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
3789	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
3790	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
3791	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
3792	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
3793	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
3794	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
3795	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
3796	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
3797	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
3798	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
3799	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
3800	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
3801	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
3802	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
3803	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
3804	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
3805	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
3806	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
3807	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
3808	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
3809	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminub_u128, iemAImpl_vpminub_u128_fallback;
3810	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminuw_u128, iemAImpl_vpminuw_u128_fallback;
3811	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminud_u128, iemAImpl_vpminud_u128_fallback;
3812	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsb_u128, iemAImpl_vpminsb_u128_fallback;
3813	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsw_u128, iemAImpl_vpminsw_u128_fallback;
3814	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsd_u128, iemAImpl_vpminsd_u128_fallback;
3815	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxub_u128, iemAImpl_vpmaxub_u128_fallback;
3816	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxuw_u128, iemAImpl_vpmaxuw_u128_fallback;
3817	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxud_u128, iemAImpl_vpmaxud_u128_fallback;
3818	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsb_u128, iemAImpl_vpmaxsb_u128_fallback;
3819	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsw_u128, iemAImpl_vpmaxsw_u128_fallback;
3820	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsd_u128, iemAImpl_vpmaxsd_u128_fallback;
3821	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpacksswb_u128, iemAImpl_vpacksswb_u128_fallback;
3822	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackssdw_u128, iemAImpl_vpackssdw_u128_fallback;
3823	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackuswb_u128, iemAImpl_vpackuswb_u128_fallback;
3824	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackusdw_u128, iemAImpl_vpackusdw_u128_fallback;
3825	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmullw_u128, iemAImpl_vpmullw_u128_fallback;
3826	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulld_u128, iemAImpl_vpmulld_u128_fallback;
3827	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhw_u128, iemAImpl_vpmulhw_u128_fallback;
3828	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhuw_u128, iemAImpl_vpmulhuw_u128_fallback;
3829	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgb_u128, iemAImpl_vpavgb_u128_fallback;
3830	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgw_u128, iemAImpl_vpavgw_u128_fallback;
3831	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignb_u128, iemAImpl_vpsignb_u128_fallback;
3832	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignw_u128, iemAImpl_vpsignw_u128_fallback;
3833	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignd_u128, iemAImpl_vpsignd_u128_fallback;
3834	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddw_u128, iemAImpl_vphaddw_u128_fallback;
3835	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddd_u128, iemAImpl_vphaddd_u128_fallback;
3836	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubw_u128, iemAImpl_vphsubw_u128_fallback;
3837	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubd_u128, iemAImpl_vphsubd_u128_fallback;
3838	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddsw_u128, iemAImpl_vphaddsw_u128_fallback;
3839	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubsw_u128, iemAImpl_vphsubsw_u128_fallback;
3840	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddubsw_u128, iemAImpl_vpmaddubsw_u128_fallback;
3841	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhrsw_u128, iemAImpl_vpmulhrsw_u128_fallback;
3842	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsadbw_u128, iemAImpl_vpsadbw_u128_fallback;
3843	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuldq_u128, iemAImpl_vpmuldq_u128_fallback;
3844	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuludq_u128, iemAImpl_vpmuludq_u128_fallback;
3845	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsb_u128, iemAImpl_vpsubsb_u128_fallback;
3846	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsw_u128, iemAImpl_vpsubsw_u128_fallback;
3847	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusb_u128, iemAImpl_vpsubusb_u128_fallback;
3848	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusw_u128, iemAImpl_vpsubusw_u128_fallback;
3849	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusb_u128, iemAImpl_vpaddusb_u128_fallback;
3850	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusw_u128, iemAImpl_vpaddusw_u128_fallback;
3851	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsb_u128, iemAImpl_vpaddsb_u128_fallback;
3852	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsw_u128, iemAImpl_vpaddsw_u128_fallback;
3853	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllw_u128, iemAImpl_vpsllw_u128_fallback;
3854	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpslld_u128, iemAImpl_vpslld_u128_fallback;
3855	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllq_u128, iemAImpl_vpsllq_u128_fallback;
3856	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsraw_u128, iemAImpl_vpsraw_u128_fallback;
3857	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrad_u128, iemAImpl_vpsrad_u128_fallback;
3858	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlw_u128, iemAImpl_vpsrlw_u128_fallback;
3859	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrld_u128, iemAImpl_vpsrld_u128_fallback;
3860	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlq_u128, iemAImpl_vpsrlq_u128_fallback;
3861	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddwd_u128, iemAImpl_vpmaddwd_u128_fallback;
3862
3863	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback;
3864	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsw_u128, iemAImpl_vpabsd_u128_fallback;
3865	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsd_u128, iemAImpl_vpabsw_u128_fallback;
3866	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback;
3867
3868	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
3869	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
3870	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
3871	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
3872	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
3873	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
3874	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
3875	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
3876	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
3877	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
3878	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
3879	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
3880	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
3881	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
3882	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
3883	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
3884	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
3885	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
3886	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
3887	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
3888	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
3889	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminub_u256, iemAImpl_vpminub_u256_fallback;
3890	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminuw_u256, iemAImpl_vpminuw_u256_fallback;
3891	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminud_u256, iemAImpl_vpminud_u256_fallback;
3892	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsb_u256, iemAImpl_vpminsb_u256_fallback;
3893	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsw_u256, iemAImpl_vpminsw_u256_fallback;
3894	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsd_u256, iemAImpl_vpminsd_u256_fallback;
3895	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxub_u256, iemAImpl_vpmaxub_u256_fallback;
3896	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxuw_u256, iemAImpl_vpmaxuw_u256_fallback;
3897	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxud_u256, iemAImpl_vpmaxud_u256_fallback;
3898	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsb_u256, iemAImpl_vpmaxsb_u256_fallback;
3899	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsw_u256, iemAImpl_vpmaxsw_u256_fallback;
3900	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsd_u256, iemAImpl_vpmaxsd_u256_fallback;
3901	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpacksswb_u256, iemAImpl_vpacksswb_u256_fallback;
3902	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackssdw_u256, iemAImpl_vpackssdw_u256_fallback;
3903	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackuswb_u256, iemAImpl_vpackuswb_u256_fallback;
3904	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackusdw_u256, iemAImpl_vpackusdw_u256_fallback;
3905	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmullw_u256, iemAImpl_vpmullw_u256_fallback;
3906	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulld_u256, iemAImpl_vpmulld_u256_fallback;
3907	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhw_u256, iemAImpl_vpmulhw_u256_fallback;
3908	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhuw_u256, iemAImpl_vpmulhuw_u256_fallback;
3909	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgb_u256, iemAImpl_vpavgb_u256_fallback;
3910	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgw_u256, iemAImpl_vpavgw_u256_fallback;
3911	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignb_u256, iemAImpl_vpsignb_u256_fallback;
3912	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignw_u256, iemAImpl_vpsignw_u256_fallback;
3913	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignd_u256, iemAImpl_vpsignd_u256_fallback;
3914	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddw_u256, iemAImpl_vphaddw_u256_fallback;
3915	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddd_u256, iemAImpl_vphaddd_u256_fallback;
3916	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubw_u256, iemAImpl_vphsubw_u256_fallback;
3917	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubd_u256, iemAImpl_vphsubd_u256_fallback;
3918	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddsw_u256, iemAImpl_vphaddsw_u256_fallback;
3919	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubsw_u256, iemAImpl_vphsubsw_u256_fallback;
3920	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddubsw_u256, iemAImpl_vpmaddubsw_u256_fallback;
3921	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhrsw_u256, iemAImpl_vpmulhrsw_u256_fallback;
3922	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsadbw_u256, iemAImpl_vpsadbw_u256_fallback;
3923	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuldq_u256, iemAImpl_vpmuldq_u256_fallback;
3924	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuludq_u256, iemAImpl_vpmuludq_u256_fallback;
3925	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsb_u256, iemAImpl_vpsubsb_u256_fallback;
3926	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsw_u256, iemAImpl_vpsubsw_u256_fallback;
3927	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusb_u256, iemAImpl_vpsubusb_u256_fallback;
3928	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusw_u256, iemAImpl_vpsubusw_u256_fallback;
3929	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusb_u256, iemAImpl_vpaddusb_u256_fallback;
3930	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusw_u256, iemAImpl_vpaddusw_u256_fallback;
3931	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsb_u256, iemAImpl_vpaddsb_u256_fallback;
3932	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsw_u256, iemAImpl_vpaddsw_u256_fallback;
3933	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllw_u256, iemAImpl_vpsllw_u256_fallback;
3934	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpslld_u256, iemAImpl_vpslld_u256_fallback;
3935	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllq_u256, iemAImpl_vpsllq_u256_fallback;
3936	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsraw_u256, iemAImpl_vpsraw_u256_fallback;
3937	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrad_u256, iemAImpl_vpsrad_u256_fallback;
3938	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlw_u256, iemAImpl_vpsrlw_u256_fallback;
3939	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrld_u256, iemAImpl_vpsrld_u256_fallback;
3940	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlq_u256, iemAImpl_vpsrlq_u256_fallback;
3941	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddwd_u256, iemAImpl_vpmaddwd_u256_fallback;
3942	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermps_u256, iemAImpl_vpermps_u256_fallback;
3943	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermd_u256, iemAImpl_vpermd_u256_fallback;
3944
3945	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback;
3946	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsw_u256, iemAImpl_vpabsw_u256_fallback;
3947	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsd_u256, iemAImpl_vpabsd_u256_fallback;
3948	/** @} */
3949
3950	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
3951	* @{ */
3952	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
3953	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
3954	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
3955	iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
3956	iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
3957	iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback,
3958	iemAImpl_vunpcklps_u128, iemAImpl_vunpcklps_u128_fallback,
3959	iemAImpl_vunpcklpd_u128, iemAImpl_vunpcklpd_u128_fallback,
3960	iemAImpl_vunpckhps_u128, iemAImpl_vunpckhps_u128_fallback,
3961	iemAImpl_vunpckhpd_u128, iemAImpl_vunpckhpd_u128_fallback;
3962
3963	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
3964	iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
3965	iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
3966	iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback,
3967	iemAImpl_vunpcklps_u256, iemAImpl_vunpcklps_u256_fallback,
3968	iemAImpl_vunpcklpd_u256, iemAImpl_vunpcklpd_u256_fallback,
3969	iemAImpl_vunpckhps_u256, iemAImpl_vunpckhps_u256_fallback,
3970	iemAImpl_vunpckhpd_u256, iemAImpl_vunpckhpd_u256_fallback;
3971	/** @} */
3972
3973	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
3974	* @{ */
3975	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
3976	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
3977	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
3978	iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
3979	iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
3980	iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
3981	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
3982	iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
3983	iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
3984	iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
3985	/** @} */
3986
3987	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
3988	* @{ */
3989	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3990	typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
3991	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
3992	typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
3993	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t puDst, uint64_t const puSrc, uint8_t bEvil));
3994	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
3995	#ifndef IEM_WITHOUT_ASSEMBLY
3996	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
3997	#endif
3998	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
3999	/** @} */
4000
4001	/** @name Media (SSE/MMX/AVX) operation: Shift Immediate Stuff (evil)
4002	* @{ */
4003	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU64,(uint64_t *puDst, uint8_t bShift));
4004	typedef FNIEMAIMPLMEDIAPSHIFTU64 *PFNIEMAIMPLMEDIAPSHIFTU64;
4005	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU128,(PRTUINT128U puDst, uint8_t bShift));
4006	typedef FNIEMAIMPLMEDIAPSHIFTU128 *PFNIEMAIMPLMEDIAPSHIFTU128;
4007	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU256,(PRTUINT256U puDst, uint8_t bShift));
4008	typedef FNIEMAIMPLMEDIAPSHIFTU256 *PFNIEMAIMPLMEDIAPSHIFTU256;
4009	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psllw_imm_u64, iemAImpl_pslld_imm_u64, iemAImpl_psllq_imm_u64;
4010	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psrlw_imm_u64, iemAImpl_psrld_imm_u64, iemAImpl_psrlq_imm_u64;
4011	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psraw_imm_u64, iemAImpl_psrad_imm_u64;
4012	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psllw_imm_u128, iemAImpl_pslld_imm_u128, iemAImpl_psllq_imm_u128;
4013	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psrlw_imm_u128, iemAImpl_psrld_imm_u128, iemAImpl_psrlq_imm_u128;
4014	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psraw_imm_u128, iemAImpl_psrad_imm_u128;
4015	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_pslldq_imm_u128, iemAImpl_psrldq_imm_u128;
4016	/** @} */
4017
4018	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
4019	* @{ */
4020	IEM_DECL_IMPL_DEF(void, iemAImpl_maskmovq_u64,(uint64_t puMem, uint64_t const puSrc, uint64_t const *puMsk));
4021	IEM_DECL_IMPL_DEF(void, iemAImpl_maskmovdqu_u128,(PRTUINT128U puMem, PCRTUINT128U puSrc, PCRTUINT128U puMsk));
4022	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t pu64Dst, uint64_t const puSrc));
4023	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
4024	#ifndef IEM_WITHOUT_ASSEMBLY
4025	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
4026	#endif
4027	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
4028	/** @} */
4029
4030	/** @name Media (SSE/MMX/AVX) operations: Variable Blend Packed Bytes/R32/R64.
4031	* @{ */
4032	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puMask));
4033	typedef FNIEMAIMPLBLENDU128 *PFNIEMAIMPLBLENDU128;
4034	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, PCRTUINT128U puMask));
4035	typedef FNIEMAIMPLAVXBLENDU128 *PFNIEMAIMPLAVXBLENDU128;
4036	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, PCRTUINT256U puMask));
4037	typedef FNIEMAIMPLAVXBLENDU256 *PFNIEMAIMPLAVXBLENDU256;
4038
4039	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128;
4040	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128_fallback;
4041	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128;
4042	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128_fallback;
4043	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256;
4044	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256_fallback;
4045
4046	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128;
4047	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128_fallback;
4048	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128;
4049	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128_fallback;
4050	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256;
4051	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256_fallback;
4052
4053	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128;
4054	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128_fallback;
4055	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128;
4056	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128_fallback;
4057	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256;
4058	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256_fallback;
4059	/** @} */
4060
4061
4062	/** @name Media (SSE/MMX/AVX) operation: Sort this later
4063	* @{ */
4064	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
4065	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
4066	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4067	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4068	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4069
4070	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
4071	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
4072	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
4073	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4074	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4075
4076	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
4077	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
4078	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
4079	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4080	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4081
4082	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
4083	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
4084	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4085	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4086	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4087
4088	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
4089	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
4090	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
4091	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4092	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4093
4094	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
4095	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
4096	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4097	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4098	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4099
4100	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
4101	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
4102	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4103	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4104	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4105
4106	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
4107	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
4108	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
4109	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4110	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4111
4112	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
4113	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
4114	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
4115	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4116	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4117
4118	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
4119	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
4120	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4121	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4122	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4123
4124	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
4125	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
4126	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
4127	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4128	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4129
4130	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
4131	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
4132	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4133	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4134	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4135
4136	IEM_DECL_IMPL_DEF(void, iemAImpl_shufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
4137	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
4138	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
4139	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
4140	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
4141
4142	IEM_DECL_IMPL_DEF(void, iemAImpl_shufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
4143	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
4144	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
4145	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
4146	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
4147
4148	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
4149	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64_fallback,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
4150
4151	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4152	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4153	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4154	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
4155	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
4156
4157	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4158	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4159	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4160	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
4161	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
4162
4163
4164	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
4165	typedef FNIEMAIMPLMEDIAOPTF2U128IMM8 *PFNIEMAIMPLMEDIAOPTF2U128IMM8;
4166	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
4167	typedef FNIEMAIMPLMEDIAOPTF2U256IMM8 *PFNIEMAIMPLMEDIAOPTF2U256IMM8;
4168	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
4169	typedef FNIEMAIMPLMEDIAOPTF3U128IMM8 *PFNIEMAIMPLMEDIAOPTF3U128IMM8;
4170	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
4171	typedef FNIEMAIMPLMEDIAOPTF3U256IMM8 *PFNIEMAIMPLMEDIAOPTF3U256IMM8;
4172
4173	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback;
4174	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback;
4175	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback;
4176	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback;
4177
4178	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpalignr_u128, iemAImpl_vpalignr_u128_fallback;
4179	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendw_u128, iemAImpl_vpblendw_u128_fallback;
4180	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendd_u128, iemAImpl_vpblendd_u128_fallback;
4181	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendps_u128, iemAImpl_vblendps_u128_fallback;
4182	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendpd_u128, iemAImpl_vblendpd_u128_fallback;
4183
4184	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpalignr_u256, iemAImpl_vpalignr_u256_fallback;
4185	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendw_u256, iemAImpl_vpblendw_u256_fallback;
4186	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendd_u256, iemAImpl_vpblendd_u256_fallback;
4187	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendps_u256, iemAImpl_vblendps_u256_fallback;
4188	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendpd_u256, iemAImpl_vblendpd_u256_fallback;
4189	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2i128_u256, iemAImpl_vperm2i128_u256_fallback;
4190	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2f128_u256, iemAImpl_vperm2f128_u256_fallback;
4191
4192	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesimc_u128, iemAImpl_aesimc_u128_fallback;
4193	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenc_u128, iemAImpl_aesenc_u128_fallback;
4194	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenclast_u128, iemAImpl_aesenclast_u128_fallback;
4195	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdec_u128, iemAImpl_aesdec_u128_fallback;
4196	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdeclast_u128, iemAImpl_aesdeclast_u128_fallback;
4197
4198	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesimc_u128, iemAImpl_vaesimc_u128_fallback;
4199	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vaesenc_u128, iemAImpl_vaesenc_u128_fallback;
4200	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vaesenclast_u128, iemAImpl_vaesenclast_u128_fallback;
4201	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vaesdec_u128, iemAImpl_vaesdec_u128_fallback;
4202	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vaesdeclast_u128, iemAImpl_vaesdeclast_u128_fallback;
4203
4204	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback;
4205
4206	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vaeskeygenassist_u128, iemAImpl_vaeskeygenassist_u128_fallback;
4207
4208	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1nexte_u128, iemAImpl_sha1nexte_u128_fallback;
4209	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg1_u128, iemAImpl_sha1msg1_u128_fallback;
4210	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg2_u128, iemAImpl_sha1msg2_u128_fallback;
4211	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg1_u128, iemAImpl_sha256msg1_u128_fallback;
4212	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg2_u128, iemAImpl_sha256msg2_u128_fallback;
4213	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_sha1rnds4_u128, iemAImpl_sha1rnds4_u128_fallback;
4214	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
4215	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
4216
4217	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermq_u256, iemAImpl_vpermq_u256_fallback;
4218	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermpd_u256, iemAImpl_vpermpd_u256_fallback;
4219
4220	typedef struct IEMPCMPISTRXSRC
4221	{
4222	RTUINT128U uSrc1;
4223	RTUINT128U uSrc2;
4224	} IEMPCMPISTRXSRC;
4225	typedef IEMPCMPISTRXSRC *PIEMPCMPISTRXSRC;
4226	typedef const IEMPCMPISTRXSRC *PCIEMPCMPISTRXSRC;
4227
4228	typedef struct IEMPCMPESTRXSRC
4229	{
4230	RTUINT128U uSrc1;
4231	RTUINT128U uSrc2;
4232	uint64_t u64Rax;
4233	uint64_t u64Rdx;
4234	} IEMPCMPESTRXSRC;
4235	typedef IEMPCMPESTRXSRC *PIEMPCMPESTRXSRC;
4236	typedef const IEMPCMPESTRXSRC *PCIEMPCMPESTRXSRC;
4237
4238	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLPCMPISTRIU128IMM8,(uint32_t *pEFlags, PCRTUINT128U pSrc1, PCRTUINT128U pSrc2, uint8_t bEvil));
4239	typedef FNIEMAIMPLPCMPISTRIU128IMM8 *PFNIEMAIMPLPCMPISTRIU128IMM8;
4240	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
4241	typedef FNIEMAIMPLPCMPESTRIU128IMM8 *PFNIEMAIMPLPCMPESTRIU128IMM8;
4242
4243	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
4244	typedef FNIEMAIMPLPCMPISTRMU128IMM8 *PFNIEMAIMPLPCMPISTRMU128IMM8;
4245	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
4246	typedef FNIEMAIMPLPCMPESTRMU128IMM8 *PFNIEMAIMPLPCMPESTRMU128IMM8;
4247
4248	FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_pcmpistri_u128, iemAImpl_pcmpistri_u128_fallback;
4249	FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_pcmpestri_u128, iemAImpl_pcmpestri_u128_fallback;
4250	FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_pcmpistrm_u128, iemAImpl_pcmpistrm_u128_fallback;
4251	FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_pcmpestrm_u128, iemAImpl_pcmpestrm_u128_fallback;
4252	FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_vpcmpistri_u128, iemAImpl_vpcmpistri_u128_fallback;
4253	FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_vpcmpestri_u128, iemAImpl_vpcmpestri_u128_fallback;
4254	FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_vpcmpistrm_u128, iemAImpl_vpcmpistrm_u128_fallback;
4255	FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_vpcmpestrm_u128, iemAImpl_vpcmpestrm_u128_fallback;
4256
4257
4258	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pclmulqdq_u128, iemAImpl_pclmulqdq_u128_fallback;
4259	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback;
4260
4261	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_mpsadbw_u128, iemAImpl_mpsadbw_u128_fallback;
4262	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vmpsadbw_u128, iemAImpl_vmpsadbw_u128_fallback;
4263	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vmpsadbw_u256, iemAImpl_vmpsadbw_u256_fallback;
4264
4265	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsllw_imm_u128, iemAImpl_vpsllw_imm_u128_fallback;
4266	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsllw_imm_u256, iemAImpl_vpsllw_imm_u256_fallback;
4267	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpslld_imm_u128, iemAImpl_vpslld_imm_u128_fallback;
4268	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpslld_imm_u256, iemAImpl_vpslld_imm_u256_fallback;
4269	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsllq_imm_u128, iemAImpl_vpsllq_imm_u128_fallback;
4270	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsllq_imm_u256, iemAImpl_vpsllq_imm_u256_fallback;
4271	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4272	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4273	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4274	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4275
4276	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsraw_imm_u128, iemAImpl_vpsraw_imm_u128_fallback;
4277	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsraw_imm_u256, iemAImpl_vpsraw_imm_u256_fallback;
4278	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrad_imm_u128, iemAImpl_vpsrad_imm_u128_fallback;
4279	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrad_imm_u256, iemAImpl_vpsrad_imm_u256_fallback;
4280
4281	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrlw_imm_u128, iemAImpl_vpsrlw_imm_u128_fallback;
4282	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrlw_imm_u256, iemAImpl_vpsrlw_imm_u256_fallback;
4283	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrld_imm_u128, iemAImpl_vpsrld_imm_u128_fallback;
4284	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrld_imm_u256, iemAImpl_vpsrld_imm_u256_fallback;
4285	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrlq_imm_u128, iemAImpl_vpsrlq_imm_u128_fallback;
4286	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrlq_imm_u256, iemAImpl_vpsrlq_imm_u256_fallback;
4287	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4288	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4289	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4290	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4291
4292	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpermilps_u128, iemAImpl_vpermilps_u128_fallback;
4293	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vpermilps_imm_u128, iemAImpl_vpermilps_imm_u128_fallback;
4294	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermilps_u256, iemAImpl_vpermilps_u256_fallback;
4295	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermilps_imm_u256, iemAImpl_vpermilps_imm_u256_fallback;
4296
4297	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpermilpd_u128, iemAImpl_vpermilpd_u128_fallback;
4298	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vpermilpd_imm_u128, iemAImpl_vpermilpd_imm_u128_fallback;
4299	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermilpd_u256, iemAImpl_vpermilpd_u256_fallback;
4300	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermilpd_imm_u256, iemAImpl_vpermilpd_imm_u256_fallback;
4301
4302	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllvd_u128, iemAImpl_vpsllvd_u128_fallback;
4303	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllvd_u256, iemAImpl_vpsllvd_u256_fallback;
4304	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllvq_u128, iemAImpl_vpsllvq_u128_fallback;
4305	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllvq_u256, iemAImpl_vpsllvq_u256_fallback;
4306	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsravd_u128, iemAImpl_vpsravd_u128_fallback;
4307	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsravd_u256, iemAImpl_vpsravd_u256_fallback;
4308	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlvd_u128, iemAImpl_vpsrlvd_u128_fallback;
4309	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlvd_u256, iemAImpl_vpsrlvd_u256_fallback;
4310	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlvq_u128, iemAImpl_vpsrlvq_u128_fallback;
4311	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlvq_u256, iemAImpl_vpsrlvq_u256_fallback;
4312	/** @} */
4313
4314	/** @name Media Odds and Ends
4315	* @{ */
4316	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
4317	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
4318	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
4319	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
4320	FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
4321	FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
4322	FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
4323	FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
4324
4325	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
4326	typedef FNIEMAIMPLF2EFL128 *PFNIEMAIMPLF2EFL128;
4327	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
4328	typedef FNIEMAIMPLF2EFL256 *PFNIEMAIMPLF2EFL256;
4329	FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
4330	FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
4331	FNIEMAIMPLF2EFL128 iemAImpl_vtestps_u128, iemAImpl_vtestps_u128_fallback;
4332	FNIEMAIMPLF2EFL256 iemAImpl_vtestps_u256, iemAImpl_vtestps_u256_fallback;
4333	FNIEMAIMPLF2EFL128 iemAImpl_vtestpd_u128, iemAImpl_vtestpd_u128_fallback;
4334	FNIEMAIMPLF2EFL256 iemAImpl_vtestpd_u256, iemAImpl_vtestpd_u256_fallback;
4335
4336	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32U64,(uint32_t uMxCsrIn, int32_t pi32Dst, const uint64_t pu64Src)); /* pu64Src is a double precision floating point. */
4337	typedef FNIEMAIMPLSSEF2I32U64 *PFNIEMAIMPLSSEF2I32U64;
4338	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64U64,(uint32_t uMxCsrIn, int64_t pi64Dst, const uint64_t pu64Src)); /* pu64Src is a double precision floating point. */
4339	typedef FNIEMAIMPLSSEF2I64U64 *PFNIEMAIMPLSSEF2I64U64;
4340	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32U32,(uint32_t uMxCsrIn, int32_t pi32Dst, const uint32_t pu32Src)); /* pu32Src is a single precision floating point. */
4341	typedef FNIEMAIMPLSSEF2I32U32 *PFNIEMAIMPLSSEF2I32U32;
4342	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64U32,(uint32_t uMxCsrIn, int64_t pi64Dst, const uint32_t pu32Src)); /* pu32Src is a single precision floating point. */
4343	typedef FNIEMAIMPLSSEF2I64U32 *PFNIEMAIMPLSSEF2I64U32;
4344	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32R32,(uint32_t uMxCsrIn, int32_t *pi32Dst, PCRTFLOAT32U pr32Src));
4345	typedef FNIEMAIMPLSSEF2I32R32 *PFNIEMAIMPLSSEF2I32R32;
4346	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64R32,(uint32_t uMxCsrIn, int64_t *pi64Dst, PCRTFLOAT32U pr32Src));
4347	typedef FNIEMAIMPLSSEF2I64R32 *PFNIEMAIMPLSSEF2I64R32;
4348	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32R64,(uint32_t uMxCsrIn, int32_t *pi32Dst, PCRTFLOAT64U pr64Src));
4349	typedef FNIEMAIMPLSSEF2I32R64 *PFNIEMAIMPLSSEF2I32R64;
4350	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64R64,(uint32_t uMxCsrIn, int64_t *pi64Dst, PCRTFLOAT64U pr64Src));
4351	typedef FNIEMAIMPLSSEF2I64R64 *PFNIEMAIMPLSSEF2I64R64;
4352
4353	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvttsd2si_i32_r64;
4354	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvtsd2si_i32_r64;
4355
4356	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvttsd2si_i64_r64;
4357	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvtsd2si_i64_r64;
4358
4359	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvttss2si_i32_r32;
4360	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvtss2si_i32_r32;
4361
4362	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvttss2si_i64_r32;
4363	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvtss2si_i64_r32;
4364
4365	FNIEMAIMPLSSEF2I32R32 iemAImpl_vcvttss2si_i32_r32, iemAImpl_vcvttss2si_i32_r32_fallback;
4366	FNIEMAIMPLSSEF2I64R32 iemAImpl_vcvttss2si_i64_r32, iemAImpl_vcvttss2si_i64_r32_fallback;
4367	FNIEMAIMPLSSEF2I32R32 iemAImpl_vcvtss2si_i32_r32, iemAImpl_vcvtss2si_i32_r32_fallback;
4368	FNIEMAIMPLSSEF2I64R32 iemAImpl_vcvtss2si_i64_r32, iemAImpl_vcvtss2si_i64_r32_fallback;
4369
4370	FNIEMAIMPLSSEF2I32R64 iemAImpl_vcvttss2si_i32_r64, iemAImpl_vcvttss2si_i32_r64_fallback;
4371	FNIEMAIMPLSSEF2I64R64 iemAImpl_vcvttss2si_i64_r64, iemAImpl_vcvttss2si_i64_r64_fallback;
4372	FNIEMAIMPLSSEF2I32R64 iemAImpl_vcvtss2si_i32_r64, iemAImpl_vcvtss2si_i32_r64_fallback;
4373	FNIEMAIMPLSSEF2I64R64 iemAImpl_vcvtss2si_i64_r64, iemAImpl_vcvtss2si_i64_r64_fallback;
4374
4375	FNIEMAIMPLSSEF2I32R32 iemAImpl_vcvttsd2si_i32_r32, iemAImpl_vcvttsd2si_i32_r32_fallback;
4376	FNIEMAIMPLSSEF2I64R32 iemAImpl_vcvttsd2si_i64_r32, iemAImpl_vcvttsd2si_i64_r32_fallback;
4377	FNIEMAIMPLSSEF2I32R32 iemAImpl_vcvtsd2si_i32_r32, iemAImpl_vcvtsd2si_i32_r32_fallback;
4378	FNIEMAIMPLSSEF2I64R32 iemAImpl_vcvtsd2si_i64_r32, iemAImpl_vcvtsd2si_i64_r32_fallback;
4379
4380	FNIEMAIMPLSSEF2I32R64 iemAImpl_vcvttsd2si_i32_r64, iemAImpl_vcvttsd2si_i32_r64_fallback;
4381	FNIEMAIMPLSSEF2I64R64 iemAImpl_vcvttsd2si_i64_r64, iemAImpl_vcvttsd2si_i64_r64_fallback;
4382	FNIEMAIMPLSSEF2I32R64 iemAImpl_vcvtsd2si_i32_r64, iemAImpl_vcvtsd2si_i32_r64_fallback;
4383	FNIEMAIMPLSSEF2I64R64 iemAImpl_vcvtsd2si_i64_r64, iemAImpl_vcvtsd2si_i64_r64_fallback;
4384
4385	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R32I32,(uint32_t uMxCsrIn, PRTFLOAT32U pr32Dst, const int32_t *pi32Src));
4386	typedef FNIEMAIMPLSSEF2R32I32 *PFNIEMAIMPLSSEF2R32I32;
4387	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R32I64,(uint32_t uMxCsrIn, PRTFLOAT32U pr32Dst, const int64_t *pi64Src));
4388	typedef FNIEMAIMPLSSEF2R32I64 *PFNIEMAIMPLSSEF2R32I64;
4389
4390	FNIEMAIMPLSSEF2R32I32 iemAImpl_cvtsi2ss_r32_i32;
4391	FNIEMAIMPLSSEF2R32I64 iemAImpl_cvtsi2ss_r32_i64;
4392
4393	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLAVXF3XMMI32,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc, const int32_t *pi32Src));
4394	typedef FNIEMAIMPLAVXF3XMMI32 *PFNIEMAIMPLAVXF3XMMI32;
4395	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLAVXF3XMMI64,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc, const int64_t *pi64Src));
4396	typedef FNIEMAIMPLAVXF3XMMI64 *PFNIEMAIMPLAVXF3XMMI64;
4397
4398	FNIEMAIMPLAVXF3XMMI32 iemAImpl_vcvtsi2ss_u128_i32, iemAImpl_vcvtsi2ss_u128_i32_fallback;
4399	FNIEMAIMPLAVXF3XMMI64 iemAImpl_vcvtsi2ss_u128_i64, iemAImpl_vcvtsi2ss_u128_i64_fallback;
4400
4401
4402	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R64I32,(uint32_t uMxCsrIn, PRTFLOAT64U pr64Dst, const int32_t *pi32Src));
4403	typedef FNIEMAIMPLSSEF2R64I32 *PFNIEMAIMPLSSEF2R64I32;
4404	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R64I64,(uint32_t uMxCsrIn, PRTFLOAT64U pr64Dst, const int64_t *pi64Src));
4405	typedef FNIEMAIMPLSSEF2R64I64 *PFNIEMAIMPLSSEF2R64I64;
4406
4407	FNIEMAIMPLSSEF2R64I32 iemAImpl_cvtsi2sd_r64_i32;
4408	FNIEMAIMPLSSEF2R64I64 iemAImpl_cvtsi2sd_r64_i64;
4409
4410	FNIEMAIMPLAVXF3XMMI32 iemAImpl_vcvtsi2sd_u128_i32, iemAImpl_vcvtsi2sd_u128_i32_fallback;
4411	FNIEMAIMPLAVXF3XMMI64 iemAImpl_vcvtsi2sd_u128_i64, iemAImpl_vcvtsi2sd_u128_i64_fallback;
4412
4413	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtps2pd_u128_u64,(uint32_t uMxCsrIn, PX86XMMREG puDst, const uint64_t pu64Src)); / Actually two single precision floating point values. */
4414	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtps2pd_u128_u64_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, const uint64_t pu64Src)); / Actually two single precision floating point values. */
4415	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtps2pd_u256_u128,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86XMMREG puSrc));
4416	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtps2pd_u256_u128_fallback,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86XMMREG puSrc));
4417
4418
4419	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtdq2pd_u128_u64,(uint32_t uMxCsrIn, PX86XMMREG puDst, const uint64_t pu64Src)); / Actually two single precision floating point values. */
4420	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtdq2pd_u128_u64_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, const uint64_t pu64Src)); / Actually two single precision floating point values. */
4421	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtdq2pd_u256_u128,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86XMMREG puSrc));
4422	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtdq2pd_u256_u128_fallback,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86XMMREG puSrc));
4423
4424
4425	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLF2EFLMXCSRR32R32,(uint32_t uMxCsrIn, uint32_t *pfEFlags, RTFLOAT32U uSrc1, RTFLOAT32U uSrc2));
4426	typedef FNIEMAIMPLF2EFLMXCSRR32R32 *PFNIEMAIMPLF2EFLMXCSRR32R32;
4427
4428	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLF2EFLMXCSRR64R64,(uint32_t uMxCsrIn, uint32_t *pfEFlags, RTFLOAT64U uSrc1, RTFLOAT64U uSrc2));
4429	typedef FNIEMAIMPLF2EFLMXCSRR64R64 *PFNIEMAIMPLF2EFLMXCSRR64R64;
4430
4431	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_ucomiss_u128;
4432	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback;
4433
4434	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_ucomisd_u128;
4435	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback;
4436
4437	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_comiss_u128;
4438	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback;
4439
4440	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_comisd_u128;
4441	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback;
4442
4443
4444	typedef struct IEMMEDIAF2XMMSRC
4445	{
4446	X86XMMREG uSrc1;
4447	X86XMMREG uSrc2;
4448	} IEMMEDIAF2XMMSRC;
4449	typedef IEMMEDIAF2XMMSRC *PIEMMEDIAF2XMMSRC;
4450	typedef const IEMMEDIAF2XMMSRC *PCIEMMEDIAF2XMMSRC;
4451
4452
4453	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF3XMMIMM8,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC puSrc, uint8_t bEvil));
4454	typedef FNIEMAIMPLMEDIAF3XMMIMM8 *PFNIEMAIMPLMEDIAF3XMMIMM8;
4455
4456
4457	typedef struct IEMMEDIAF2YMMSRC
4458	{
4459	X86YMMREG uSrc1;
4460	X86YMMREG uSrc2;
4461	} IEMMEDIAF2YMMSRC;
4462	typedef IEMMEDIAF2YMMSRC *PIEMMEDIAF2YMMSRC;
4463	typedef const IEMMEDIAF2YMMSRC *PCIEMMEDIAF2YMMSRC;
4464
4465
4466	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF3YMMIMM8,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCIEMMEDIAF2YMMSRC puSrc, uint8_t bEvil));
4467	typedef FNIEMAIMPLMEDIAF3YMMIMM8 *PFNIEMAIMPLMEDIAF3YMMIMM8;
4468
4469
4470	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_cmpps_u128;
4471	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_cmppd_u128;
4472	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_cmpss_u128;
4473	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_cmpsd_u128;
4474
4475	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vcmpps_u128, iemAImpl_vcmpps_u128_fallback;
4476	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vcmppd_u128, iemAImpl_vcmppd_u128_fallback;
4477	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vcmpss_u128, iemAImpl_vcmpss_u128_fallback;
4478	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vcmpsd_u128, iemAImpl_vcmpsd_u128_fallback;
4479
4480	FNIEMAIMPLMEDIAF3YMMIMM8 iemAImpl_vcmpps_u256, iemAImpl_vcmpps_u256_fallback;
4481	FNIEMAIMPLMEDIAF3YMMIMM8 iemAImpl_vcmppd_u256, iemAImpl_vcmppd_u256_fallback;
4482
4483	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_roundss_u128;
4484	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_roundsd_u128;
4485
4486	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_dpps_u128, iemAImpl_dpps_u128_fallback;
4487	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_dppd_u128, iemAImpl_dppd_u128_fallback;
4488
4489
4490	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF2U128IMM8,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc, uint8_t bEvil));
4491	typedef FNIEMAIMPLMEDIAF2U128IMM8 *PFNIEMAIMPLMEDIAF2U128IMM8;
4492
4493
4494	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF2U256IMM8,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86YMMREG puSrc, uint8_t bEvil));
4495	typedef FNIEMAIMPLMEDIAF2U256IMM8 *PFNIEMAIMPLMEDIAF2U256IMM8;
4496
4497
4498	FNIEMAIMPLMEDIAF2U128IMM8 iemAImpl_roundps_u128, iemAImpl_roundps_u128_fallback;
4499	FNIEMAIMPLMEDIAF2U128IMM8 iemAImpl_roundpd_u128, iemAImpl_roundpd_u128_fallback;
4500
4501	FNIEMAIMPLMEDIAF2U128IMM8 iemAImpl_vroundps_u128, iemAImpl_vroundps_u128_fallback;
4502	FNIEMAIMPLMEDIAF2U128IMM8 iemAImpl_vroundpd_u128, iemAImpl_vroundpd_u128_fallback;
4503
4504	FNIEMAIMPLMEDIAF2U256IMM8 iemAImpl_vroundps_u256, iemAImpl_vroundps_u256_fallback;
4505	FNIEMAIMPLMEDIAF2U256IMM8 iemAImpl_vroundpd_u256, iemAImpl_vroundpd_u256_fallback;
4506
4507	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vroundss_u128, iemAImpl_vroundss_u128_fallback;
4508	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vroundsd_u128, iemAImpl_vroundsd_u128_fallback;
4509
4510	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vdpps_u128, iemAImpl_vdpps_u128_fallback;
4511	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vdppd_u128, iemAImpl_vdppd_u128_fallback;
4512
4513	FNIEMAIMPLMEDIAF3YMMIMM8 iemAImpl_vdpps_u256, iemAImpl_vdpps_u256_fallback;
4514
4515
4516	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU64U128,(uint32_t fMxCsrIn, uint64_t *pu64Dst, PCX86XMMREG pSrc));
4517	typedef FNIEMAIMPLMXCSRU64U128 *PFNIEMAIMPLMXCSRU64U128;
4518
4519	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvtpd2pi_u128;
4520	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvttpd2pi_u128;
4521
4522	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU128U64,(uint32_t fMxCsrIn, PX86XMMREG pDst, uint64_t u64Src));
4523	typedef FNIEMAIMPLMXCSRU128U64 *PFNIEMAIMPLMXCSRU128U64;
4524
4525	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2ps_u128;
4526	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2pd_u128;
4527
4528	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU64U64,(uint32_t fMxCsrIn, uint64_t *pu64Dst, uint64_t u64Src));
4529	typedef FNIEMAIMPLMXCSRU64U64 *PFNIEMAIMPLMXCSRU64U64;
4530
4531	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvtps2pi_u128;
4532	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvttps2pi_u128;
4533
4534	/** @} */
4535
4536
4537	/** @name Function tables.
4538	* @{
4539	*/
4540
4541	/**
4542	* Function table for a binary operator providing implementation based on
4543	* operand size.
4544	*/
4545	typedef struct IEMOPBINSIZES
4546	{
4547	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
4548	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
4549	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
4550	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
4551	} IEMOPBINSIZES;
4552	/** Pointer to a binary operator function table. */
4553	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
4554
4555
4556	/**
4557	* Function table for a unary operator providing implementation based on
4558	* operand size.
4559	*/
4560	typedef struct IEMOPUNARYSIZES
4561	{
4562	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
4563	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
4564	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
4565	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
4566	} IEMOPUNARYSIZES;
4567	/** Pointer to a unary operator function table. */
4568	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
4569
4570
4571	/**
4572	* Function table for a shift operator providing implementation based on
4573	* operand size.
4574	*/
4575	typedef struct IEMOPSHIFTSIZES
4576	{
4577	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
4578	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
4579	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
4580	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
4581	} IEMOPSHIFTSIZES;
4582	/** Pointer to a shift operator function table. */
4583	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
4584
4585
4586	/**
4587	* Function table for a multiplication or division operation.
4588	*/
4589	typedef struct IEMOPMULDIVSIZES
4590	{
4591	PFNIEMAIMPLMULDIVU8 pfnU8;
4592	PFNIEMAIMPLMULDIVU16 pfnU16;
4593	PFNIEMAIMPLMULDIVU32 pfnU32;
4594	PFNIEMAIMPLMULDIVU64 pfnU64;
4595	} IEMOPMULDIVSIZES;
4596	/** Pointer to a multiplication or division operation function table. */
4597	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
4598
4599
4600	/**
4601	* Function table for a double precision shift operator providing implementation
4602	* based on operand size.
4603	*/
4604	typedef struct IEMOPSHIFTDBLSIZES
4605	{
4606	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
4607	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
4608	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
4609	} IEMOPSHIFTDBLSIZES;
4610	/** Pointer to a double precision shift function table. */
4611	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
4612
4613
4614	/**
4615	* Function table for media instruction taking two full sized media source
4616	* registers and one full sized destination register (AVX).
4617	*/
4618	typedef struct IEMOPMEDIAF3
4619	{
4620	PFNIEMAIMPLMEDIAF3U128 pfnU128;
4621	PFNIEMAIMPLMEDIAF3U256 pfnU256;
4622	} IEMOPMEDIAF3;
4623	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4624	typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
4625
4626	/** @def IEMOPMEDIAF3_INIT_VARS_EX
4627	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4628	* given functions as initializers. For use in AVX functions where a pair of
4629	* functions are only used once and the function table need not be public. */
4630	#ifndef TST_IEM_CHECK_MC
4631	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4632	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4633	static IEMOPMEDIAF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4634	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4635	# else
4636	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4637	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4638	# endif
4639	#else
4640	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4641	#endif
4642	/** @def IEMOPMEDIAF3_INIT_VARS
4643	* Generate AVX function tables for the @a a_InstrNm instruction.
4644	* @sa IEMOPMEDIAF3_INIT_VARS_EX */
4645	#define IEMOPMEDIAF3_INIT_VARS(a_InstrNm) \
4646	IEMOPMEDIAF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4647	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4648
4649
4650	/**
4651	* Function table for media instruction taking one full sized media source
4652	* registers and one full sized destination register (AVX).
4653	*/
4654	typedef struct IEMOPMEDIAF2
4655	{
4656	PFNIEMAIMPLMEDIAF2U128 pfnU128;
4657	PFNIEMAIMPLMEDIAF2U256 pfnU256;
4658	} IEMOPMEDIAF2;
4659	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4660	typedef IEMOPMEDIAF2 const *PCIEMOPMEDIAF2;
4661
4662	/** @def IEMOPMEDIAF2_INIT_VARS_EX
4663	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4664	* given functions as initializers. For use in AVX functions where a pair of
4665	* functions are only used once and the function table need not be public. */
4666	#ifndef TST_IEM_CHECK_MC
4667	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4668	# define IEMOPMEDIAF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4669	static IEMOPMEDIAF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4670	static IEMOPMEDIAF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4671	# else
4672	# define IEMOPMEDIAF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4673	static IEMOPMEDIAF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4674	# endif
4675	#else
4676	# define IEMOPMEDIAF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4677	#endif
4678	/** @def IEMOPMEDIAF2_INIT_VARS
4679	* Generate AVX function tables for the @a a_InstrNm instruction.
4680	* @sa IEMOPMEDIAF2_INIT_VARS_EX */
4681	#define IEMOPMEDIAF2_INIT_VARS(a_InstrNm) \
4682	IEMOPMEDIAF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4683	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4684
4685
4686	/**
4687	* Function table for media instruction taking two full sized media source
4688	* registers and one full sized destination register, but no additional state
4689	* (AVX).
4690	*/
4691	typedef struct IEMOPMEDIAOPTF3
4692	{
4693	PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
4694	PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
4695	} IEMOPMEDIAOPTF3;
4696	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4697	typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
4698
4699	/** @def IEMOPMEDIAOPTF3_INIT_VARS_EX
4700	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4701	* given functions as initializers. For use in AVX functions where a pair of
4702	* functions are only used once and the function table need not be public. */
4703	#ifndef TST_IEM_CHECK_MC
4704	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4705	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4706	static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4707	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4708	# else
4709	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4710	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4711	# endif
4712	#else
4713	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4714	#endif
4715	/** @def IEMOPMEDIAOPTF3_INIT_VARS
4716	* Generate AVX function tables for the @a a_InstrNm instruction.
4717	* @sa IEMOPMEDIAOPTF3_INIT_VARS_EX */
4718	#define IEMOPMEDIAOPTF3_INIT_VARS(a_InstrNm) \
4719	IEMOPMEDIAOPTF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4720	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4721
4722	/**
4723	* Function table for media instruction taking one full sized media source
4724	* registers and one full sized destination register, but no additional state
4725	* (AVX).
4726	*/
4727	typedef struct IEMOPMEDIAOPTF2
4728	{
4729	PFNIEMAIMPLMEDIAOPTF2U128 pfnU128;
4730	PFNIEMAIMPLMEDIAOPTF2U256 pfnU256;
4731	} IEMOPMEDIAOPTF2;
4732	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4733	typedef IEMOPMEDIAOPTF2 const *PCIEMOPMEDIAOPTF2;
4734
4735	/** @def IEMOPMEDIAOPTF2_INIT_VARS_EX
4736	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4737	* given functions as initializers. For use in AVX functions where a pair of
4738	* functions are only used once and the function table need not be public. */
4739	#ifndef TST_IEM_CHECK_MC
4740	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4741	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4742	static IEMOPMEDIAOPTF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4743	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4744	# else
4745	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4746	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4747	# endif
4748	#else
4749	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4750	#endif
4751	/** @def IEMOPMEDIAOPTF2_INIT_VARS
4752	* Generate AVX function tables for the @a a_InstrNm instruction.
4753	* @sa IEMOPMEDIAOPTF2_INIT_VARS_EX */
4754	#define IEMOPMEDIAOPTF2_INIT_VARS(a_InstrNm) \
4755	IEMOPMEDIAOPTF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4756	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4757
4758
4759	/**
4760	* Function table for media instruction taking one full sized media source
4761	* register and one full sized destination register and an 8-bit immediate (AVX).
4762	*/
4763	typedef struct IEMOPMEDIAF2IMM8
4764	{
4765	PFNIEMAIMPLMEDIAF2U128IMM8 pfnU128;
4766	PFNIEMAIMPLMEDIAF2U256IMM8 pfnU256;
4767	} IEMOPMEDIAF2IMM8;
4768	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4769	typedef IEMOPMEDIAF2IMM8 const *PCIEMOPMEDIAF2IMM8;
4770
4771	/** @def IEMOPMEDIAF2IMM8_INIT_VARS_EX
4772	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4773	* given functions as initializers. For use in AVX functions where a pair of
4774	* functions are only used once and the function table need not be public. */
4775	#ifndef TST_IEM_CHECK_MC
4776	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4777	# define IEMOPMEDIAF2IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4778	static IEMOPMEDIAF2IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4779	static IEMOPMEDIAF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4780	# else
4781	# define IEMOPMEDIAF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4782	static IEMOPMEDIAF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4783	# endif
4784	#else
4785	# define IEMOPMEDIAF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4786	#endif
4787	/** @def IEMOPMEDIAF2IMM8_INIT_VARS
4788	* Generate AVX function tables for the @a a_InstrNm instruction.
4789	* @sa IEMOPMEDIAF2IMM8_INIT_VARS_EX */
4790	#define IEMOPMEDIAF2IMM8_INIT_VARS(a_InstrNm) \
4791	IEMOPMEDIAF2IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4792	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4793
4794
4795	/**
4796	* Function table for media instruction taking one full sized media source
4797	* register and one full sized destination register and an 8-bit immediate, but no additional state
4798	* (AVX).
4799	*/
4800	typedef struct IEMOPMEDIAOPTF2IMM8
4801	{
4802	PFNIEMAIMPLMEDIAOPTF2U128IMM8 pfnU128;
4803	PFNIEMAIMPLMEDIAOPTF2U256IMM8 pfnU256;
4804	} IEMOPMEDIAOPTF2IMM8;
4805	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4806	typedef IEMOPMEDIAOPTF2IMM8 const *PCIEMOPMEDIAOPTF2IMM8;
4807
4808	/** @def IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX
4809	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4810	* given functions as initializers. For use in AVX functions where a pair of
4811	* functions are only used once and the function table need not be public. */
4812	#ifndef TST_IEM_CHECK_MC
4813	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4814	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4815	static IEMOPMEDIAOPTF2IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4816	static IEMOPMEDIAOPTF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4817	# else
4818	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4819	static IEMOPMEDIAOPTF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4820	# endif
4821	#else
4822	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4823	#endif
4824	/** @def IEMOPMEDIAOPTF2IMM8_INIT_VARS
4825	* Generate AVX function tables for the @a a_InstrNm instruction.
4826	* @sa IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX */
4827	#define IEMOPMEDIAOPTF2IMM8_INIT_VARS(a_InstrNm) \
4828	IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u256),\
4829	RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u256_fallback))
4830
4831	/**
4832	* Function table for media instruction taking two full sized media source
4833	* registers and one full sized destination register and an 8-bit immediate, but no additional state
4834	* (AVX).
4835	*/
4836	typedef struct IEMOPMEDIAOPTF3IMM8
4837	{
4838	PFNIEMAIMPLMEDIAOPTF3U128IMM8 pfnU128;
4839	PFNIEMAIMPLMEDIAOPTF3U256IMM8 pfnU256;
4840	} IEMOPMEDIAOPTF3IMM8;
4841	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4842	typedef IEMOPMEDIAOPTF3IMM8 const *PCIEMOPMEDIAOPTF3IMM8;
4843
4844	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX
4845	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4846	* given functions as initializers. For use in AVX functions where a pair of
4847	* functions are only used once and the function table need not be public. */
4848	#ifndef TST_IEM_CHECK_MC
4849	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4850	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4851	static IEMOPMEDIAOPTF3IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4852	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4853	# else
4854	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4855	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4856	# endif
4857	#else
4858	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4859	#endif
4860	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS
4861	* Generate AVX function tables for the @a a_InstrNm instruction.
4862	* @sa IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX */
4863	#define IEMOPMEDIAOPTF3IMM8_INIT_VARS(a_InstrNm) \
4864	IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4865	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4866	/** @} */
4867
4868
4869	/**
4870	* Function table for blend type instruction taking three full sized media source
4871	* registers and one full sized destination register, but no additional state
4872	* (AVX).
4873	*/
4874	typedef struct IEMOPBLENDOP
4875	{
4876	PFNIEMAIMPLAVXBLENDU128 pfnU128;
4877	PFNIEMAIMPLAVXBLENDU256 pfnU256;
4878	} IEMOPBLENDOP;
4879	/** Pointer to a media operation function table for 4 full sized ops (AVX). */
4880	typedef IEMOPBLENDOP const *PCIEMOPBLENDOP;
4881
4882	/** @def IEMOPBLENDOP_INIT_VARS_EX
4883	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4884	* given functions as initializers. For use in AVX functions where a pair of
4885	* functions are only used once and the function table need not be public. */
4886	#ifndef TST_IEM_CHECK_MC
4887	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4888	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4889	static IEMOPBLENDOP const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4890	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4891	# else
4892	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4893	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4894	# endif
4895	#else
4896	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4897	#endif
4898	/** @def IEMOPBLENDOP_INIT_VARS
4899	* Generate AVX function tables for the @a a_InstrNm instruction.
4900	* @sa IEMOPBLENDOP_INIT_VARS_EX */
4901	#define IEMOPBLENDOP_INIT_VARS(a_InstrNm) \
4902	IEMOPBLENDOP_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4903	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4904
4905
4906	/** @name SSE/AVX single/double precision floating point operations.
4907	* @{ */
4908	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
4909	typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128;
4910	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128R32,(uint32_t uMxCsrIn, PX86XMMREG Result, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
4911	typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32;
4912	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128R64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
4913	typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64;
4914
4915	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
4916	typedef FNIEMAIMPLFPAVXF3U128 *PFNIEMAIMPLFPAVXF3U128;
4917	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128R32,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
4918	typedef FNIEMAIMPLFPAVXF3U128R32 *PFNIEMAIMPLFPAVXF3U128R32;
4919	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128R64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
4920	typedef FNIEMAIMPLFPAVXF3U128R64 *PFNIEMAIMPLFPAVXF3U128R64;
4921
4922	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U256,(uint32_t uMxCsrIn, PX86YMMREG pResult, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
4923	typedef FNIEMAIMPLFPAVXF3U256 *PFNIEMAIMPLFPAVXF3U256;
4924
4925	FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
4926	FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
4927	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
4928	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
4929	FNIEMAIMPLFPSSEF2U128 iemAImpl_subps_u128;
4930	FNIEMAIMPLFPSSEF2U128 iemAImpl_subpd_u128;
4931	FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
4932	FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
4933	FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
4934	FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
4935	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxps_u128;
4936	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxpd_u128;
4937	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddps_u128;
4938	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddpd_u128;
4939	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubps_u128;
4940	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubpd_u128;
4941	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtps_u128;
4942	FNIEMAIMPLFPSSEF2U128 iemAImpl_rsqrtps_u128;
4943	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtpd_u128;
4944	FNIEMAIMPLFPSSEF2U128 iemAImpl_rcpps_u128;
4945	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubps_u128;
4946	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubpd_u128;
4947
4948	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2ps_u128;
4949	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_cvtps2pd_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, uint64_t const *pu64Src));
4950
4951	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2ps_u128;
4952	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2dq_u128;
4953	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttps2dq_u128;
4954	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttpd2dq_u128;
4955	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2pd_u128;
4956	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2dq_u128;
4957
4958	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_addss_u128_r32;
4959	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_addsd_u128_r64;
4960	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_mulss_u128_r32;
4961	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_mulsd_u128_r64;
4962	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_subss_u128_r32;
4963	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_subsd_u128_r64;
4964	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_minss_u128_r32;
4965	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_minsd_u128_r64;
4966	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_divss_u128_r32;
4967	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_divsd_u128_r64;
4968	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_maxss_u128_r32;
4969	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_maxsd_u128_r64;
4970	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_cvtss2sd_u128_r32;
4971	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_cvtsd2ss_u128_r64;
4972	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_sqrtss_u128_r32;
4973	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_sqrtsd_u128_r64;
4974	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rsqrtss_u128_r32;
4975	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rcpss_u128_r32;
4976
4977	FNIEMAIMPLMEDIAF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
4978	FNIEMAIMPLMEDIAF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
4979	FNIEMAIMPLMEDIAF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
4980	FNIEMAIMPLMEDIAF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
4981	FNIEMAIMPLMEDIAF3U128 iemAImpl_vsubps_u128, iemAImpl_vsubps_u128_fallback;
4982	FNIEMAIMPLMEDIAF3U128 iemAImpl_vsubpd_u128, iemAImpl_vsubpd_u128_fallback;
4983	FNIEMAIMPLMEDIAF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
4984	FNIEMAIMPLMEDIAF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
4985	FNIEMAIMPLMEDIAF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
4986	FNIEMAIMPLMEDIAF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
4987	FNIEMAIMPLMEDIAF3U128 iemAImpl_vmaxps_u128, iemAImpl_vmaxps_u128_fallback;
4988	FNIEMAIMPLMEDIAF3U128 iemAImpl_vmaxpd_u128, iemAImpl_vmaxpd_u128_fallback;
4989	FNIEMAIMPLMEDIAF3U128 iemAImpl_vhaddps_u128, iemAImpl_vhaddps_u128_fallback;
4990	FNIEMAIMPLMEDIAF3U128 iemAImpl_vhaddpd_u128, iemAImpl_vhaddpd_u128_fallback;
4991	FNIEMAIMPLMEDIAF3U128 iemAImpl_vhsubps_u128, iemAImpl_vhsubps_u128_fallback;
4992	FNIEMAIMPLMEDIAF3U128 iemAImpl_vhsubpd_u128, iemAImpl_vhsubpd_u128_fallback;
4993	FNIEMAIMPLMEDIAF2U128 iemAImpl_vsqrtps_u128, iemAImpl_vsqrtps_u128_fallback;
4994	FNIEMAIMPLMEDIAF2U128 iemAImpl_vsqrtpd_u128, iemAImpl_vsqrtpd_u128_fallback;
4995	FNIEMAIMPLMEDIAF2U128 iemAImpl_vrsqrtps_u128, iemAImpl_vrsqrtps_u128_fallback;
4996	FNIEMAIMPLMEDIAF2U128 iemAImpl_vrcpps_u128, iemAImpl_vrcpps_u128_fallback;
4997	FNIEMAIMPLMEDIAF3U128 iemAImpl_vaddsubps_u128, iemAImpl_vaddsubps_u128_fallback;
4998	FNIEMAIMPLMEDIAF3U128 iemAImpl_vaddsubpd_u128, iemAImpl_vaddsubpd_u128_fallback;
4999	FNIEMAIMPLMEDIAF2U128 iemAImpl_vcvtdq2ps_u128, iemAImpl_vcvtdq2ps_u128_fallback;
5000	FNIEMAIMPLMEDIAF2U128 iemAImpl_vcvtps2dq_u128, iemAImpl_vcvtps2dq_u128_fallback;
5001	FNIEMAIMPLMEDIAF2U128 iemAImpl_vcvttps2dq_u128, iemAImpl_vcvttps2dq_u128_fallback;
5002	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2ps_u128_u128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
5003	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2ps_u128_u128_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
5004	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvttpd2dq_u128_u128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
5005	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvttpd2dq_u128_u128_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
5006	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2dq_u128_u128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
5007	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2dq_u128_u128_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
5008
5009
5010	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback;
5011	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback;
5012	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback;
5013	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback;
5014	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback;
5015	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback;
5016	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback;
5017	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback;
5018	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback;
5019	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback;
5020	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmaxss_u128_r32, iemAImpl_vmaxss_u128_r32_fallback;
5021	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmaxsd_u128_r64, iemAImpl_vmaxsd_u128_r64_fallback;
5022	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsqrtss_u128_r32, iemAImpl_vsqrtss_u128_r32_fallback;
5023	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsqrtsd_u128_r64, iemAImpl_vsqrtsd_u128_r64_fallback;
5024	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vrsqrtss_u128_r32, iemAImpl_vrsqrtss_u128_r32_fallback;
5025	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vrcpss_u128_r32, iemAImpl_vrcpss_u128_r32_fallback;
5026	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vcvtss2sd_u128_r32, iemAImpl_vcvtss2sd_u128_r32_fallback;
5027	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vcvtsd2ss_u128_r64, iemAImpl_vcvtsd2ss_u128_r64_fallback;
5028
5029
5030	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
5031	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
5032	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
5033	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
5034	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubps_u256, iemAImpl_vsubps_u256_fallback;
5035	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubpd_u256, iemAImpl_vsubpd_u256_fallback;
5036	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
5037	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
5038	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
5039	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
5040	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxps_u256, iemAImpl_vmaxps_u256_fallback;
5041	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxpd_u256, iemAImpl_vmaxpd_u256_fallback;
5042	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddps_u256, iemAImpl_vhaddps_u256_fallback;
5043	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddpd_u256, iemAImpl_vhaddpd_u256_fallback;
5044	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubps_u256, iemAImpl_vhsubps_u256_fallback;
5045	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubpd_u256, iemAImpl_vhsubpd_u256_fallback;
5046	FNIEMAIMPLMEDIAF3U256 iemAImpl_vaddsubps_u256, iemAImpl_vaddsubps_u256_fallback;
5047	FNIEMAIMPLMEDIAF3U256 iemAImpl_vaddsubpd_u256, iemAImpl_vaddsubpd_u256_fallback;
5048	FNIEMAIMPLMEDIAF2U256 iemAImpl_vsqrtps_u256, iemAImpl_vsqrtps_u256_fallback;
5049	FNIEMAIMPLMEDIAF2U256 iemAImpl_vsqrtpd_u256, iemAImpl_vsqrtpd_u256_fallback;
5050	FNIEMAIMPLMEDIAF2U256 iemAImpl_vrsqrtps_u256, iemAImpl_vrsqrtps_u256_fallback;
5051	FNIEMAIMPLMEDIAF2U256 iemAImpl_vrcpps_u256, iemAImpl_vrcpps_u256_fallback;
5052	FNIEMAIMPLMEDIAF2U256 iemAImpl_vcvtdq2ps_u256, iemAImpl_vcvtdq2ps_u256_fallback;
5053	FNIEMAIMPLMEDIAF2U256 iemAImpl_vcvtps2dq_u256, iemAImpl_vcvtps2dq_u256_fallback;
5054	FNIEMAIMPLMEDIAF2U256 iemAImpl_vcvttps2dq_u256, iemAImpl_vcvttps2dq_u256_fallback;
5055	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2ps_u128_u256,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5056	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2ps_u128_u256_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5057	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvttpd2dq_u128_u256,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5058	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvttpd2dq_u128_u256_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5059	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2dq_u128_u256,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5060	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2dq_u128_u256_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5061	/** @} */
5062
5063	/** @name C instruction implementations for anything slightly complicated.
5064	* @{ */
5065
5066	/**
5067	* For typedef'ing or declaring a C instruction implementation function taking
5068	* no extra arguments.
5069	*
5070	* @param a_Name The name of the type.
5071	*/
5072	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
5073	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
5074	/**
5075	* For defining a C instruction implementation function taking no extra
5076	* arguments.
5077	*
5078	* @param a_Name The name of the function
5079	*/
5080	# define IEM_CIMPL_DEF_0(a_Name) \
5081	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
5082	/**
5083	* Prototype version of IEM_CIMPL_DEF_0.
5084	*/
5085	# define IEM_CIMPL_PROTO_0(a_Name) \
5086	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
5087	/**
5088	* For calling a C instruction implementation function taking no extra
5089	* arguments.
5090	*
5091	* This special call macro adds default arguments to the call and allow us to
5092	* change these later.
5093	*
5094	* @param a_fn The name of the function.
5095	*/
5096	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
5097
5098	/** Type for a C instruction implementation function taking no extra
5099	* arguments. */
5100	typedef IEM_CIMPL_DECL_TYPE_0(FNIEMCIMPL0);
5101	/** Function pointer type for a C instruction implementation function taking
5102	* no extra arguments. */
5103	typedef FNIEMCIMPL0 *PFNIEMCIMPL0;
5104
5105	/**
5106	* For typedef'ing or declaring a C instruction implementation function taking
5107	* one extra argument.
5108	*
5109	* @param a_Name The name of the type.
5110	* @param a_Type0 The argument type.
5111	* @param a_Arg0 The argument name.
5112	*/
5113	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
5114	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
5115	/**
5116	* For defining a C instruction implementation function taking one extra
5117	* argument.
5118	*
5119	* @param a_Name The name of the function
5120	* @param a_Type0 The argument type.
5121	* @param a_Arg0 The argument name.
5122	*/
5123	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
5124	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
5125	/**
5126	* Prototype version of IEM_CIMPL_DEF_1.
5127	*/
5128	# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
5129	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
5130	/**
5131	* For calling a C instruction implementation function taking one extra
5132	* argument.
5133	*
5134	* This special call macro adds default arguments to the call and allow us to
5135	* change these later.
5136	*
5137	* @param a_fn The name of the function.
5138	* @param a0 The name of the 1st argument.
5139	*/
5140	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
5141
5142	/**
5143	* For typedef'ing or declaring a C instruction implementation function taking
5144	* two extra arguments.
5145	*
5146	* @param a_Name The name of the type.
5147	* @param a_Type0 The type of the 1st argument
5148	* @param a_Arg0 The name of the 1st argument.
5149	* @param a_Type1 The type of the 2nd argument.
5150	* @param a_Arg1 The name of the 2nd argument.
5151	*/
5152	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
5153	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
5154	/**
5155	* For defining a C instruction implementation function taking two extra
5156	* arguments.
5157	*
5158	* @param a_Name The name of the function.
5159	* @param a_Type0 The type of the 1st argument
5160	* @param a_Arg0 The name of the 1st argument.
5161	* @param a_Type1 The type of the 2nd argument.
5162	* @param a_Arg1 The name of the 2nd argument.
5163	*/
5164	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
5165	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
5166	/**
5167	* Prototype version of IEM_CIMPL_DEF_2.
5168	*/
5169	# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
5170	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
5171	/**
5172	* For calling a C instruction implementation function taking two extra
5173	* arguments.
5174	*
5175	* This special call macro adds default arguments to the call and allow us to
5176	* change these later.
5177	*
5178	* @param a_fn The name of the function.
5179	* @param a0 The name of the 1st argument.
5180	* @param a1 The name of the 2nd argument.
5181	*/
5182	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
5183
5184	/**
5185	* For typedef'ing or declaring a C instruction implementation function taking
5186	* three extra arguments.
5187	*
5188	* @param a_Name The name of the type.
5189	* @param a_Type0 The type of the 1st argument
5190	* @param a_Arg0 The name of the 1st argument.
5191	* @param a_Type1 The type of the 2nd argument.
5192	* @param a_Arg1 The name of the 2nd argument.
5193	* @param a_Type2 The type of the 3rd argument.
5194	* @param a_Arg2 The name of the 3rd argument.
5195	*/
5196	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
5197	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
5198	/**
5199	* For defining a C instruction implementation function taking three extra
5200	* arguments.
5201	*
5202	* @param a_Name The name of the function.
5203	* @param a_Type0 The type of the 1st argument
5204	* @param a_Arg0 The name of the 1st argument.
5205	* @param a_Type1 The type of the 2nd argument.
5206	* @param a_Arg1 The name of the 2nd argument.
5207	* @param a_Type2 The type of the 3rd argument.
5208	* @param a_Arg2 The name of the 3rd argument.
5209	*/
5210	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
5211	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
5212	/**
5213	* Prototype version of IEM_CIMPL_DEF_3.
5214	*/
5215	# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
5216	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
5217	/**
5218	* For calling a C instruction implementation function taking three extra
5219	* arguments.
5220	*
5221	* This special call macro adds default arguments to the call and allow us to
5222	* change these later.
5223	*
5224	* @param a_fn The name of the function.
5225	* @param a0 The name of the 1st argument.
5226	* @param a1 The name of the 2nd argument.
5227	* @param a2 The name of the 3rd argument.
5228	*/
5229	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
5230
5231
5232	/**
5233	* For typedef'ing or declaring a C instruction implementation function taking
5234	* four extra arguments.
5235	*
5236	* @param a_Name The name of the type.
5237	* @param a_Type0 The type of the 1st argument
5238	* @param a_Arg0 The name of the 1st argument.
5239	* @param a_Type1 The type of the 2nd argument.
5240	* @param a_Arg1 The name of the 2nd argument.
5241	* @param a_Type2 The type of the 3rd argument.
5242	* @param a_Arg2 The name of the 3rd argument.
5243	* @param a_Type3 The type of the 4th argument.
5244	* @param a_Arg3 The name of the 4th argument.
5245	*/
5246	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
5247	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
5248	/**
5249	* For defining a C instruction implementation function taking four extra
5250	* arguments.
5251	*
5252	* @param a_Name The name of the function.
5253	* @param a_Type0 The type of the 1st argument
5254	* @param a_Arg0 The name of the 1st argument.
5255	* @param a_Type1 The type of the 2nd argument.
5256	* @param a_Arg1 The name of the 2nd argument.
5257	* @param a_Type2 The type of the 3rd argument.
5258	* @param a_Arg2 The name of the 3rd argument.
5259	* @param a_Type3 The type of the 4th argument.
5260	* @param a_Arg3 The name of the 4th argument.
5261	*/
5262	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
5263	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
5264	a_Type2 a_Arg2, a_Type3 a_Arg3))
5265	/**
5266	* Prototype version of IEM_CIMPL_DEF_4.
5267	*/
5268	# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
5269	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
5270	a_Type2 a_Arg2, a_Type3 a_Arg3))
5271	/**
5272	* For calling a C instruction implementation function taking four extra
5273	* arguments.
5274	*
5275	* This special call macro adds default arguments to the call and allow us to
5276	* change these later.
5277	*
5278	* @param a_fn The name of the function.
5279	* @param a0 The name of the 1st argument.
5280	* @param a1 The name of the 2nd argument.
5281	* @param a2 The name of the 3rd argument.
5282	* @param a3 The name of the 4th argument.
5283	*/
5284	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
5285
5286
5287	/**
5288	* For typedef'ing or declaring a C instruction implementation function taking
5289	* five extra arguments.
5290	*
5291	* @param a_Name The name of the type.
5292	* @param a_Type0 The type of the 1st argument
5293	* @param a_Arg0 The name of the 1st argument.
5294	* @param a_Type1 The type of the 2nd argument.
5295	* @param a_Arg1 The name of the 2nd argument.
5296	* @param a_Type2 The type of the 3rd argument.
5297	* @param a_Arg2 The name of the 3rd argument.
5298	* @param a_Type3 The type of the 4th argument.
5299	* @param a_Arg3 The name of the 4th argument.
5300	* @param a_Type4 The type of the 5th argument.
5301	* @param a_Arg4 The name of the 5th argument.
5302	*/
5303	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
5304	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
5305	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
5306	a_Type3 a_Arg3, a_Type4 a_Arg4))
5307	/**
5308	* For defining a C instruction implementation function taking five extra
5309	* arguments.
5310	*
5311	* @param a_Name The name of the function.
5312	* @param a_Type0 The type of the 1st argument
5313	* @param a_Arg0 The name of the 1st argument.
5314	* @param a_Type1 The type of the 2nd argument.
5315	* @param a_Arg1 The name of the 2nd argument.
5316	* @param a_Type2 The type of the 3rd argument.
5317	* @param a_Arg2 The name of the 3rd argument.
5318	* @param a_Type3 The type of the 4th argument.
5319	* @param a_Arg3 The name of the 4th argument.
5320	* @param a_Type4 The type of the 5th argument.
5321	* @param a_Arg4 The name of the 5th argument.
5322	*/
5323	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
5324	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
5325	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
5326	/**
5327	* Prototype version of IEM_CIMPL_DEF_5.
5328	*/
5329	# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
5330	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
5331	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
5332	/**
5333	* For calling a C instruction implementation function taking five extra
5334	* arguments.
5335	*
5336	* This special call macro adds default arguments to the call and allow us to
5337	* change these later.
5338	*
5339	* @param a_fn The name of the function.
5340	* @param a0 The name of the 1st argument.
5341	* @param a1 The name of the 2nd argument.
5342	* @param a2 The name of the 3rd argument.
5343	* @param a3 The name of the 4th argument.
5344	* @param a4 The name of the 5th argument.
5345	*/
5346	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
5347
5348	/** @} */
5349
5350
5351	/** @name Opcode Decoder Function Types.
5352	* @{ */
5353
5354	/** @typedef PFNIEMOP
5355	* Pointer to an opcode decoder function.
5356	*/
5357
5358	/** @def FNIEMOP_DEF
5359	* Define an opcode decoder function.
5360	*
5361	* We're using macors for this so that adding and removing parameters as well as
5362	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
5363	*
5364	* @param a_Name The function name.
5365	*/
5366
5367	/** @typedef PFNIEMOPRM
5368	* Pointer to an opcode decoder function with RM byte.
5369	*/
5370
5371	/** @def FNIEMOPRM_DEF
5372	* Define an opcode decoder function with RM byte.
5373	*
5374	* We're using macors for this so that adding and removing parameters as well as
5375	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
5376	*
5377	* @param a_Name The function name.
5378	*/
5379
5380	#if defined(__GNUC__) && defined(RT_ARCH_X86)
5381	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
5382	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
5383	# define FNIEMOP_DEF(a_Name) \
5384	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
5385	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
5386	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
5387	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
5388	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
5389
5390	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
5391	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
5392	typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
5393	# define FNIEMOP_DEF(a_Name) \
5394	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
5395	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
5396	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
5397	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
5398	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
5399
5400	#elif defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
5401	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
5402	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
5403	# define FNIEMOP_DEF(a_Name) \
5404	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
5405	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
5406	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
5407	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
5408	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
5409
5410	#else
5411	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
5412	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
5413	# define FNIEMOP_DEF(a_Name) \
5414	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
5415	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
5416	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
5417	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
5418	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
5419
5420	#endif
5421	#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
5422
5423	/**
5424	* Call an opcode decoder function.
5425	*
5426	* We're using macors for this so that adding and removing parameters can be
5427	* done as we please. See FNIEMOP_DEF.
5428	*/
5429	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
5430
5431	/**
5432	* Call a common opcode decoder function taking one extra argument.
5433	*
5434	* We're using macors for this so that adding and removing parameters can be
5435	* done as we please. See FNIEMOP_DEF_1.
5436	*/
5437	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
5438
5439	/**
5440	* Call a common opcode decoder function taking one extra argument.
5441	*
5442	* We're using macors for this so that adding and removing parameters can be
5443	* done as we please. See FNIEMOP_DEF_1.
5444	*/
5445	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
5446	/** @} */
5447
5448
5449	/** @name Misc Helpers
5450	* @{ */
5451
5452	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
5453	* due to GCC lacking knowledge about the value range of a switch. */
5454	#if RT_CPLUSPLUS_PREREQ(202000)
5455	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: [[unlikely]] AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
5456	#else
5457	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
5458	#endif
5459
5460	/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
5461	#if RT_CPLUSPLUS_PREREQ(202000)
5462	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: [[unlikely]] AssertFailedReturn(a_RetValue)
5463	#else
5464	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
5465	#endif
5466
5467	/**
5468	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
5469	* occation.
5470	*/
5471	#ifdef LOG_ENABLED
5472	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
5473	do { \
5474	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
5475	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
5476	} while (0)
5477	#else
5478	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
5479	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
5480	#endif
5481
5482	/**
5483	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
5484	* occation using the supplied logger statement.
5485	*
5486	* @param a_LoggerArgs What to log on failure.
5487	*/
5488	#ifdef LOG_ENABLED
5489	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
5490	do { \
5491	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
5492	/LogFunc(a_LoggerArgs);/ \
5493	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
5494	} while (0)
5495	#else
5496	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
5497	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
5498	#endif
5499
5500	/**
5501	* Gets the CPU mode (from fExec) as a IEMMODE value.
5502	*
5503	* @returns IEMMODE
5504	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5505	*/
5506	#define IEM_GET_CPU_MODE(a_pVCpu) ((a_pVCpu)->iem.s.fExec & IEM_F_MODE_CPUMODE_MASK)
5507
5508	/**
5509	* Check if we're currently executing in real or virtual 8086 mode.
5510	*
5511	* @returns @c true if it is, @c false if not.
5512	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5513	*/
5514	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (( ((a_pVCpu)->iem.s.fExec ^ IEM_F_MODE_X86_PROT_MASK) \
5515	& (IEM_F_MODE_X86_V86_MASK \| IEM_F_MODE_X86_PROT_MASK)) != 0)
5516
5517	/**
5518	* Check if we're currently executing in virtual 8086 mode.
5519	*
5520	* @returns @c true if it is, @c false if not.
5521	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5522	*/
5523	#define IEM_IS_V86_MODE(a_pVCpu) (((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_V86_MASK) != 0)
5524
5525	/**
5526	* Check if we're currently executing in long mode.
5527	*
5528	* @returns @c true if it is, @c false if not.
5529	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5530	*/
5531	#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
5532
5533	/**
5534	* Check if we're currently executing in a 16-bit code segment.
5535	*
5536	* @returns @c true if it is, @c false if not.
5537	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5538	*/
5539	#define IEM_IS_16BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_16BIT)
5540
5541	/**
5542	* Check if we're currently executing in a 32-bit code segment.
5543	*
5544	* @returns @c true if it is, @c false if not.
5545	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5546	*/
5547	#define IEM_IS_32BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_32BIT)
5548
5549	/**
5550	* Check if we're currently executing in a 64-bit code segment.
5551	*
5552	* @returns @c true if it is, @c false if not.
5553	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5554	*/
5555	#define IEM_IS_64BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_64BIT)
5556
5557	/**
5558	* Check if we're currently executing in real mode.
5559	*
5560	* @returns @c true if it is, @c false if not.
5561	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5562	*/
5563	#define IEM_IS_REAL_MODE(a_pVCpu) (!((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_PROT_MASK))
5564
5565	/**
5566	* Gets the current protection level (CPL).
5567	*
5568	* @returns 0..3
5569	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5570	*/
5571	#define IEM_GET_CPL(a_pVCpu) (((a_pVCpu)->iem.s.fExec >> IEM_F_X86_CPL_SHIFT) & IEM_F_X86_CPL_SMASK)
5572
5573	/**
5574	* Sets the current protection level (CPL).
5575	*
5576	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5577	*/
5578	#define IEM_SET_CPL(a_pVCpu, a_uCpl) \
5579	do { (a_pVCpu)->iem.s.fExec = ((a_pVCpu)->iem.s.fExec & ~IEM_F_X86_CPL_MASK) \| ((a_uCpl) << IEM_F_X86_CPL_SHIFT); } while (0)
5580
5581	/**
5582	* Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
5583	* @returns PCCPUMFEATURES
5584	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5585	*/
5586	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
5587
5588	/**
5589	* Returns a (const) pointer to the CPUMFEATURES for the host CPU.
5590	* @returns PCCPUMFEATURES
5591	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5592	*/
5593	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
5594
5595	/**
5596	* Evaluates to true if we're presenting an Intel CPU to the guest.
5597	*/
5598	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
5599
5600	/**
5601	* Evaluates to true if we're presenting an AMD CPU to the guest.
5602	*/
5603	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD \|\| (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
5604
5605	/**
5606	* Check if the address is canonical.
5607	*/
5608	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
5609
5610	/** Checks if the ModR/M byte is in register mode or not. */
5611	#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
5612	/** Checks if the ModR/M byte is in memory mode or not. */
5613	#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
5614
5615	/**
5616	* Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
5617	*
5618	* For use during decoding.
5619	*/
5620	#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| (a_pVCpu)->iem.s.uRexReg )
5621	/**
5622	* Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
5623	*
5624	* For use during decoding.
5625	*/
5626	#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) \| (a_pVCpu)->iem.s.uRexB )
5627
5628	/**
5629	* Gets the register (reg) part of a ModR/M encoding, without REX.R.
5630	*
5631	* For use during decoding.
5632	*/
5633	#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
5634	/**
5635	* Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
5636	*
5637	* For use during decoding.
5638	*/
5639	#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
5640
5641	/**
5642	* Gets the register (reg) part of a ModR/M encoding as an extended 8-bit
5643	* register index, with REX.R added in.
5644	*
5645	* For use during decoding.
5646	*
5647	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
5648	*/
5649	#define IEM_GET_MODRM_REG_EX8(a_pVCpu, a_bRm) \
5650	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
5651	\|\| !((a_bRm) & (4 << X86_MODRM_REG_SHIFT)) /* IEM_GET_MODRM_REG(pVCpu, a_bRm) < 4 */ \
5652	? IEM_GET_MODRM_REG(pVCpu, a_bRm) : (((a_bRm) >> X86_MODRM_REG_SHIFT) & 3) \| 16)
5653	/**
5654	* Gets the r/m part of a ModR/M encoding as an extended 8-bit register index,
5655	* with REX.B added in.
5656	*
5657	* For use during decoding.
5658	*
5659	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
5660	*/
5661	#define IEM_GET_MODRM_RM_EX8(a_pVCpu, a_bRm) \
5662	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
5663	\|\| !((a_bRm) & 4) /* IEM_GET_MODRM_RM(pVCpu, a_bRm) < 4 */ \
5664	? IEM_GET_MODRM_RM(pVCpu, a_bRm) : ((a_bRm) & 3) \| 16)
5665
5666	/**
5667	* Combines the prefix REX and ModR/M byte for passing to
5668	* iemOpHlpCalcRmEffAddrThreadedAddr64().
5669	*
5670	* @returns The ModRM byte but with bit 3 set to REX.B and bit 4 to REX.X.
5671	* The two bits are part of the REG sub-field, which isn't needed in
5672	* iemOpHlpCalcRmEffAddrThreadedAddr64().
5673	*
5674	* For use during decoding/recompiling.
5675	*/
5676	#define IEM_GET_MODRM_EX(a_pVCpu, a_bRm) \
5677	( ((a_bRm) & ~X86_MODRM_REG_MASK) \
5678	\| (uint8_t)( (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X)) >> (25 - 3) ) )
5679	AssertCompile(IEM_OP_PRF_REX_B == RT_BIT_32(25));
5680	AssertCompile(IEM_OP_PRF_REX_X == RT_BIT_32(26));
5681
5682	/**
5683	* Gets the effective VEX.VVVV value.
5684	*
5685	* The 4th bit is ignored if not 64-bit code.
5686	* @returns effective V-register value.
5687	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5688	*/
5689	#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
5690	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
5691
5692
5693	/**
5694	* Gets the register (reg) part of a the special 4th register byte used by
5695	* vblendvps and vblendvpd.
5696	*
5697	* For use during decoding.
5698	*/
5699	#define IEM_GET_IMM8_REG(a_pVCpu, a_bRegImm8) \
5700	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_bRegImm8) >> 4 : ((a_bRegImm8) >> 4) & 7)
5701
5702
5703	/**
5704	* Checks if we're executing inside an AMD-V or VT-x guest.
5705	*/
5706	#if defined(VBOX_WITH_NESTED_HWVIRT_VMX) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
5707	# define IEM_IS_IN_GUEST(a_pVCpu) RT_BOOL((a_pVCpu)->iem.s.fExec & IEM_F_X86_CTX_IN_GUEST)
5708	#else
5709	# define IEM_IS_IN_GUEST(a_pVCpu) false
5710	#endif
5711
5712
5713	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5714
5715	/**
5716	* Check if the guest has entered VMX root operation.
5717	*/
5718	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
5719
5720	/**
5721	* Check if the guest has entered VMX non-root operation.
5722	*/
5723	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) ( ((a_pVCpu)->iem.s.fExec & (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST)) \
5724	== (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST) )
5725
5726	/**
5727	* Check if the nested-guest has the given Pin-based VM-execution control set.
5728	*/
5729	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) (CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
5730
5731	/**
5732	* Check if the nested-guest has the given Processor-based VM-execution control set.
5733	*/
5734	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) (CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
5735
5736	/**
5737	* Check if the nested-guest has the given Secondary Processor-based VM-execution
5738	* control set.
5739	*/
5740	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) (CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
5741
5742	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
5743	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
5744
5745	/** Whether a shadow VMCS is present for the given VCPU. */
5746	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
5747
5748	/** Gets the VMXON region pointer. */
5749	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
5750
5751	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
5752	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
5753
5754	/** Whether a current VMCS is present for the given VCPU. */
5755	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
5756
5757	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
5758	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
5759	do \
5760	{ \
5761	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
5762	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
5763	} while (0)
5764
5765	/** Clears any current VMCS for the given VCPU. */
5766	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
5767	do \
5768	{ \
5769	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
5770	} while (0)
5771
5772	/**
5773	* Invokes the VMX VM-exit handler for an instruction intercept.
5774	*/
5775	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
5776	do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
5777
5778	/**
5779	* Invokes the VMX VM-exit handler for an instruction intercept where the
5780	* instruction provides additional VM-exit information.
5781	*/
5782	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
5783	do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
5784
5785	/**
5786	* Invokes the VMX VM-exit handler for a task switch.
5787	*/
5788	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
5789	do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
5790
5791	/**
5792	* Invokes the VMX VM-exit handler for MWAIT.
5793	*/
5794	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
5795	do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
5796
5797	/**
5798	* Invokes the VMX VM-exit handler for EPT faults.
5799	*/
5800	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
5801	do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
5802
5803	/**
5804	* Invokes the VMX VM-exit handler.
5805	*/
5806	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
5807	do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
5808
5809	#else
5810	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
5811	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
5812	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
5813	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
5814	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
5815	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5816	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5817	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5818	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5819	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5820	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
5821
5822	#endif
5823
5824	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5825	/**
5826	* Checks if we're executing a guest using AMD-V.
5827	*/
5828	# define IEM_SVM_IS_IN_GUEST(a_pVCpu) ( (a_pVCpu->iem.s.fExec & (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST)) \
5829	== (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST))
5830	/**
5831	* Check if an SVM control/instruction intercept is set.
5832	*/
5833	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
5834	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
5835
5836	/**
5837	* Check if an SVM read CRx intercept is set.
5838	*/
5839	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
5840	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
5841
5842	/**
5843	* Check if an SVM write CRx intercept is set.
5844	*/
5845	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
5846	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
5847
5848	/**
5849	* Check if an SVM read DRx intercept is set.
5850	*/
5851	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
5852	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
5853
5854	/**
5855	* Check if an SVM write DRx intercept is set.
5856	*/
5857	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
5858	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
5859
5860	/**
5861	* Check if an SVM exception intercept is set.
5862	*/
5863	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
5864	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
5865
5866	/**
5867	* Invokes the SVM \#VMEXIT handler for the nested-guest.
5868	*/
5869	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
5870	do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
5871
5872	/**
5873	* Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
5874	* corresponding decode assist information.
5875	*/
5876	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
5877	do \
5878	{ \
5879	uint64_t uExitInfo1; \
5880	if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
5881	&& (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
5882	uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK \| ((a_iGReg) & 7); \
5883	else \
5884	uExitInfo1 = 0; \
5885	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
5886	} while (0)
5887
5888	/** Check and handles SVM nested-guest instruction intercept and updates
5889	* NRIP if needed.
5890	*/
5891	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
5892	do \
5893	{ \
5894	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
5895	{ \
5896	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
5897	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
5898	} \
5899	} while (0)
5900
5901	/** Checks and handles SVM nested-guest CR0 read intercept. */
5902	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
5903	do \
5904	{ \
5905	if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
5906	{ /* probably likely */ } \
5907	else \
5908	{ \
5909	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
5910	IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
5911	} \
5912	} while (0)
5913
5914	/**
5915	* Updates the NextRIP (NRI) field in the nested-guest VMCB.
5916	*/
5917	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) \
5918	do { \
5919	if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
5920	CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_cbInstr)); \
5921	} while (0)
5922
5923	#else
5924	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
5925	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
5926	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
5927	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
5928	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
5929	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
5930	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
5931	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
5932	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, \
5933	a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
5934	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
5935	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) do { } while (0)
5936
5937	#endif
5938
5939	/** @} */
5940
5941	uint32_t iemCalcExecDbgFlagsSlow(PVMCPUCC pVCpu);
5942	VBOXSTRICTRC iemExecInjectPendingTrap(PVMCPUCC pVCpu);
5943
5944
5945	/**
5946	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
5947	*/
5948	typedef union IEMSELDESC
5949	{
5950	/** The legacy view. */
5951	X86DESC Legacy;
5952	/** The long mode view. */
5953	X86DESC64 Long;
5954	} IEMSELDESC;
5955	/** Pointer to a selector descriptor table entry. */
5956	typedef IEMSELDESC *PIEMSELDESC;
5957
5958	/** @name Raising Exceptions.
5959	* @{ */
5960	VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
5961	uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
5962
5963	VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
5964	uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
5965	#ifdef IEM_WITH_SETJMP
5966	DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
5967	uint32_t fFlags, uint16_t uErr, uint64_t uCr2) IEM_NOEXCEPT_MAY_LONGJMP;
5968	#endif
5969	VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
5970	#ifdef IEM_WITH_SETJMP
5971	DECL_NO_RETURN(void) iemRaiseDivideErrorJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5972	#endif
5973	VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
5974	VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
5975	VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
5976	#ifdef IEM_WITH_SETJMP
5977	DECL_NO_RETURN(void) iemRaiseUndefinedOpcodeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5978	#endif
5979	VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
5980	#ifdef IEM_WITH_SETJMP
5981	DECL_NO_RETURN(void) iemRaiseDeviceNotAvailableJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5982	#endif
5983	VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5984	VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
5985	VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
5986	VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5987	/VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;/
5988	VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5989	VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5990	VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5991	VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5992	VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5993	VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
5994	#ifdef IEM_WITH_SETJMP
5995	DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5996	#endif
5997	VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
5998	VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
5999	VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
6000	#ifdef IEM_WITH_SETJMP
6001	DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
6002	#endif
6003	VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
6004	#ifdef IEM_WITH_SETJMP
6005	DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) IEM_NOEXCEPT_MAY_LONGJMP;
6006	#endif
6007	VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
6008	#ifdef IEM_WITH_SETJMP
6009	DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
6010	#endif
6011	VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) RT_NOEXCEPT;
6012	#ifdef IEM_WITH_SETJMP
6013	DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) IEM_NOEXCEPT_MAY_LONGJMP;
6014	#endif
6015	VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
6016	#ifdef IEM_WITH_SETJMP
6017	DECL_NO_RETURN(void) iemRaiseMathFaultJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6018	#endif
6019	VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu) RT_NOEXCEPT;
6020	#ifdef IEM_WITH_SETJMP
6021	DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6022	#endif
6023	VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
6024	#ifdef IEM_WITH_SETJMP
6025	DECL_NO_RETURN(void) iemRaiseSimdFpExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6026	#endif
6027
6028	void iemLogSyscallRealModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
6029	void iemLogSyscallProtModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
6030
6031	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
6032	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
6033	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
6034
6035	/**
6036	* Macro for calling iemCImplRaiseDivideError().
6037	*
6038	* This is for things that will _always_ decode to an \#DE, taking the
6039	* recompiler into consideration and everything.
6040	*
6041	* @return Strict VBox status code.
6042	*/
6043	#define IEMOP_RAISE_DIVIDE_ERROR_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseDivideError)
6044
6045	/**
6046	* Macro for calling iemCImplRaiseInvalidLockPrefix().
6047	*
6048	* This is for things that will _always_ decode to an \#UD, taking the
6049	* recompiler into consideration and everything.
6050	*
6051	* @return Strict VBox status code.
6052	*/
6053	#define IEMOP_RAISE_INVALID_LOCK_PREFIX_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidLockPrefix)
6054
6055	/**
6056	* Macro for calling iemCImplRaiseInvalidOpcode() for decode/static \#UDs.
6057	*
6058	* This is for things that will _always_ decode to an \#UD, taking the
6059	* recompiler into consideration and everything.
6060	*
6061	* @return Strict VBox status code.
6062	*/
6063	#define IEMOP_RAISE_INVALID_OPCODE_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
6064
6065	/**
6066	* Macro for calling iemCImplRaiseInvalidOpcode() for runtime-style \#UDs.
6067	*
6068	* Using this macro means you've got _buggy_ _code_ and are doing things that
6069	* belongs exclusively in IEMAllCImpl.cpp during decoding.
6070	*
6071	* @return Strict VBox status code.
6072	* @see IEMOP_RAISE_INVALID_OPCODE_RET
6073	*/
6074	#define IEMOP_RAISE_INVALID_OPCODE_RUNTIME_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
6075
6076	/** @} */
6077
6078	/** @name Register Access.
6079	* @{ */
6080	VBOXSTRICTRC iemRegRipRelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
6081	IEMMODE enmEffOpSize) RT_NOEXCEPT;
6082	VBOXSTRICTRC iemRegRipRelativeJumpS16AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int16_t offNextInstr) RT_NOEXCEPT;
6083	VBOXSTRICTRC iemRegRipRelativeJumpS32AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int32_t offNextInstr,
6084	IEMMODE enmEffOpSize) RT_NOEXCEPT;
6085	/** @} */
6086
6087	/** @name FPU access and helpers.
6088	* @{ */
6089	void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
6090	void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6091	void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
6092	void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
6093	void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
6094	void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
6095	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6096	void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
6097	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6098	void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
6099	void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
6100	void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
6101	void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6102	void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
6103	void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6104	void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
6105	void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6106	void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
6107	void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6108	void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
6109	void iemFpuStackPushUnderflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
6110	void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
6111	void iemFpuStackPushOverflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
6112	void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6113	/** @} */
6114
6115	/** @name SSE+AVX SIMD access and helpers.
6116	* @{ */
6117	void iemSseUpdateMxcsr(PVMCPUCC pVCpu, uint32_t fMxcsr) RT_NOEXCEPT;
6118	/** @} */
6119
6120	/** @name Memory access.
6121	* @{ */
6122
6123	/** Report a \#GP instead of \#AC and do not restrict to ring-3 */
6124	#define IEM_MEMMAP_F_ALIGN_GP RT_BIT_32(16)
6125	/** SSE access that should report a \#GP instead of \#AC, unless MXCSR.MM=1
6126	* when it works like normal \#AC. Always used with IEM_MEMMAP_F_ALIGN_GP. */
6127	#define IEM_MEMMAP_F_ALIGN_SSE RT_BIT_32(17)
6128	/** If \#AC is applicable, raise it. Always used with IEM_MEMMAP_F_ALIGN_GP.
6129	* Users include FXSAVE & FXRSTOR. */
6130	#define IEM_MEMMAP_F_ALIGN_GP_OR_AC RT_BIT_32(18)
6131
6132	VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void *ppvMem, uint8_t pbUnmapInfo, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
6133	uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
6134	VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
6135	#ifndef IN_RING3
6136	VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
6137	#endif
6138	void iemMemRollbackAndUnmap(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
6139	void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
6140	VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
6141	VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
6142	VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t cbAccess, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
6143
6144	void iemOpcodeFlushLight(PVMCPUCC pVCpu, uint8_t cbInstr);
6145	void iemOpcodeFlushHeavy(PVMCPUCC pVCpu, uint8_t cbInstr);
6146	#ifdef IEM_WITH_CODE_TLB
6147	void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) IEM_NOEXCEPT_MAY_LONGJMP;
6148	#else
6149	VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
6150	#endif
6151	#ifdef IEM_WITH_SETJMP
6152	uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6153	uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6154	uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6155	uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6156	#else
6157	VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
6158	VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
6159	VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
6160	VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
6161	VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
6162	VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
6163	VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
6164	VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
6165	VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
6166	VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
6167	VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
6168	#endif
6169
6170	VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6171	VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6172	VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6173	VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6174	VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6175	VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6176	VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6177	VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6178	VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6179	VBOXSTRICTRC iemMemFetchDataU128NoAc(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6180	VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6181	VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6182	VBOXSTRICTRC iemMemFetchDataU256NoAc(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6183	VBOXSTRICTRC iemMemFetchDataU256AlignedAvx(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6184	VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
6185	RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
6186	#ifdef IEM_WITH_SETJMP
6187	uint8_t iemMemFetchDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6188	uint16_t iemMemFetchDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6189	uint32_t iemMemFetchDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6190	uint32_t iemMemFetchDataU32NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6191	uint32_t iemMemFlatFetchDataU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6192	uint64_t iemMemFetchDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6193	uint64_t iemMemFetchDataU64NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6194	uint64_t iemMemFetchDataU64AlignedU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6195	void iemMemFetchDataR80SafeJmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6196	void iemMemFetchDataD80SafeJmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6197	void iemMemFetchDataU128SafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6198	void iemMemFetchDataU128NoAcSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6199	void iemMemFetchDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6200	void iemMemFetchDataU256SafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6201	void iemMemFetchDataU256NoAcSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6202	void iemMemFetchDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6203	# if 0 /* these are inlined now */
6204	uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6205	uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6206	uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6207	uint32_t iemMemFlatFetchDataU32Jmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6208	uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6209	uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6210	void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6211	void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6212	void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6213	void iemMemFetchDataU128NoAcJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6214	void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6215	void iemMemFetchDataU256NoAcJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6216	void iemMemFetchDataU256AlignedAvxJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6217	# endif
6218	void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6219	#endif
6220
6221	VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6222	VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6223	VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6224	VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6225	VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
6226
6227	VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
6228	VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
6229	VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
6230	VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
6231	VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
6232	VBOXSTRICTRC iemMemStoreDataU128NoAc(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
6233	VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
6234	VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
6235	VBOXSTRICTRC iemMemStoreDataU256NoAc(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
6236	VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
6237	VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6238	#ifdef IEM_WITH_SETJMP
6239	void iemMemStoreDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
6240	void iemMemStoreDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
6241	void iemMemStoreDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
6242	void iemMemStoreDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
6243	void iemMemStoreDataU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
6244	void iemMemStoreDataU128NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U pu128Value) IEM_NOEXCEPT_MAY_LONGJMP;
6245	void iemMemStoreDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U pu128Value) IEM_NOEXCEPT_MAY_LONGJMP;
6246	void iemMemStoreDataU256SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
6247	void iemMemStoreDataU256NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
6248	void iemMemStoreDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
6249	void iemMemStoreDataR80SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTFLOAT80U pr80Value) IEM_NOEXCEPT_MAY_LONGJMP;
6250	void iemMemStoreDataD80SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTPBCD80U pd80Value) IEM_NOEXCEPT_MAY_LONGJMP;
6251	#if 0
6252	void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
6253	void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
6254	void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
6255	void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
6256	void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
6257	void iemMemStoreDataNoAcU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
6258	void iemMemStoreDataU256NoAcJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
6259	void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
6260	#endif
6261	void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
6262	void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
6263	#endif
6264
6265	#ifdef IEM_WITH_SETJMP
6266	uint8_t iemMemMapDataU8RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6267	uint8_t iemMemMapDataU8AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6268	uint8_t iemMemMapDataU8WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6269	uint8_t const iemMemMapDataU8RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6270	uint16_t iemMemMapDataU16RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6271	uint16_t iemMemMapDataU16AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6272	uint16_t iemMemMapDataU16WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6273	uint16_t const iemMemMapDataU16RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6274	uint32_t iemMemMapDataU32RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6275	uint32_t iemMemMapDataU32AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6276	uint32_t iemMemMapDataU32WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6277	uint32_t const iemMemMapDataU32RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6278	uint64_t iemMemMapDataU64RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6279	uint64_t iemMemMapDataU64AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6280	uint64_t iemMemMapDataU64WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6281	uint64_t const iemMemMapDataU64RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6282	PRTFLOAT80U iemMemMapDataR80RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6283	PRTFLOAT80U iemMemMapDataR80WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6284	PCRTFLOAT80U iemMemMapDataR80RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6285	PRTPBCD80U iemMemMapDataD80RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6286	PRTPBCD80U iemMemMapDataD80WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6287	PCRTPBCD80U iemMemMapDataD80RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6288	PRTUINT128U iemMemMapDataU128RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6289	PRTUINT128U iemMemMapDataU128AtSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6290	PRTUINT128U iemMemMapDataU128WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6291	PCRTUINT128U iemMemMapDataU128RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6292
6293	void iemMemCommitAndUnmapJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
6294	void iemMemCommitAndUnmapRwSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
6295	void iemMemCommitAndUnmapAtSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
6296	void iemMemCommitAndUnmapWoSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
6297	void iemMemCommitAndUnmapRoSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
6298	void iemMemRollbackAndUnmapWoSafe(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
6299	#endif
6300
6301	VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
6302	void *ppvMem, uint8_t pbUnmapInfo, uint64_t *puNewRsp) RT_NOEXCEPT;
6303	VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, uint8_t bUnmapInfo, uint64_t uNewRsp) RT_NOEXCEPT;
6304	VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
6305	VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
6306	VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
6307	VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6308	VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6309	VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6310	VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
6311	VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
6312	void const *ppvMem, uint8_t pbUnmapInfo, uint64_t *puNewRsp) RT_NOEXCEPT;
6313	VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t off, size_t cbMem,
6314	void const *ppvMem, uint8_t pbUnmapInfo, uint64_t uCurNewRsp) RT_NOEXCEPT;
6315	VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
6316	VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
6317	VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
6318	VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
6319	VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6320	VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6321	VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6322
6323	#ifdef IEM_WITH_SETJMP
6324	void iemMemStackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6325	void iemMemStackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6326	void iemMemStackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6327	void iemMemStackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6328	void iemMemStackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6329	void iemMemStackPopGRegU32SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6330	void iemMemStackPopGRegU64SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6331
6332	void iemMemFlat32StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6333	void iemMemFlat32StackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6334	void iemMemFlat32StackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6335	void iemMemFlat32StackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6336	void iemMemFlat32StackPopGRegU32SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6337
6338	void iemMemFlat64StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6339	void iemMemFlat64StackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6340	void iemMemFlat64StackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6341	void iemMemFlat64StackPopGRegU64SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6342
6343	void iemMemStoreStackU16SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6344	void iemMemStoreStackU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6345	void iemMemStoreStackU32SRegSafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6346	void iemMemStoreStackU64SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6347
6348	uint16_t iemMemFetchStackU16SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6349	uint32_t iemMemFetchStackU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6350	uint64_t iemMemFetchStackU64SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6351
6352	#endif
6353
6354	/** @} */
6355
6356	/** @name IEMAllCImpl.cpp
6357	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
6358	* @{ */
6359	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem16, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6360	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem32, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6361	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem64, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6362	IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
6363	IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
6364	IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
6365	IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
6366	IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
6367	IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
6368	IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
6369	IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
6370	typedef IEM_CIMPL_DECL_TYPE_3(FNIEMCIMPLFARBRANCH, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
6371	typedef FNIEMCIMPLFARBRANCH *PFNIEMCIMPLFARBRANCH;
6372	IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
6373	IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
6374	IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
6375	IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
6376	IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
6377	IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
6378	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
6379	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
6380	IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
6381	IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
6382	IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
6383	IEM_CIMPL_PROTO_0(iemCImpl_syscall);
6384	IEM_CIMPL_PROTO_1(iemCImpl_sysret, IEMMODE, enmEffOpSize);
6385	IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
6386	IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
6387	IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
6388	IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
6389	IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
6390	IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
6391	IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
6392	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
6393	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
6394	IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
6395	IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6396	IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
6397	IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6398	IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
6399	IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
6400	IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6401	IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
6402	IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
6403	IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6404	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
6405	IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
6406	IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6407	IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
6408	IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
6409	IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
6410	IEM_CIMPL_PROTO_0(iemCImpl_clts);
6411	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
6412	IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
6413	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
6414	IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
6415	IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
6416	IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
6417	IEM_CIMPL_PROTO_0(iemCImpl_invd);
6418	IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
6419	IEM_CIMPL_PROTO_0(iemCImpl_rsm);
6420	IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
6421	IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
6422	IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
6423	IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
6424	IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
6425	IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
6426	IEM_CIMPL_PROTO_2(iemCImpl_in_eAX_DX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
6427	IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
6428	IEM_CIMPL_PROTO_2(iemCImpl_out_DX_eAX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
6429	IEM_CIMPL_PROTO_0(iemCImpl_cli);
6430	IEM_CIMPL_PROTO_0(iemCImpl_sti);
6431	IEM_CIMPL_PROTO_0(iemCImpl_hlt);
6432	IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
6433	IEM_CIMPL_PROTO_0(iemCImpl_mwait);
6434	IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
6435	IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
6436	IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
6437	IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
6438	IEM_CIMPL_PROTO_0(iemCImpl_daa);
6439	IEM_CIMPL_PROTO_0(iemCImpl_das);
6440	IEM_CIMPL_PROTO_0(iemCImpl_aaa);
6441	IEM_CIMPL_PROTO_0(iemCImpl_aas);
6442	IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
6443	IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
6444	IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
6445	IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
6446	IEM_CIMPL_PROTO_5(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
6447	PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags, uint8_t, bUnmapInfo);
6448	IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6449	IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
6450	IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
6451	IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
6452	IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
6453	IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
6454	IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6455	IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6456	IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6457	IEM_CIMPL_PROTO_2(iemCImpl_vldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6458	IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6459	IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6460	IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6461	IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6462	IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
6463	IEM_CIMPL_PROTO_2(iemCImpl_fxch_underflow, uint8_t, iStReg, uint16_t, uFpuOpcode);
6464	IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, bool, fUCmp, uint32_t, uPopAndFpuOpcode);
6465	IEM_CIMPL_PROTO_2(iemCImpl_rdseed, uint8_t, iReg, IEMMODE, enmEffOpSize);
6466	IEM_CIMPL_PROTO_2(iemCImpl_rdrand, uint8_t, iReg, IEMMODE, enmEffOpSize);
6467	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6468	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6469	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6470	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6471	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6472	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6473	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6474	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6475	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6476	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6477	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6478	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6479	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6480	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6481	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6482	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6483
6484	/** @} */
6485
6486	/** @name IEMAllCImplStrInstr.cpp.h
6487	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
6488	* -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
6489	* @{ */
6490	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
6491	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
6492	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
6493	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
6494	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
6495	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
6496	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
6497	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
6498	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
6499	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6500	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6501
6502	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
6503	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
6504	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
6505	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
6506	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
6507	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
6508	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
6509	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
6510	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
6511	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6512	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6513
6514	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
6515	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
6516	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
6517	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
6518	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
6519	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
6520	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
6521	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
6522	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
6523	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6524	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6525
6526
6527	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
6528	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
6529	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
6530	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
6531	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
6532	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
6533	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
6534	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
6535	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
6536	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6537	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6538
6539	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
6540	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
6541	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
6542	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
6543	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
6544	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
6545	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
6546	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
6547	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
6548	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6549	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6550
6551	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
6552	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
6553	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
6554	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
6555	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
6556	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
6557	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
6558	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
6559	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
6560	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6561	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6562
6563	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
6564	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
6565	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
6566	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
6567	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
6568	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
6569	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
6570	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
6571	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
6572	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6573	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6574
6575
6576	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
6577	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
6578	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
6579	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
6580	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
6581	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
6582	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
6583	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
6584	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
6585	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6586	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6587
6588	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
6589	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
6590	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
6591	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
6592	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
6593	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
6594	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
6595	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
6596	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
6597	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6598	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6599
6600	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
6601	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
6602	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
6603	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
6604	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
6605	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
6606	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
6607	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
6608	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
6609	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6610	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6611
6612	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
6613	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
6614	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
6615	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
6616	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
6617	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
6618	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
6619	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
6620	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
6621	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6622	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6623	/** @} */
6624
6625	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6626	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
6627	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
6628	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
6629	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
6630	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
6631	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
6632	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALKFAST pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
6633	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
6634	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
6635	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
6636	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
6637	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
6638	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
6639	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6640	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6641	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6642	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6643	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6644	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6645	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
6646	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
6647	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
6648	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
6649	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
6650	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
6651	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
6652	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
6653	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
6654	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
6655	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
6656	IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
6657	IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
6658	IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
6659	IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
6660	IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6661	IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6662	IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6663	IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
6664	IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
6665	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
6666	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint64_t *, pu32Dst, uint32_t, u32VmcsField);
6667	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
6668	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
6669	IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
6670	IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
6671	IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
6672	#endif
6673
6674	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
6675	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
6676	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
6677	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
6678	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
6679	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite, uint8_t cbInstr) RT_NOEXCEPT;
6680	IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
6681	IEM_CIMPL_PROTO_0(iemCImpl_vmload);
6682	IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
6683	IEM_CIMPL_PROTO_0(iemCImpl_clgi);
6684	IEM_CIMPL_PROTO_0(iemCImpl_stgi);
6685	IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
6686	IEM_CIMPL_PROTO_0(iemCImpl_skinit);
6687	IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
6688	#endif
6689
6690	IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
6691	IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
6692	IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
6693
6694	extern const PFNIEMOP g_apfnIemInterpretOnlyOneByteMap[256];
6695	extern const PFNIEMOP g_apfnIemInterpretOnlyTwoByteMap[1024];
6696	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f3a[1024];
6697	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f38[1024];
6698	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap1[1024];
6699	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap2[1024];
6700	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap3[1024];
6701
6702	/*
6703	* Recompiler related stuff.
6704	*/
6705	extern const PFNIEMOP g_apfnIemThreadedRecompilerOneByteMap[256];
6706	extern const PFNIEMOP g_apfnIemThreadedRecompilerTwoByteMap[1024];
6707	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f3a[1024];
6708	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f38[1024];
6709	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap1[1024];
6710	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap2[1024];
6711	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap3[1024];
6712
6713	DECLCALLBACK(int) iemTbInit(PVMCC pVM, uint32_t cInitialTbs, uint32_t cMaxTbs,
6714	uint64_t cbInitialExec, uint64_t cbMaxExec, uint32_t cbChunkExec);
6715	void iemThreadedTbObsolete(PVMCPUCC pVCpu, PIEMTB pTb, bool fSafeToFree);
6716	DECLHIDDEN(void) iemTbAllocatorFree(PVMCPUCC pVCpu, PIEMTB pTb);
6717	void iemTbAllocatorProcessDelayedFrees(PVMCPUCC pVCpu, PIEMTBALLOCATOR pTbAllocator);
6718	void iemTbAllocatorFreeupNativeSpace(PVMCPUCC pVCpu, uint32_t cNeededInstrs);
6719	DECLHIDDEN(const char ) iemTbFlagsToString(uint32_t fFlags, char pszBuf, size_t cbBuf) RT_NOEXCEPT;
6720	DECLHIDDEN(void) iemThreadedDisassembleTb(PCIEMTB pTb, PCDBGFINFOHLP pHlp) RT_NOEXCEPT;
6721
6722
6723	/** @todo FNIEMTHREADEDFUNC and friends may need more work... */
6724	#if defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
6725	typedef VBOXSTRICTRC /__attribute__((__nothrow__))/ FNIEMTHREADEDFUNC(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
6726	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
6727	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
6728	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
6729	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
6730	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
6731
6732	#else
6733	typedef VBOXSTRICTRC (FNIEMTHREADEDFUNC)(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
6734	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
6735	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
6736	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
6737	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
6738	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
6739	#endif
6740
6741
6742	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_Nop);
6743	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_LogCpuState);
6744
6745	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_DeferToCImpl0);
6746
6747	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckIrq);
6748	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckMode);
6749	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckHwInstrBps);
6750	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLim);
6751
6752	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodes);
6753	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodes);
6754	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesConsiderCsLim);
6755
6756	/* Branching: */
6757	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndPcAndOpcodes);
6758	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodes);
6759	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodesConsiderCsLim);
6760
6761	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesLoadingTlb);
6762	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlb);
6763	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlbConsiderCsLim);
6764
6765	/* Natural page crossing: */
6766	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesAcrossPageLoadingTlb);
6767	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlb);
6768	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlbConsiderCsLim);
6769
6770	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNextPageLoadingTlb);
6771	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlb);
6772	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlbConsiderCsLim);
6773
6774	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNewPageLoadingTlb);
6775	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlb);
6776	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlbConsiderCsLim);
6777
6778	bool iemThreadedCompileEmitIrqCheckBefore(PVMCPUCC pVCpu, PIEMTB pTb);
6779	bool iemThreadedCompileBeginEmitCallsComplications(PVMCPUCC pVCpu, PIEMTB pTb);
6780
6781	/* Native recompiler public bits: */
6782
6783	DECLHIDDEN(PIEMTB) iemNativeRecompile(PVMCPUCC pVCpu, PIEMTB pTb) RT_NOEXCEPT;
6784	DECLHIDDEN(void) iemNativeDisassembleTb(PVMCPU pVCpu, PCIEMTB pTb, PCDBGFINFOHLP pHlp) RT_NOEXCEPT;
6785	int iemExecMemAllocatorInit(PVMCPU pVCpu, uint64_t cbMax, uint64_t cbInitial, uint32_t cbChunk) RT_NOEXCEPT;
6786	DECLHIDDEN(PIEMNATIVEINSTR) iemExecMemAllocatorAlloc(PVMCPU pVCpu, uint32_t cbReq, PIEMTB pTb, PIEMNATIVEINSTR *ppaExec,
6787	struct IEMNATIVEPERCHUNKCTX const **ppChunkCtx) RT_NOEXCEPT;
6788	DECLHIDDEN(PIEMNATIVEINSTR) iemExecMemAllocatorAllocFromChunk(PVMCPU pVCpu, uint32_t idxChunk, uint32_t cbReq,
6789	PIEMNATIVEINSTR *ppaExec);
6790	DECLHIDDEN(void) iemExecMemAllocatorReadyForUse(PVMCPUCC pVCpu, void *pv, size_t cb) RT_NOEXCEPT;
6791	void iemExecMemAllocatorFree(PVMCPU pVCpu, void *pv, size_t cb) RT_NOEXCEPT;
6792	DECLASM(DECL_NO_RETURN(void)) iemNativeTbLongJmp(void *pvFramePointer, int rc) RT_NOEXCEPT;
6793	DECLHIDDEN(struct IEMNATIVEPERCHUNKCTX const *) iemExecMemGetTbChunkCtx(PVMCPU pVCpu, PCIEMTB pTb);
6794	DECLHIDDEN(struct IEMNATIVEPERCHUNKCTX const *) iemNativeRecompileAttachExecMemChunkCtx(PVMCPU pVCpu, uint32_t idxChunk);
6795
6796	#endif /* !RT_IN_ASSEMBLER - ASM-NOINC-END */
6797
6798
6799	/** @} */
6800
6801	RT_C_DECLS_END
6802
6803	/* ASM-INC: %include "IEMInternalStruct.mac" */
6804
6805	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
6806

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