IEMInternal.h@ 105560

最後變更在這個檔案從105560是 105560,由 vboxsync 提交於 8 月前
VMM/IEM: A few more TLB tracing events. bugref:10727
屬性 svn:eol-style 設為 `native` 屬性 svn:keywords 設為 `Author Date Id Revision`
檔案大小: 350.6 KB

行
1	/* $Id: IEMInternal.h 105560 2024-08-01 10:14:06Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.alldomusa.eu.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
29	#define VMM_INCLUDED_SRC_include_IEMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#ifndef RT_IN_ASSEMBLER
35	# include <VBox/vmm/cpum.h>
36	# include <VBox/vmm/iem.h>
37	# include <VBox/vmm/pgm.h>
38	# include <VBox/vmm/stam.h>
39	# include <VBox/param.h>
40
41	# include <iprt/setjmp-without-sigmask.h>
42	# include <iprt/list.h>
43	#endif /* !RT_IN_ASSEMBLER */
44
45
46	RT_C_DECLS_BEGIN
47
48
49	/** @defgroup grp_iem_int Internals
50	* @ingroup grp_iem
51	* @internal
52	* @{
53	*/
54
55	/* Make doxygen happy w/o overcomplicating the #if checks. */
56	#ifdef DOXYGEN_RUNNING
57	# define IEM_WITH_THROW_CATCH
58	# define VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
59	#endif
60
61	/** For expanding symbol in slickedit and other products tagging and
62	* crossreferencing IEM symbols. */
63	#ifndef IEM_STATIC
64	# define IEM_STATIC static
65	#endif
66
67	/** @def IEM_WITH_SETJMP
68	* Enables alternative status code handling using setjmps.
69	*
70	* This adds a bit of expense via the setjmp() call since it saves all the
71	* non-volatile registers. However, it eliminates return code checks and allows
72	* for more optimal return value passing (return regs instead of stack buffer).
73	*/
74	#if defined(DOXYGEN_RUNNING) \|\| defined(RT_OS_WINDOWS) \|\| 1
75	# define IEM_WITH_SETJMP
76	#endif
77
78	/** @def IEM_WITH_THROW_CATCH
79	* Enables using C++ throw/catch as an alternative to setjmp/longjmp in user
80	* mode code when IEM_WITH_SETJMP is in effect.
81	*
82	* With GCC 11.3.1 and code TLB on linux, using throw/catch instead of
83	* setjmp/long resulted in bs2-test-1 running 3.00% faster and all but on test
84	* result value improving by more than 1%. (Best out of three.)
85	*
86	* With Visual C++ 2019 and code TLB on windows, using throw/catch instead of
87	* setjmp/long resulted in bs2-test-1 running 3.68% faster and all but some of
88	* the MMIO and CPUID tests ran noticeably faster. Variation is greater than on
89	* Linux, but it should be quite a bit faster for normal code.
90	*/
91	#if defined(__cplusplus) && defined(IEM_WITH_SETJMP) && defined(IN_RING3) && (defined(__GNUC__) \|\| defined(_MSC_VER)) /* ASM-NOINC-START */
92	# define IEM_WITH_THROW_CATCH
93	#endif /ASM-NOINC-END/
94
95	/** @def IEMNATIVE_WITH_DELAYED_PC_UPDATING
96	* Enables the delayed PC updating optimization (see @bugref{10373}).
97	*/
98	#if defined(DOXYGEN_RUNNING) \|\| 1
99	# define IEMNATIVE_WITH_DELAYED_PC_UPDATING
100	#endif
101
102	/** Enables the SIMD register allocator @bugref{10614}. */
103	#if defined(DOXYGEN_RUNNING) \|\| 1
104	# define IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
105	#endif
106	/** Enables access to even callee saved registers. */
107	//# define IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS
108
109	#if defined(DOXYGEN_RUNNING) \|\| 1
110	/** @def IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
111	* Delay the writeback or dirty registers as long as possible. */
112	# define IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
113	#endif
114
115	/** @def IEM_WITH_TLB_STATISTICS
116	* Enables all TLB statistics. */
117	#if defined(VBOX_WITH_STATISTICS) \|\| defined(DOXYGEN_RUNNING)
118	# define IEM_WITH_TLB_STATISTICS
119	#endif
120
121	/** @def IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS
122	* Enable this to use native emitters for certain SIMD FP operations. */
123	#if 1 \|\| defined(DOXYGEN_RUNNING)
124	# define IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS
125	#endif
126
127	/** @def VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
128	* Enables a quicker alternative to throw/longjmp for IEM_DO_LONGJMP when
129	* executing native translation blocks.
130	*
131	* This exploits the fact that we save all non-volatile registers in the TB
132	* prologue and thus just need to do the same as the TB epilogue to get the
133	* effect of a longjmp/throw. Since MSC marks XMM6 thru XMM15 as
134	* non-volatile (and does something even more crazy for ARM), this probably
135	* won't work reliably on Windows. */
136	#ifdef RT_ARCH_ARM64
137	# ifndef RT_OS_WINDOWS
138	# define VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
139	# endif
140	#endif
141	/* ASM-NOINC-START */
142	#ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
143	# if !defined(IN_RING3) \
144	\|\| !defined(VBOX_WITH_IEM_RECOMPILER) \
145	\|\| !defined(VBOX_WITH_IEM_NATIVE_RECOMPILER)
146	# undef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
147	# elif defined(RT_OS_WINDOWS)
148	# pragma message("VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP is not safe to use on windows")
149	# endif
150	#endif
151
152
153	/** @def IEM_DO_LONGJMP
154	*
155	* Wrapper around longjmp / throw.
156	*
157	* @param a_pVCpu The CPU handle.
158	* @param a_rc The status code jump back with / throw.
159	*/
160	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
161	# ifdef IEM_WITH_THROW_CATCH
162	# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
163	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) do { \
164	if ((a_pVCpu)->iem.s.pvTbFramePointerR3) \
165	iemNativeTbLongJmp((a_pVCpu)->iem.s.pvTbFramePointerR3, (a_rc)); \
166	throw int(a_rc); \
167	} while (0)
168	# else
169	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) throw int(a_rc)
170	# endif
171	# else
172	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
173	# endif
174	#endif
175
176	/** For use with IEM function that may do a longjmp (when enabled).
177	*
178	* Visual C++ has trouble longjmp'ing from/over functions with the noexcept
179	* attribute. So, we indicate that function that may be part of a longjmp may
180	* throw "exceptions" and that the compiler should definitely not generate and
181	* std::terminate calling unwind code.
182	*
183	* Here is one example of this ending in std::terminate:
184	* @code{.txt}
185	00 00000041`cadfda10 00007ffc`5d5a1f9f ucrtbase!abort+0x4e
186	01 00000041`cadfda40 00007ffc`57af229a ucrtbase!terminate+0x1f
187	02 00000041`cadfda70 00007ffb`eec91030 VCRUNTIME140!__std_terminate+0xa [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\ehhelpers.cpp @ 192]
188	03 00000041`cadfdaa0 00007ffb`eec92c6d VCRUNTIME140_1!_CallSettingFrame+0x20 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\handlers.asm @ 50]
189	04 00000041`cadfdad0 00007ffb`eec93ae5 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToState+0x241 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 1085]
190	05 00000041`cadfdc00 00007ffb`eec92258 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToEmptyState+0x2d [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 218]
191	06 00000041`cadfdc30 00007ffb`eec940e9 VCRUNTIME140_1!__InternalCxxFrameHandler<__FrameHandler4>+0x194 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 304]
192	07 00000041`cadfdcd0 00007ffc`5f9f249f VCRUNTIME140_1!__CxxFrameHandler4+0xa9 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 290]
193	08 00000041`cadfdd40 00007ffc`5f980939 ntdll!RtlpExecuteHandlerForUnwind+0xf
194	09 00000041`cadfdd70 00007ffc`5f9a0edd ntdll!RtlUnwindEx+0x339
195	0a 00000041`cadfe490 00007ffc`57aff976 ntdll!RtlUnwind+0xcd
196	0b 00000041`cadfea00 00007ffb`e1b5de01 VCRUNTIME140!__longjmp_internal+0xe6 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\longjmp.asm @ 140]
197	0c (Inline Function) --------`-------- VBoxVMM!iemOpcodeGetNextU8SlowJmp+0x95 [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 1155]
198	0d 00000041`cadfea50 00007ffb`e1b60f6b VBoxVMM!iemOpcodeGetNextU8Jmp+0xc1 [L:\vbox-intern\src\VBox\VMM\include\IEMInline.h @ 402]
199	0e 00000041`cadfea90 00007ffb`e1cc6201 VBoxVMM!IEMExecForExits+0xdb [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 10185]
200	0f 00000041`cadfec70 00007ffb`e1d0df8d VBoxVMM!EMHistoryExec+0x4f1 [L:\vbox-intern\src\VBox\VMM\VMMAll\EMAll.cpp @ 452]
201	10 00000041`cadfed60 00007ffb`e1d0d4c0 VBoxVMM!nemR3WinHandleExitCpuId+0x79d [L:\vbox-intern\src\VBox\VMM\VMMAll\NEMAllNativeTemplate-win.cpp.h @ 1829] @encode
202	@endcode
203	*
204	* @see https://developercommunity.visualstudio.com/t/fragile-behavior-of-longjmp-called-from-noexcept-f/1532859
205	*/
206	#if defined(IEM_WITH_SETJMP) && (defined(_MSC_VER) \|\| defined(IEM_WITH_THROW_CATCH))
207	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT_EX(false)
208	#else
209	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT
210	#endif
211	/* ASM-NOINC-END */
212
213	#define IEM_IMPLEMENTS_TASKSWITCH
214
215	/** @def IEM_WITH_3DNOW
216	* Includes the 3DNow decoding. */
217	#if !defined(IEM_WITH_3DNOW) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
218	# ifndef IEM_WITHOUT_3DNOW
219	# define IEM_WITH_3DNOW
220	# endif
221	#endif
222
223	/** @def IEM_WITH_THREE_0F_38
224	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
225	#if !defined(IEM_WITH_THREE_0F_38) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
226	# ifndef IEM_WITHOUT_THREE_0F_38
227	# define IEM_WITH_THREE_0F_38
228	# endif
229	#endif
230
231	/** @def IEM_WITH_THREE_0F_3A
232	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
233	#if !defined(IEM_WITH_THREE_0F_3A) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
234	# ifndef IEM_WITHOUT_THREE_0F_3A
235	# define IEM_WITH_THREE_0F_3A
236	# endif
237	#endif
238
239	/** @def IEM_WITH_VEX
240	* Includes the VEX decoding. */
241	#if !defined(IEM_WITH_VEX) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
242	# ifndef IEM_WITHOUT_VEX
243	# define IEM_WITH_VEX
244	# endif
245	#endif
246
247	/** @def IEM_CFG_TARGET_CPU
248	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
249	*
250	* By default we allow this to be configured by the user via the
251	* CPUM/GuestCpuName config string, but this comes at a slight cost during
252	* decoding. So, for applications of this code where there is no need to
253	* be dynamic wrt target CPU, just modify this define.
254	*/
255	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
256	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
257	#endif
258
259	//#define IEM_WITH_CODE_TLB // - work in progress
260	//#define IEM_WITH_DATA_TLB // - work in progress
261
262
263	/** @def IEM_USE_UNALIGNED_DATA_ACCESS
264	* Use unaligned accesses instead of elaborate byte assembly. */
265	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(DOXYGEN_RUNNING) /ASM-NOINC/
266	# define IEM_USE_UNALIGNED_DATA_ACCESS
267	#endif /ASM-NOINC/
268
269	//#define IEM_LOG_MEMORY_WRITES
270
271
272
273	#ifndef RT_IN_ASSEMBLER /* ASM-NOINC-START - the rest of the file */
274
275	# if !defined(IEM_WITHOUT_INSTRUCTION_STATS) && !defined(DOXYGEN_RUNNING)
276	/** Instruction statistics. */
277	typedef struct IEMINSTRSTATS
278	{
279	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
280	# include "IEMInstructionStatisticsTmpl.h"
281	# undef IEM_DO_INSTR_STAT
282	} IEMINSTRSTATS;
283	#else
284	struct IEMINSTRSTATS;
285	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
286	#endif
287	/** Pointer to IEM instruction statistics. */
288	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
289
290
291	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
292	* @{ */
293	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
294	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
295	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
296	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
297	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
298	/** Selects the right variant from a_aArray.
299	* pVCpu is implicit in the caller context. */
300	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
301	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
302	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
303	* be used because the host CPU does not support the operation. */
304	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
305	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
306	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
307	* array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
308	* into the two.
309	* @sa IEM_SELECT_NATIVE_OR_FALLBACK */
310	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
311	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
312	(a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
313	#else
314	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
315	(a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
316	#endif
317	/** @} */
318
319	/**
320	* Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
321	* indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
322	*
323	* On non-x86 hosts, this will shortcut to the fallback w/o checking the
324	* indicator.
325	*
326	* @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
327	*/
328	#if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
329	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
330	(g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
331	#else
332	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
333	#endif
334
335
336	/**
337	* Branch types.
338	*/
339	typedef enum IEMBRANCH
340	{
341	IEMBRANCH_JUMP = 1,
342	IEMBRANCH_CALL,
343	IEMBRANCH_TRAP,
344	IEMBRANCH_SOFTWARE_INT,
345	IEMBRANCH_HARDWARE_INT
346	} IEMBRANCH;
347	AssertCompileSize(IEMBRANCH, 4);
348
349
350	/**
351	* INT instruction types.
352	*/
353	typedef enum IEMINT
354	{
355	/** INT n instruction (opcode 0xcd imm). */
356	IEMINT_INTN = 0,
357	/** Single byte INT3 instruction (opcode 0xcc). */
358	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
359	/** Single byte INTO instruction (opcode 0xce). */
360	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
361	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
362	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
363	} IEMINT;
364	AssertCompileSize(IEMINT, 4);
365
366
367	/**
368	* A FPU result.
369	*/
370	typedef struct IEMFPURESULT
371	{
372	/** The output value. */
373	RTFLOAT80U r80Result;
374	/** The output status. */
375	uint16_t FSW;
376	} IEMFPURESULT;
377	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
378	/** Pointer to a FPU result. */
379	typedef IEMFPURESULT *PIEMFPURESULT;
380	/** Pointer to a const FPU result. */
381	typedef IEMFPURESULT const *PCIEMFPURESULT;
382
383
384	/**
385	* A FPU result consisting of two output values and FSW.
386	*/
387	typedef struct IEMFPURESULTTWO
388	{
389	/** The first output value. */
390	RTFLOAT80U r80Result1;
391	/** The output status. */
392	uint16_t FSW;
393	/** The second output value. */
394	RTFLOAT80U r80Result2;
395	} IEMFPURESULTTWO;
396	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
397	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
398	/** Pointer to a FPU result consisting of two output values and FSW. */
399	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
400	/** Pointer to a const FPU result consisting of two output values and FSW. */
401	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
402
403
404	/**
405	* IEM TLB entry.
406	*
407	* Lookup assembly:
408	* @code{.asm}
409	; Calculate tag.
410	mov rax, [VA]
411	shl rax, 16
412	shr rax, 16 + X86_PAGE_SHIFT
413	or rax, [uTlbRevision]
414
415	; Do indexing.
416	movzx ecx, al
417	lea rcx, [pTlbEntries + rcx]
418
419	; Check tag.
420	cmp [rcx + IEMTLBENTRY.uTag], rax
421	jne .TlbMiss
422
423	; Check access.
424	mov rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
425	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
426	cmp rax, [uTlbPhysRev]
427	jne .TlbMiss
428
429	; Calc address and we're done.
430	mov eax, X86_PAGE_OFFSET_MASK
431	and eax, [VA]
432	or rax, [rcx + IEMTLBENTRY.pMappingR3]
433	%ifdef VBOX_WITH_STATISTICS
434	inc qword [cTlbHits]
435	%endif
436	jmp .Done
437
438	.TlbMiss:
439	mov r8d, ACCESS_FLAGS
440	mov rdx, [VA]
441	mov rcx, [pVCpu]
442	call iemTlbTypeMiss
443	.Done:
444
445	@endcode
446	*
447	*/
448	typedef struct IEMTLBENTRY
449	{
450	/** The TLB entry tag.
451	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
452	* is ASSUMING a virtual address width of 48 bits.
453	*
454	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
455	*
456	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
457	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
458	* revision wraps around though, the tags needs to be zeroed.
459	*
460	* @note Try use SHRD instruction? After seeing
461	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
462	*
463	* @todo This will need to be reorganized for 57-bit wide virtual address and
464	* PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
465	* have to move the TLB entry versioning entirely to the
466	* fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
467	* 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
468	* consumed by PCID and ASID (12 + 6 = 18).
469	*/
470	uint64_t uTag;
471	/** Access flags and physical TLB revision.
472	*
473	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
474	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
475	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
476	* - Bit 3 - pgm phys/virt - not directly writable.
477	* - Bit 4 - pgm phys page - not directly readable.
478	* - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
479	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
480	* - Bit 7 - tlb entry - pMappingR3 member not valid.
481	* - Bits 63 thru 8 are used for the physical TLB revision number.
482	*
483	* We're using complemented bit meanings here because it makes it easy to check
484	* whether special action is required. For instance a user mode write access
485	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
486	* non-zero result would mean special handling needed because either it wasn't
487	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
488	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
489	* need to check any PTE flag.
490	*/
491	uint64_t fFlagsAndPhysRev;
492	/** The guest physical page address. */
493	uint64_t GCPhys;
494	/** Pointer to the ring-3 mapping. */
495	R3PTRTYPE(uint8_t *) pbMappingR3;
496	#if HC_ARCH_BITS == 32
497	uint32_t u32Padding1;
498	#endif
499	} IEMTLBENTRY;
500	AssertCompileSize(IEMTLBENTRY, 32);
501	/** Pointer to an IEM TLB entry. */
502	typedef IEMTLBENTRY *PIEMTLBENTRY;
503	/** Pointer to a const IEM TLB entry. */
504	typedef IEMTLBENTRY const *PCIEMTLBENTRY;
505
506	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
507	* @{ */
508	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
509	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
510	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
511	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
512	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
513	#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /*< Phys tables: Not accessed (need to be marked accessed). /
514	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
515	#define IEMTLBE_F_PT_LARGE_PAGE RT_BIT_64(7) /*< Page tables: Large 2 or 4 MiB page (for flushing). /
516	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(8) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
517	#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(9) /*< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). /
518	#define IEMTLBE_F_PG_CODE_PAGE RT_BIT_64(10) /*< Phys page: Code page. /
519	#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffff800) /*< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR /
520	/** @} */
521	AssertCompile(PGMIEMGCPHYS2PTR_F_NO_WRITE == IEMTLBE_F_PG_NO_WRITE);
522	AssertCompile(PGMIEMGCPHYS2PTR_F_NO_READ == IEMTLBE_F_PG_NO_READ);
523	AssertCompile(PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 == IEMTLBE_F_NO_MAPPINGR3);
524	AssertCompile(PGMIEMGCPHYS2PTR_F_UNASSIGNED == IEMTLBE_F_PG_UNASSIGNED);
525	AssertCompile(PGMIEMGCPHYS2PTR_F_CODE_PAGE == IEMTLBE_F_PG_CODE_PAGE);
526	AssertCompile(PGM_WALKINFO_BIG_PAGE == IEMTLBE_F_PT_LARGE_PAGE);
527	/** The bits set by PGMPhysIemGCPhys2PtrNoLock. */
528	#define IEMTLBE_GCPHYS2PTR_MASK ( PGMIEMGCPHYS2PTR_F_NO_WRITE \
529	\| PGMIEMGCPHYS2PTR_F_NO_READ \
530	\| PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 \
531	\| PGMIEMGCPHYS2PTR_F_UNASSIGNED \
532	\| PGMIEMGCPHYS2PTR_F_CODE_PAGE \
533	\| IEMTLBE_F_PHYS_REV )
534
535
536	/** The TLB size (power of two).
537	* We initially chose 256 because that way we can obtain the result directly
538	* from a 8-bit register without an additional AND instruction.
539	* See also @bugref{10687}. */
540	#if defined(RT_ARCH_AMD64)
541	# define IEMTLB_ENTRY_COUNT 256
542	# define IEMTLB_ENTRY_COUNT_AS_POWER_OF_TWO 8
543	#else
544	# define IEMTLB_ENTRY_COUNT 8192
545	# define IEMTLB_ENTRY_COUNT_AS_POWER_OF_TWO 13
546	#endif
547	AssertCompile(RT_BIT_32(IEMTLB_ENTRY_COUNT_AS_POWER_OF_TWO) == IEMTLB_ENTRY_COUNT);
548
549	/** TLB slot format spec (assumes uint32_t or unsigned value). */
550	#if IEMTLB_ENTRY_COUNT <= 0x100 / 2
551	# define IEMTLB_SLOT_FMT "%02x"
552	#elif IEMTLB_ENTRY_COUNT <= 0x1000 / 2
553	# define IEMTLB_SLOT_FMT "%03x"
554	#elif IEMTLB_ENTRY_COUNT <= 0x10000 / 2
555	# define IEMTLB_SLOT_FMT "%04x"
556	#else
557	# define IEMTLB_SLOT_FMT "%05x"
558	#endif
559
560
561	/**
562	* An IEM TLB.
563	*
564	* We've got two of these, one for data and one for instructions.
565	*/
566	typedef struct IEMTLB
567	{
568	/** The non-global TLB revision.
569	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
570	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
571	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
572	* (The revision zero indicates an invalid TLB entry.)
573	*
574	* The initial value is choosen to cause an early wraparound. */
575	uint64_t uTlbRevision;
576	/** The TLB physical address revision - shadow of PGM variable.
577	*
578	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
579	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
580	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
581	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
582	*
583	* The initial value is choosen to cause an early wraparound.
584	*
585	* @note This is placed between the two TLB revisions because we
586	* load it in pair with one or the other on arm64. */
587	uint64_t volatile uTlbPhysRev;
588	/** The global TLB revision.
589	* Same as uTlbRevision, but only increased for global flushes. */
590	uint64_t uTlbRevisionGlobal;
591
592	/** Large page tag range.
593	*
594	* This is used to avoid scanning a large page's worth of TLB entries for each
595	* INVLPG instruction, and only to do so iff we've loaded any and when the
596	* address is in this range. This is kept up to date when we loading new TLB
597	* entries.
598	*/
599	struct LARGEPAGERANGE
600	{
601	/** The lowest large page address tag, UINT64_MAX if none. */
602	uint64_t uFirstTag;
603	/** The highest large page address tag (with offset mask part set), 0 if none. */
604	uint64_t uLastTag;
605	}
606	/** Large page range for non-global pages. */
607	NonGlobalLargePageRange,
608	/** Large page range for global pages. */
609	GlobalLargePageRange;
610	/** Number of non-global entries for large pages loaded since last TLB flush. */
611	uint32_t cTlbNonGlobalLargePageCurLoads;
612	/** Number of global entries for large pages loaded since last TLB flush. */
613	uint32_t cTlbGlobalLargePageCurLoads;
614
615	/* Statistics: */
616
617	/** TLB hits in IEMAll.cpp code (IEM_WITH_TLB_STATISTICS only; both).
618	* @note For the data TLB this is only used in iemMemMap and and for direct (i.e.
619	* not via safe read/write path) calls to iemMemMapJmp. */
620	uint64_t cTlbCoreHits;
621	/** Safe read/write TLB hits in iemMemMapJmp (IEM_WITH_TLB_STATISTICS
622	* only; data tlb only). */
623	uint64_t cTlbSafeHits;
624	/** TLB hits in IEMAllMemRWTmplInline.cpp.h (data + IEM_WITH_TLB_STATISTICS only). */
625	uint64_t cTlbInlineCodeHits;
626
627	/** TLB misses in IEMAll.cpp code (both).
628	* @note For the data TLB this is only used in iemMemMap and for direct (i.e.
629	* not via safe read/write path) calls to iemMemMapJmp. So,
630	* for the data TLB this more like 'other misses', while for the code
631	* TLB is all misses. */
632	uint64_t cTlbCoreMisses;
633	/** Subset of cTlbCoreMisses that results in PTE.G=1 loads (odd entries). */
634	uint64_t cTlbCoreGlobalLoads;
635	/** Safe read/write TLB misses in iemMemMapJmp (so data only). */
636	uint64_t cTlbSafeMisses;
637	/** Subset of cTlbSafeMisses that results in PTE.G=1 loads (odd entries). */
638	uint64_t cTlbSafeGlobalLoads;
639	/** Safe read path taken (data only). */
640	uint64_t cTlbSafeReadPath;
641	/** Safe write path taken (data only). */
642	uint64_t cTlbSafeWritePath;
643
644	/** @name Details for native code TLB misses.
645	* @note These counts are included in the above counters (cTlbSafeReadPath,
646	* cTlbSafeWritePath, cTlbInlineCodeHits).
647	* @{ */
648	/** TLB misses in native code due to tag mismatch. */
649	STAMCOUNTER cTlbNativeMissTag;
650	/** TLB misses in native code due to flags or physical revision mismatch. */
651	STAMCOUNTER cTlbNativeMissFlagsAndPhysRev;
652	/** TLB misses in native code due to misaligned access. */
653	STAMCOUNTER cTlbNativeMissAlignment;
654	/** TLB misses in native code due to cross page access. */
655	uint32_t cTlbNativeMissCrossPage;
656	/** TLB misses in native code due to non-canonical address. */
657	uint32_t cTlbNativeMissNonCanonical;
658	/** @} */
659
660	/** Slow read path (code only). */
661	uint32_t cTlbSlowCodeReadPath;
662
663	/** Regular TLB flush count. */
664	uint32_t cTlsFlushes;
665	/** Global TLB flush count. */
666	uint32_t cTlsGlobalFlushes;
667	/** Revision rollovers. */
668	uint32_t cTlbRevisionRollovers;
669	/** Physical revision flushes. */
670	uint32_t cTlbPhysRevFlushes;
671	/** Physical revision rollovers. */
672	uint32_t cTlbPhysRevRollovers;
673
674	/uint32_t au32Padding[2];/
675
676	/** The TLB entries.
677	* Even entries are for PTE.G=0 and uses uTlbRevision.
678	* Odd entries are for PTE.G=1 and uses uTlbRevisionGlobal. */
679	IEMTLBENTRY aEntries[IEMTLB_ENTRY_COUNT * 2];
680	} IEMTLB;
681	AssertCompileSizeAlignment(IEMTLB, 64);
682	/** The width (in bits) of the address portion of the TLB tag. */
683	#define IEMTLB_TAG_ADDR_WIDTH 36
684	/** IEMTLB::uTlbRevision increment. */
685	#define IEMTLB_REVISION_INCR RT_BIT_64(IEMTLB_TAG_ADDR_WIDTH)
686	/** IEMTLB::uTlbRevision mask. */
687	#define IEMTLB_REVISION_MASK (~(RT_BIT_64(IEMTLB_TAG_ADDR_WIDTH) - 1))
688
689	/** IEMTLB::uTlbPhysRev increment.
690	* @sa IEMTLBE_F_PHYS_REV */
691	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(11)
692	AssertCompile(IEMTLBE_F_PHYS_REV == ~(IEMTLB_PHYS_REV_INCR - 1U));
693
694	/**
695	* Calculates the TLB tag for a virtual address but without TLB revision.
696	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
697	* @param a_GCPtr The virtual address. Must be RTGCPTR or same size or
698	* the clearing of the top 16 bits won't work (if 32-bit
699	* we'll end up with mostly zeros).
700	*/
701	#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
702	/**
703	* Converts a TLB tag value into a even TLB index.
704	* @returns Index into IEMTLB::aEntries.
705	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
706	*/
707	#if IEMTLB_ENTRY_COUNT == 256
708	# define IEMTLB_TAG_TO_EVEN_INDEX(a_uTag) ( (uint8_t)(a_uTag) * 2U )
709	#else
710	# define IEMTLB_TAG_TO_EVEN_INDEX(a_uTag) ( ((a_uTag) & (IEMTLB_ENTRY_COUNT - 1U)) * 2U )
711	AssertCompile(RT_IS_POWER_OF_TWO(IEMTLB_ENTRY_COUNT));
712	#endif
713	/**
714	* Converts a TLB tag value into an even TLB index.
715	* @returns Pointer into IEMTLB::aEntries corresponding to .
716	* @param a_pTlb The TLB.
717	* @param a_uTag Value returned by IEMTLB_CALC_TAG or
718	* IEMTLB_CALC_TAG_NO_REV.
719	*/
720	#define IEMTLB_TAG_TO_EVEN_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_EVEN_INDEX(a_uTag)] )
721
722	/** Converts a GC address to an even TLB index. */
723	#define IEMTLB_ADDR_TO_EVEN_INDEX(a_GCPtr) IEMTLB_TAG_TO_EVEN_INDEX(IEMTLB_CALC_TAG_NO_REV(a_GCPtr))
724
725
726	/** @def IEM_WITH_TLB_TRACE
727	* Enables the TLB tracing.
728	* Adjust buffer size in IEMR3Init. */
729	#if defined(DOXYGEN_RUNNING) \|\| 0
730	# define IEM_WITH_TLB_TRACE
731	#endif
732
733	#ifdef IEM_WITH_TLB_TRACE
734
735	/** TLB trace entry types. */
736	typedef enum : uint8_t
737	{
738	kIemTlbTraceType_Invalid,
739	kIemTlbTraceType_InvlPg,
740	kIemTlbTraceType_Flush,
741	kIemTlbTraceType_FlushGlobal,
742	kIemTlbTraceType_Load,
743	kIemTlbTraceType_LoadGlobal,
744	kIemTlbTraceType_Load_Cr0,
745	kIemTlbTraceType_Load_Cr3,
746	kIemTlbTraceType_Load_Cr4,
747	kIemTlbTraceType_Load_Efer,
748	kIemTlbTraceType_Irq,
749	kIemTlbTraceType_Xcpt,
750	kIemTlbTraceType_IRet,
751	kIemTlbTraceType_Tb_Compile,
752	kIemTlbTraceType_Tb_Exec_Threaded,
753	kIemTlbTraceType_Tb_Exec_Native
754	} IEMTLBTRACETYPE;
755
756	/** TLB trace entry. */
757	typedef struct IEMTLBTRACEENTRY
758	{
759	/** The flattened RIP for the event. */
760	uint64_t rip;
761	/** The event type. */
762	IEMTLBTRACETYPE enmType;
763	/** Byte parameter - typically used as 'bool fDataTlb'. */
764	uint8_t bParam;
765	/** 16-bit parameter value. */
766	uint16_t u16Param;
767	/** 32-bit parameter value. */
768	uint32_t u32Param;
769	/** 64-bit parameter value. */
770	uint64_t u64Param;
771	/** 64-bit parameter value. */
772	uint64_t u64Param2;
773	} IEMTLBTRACEENTRY;
774	AssertCompileSize(IEMTLBTRACEENTRY, 32);
775	/** Pointer to a TLB trace entry. */
776	typedef IEMTLBTRACEENTRY *PIEMTLBTRACEENTRY;
777	/** Pointer to a const TLB trace entry. */
778	typedef IEMTLBTRACEENTRY const *PCIEMTLBTRACEENTRY;
779	#endif /* !IEM_WITH_TLB_TRACE */
780
781	#if defined(IEM_WITH_TLB_TRACE) && defined(IN_RING3)
782	# define IEMTLBTRACE_INVLPG(a_pVCpu, a_GCPtr) iemTlbTrace(a_pVCpu, kIemTlbTraceType_InvlPg, a_GCPtr)
783	# define IEMTLBTRACE_FLUSH(a_pVCpu, a_uRev, a_fDataTlb) iemTlbTrace(a_pVCpu, kIemTlbTraceType_Flush, a_uRev, 0, a_fDataTlb)
784	# define IEMTLBTRACE_FLUSH_GLOBAL(a_pVCpu, a_uRev, a_uGRev, a_fDataTlb) \
785	iemTlbTrace(a_pVCpu, kIemTlbTraceType_FlushGlobal, a_uRev, a_uGRev, a_fDataTlb)
786	# define IEMTLBTRACE_LOAD(a_pVCpu, a_GCPtr, a_fDataTlb) iemTlbTrace(a_pVCpu, kIemTlbTraceType_Load, a_GCPtr, 0, a_fDataTlb)
787	# define IEMTLBTRACE_LOAD_GLOBAL(a_pVCpu, a_GCPtr, a_fDataTlb) \
788	iemTlbTrace(a_pVCpu, kIemTlbTraceType_LoadGlobal, a_GCPtr, 0, a_fDataTlb)
789	#else
790	# define IEMTLBTRACE_INVLPG(a_pVCpu, a_GCPtr) do { } while (0)
791	# define IEMTLBTRACE_FLUSH(a_pVCpu, a_uRev, a_fDataTlb) do { } while (0)
792	# define IEMTLBTRACE_FLUSH_GLOBAL(a_pVCpu, a_uRev, a_uGRev, a_fDataTlb) do { } while (0)
793	# define IEMTLBTRACE_LOAD(a_pVCpu, a_GCPtr, a_fDataTlb) do { } while (0)
794	# define IEMTLBTRACE_LOAD_GLOBAL(a_pVCpu, a_GCPtr, a_fDataTlb) do { } while (0)
795	#endif
796
797	#if defined(IEM_WITH_TLB_TRACE) && defined(IN_RING3) && 1
798	# define IEMTLBTRACE_LOAD_CR0(a_pVCpu, a_uNew, a_uOld) iemTlbTrace(a_pVCpu, kIemTlbTraceType_Load_Cr0, a_uNew, a_uOld)
799	# define IEMTLBTRACE_LOAD_CR3(a_pVCpu, a_uNew, a_uOld) iemTlbTrace(a_pVCpu, kIemTlbTraceType_Load_Cr3, a_uNew, a_uOld)
800	# define IEMTLBTRACE_LOAD_CR4(a_pVCpu, a_uNew, a_uOld) iemTlbTrace(a_pVCpu, kIemTlbTraceType_Load_Cr4, a_uNew, a_uOld)
801	# define IEMTLBTRACE_LOAD_EFER(a_pVCpu, a_uNew, a_uOld) iemTlbTrace(a_pVCpu, kIemTlbTraceType_Load_Efer, a_uNew, a_uOld)
802	#else
803	# define IEMTLBTRACE_LOAD_CR0(a_pVCpu, a_uNew, a_uOld) do { } while (0)
804	# define IEMTLBTRACE_LOAD_CR3(a_pVCpu, a_uNew, a_uOld) do { } while (0)
805	# define IEMTLBTRACE_LOAD_CR4(a_pVCpu, a_uNew, a_uOld) do { } while (0)
806	# define IEMTLBTRACE_LOAD_EFER(a_pVCpu, a_uNew, a_uOld) do { } while (0)
807	#endif
808
809	#if defined(IEM_WITH_TLB_TRACE) && defined(IN_RING3) && 1
810	# define IEMTLBTRACE_IRQ(a_pVCpu, a_uVector, a_fFlags, a_fEFlags) \
811	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Irq, a_fEFlags, 0, a_uVector, a_fFlags)
812	# define IEMTLBTRACE_XCPT(a_pVCpu, a_uVector, a_uErr, a_uCr2, a_fFlags) \
813	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Xcpt, a_uErr, a_uCr2, a_uVector, a_fFlags)
814	# define IEMTLBTRACE_IRET(a_pVCpu, a_uRetCs, a_uRetRip, a_fEFlags) \
815	iemTlbTrace(a_pVCpu, kIemTlbTraceType_IRet, a_uRetRip, a_fEFlags, 0, a_uRetCs)
816	#else
817	# define IEMTLBTRACE_IRQ(a_pVCpu, a_uVector, a_fFlags, a_fEFlags) do { } while (0)
818	# define IEMTLBTRACE_XCPT(a_pVCpu, a_uVector, a_uErr, a_uCr2, a_fFlags) do { } while (0)
819	# define IEMTLBTRACE_IRET(a_pVCpu, a_uRetCs, a_uRetRip, a_fEFlags) do { } while (0)
820	#endif
821
822	#if defined(IEM_WITH_TLB_TRACE) && defined(IN_RING3) && 1
823	# define IEMTLBTRACE_TB_COMPILE(a_pVCpu, a_GCPhysPc) \
824	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Tb_Compile, a_GCPhysPc)
825	# define IEMTLBTRACE_TB_EXEC_THRD(a_pVCpu, a_pTb) \
826	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Tb_Exec_Threaded, (a_pTb)->GCPhysPc, (uintptr_t)a_pTb, 0, (a_pTb)->cUsed)
827	# define IEMTLBTRACE_TB_EXEC_N8VE(a_pVCpu, a_pTb) \
828	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Tb_Exec_Native, (a_pTb)->GCPhysPc, (uintptr_t)a_pTb, 0, (a_pTb)->cUsed)
829	#else
830	# define IEMTLBTRACE_TB_COMPILE(a_pVCpu, a_GCPhysPc) do { } while (0)
831	# define IEMTLBTRACE_TB_EXEC_THRD(a_pVCpu, a_pTb) do { } while (0)
832	# define IEMTLBTRACE_TB_EXEC_N8VE(a_pVCpu, a_pTb) do { } while (0)
833	#endif
834
835
836	/** @name IEM_MC_F_XXX - MC block flags/clues.
837	* @todo Merge with IEM_CIMPL_F_XXX
838	* @{ */
839	#define IEM_MC_F_ONLY_8086 RT_BIT_32(0)
840	#define IEM_MC_F_MIN_186 RT_BIT_32(1)
841	#define IEM_MC_F_MIN_286 RT_BIT_32(2)
842	#define IEM_MC_F_NOT_286_OR_OLDER IEM_MC_F_MIN_386
843	#define IEM_MC_F_MIN_386 RT_BIT_32(3)
844	#define IEM_MC_F_MIN_486 RT_BIT_32(4)
845	#define IEM_MC_F_MIN_PENTIUM RT_BIT_32(5)
846	#define IEM_MC_F_MIN_PENTIUM_II IEM_MC_F_MIN_PENTIUM
847	#define IEM_MC_F_MIN_CORE IEM_MC_F_MIN_PENTIUM
848	#define IEM_MC_F_64BIT RT_BIT_32(6)
849	#define IEM_MC_F_NOT_64BIT RT_BIT_32(7)
850	/** This is set by IEMAllN8vePython.py to indicate a variation without the
851	* flags-clearing-and-checking, when there is also a variation with that.
852	* @note Do not use this manully, it's only for python and for testing in
853	* the native recompiler! */
854	#define IEM_MC_F_WITHOUT_FLAGS RT_BIT_32(8)
855	/** @} */
856
857	/** @name IEM_CIMPL_F_XXX - State change clues for CIMPL calls.
858	*
859	* These clues are mainly for the recompiler, so that it can emit correct code.
860	*
861	* They are processed by the python script and which also automatically
862	* calculates flags for MC blocks based on the statements, extending the use of
863	* these flags to describe MC block behavior to the recompiler core. The python
864	* script pass the flags to the IEM_MC2_END_EMIT_CALLS macro, but mainly for
865	* error checking purposes. The script emits the necessary fEndTb = true and
866	* similar statements as this reduces compile time a tiny bit.
867	*
868	* @{ */
869	/** Flag set if direct branch, clear if absolute or indirect. */
870	#define IEM_CIMPL_F_BRANCH_DIRECT RT_BIT_32(0)
871	/** Flag set if indirect branch, clear if direct or relative.
872	* This is also used for all system control transfers (SYSCALL, SYSRET, INT, ++)
873	* as well as for return instructions (RET, IRET, RETF). */
874	#define IEM_CIMPL_F_BRANCH_INDIRECT RT_BIT_32(1)
875	/** Flag set if relative branch, clear if absolute or indirect. */
876	#define IEM_CIMPL_F_BRANCH_RELATIVE RT_BIT_32(2)
877	/** Flag set if conditional branch, clear if unconditional. */
878	#define IEM_CIMPL_F_BRANCH_CONDITIONAL RT_BIT_32(3)
879	/** Flag set if it's a far branch (changes CS). */
880	#define IEM_CIMPL_F_BRANCH_FAR RT_BIT_32(4)
881	/** Convenience: Testing any kind of branch. */
882	#define IEM_CIMPL_F_BRANCH_ANY (IEM_CIMPL_F_BRANCH_DIRECT \| IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_RELATIVE)
883
884	/** Execution flags may change (IEMCPU::fExec). */
885	#define IEM_CIMPL_F_MODE RT_BIT_32(5)
886	/** May change significant portions of RFLAGS. */
887	#define IEM_CIMPL_F_RFLAGS RT_BIT_32(6)
888	/** May change the status bits (X86_EFL_STATUS_BITS) in RFLAGS. */
889	#define IEM_CIMPL_F_STATUS_FLAGS RT_BIT_32(7)
890	/** May trigger interrupt shadowing. */
891	#define IEM_CIMPL_F_INHIBIT_SHADOW RT_BIT_32(8)
892	/** May enable interrupts, so recheck IRQ immediately afterwards executing
893	* the instruction. */
894	#define IEM_CIMPL_F_CHECK_IRQ_AFTER RT_BIT_32(9)
895	/** May disable interrupts, so recheck IRQ immediately before executing the
896	* instruction. */
897	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE RT_BIT_32(10)
898	/** Convenience: Check for IRQ both before and after an instruction. */
899	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE_AND_AFTER (IEM_CIMPL_F_CHECK_IRQ_BEFORE \| IEM_CIMPL_F_CHECK_IRQ_AFTER)
900	/** May trigger a VM exit (treated like IEM_CIMPL_F_MODE atm). */
901	#define IEM_CIMPL_F_VMEXIT RT_BIT_32(11)
902	/** May modify FPU state.
903	* @todo Not sure if this is useful yet. */
904	#define IEM_CIMPL_F_FPU RT_BIT_32(12)
905	/** REP prefixed instruction which may yield before updating PC.
906	* @todo Not sure if this is useful, REP functions now return non-zero
907	* status if they don't update the PC. */
908	#define IEM_CIMPL_F_REP RT_BIT_32(13)
909	/** I/O instruction.
910	* @todo Not sure if this is useful yet. */
911	#define IEM_CIMPL_F_IO RT_BIT_32(14)
912	/** Force end of TB after the instruction. */
913	#define IEM_CIMPL_F_END_TB RT_BIT_32(15)
914	/** Flag set if a branch may also modify the stack (push/pop return address). */
915	#define IEM_CIMPL_F_BRANCH_STACK RT_BIT_32(16)
916	/** Flag set if a branch may also modify the stack (push/pop return address)
917	* and switch it (load/restore SS:RSP). */
918	#define IEM_CIMPL_F_BRANCH_STACK_FAR RT_BIT_32(17)
919	/** Convenience: Raise exception (technically unnecessary, since it shouldn't return VINF_SUCCESS). */
920	#define IEM_CIMPL_F_XCPT \
921	(IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_FAR \| IEM_CIMPL_F_BRANCH_STACK_FAR \
922	\| IEM_CIMPL_F_MODE \| IEM_CIMPL_F_RFLAGS \| IEM_CIMPL_F_VMEXIT)
923
924	/** The block calls a C-implementation instruction function with two implicit arguments.
925	* Mutually exclusive with IEM_CIMPL_F_CALLS_AIMPL and
926	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
927	* @note The python scripts will add this if missing. */
928	#define IEM_CIMPL_F_CALLS_CIMPL RT_BIT_32(18)
929	/** The block calls an ASM-implementation instruction function.
930	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL and
931	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
932	* @note The python scripts will add this if missing. */
933	#define IEM_CIMPL_F_CALLS_AIMPL RT_BIT_32(19)
934	/** The block calls an ASM-implementation instruction function with an implicit
935	* X86FXSTATE pointer argument.
936	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL, IEM_CIMPL_F_CALLS_AIMPL and
937	* IEM_CIMPL_F_CALLS_AIMPL_WITH_XSTATE.
938	* @note The python scripts will add this if missing. */
939	#define IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE RT_BIT_32(20)
940	/** The block calls an ASM-implementation instruction function with an implicit
941	* X86XSAVEAREA pointer argument.
942	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL, IEM_CIMPL_F_CALLS_AIMPL and
943	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
944	* @note No different from IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE, so same value.
945	* @note The python scripts will add this if missing. */
946	#define IEM_CIMPL_F_CALLS_AIMPL_WITH_XSTATE IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE
947	/** @} */
948
949
950	/** @name IEM_F_XXX - Execution mode flags (IEMCPU::fExec, IEMTB::fFlags).
951	*
952	* These flags are set when entering IEM and adjusted as code is executed, such
953	* that they will always contain the current values as instructions are
954	* finished.
955	*
956	* In recompiled execution mode, (most of) these flags are included in the
957	* translation block selection key and stored in IEMTB::fFlags alongside the
958	* IEMTB_F_XXX flags. The latter flags uses bits 31 thru 24, which are all zero
959	* in IEMCPU::fExec.
960	*
961	* @{ */
962	/** Mode: The block target mode mask. */
963	#define IEM_F_MODE_MASK UINT32_C(0x0000001f)
964	/** Mode: The IEMMODE part of the IEMTB_F_MODE_MASK value. */
965	#define IEM_F_MODE_CPUMODE_MASK UINT32_C(0x00000003)
966	/** X86 Mode: Bit used to indicating pre-386 CPU in 16-bit mode (for eliminating
967	* conditional in EIP/IP updating), and flat wide open CS, SS, DS, and ES in
968	* 32-bit mode (for simplifying most memory accesses). */
969	#define IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK UINT32_C(0x00000004)
970	/** X86 Mode: Bit indicating protected mode, real mode (or SMM) when not set. */
971	#define IEM_F_MODE_X86_PROT_MASK UINT32_C(0x00000008)
972	/** X86 Mode: Bit used to indicate virtual 8086 mode (only 16-bit). */
973	#define IEM_F_MODE_X86_V86_MASK UINT32_C(0x00000010)
974
975	/** X86 Mode: 16-bit on 386 or later. */
976	#define IEM_F_MODE_X86_16BIT UINT32_C(0x00000000)
977	/** X86 Mode: 80286, 80186 and 8086/88 targetting blocks (EIP update opt). */
978	#define IEM_F_MODE_X86_16BIT_PRE_386 UINT32_C(0x00000004)
979	/** X86 Mode: 16-bit protected mode on 386 or later. */
980	#define IEM_F_MODE_X86_16BIT_PROT UINT32_C(0x00000008)
981	/** X86 Mode: 16-bit protected mode on 386 or later. */
982	#define IEM_F_MODE_X86_16BIT_PROT_PRE_386 UINT32_C(0x0000000c)
983	/** X86 Mode: 16-bit virtual 8086 protected mode (on 386 or later). */
984	#define IEM_F_MODE_X86_16BIT_PROT_V86 UINT32_C(0x00000018)
985
986	/** X86 Mode: 32-bit on 386 or later. */
987	#define IEM_F_MODE_X86_32BIT UINT32_C(0x00000001)
988	/** X86 Mode: 32-bit mode with wide open flat CS, SS, DS and ES. */
989	#define IEM_F_MODE_X86_32BIT_FLAT UINT32_C(0x00000005)
990	/** X86 Mode: 32-bit protected mode. */
991	#define IEM_F_MODE_X86_32BIT_PROT UINT32_C(0x00000009)
992	/** X86 Mode: 32-bit protected mode with wide open flat CS, SS, DS and ES. */
993	#define IEM_F_MODE_X86_32BIT_PROT_FLAT UINT32_C(0x0000000d)
994
995	/** X86 Mode: 64-bit (includes protected, but not the flat bit). */
996	#define IEM_F_MODE_X86_64BIT UINT32_C(0x0000000a)
997
998	/** X86 Mode: Checks if @a a_fExec represent a FLAT mode. */
999	#define IEM_F_MODE_X86_IS_FLAT(a_fExec) ( ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_64BIT \
1000	\|\| ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_PROT_FLAT \
1001	\|\| ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_FLAT)
1002
1003	/** Bypass access handlers when set. */
1004	#define IEM_F_BYPASS_HANDLERS UINT32_C(0x00010000)
1005	/** Have pending hardware instruction breakpoints. */
1006	#define IEM_F_PENDING_BRK_INSTR UINT32_C(0x00020000)
1007	/** Have pending hardware data breakpoints. */
1008	#define IEM_F_PENDING_BRK_DATA UINT32_C(0x00040000)
1009
1010	/** X86: Have pending hardware I/O breakpoints. */
1011	#define IEM_F_PENDING_BRK_X86_IO UINT32_C(0x00000400)
1012	/** X86: Disregard the lock prefix (implied or not) when set. */
1013	#define IEM_F_X86_DISREGARD_LOCK UINT32_C(0x00000800)
1014
1015	/** Pending breakpoint mask (what iemCalcExecDbgFlags works out). */
1016	#define IEM_F_PENDING_BRK_MASK (IEM_F_PENDING_BRK_INSTR \| IEM_F_PENDING_BRK_DATA \| IEM_F_PENDING_BRK_X86_IO)
1017
1018	/** Caller configurable options. */
1019	#define IEM_F_USER_OPTS (IEM_F_BYPASS_HANDLERS \| IEM_F_X86_DISREGARD_LOCK)
1020
1021	/** X86: The current protection level (CPL) shift factor. */
1022	#define IEM_F_X86_CPL_SHIFT 8
1023	/** X86: The current protection level (CPL) mask. */
1024	#define IEM_F_X86_CPL_MASK UINT32_C(0x00000300)
1025	/** X86: The current protection level (CPL) shifted mask. */
1026	#define IEM_F_X86_CPL_SMASK UINT32_C(0x00000003)
1027
1028	/** X86: Alignment checks enabled (CR0.AM=1 & EFLAGS.AC=1). */
1029	#define IEM_F_X86_AC UINT32_C(0x00080000)
1030
1031	/** X86 execution context.
1032	* The IEM_F_X86_CTX_XXX values are individual flags that can be combined (with
1033	* the exception of IEM_F_X86_CTX_NORMAL). This allows running VMs from SMM
1034	* mode. */
1035	#define IEM_F_X86_CTX_MASK UINT32_C(0x0000f000)
1036	/** X86 context: Plain regular execution context. */
1037	#define IEM_F_X86_CTX_NORMAL UINT32_C(0x00000000)
1038	/** X86 context: VT-x enabled. */
1039	#define IEM_F_X86_CTX_VMX UINT32_C(0x00001000)
1040	/** X86 context: AMD-V enabled. */
1041	#define IEM_F_X86_CTX_SVM UINT32_C(0x00002000)
1042	/** X86 context: In AMD-V or VT-x guest mode. */
1043	#define IEM_F_X86_CTX_IN_GUEST UINT32_C(0x00004000)
1044	/** X86 context: System management mode (SMM). */
1045	#define IEM_F_X86_CTX_SMM UINT32_C(0x00008000)
1046
1047	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
1048	* iemRegFinishClearingRF() most for most situations (CPUMCTX_DBG_HIT_DRX_MASK
1049	* and CPUMCTX_DBG_DBGF_MASK are covered by the IEM_F_PENDING_BRK_XXX bits
1050	* alread). */
1051
1052	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
1053	* iemRegFinishClearingRF() most for most situations
1054	* (CPUMCTX_DBG_HIT_DRX_MASK and CPUMCTX_DBG_DBGF_MASK are covered by
1055	* the IEM_F_PENDING_BRK_XXX bits alread). */
1056
1057	/** @} */
1058
1059
1060	/** @name IEMTB_F_XXX - Translation block flags (IEMTB::fFlags).
1061	*
1062	* Extends the IEM_F_XXX flags (subject to IEMTB_F_IEM_F_MASK) to make up the
1063	* translation block flags. The combined flag mask (subject to
1064	* IEMTB_F_KEY_MASK) is used as part of the lookup key for translation blocks.
1065	*
1066	* @{ */
1067	/** Mask of IEM_F_XXX flags included in IEMTB_F_XXX. */
1068	#define IEMTB_F_IEM_F_MASK UINT32_C(0x00ffffff)
1069
1070	/** Type: The block type mask. */
1071	#define IEMTB_F_TYPE_MASK UINT32_C(0x03000000)
1072	/** Type: Purly threaded recompiler (via tables). */
1073	#define IEMTB_F_TYPE_THREADED UINT32_C(0x01000000)
1074	/** Type: Native recompilation. */
1075	#define IEMTB_F_TYPE_NATIVE UINT32_C(0x02000000)
1076
1077	/** Set when we're starting the block in an "interrupt shadow".
1078	* We don't need to distingish between the two types of this mask, thus the one.
1079	* @see CPUMCTX_INHIBIT_SHADOW, CPUMIsInInterruptShadow() */
1080	#define IEMTB_F_INHIBIT_SHADOW UINT32_C(0x04000000)
1081	/** Set when we're currently inhibiting NMIs
1082	* @see CPUMCTX_INHIBIT_NMI, CPUMAreInterruptsInhibitedByNmi() */
1083	#define IEMTB_F_INHIBIT_NMI UINT32_C(0x08000000)
1084
1085	/** Checks that EIP/IP is wihin CS.LIM before each instruction. Used when
1086	* we're close the limit before starting a TB, as determined by
1087	* iemGetTbFlagsForCurrentPc(). */
1088	#define IEMTB_F_CS_LIM_CHECKS UINT32_C(0x10000000)
1089
1090	/** Mask of the IEMTB_F_XXX flags that are part of the TB lookup key.
1091	*
1092	* @note We skip all of IEM_F_X86_CTX_MASK, with the exception of SMM (which we
1093	* don't implement), because we don't currently generate any context
1094	* specific code - that's all handled in CIMPL functions.
1095	*
1096	* For the threaded recompiler we don't generate any CPL specific code
1097	* either, but the native recompiler does for memory access (saves getting
1098	* the CPL from fExec and turning it into IEMTLBE_F_PT_NO_USER).
1099	* Since most OSes will not share code between rings, this shouldn't
1100	* have any real effect on TB/memory/recompiling load.
1101	*/
1102	#define IEMTB_F_KEY_MASK ((UINT32_MAX & ~(IEM_F_X86_CTX_MASK \| IEMTB_F_TYPE_MASK)) \| IEM_F_X86_CTX_SMM)
1103	/** @} */
1104
1105	AssertCompile( (IEM_F_MODE_X86_16BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
1106	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1107	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_PROT_MASK));
1108	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_V86_MASK));
1109	AssertCompile( (IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
1110	AssertCompile( IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
1111	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_PROT_MASK));
1112	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
1113	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
1114	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1115	AssertCompile( IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
1116	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_V86_MASK));
1117	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
1118	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
1119	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_PROT_MASK);
1120	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
1121	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_PROT_MASK);
1122	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1123	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_V86_MASK);
1124
1125	AssertCompile( (IEM_F_MODE_X86_32BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
1126	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1127	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_PROT_MASK));
1128	AssertCompile( (IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
1129	AssertCompile( IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
1130	AssertCompile(!(IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_PROT_MASK));
1131	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
1132	AssertCompile(!(IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1133	AssertCompile( IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
1134	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
1135	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
1136	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_PROT_MASK);
1137
1138	AssertCompile( (IEM_F_MODE_X86_64BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT);
1139	AssertCompile( IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_PROT_MASK);
1140	AssertCompile(!(IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1141
1142	/** Native instruction type for use with the native code generator.
1143	* This is a byte (uint8_t) for x86 and amd64 and uint32_t for the other(s). */
1144	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
1145	typedef uint8_t IEMNATIVEINSTR;
1146	#else
1147	typedef uint32_t IEMNATIVEINSTR;
1148	#endif
1149	/** Pointer to a native instruction unit. */
1150	typedef IEMNATIVEINSTR *PIEMNATIVEINSTR;
1151	/** Pointer to a const native instruction unit. */
1152	typedef IEMNATIVEINSTR const *PCIEMNATIVEINSTR;
1153
1154	/**
1155	* A call for the threaded call table.
1156	*/
1157	typedef struct IEMTHRDEDCALLENTRY
1158	{
1159	/** The function to call (IEMTHREADEDFUNCS). */
1160	uint16_t enmFunction;
1161
1162	/** Instruction number in the TB (for statistics). */
1163	uint8_t idxInstr;
1164	/** The opcode length. */
1165	uint8_t cbOpcode;
1166	/** Offset into IEMTB::pabOpcodes. */
1167	uint16_t offOpcode;
1168
1169	/** TB lookup table index (7 bits) and large size (1 bits).
1170	*
1171	* The default size is 1 entry, but for indirect calls and returns we set the
1172	* top bit and allocate 4 (IEM_TB_LOOKUP_TAB_LARGE_SIZE) entries. The large
1173	* tables uses RIP for selecting the entry to use, as it is assumed a hash table
1174	* lookup isn't that slow compared to sequentially trying out 4 TBs.
1175	*
1176	* By default lookup table entry 0 for a TB is reserved as a fallback for
1177	* calltable entries w/o explicit entreis, so this member will be non-zero if
1178	* there is a lookup entry associated with this call.
1179	*
1180	* @sa IEM_TB_LOOKUP_TAB_GET_SIZE, IEM_TB_LOOKUP_TAB_GET_IDX
1181	*/
1182	uint8_t uTbLookup;
1183
1184	/** Unused atm. */
1185	uint8_t uUnused0;
1186
1187	/** Generic parameters. */
1188	uint64_t auParams[3];
1189	} IEMTHRDEDCALLENTRY;
1190	AssertCompileSize(IEMTHRDEDCALLENTRY, sizeof(uint64_t) * 4);
1191	/** Pointer to a threaded call entry. */
1192	typedef struct IEMTHRDEDCALLENTRY *PIEMTHRDEDCALLENTRY;
1193	/** Pointer to a const threaded call entry. */
1194	typedef IEMTHRDEDCALLENTRY const *PCIEMTHRDEDCALLENTRY;
1195
1196	/** The number of TB lookup table entries for a large allocation
1197	* (IEMTHRDEDCALLENTRY::uTbLookup bit 7 set). */
1198	#define IEM_TB_LOOKUP_TAB_LARGE_SIZE 4
1199	/** Get the lookup table size from IEMTHRDEDCALLENTRY::uTbLookup. */
1200	#define IEM_TB_LOOKUP_TAB_GET_SIZE(a_uTbLookup) (!((a_uTbLookup) & 0x80) ? 1 : IEM_TB_LOOKUP_TAB_LARGE_SIZE)
1201	/** Get the first lookup table index from IEMTHRDEDCALLENTRY::uTbLookup. */
1202	#define IEM_TB_LOOKUP_TAB_GET_IDX(a_uTbLookup) ((a_uTbLookup) & 0x7f)
1203	/** Get the lookup table index from IEMTHRDEDCALLENTRY::uTbLookup and RIP. */
1204	#define IEM_TB_LOOKUP_TAB_GET_IDX_WITH_RIP(a_uTbLookup, a_Rip) \
1205	(!((a_uTbLookup) & 0x80) ? (a_uTbLookup) & 0x7f : ((a_uTbLookup) & 0x7f) + ((a_Rip) & (IEM_TB_LOOKUP_TAB_LARGE_SIZE - 1)) )
1206
1207	/** Make a IEMTHRDEDCALLENTRY::uTbLookup value. */
1208	#define IEM_TB_LOOKUP_TAB_MAKE(a_idxTable, a_fLarge) ((a_idxTable) \| ((a_fLarge) ? 0x80 : 0))
1209
1210	/**
1211	* Native IEM TB 'function' typedef.
1212	*
1213	* This will throw/longjmp on occation.
1214	*
1215	* @note AMD64 doesn't have that many non-volatile registers and does sport
1216	* 32-bit address displacments, so we don't need pCtx.
1217	*
1218	* On ARM64 pCtx allows us to directly address the whole register
1219	* context without requiring a separate indexing register holding the
1220	* offset. This saves an instruction loading the offset for each guest
1221	* CPU context access, at the cost of a non-volatile register.
1222	* Fortunately, ARM64 has quite a lot more registers.
1223	*/
1224	typedef
1225	#ifdef RT_ARCH_AMD64
1226	int FNIEMTBNATIVE(PVMCPUCC pVCpu)
1227	#else
1228	int FNIEMTBNATIVE(PVMCPUCC pVCpu, PCPUMCTX pCtx)
1229	#endif
1230	#if RT_CPLUSPLUS_PREREQ(201700)
1231	IEM_NOEXCEPT_MAY_LONGJMP
1232	#endif
1233	;
1234	/** Pointer to a native IEM TB entry point function.
1235	* This will throw/longjmp on occation. */
1236	typedef FNIEMTBNATIVE *PFNIEMTBNATIVE;
1237
1238
1239	/**
1240	* Translation block debug info entry type.
1241	*/
1242	typedef enum IEMTBDBGENTRYTYPE
1243	{
1244	kIemTbDbgEntryType_Invalid = 0,
1245	/** The entry is for marking a native code position.
1246	* Entries following this all apply to this position. */
1247	kIemTbDbgEntryType_NativeOffset,
1248	/** The entry is for a new guest instruction. */
1249	kIemTbDbgEntryType_GuestInstruction,
1250	/** Marks the start of a threaded call. */
1251	kIemTbDbgEntryType_ThreadedCall,
1252	/** Marks the location of a label. */
1253	kIemTbDbgEntryType_Label,
1254	/** Info about a host register shadowing a guest register. */
1255	kIemTbDbgEntryType_GuestRegShadowing,
1256	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1257	/** Info about a host SIMD register shadowing a guest SIMD register. */
1258	kIemTbDbgEntryType_GuestSimdRegShadowing,
1259	#endif
1260	#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
1261	/** Info about a delayed RIP update. */
1262	kIemTbDbgEntryType_DelayedPcUpdate,
1263	#endif
1264	#if defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK) \|\| defined(IEMNATIVE_WITH_SIMD_REG_ALLOCATOR)
1265	/** Info about a shadowed guest register becoming dirty. */
1266	kIemTbDbgEntryType_GuestRegDirty,
1267	/** Info about register writeback/flush oepration. */
1268	kIemTbDbgEntryType_GuestRegWriteback,
1269	#endif
1270	kIemTbDbgEntryType_End
1271	} IEMTBDBGENTRYTYPE;
1272
1273	/**
1274	* Translation block debug info entry.
1275	*/
1276	typedef union IEMTBDBGENTRY
1277	{
1278	/** Plain 32-bit view. */
1279	uint32_t u;
1280
1281	/** Generic view for getting at the type field. */
1282	struct
1283	{
1284	/** IEMTBDBGENTRYTYPE */
1285	uint32_t uType : 4;
1286	uint32_t uTypeSpecific : 28;
1287	} Gen;
1288
1289	struct
1290	{
1291	/** kIemTbDbgEntryType_ThreadedCall1. */
1292	uint32_t uType : 4;
1293	/** Native code offset. */
1294	uint32_t offNative : 28;
1295	} NativeOffset;
1296
1297	struct
1298	{
1299	/** kIemTbDbgEntryType_GuestInstruction. */
1300	uint32_t uType : 4;
1301	uint32_t uUnused : 4;
1302	/** The IEM_F_XXX flags. */
1303	uint32_t fExec : 24;
1304	} GuestInstruction;
1305
1306	struct
1307	{
1308	/* kIemTbDbgEntryType_ThreadedCall. */
1309	uint32_t uType : 4;
1310	/** Set if the call was recompiled to native code, clear if just calling
1311	* threaded function. */
1312	uint32_t fRecompiled : 1;
1313	uint32_t uUnused : 11;
1314	/** The threaded call number (IEMTHREADEDFUNCS). */
1315	uint32_t enmCall : 16;
1316	} ThreadedCall;
1317
1318	struct
1319	{
1320	/* kIemTbDbgEntryType_Label. */
1321	uint32_t uType : 4;
1322	uint32_t uUnused : 4;
1323	/** The label type (IEMNATIVELABELTYPE). */
1324	uint32_t enmLabel : 8;
1325	/** The label data. */
1326	uint32_t uData : 16;
1327	} Label;
1328
1329	struct
1330	{
1331	/* kIemTbDbgEntryType_GuestRegShadowing. */
1332	uint32_t uType : 4;
1333	uint32_t uUnused : 4;
1334	/** The guest register being shadowed (IEMNATIVEGSTREG). */
1335	uint32_t idxGstReg : 8;
1336	/** The host new register number, UINT8_MAX if dropped. */
1337	uint32_t idxHstReg : 8;
1338	/** The previous host register number, UINT8_MAX if new. */
1339	uint32_t idxHstRegPrev : 8;
1340	} GuestRegShadowing;
1341
1342	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1343	struct
1344	{
1345	/* kIemTbDbgEntryType_GuestSimdRegShadowing. */
1346	uint32_t uType : 4;
1347	uint32_t uUnused : 4;
1348	/** The guest register being shadowed (IEMNATIVEGSTSIMDREG). */
1349	uint32_t idxGstSimdReg : 8;
1350	/** The host new register number, UINT8_MAX if dropped. */
1351	uint32_t idxHstSimdReg : 8;
1352	/** The previous host register number, UINT8_MAX if new. */
1353	uint32_t idxHstSimdRegPrev : 8;
1354	} GuestSimdRegShadowing;
1355	#endif
1356
1357	#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
1358	struct
1359	{
1360	/* kIemTbDbgEntryType_DelayedPcUpdate. */
1361	uint32_t uType : 4;
1362	/* The instruction offset added to the program counter. */
1363	uint32_t offPc : 14;
1364	/** Number of instructions skipped. */
1365	uint32_t cInstrSkipped : 14;
1366	} DelayedPcUpdate;
1367	#endif
1368
1369	#if defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK) \|\| defined(IEMNATIVE_WITH_SIMD_REG_ALLOCATOR)
1370	struct
1371	{
1372	/* kIemTbDbgEntryType_GuestRegDirty. */
1373	uint32_t uType : 4;
1374	uint32_t uUnused : 11;
1375	/** Flag whether this is about a SIMD (true) or general (false) register. */
1376	uint32_t fSimdReg : 1;
1377	/** The guest register index being marked as dirty. */
1378	uint32_t idxGstReg : 8;
1379	/** The host register number this register is shadowed in .*/
1380	uint32_t idxHstReg : 8;
1381	} GuestRegDirty;
1382
1383	struct
1384	{
1385	/* kIemTbDbgEntryType_GuestRegWriteback. */
1386	uint32_t uType : 4;
1387	/** Flag whether this is about a SIMD (true) or general (false) register flush. */
1388	uint32_t fSimdReg : 1;
1389	/** The mask shift. */
1390	uint32_t cShift : 2;
1391	/** The guest register mask being written back. */
1392	uint32_t fGstReg : 25;
1393	} GuestRegWriteback;
1394	#endif
1395
1396	} IEMTBDBGENTRY;
1397	AssertCompileSize(IEMTBDBGENTRY, sizeof(uint32_t));
1398	/** Pointer to a debug info entry. */
1399	typedef IEMTBDBGENTRY *PIEMTBDBGENTRY;
1400	/** Pointer to a const debug info entry. */
1401	typedef IEMTBDBGENTRY const *PCIEMTBDBGENTRY;
1402
1403	/**
1404	* Translation block debug info.
1405	*/
1406	typedef struct IEMTBDBG
1407	{
1408	/** Number of entries in aEntries. */
1409	uint32_t cEntries;
1410	/** The offset of the last kIemTbDbgEntryType_NativeOffset record. */
1411	uint32_t offNativeLast;
1412	/** Debug info entries. */
1413	RT_FLEXIBLE_ARRAY_EXTENSION
1414	IEMTBDBGENTRY aEntries[RT_FLEXIBLE_ARRAY];
1415	} IEMTBDBG;
1416	/** Pointer to TB debug info. */
1417	typedef IEMTBDBG *PIEMTBDBG;
1418	/** Pointer to const TB debug info. */
1419	typedef IEMTBDBG const *PCIEMTBDBG;
1420
1421
1422	/**
1423	* Translation block.
1424	*
1425	* The current plan is to just keep TBs and associated lookup hash table private
1426	* to each VCpu as that simplifies TB removal greatly (no races) and generally
1427	* avoids using expensive atomic primitives for updating lists and stuff.
1428	*/
1429	#pragma pack(2) /* to prevent the Thrd structure from being padded unnecessarily */
1430	typedef struct IEMTB
1431	{
1432	/** Next block with the same hash table entry. */
1433	struct IEMTB *pNext;
1434	/** Usage counter. */
1435	uint32_t cUsed;
1436	/** The IEMCPU::msRecompilerPollNow last time it was used. */
1437	uint32_t msLastUsed;
1438
1439	/** @name What uniquely identifies the block.
1440	* @{ */
1441	RTGCPHYS GCPhysPc;
1442	/** IEMTB_F_XXX (i.e. IEM_F_XXX ++). */
1443	uint32_t fFlags;
1444	union
1445	{
1446	struct
1447	{
1448	/*< Relevant CS X86DESCATTR_XXX bits. /
1449	uint16_t fAttr;
1450	} x86;
1451	};
1452	/** @} */
1453
1454	/** Number of opcode ranges. */
1455	uint8_t cRanges;
1456	/** Statistics: Number of instructions in the block. */
1457	uint8_t cInstructions;
1458
1459	/** Type specific info. */
1460	union
1461	{
1462	struct
1463	{
1464	/** The call sequence table. */
1465	PIEMTHRDEDCALLENTRY paCalls;
1466	/** Number of calls in paCalls. */
1467	uint16_t cCalls;
1468	/** Number of calls allocated. */
1469	uint16_t cAllocated;
1470	} Thrd;
1471	struct
1472	{
1473	/** The native instructions (PFNIEMTBNATIVE). */
1474	PIEMNATIVEINSTR paInstructions;
1475	/** Number of instructions pointed to by paInstructions. */
1476	uint32_t cInstructions;
1477	} Native;
1478	/** Generic view for zeroing when freeing. */
1479	struct
1480	{
1481	uintptr_t uPtr;
1482	uint32_t uData;
1483	} Gen;
1484	};
1485
1486	/** The allocation chunk this TB belongs to. */
1487	uint8_t idxAllocChunk;
1488	/** The number of entries in the lookup table.
1489	* Because we're out of space, the TB lookup table is located before the
1490	* opcodes pointed to by pabOpcodes. */
1491	uint8_t cTbLookupEntries;
1492
1493	/** Number of bytes of opcodes stored in pabOpcodes.
1494	* @todo this field isn't really needed, aRanges keeps the actual info. */
1495	uint16_t cbOpcodes;
1496	/** Pointer to the opcode bytes this block was recompiled from.
1497	* This also points to the TB lookup table, which starts cTbLookupEntries
1498	* entries before the opcodes (we don't have room atm for another point). */
1499	uint8_t *pabOpcodes;
1500
1501	/** Debug info if enabled.
1502	* This is only generated by the native recompiler. */
1503	PIEMTBDBG pDbgInfo;
1504
1505	/* --- 64 byte cache line end --- */
1506
1507	/** Opcode ranges.
1508	*
1509	* The opcode checkers and maybe TLB loading functions will use this to figure
1510	* out what to do. The parameter will specify an entry and the opcode offset to
1511	* start at and the minimum number of bytes to verify (instruction length).
1512	*
1513	* When VT-x and AMD-V looks up the opcode bytes for an exitting instruction,
1514	* they'll first translate RIP (+ cbInstr - 1) to a physical address using the
1515	* code TLB (must have a valid entry for that address) and scan the ranges to
1516	* locate the corresponding opcodes. Probably.
1517	*/
1518	struct IEMTBOPCODERANGE
1519	{
1520	/** Offset within pabOpcodes. */
1521	uint16_t offOpcodes;
1522	/** Number of bytes. */
1523	uint16_t cbOpcodes;
1524	/** The page offset. */
1525	RT_GCC_EXTENSION
1526	uint16_t offPhysPage : 12;
1527	/** Unused bits. */
1528	RT_GCC_EXTENSION
1529	uint16_t u2Unused : 2;
1530	/** Index into GCPhysPc + aGCPhysPages for the physical page address. */
1531	RT_GCC_EXTENSION
1532	uint16_t idxPhysPage : 2;
1533	} aRanges[8];
1534
1535	/** Physical pages that this TB covers.
1536	* The GCPhysPc w/o page offset is element zero, so starting here with 1. */
1537	RTGCPHYS aGCPhysPages[2];
1538	} IEMTB;
1539	#pragma pack()
1540	AssertCompileMemberAlignment(IEMTB, GCPhysPc, sizeof(RTGCPHYS));
1541	AssertCompileMemberAlignment(IEMTB, Thrd, sizeof(void *));
1542	AssertCompileMemberAlignment(IEMTB, pabOpcodes, sizeof(void *));
1543	AssertCompileMemberAlignment(IEMTB, pDbgInfo, sizeof(void *));
1544	AssertCompileMemberAlignment(IEMTB, aGCPhysPages, sizeof(RTGCPHYS));
1545	AssertCompileMemberOffset(IEMTB, aRanges, 64);
1546	AssertCompileMemberSize(IEMTB, aRanges[0], 6);
1547	#if 1
1548	AssertCompileSize(IEMTB, 128);
1549	# define IEMTB_SIZE_IS_POWER_OF_TWO /*< The IEMTB size is a power of two. /
1550	#else
1551	AssertCompileSize(IEMTB, 168);
1552	# undef IEMTB_SIZE_IS_POWER_OF_TWO
1553	#endif
1554
1555	/** Pointer to a translation block. */
1556	typedef IEMTB *PIEMTB;
1557	/** Pointer to a const translation block. */
1558	typedef IEMTB const *PCIEMTB;
1559
1560	/** Gets address of the given TB lookup table entry. */
1561	#define IEMTB_GET_TB_LOOKUP_TAB_ENTRY(a_pTb, a_idx) \
1562	((PIEMTB )&(a_pTb)->pabOpcodes[-(int)((a_pTb)->cTbLookupEntries - (a_idx)) sizeof(PIEMTB)])
1563
1564	/**
1565	* Gets the physical address for a TB opcode range.
1566	*/
1567	DECL_FORCE_INLINE(RTGCPHYS) iemTbGetRangePhysPageAddr(PCIEMTB pTb, uint8_t idxRange)
1568	{
1569	Assert(idxRange < RT_MIN(pTb->cRanges, RT_ELEMENTS(pTb->aRanges)));
1570	uint8_t const idxPage = pTb->aRanges[idxRange].idxPhysPage;
1571	Assert(idxPage <= RT_ELEMENTS(pTb->aGCPhysPages));
1572	if (idxPage == 0)
1573	return pTb->GCPhysPc & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
1574	Assert(!(pTb->aGCPhysPages[idxPage - 1] & GUEST_PAGE_OFFSET_MASK));
1575	return pTb->aGCPhysPages[idxPage - 1];
1576	}
1577
1578
1579	/**
1580	* A chunk of memory in the TB allocator.
1581	*/
1582	typedef struct IEMTBCHUNK
1583	{
1584	/** Pointer to the translation blocks in this chunk. */
1585	PIEMTB paTbs;
1586	#ifdef IN_RING0
1587	/** Allocation handle. */
1588	RTR0MEMOBJ hMemObj;
1589	#endif
1590	} IEMTBCHUNK;
1591
1592	/**
1593	* A per-CPU translation block allocator.
1594	*
1595	* Because of how the IEMTBCACHE uses the lower 6 bits of the TB address to keep
1596	* the length of the collision list, and of course also for cache line alignment
1597	* reasons, the TBs must be allocated with at least 64-byte alignment.
1598	* Memory is there therefore allocated using one of the page aligned allocators.
1599	*
1600	*
1601	* To avoid wasting too much memory, it is allocated piecemeal as needed,
1602	* in chunks (IEMTBCHUNK) of 2 MiB or more. The TB has an 8-bit chunk index
1603	* that enables us to quickly calculate the allocation bitmap position when
1604	* freeing the translation block.
1605	*/
1606	typedef struct IEMTBALLOCATOR
1607	{
1608	/** Magic value (IEMTBALLOCATOR_MAGIC). */
1609	uint32_t uMagic;
1610
1611	#ifdef IEMTB_SIZE_IS_POWER_OF_TWO
1612	/** Mask corresponding to cTbsPerChunk - 1. */
1613	uint32_t fChunkMask;
1614	/** Shift count corresponding to cTbsPerChunk. */
1615	uint8_t cChunkShift;
1616	#else
1617	uint32_t uUnused;
1618	uint8_t bUnused;
1619	#endif
1620	/** Number of chunks we're allowed to allocate. */
1621	uint8_t cMaxChunks;
1622	/** Number of chunks currently populated. */
1623	uint16_t cAllocatedChunks;
1624	/** Number of translation blocks per chunk. */
1625	uint32_t cTbsPerChunk;
1626	/** Chunk size. */
1627	uint32_t cbPerChunk;
1628
1629	/** The maximum number of TBs. */
1630	uint32_t cMaxTbs;
1631	/** Total number of TBs in the populated chunks.
1632	* (cAllocatedChunks * cTbsPerChunk) */
1633	uint32_t cTotalTbs;
1634	/** The current number of TBs in use.
1635	* The number of free TBs: cAllocatedTbs - cInUseTbs; */
1636	uint32_t cInUseTbs;
1637	/** Statistics: Number of the cInUseTbs that are native ones. */
1638	uint32_t cNativeTbs;
1639	/** Statistics: Number of the cInUseTbs that are threaded ones. */
1640	uint32_t cThreadedTbs;
1641
1642	/** Where to start pruning TBs from when we're out.
1643	* See iemTbAllocatorAllocSlow for details. */
1644	uint32_t iPruneFrom;
1645	/** Where to start pruning native TBs from when we're out of executable memory.
1646	* See iemTbAllocatorFreeupNativeSpace for details. */
1647	uint32_t iPruneNativeFrom;
1648	uint64_t u64Padding;
1649
1650	/** Statistics: Number of TB allocation calls. */
1651	STAMCOUNTER StatAllocs;
1652	/** Statistics: Number of TB free calls. */
1653	STAMCOUNTER StatFrees;
1654	/** Statistics: Time spend pruning. */
1655	STAMPROFILE StatPrune;
1656	/** Statistics: Time spend pruning native TBs. */
1657	STAMPROFILE StatPruneNative;
1658
1659	/** The delayed free list (see iemTbAlloctorScheduleForFree). */
1660	PIEMTB pDelayedFreeHead;
1661	/* Head of the list of free TBs. */
1662	PIEMTB pTbsFreeHead;
1663
1664	/** Allocation chunks. */
1665	IEMTBCHUNK aChunks[256];
1666	} IEMTBALLOCATOR;
1667	/** Pointer to a TB allocator. */
1668	typedef struct IEMTBALLOCATOR *PIEMTBALLOCATOR;
1669
1670	/** Magic value for the TB allocator (Emmet Harley Cohen). */
1671	#define IEMTBALLOCATOR_MAGIC UINT32_C(0x19900525)
1672
1673
1674	/**
1675	* A per-CPU translation block cache (hash table).
1676	*
1677	* The hash table is allocated once during IEM initialization and size double
1678	* the max TB count, rounded up to the nearest power of two (so we can use and
1679	* AND mask rather than a rest division when hashing).
1680	*/
1681	typedef struct IEMTBCACHE
1682	{
1683	/** Magic value (IEMTBCACHE_MAGIC). */
1684	uint32_t uMagic;
1685	/** Size of the hash table. This is a power of two. */
1686	uint32_t cHash;
1687	/** The mask corresponding to cHash. */
1688	uint32_t uHashMask;
1689	uint32_t uPadding;
1690
1691	/** @name Statistics
1692	* @{ */
1693	/** Number of collisions ever. */
1694	STAMCOUNTER cCollisions;
1695
1696	/** Statistics: Number of TB lookup misses. */
1697	STAMCOUNTER cLookupMisses;
1698	/** Statistics: Number of TB lookup hits via hash table (debug only). */
1699	STAMCOUNTER cLookupHits;
1700	/** Statistics: Number of TB lookup hits via TB associated lookup table (debug only). */
1701	STAMCOUNTER cLookupHitsViaTbLookupTable;
1702	STAMCOUNTER auPadding2[2];
1703	/** Statistics: Collision list length pruning. */
1704	STAMPROFILE StatPrune;
1705	/** @} */
1706
1707	/** The hash table itself.
1708	* @note The lower 6 bits of the pointer is used for keeping the collision
1709	* list length, so we can take action when it grows too long.
1710	* This works because TBs are allocated using a 64 byte (or
1711	* higher) alignment from page aligned chunks of memory, so the lower
1712	* 6 bits of the address will always be zero.
1713	* See IEMTBCACHE_PTR_COUNT_MASK, IEMTBCACHE_PTR_MAKE and friends.
1714	*/
1715	RT_FLEXIBLE_ARRAY_EXTENSION
1716	PIEMTB apHash[RT_FLEXIBLE_ARRAY];
1717	} IEMTBCACHE;
1718	/** Pointer to a per-CPU translation block cahce. */
1719	typedef IEMTBCACHE *PIEMTBCACHE;
1720
1721	/** Magic value for IEMTBCACHE (Johnny O'Neal). */
1722	#define IEMTBCACHE_MAGIC UINT32_C(0x19561010)
1723
1724	/** The collision count mask for IEMTBCACHE::apHash entries. */
1725	#define IEMTBCACHE_PTR_COUNT_MASK ((uintptr_t)0x3f)
1726	/** The max collision count for IEMTBCACHE::apHash entries before pruning. */
1727	#define IEMTBCACHE_PTR_MAX_COUNT ((uintptr_t)0x30)
1728	/** Combine a TB pointer and a collision list length into a value for an
1729	* IEMTBCACHE::apHash entry. */
1730	#define IEMTBCACHE_PTR_MAKE(a_pTb, a_cCount) (PIEMTB)((uintptr_t)(a_pTb) \| (a_cCount))
1731	/** Combine a TB pointer and a collision list length into a value for an
1732	* IEMTBCACHE::apHash entry. */
1733	#define IEMTBCACHE_PTR_GET_TB(a_pHashEntry) (PIEMTB)((uintptr_t)(a_pHashEntry) & ~IEMTBCACHE_PTR_COUNT_MASK)
1734	/** Combine a TB pointer and a collision list length into a value for an
1735	* IEMTBCACHE::apHash entry. */
1736	#define IEMTBCACHE_PTR_GET_COUNT(a_pHashEntry) ((uintptr_t)(a_pHashEntry) & IEMTBCACHE_PTR_COUNT_MASK)
1737
1738	/**
1739	* Calculates the hash table slot for a TB from physical PC address and TB flags.
1740	*/
1741	#define IEMTBCACHE_HASH(a_paCache, a_fTbFlags, a_GCPhysPc) \
1742	IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, (a_fTbFlags) & IEMTB_F_KEY_MASK, a_GCPhysPc)
1743
1744	/**
1745	* Calculates the hash table slot for a TB from physical PC address and TB
1746	* flags, ASSUMING the caller has applied IEMTB_F_KEY_MASK to @a a_fTbFlags.
1747	*/
1748	#define IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, a_fTbFlags, a_GCPhysPc) \
1749	(((uint32_t)(a_GCPhysPc) ^ (a_fTbFlags)) & (a_paCache)->uHashMask)
1750
1751
1752	/** @name IEMBRANCHED_F_XXX - Branched indicator (IEMCPU::fTbBranched).
1753	*
1754	* These flags parallels the main IEM_CIMPL_F_BRANCH_XXX flags.
1755	*
1756	* @{ */
1757	/** Value if no branching happened recently. */
1758	#define IEMBRANCHED_F_NO UINT8_C(0x00)
1759	/** Flag set if direct branch, clear if absolute or indirect. */
1760	#define IEMBRANCHED_F_DIRECT UINT8_C(0x01)
1761	/** Flag set if indirect branch, clear if direct or relative. */
1762	#define IEMBRANCHED_F_INDIRECT UINT8_C(0x02)
1763	/** Flag set if relative branch, clear if absolute or indirect. */
1764	#define IEMBRANCHED_F_RELATIVE UINT8_C(0x04)
1765	/** Flag set if conditional branch, clear if unconditional. */
1766	#define IEMBRANCHED_F_CONDITIONAL UINT8_C(0x08)
1767	/** Flag set if it's a far branch. */
1768	#define IEMBRANCHED_F_FAR UINT8_C(0x10)
1769	/** Flag set if the stack pointer is modified. */
1770	#define IEMBRANCHED_F_STACK UINT8_C(0x20)
1771	/** Flag set if the stack pointer and (maybe) the stack segment are modified. */
1772	#define IEMBRANCHED_F_STACK_FAR UINT8_C(0x40)
1773	/** Flag set (by IEM_MC_REL_JMP_XXX) if it's a zero bytes relative jump. */
1774	#define IEMBRANCHED_F_ZERO UINT8_C(0x80)
1775	/** @} */
1776
1777
1778	/**
1779	* The per-CPU IEM state.
1780	*/
1781	typedef struct IEMCPU
1782	{
1783	/** Info status code that needs to be propagated to the IEM caller.
1784	* This cannot be passed internally, as it would complicate all success
1785	* checks within the interpreter making the code larger and almost impossible
1786	* to get right. Instead, we'll store status codes to pass on here. Each
1787	* source of these codes will perform appropriate sanity checks. */
1788	int32_t rcPassUp; /* 0x00 */
1789	/** Execution flag, IEM_F_XXX. */
1790	uint32_t fExec; /* 0x04 */
1791
1792	/** @name Decoder state.
1793	* @{ */
1794	#ifdef IEM_WITH_CODE_TLB
1795	/** The offset of the next instruction byte. */
1796	uint32_t offInstrNextByte; /* 0x08 */
1797	/** The number of bytes available at pbInstrBuf for the current instruction.
1798	* This takes the max opcode length into account so that doesn't need to be
1799	* checked separately. */
1800	uint32_t cbInstrBuf; /* 0x0c */
1801	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
1802	* This can be NULL if the page isn't mappable for some reason, in which
1803	* case we'll do fallback stuff.
1804	*
1805	* If we're executing an instruction from a user specified buffer,
1806	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
1807	* aligned pointer but pointer to the user data.
1808	*
1809	* For instructions crossing pages, this will start on the first page and be
1810	* advanced to the next page by the time we've decoded the instruction. This
1811	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
1812	*/
1813	uint8_t const pbInstrBuf; / 0x10 */
1814	# if ARCH_BITS == 32
1815	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
1816	# endif
1817	/** The program counter corresponding to pbInstrBuf.
1818	* This is set to a non-canonical address when we need to invalidate it. */
1819	uint64_t uInstrBufPc; /* 0x18 */
1820	/** The guest physical address corresponding to pbInstrBuf. */
1821	RTGCPHYS GCPhysInstrBuf; /* 0x20 */
1822	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
1823	* This takes the CS segment limit into account.
1824	* @note Set to zero when the code TLB is flushed to trigger TLB reload. */
1825	uint16_t cbInstrBufTotal; /* 0x28 */
1826	/** Offset into pbInstrBuf of the first byte of the current instruction.
1827	* Can be negative to efficiently handle cross page instructions. */
1828	int16_t offCurInstrStart; /* 0x2a */
1829
1830	# ifndef IEM_WITH_OPAQUE_DECODER_STATE
1831	/** The prefix mask (IEM_OP_PRF_XXX). */
1832	uint32_t fPrefixes; /* 0x2c */
1833	/** The extra REX ModR/M register field bit (REX.R << 3). */
1834	uint8_t uRexReg; /* 0x30 */
1835	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1836	* (REX.B << 3). */
1837	uint8_t uRexB; /* 0x31 */
1838	/** The extra REX SIB index field bit (REX.X << 3). */
1839	uint8_t uRexIndex; /* 0x32 */
1840
1841	/** The effective segment register (X86_SREG_XXX). */
1842	uint8_t iEffSeg; /* 0x33 */
1843
1844	/** The offset of the ModR/M byte relative to the start of the instruction. */
1845	uint8_t offModRm; /* 0x34 */
1846
1847	# ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
1848	/** The current offset into abOpcode. */
1849	uint8_t offOpcode; /* 0x35 */
1850	# else
1851	uint8_t bUnused; /* 0x35 */
1852	# endif
1853	# else /* IEM_WITH_OPAQUE_DECODER_STATE */
1854	uint8_t abOpaqueDecoderPart1[0x36 - 0x2c];
1855	# endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1856
1857	#else /* !IEM_WITH_CODE_TLB */
1858	# ifndef IEM_WITH_OPAQUE_DECODER_STATE
1859	/** The size of what has currently been fetched into abOpcode. */
1860	uint8_t cbOpcode; /* 0x08 */
1861	/** The current offset into abOpcode. */
1862	uint8_t offOpcode; /* 0x09 */
1863	/** The offset of the ModR/M byte relative to the start of the instruction. */
1864	uint8_t offModRm; /* 0x0a */
1865
1866	/** The effective segment register (X86_SREG_XXX). */
1867	uint8_t iEffSeg; /* 0x0b */
1868
1869	/** The prefix mask (IEM_OP_PRF_XXX). */
1870	uint32_t fPrefixes; /* 0x0c */
1871	/** The extra REX ModR/M register field bit (REX.R << 3). */
1872	uint8_t uRexReg; /* 0x10 */
1873	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1874	* (REX.B << 3). */
1875	uint8_t uRexB; /* 0x11 */
1876	/** The extra REX SIB index field bit (REX.X << 3). */
1877	uint8_t uRexIndex; /* 0x12 */
1878
1879	# else /* IEM_WITH_OPAQUE_DECODER_STATE */
1880	uint8_t abOpaqueDecoderPart1[0x13 - 0x08];
1881	# endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1882	#endif /* !IEM_WITH_CODE_TLB */
1883
1884	#ifndef IEM_WITH_OPAQUE_DECODER_STATE
1885	/** The effective operand mode. */
1886	IEMMODE enmEffOpSize; /* 0x36, 0x13 */
1887	/** The default addressing mode. */
1888	IEMMODE enmDefAddrMode; /* 0x37, 0x14 */
1889	/** The effective addressing mode. */
1890	IEMMODE enmEffAddrMode; /* 0x38, 0x15 */
1891	/** The default operand mode. */
1892	IEMMODE enmDefOpSize; /* 0x39, 0x16 */
1893
1894	/** Prefix index (VEX.pp) for two byte and three byte tables. */
1895	uint8_t idxPrefix; /* 0x3a, 0x17 */
1896	/** 3rd VEX/EVEX/XOP register.
1897	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
1898	uint8_t uVex3rdReg; /* 0x3b, 0x18 */
1899	/** The VEX/EVEX/XOP length field. */
1900	uint8_t uVexLength; /* 0x3c, 0x19 */
1901	/** Additional EVEX stuff. */
1902	uint8_t fEvexStuff; /* 0x3d, 0x1a */
1903
1904	# ifndef IEM_WITH_CODE_TLB
1905	/** Explicit alignment padding. */
1906	uint8_t abAlignment2a[1]; /* 0x1b */
1907	# endif
1908	/** The FPU opcode (FOP). */
1909	uint16_t uFpuOpcode; /* 0x3e, 0x1c */
1910	# ifndef IEM_WITH_CODE_TLB
1911	/** Explicit alignment padding. */
1912	uint8_t abAlignment2b[2]; /* 0x1e */
1913	# endif
1914
1915	/** The opcode bytes. */
1916	uint8_t abOpcode[15]; /* 0x40, 0x20 */
1917	/** Explicit alignment padding. */
1918	# ifdef IEM_WITH_CODE_TLB
1919	//uint8_t abAlignment2c[0x4f - 0x4f]; /* 0x4f */
1920	# else
1921	uint8_t abAlignment2c[0x4f - 0x2f]; /* 0x2f */
1922	# endif
1923
1924	#else /* IEM_WITH_OPAQUE_DECODER_STATE */
1925	# ifdef IEM_WITH_CODE_TLB
1926	uint8_t abOpaqueDecoderPart2[0x4f - 0x36];
1927	# else
1928	uint8_t abOpaqueDecoderPart2[0x4f - 0x13];
1929	# endif
1930	#endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1931	/** @} */
1932
1933
1934	/** The number of active guest memory mappings. */
1935	uint8_t cActiveMappings; /* 0x4f, 0x4f */
1936
1937	/** Records for tracking guest memory mappings. */
1938	struct
1939	{
1940	/** The address of the mapped bytes. */
1941	R3R0PTRTYPE(void *) pv;
1942	/** The access flags (IEM_ACCESS_XXX).
1943	* IEM_ACCESS_INVALID if the entry is unused. */
1944	uint32_t fAccess;
1945	#if HC_ARCH_BITS == 64
1946	uint32_t u32Alignment4; /*< Alignment padding. /
1947	#endif
1948	} aMemMappings[3]; /* 0x50 LB 0x30 */
1949
1950	/** Locking records for the mapped memory. */
1951	union
1952	{
1953	PGMPAGEMAPLOCK Lock;
1954	uint64_t au64Padding[2];
1955	} aMemMappingLocks[3]; /* 0x80 LB 0x30 */
1956
1957	/** Bounce buffer info.
1958	* This runs in parallel to aMemMappings. */
1959	struct
1960	{
1961	/** The physical address of the first byte. */
1962	RTGCPHYS GCPhysFirst;
1963	/** The physical address of the second page. */
1964	RTGCPHYS GCPhysSecond;
1965	/** The number of bytes in the first page. */
1966	uint16_t cbFirst;
1967	/** The number of bytes in the second page. */
1968	uint16_t cbSecond;
1969	/** Whether it's unassigned memory. */
1970	bool fUnassigned;
1971	/** Explicit alignment padding. */
1972	bool afAlignment5[3];
1973	} aMemBbMappings[3]; /* 0xb0 LB 0x48 */
1974
1975	/** The flags of the current exception / interrupt. */
1976	uint32_t fCurXcpt; /* 0xf8 */
1977	/** The current exception / interrupt. */
1978	uint8_t uCurXcpt; /* 0xfc */
1979	/** Exception / interrupt recursion depth. */
1980	int8_t cXcptRecursions; /* 0xfb */
1981
1982	/** The next unused mapping index.
1983	* @todo try find room for this up with cActiveMappings. */
1984	uint8_t iNextMapping; /* 0xfd */
1985	uint8_t abAlignment7[1];
1986
1987	/** Bounce buffer storage.
1988	* This runs in parallel to aMemMappings and aMemBbMappings. */
1989	struct
1990	{
1991	uint8_t ab[512];
1992	} aBounceBuffers[3]; /* 0x100 LB 0x600 */
1993
1994
1995	/** Pointer set jump buffer - ring-3 context. */
1996	R3PTRTYPE(jmp_buf *) pJmpBufR3;
1997	/** Pointer set jump buffer - ring-0 context. */
1998	R0PTRTYPE(jmp_buf *) pJmpBufR0;
1999
2000	/** @todo Should move this near @a fCurXcpt later. */
2001	/** The CR2 for the current exception / interrupt. */
2002	uint64_t uCurXcptCr2;
2003	/** The error code for the current exception / interrupt. */
2004	uint32_t uCurXcptErr;
2005
2006	/** @name Statistics
2007	* @{ */
2008	/** The number of instructions we've executed. */
2009	uint32_t cInstructions;
2010	/** The number of potential exits. */
2011	uint32_t cPotentialExits;
2012	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
2013	* This may contain uncommitted writes. */
2014	uint32_t cbWritten;
2015	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
2016	uint32_t cRetInstrNotImplemented;
2017	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
2018	uint32_t cRetAspectNotImplemented;
2019	/** Counts informational statuses returned (other than VINF_SUCCESS). */
2020	uint32_t cRetInfStatuses;
2021	/** Counts other error statuses returned. */
2022	uint32_t cRetErrStatuses;
2023	/** Number of times rcPassUp has been used. */
2024	uint32_t cRetPassUpStatus;
2025	/** Number of times RZ left with instruction commit pending for ring-3. */
2026	uint32_t cPendingCommit;
2027	/** Number of misaligned (host sense) atomic instruction accesses. */
2028	uint32_t cMisalignedAtomics;
2029	/** Number of long jumps. */
2030	uint32_t cLongJumps;
2031	/** @} */
2032
2033	/** @name Target CPU information.
2034	* @{ */
2035	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
2036	/** The target CPU. */
2037	uint8_t uTargetCpu;
2038	#else
2039	uint8_t bTargetCpuPadding;
2040	#endif
2041	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
2042	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
2043	* native host support and the 2nd for when there is.
2044	*
2045	* The two values are typically indexed by a g_CpumHostFeatures bit.
2046	*
2047	* This is for instance used for the BSF & BSR instructions where AMD and
2048	* Intel CPUs produce different EFLAGS. */
2049	uint8_t aidxTargetCpuEflFlavour[2];
2050
2051	/** The CPU vendor. */
2052	CPUMCPUVENDOR enmCpuVendor;
2053	/** @} */
2054
2055	/** @name Host CPU information.
2056	* @{ */
2057	/** The CPU vendor. */
2058	CPUMCPUVENDOR enmHostCpuVendor;
2059	/** @} */
2060
2061	/** Counts RDMSR \#GP(0) LogRel(). */
2062	uint8_t cLogRelRdMsr;
2063	/** Counts WRMSR \#GP(0) LogRel(). */
2064	uint8_t cLogRelWrMsr;
2065	/** Alignment padding. */
2066	uint8_t abAlignment9[42];
2067
2068	/** @name Recompilation
2069	* @{ */
2070	/** Pointer to the current translation block.
2071	* This can either be one being executed or one being compiled. */
2072	R3PTRTYPE(PIEMTB) pCurTbR3;
2073	#ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
2074	/** Frame pointer for the last native TB to execute. */
2075	R3PTRTYPE(void *) pvTbFramePointerR3;
2076	#else
2077	R3PTRTYPE(void *) pvUnusedR3;
2078	#endif
2079	#ifdef IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS
2080	/** The saved host floating point control register (MXCSR on x86, FPCR on arm64)
2081	* needing restore when the TB finished, IEMNATIVE_SIMD_FP_CTRL_REG_NOT_MODIFIED indicates the TB
2082	* didn't modify it so we don't need to restore it. */
2083	# ifdef RT_ARCH_AMD64
2084	uint32_t uRegFpCtrl;
2085	/** Temporary copy of MXCSR for stmxcsr/ldmxcsr (so we don't have to fiddle with stack pointers). */
2086	uint32_t uRegMxcsrTmp;
2087	# elif defined(RT_ARCH_ARM64)
2088	uint64_t uRegFpCtrl;
2089	# else
2090	# error "Port me"
2091	# endif
2092	#else
2093	uint64_t u64Unused;
2094	#endif
2095	/** Fixed TB used for threaded recompilation.
2096	* This is allocated once with maxed-out sizes and re-used afterwards. */
2097	R3PTRTYPE(PIEMTB) pThrdCompileTbR3;
2098	/** Pointer to the ring-3 TB cache for this EMT. */
2099	R3PTRTYPE(PIEMTBCACHE) pTbCacheR3;
2100	/** Pointer to the ring-3 TB lookup entry.
2101	* This either points to pTbLookupEntryDummyR3 or an actually lookuptable
2102	* entry, thus it can always safely be used w/o NULL checking. */
2103	R3PTRTYPE(PIEMTB *) ppTbLookupEntryR3;
2104	/** The PC (RIP) at the start of pCurTbR3/pCurTbR0.
2105	* The TBs are based on physical addresses, so this is needed to correleated
2106	* RIP to opcode bytes stored in the TB (AMD-V / VT-x). */
2107	uint64_t uCurTbStartPc;
2108	/** Number of threaded TBs executed. */
2109	uint64_t cTbExecThreaded;
2110	/** Number of native TBs executed. */
2111	uint64_t cTbExecNative;
2112	/** Whether we need to check the opcode bytes for the current instruction.
2113	* This is set by a previous instruction if it modified memory or similar. */
2114	bool fTbCheckOpcodes;
2115	/** Indicates whether and how we just branched - IEMBRANCHED_F_XXX. */
2116	uint8_t fTbBranched;
2117	/** Set when GCPhysInstrBuf is updated because of a page crossing. */
2118	bool fTbCrossedPage;
2119	/** Whether to end the current TB. */
2120	bool fEndTb;
2121	/** Number of instructions before we need emit an IRQ check call again.
2122	* This helps making sure we don't execute too long w/o checking for
2123	* interrupts and immediately following instructions that may enable
2124	* interrupts (e.g. POPF, IRET, STI). With STI an additional hack is
2125	* required to make sure we check following the next instruction as well, see
2126	* fTbCurInstrIsSti. */
2127	uint8_t cInstrTillIrqCheck;
2128	/** Indicates that the current instruction is an STI. This is set by the
2129	* iemCImpl_sti code and subsequently cleared by the recompiler. */
2130	bool fTbCurInstrIsSti;
2131	/** The size of the IEMTB::pabOpcodes allocation in pThrdCompileTbR3. */
2132	uint16_t cbOpcodesAllocated;
2133	/** The current instruction number in a native TB.
2134	* This is set by code that may trigger an unexpected TB exit (throw/longjmp)
2135	* and will be picked up by the TB execution loop. Only used when
2136	* IEMNATIVE_WITH_INSTRUCTION_COUNTING is defined. */
2137	uint8_t idxTbCurInstr;
2138	/** Spaced reserved for recompiler data / alignment. */
2139	bool afRecompilerStuff1[3];
2140	/** The virtual sync time at the last timer poll call. */
2141	uint32_t msRecompilerPollNow;
2142	/** The IEMTB::cUsed value when to attempt native recompilation of a TB. */
2143	uint32_t uTbNativeRecompileAtUsedCount;
2144	/** The IEM_CIMPL_F_XXX mask for the current instruction. */
2145	uint32_t fTbCurInstr;
2146	/** The IEM_CIMPL_F_XXX mask for the previous instruction. */
2147	uint32_t fTbPrevInstr;
2148	/** Strict: Tracking skipped EFLAGS calculations. Any bits set here are
2149	* currently not up to date in EFLAGS. */
2150	uint32_t fSkippingEFlags;
2151	/** Previous GCPhysInstrBuf value - only valid if fTbCrossedPage is set. */
2152	RTGCPHYS GCPhysInstrBufPrev;
2153	/** Pointer to the ring-3 TB allocator for this EMT. */
2154	R3PTRTYPE(PIEMTBALLOCATOR) pTbAllocatorR3;
2155	/** Pointer to the ring-3 executable memory allocator for this EMT. */
2156	R3PTRTYPE(struct IEMEXECMEMALLOCATOR *) pExecMemAllocatorR3;
2157	/** Pointer to the native recompiler state for ring-3. */
2158	R3PTRTYPE(struct IEMRECOMPILERSTATE *) pNativeRecompilerStateR3;
2159	/** Dummy entry for ppTbLookupEntryR3. */
2160	R3PTRTYPE(PIEMTB) pTbLookupEntryDummyR3;
2161
2162	/** Dummy TLB entry used for accesses to pages with databreakpoints. */
2163	IEMTLBENTRY DataBreakpointTlbe;
2164
2165	/** Threaded TB statistics: Times TB execution was broken off before reaching the end. */
2166	STAMCOUNTER StatTbThreadedExecBreaks;
2167	/** Statistics: Times BltIn_CheckIrq breaks out of the TB. */
2168	STAMCOUNTER StatCheckIrqBreaks;
2169	/** Statistics: Times BltIn_CheckMode breaks out of the TB. */
2170	STAMCOUNTER StatCheckModeBreaks;
2171	/** Threaded TB statistics: Times execution break on call with lookup entries. */
2172	STAMCOUNTER StatTbThreadedExecBreaksWithLookup;
2173	/** Threaded TB statistics: Times execution break on call without lookup entries. */
2174	STAMCOUNTER StatTbThreadedExecBreaksWithoutLookup;
2175	/** Statistics: Times a post jump target check missed and had to find new TB. */
2176	STAMCOUNTER StatCheckBranchMisses;
2177	/** Statistics: Times a jump or page crossing required a TB with CS.LIM checking. */
2178	STAMCOUNTER StatCheckNeedCsLimChecking;
2179	/** Statistics: Times a loop was detected within a TB.. */
2180	STAMCOUNTER StatTbLoopInTbDetected;
2181	/** Exec memory allocator statistics: Number of times allocaintg executable memory failed. */
2182	STAMCOUNTER StatNativeExecMemInstrBufAllocFailed;
2183	/** Native TB statistics: Number of fully recompiled TBs. */
2184	STAMCOUNTER StatNativeFullyRecompiledTbs;
2185	/** TB statistics: Number of instructions per TB. */
2186	STAMPROFILE StatTbInstr;
2187	/** TB statistics: Number of TB lookup table entries per TB. */
2188	STAMPROFILE StatTbLookupEntries;
2189	/** Threaded TB statistics: Number of calls per TB. */
2190	STAMPROFILE StatTbThreadedCalls;
2191	/** Native TB statistics: Native code size per TB. */
2192	STAMPROFILE StatTbNativeCode;
2193	/** Native TB statistics: Profiling native recompilation. */
2194	STAMPROFILE StatNativeRecompilation;
2195	/** Native TB statistics: Number of calls per TB that were recompiled properly. */
2196	STAMPROFILE StatNativeCallsRecompiled;
2197	/** Native TB statistics: Number of threaded calls per TB that weren't recompiled. */
2198	STAMPROFILE StatNativeCallsThreaded;
2199	/** Native recompiled execution: TLB hits for data fetches. */
2200	STAMCOUNTER StatNativeTlbHitsForFetch;
2201	/** Native recompiled execution: TLB hits for data stores. */
2202	STAMCOUNTER StatNativeTlbHitsForStore;
2203	/** Native recompiled execution: TLB hits for stack accesses. */
2204	STAMCOUNTER StatNativeTlbHitsForStack;
2205	/** Native recompiled execution: TLB hits for mapped accesses. */
2206	STAMCOUNTER StatNativeTlbHitsForMapped;
2207	/** Native recompiled execution: Code TLB misses for new page. */
2208	STAMCOUNTER StatNativeCodeTlbMissesNewPage;
2209	/** Native recompiled execution: Code TLB hits for new page. */
2210	STAMCOUNTER StatNativeCodeTlbHitsForNewPage;
2211	/** Native recompiled execution: Code TLB misses for new page with offset. */
2212	STAMCOUNTER StatNativeCodeTlbMissesNewPageWithOffset;
2213	/** Native recompiled execution: Code TLB hits for new page with offset. */
2214	STAMCOUNTER StatNativeCodeTlbHitsForNewPageWithOffset;
2215
2216	/** Native recompiler: Number of calls to iemNativeRegAllocFindFree. */
2217	STAMCOUNTER StatNativeRegFindFree;
2218	/** Native recompiler: Number of times iemNativeRegAllocFindFree needed
2219	* to free a variable. */
2220	STAMCOUNTER StatNativeRegFindFreeVar;
2221	/** Native recompiler: Number of times iemNativeRegAllocFindFree did
2222	* not need to free any variables. */
2223	STAMCOUNTER StatNativeRegFindFreeNoVar;
2224	/** Native recompiler: Liveness info freed shadowed guest registers in
2225	* iemNativeRegAllocFindFree. */
2226	STAMCOUNTER StatNativeRegFindFreeLivenessUnshadowed;
2227	/** Native recompiler: Liveness info helped with the allocation in
2228	* iemNativeRegAllocFindFree. */
2229	STAMCOUNTER StatNativeRegFindFreeLivenessHelped;
2230
2231	/** Native recompiler: Number of times status flags calc has been skipped. */
2232	STAMCOUNTER StatNativeEflSkippedArithmetic;
2233	/** Native recompiler: Number of times status flags calc has been skipped. */
2234	STAMCOUNTER StatNativeEflSkippedLogical;
2235
2236	/** Native recompiler: Number of opportunities to skip EFLAGS.CF updating. */
2237	STAMCOUNTER StatNativeLivenessEflCfSkippable;
2238	/** Native recompiler: Number of opportunities to skip EFLAGS.PF updating. */
2239	STAMCOUNTER StatNativeLivenessEflPfSkippable;
2240	/** Native recompiler: Number of opportunities to skip EFLAGS.AF updating. */
2241	STAMCOUNTER StatNativeLivenessEflAfSkippable;
2242	/** Native recompiler: Number of opportunities to skip EFLAGS.ZF updating. */
2243	STAMCOUNTER StatNativeLivenessEflZfSkippable;
2244	/** Native recompiler: Number of opportunities to skip EFLAGS.SF updating. */
2245	STAMCOUNTER StatNativeLivenessEflSfSkippable;
2246	/** Native recompiler: Number of opportunities to skip EFLAGS.OF updating. */
2247	STAMCOUNTER StatNativeLivenessEflOfSkippable;
2248	/** Native recompiler: Number of required EFLAGS.CF updates. */
2249	STAMCOUNTER StatNativeLivenessEflCfRequired;
2250	/** Native recompiler: Number of required EFLAGS.PF updates. */
2251	STAMCOUNTER StatNativeLivenessEflPfRequired;
2252	/** Native recompiler: Number of required EFLAGS.AF updates. */
2253	STAMCOUNTER StatNativeLivenessEflAfRequired;
2254	/** Native recompiler: Number of required EFLAGS.ZF updates. */
2255	STAMCOUNTER StatNativeLivenessEflZfRequired;
2256	/** Native recompiler: Number of required EFLAGS.SF updates. */
2257	STAMCOUNTER StatNativeLivenessEflSfRequired;
2258	/** Native recompiler: Number of required EFLAGS.OF updates. */
2259	STAMCOUNTER StatNativeLivenessEflOfRequired;
2260	/** Native recompiler: Number of potentially delayable EFLAGS.CF updates. */
2261	STAMCOUNTER StatNativeLivenessEflCfDelayable;
2262	/** Native recompiler: Number of potentially delayable EFLAGS.PF updates. */
2263	STAMCOUNTER StatNativeLivenessEflPfDelayable;
2264	/** Native recompiler: Number of potentially delayable EFLAGS.AF updates. */
2265	STAMCOUNTER StatNativeLivenessEflAfDelayable;
2266	/** Native recompiler: Number of potentially delayable EFLAGS.ZF updates. */
2267	STAMCOUNTER StatNativeLivenessEflZfDelayable;
2268	/** Native recompiler: Number of potentially delayable EFLAGS.SF updates. */
2269	STAMCOUNTER StatNativeLivenessEflSfDelayable;
2270	/** Native recompiler: Number of potentially delayable EFLAGS.OF updates. */
2271	STAMCOUNTER StatNativeLivenessEflOfDelayable;
2272
2273	/** Native recompiler: Number of potential PC updates in total. */
2274	STAMCOUNTER StatNativePcUpdateTotal;
2275	/** Native recompiler: Number of PC updates which could be delayed. */
2276	STAMCOUNTER StatNativePcUpdateDelayed;
2277
2278	//#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
2279	/** Native recompiler: Number of calls to iemNativeSimdRegAllocFindFree. */
2280	STAMCOUNTER StatNativeSimdRegFindFree;
2281	/** Native recompiler: Number of times iemNativeSimdRegAllocFindFree needed
2282	* to free a variable. */
2283	STAMCOUNTER StatNativeSimdRegFindFreeVar;
2284	/** Native recompiler: Number of times iemNativeSimdRegAllocFindFree did
2285	* not need to free any variables. */
2286	STAMCOUNTER StatNativeSimdRegFindFreeNoVar;
2287	/** Native recompiler: Liveness info freed shadowed guest registers in
2288	* iemNativeSimdRegAllocFindFree. */
2289	STAMCOUNTER StatNativeSimdRegFindFreeLivenessUnshadowed;
2290	/** Native recompiler: Liveness info helped with the allocation in
2291	* iemNativeSimdRegAllocFindFree. */
2292	STAMCOUNTER StatNativeSimdRegFindFreeLivenessHelped;
2293
2294	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks. */
2295	STAMCOUNTER StatNativeMaybeDeviceNotAvailXcptCheckPotential;
2296	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() checks. */
2297	STAMCOUNTER StatNativeMaybeWaitDeviceNotAvailXcptCheckPotential;
2298	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks. */
2299	STAMCOUNTER StatNativeMaybeSseXcptCheckPotential;
2300	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks. */
2301	STAMCOUNTER StatNativeMaybeAvxXcptCheckPotential;
2302
2303	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks omitted. */
2304	STAMCOUNTER StatNativeMaybeDeviceNotAvailXcptCheckOmitted;
2305	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() checks omitted. */
2306	STAMCOUNTER StatNativeMaybeWaitDeviceNotAvailXcptCheckOmitted;
2307	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks omitted. */
2308	STAMCOUNTER StatNativeMaybeSseXcptCheckOmitted;
2309	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks omitted. */
2310	STAMCOUNTER StatNativeMaybeAvxXcptCheckOmitted;
2311	//#endif
2312
2313	/** Native recompiler: The TB finished executing completely without jumping to a an exit label.
2314	* Not availabe in release builds. */
2315	STAMCOUNTER StatNativeTbFinished;
2316	/** Native recompiler: The TB finished executing jumping to the ReturnBreak label. */
2317	STAMCOUNTER StatNativeTbExitReturnBreak;
2318	/** Native recompiler: The TB finished executing jumping to the ReturnBreakFF label. */
2319	STAMCOUNTER StatNativeTbExitReturnBreakFF;
2320	/** Native recompiler: The TB finished executing jumping to the ReturnWithFlags label. */
2321	STAMCOUNTER StatNativeTbExitReturnWithFlags;
2322	/** Native recompiler: The TB finished executing with other non-zero status. */
2323	STAMCOUNTER StatNativeTbExitReturnOtherStatus;
2324	/** Native recompiler: The TB finished executing via throw / long jump. */
2325	STAMCOUNTER StatNativeTbExitLongJump;
2326	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2327	* label, but directly jumped to the next TB, scenario \#1 w/o IRQ checks. */
2328	STAMCOUNTER StatNativeTbExitDirectLinking1NoIrq;
2329	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2330	* label, but directly jumped to the next TB, scenario \#1 with IRQ checks. */
2331	STAMCOUNTER StatNativeTbExitDirectLinking1Irq;
2332	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2333	* label, but directly jumped to the next TB, scenario \#1 w/o IRQ checks. */
2334	STAMCOUNTER StatNativeTbExitDirectLinking2NoIrq;
2335	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2336	* label, but directly jumped to the next TB, scenario \#2 with IRQ checks. */
2337	STAMCOUNTER StatNativeTbExitDirectLinking2Irq;
2338
2339	/** Native recompiler: The TB finished executing jumping to the RaiseDe label. */
2340	STAMCOUNTER StatNativeTbExitRaiseDe;
2341	/** Native recompiler: The TB finished executing jumping to the RaiseUd label. */
2342	STAMCOUNTER StatNativeTbExitRaiseUd;
2343	/** Native recompiler: The TB finished executing jumping to the RaiseSseRelated label. */
2344	STAMCOUNTER StatNativeTbExitRaiseSseRelated;
2345	/** Native recompiler: The TB finished executing jumping to the RaiseAvxRelated label. */
2346	STAMCOUNTER StatNativeTbExitRaiseAvxRelated;
2347	/** Native recompiler: The TB finished executing jumping to the RaiseSseAvxFpRelated label. */
2348	STAMCOUNTER StatNativeTbExitRaiseSseAvxFpRelated;
2349	/** Native recompiler: The TB finished executing jumping to the RaiseNm label. */
2350	STAMCOUNTER StatNativeTbExitRaiseNm;
2351	/** Native recompiler: The TB finished executing jumping to the RaiseGp0 label. */
2352	STAMCOUNTER StatNativeTbExitRaiseGp0;
2353	/** Native recompiler: The TB finished executing jumping to the RaiseMf label. */
2354	STAMCOUNTER StatNativeTbExitRaiseMf;
2355	/** Native recompiler: The TB finished executing jumping to the RaiseXf label. */
2356	STAMCOUNTER StatNativeTbExitRaiseXf;
2357	/** Native recompiler: The TB finished executing jumping to the ObsoleteTb label. */
2358	STAMCOUNTER StatNativeTbExitObsoleteTb;
2359
2360	/** Native recompiler: Failure situations with direct linking scenario \#1.
2361	* Counter with StatNativeTbExitReturnBreak. Not in release builds.
2362	* @{ */
2363	STAMCOUNTER StatNativeTbExitDirectLinking1NoTb;
2364	STAMCOUNTER StatNativeTbExitDirectLinking1MismatchGCPhysPc;
2365	STAMCOUNTER StatNativeTbExitDirectLinking1MismatchFlags;
2366	STAMCOUNTER StatNativeTbExitDirectLinking1PendingIrq;
2367	/** @} */
2368
2369	/** Native recompiler: Failure situations with direct linking scenario \#2.
2370	* Counter with StatNativeTbExitReturnBreak. Not in release builds.
2371	* @{ */
2372	STAMCOUNTER StatNativeTbExitDirectLinking2NoTb;
2373	STAMCOUNTER StatNativeTbExitDirectLinking2MismatchGCPhysPc;
2374	STAMCOUNTER StatNativeTbExitDirectLinking2MismatchFlags;
2375	STAMCOUNTER StatNativeTbExitDirectLinking2PendingIrq;
2376	/** @} */
2377
2378	/** iemMemMap and iemMemMapJmp statistics.
2379	* @{ */
2380	STAMCOUNTER StatMemMapJmp;
2381	STAMCOUNTER StatMemMapNoJmp;
2382	STAMCOUNTER StatMemBounceBufferCrossPage;
2383	STAMCOUNTER StatMemBounceBufferMapPhys;
2384	/** @} */
2385
2386	#ifdef IEM_WITH_TLB_TRACE
2387	uint64_t au64Padding[2];
2388	#else
2389	uint64_t au64Padding[4];
2390	#endif
2391	/** @} */
2392
2393	#ifdef IEM_WITH_TLB_TRACE
2394	/** The end (next) trace entry. */
2395	uint32_t idxTlbTraceEntry;
2396	/** Number of trace entries allocated expressed as a power of two. */
2397	uint32_t cTlbTraceEntriesShift;
2398	/** The trace entries. */
2399	PIEMTLBTRACEENTRY paTlbTraceEntries;
2400	#endif
2401
2402	/** Data TLB.
2403	* @remarks Must be 64-byte aligned. */
2404	IEMTLB DataTlb;
2405	/** Instruction TLB.
2406	* @remarks Must be 64-byte aligned. */
2407	IEMTLB CodeTlb;
2408
2409	/** Exception statistics. */
2410	STAMCOUNTER aStatXcpts[32];
2411	/** Interrupt statistics. */
2412	uint32_t aStatInts[256];
2413
2414	#if defined(VBOX_WITH_STATISTICS) && !defined(DOXYGEN_RUNNING) && !defined(IEM_WITHOUT_INSTRUCTION_STATS)
2415	/** Instruction statistics for ring-0/raw-mode. */
2416	IEMINSTRSTATS StatsRZ;
2417	/** Instruction statistics for ring-3. */
2418	IEMINSTRSTATS StatsR3;
2419	# ifdef VBOX_WITH_IEM_RECOMPILER
2420	/** Statistics per threaded function call.
2421	* Updated by both the threaded and native recompilers. */
2422	uint32_t acThreadedFuncStats[0x6000 /24576/];
2423	# endif
2424	#endif
2425	} IEMCPU;
2426	AssertCompileMemberOffset(IEMCPU, cActiveMappings, 0x4f);
2427	AssertCompileMemberAlignment(IEMCPU, aMemMappings, 16);
2428	AssertCompileMemberAlignment(IEMCPU, aMemMappingLocks, 16);
2429	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 64);
2430	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
2431	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
2432
2433	/** Pointer to the per-CPU IEM state. */
2434	typedef IEMCPU *PIEMCPU;
2435	/** Pointer to the const per-CPU IEM state. */
2436	typedef IEMCPU const *PCIEMCPU;
2437
2438	/** @def IEMNATIVE_SIMD_FP_CTRL_REG_NOT_MODIFIED
2439	* Value indicating the TB didn't modified the floating point control register.
2440	* @note Neither FPCR nor MXCSR accept this as a valid value (MXCSR is not fully populated,
2441	* FPCR has the upper 32-bit reserved), so this is safe. */
2442	#if defined(IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS) \|\| defined(DOXYGEN_RUNNING)
2443	# ifdef RT_ARCH_AMD64
2444	# define IEMNATIVE_SIMD_FP_CTRL_REG_NOT_MODIFIED UINT32_MAX
2445	# elif defined(RT_ARCH_ARM64)
2446	# define IEMNATIVE_SIMD_FP_CTRL_REG_NOT_MODIFIED UINT64_MAX
2447	# else
2448	# error "Port me"
2449	# endif
2450	#endif
2451
2452	/** @def IEM_GET_CTX
2453	* Gets the guest CPU context for the calling EMT.
2454	* @returns PCPUMCTX
2455	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2456	*/
2457	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
2458
2459	/** @def IEM_CTX_ASSERT
2460	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
2461	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2462	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
2463	*/
2464	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) \
2465	AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
2466	("fExtrn=%#RX64 & fExtrnMbz=%#RX64 -> %#RX64\n", \
2467	(a_pVCpu)->cpum.GstCtx.fExtrn, (a_fExtrnMbz), (a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz) ))
2468
2469	/** @def IEM_CTX_IMPORT_RET
2470	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2471	*
2472	* Will call the keep to import the bits as needed.
2473	*
2474	* Returns on import failure.
2475	*
2476	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2477	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2478	*/
2479	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
2480	do { \
2481	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2482	{ /* likely */ } \
2483	else \
2484	{ \
2485	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2486	AssertRCReturn(rcCtxImport, rcCtxImport); \
2487	} \
2488	} while (0)
2489
2490	/** @def IEM_CTX_IMPORT_NORET
2491	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2492	*
2493	* Will call the keep to import the bits as needed.
2494	*
2495	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2496	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2497	*/
2498	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
2499	do { \
2500	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2501	{ /* likely */ } \
2502	else \
2503	{ \
2504	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2505	AssertLogRelRC(rcCtxImport); \
2506	} \
2507	} while (0)
2508
2509	/** @def IEM_CTX_IMPORT_JMP
2510	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2511	*
2512	* Will call the keep to import the bits as needed.
2513	*
2514	* Jumps on import failure.
2515	*
2516	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2517	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2518	*/
2519	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
2520	do { \
2521	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2522	{ /* likely */ } \
2523	else \
2524	{ \
2525	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2526	AssertRCStmt(rcCtxImport, IEM_DO_LONGJMP(pVCpu, rcCtxImport)); \
2527	} \
2528	} while (0)
2529
2530
2531
2532	/** @def IEM_GET_TARGET_CPU
2533	* Gets the current IEMTARGETCPU value.
2534	* @returns IEMTARGETCPU value.
2535	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2536	*/
2537	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
2538	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
2539	#else
2540	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
2541	#endif
2542
2543	/** @def IEM_GET_INSTR_LEN
2544	* Gets the instruction length. */
2545	#ifdef IEM_WITH_CODE_TLB
2546	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
2547	#else
2548	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
2549	#endif
2550
2551	/** @def IEM_TRY_SETJMP
2552	* Wrapper around setjmp / try, hiding all the ugly differences.
2553	*
2554	* @note Use with extreme care as this is a fragile macro.
2555	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2556	* @param a_rcTarget The variable that should receive the status code in case
2557	* of a longjmp/throw.
2558	*/
2559	/** @def IEM_TRY_SETJMP_AGAIN
2560	* For when setjmp / try is used again in the same variable scope as a previous
2561	* IEM_TRY_SETJMP invocation.
2562	*/
2563	/** @def IEM_CATCH_LONGJMP_BEGIN
2564	* Start wrapper for catch / setjmp-else.
2565	*
2566	* This will set up a scope.
2567	*
2568	* @note Use with extreme care as this is a fragile macro.
2569	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2570	* @param a_rcTarget The variable that should receive the status code in case
2571	* of a longjmp/throw.
2572	*/
2573	/** @def IEM_CATCH_LONGJMP_END
2574	* End wrapper for catch / setjmp-else.
2575	*
2576	* This will close the scope set up by IEM_CATCH_LONGJMP_BEGIN and clean up the
2577	* state.
2578	*
2579	* @note Use with extreme care as this is a fragile macro.
2580	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2581	*/
2582	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
2583	# ifdef IEM_WITH_THROW_CATCH
2584	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
2585	a_rcTarget = VINF_SUCCESS; \
2586	try
2587	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
2588	IEM_TRY_SETJMP(a_pVCpu, a_rcTarget)
2589	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
2590	catch (int rcThrown) \
2591	{ \
2592	a_rcTarget = rcThrown
2593	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
2594	} \
2595	((void)0)
2596	# else /* !IEM_WITH_THROW_CATCH */
2597	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
2598	jmp_buf JmpBuf; \
2599	jmp_buf * volatile pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
2600	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
2601	if ((rcStrict = setjmp(JmpBuf)) == 0)
2602	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
2603	pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
2604	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
2605	if ((rcStrict = setjmp(JmpBuf)) == 0)
2606	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
2607	else \
2608	{ \
2609	((void)0)
2610	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
2611	} \
2612	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = pSavedJmpBuf
2613	# endif /* !IEM_WITH_THROW_CATCH */
2614	#endif /* IEM_WITH_SETJMP */
2615
2616
2617	/**
2618	* Shared per-VM IEM data.
2619	*/
2620	typedef struct IEM
2621	{
2622	/** The VMX APIC-access page handler type. */
2623	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
2624	#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
2625	/** Set if the CPUID host call functionality is enabled. */
2626	bool fCpuIdHostCall;
2627	#endif
2628	} IEM;
2629
2630
2631
2632	/** @name IEM_ACCESS_XXX - Access details.
2633	* @{ */
2634	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
2635	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
2636	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
2637	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
2638	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
2639	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
2640	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
2641	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
2642	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
2643	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
2644	/** The writes are partial, so if initialize the bounce buffer with the
2645	* orignal RAM content. */
2646	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
2647	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
2648	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
2649	/** Bounce buffer with ring-3 write pending, first page. */
2650	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
2651	/** Bounce buffer with ring-3 write pending, second page. */
2652	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
2653	/** Not locked, accessed via the TLB. */
2654	#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
2655	/** Atomic access.
2656	* This enables special alignment checks and the VINF_EM_EMULATE_SPLIT_LOCK
2657	* fallback for misaligned stuff. See @bugref{10547}. */
2658	#define IEM_ACCESS_ATOMIC UINT32_C(0x00002000)
2659	/** Valid bit mask. */
2660	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00003fff)
2661	/** Shift count for the TLB flags (upper word). */
2662	#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
2663
2664	/** Atomic read+write data alias. */
2665	#define IEM_ACCESS_DATA_ATOMIC (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA \| IEM_ACCESS_ATOMIC)
2666	/** Read+write data alias. */
2667	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
2668	/** Write data alias. */
2669	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
2670	/** Read data alias. */
2671	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
2672	/** Instruction fetch alias. */
2673	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
2674	/** Stack write alias. */
2675	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
2676	/** Stack read alias. */
2677	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
2678	/** Stack read+write alias. */
2679	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
2680	/** Read system table alias. */
2681	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
2682	/** Read+write system table alias. */
2683	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
2684	/** @} */
2685
2686	/** @name Prefix constants (IEMCPU::fPrefixes)
2687	* @{ */
2688	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
2689	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
2690	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
2691	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
2692	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
2693	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
2694	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
2695
2696	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
2697	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
2698	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
2699
2700	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
2701	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
2702	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
2703
2704	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
2705	#define IEM_OP_PRF_REX_B RT_BIT_32(25) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
2706	#define IEM_OP_PRF_REX_X RT_BIT_32(26) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
2707	#define IEM_OP_PRF_REX_R RT_BIT_32(27) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
2708	/** Mask with all the REX prefix flags.
2709	* This is generally for use when needing to undo the REX prefixes when they
2710	* are followed legacy prefixes and therefore does not immediately preceed
2711	* the first opcode byte.
2712	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
2713	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
2714
2715	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
2716	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
2717	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
2718	/** @} */
2719
2720	/** @name IEMOPFORM_XXX - Opcode forms
2721	* @note These are ORed together with IEMOPHINT_XXX.
2722	* @{ */
2723	/** ModR/M: reg, r/m */
2724	#define IEMOPFORM_RM 0
2725	/** ModR/M: reg, r/m (register) */
2726	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
2727	/** ModR/M: reg, r/m (memory) */
2728	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
2729	/** ModR/M: reg, r/m, imm */
2730	#define IEMOPFORM_RMI 1
2731	/** ModR/M: reg, r/m (register), imm */
2732	#define IEMOPFORM_RMI_REG (IEMOPFORM_RMI \| IEMOPFORM_MOD3)
2733	/** ModR/M: reg, r/m (memory), imm */
2734	#define IEMOPFORM_RMI_MEM (IEMOPFORM_RMI \| IEMOPFORM_NOT_MOD3)
2735	/** ModR/M: reg, r/m, xmm0 */
2736	#define IEMOPFORM_RM0 2
2737	/** ModR/M: reg, r/m (register), xmm0 */
2738	#define IEMOPFORM_RM0_REG (IEMOPFORM_RM0 \| IEMOPFORM_MOD3)
2739	/** ModR/M: reg, r/m (memory), xmm0 */
2740	#define IEMOPFORM_RM0_MEM (IEMOPFORM_RM0 \| IEMOPFORM_NOT_MOD3)
2741	/** ModR/M: r/m, reg */
2742	#define IEMOPFORM_MR 3
2743	/** ModR/M: r/m (register), reg */
2744	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
2745	/** ModR/M: r/m (memory), reg */
2746	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
2747	/** ModR/M: r/m, reg, imm */
2748	#define IEMOPFORM_MRI 4
2749	/** ModR/M: r/m (register), reg, imm */
2750	#define IEMOPFORM_MRI_REG (IEMOPFORM_MRI \| IEMOPFORM_MOD3)
2751	/** ModR/M: r/m (memory), reg, imm */
2752	#define IEMOPFORM_MRI_MEM (IEMOPFORM_MRI \| IEMOPFORM_NOT_MOD3)
2753	/** ModR/M: r/m only */
2754	#define IEMOPFORM_M 5
2755	/** ModR/M: r/m only (register). */
2756	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
2757	/** ModR/M: r/m only (memory). */
2758	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
2759	/** ModR/M: r/m, imm */
2760	#define IEMOPFORM_MI 6
2761	/** ModR/M: r/m (register), imm */
2762	#define IEMOPFORM_MI_REG (IEMOPFORM_MI \| IEMOPFORM_MOD3)
2763	/** ModR/M: r/m (memory), imm */
2764	#define IEMOPFORM_MI_MEM (IEMOPFORM_MI \| IEMOPFORM_NOT_MOD3)
2765	/** ModR/M: r/m, 1 (shift and rotate instructions) */
2766	#define IEMOPFORM_M1 7
2767	/** ModR/M: r/m (register), 1. */
2768	#define IEMOPFORM_M1_REG (IEMOPFORM_M1 \| IEMOPFORM_MOD3)
2769	/** ModR/M: r/m (memory), 1. */
2770	#define IEMOPFORM_M1_MEM (IEMOPFORM_M1 \| IEMOPFORM_NOT_MOD3)
2771	/** ModR/M: r/m, CL (shift and rotate instructions)
2772	* @todo This should just've been a generic fixed register. But the python
2773	* code doesn't needs more convincing. */
2774	#define IEMOPFORM_M_CL 8
2775	/** ModR/M: r/m (register), CL. */
2776	#define IEMOPFORM_M_CL_REG (IEMOPFORM_M_CL \| IEMOPFORM_MOD3)
2777	/** ModR/M: r/m (memory), CL. */
2778	#define IEMOPFORM_M_CL_MEM (IEMOPFORM_M_CL \| IEMOPFORM_NOT_MOD3)
2779	/** ModR/M: reg only */
2780	#define IEMOPFORM_R 9
2781
2782	/** VEX+ModR/M: reg, r/m */
2783	#define IEMOPFORM_VEX_RM 16
2784	/** VEX+ModR/M: reg, r/m (register) */
2785	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
2786	/** VEX+ModR/M: reg, r/m (memory) */
2787	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
2788	/** VEX+ModR/M: r/m, reg */
2789	#define IEMOPFORM_VEX_MR 17
2790	/** VEX+ModR/M: r/m (register), reg */
2791	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
2792	/** VEX+ModR/M: r/m (memory), reg */
2793	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
2794	/** VEX+ModR/M: r/m, reg, imm8 */
2795	#define IEMOPFORM_VEX_MRI 18
2796	/** VEX+ModR/M: r/m (register), reg, imm8 */
2797	#define IEMOPFORM_VEX_MRI_REG (IEMOPFORM_VEX_MRI \| IEMOPFORM_MOD3)
2798	/** VEX+ModR/M: r/m (memory), reg, imm8 */
2799	#define IEMOPFORM_VEX_MRI_MEM (IEMOPFORM_VEX_MRI \| IEMOPFORM_NOT_MOD3)
2800	/** VEX+ModR/M: r/m only */
2801	#define IEMOPFORM_VEX_M 19
2802	/** VEX+ModR/M: r/m only (register). */
2803	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
2804	/** VEX+ModR/M: r/m only (memory). */
2805	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
2806	/** VEX+ModR/M: reg only */
2807	#define IEMOPFORM_VEX_R 20
2808	/** VEX+ModR/M: reg, vvvv, r/m */
2809	#define IEMOPFORM_VEX_RVM 21
2810	/** VEX+ModR/M: reg, vvvv, r/m (register). */
2811	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
2812	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
2813	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
2814	/** VEX+ModR/M: reg, vvvv, r/m, imm */
2815	#define IEMOPFORM_VEX_RVMI 22
2816	/** VEX+ModR/M: reg, vvvv, r/m (register), imm. */
2817	#define IEMOPFORM_VEX_RVMI_REG (IEMOPFORM_VEX_RVMI \| IEMOPFORM_MOD3)
2818	/** VEX+ModR/M: reg, vvvv, r/m (memory), imm. */
2819	#define IEMOPFORM_VEX_RVMI_MEM (IEMOPFORM_VEX_RVMI \| IEMOPFORM_NOT_MOD3)
2820	/** VEX+ModR/M: reg, vvvv, r/m, imm(reg) */
2821	#define IEMOPFORM_VEX_RVMR 23
2822	/** VEX+ModR/M: reg, vvvv, r/m (register), imm(reg). */
2823	#define IEMOPFORM_VEX_RVMR_REG (IEMOPFORM_VEX_RVMI \| IEMOPFORM_MOD3)
2824	/** VEX+ModR/M: reg, vvvv, r/m (memory), imm(reg). */
2825	#define IEMOPFORM_VEX_RVMR_MEM (IEMOPFORM_VEX_RVMI \| IEMOPFORM_NOT_MOD3)
2826	/** VEX+ModR/M: reg, r/m, vvvv */
2827	#define IEMOPFORM_VEX_RMV 24
2828	/** VEX+ModR/M: reg, r/m, vvvv (register). */
2829	#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV \| IEMOPFORM_MOD3)
2830	/** VEX+ModR/M: reg, r/m, vvvv (memory). */
2831	#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV \| IEMOPFORM_NOT_MOD3)
2832	/** VEX+ModR/M: reg, r/m, imm8 */
2833	#define IEMOPFORM_VEX_RMI 25
2834	/** VEX+ModR/M: reg, r/m, imm8 (register). */
2835	#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI \| IEMOPFORM_MOD3)
2836	/** VEX+ModR/M: reg, r/m, imm8 (memory). */
2837	#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI \| IEMOPFORM_NOT_MOD3)
2838	/** VEX+ModR/M: r/m, vvvv, reg */
2839	#define IEMOPFORM_VEX_MVR 26
2840	/** VEX+ModR/M: r/m, vvvv, reg (register) */
2841	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
2842	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
2843	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
2844	/** VEX+ModR/M+/n: vvvv, r/m */
2845	#define IEMOPFORM_VEX_VM 27
2846	/** VEX+ModR/M+/n: vvvv, r/m (register) */
2847	#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM \| IEMOPFORM_MOD3)
2848	/** VEX+ModR/M+/n: vvvv, r/m (memory) */
2849	#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM \| IEMOPFORM_NOT_MOD3)
2850	/** VEX+ModR/M+/n: vvvv, r/m, imm8 */
2851	#define IEMOPFORM_VEX_VMI 28
2852	/** VEX+ModR/M+/n: vvvv, r/m, imm8 (register) */
2853	#define IEMOPFORM_VEX_VMI_REG (IEMOPFORM_VEX_VMI \| IEMOPFORM_MOD3)
2854	/** VEX+ModR/M+/n: vvvv, r/m, imm8 (memory) */
2855	#define IEMOPFORM_VEX_VMI_MEM (IEMOPFORM_VEX_VMI \| IEMOPFORM_NOT_MOD3)
2856
2857	/** Fixed register instruction, no R/M. */
2858	#define IEMOPFORM_FIXED 32
2859
2860	/** The r/m is a register. */
2861	#define IEMOPFORM_MOD3 RT_BIT_32(8)
2862	/** The r/m is a memory access. */
2863	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
2864	/** @} */
2865
2866	/** @name IEMOPHINT_XXX - Additional Opcode Hints
2867	* @note These are ORed together with IEMOPFORM_XXX.
2868	* @{ */
2869	/** Ignores the operand size prefix (66h). */
2870	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
2871	/** Ignores REX.W (aka WIG). */
2872	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
2873	/** Both the operand size prefixes (66h + REX.W) are ignored. */
2874	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
2875	/** Allowed with the lock prefix. */
2876	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
2877	/** The VEX.L value is ignored (aka LIG). */
2878	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
2879	/** The VEX.L value must be zero (i.e. 128-bit width only). */
2880	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
2881	/** The VEX.L value must be one (i.e. 256-bit width only). */
2882	#define IEMOPHINT_VEX_L_ONE RT_BIT_32(14)
2883	/** The VEX.V value must be zero. */
2884	#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(15)
2885	/** The REX.W/VEX.V value must be zero. */
2886	#define IEMOPHINT_REX_W_ZERO RT_BIT_32(16)
2887	#define IEMOPHINT_VEX_W_ZERO IEMOPHINT_REX_W_ZERO
2888	/** The REX.W/VEX.V value must be one. */
2889	#define IEMOPHINT_REX_W_ONE RT_BIT_32(17)
2890	#define IEMOPHINT_VEX_W_ONE IEMOPHINT_REX_W_ONE
2891
2892	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
2893	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
2894	/** @} */
2895
2896	/**
2897	* Possible hardware task switch sources.
2898	*/
2899	typedef enum IEMTASKSWITCH
2900	{
2901	/** Task switch caused by an interrupt/exception. */
2902	IEMTASKSWITCH_INT_XCPT = 1,
2903	/** Task switch caused by a far CALL. */
2904	IEMTASKSWITCH_CALL,
2905	/** Task switch caused by a far JMP. */
2906	IEMTASKSWITCH_JUMP,
2907	/** Task switch caused by an IRET. */
2908	IEMTASKSWITCH_IRET
2909	} IEMTASKSWITCH;
2910	AssertCompileSize(IEMTASKSWITCH, 4);
2911
2912	/**
2913	* Possible CrX load (write) sources.
2914	*/
2915	typedef enum IEMACCESSCRX
2916	{
2917	/** CrX access caused by 'mov crX' instruction. */
2918	IEMACCESSCRX_MOV_CRX,
2919	/** CrX (CR0) write caused by 'lmsw' instruction. */
2920	IEMACCESSCRX_LMSW,
2921	/** CrX (CR0) write caused by 'clts' instruction. */
2922	IEMACCESSCRX_CLTS,
2923	/** CrX (CR0) read caused by 'smsw' instruction. */
2924	IEMACCESSCRX_SMSW
2925	} IEMACCESSCRX;
2926
2927	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2928	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
2929	*
2930	* These flags provide further context to SLAT page-walk failures that could not be
2931	* determined by PGM (e.g, PGM is not privy to memory access permissions).
2932	*
2933	* @{
2934	*/
2935	/** Translating a nested-guest linear address failed accessing a nested-guest
2936	* physical address. */
2937	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
2938	/** Translating a nested-guest linear address failed accessing a
2939	* paging-structure entry or updating accessed/dirty bits. */
2940	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
2941	/** @} */
2942
2943	DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
2944	# ifndef IN_RING3
2945	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
2946	# endif
2947	#endif
2948
2949	/**
2950	* Indicates to the verifier that the given flag set is undefined.
2951	*
2952	* Can be invoked again to add more flags.
2953	*
2954	* This is a NOOP if the verifier isn't compiled in.
2955	*
2956	* @note We're temporarily keeping this until code is converted to new
2957	* disassembler style opcode handling.
2958	*/
2959	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
2960
2961
2962	/** @def IEM_DECL_IMPL_TYPE
2963	* For typedef'ing an instruction implementation function.
2964	*
2965	* @param a_RetType The return type.
2966	* @param a_Name The name of the type.
2967	* @param a_ArgList The argument list enclosed in parentheses.
2968	*/
2969
2970	/** @def IEM_DECL_IMPL_DEF
2971	* For defining an instruction implementation function.
2972	*
2973	* @param a_RetType The return type.
2974	* @param a_Name The name of the type.
2975	* @param a_ArgList The argument list enclosed in parentheses.
2976	*/
2977
2978	#if defined(__GNUC__) && defined(RT_ARCH_X86)
2979	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2980	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
2981	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2982	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
2983	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2984	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
2985
2986	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
2987	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2988	a_RetType (__fastcall a_Name) a_ArgList
2989	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2990	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
2991	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2992	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
2993
2994	#elif __cplusplus >= 201700 /* P0012R1 support */
2995	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2996	a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
2997	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2998	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
2999	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
3000	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
3001
3002	#else
3003	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
3004	a_RetType (VBOXCALL a_Name) a_ArgList
3005	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
3006	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
3007	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
3008	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
3009
3010	#endif
3011
3012	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
3013	RT_C_DECLS_BEGIN
3014	extern uint8_t const g_afParity[256];
3015	RT_C_DECLS_END
3016
3017
3018	/** @name Arithmetic assignment operations on bytes (binary).
3019	* @{ */
3020	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU8, (uint32_t fEFlagsIn, uint8_t *pu8Dst, uint8_t u8Src));
3021	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
3022	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
3023	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
3024	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
3025	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
3026	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
3027	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
3028	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
3029	/** @} */
3030
3031	/** @name Arithmetic assignment operations on words (binary).
3032	* @{ */
3033	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU16, (uint32_t fEFlagsIn, uint16_t *pu16Dst, uint16_t u16Src));
3034	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
3035	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
3036	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
3037	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
3038	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
3039	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
3040	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
3041	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
3042	/** @} */
3043
3044
3045	/** @name Arithmetic assignment operations on double words (binary).
3046	* @{ */
3047	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU32, (uint32_t fEFlagsIn, uint32_t *pu32Dst, uint32_t u32Src));
3048	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
3049	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
3050	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
3051	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
3052	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
3053	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
3054	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
3055	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
3056	FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
3057	FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
3058	FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
3059	/** @} */
3060
3061	/** @name Arithmetic assignment operations on quad words (binary).
3062	* @{ */
3063	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU64, (uint32_t fEFlagsIn, uint64_t *pu64Dst, uint64_t u64Src));
3064	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
3065	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
3066	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
3067	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
3068	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
3069	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
3070	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
3071	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
3072	FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
3073	FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
3074	FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
3075	/** @} */
3076
3077	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU8, (uint32_t fEFlagsIn, uint8_t const *pu8Dst, uint8_t u8Src));
3078	typedef FNIEMAIMPLBINROU8 *PFNIEMAIMPLBINROU8;
3079	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU16,(uint32_t fEFlagsIn, uint16_t const *pu16Dst, uint16_t u16Src));
3080	typedef FNIEMAIMPLBINROU16 *PFNIEMAIMPLBINROU16;
3081	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU32,(uint32_t fEFlagsIn, uint32_t const *pu32Dst, uint32_t u32Src));
3082	typedef FNIEMAIMPLBINROU32 *PFNIEMAIMPLBINROU32;
3083	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU64,(uint32_t fEFlagsIn, uint64_t const *pu64Dst, uint64_t u64Src));
3084	typedef FNIEMAIMPLBINROU64 *PFNIEMAIMPLBINROU64;
3085
3086	/** @name Compare operations (thrown in with the binary ops).
3087	* @{ */
3088	FNIEMAIMPLBINROU8 iemAImpl_cmp_u8;
3089	FNIEMAIMPLBINROU16 iemAImpl_cmp_u16;
3090	FNIEMAIMPLBINROU32 iemAImpl_cmp_u32;
3091	FNIEMAIMPLBINROU64 iemAImpl_cmp_u64;
3092	/** @} */
3093
3094	/** @name Test operations (thrown in with the binary ops).
3095	* @{ */
3096	FNIEMAIMPLBINROU8 iemAImpl_test_u8;
3097	FNIEMAIMPLBINROU16 iemAImpl_test_u16;
3098	FNIEMAIMPLBINROU32 iemAImpl_test_u32;
3099	FNIEMAIMPLBINROU64 iemAImpl_test_u64;
3100	/** @} */
3101
3102	/** @name Bit operations operations (thrown in with the binary ops).
3103	* @{ */
3104	FNIEMAIMPLBINROU16 iemAImpl_bt_u16;
3105	FNIEMAIMPLBINROU32 iemAImpl_bt_u32;
3106	FNIEMAIMPLBINROU64 iemAImpl_bt_u64;
3107	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
3108	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
3109	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
3110	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
3111	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
3112	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
3113	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
3114	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
3115	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
3116	/** @} */
3117
3118	/** @name Arithmetic three operand operations on double words (binary).
3119	* @{ */
3120	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t pEFlags));
3121	typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
3122	FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
3123	FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
3124	FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
3125	/** @} */
3126
3127	/** @name Arithmetic three operand operations on quad words (binary).
3128	* @{ */
3129	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t pEFlags));
3130	typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
3131	FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
3132	FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
3133	FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
3134	/** @} */
3135
3136	/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
3137	* @{ */
3138	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
3139	typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
3140	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
3141	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
3142	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
3143	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
3144	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
3145	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
3146	/** @} */
3147
3148	/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
3149	* @{ */
3150	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
3151	typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
3152	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
3153	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
3154	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
3155	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
3156	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
3157	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
3158	/** @} */
3159
3160	/** @name MULX 32-bit and 64-bit.
3161	* @{ */
3162	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t puDst1, uint32_t puDst2, uint32_t uSrc1, uint32_t uSrc2));
3163	typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
3164	FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
3165
3166	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t puDst1, uint64_t puDst2, uint64_t uSrc1, uint64_t uSrc2));
3167	typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
3168	FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
3169	/** @} */
3170
3171
3172	/** @name Exchange memory with register operations.
3173	* @{ */
3174	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
3175	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
3176	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
3177	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
3178	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
3179	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
3180	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
3181	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
3182	/** @} */
3183
3184	/** @name Exchange and add operations.
3185	* @{ */
3186	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
3187	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
3188	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
3189	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
3190	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
3191	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
3192	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
3193	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
3194	/** @} */
3195
3196	/** @name Compare and exchange.
3197	* @{ */
3198	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
3199	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
3200	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
3201	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
3202	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
3203	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
3204	#if ARCH_BITS == 32
3205	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
3206	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
3207	#else
3208	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
3209	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
3210	#endif
3211	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
3212	uint32_t *pEFlags));
3213	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
3214	uint32_t *pEFlags));
3215	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
3216	uint32_t *pEFlags));
3217	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
3218	uint32_t *pEFlags));
3219	#ifndef RT_ARCH_ARM64
3220	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
3221	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
3222	#endif
3223	/** @} */
3224
3225	/** @name Memory ordering
3226	* @{ */
3227	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
3228	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
3229	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
3230	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
3231	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
3232	#ifndef RT_ARCH_ARM64
3233	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
3234	#endif
3235	/** @} */
3236
3237	/** @name Double precision shifts
3238	* @{ */
3239	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
3240	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
3241	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
3242	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
3243	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
3244	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
3245	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
3246	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
3247	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
3248	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
3249	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
3250	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
3251	/** @} */
3252
3253
3254	/** @name Bit search operations (thrown in with the binary ops).
3255	* @{ */
3256	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
3257	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
3258	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
3259	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
3260	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
3261	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
3262	FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
3263	FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
3264	FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
3265	FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
3266	FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
3267	FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
3268	FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
3269	FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
3270	FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
3271	/** @} */
3272
3273	/** @name Signed multiplication operations (thrown in with the binary ops).
3274	* @{ */
3275	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
3276	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
3277	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
3278	/** @} */
3279
3280	/** @name Arithmetic assignment operations on bytes (unary).
3281	* @{ */
3282	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
3283	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
3284	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
3285	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
3286	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
3287	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
3288	/** @} */
3289
3290	/** @name Arithmetic assignment operations on words (unary).
3291	* @{ */
3292	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
3293	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
3294	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
3295	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
3296	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
3297	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
3298	/** @} */
3299
3300	/** @name Arithmetic assignment operations on double words (unary).
3301	* @{ */
3302	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
3303	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
3304	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
3305	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
3306	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
3307	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
3308	/** @} */
3309
3310	/** @name Arithmetic assignment operations on quad words (unary).
3311	* @{ */
3312	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
3313	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
3314	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
3315	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
3316	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
3317	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
3318	/** @} */
3319
3320
3321	/** @name Shift operations on bytes (Group 2).
3322	* @{ */
3323	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU8,(uint32_t fEFlagsIn, uint8_t *pu8Dst, uint8_t cShift));
3324	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
3325	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
3326	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
3327	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
3328	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
3329	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
3330	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
3331	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
3332	/** @} */
3333
3334	/** @name Shift operations on words (Group 2).
3335	* @{ */
3336	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU16,(uint32_t fEFlagsIn, uint16_t *pu16Dst, uint8_t cShift));
3337	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
3338	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
3339	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
3340	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
3341	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
3342	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
3343	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
3344	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
3345	/** @} */
3346
3347	/** @name Shift operations on double words (Group 2).
3348	* @{ */
3349	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU32,(uint32_t fEFlagsIn, uint32_t *pu32Dst, uint8_t cShift));
3350	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
3351	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
3352	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
3353	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
3354	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
3355	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
3356	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
3357	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
3358	/** @} */
3359
3360	/** @name Shift operations on words (Group 2).
3361	* @{ */
3362	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU64,(uint32_t fEFlagsIn, uint64_t *pu64Dst, uint8_t cShift));
3363	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
3364	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
3365	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
3366	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
3367	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
3368	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
3369	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
3370	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
3371	/** @} */
3372
3373	/** @name Multiplication and division operations.
3374	* @{ */
3375	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
3376	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
3377	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
3378	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
3379	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
3380	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
3381
3382	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
3383	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
3384	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
3385	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
3386	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
3387	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
3388
3389	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
3390	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
3391	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
3392	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
3393	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
3394	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
3395
3396	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
3397	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
3398	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
3399	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
3400	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
3401	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
3402	/** @} */
3403
3404	/** @name Byte Swap.
3405	* @{ */
3406	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
3407	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
3408	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
3409	/** @} */
3410
3411	/** @name Misc.
3412	* @{ */
3413	FNIEMAIMPLBINU16 iemAImpl_arpl;
3414	/** @} */
3415
3416	/** @name RDRAND and RDSEED
3417	* @{ */
3418	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU16,(uint16_t puDst, uint32_t pEFlags));
3419	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU32,(uint32_t puDst, uint32_t pEFlags));
3420	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU64,(uint64_t puDst, uint32_t pEFlags));
3421	typedef FNIEMAIMPLRDRANDSEEDU16 *PFNIEMAIMPLRDRANDSEEDU16;
3422	typedef FNIEMAIMPLRDRANDSEEDU32 *PFNIEMAIMPLRDRANDSEEDU32;
3423	typedef FNIEMAIMPLRDRANDSEEDU64 *PFNIEMAIMPLRDRANDSEEDU64;
3424
3425	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdrand_u16, iemAImpl_rdrand_u16_fallback;
3426	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdrand_u32, iemAImpl_rdrand_u32_fallback;
3427	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdrand_u64, iemAImpl_rdrand_u64_fallback;
3428	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdseed_u16, iemAImpl_rdseed_u16_fallback;
3429	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdseed_u32, iemAImpl_rdseed_u32_fallback;
3430	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdseed_u64, iemAImpl_rdseed_u64_fallback;
3431	/** @} */
3432
3433	/** @name ADOX and ADCX
3434	* @{ */
3435	FNIEMAIMPLBINU32 iemAImpl_adcx_u32, iemAImpl_adcx_u32_fallback;
3436	FNIEMAIMPLBINU64 iemAImpl_adcx_u64, iemAImpl_adcx_u64_fallback;
3437	FNIEMAIMPLBINU32 iemAImpl_adox_u32, iemAImpl_adox_u32_fallback;
3438	FNIEMAIMPLBINU64 iemAImpl_adox_u64, iemAImpl_adox_u64_fallback;
3439	/** @} */
3440
3441	/** @name FPU operations taking a 32-bit float argument
3442	* @{ */
3443	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3444	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
3445	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
3446
3447	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3448	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
3449	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
3450
3451	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
3452	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
3453	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
3454	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
3455	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
3456	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
3457	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
3458
3459	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
3460	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3461	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
3462	/** @} */
3463
3464	/** @name FPU operations taking a 64-bit float argument
3465	* @{ */
3466	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3467	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
3468	typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
3469
3470	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3471	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
3472	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
3473
3474	FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
3475	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
3476	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
3477	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
3478	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
3479	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
3480	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
3481
3482	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
3483	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3484	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
3485	/** @} */
3486
3487	/** @name FPU operations taking a 80-bit float argument
3488	* @{ */
3489	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3490	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3491	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
3492	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
3493	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
3494	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
3495	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
3496	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
3497	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
3498	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
3499	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
3500	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
3501
3502	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
3503	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
3504	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
3505
3506	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3507	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3508	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
3509	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
3510	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
3511
3512	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
3513	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3514	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
3515	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
3516	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
3517
3518	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
3519	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
3520	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
3521	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
3522	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
3523	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
3524	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
3525	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
3526	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
3527
3528	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
3529	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
3530	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
3531	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
3532
3533	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
3534	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
3535	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
3536	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
3537	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
3538	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
3539	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
3540	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
3541	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
3542
3543	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
3544	PCRTFLOAT80U pr80Val));
3545	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
3546	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
3547	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
3548	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
3549
3550	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
3551	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3552	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
3553
3554	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
3555	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3556	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
3557
3558	/** @} */
3559
3560	/** @name FPU operations taking a 16-bit signed integer argument
3561	* @{ */
3562	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3563	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
3564	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
3565	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3566	int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
3567	typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
3568
3569	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
3570	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
3571	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
3572	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
3573	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
3574	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
3575
3576	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3577	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
3578	typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
3579	FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
3580
3581	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
3582	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
3583	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
3584	/** @} */
3585
3586	/** @name FPU operations taking a 32-bit signed integer argument
3587	* @{ */
3588	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3589	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
3590	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
3591	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3592	int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
3593	typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
3594
3595	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
3596	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
3597	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
3598	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
3599	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
3600	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
3601
3602	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3603	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
3604	typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
3605	FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
3606
3607	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
3608	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
3609	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
3610	/** @} */
3611
3612	/** @name FPU operations taking a 64-bit signed integer argument
3613	* @{ */
3614	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3615	int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
3616	typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
3617
3618	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
3619	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
3620	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
3621	/** @} */
3622
3623
3624	/** Temporary type representing a 256-bit vector register. */
3625	typedef struct { uint64_t au64[4]; } IEMVMM256;
3626	/** Temporary type pointing to a 256-bit vector register. */
3627	typedef IEMVMM256 *PIEMVMM256;
3628	/** Temporary type pointing to a const 256-bit vector register. */
3629	typedef IEMVMM256 *PCIEMVMM256;
3630
3631
3632	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
3633	* @{ */
3634	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t puDst, uint64_t const puSrc));
3635	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
3636	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF2U128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
3637	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
3638	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF2U256,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86YMMREG puSrc));
3639	typedef FNIEMAIMPLMEDIAF2U256 *PFNIEMAIMPLMEDIAF2U256;
3640	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF3U128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3641	typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
3642	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF3U256,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
3643	typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
3644	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t puDst, uint64_t const puSrc));
3645	typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
3646	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
3647	typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
3648	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
3649	typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
3650	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
3651	typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
3652	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256,(PRTUINT256U puDst, PCRTUINT256U puSrc));
3653	typedef FNIEMAIMPLMEDIAOPTF2U256 *PFNIEMAIMPLMEDIAOPTF2U256;
3654	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
3655	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
3656	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
3657	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
3658	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddb_u64, iemAImpl_paddsb_u64, iemAImpl_paddusb_u64;
3659	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddw_u64, iemAImpl_paddsw_u64, iemAImpl_paddusw_u64;
3660	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddd_u64;
3661	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddq_u64;
3662	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubb_u64, iemAImpl_psubsb_u64, iemAImpl_psubusb_u64;
3663	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubw_u64, iemAImpl_psubsw_u64, iemAImpl_psubusw_u64;
3664	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubd_u64;
3665	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubq_u64;
3666	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmaddwd_u64, iemAImpl_pmaddwd_u64_fallback;
3667	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmullw_u64, iemAImpl_pmulhw_u64;
3668	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pminub_u64, iemAImpl_pmaxub_u64;
3669	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pminsw_u64, iemAImpl_pmaxsw_u64;
3670	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsb_u64, iemAImpl_pabsb_u64_fallback;
3671	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsw_u64, iemAImpl_pabsw_u64_fallback;
3672	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsd_u64, iemAImpl_pabsd_u64_fallback;
3673	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignb_u64, iemAImpl_psignb_u64_fallback;
3674	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignw_u64, iemAImpl_psignw_u64_fallback;
3675	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignd_u64, iemAImpl_psignd_u64_fallback;
3676	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddw_u64, iemAImpl_phaddw_u64_fallback;
3677	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddd_u64, iemAImpl_phaddd_u64_fallback;
3678	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubw_u64, iemAImpl_phsubw_u64_fallback;
3679	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubd_u64, iemAImpl_phsubd_u64_fallback;
3680	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddsw_u64, iemAImpl_phaddsw_u64_fallback;
3681	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubsw_u64, iemAImpl_phsubsw_u64_fallback;
3682	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmaddubsw_u64, iemAImpl_pmaddubsw_u64_fallback;
3683	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhrsw_u64, iemAImpl_pmulhrsw_u64_fallback;
3684	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmuludq_u64;
3685	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllw_u64, iemAImpl_psrlw_u64, iemAImpl_psraw_u64;
3686	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pslld_u64, iemAImpl_psrld_u64, iemAImpl_psrad_u64;
3687	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllq_u64, iemAImpl_psrlq_u64;
3688	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packsswb_u64, iemAImpl_packuswb_u64;
3689	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packssdw_u64;
3690	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhuw_u64;
3691	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pavgb_u64, iemAImpl_pavgw_u64;
3692	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psadbw_u64;
3693
3694	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
3695	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
3696	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
3697	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
3698	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
3699	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
3700	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddb_u128, iemAImpl_paddsb_u128, iemAImpl_paddusb_u128;
3701	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddw_u128, iemAImpl_paddsw_u128, iemAImpl_paddusw_u128;
3702	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddd_u128;
3703	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddq_u128;
3704	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubb_u128, iemAImpl_psubsb_u128, iemAImpl_psubusb_u128;
3705	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubw_u128, iemAImpl_psubsw_u128, iemAImpl_psubusw_u128;
3706	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubd_u128;
3707	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubq_u128;
3708	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmullw_u128, iemAImpl_pmullw_u128_fallback;
3709	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhw_u128;
3710	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback;
3711	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddwd_u128, iemAImpl_pmaddwd_u128_fallback;
3712	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminub_u128;
3713	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback;
3714	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback;
3715	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback;
3716	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback;
3717	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsw_u128, iemAImpl_pminsw_u128_fallback;
3718	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxub_u128;
3719	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback;
3720	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback;
3721	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback;
3722	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsw_u128;
3723	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback;
3724	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback;
3725	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback;
3726	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback;
3727	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback;
3728	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback;
3729	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback;
3730	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback;
3731	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback;
3732	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback;
3733	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback;
3734	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback;
3735	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback;
3736	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback;
3737	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback;
3738	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuludq_u128;
3739	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddwd_u128, iemAImpl_pmaddwd_u128_fallback;
3740	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packsswb_u128, iemAImpl_packuswb_u128;
3741	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packssdw_u128, iemAImpl_packusdw_u128;
3742	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllw_u128, iemAImpl_psrlw_u128, iemAImpl_psraw_u128;
3743	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pslld_u128, iemAImpl_psrld_u128, iemAImpl_psrad_u128;
3744	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllq_u128, iemAImpl_psrlq_u128;
3745	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhuw_u128;
3746	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pavgb_u128, iemAImpl_pavgw_u128;
3747	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psadbw_u128;
3748	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback;
3749	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpcklps_u128, iemAImpl_unpcklpd_u128;
3750	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpckhps_u128, iemAImpl_unpckhpd_u128;
3751	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback;
3752
3753	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
3754	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
3755	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
3756	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
3757	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
3758	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
3759	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
3760	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
3761	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
3762	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
3763	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
3764	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
3765	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
3766	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
3767	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
3768	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
3769	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
3770	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
3771	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
3772	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
3773	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
3774	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminub_u128, iemAImpl_vpminub_u128_fallback;
3775	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminuw_u128, iemAImpl_vpminuw_u128_fallback;
3776	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminud_u128, iemAImpl_vpminud_u128_fallback;
3777	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsb_u128, iemAImpl_vpminsb_u128_fallback;
3778	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsw_u128, iemAImpl_vpminsw_u128_fallback;
3779	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsd_u128, iemAImpl_vpminsd_u128_fallback;
3780	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxub_u128, iemAImpl_vpmaxub_u128_fallback;
3781	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxuw_u128, iemAImpl_vpmaxuw_u128_fallback;
3782	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxud_u128, iemAImpl_vpmaxud_u128_fallback;
3783	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsb_u128, iemAImpl_vpmaxsb_u128_fallback;
3784	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsw_u128, iemAImpl_vpmaxsw_u128_fallback;
3785	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsd_u128, iemAImpl_vpmaxsd_u128_fallback;
3786	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpacksswb_u128, iemAImpl_vpacksswb_u128_fallback;
3787	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackssdw_u128, iemAImpl_vpackssdw_u128_fallback;
3788	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackuswb_u128, iemAImpl_vpackuswb_u128_fallback;
3789	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackusdw_u128, iemAImpl_vpackusdw_u128_fallback;
3790	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmullw_u128, iemAImpl_vpmullw_u128_fallback;
3791	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulld_u128, iemAImpl_vpmulld_u128_fallback;
3792	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhw_u128, iemAImpl_vpmulhw_u128_fallback;
3793	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhuw_u128, iemAImpl_vpmulhuw_u128_fallback;
3794	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgb_u128, iemAImpl_vpavgb_u128_fallback;
3795	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgw_u128, iemAImpl_vpavgw_u128_fallback;
3796	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignb_u128, iemAImpl_vpsignb_u128_fallback;
3797	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignw_u128, iemAImpl_vpsignw_u128_fallback;
3798	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignd_u128, iemAImpl_vpsignd_u128_fallback;
3799	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddw_u128, iemAImpl_vphaddw_u128_fallback;
3800	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddd_u128, iemAImpl_vphaddd_u128_fallback;
3801	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubw_u128, iemAImpl_vphsubw_u128_fallback;
3802	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubd_u128, iemAImpl_vphsubd_u128_fallback;
3803	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddsw_u128, iemAImpl_vphaddsw_u128_fallback;
3804	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubsw_u128, iemAImpl_vphsubsw_u128_fallback;
3805	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddubsw_u128, iemAImpl_vpmaddubsw_u128_fallback;
3806	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhrsw_u128, iemAImpl_vpmulhrsw_u128_fallback;
3807	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsadbw_u128, iemAImpl_vpsadbw_u128_fallback;
3808	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuldq_u128, iemAImpl_vpmuldq_u128_fallback;
3809	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuludq_u128, iemAImpl_vpmuludq_u128_fallback;
3810	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsb_u128, iemAImpl_vpsubsb_u128_fallback;
3811	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsw_u128, iemAImpl_vpsubsw_u128_fallback;
3812	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusb_u128, iemAImpl_vpsubusb_u128_fallback;
3813	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusw_u128, iemAImpl_vpsubusw_u128_fallback;
3814	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusb_u128, iemAImpl_vpaddusb_u128_fallback;
3815	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusw_u128, iemAImpl_vpaddusw_u128_fallback;
3816	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsb_u128, iemAImpl_vpaddsb_u128_fallback;
3817	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsw_u128, iemAImpl_vpaddsw_u128_fallback;
3818	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllw_u128, iemAImpl_vpsllw_u128_fallback;
3819	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpslld_u128, iemAImpl_vpslld_u128_fallback;
3820	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllq_u128, iemAImpl_vpsllq_u128_fallback;
3821	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsraw_u128, iemAImpl_vpsraw_u128_fallback;
3822	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrad_u128, iemAImpl_vpsrad_u128_fallback;
3823	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlw_u128, iemAImpl_vpsrlw_u128_fallback;
3824	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrld_u128, iemAImpl_vpsrld_u128_fallback;
3825	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlq_u128, iemAImpl_vpsrlq_u128_fallback;
3826	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddwd_u128, iemAImpl_vpmaddwd_u128_fallback;
3827
3828	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback;
3829	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsw_u128, iemAImpl_vpabsd_u128_fallback;
3830	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsd_u128, iemAImpl_vpabsw_u128_fallback;
3831	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback;
3832
3833	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
3834	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
3835	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
3836	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
3837	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
3838	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
3839	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
3840	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
3841	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
3842	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
3843	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
3844	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
3845	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
3846	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
3847	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
3848	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
3849	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
3850	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
3851	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
3852	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
3853	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
3854	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminub_u256, iemAImpl_vpminub_u256_fallback;
3855	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminuw_u256, iemAImpl_vpminuw_u256_fallback;
3856	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminud_u256, iemAImpl_vpminud_u256_fallback;
3857	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsb_u256, iemAImpl_vpminsb_u256_fallback;
3858	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsw_u256, iemAImpl_vpminsw_u256_fallback;
3859	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsd_u256, iemAImpl_vpminsd_u256_fallback;
3860	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxub_u256, iemAImpl_vpmaxub_u256_fallback;
3861	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxuw_u256, iemAImpl_vpmaxuw_u256_fallback;
3862	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxud_u256, iemAImpl_vpmaxud_u256_fallback;
3863	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsb_u256, iemAImpl_vpmaxsb_u256_fallback;
3864	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsw_u256, iemAImpl_vpmaxsw_u256_fallback;
3865	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsd_u256, iemAImpl_vpmaxsd_u256_fallback;
3866	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpacksswb_u256, iemAImpl_vpacksswb_u256_fallback;
3867	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackssdw_u256, iemAImpl_vpackssdw_u256_fallback;
3868	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackuswb_u256, iemAImpl_vpackuswb_u256_fallback;
3869	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackusdw_u256, iemAImpl_vpackusdw_u256_fallback;
3870	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmullw_u256, iemAImpl_vpmullw_u256_fallback;
3871	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulld_u256, iemAImpl_vpmulld_u256_fallback;
3872	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhw_u256, iemAImpl_vpmulhw_u256_fallback;
3873	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhuw_u256, iemAImpl_vpmulhuw_u256_fallback;
3874	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgb_u256, iemAImpl_vpavgb_u256_fallback;
3875	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgw_u256, iemAImpl_vpavgw_u256_fallback;
3876	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignb_u256, iemAImpl_vpsignb_u256_fallback;
3877	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignw_u256, iemAImpl_vpsignw_u256_fallback;
3878	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignd_u256, iemAImpl_vpsignd_u256_fallback;
3879	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddw_u256, iemAImpl_vphaddw_u256_fallback;
3880	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddd_u256, iemAImpl_vphaddd_u256_fallback;
3881	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubw_u256, iemAImpl_vphsubw_u256_fallback;
3882	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubd_u256, iemAImpl_vphsubd_u256_fallback;
3883	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddsw_u256, iemAImpl_vphaddsw_u256_fallback;
3884	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubsw_u256, iemAImpl_vphsubsw_u256_fallback;
3885	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddubsw_u256, iemAImpl_vpmaddubsw_u256_fallback;
3886	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhrsw_u256, iemAImpl_vpmulhrsw_u256_fallback;
3887	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsadbw_u256, iemAImpl_vpsadbw_u256_fallback;
3888	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuldq_u256, iemAImpl_vpmuldq_u256_fallback;
3889	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuludq_u256, iemAImpl_vpmuludq_u256_fallback;
3890	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsb_u256, iemAImpl_vpsubsb_u256_fallback;
3891	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsw_u256, iemAImpl_vpsubsw_u256_fallback;
3892	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusb_u256, iemAImpl_vpsubusb_u256_fallback;
3893	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusw_u256, iemAImpl_vpsubusw_u256_fallback;
3894	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusb_u256, iemAImpl_vpaddusb_u256_fallback;
3895	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusw_u256, iemAImpl_vpaddusw_u256_fallback;
3896	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsb_u256, iemAImpl_vpaddsb_u256_fallback;
3897	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsw_u256, iemAImpl_vpaddsw_u256_fallback;
3898	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllw_u256, iemAImpl_vpsllw_u256_fallback;
3899	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpslld_u256, iemAImpl_vpslld_u256_fallback;
3900	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllq_u256, iemAImpl_vpsllq_u256_fallback;
3901	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsraw_u256, iemAImpl_vpsraw_u256_fallback;
3902	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrad_u256, iemAImpl_vpsrad_u256_fallback;
3903	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlw_u256, iemAImpl_vpsrlw_u256_fallback;
3904	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrld_u256, iemAImpl_vpsrld_u256_fallback;
3905	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlq_u256, iemAImpl_vpsrlq_u256_fallback;
3906	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddwd_u256, iemAImpl_vpmaddwd_u256_fallback;
3907	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermps_u256, iemAImpl_vpermps_u256_fallback;
3908	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermd_u256, iemAImpl_vpermd_u256_fallback;
3909
3910	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback;
3911	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsw_u256, iemAImpl_vpabsw_u256_fallback;
3912	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsd_u256, iemAImpl_vpabsd_u256_fallback;
3913	/** @} */
3914
3915	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
3916	* @{ */
3917	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
3918	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
3919	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
3920	iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
3921	iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
3922	iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback,
3923	iemAImpl_vunpcklps_u128, iemAImpl_vunpcklps_u128_fallback,
3924	iemAImpl_vunpcklpd_u128, iemAImpl_vunpcklpd_u128_fallback,
3925	iemAImpl_vunpckhps_u128, iemAImpl_vunpckhps_u128_fallback,
3926	iemAImpl_vunpckhpd_u128, iemAImpl_vunpckhpd_u128_fallback;
3927
3928	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
3929	iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
3930	iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
3931	iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback,
3932	iemAImpl_vunpcklps_u256, iemAImpl_vunpcklps_u256_fallback,
3933	iemAImpl_vunpcklpd_u256, iemAImpl_vunpcklpd_u256_fallback,
3934	iemAImpl_vunpckhps_u256, iemAImpl_vunpckhps_u256_fallback,
3935	iemAImpl_vunpckhpd_u256, iemAImpl_vunpckhpd_u256_fallback;
3936	/** @} */
3937
3938	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
3939	* @{ */
3940	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
3941	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
3942	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
3943	iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
3944	iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
3945	iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
3946	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
3947	iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
3948	iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
3949	iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
3950	/** @} */
3951
3952	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
3953	* @{ */
3954	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3955	typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
3956	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
3957	typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
3958	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t puDst, uint64_t const puSrc, uint8_t bEvil));
3959	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
3960	#ifndef IEM_WITHOUT_ASSEMBLY
3961	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
3962	#endif
3963	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
3964	/** @} */
3965
3966	/** @name Media (SSE/MMX/AVX) operation: Shift Immediate Stuff (evil)
3967	* @{ */
3968	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU64,(uint64_t *puDst, uint8_t bShift));
3969	typedef FNIEMAIMPLMEDIAPSHIFTU64 *PFNIEMAIMPLMEDIAPSHIFTU64;
3970	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU128,(PRTUINT128U puDst, uint8_t bShift));
3971	typedef FNIEMAIMPLMEDIAPSHIFTU128 *PFNIEMAIMPLMEDIAPSHIFTU128;
3972	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU256,(PRTUINT256U puDst, uint8_t bShift));
3973	typedef FNIEMAIMPLMEDIAPSHIFTU256 *PFNIEMAIMPLMEDIAPSHIFTU256;
3974	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psllw_imm_u64, iemAImpl_pslld_imm_u64, iemAImpl_psllq_imm_u64;
3975	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psrlw_imm_u64, iemAImpl_psrld_imm_u64, iemAImpl_psrlq_imm_u64;
3976	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psraw_imm_u64, iemAImpl_psrad_imm_u64;
3977	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psllw_imm_u128, iemAImpl_pslld_imm_u128, iemAImpl_psllq_imm_u128;
3978	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psrlw_imm_u128, iemAImpl_psrld_imm_u128, iemAImpl_psrlq_imm_u128;
3979	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psraw_imm_u128, iemAImpl_psrad_imm_u128;
3980	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_pslldq_imm_u128, iemAImpl_psrldq_imm_u128;
3981	/** @} */
3982
3983	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
3984	* @{ */
3985	IEM_DECL_IMPL_DEF(void, iemAImpl_maskmovq_u64,(uint64_t puMem, uint64_t const puSrc, uint64_t const *puMsk));
3986	IEM_DECL_IMPL_DEF(void, iemAImpl_maskmovdqu_u128,(PRTUINT128U puMem, PCRTUINT128U puSrc, PCRTUINT128U puMsk));
3987	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t pu64Dst, uint64_t const puSrc));
3988	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
3989	#ifndef IEM_WITHOUT_ASSEMBLY
3990	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
3991	#endif
3992	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
3993	/** @} */
3994
3995	/** @name Media (SSE/MMX/AVX) operations: Variable Blend Packed Bytes/R32/R64.
3996	* @{ */
3997	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puMask));
3998	typedef FNIEMAIMPLBLENDU128 *PFNIEMAIMPLBLENDU128;
3999	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, PCRTUINT128U puMask));
4000	typedef FNIEMAIMPLAVXBLENDU128 *PFNIEMAIMPLAVXBLENDU128;
4001	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, PCRTUINT256U puMask));
4002	typedef FNIEMAIMPLAVXBLENDU256 *PFNIEMAIMPLAVXBLENDU256;
4003
4004	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128;
4005	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128_fallback;
4006	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128;
4007	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128_fallback;
4008	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256;
4009	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256_fallback;
4010
4011	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128;
4012	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128_fallback;
4013	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128;
4014	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128_fallback;
4015	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256;
4016	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256_fallback;
4017
4018	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128;
4019	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128_fallback;
4020	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128;
4021	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128_fallback;
4022	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256;
4023	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256_fallback;
4024	/** @} */
4025
4026
4027	/** @name Media (SSE/MMX/AVX) operation: Sort this later
4028	* @{ */
4029	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
4030	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
4031	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4032	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4033	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4034
4035	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
4036	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
4037	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
4038	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4039	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4040
4041	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
4042	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
4043	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
4044	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4045	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4046
4047	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
4048	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
4049	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4050	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4051	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4052
4053	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
4054	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
4055	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
4056	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4057	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4058
4059	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
4060	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
4061	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4062	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4063	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4064
4065	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
4066	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
4067	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4068	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4069	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4070
4071	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
4072	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
4073	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
4074	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4075	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4076
4077	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
4078	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
4079	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
4080	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4081	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4082
4083	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
4084	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
4085	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4086	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4087	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4088
4089	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
4090	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
4091	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
4092	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4093	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4094
4095	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
4096	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
4097	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4098	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4099	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4100
4101	IEM_DECL_IMPL_DEF(void, iemAImpl_shufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
4102	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
4103	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
4104	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
4105	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
4106
4107	IEM_DECL_IMPL_DEF(void, iemAImpl_shufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
4108	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
4109	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
4110	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
4111	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
4112
4113	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
4114	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64_fallback,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
4115
4116	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4117	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4118	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4119	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
4120	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
4121
4122	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4123	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4124	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4125	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
4126	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
4127
4128
4129	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
4130	typedef FNIEMAIMPLMEDIAOPTF2U128IMM8 *PFNIEMAIMPLMEDIAOPTF2U128IMM8;
4131	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
4132	typedef FNIEMAIMPLMEDIAOPTF2U256IMM8 *PFNIEMAIMPLMEDIAOPTF2U256IMM8;
4133	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
4134	typedef FNIEMAIMPLMEDIAOPTF3U128IMM8 *PFNIEMAIMPLMEDIAOPTF3U128IMM8;
4135	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
4136	typedef FNIEMAIMPLMEDIAOPTF3U256IMM8 *PFNIEMAIMPLMEDIAOPTF3U256IMM8;
4137
4138	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback;
4139	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback;
4140	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback;
4141	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback;
4142
4143	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpalignr_u128, iemAImpl_vpalignr_u128_fallback;
4144	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendw_u128, iemAImpl_vpblendw_u128_fallback;
4145	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendd_u128, iemAImpl_vpblendd_u128_fallback;
4146	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendps_u128, iemAImpl_vblendps_u128_fallback;
4147	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendpd_u128, iemAImpl_vblendpd_u128_fallback;
4148
4149	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpalignr_u256, iemAImpl_vpalignr_u256_fallback;
4150	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendw_u256, iemAImpl_vpblendw_u256_fallback;
4151	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendd_u256, iemAImpl_vpblendd_u256_fallback;
4152	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendps_u256, iemAImpl_vblendps_u256_fallback;
4153	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendpd_u256, iemAImpl_vblendpd_u256_fallback;
4154	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2i128_u256, iemAImpl_vperm2i128_u256_fallback;
4155	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2f128_u256, iemAImpl_vperm2f128_u256_fallback;
4156
4157	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesimc_u128, iemAImpl_aesimc_u128_fallback;
4158	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenc_u128, iemAImpl_aesenc_u128_fallback;
4159	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenclast_u128, iemAImpl_aesenclast_u128_fallback;
4160	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdec_u128, iemAImpl_aesdec_u128_fallback;
4161	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdeclast_u128, iemAImpl_aesdeclast_u128_fallback;
4162
4163	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesimc_u128, iemAImpl_vaesimc_u128_fallback;
4164	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vaesenc_u128, iemAImpl_vaesenc_u128_fallback;
4165	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vaesenclast_u128, iemAImpl_vaesenclast_u128_fallback;
4166	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vaesdec_u128, iemAImpl_vaesdec_u128_fallback;
4167	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vaesdeclast_u128, iemAImpl_vaesdeclast_u128_fallback;
4168
4169	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback;
4170
4171	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vaeskeygenassist_u128, iemAImpl_vaeskeygenassist_u128_fallback;
4172
4173	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1nexte_u128, iemAImpl_sha1nexte_u128_fallback;
4174	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg1_u128, iemAImpl_sha1msg1_u128_fallback;
4175	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg2_u128, iemAImpl_sha1msg2_u128_fallback;
4176	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg1_u128, iemAImpl_sha256msg1_u128_fallback;
4177	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg2_u128, iemAImpl_sha256msg2_u128_fallback;
4178	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_sha1rnds4_u128, iemAImpl_sha1rnds4_u128_fallback;
4179	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
4180	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
4181
4182	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermq_u256, iemAImpl_vpermq_u256_fallback;
4183	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermpd_u256, iemAImpl_vpermpd_u256_fallback;
4184
4185	typedef struct IEMPCMPISTRXSRC
4186	{
4187	RTUINT128U uSrc1;
4188	RTUINT128U uSrc2;
4189	} IEMPCMPISTRXSRC;
4190	typedef IEMPCMPISTRXSRC *PIEMPCMPISTRXSRC;
4191	typedef const IEMPCMPISTRXSRC *PCIEMPCMPISTRXSRC;
4192
4193	typedef struct IEMPCMPESTRXSRC
4194	{
4195	RTUINT128U uSrc1;
4196	RTUINT128U uSrc2;
4197	uint64_t u64Rax;
4198	uint64_t u64Rdx;
4199	} IEMPCMPESTRXSRC;
4200	typedef IEMPCMPESTRXSRC *PIEMPCMPESTRXSRC;
4201	typedef const IEMPCMPESTRXSRC *PCIEMPCMPESTRXSRC;
4202
4203	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLPCMPISTRIU128IMM8,(uint32_t *pEFlags, PCRTUINT128U pSrc1, PCRTUINT128U pSrc2, uint8_t bEvil));
4204	typedef FNIEMAIMPLPCMPISTRIU128IMM8 *PFNIEMAIMPLPCMPISTRIU128IMM8;
4205	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
4206	typedef FNIEMAIMPLPCMPESTRIU128IMM8 *PFNIEMAIMPLPCMPESTRIU128IMM8;
4207
4208	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
4209	typedef FNIEMAIMPLPCMPISTRMU128IMM8 *PFNIEMAIMPLPCMPISTRMU128IMM8;
4210	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
4211	typedef FNIEMAIMPLPCMPESTRMU128IMM8 *PFNIEMAIMPLPCMPESTRMU128IMM8;
4212
4213	FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_pcmpistri_u128, iemAImpl_pcmpistri_u128_fallback;
4214	FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_pcmpestri_u128, iemAImpl_pcmpestri_u128_fallback;
4215	FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_pcmpistrm_u128, iemAImpl_pcmpistrm_u128_fallback;
4216	FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_pcmpestrm_u128, iemAImpl_pcmpestrm_u128_fallback;
4217	FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_vpcmpistri_u128, iemAImpl_vpcmpistri_u128_fallback;
4218	FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_vpcmpestri_u128, iemAImpl_vpcmpestri_u128_fallback;
4219	FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_vpcmpistrm_u128, iemAImpl_vpcmpistrm_u128_fallback;
4220	FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_vpcmpestrm_u128, iemAImpl_vpcmpestrm_u128_fallback;
4221
4222
4223	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pclmulqdq_u128, iemAImpl_pclmulqdq_u128_fallback;
4224	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback;
4225
4226	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_mpsadbw_u128, iemAImpl_mpsadbw_u128_fallback;
4227	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vmpsadbw_u128, iemAImpl_vmpsadbw_u128_fallback;
4228	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vmpsadbw_u256, iemAImpl_vmpsadbw_u256_fallback;
4229
4230	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsllw_imm_u128, iemAImpl_vpsllw_imm_u128_fallback;
4231	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsllw_imm_u256, iemAImpl_vpsllw_imm_u256_fallback;
4232	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpslld_imm_u128, iemAImpl_vpslld_imm_u128_fallback;
4233	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpslld_imm_u256, iemAImpl_vpslld_imm_u256_fallback;
4234	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsllq_imm_u128, iemAImpl_vpsllq_imm_u128_fallback;
4235	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsllq_imm_u256, iemAImpl_vpsllq_imm_u256_fallback;
4236	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4237	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4238	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4239	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4240
4241	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsraw_imm_u128, iemAImpl_vpsraw_imm_u128_fallback;
4242	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsraw_imm_u256, iemAImpl_vpsraw_imm_u256_fallback;
4243	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrad_imm_u128, iemAImpl_vpsrad_imm_u128_fallback;
4244	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrad_imm_u256, iemAImpl_vpsrad_imm_u256_fallback;
4245
4246	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrlw_imm_u128, iemAImpl_vpsrlw_imm_u128_fallback;
4247	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrlw_imm_u256, iemAImpl_vpsrlw_imm_u256_fallback;
4248	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrld_imm_u128, iemAImpl_vpsrld_imm_u128_fallback;
4249	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrld_imm_u256, iemAImpl_vpsrld_imm_u256_fallback;
4250	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrlq_imm_u128, iemAImpl_vpsrlq_imm_u128_fallback;
4251	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrlq_imm_u256, iemAImpl_vpsrlq_imm_u256_fallback;
4252	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4253	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4254	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4255	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4256
4257	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpermilps_u128, iemAImpl_vpermilps_u128_fallback;
4258	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vpermilps_imm_u128, iemAImpl_vpermilps_imm_u128_fallback;
4259	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermilps_u256, iemAImpl_vpermilps_u256_fallback;
4260	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermilps_imm_u256, iemAImpl_vpermilps_imm_u256_fallback;
4261
4262	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpermilpd_u128, iemAImpl_vpermilpd_u128_fallback;
4263	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vpermilpd_imm_u128, iemAImpl_vpermilpd_imm_u128_fallback;
4264	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermilpd_u256, iemAImpl_vpermilpd_u256_fallback;
4265	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermilpd_imm_u256, iemAImpl_vpermilpd_imm_u256_fallback;
4266
4267	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllvd_u128, iemAImpl_vpsllvd_u128_fallback;
4268	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllvd_u256, iemAImpl_vpsllvd_u256_fallback;
4269	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllvq_u128, iemAImpl_vpsllvq_u128_fallback;
4270	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllvq_u256, iemAImpl_vpsllvq_u256_fallback;
4271	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsravd_u128, iemAImpl_vpsravd_u128_fallback;
4272	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsravd_u256, iemAImpl_vpsravd_u256_fallback;
4273	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlvd_u128, iemAImpl_vpsrlvd_u128_fallback;
4274	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlvd_u256, iemAImpl_vpsrlvd_u256_fallback;
4275	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlvq_u128, iemAImpl_vpsrlvq_u128_fallback;
4276	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlvq_u256, iemAImpl_vpsrlvq_u256_fallback;
4277	/** @} */
4278
4279	/** @name Media Odds and Ends
4280	* @{ */
4281	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
4282	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
4283	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
4284	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
4285	FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
4286	FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
4287	FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
4288	FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
4289
4290	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
4291	typedef FNIEMAIMPLF2EFL128 *PFNIEMAIMPLF2EFL128;
4292	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
4293	typedef FNIEMAIMPLF2EFL256 *PFNIEMAIMPLF2EFL256;
4294	FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
4295	FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
4296	FNIEMAIMPLF2EFL128 iemAImpl_vtestps_u128, iemAImpl_vtestps_u128_fallback;
4297	FNIEMAIMPLF2EFL256 iemAImpl_vtestps_u256, iemAImpl_vtestps_u256_fallback;
4298	FNIEMAIMPLF2EFL128 iemAImpl_vtestpd_u128, iemAImpl_vtestpd_u128_fallback;
4299	FNIEMAIMPLF2EFL256 iemAImpl_vtestpd_u256, iemAImpl_vtestpd_u256_fallback;
4300
4301	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32U64,(uint32_t uMxCsrIn, int32_t pi32Dst, const uint64_t pu64Src)); /* pu64Src is a double precision floating point. */
4302	typedef FNIEMAIMPLSSEF2I32U64 *PFNIEMAIMPLSSEF2I32U64;
4303	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64U64,(uint32_t uMxCsrIn, int64_t pi64Dst, const uint64_t pu64Src)); /* pu64Src is a double precision floating point. */
4304	typedef FNIEMAIMPLSSEF2I64U64 *PFNIEMAIMPLSSEF2I64U64;
4305	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32U32,(uint32_t uMxCsrIn, int32_t pi32Dst, const uint32_t pu32Src)); /* pu32Src is a single precision floating point. */
4306	typedef FNIEMAIMPLSSEF2I32U32 *PFNIEMAIMPLSSEF2I32U32;
4307	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64U32,(uint32_t uMxCsrIn, int64_t pi64Dst, const uint32_t pu32Src)); /* pu32Src is a single precision floating point. */
4308	typedef FNIEMAIMPLSSEF2I64U32 *PFNIEMAIMPLSSEF2I64U32;
4309	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32R32,(uint32_t uMxCsrIn, int32_t *pi32Dst, PCRTFLOAT32U pr32Src));
4310	typedef FNIEMAIMPLSSEF2I32R32 *PFNIEMAIMPLSSEF2I32R32;
4311	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64R32,(uint32_t uMxCsrIn, int64_t *pi64Dst, PCRTFLOAT32U pr32Src));
4312	typedef FNIEMAIMPLSSEF2I64R32 *PFNIEMAIMPLSSEF2I64R32;
4313	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32R64,(uint32_t uMxCsrIn, int32_t *pi32Dst, PCRTFLOAT64U pr64Src));
4314	typedef FNIEMAIMPLSSEF2I32R64 *PFNIEMAIMPLSSEF2I32R64;
4315	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64R64,(uint32_t uMxCsrIn, int64_t *pi64Dst, PCRTFLOAT64U pr64Src));
4316	typedef FNIEMAIMPLSSEF2I64R64 *PFNIEMAIMPLSSEF2I64R64;
4317
4318	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvttsd2si_i32_r64;
4319	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvtsd2si_i32_r64;
4320
4321	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvttsd2si_i64_r64;
4322	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvtsd2si_i64_r64;
4323
4324	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvttss2si_i32_r32;
4325	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvtss2si_i32_r32;
4326
4327	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvttss2si_i64_r32;
4328	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvtss2si_i64_r32;
4329
4330	FNIEMAIMPLSSEF2I32R32 iemAImpl_vcvttss2si_i32_r32, iemAImpl_vcvttss2si_i32_r32_fallback;
4331	FNIEMAIMPLSSEF2I64R32 iemAImpl_vcvttss2si_i64_r32, iemAImpl_vcvttss2si_i64_r32_fallback;
4332	FNIEMAIMPLSSEF2I32R32 iemAImpl_vcvtss2si_i32_r32, iemAImpl_vcvtss2si_i32_r32_fallback;
4333	FNIEMAIMPLSSEF2I64R32 iemAImpl_vcvtss2si_i64_r32, iemAImpl_vcvtss2si_i64_r32_fallback;
4334
4335	FNIEMAIMPLSSEF2I32R64 iemAImpl_vcvttss2si_i32_r64, iemAImpl_vcvttss2si_i32_r64_fallback;
4336	FNIEMAIMPLSSEF2I64R64 iemAImpl_vcvttss2si_i64_r64, iemAImpl_vcvttss2si_i64_r64_fallback;
4337	FNIEMAIMPLSSEF2I32R64 iemAImpl_vcvtss2si_i32_r64, iemAImpl_vcvtss2si_i32_r64_fallback;
4338	FNIEMAIMPLSSEF2I64R64 iemAImpl_vcvtss2si_i64_r64, iemAImpl_vcvtss2si_i64_r64_fallback;
4339
4340	FNIEMAIMPLSSEF2I32R32 iemAImpl_vcvttsd2si_i32_r32, iemAImpl_vcvttsd2si_i32_r32_fallback;
4341	FNIEMAIMPLSSEF2I64R32 iemAImpl_vcvttsd2si_i64_r32, iemAImpl_vcvttsd2si_i64_r32_fallback;
4342	FNIEMAIMPLSSEF2I32R32 iemAImpl_vcvtsd2si_i32_r32, iemAImpl_vcvtsd2si_i32_r32_fallback;
4343	FNIEMAIMPLSSEF2I64R32 iemAImpl_vcvtsd2si_i64_r32, iemAImpl_vcvtsd2si_i64_r32_fallback;
4344
4345	FNIEMAIMPLSSEF2I32R64 iemAImpl_vcvttsd2si_i32_r64, iemAImpl_vcvttsd2si_i32_r64_fallback;
4346	FNIEMAIMPLSSEF2I64R64 iemAImpl_vcvttsd2si_i64_r64, iemAImpl_vcvttsd2si_i64_r64_fallback;
4347	FNIEMAIMPLSSEF2I32R64 iemAImpl_vcvtsd2si_i32_r64, iemAImpl_vcvtsd2si_i32_r64_fallback;
4348	FNIEMAIMPLSSEF2I64R64 iemAImpl_vcvtsd2si_i64_r64, iemAImpl_vcvtsd2si_i64_r64_fallback;
4349
4350	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R32I32,(uint32_t uMxCsrIn, PRTFLOAT32U pr32Dst, const int32_t *pi32Src));
4351	typedef FNIEMAIMPLSSEF2R32I32 *PFNIEMAIMPLSSEF2R32I32;
4352	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R32I64,(uint32_t uMxCsrIn, PRTFLOAT32U pr32Dst, const int64_t *pi64Src));
4353	typedef FNIEMAIMPLSSEF2R32I64 *PFNIEMAIMPLSSEF2R32I64;
4354
4355	FNIEMAIMPLSSEF2R32I32 iemAImpl_cvtsi2ss_r32_i32;
4356	FNIEMAIMPLSSEF2R32I64 iemAImpl_cvtsi2ss_r32_i64;
4357
4358	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLAVXF3XMMI32,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc, const int32_t *pi32Src));
4359	typedef FNIEMAIMPLAVXF3XMMI32 *PFNIEMAIMPLAVXF3XMMI32;
4360	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLAVXF3XMMI64,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc, const int64_t *pi64Src));
4361	typedef FNIEMAIMPLAVXF3XMMI64 *PFNIEMAIMPLAVXF3XMMI64;
4362
4363	FNIEMAIMPLAVXF3XMMI32 iemAImpl_vcvtsi2ss_u128_i32, iemAImpl_vcvtsi2ss_u128_i32_fallback;
4364	FNIEMAIMPLAVXF3XMMI64 iemAImpl_vcvtsi2ss_u128_i64, iemAImpl_vcvtsi2ss_u128_i64_fallback;
4365
4366
4367	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R64I32,(uint32_t uMxCsrIn, PRTFLOAT64U pr64Dst, const int32_t *pi32Src));
4368	typedef FNIEMAIMPLSSEF2R64I32 *PFNIEMAIMPLSSEF2R64I32;
4369	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R64I64,(uint32_t uMxCsrIn, PRTFLOAT64U pr64Dst, const int64_t *pi64Src));
4370	typedef FNIEMAIMPLSSEF2R64I64 *PFNIEMAIMPLSSEF2R64I64;
4371
4372	FNIEMAIMPLSSEF2R64I32 iemAImpl_cvtsi2sd_r64_i32;
4373	FNIEMAIMPLSSEF2R64I64 iemAImpl_cvtsi2sd_r64_i64;
4374
4375	FNIEMAIMPLAVXF3XMMI32 iemAImpl_vcvtsi2sd_u128_i32, iemAImpl_vcvtsi2sd_u128_i32_fallback;
4376	FNIEMAIMPLAVXF3XMMI64 iemAImpl_vcvtsi2sd_u128_i64, iemAImpl_vcvtsi2sd_u128_i64_fallback;
4377
4378	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtps2pd_u128_u64,(uint32_t uMxCsrIn, PX86XMMREG puDst, const uint64_t pu64Src)); / Actually two single precision floating point values. */
4379	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtps2pd_u128_u64_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, const uint64_t pu64Src)); / Actually two single precision floating point values. */
4380	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtps2pd_u256_u128,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86XMMREG puSrc));
4381	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtps2pd_u256_u128_fallback,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86XMMREG puSrc));
4382
4383
4384	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtdq2pd_u128_u64,(uint32_t uMxCsrIn, PX86XMMREG puDst, const uint64_t pu64Src)); / Actually two single precision floating point values. */
4385	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtdq2pd_u128_u64_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, const uint64_t pu64Src)); / Actually two single precision floating point values. */
4386	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtdq2pd_u256_u128,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86XMMREG puSrc));
4387	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtdq2pd_u256_u128_fallback,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86XMMREG puSrc));
4388
4389
4390	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLF2EFLMXCSRR32R32,(uint32_t uMxCsrIn, uint32_t *pfEFlags, RTFLOAT32U uSrc1, RTFLOAT32U uSrc2));
4391	typedef FNIEMAIMPLF2EFLMXCSRR32R32 *PFNIEMAIMPLF2EFLMXCSRR32R32;
4392
4393	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLF2EFLMXCSRR64R64,(uint32_t uMxCsrIn, uint32_t *pfEFlags, RTFLOAT64U uSrc1, RTFLOAT64U uSrc2));
4394	typedef FNIEMAIMPLF2EFLMXCSRR64R64 *PFNIEMAIMPLF2EFLMXCSRR64R64;
4395
4396	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_ucomiss_u128;
4397	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback;
4398
4399	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_ucomisd_u128;
4400	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback;
4401
4402	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_comiss_u128;
4403	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback;
4404
4405	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_comisd_u128;
4406	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback;
4407
4408
4409	typedef struct IEMMEDIAF2XMMSRC
4410	{
4411	X86XMMREG uSrc1;
4412	X86XMMREG uSrc2;
4413	} IEMMEDIAF2XMMSRC;
4414	typedef IEMMEDIAF2XMMSRC *PIEMMEDIAF2XMMSRC;
4415	typedef const IEMMEDIAF2XMMSRC *PCIEMMEDIAF2XMMSRC;
4416
4417
4418	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF3XMMIMM8,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC puSrc, uint8_t bEvil));
4419	typedef FNIEMAIMPLMEDIAF3XMMIMM8 *PFNIEMAIMPLMEDIAF3XMMIMM8;
4420
4421
4422	typedef struct IEMMEDIAF2YMMSRC
4423	{
4424	X86YMMREG uSrc1;
4425	X86YMMREG uSrc2;
4426	} IEMMEDIAF2YMMSRC;
4427	typedef IEMMEDIAF2YMMSRC *PIEMMEDIAF2YMMSRC;
4428	typedef const IEMMEDIAF2YMMSRC *PCIEMMEDIAF2YMMSRC;
4429
4430
4431	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF3YMMIMM8,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCIEMMEDIAF2YMMSRC puSrc, uint8_t bEvil));
4432	typedef FNIEMAIMPLMEDIAF3YMMIMM8 *PFNIEMAIMPLMEDIAF3YMMIMM8;
4433
4434
4435	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_cmpps_u128;
4436	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_cmppd_u128;
4437	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_cmpss_u128;
4438	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_cmpsd_u128;
4439
4440	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vcmpps_u128, iemAImpl_vcmpps_u128_fallback;
4441	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vcmppd_u128, iemAImpl_vcmppd_u128_fallback;
4442	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vcmpss_u128, iemAImpl_vcmpss_u128_fallback;
4443	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vcmpsd_u128, iemAImpl_vcmpsd_u128_fallback;
4444
4445	FNIEMAIMPLMEDIAF3YMMIMM8 iemAImpl_vcmpps_u256, iemAImpl_vcmpps_u256_fallback;
4446	FNIEMAIMPLMEDIAF3YMMIMM8 iemAImpl_vcmppd_u256, iemAImpl_vcmppd_u256_fallback;
4447
4448	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_roundss_u128;
4449	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_roundsd_u128;
4450
4451	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_dpps_u128, iemAImpl_dpps_u128_fallback;
4452	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_dppd_u128, iemAImpl_dppd_u128_fallback;
4453
4454
4455	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF2U128IMM8,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc, uint8_t bEvil));
4456	typedef FNIEMAIMPLMEDIAF2U128IMM8 *PFNIEMAIMPLMEDIAF2U128IMM8;
4457
4458
4459	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF2U256IMM8,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86YMMREG puSrc, uint8_t bEvil));
4460	typedef FNIEMAIMPLMEDIAF2U256IMM8 *PFNIEMAIMPLMEDIAF2U256IMM8;
4461
4462
4463	FNIEMAIMPLMEDIAF2U128IMM8 iemAImpl_roundps_u128, iemAImpl_roundps_u128_fallback;
4464	FNIEMAIMPLMEDIAF2U128IMM8 iemAImpl_roundpd_u128, iemAImpl_roundpd_u128_fallback;
4465
4466	FNIEMAIMPLMEDIAF2U128IMM8 iemAImpl_vroundps_u128, iemAImpl_vroundps_u128_fallback;
4467	FNIEMAIMPLMEDIAF2U128IMM8 iemAImpl_vroundpd_u128, iemAImpl_vroundpd_u128_fallback;
4468
4469	FNIEMAIMPLMEDIAF2U256IMM8 iemAImpl_vroundps_u256, iemAImpl_vroundps_u256_fallback;
4470	FNIEMAIMPLMEDIAF2U256IMM8 iemAImpl_vroundpd_u256, iemAImpl_vroundpd_u256_fallback;
4471
4472	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vroundss_u128, iemAImpl_vroundss_u128_fallback;
4473	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vroundsd_u128, iemAImpl_vroundsd_u128_fallback;
4474
4475	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vdpps_u128, iemAImpl_vdpps_u128_fallback;
4476	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vdppd_u128, iemAImpl_vdppd_u128_fallback;
4477
4478	FNIEMAIMPLMEDIAF3YMMIMM8 iemAImpl_vdpps_u256, iemAImpl_vdpps_u256_fallback;
4479
4480
4481	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU64U128,(uint32_t fMxCsrIn, uint64_t *pu64Dst, PCX86XMMREG pSrc));
4482	typedef FNIEMAIMPLMXCSRU64U128 *PFNIEMAIMPLMXCSRU64U128;
4483
4484	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvtpd2pi_u128;
4485	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvttpd2pi_u128;
4486
4487	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU128U64,(uint32_t fMxCsrIn, PX86XMMREG pDst, uint64_t u64Src));
4488	typedef FNIEMAIMPLMXCSRU128U64 *PFNIEMAIMPLMXCSRU128U64;
4489
4490	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2ps_u128;
4491	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2pd_u128;
4492
4493	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU64U64,(uint32_t fMxCsrIn, uint64_t *pu64Dst, uint64_t u64Src));
4494	typedef FNIEMAIMPLMXCSRU64U64 *PFNIEMAIMPLMXCSRU64U64;
4495
4496	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvtps2pi_u128;
4497	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvttps2pi_u128;
4498
4499	/** @} */
4500
4501
4502	/** @name Function tables.
4503	* @{
4504	*/
4505
4506	/**
4507	* Function table for a binary operator providing implementation based on
4508	* operand size.
4509	*/
4510	typedef struct IEMOPBINSIZES
4511	{
4512	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
4513	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
4514	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
4515	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
4516	} IEMOPBINSIZES;
4517	/** Pointer to a binary operator function table. */
4518	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
4519
4520
4521	/**
4522	* Function table for a unary operator providing implementation based on
4523	* operand size.
4524	*/
4525	typedef struct IEMOPUNARYSIZES
4526	{
4527	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
4528	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
4529	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
4530	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
4531	} IEMOPUNARYSIZES;
4532	/** Pointer to a unary operator function table. */
4533	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
4534
4535
4536	/**
4537	* Function table for a shift operator providing implementation based on
4538	* operand size.
4539	*/
4540	typedef struct IEMOPSHIFTSIZES
4541	{
4542	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
4543	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
4544	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
4545	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
4546	} IEMOPSHIFTSIZES;
4547	/** Pointer to a shift operator function table. */
4548	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
4549
4550
4551	/**
4552	* Function table for a multiplication or division operation.
4553	*/
4554	typedef struct IEMOPMULDIVSIZES
4555	{
4556	PFNIEMAIMPLMULDIVU8 pfnU8;
4557	PFNIEMAIMPLMULDIVU16 pfnU16;
4558	PFNIEMAIMPLMULDIVU32 pfnU32;
4559	PFNIEMAIMPLMULDIVU64 pfnU64;
4560	} IEMOPMULDIVSIZES;
4561	/** Pointer to a multiplication or division operation function table. */
4562	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
4563
4564
4565	/**
4566	* Function table for a double precision shift operator providing implementation
4567	* based on operand size.
4568	*/
4569	typedef struct IEMOPSHIFTDBLSIZES
4570	{
4571	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
4572	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
4573	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
4574	} IEMOPSHIFTDBLSIZES;
4575	/** Pointer to a double precision shift function table. */
4576	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
4577
4578
4579	/**
4580	* Function table for media instruction taking two full sized media source
4581	* registers and one full sized destination register (AVX).
4582	*/
4583	typedef struct IEMOPMEDIAF3
4584	{
4585	PFNIEMAIMPLMEDIAF3U128 pfnU128;
4586	PFNIEMAIMPLMEDIAF3U256 pfnU256;
4587	} IEMOPMEDIAF3;
4588	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4589	typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
4590
4591	/** @def IEMOPMEDIAF3_INIT_VARS_EX
4592	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4593	* given functions as initializers. For use in AVX functions where a pair of
4594	* functions are only used once and the function table need not be public. */
4595	#ifndef TST_IEM_CHECK_MC
4596	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4597	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4598	static IEMOPMEDIAF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4599	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4600	# else
4601	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4602	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4603	# endif
4604	#else
4605	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4606	#endif
4607	/** @def IEMOPMEDIAF3_INIT_VARS
4608	* Generate AVX function tables for the @a a_InstrNm instruction.
4609	* @sa IEMOPMEDIAF3_INIT_VARS_EX */
4610	#define IEMOPMEDIAF3_INIT_VARS(a_InstrNm) \
4611	IEMOPMEDIAF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4612	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4613
4614
4615	/**
4616	* Function table for media instruction taking one full sized media source
4617	* registers and one full sized destination register (AVX).
4618	*/
4619	typedef struct IEMOPMEDIAF2
4620	{
4621	PFNIEMAIMPLMEDIAF2U128 pfnU128;
4622	PFNIEMAIMPLMEDIAF2U256 pfnU256;
4623	} IEMOPMEDIAF2;
4624	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4625	typedef IEMOPMEDIAF2 const *PCIEMOPMEDIAF2;
4626
4627	/** @def IEMOPMEDIAF2_INIT_VARS_EX
4628	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4629	* given functions as initializers. For use in AVX functions where a pair of
4630	* functions are only used once and the function table need not be public. */
4631	#ifndef TST_IEM_CHECK_MC
4632	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4633	# define IEMOPMEDIAF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4634	static IEMOPMEDIAF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4635	static IEMOPMEDIAF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4636	# else
4637	# define IEMOPMEDIAF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4638	static IEMOPMEDIAF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4639	# endif
4640	#else
4641	# define IEMOPMEDIAF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4642	#endif
4643	/** @def IEMOPMEDIAF2_INIT_VARS
4644	* Generate AVX function tables for the @a a_InstrNm instruction.
4645	* @sa IEMOPMEDIAF2_INIT_VARS_EX */
4646	#define IEMOPMEDIAF2_INIT_VARS(a_InstrNm) \
4647	IEMOPMEDIAF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4648	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4649
4650
4651	/**
4652	* Function table for media instruction taking two full sized media source
4653	* registers and one full sized destination register, but no additional state
4654	* (AVX).
4655	*/
4656	typedef struct IEMOPMEDIAOPTF3
4657	{
4658	PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
4659	PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
4660	} IEMOPMEDIAOPTF3;
4661	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4662	typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
4663
4664	/** @def IEMOPMEDIAOPTF3_INIT_VARS_EX
4665	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4666	* given functions as initializers. For use in AVX functions where a pair of
4667	* functions are only used once and the function table need not be public. */
4668	#ifndef TST_IEM_CHECK_MC
4669	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4670	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4671	static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4672	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4673	# else
4674	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4675	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4676	# endif
4677	#else
4678	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4679	#endif
4680	/** @def IEMOPMEDIAOPTF3_INIT_VARS
4681	* Generate AVX function tables for the @a a_InstrNm instruction.
4682	* @sa IEMOPMEDIAOPTF3_INIT_VARS_EX */
4683	#define IEMOPMEDIAOPTF3_INIT_VARS(a_InstrNm) \
4684	IEMOPMEDIAOPTF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4685	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4686
4687	/**
4688	* Function table for media instruction taking one full sized media source
4689	* registers and one full sized destination register, but no additional state
4690	* (AVX).
4691	*/
4692	typedef struct IEMOPMEDIAOPTF2
4693	{
4694	PFNIEMAIMPLMEDIAOPTF2U128 pfnU128;
4695	PFNIEMAIMPLMEDIAOPTF2U256 pfnU256;
4696	} IEMOPMEDIAOPTF2;
4697	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4698	typedef IEMOPMEDIAOPTF2 const *PCIEMOPMEDIAOPTF2;
4699
4700	/** @def IEMOPMEDIAOPTF2_INIT_VARS_EX
4701	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4702	* given functions as initializers. For use in AVX functions where a pair of
4703	* functions are only used once and the function table need not be public. */
4704	#ifndef TST_IEM_CHECK_MC
4705	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4706	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4707	static IEMOPMEDIAOPTF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4708	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4709	# else
4710	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4711	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4712	# endif
4713	#else
4714	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4715	#endif
4716	/** @def IEMOPMEDIAOPTF2_INIT_VARS
4717	* Generate AVX function tables for the @a a_InstrNm instruction.
4718	* @sa IEMOPMEDIAOPTF2_INIT_VARS_EX */
4719	#define IEMOPMEDIAOPTF2_INIT_VARS(a_InstrNm) \
4720	IEMOPMEDIAOPTF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4721	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4722
4723
4724	/**
4725	* Function table for media instruction taking one full sized media source
4726	* register and one full sized destination register and an 8-bit immediate (AVX).
4727	*/
4728	typedef struct IEMOPMEDIAF2IMM8
4729	{
4730	PFNIEMAIMPLMEDIAF2U128IMM8 pfnU128;
4731	PFNIEMAIMPLMEDIAF2U256IMM8 pfnU256;
4732	} IEMOPMEDIAF2IMM8;
4733	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4734	typedef IEMOPMEDIAF2IMM8 const *PCIEMOPMEDIAF2IMM8;
4735
4736	/** @def IEMOPMEDIAF2IMM8_INIT_VARS_EX
4737	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4738	* given functions as initializers. For use in AVX functions where a pair of
4739	* functions are only used once and the function table need not be public. */
4740	#ifndef TST_IEM_CHECK_MC
4741	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4742	# define IEMOPMEDIAF2IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4743	static IEMOPMEDIAF2IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4744	static IEMOPMEDIAF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4745	# else
4746	# define IEMOPMEDIAF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4747	static IEMOPMEDIAF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4748	# endif
4749	#else
4750	# define IEMOPMEDIAF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4751	#endif
4752	/** @def IEMOPMEDIAF2IMM8_INIT_VARS
4753	* Generate AVX function tables for the @a a_InstrNm instruction.
4754	* @sa IEMOPMEDIAF2IMM8_INIT_VARS_EX */
4755	#define IEMOPMEDIAF2IMM8_INIT_VARS(a_InstrNm) \
4756	IEMOPMEDIAF2IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4757	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4758
4759
4760	/**
4761	* Function table for media instruction taking one full sized media source
4762	* register and one full sized destination register and an 8-bit immediate, but no additional state
4763	* (AVX).
4764	*/
4765	typedef struct IEMOPMEDIAOPTF2IMM8
4766	{
4767	PFNIEMAIMPLMEDIAOPTF2U128IMM8 pfnU128;
4768	PFNIEMAIMPLMEDIAOPTF2U256IMM8 pfnU256;
4769	} IEMOPMEDIAOPTF2IMM8;
4770	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4771	typedef IEMOPMEDIAOPTF2IMM8 const *PCIEMOPMEDIAOPTF2IMM8;
4772
4773	/** @def IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX
4774	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4775	* given functions as initializers. For use in AVX functions where a pair of
4776	* functions are only used once and the function table need not be public. */
4777	#ifndef TST_IEM_CHECK_MC
4778	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4779	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4780	static IEMOPMEDIAOPTF2IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4781	static IEMOPMEDIAOPTF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4782	# else
4783	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4784	static IEMOPMEDIAOPTF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4785	# endif
4786	#else
4787	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4788	#endif
4789	/** @def IEMOPMEDIAOPTF2IMM8_INIT_VARS
4790	* Generate AVX function tables for the @a a_InstrNm instruction.
4791	* @sa IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX */
4792	#define IEMOPMEDIAOPTF2IMM8_INIT_VARS(a_InstrNm) \
4793	IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u256),\
4794	RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u256_fallback))
4795
4796	/**
4797	* Function table for media instruction taking two full sized media source
4798	* registers and one full sized destination register and an 8-bit immediate, but no additional state
4799	* (AVX).
4800	*/
4801	typedef struct IEMOPMEDIAOPTF3IMM8
4802	{
4803	PFNIEMAIMPLMEDIAOPTF3U128IMM8 pfnU128;
4804	PFNIEMAIMPLMEDIAOPTF3U256IMM8 pfnU256;
4805	} IEMOPMEDIAOPTF3IMM8;
4806	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4807	typedef IEMOPMEDIAOPTF3IMM8 const *PCIEMOPMEDIAOPTF3IMM8;
4808
4809	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX
4810	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4811	* given functions as initializers. For use in AVX functions where a pair of
4812	* functions are only used once and the function table need not be public. */
4813	#ifndef TST_IEM_CHECK_MC
4814	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4815	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4816	static IEMOPMEDIAOPTF3IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4817	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4818	# else
4819	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4820	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4821	# endif
4822	#else
4823	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4824	#endif
4825	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS
4826	* Generate AVX function tables for the @a a_InstrNm instruction.
4827	* @sa IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX */
4828	#define IEMOPMEDIAOPTF3IMM8_INIT_VARS(a_InstrNm) \
4829	IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4830	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4831	/** @} */
4832
4833
4834	/**
4835	* Function table for blend type instruction taking three full sized media source
4836	* registers and one full sized destination register, but no additional state
4837	* (AVX).
4838	*/
4839	typedef struct IEMOPBLENDOP
4840	{
4841	PFNIEMAIMPLAVXBLENDU128 pfnU128;
4842	PFNIEMAIMPLAVXBLENDU256 pfnU256;
4843	} IEMOPBLENDOP;
4844	/** Pointer to a media operation function table for 4 full sized ops (AVX). */
4845	typedef IEMOPBLENDOP const *PCIEMOPBLENDOP;
4846
4847	/** @def IEMOPBLENDOP_INIT_VARS_EX
4848	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4849	* given functions as initializers. For use in AVX functions where a pair of
4850	* functions are only used once and the function table need not be public. */
4851	#ifndef TST_IEM_CHECK_MC
4852	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4853	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4854	static IEMOPBLENDOP const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4855	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4856	# else
4857	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4858	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4859	# endif
4860	#else
4861	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4862	#endif
4863	/** @def IEMOPBLENDOP_INIT_VARS
4864	* Generate AVX function tables for the @a a_InstrNm instruction.
4865	* @sa IEMOPBLENDOP_INIT_VARS_EX */
4866	#define IEMOPBLENDOP_INIT_VARS(a_InstrNm) \
4867	IEMOPBLENDOP_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4868	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4869
4870
4871	/** @name SSE/AVX single/double precision floating point operations.
4872	* @{ */
4873	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
4874	typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128;
4875	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128R32,(uint32_t uMxCsrIn, PX86XMMREG Result, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
4876	typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32;
4877	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128R64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
4878	typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64;
4879
4880	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
4881	typedef FNIEMAIMPLFPAVXF3U128 *PFNIEMAIMPLFPAVXF3U128;
4882	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128R32,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
4883	typedef FNIEMAIMPLFPAVXF3U128R32 *PFNIEMAIMPLFPAVXF3U128R32;
4884	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128R64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
4885	typedef FNIEMAIMPLFPAVXF3U128R64 *PFNIEMAIMPLFPAVXF3U128R64;
4886
4887	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U256,(uint32_t uMxCsrIn, PX86YMMREG pResult, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
4888	typedef FNIEMAIMPLFPAVXF3U256 *PFNIEMAIMPLFPAVXF3U256;
4889
4890	FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
4891	FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
4892	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
4893	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
4894	FNIEMAIMPLFPSSEF2U128 iemAImpl_subps_u128;
4895	FNIEMAIMPLFPSSEF2U128 iemAImpl_subpd_u128;
4896	FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
4897	FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
4898	FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
4899	FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
4900	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxps_u128;
4901	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxpd_u128;
4902	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddps_u128;
4903	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddpd_u128;
4904	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubps_u128;
4905	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubpd_u128;
4906	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtps_u128;
4907	FNIEMAIMPLFPSSEF2U128 iemAImpl_rsqrtps_u128;
4908	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtpd_u128;
4909	FNIEMAIMPLFPSSEF2U128 iemAImpl_rcpps_u128;
4910	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubps_u128;
4911	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubpd_u128;
4912
4913	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2ps_u128;
4914	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_cvtps2pd_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, uint64_t const *pu64Src));
4915
4916	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2ps_u128;
4917	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2dq_u128;
4918	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttps2dq_u128;
4919	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttpd2dq_u128;
4920	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2pd_u128;
4921	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2dq_u128;
4922
4923	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_addss_u128_r32;
4924	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_addsd_u128_r64;
4925	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_mulss_u128_r32;
4926	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_mulsd_u128_r64;
4927	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_subss_u128_r32;
4928	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_subsd_u128_r64;
4929	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_minss_u128_r32;
4930	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_minsd_u128_r64;
4931	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_divss_u128_r32;
4932	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_divsd_u128_r64;
4933	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_maxss_u128_r32;
4934	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_maxsd_u128_r64;
4935	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_cvtss2sd_u128_r32;
4936	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_cvtsd2ss_u128_r64;
4937	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_sqrtss_u128_r32;
4938	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_sqrtsd_u128_r64;
4939	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rsqrtss_u128_r32;
4940	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rcpss_u128_r32;
4941
4942	FNIEMAIMPLMEDIAF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
4943	FNIEMAIMPLMEDIAF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
4944	FNIEMAIMPLMEDIAF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
4945	FNIEMAIMPLMEDIAF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
4946	FNIEMAIMPLMEDIAF3U128 iemAImpl_vsubps_u128, iemAImpl_vsubps_u128_fallback;
4947	FNIEMAIMPLMEDIAF3U128 iemAImpl_vsubpd_u128, iemAImpl_vsubpd_u128_fallback;
4948	FNIEMAIMPLMEDIAF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
4949	FNIEMAIMPLMEDIAF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
4950	FNIEMAIMPLMEDIAF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
4951	FNIEMAIMPLMEDIAF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
4952	FNIEMAIMPLMEDIAF3U128 iemAImpl_vmaxps_u128, iemAImpl_vmaxps_u128_fallback;
4953	FNIEMAIMPLMEDIAF3U128 iemAImpl_vmaxpd_u128, iemAImpl_vmaxpd_u128_fallback;
4954	FNIEMAIMPLMEDIAF3U128 iemAImpl_vhaddps_u128, iemAImpl_vhaddps_u128_fallback;
4955	FNIEMAIMPLMEDIAF3U128 iemAImpl_vhaddpd_u128, iemAImpl_vhaddpd_u128_fallback;
4956	FNIEMAIMPLMEDIAF3U128 iemAImpl_vhsubps_u128, iemAImpl_vhsubps_u128_fallback;
4957	FNIEMAIMPLMEDIAF3U128 iemAImpl_vhsubpd_u128, iemAImpl_vhsubpd_u128_fallback;
4958	FNIEMAIMPLMEDIAF2U128 iemAImpl_vsqrtps_u128, iemAImpl_vsqrtps_u128_fallback;
4959	FNIEMAIMPLMEDIAF2U128 iemAImpl_vsqrtpd_u128, iemAImpl_vsqrtpd_u128_fallback;
4960	FNIEMAIMPLMEDIAF2U128 iemAImpl_vrsqrtps_u128, iemAImpl_vrsqrtps_u128_fallback;
4961	FNIEMAIMPLMEDIAF2U128 iemAImpl_vrcpps_u128, iemAImpl_vrcpps_u128_fallback;
4962	FNIEMAIMPLMEDIAF3U128 iemAImpl_vaddsubps_u128, iemAImpl_vaddsubps_u128_fallback;
4963	FNIEMAIMPLMEDIAF3U128 iemAImpl_vaddsubpd_u128, iemAImpl_vaddsubpd_u128_fallback;
4964	FNIEMAIMPLMEDIAF2U128 iemAImpl_vcvtdq2ps_u128, iemAImpl_vcvtdq2ps_u128_fallback;
4965	FNIEMAIMPLMEDIAF2U128 iemAImpl_vcvtps2dq_u128, iemAImpl_vcvtps2dq_u128_fallback;
4966	FNIEMAIMPLMEDIAF2U128 iemAImpl_vcvttps2dq_u128, iemAImpl_vcvttps2dq_u128_fallback;
4967	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2ps_u128_u128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
4968	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2ps_u128_u128_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
4969	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvttpd2dq_u128_u128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
4970	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvttpd2dq_u128_u128_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
4971	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2dq_u128_u128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
4972	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2dq_u128_u128_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
4973
4974
4975	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback;
4976	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback;
4977	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback;
4978	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback;
4979	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback;
4980	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback;
4981	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback;
4982	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback;
4983	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback;
4984	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback;
4985	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmaxss_u128_r32, iemAImpl_vmaxss_u128_r32_fallback;
4986	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmaxsd_u128_r64, iemAImpl_vmaxsd_u128_r64_fallback;
4987	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsqrtss_u128_r32, iemAImpl_vsqrtss_u128_r32_fallback;
4988	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsqrtsd_u128_r64, iemAImpl_vsqrtsd_u128_r64_fallback;
4989	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vrsqrtss_u128_r32, iemAImpl_vrsqrtss_u128_r32_fallback;
4990	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vrcpss_u128_r32, iemAImpl_vrcpss_u128_r32_fallback;
4991	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vcvtss2sd_u128_r32, iemAImpl_vcvtss2sd_u128_r32_fallback;
4992	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vcvtsd2ss_u128_r64, iemAImpl_vcvtsd2ss_u128_r64_fallback;
4993
4994
4995	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
4996	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
4997	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
4998	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
4999	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubps_u256, iemAImpl_vsubps_u256_fallback;
5000	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubpd_u256, iemAImpl_vsubpd_u256_fallback;
5001	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
5002	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
5003	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
5004	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
5005	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxps_u256, iemAImpl_vmaxps_u256_fallback;
5006	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxpd_u256, iemAImpl_vmaxpd_u256_fallback;
5007	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddps_u256, iemAImpl_vhaddps_u256_fallback;
5008	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddpd_u256, iemAImpl_vhaddpd_u256_fallback;
5009	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubps_u256, iemAImpl_vhsubps_u256_fallback;
5010	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubpd_u256, iemAImpl_vhsubpd_u256_fallback;
5011	FNIEMAIMPLMEDIAF3U256 iemAImpl_vaddsubps_u256, iemAImpl_vaddsubps_u256_fallback;
5012	FNIEMAIMPLMEDIAF3U256 iemAImpl_vaddsubpd_u256, iemAImpl_vaddsubpd_u256_fallback;
5013	FNIEMAIMPLMEDIAF2U256 iemAImpl_vsqrtps_u256, iemAImpl_vsqrtps_u256_fallback;
5014	FNIEMAIMPLMEDIAF2U256 iemAImpl_vsqrtpd_u256, iemAImpl_vsqrtpd_u256_fallback;
5015	FNIEMAIMPLMEDIAF2U256 iemAImpl_vrsqrtps_u256, iemAImpl_vrsqrtps_u256_fallback;
5016	FNIEMAIMPLMEDIAF2U256 iemAImpl_vrcpps_u256, iemAImpl_vrcpps_u256_fallback;
5017	FNIEMAIMPLMEDIAF2U256 iemAImpl_vcvtdq2ps_u256, iemAImpl_vcvtdq2ps_u256_fallback;
5018	FNIEMAIMPLMEDIAF2U256 iemAImpl_vcvtps2dq_u256, iemAImpl_vcvtps2dq_u256_fallback;
5019	FNIEMAIMPLMEDIAF2U256 iemAImpl_vcvttps2dq_u256, iemAImpl_vcvttps2dq_u256_fallback;
5020	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2ps_u128_u256,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5021	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2ps_u128_u256_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5022	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvttpd2dq_u128_u256,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5023	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvttpd2dq_u128_u256_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5024	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2dq_u128_u256,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5025	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2dq_u128_u256_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5026	/** @} */
5027
5028	/** @name C instruction implementations for anything slightly complicated.
5029	* @{ */
5030
5031	/**
5032	* For typedef'ing or declaring a C instruction implementation function taking
5033	* no extra arguments.
5034	*
5035	* @param a_Name The name of the type.
5036	*/
5037	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
5038	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
5039	/**
5040	* For defining a C instruction implementation function taking no extra
5041	* arguments.
5042	*
5043	* @param a_Name The name of the function
5044	*/
5045	# define IEM_CIMPL_DEF_0(a_Name) \
5046	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
5047	/**
5048	* Prototype version of IEM_CIMPL_DEF_0.
5049	*/
5050	# define IEM_CIMPL_PROTO_0(a_Name) \
5051	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
5052	/**
5053	* For calling a C instruction implementation function taking no extra
5054	* arguments.
5055	*
5056	* This special call macro adds default arguments to the call and allow us to
5057	* change these later.
5058	*
5059	* @param a_fn The name of the function.
5060	*/
5061	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
5062
5063	/** Type for a C instruction implementation function taking no extra
5064	* arguments. */
5065	typedef IEM_CIMPL_DECL_TYPE_0(FNIEMCIMPL0);
5066	/** Function pointer type for a C instruction implementation function taking
5067	* no extra arguments. */
5068	typedef FNIEMCIMPL0 *PFNIEMCIMPL0;
5069
5070	/**
5071	* For typedef'ing or declaring a C instruction implementation function taking
5072	* one extra argument.
5073	*
5074	* @param a_Name The name of the type.
5075	* @param a_Type0 The argument type.
5076	* @param a_Arg0 The argument name.
5077	*/
5078	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
5079	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
5080	/**
5081	* For defining a C instruction implementation function taking one extra
5082	* argument.
5083	*
5084	* @param a_Name The name of the function
5085	* @param a_Type0 The argument type.
5086	* @param a_Arg0 The argument name.
5087	*/
5088	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
5089	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
5090	/**
5091	* Prototype version of IEM_CIMPL_DEF_1.
5092	*/
5093	# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
5094	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
5095	/**
5096	* For calling a C instruction implementation function taking one extra
5097	* argument.
5098	*
5099	* This special call macro adds default arguments to the call and allow us to
5100	* change these later.
5101	*
5102	* @param a_fn The name of the function.
5103	* @param a0 The name of the 1st argument.
5104	*/
5105	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
5106
5107	/**
5108	* For typedef'ing or declaring a C instruction implementation function taking
5109	* two extra arguments.
5110	*
5111	* @param a_Name The name of the type.
5112	* @param a_Type0 The type of the 1st argument
5113	* @param a_Arg0 The name of the 1st argument.
5114	* @param a_Type1 The type of the 2nd argument.
5115	* @param a_Arg1 The name of the 2nd argument.
5116	*/
5117	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
5118	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
5119	/**
5120	* For defining a C instruction implementation function taking two extra
5121	* arguments.
5122	*
5123	* @param a_Name The name of the function.
5124	* @param a_Type0 The type of the 1st argument
5125	* @param a_Arg0 The name of the 1st argument.
5126	* @param a_Type1 The type of the 2nd argument.
5127	* @param a_Arg1 The name of the 2nd argument.
5128	*/
5129	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
5130	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
5131	/**
5132	* Prototype version of IEM_CIMPL_DEF_2.
5133	*/
5134	# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
5135	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
5136	/**
5137	* For calling a C instruction implementation function taking two extra
5138	* arguments.
5139	*
5140	* This special call macro adds default arguments to the call and allow us to
5141	* change these later.
5142	*
5143	* @param a_fn The name of the function.
5144	* @param a0 The name of the 1st argument.
5145	* @param a1 The name of the 2nd argument.
5146	*/
5147	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
5148
5149	/**
5150	* For typedef'ing or declaring a C instruction implementation function taking
5151	* three extra arguments.
5152	*
5153	* @param a_Name The name of the type.
5154	* @param a_Type0 The type of the 1st argument
5155	* @param a_Arg0 The name of the 1st argument.
5156	* @param a_Type1 The type of the 2nd argument.
5157	* @param a_Arg1 The name of the 2nd argument.
5158	* @param a_Type2 The type of the 3rd argument.
5159	* @param a_Arg2 The name of the 3rd argument.
5160	*/
5161	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
5162	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
5163	/**
5164	* For defining a C instruction implementation function taking three extra
5165	* arguments.
5166	*
5167	* @param a_Name The name of the function.
5168	* @param a_Type0 The type of the 1st argument
5169	* @param a_Arg0 The name of the 1st argument.
5170	* @param a_Type1 The type of the 2nd argument.
5171	* @param a_Arg1 The name of the 2nd argument.
5172	* @param a_Type2 The type of the 3rd argument.
5173	* @param a_Arg2 The name of the 3rd argument.
5174	*/
5175	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
5176	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
5177	/**
5178	* Prototype version of IEM_CIMPL_DEF_3.
5179	*/
5180	# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
5181	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
5182	/**
5183	* For calling a C instruction implementation function taking three extra
5184	* arguments.
5185	*
5186	* This special call macro adds default arguments to the call and allow us to
5187	* change these later.
5188	*
5189	* @param a_fn The name of the function.
5190	* @param a0 The name of the 1st argument.
5191	* @param a1 The name of the 2nd argument.
5192	* @param a2 The name of the 3rd argument.
5193	*/
5194	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
5195
5196
5197	/**
5198	* For typedef'ing or declaring a C instruction implementation function taking
5199	* four extra arguments.
5200	*
5201	* @param a_Name The name of the type.
5202	* @param a_Type0 The type of the 1st argument
5203	* @param a_Arg0 The name of the 1st argument.
5204	* @param a_Type1 The type of the 2nd argument.
5205	* @param a_Arg1 The name of the 2nd argument.
5206	* @param a_Type2 The type of the 3rd argument.
5207	* @param a_Arg2 The name of the 3rd argument.
5208	* @param a_Type3 The type of the 4th argument.
5209	* @param a_Arg3 The name of the 4th argument.
5210	*/
5211	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
5212	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
5213	/**
5214	* For defining a C instruction implementation function taking four extra
5215	* arguments.
5216	*
5217	* @param a_Name The name of the function.
5218	* @param a_Type0 The type of the 1st argument
5219	* @param a_Arg0 The name of the 1st argument.
5220	* @param a_Type1 The type of the 2nd argument.
5221	* @param a_Arg1 The name of the 2nd argument.
5222	* @param a_Type2 The type of the 3rd argument.
5223	* @param a_Arg2 The name of the 3rd argument.
5224	* @param a_Type3 The type of the 4th argument.
5225	* @param a_Arg3 The name of the 4th argument.
5226	*/
5227	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
5228	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
5229	a_Type2 a_Arg2, a_Type3 a_Arg3))
5230	/**
5231	* Prototype version of IEM_CIMPL_DEF_4.
5232	*/
5233	# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
5234	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
5235	a_Type2 a_Arg2, a_Type3 a_Arg3))
5236	/**
5237	* For calling a C instruction implementation function taking four extra
5238	* arguments.
5239	*
5240	* This special call macro adds default arguments to the call and allow us to
5241	* change these later.
5242	*
5243	* @param a_fn The name of the function.
5244	* @param a0 The name of the 1st argument.
5245	* @param a1 The name of the 2nd argument.
5246	* @param a2 The name of the 3rd argument.
5247	* @param a3 The name of the 4th argument.
5248	*/
5249	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
5250
5251
5252	/**
5253	* For typedef'ing or declaring a C instruction implementation function taking
5254	* five extra arguments.
5255	*
5256	* @param a_Name The name of the type.
5257	* @param a_Type0 The type of the 1st argument
5258	* @param a_Arg0 The name of the 1st argument.
5259	* @param a_Type1 The type of the 2nd argument.
5260	* @param a_Arg1 The name of the 2nd argument.
5261	* @param a_Type2 The type of the 3rd argument.
5262	* @param a_Arg2 The name of the 3rd argument.
5263	* @param a_Type3 The type of the 4th argument.
5264	* @param a_Arg3 The name of the 4th argument.
5265	* @param a_Type4 The type of the 5th argument.
5266	* @param a_Arg4 The name of the 5th argument.
5267	*/
5268	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
5269	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
5270	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
5271	a_Type3 a_Arg3, a_Type4 a_Arg4))
5272	/**
5273	* For defining a C instruction implementation function taking five extra
5274	* arguments.
5275	*
5276	* @param a_Name The name of the function.
5277	* @param a_Type0 The type of the 1st argument
5278	* @param a_Arg0 The name of the 1st argument.
5279	* @param a_Type1 The type of the 2nd argument.
5280	* @param a_Arg1 The name of the 2nd argument.
5281	* @param a_Type2 The type of the 3rd argument.
5282	* @param a_Arg2 The name of the 3rd argument.
5283	* @param a_Type3 The type of the 4th argument.
5284	* @param a_Arg3 The name of the 4th argument.
5285	* @param a_Type4 The type of the 5th argument.
5286	* @param a_Arg4 The name of the 5th argument.
5287	*/
5288	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
5289	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
5290	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
5291	/**
5292	* Prototype version of IEM_CIMPL_DEF_5.
5293	*/
5294	# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
5295	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
5296	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
5297	/**
5298	* For calling a C instruction implementation function taking five extra
5299	* arguments.
5300	*
5301	* This special call macro adds default arguments to the call and allow us to
5302	* change these later.
5303	*
5304	* @param a_fn The name of the function.
5305	* @param a0 The name of the 1st argument.
5306	* @param a1 The name of the 2nd argument.
5307	* @param a2 The name of the 3rd argument.
5308	* @param a3 The name of the 4th argument.
5309	* @param a4 The name of the 5th argument.
5310	*/
5311	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
5312
5313	/** @} */
5314
5315
5316	/** @name Opcode Decoder Function Types.
5317	* @{ */
5318
5319	/** @typedef PFNIEMOP
5320	* Pointer to an opcode decoder function.
5321	*/
5322
5323	/** @def FNIEMOP_DEF
5324	* Define an opcode decoder function.
5325	*
5326	* We're using macors for this so that adding and removing parameters as well as
5327	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
5328	*
5329	* @param a_Name The function name.
5330	*/
5331
5332	/** @typedef PFNIEMOPRM
5333	* Pointer to an opcode decoder function with RM byte.
5334	*/
5335
5336	/** @def FNIEMOPRM_DEF
5337	* Define an opcode decoder function with RM byte.
5338	*
5339	* We're using macors for this so that adding and removing parameters as well as
5340	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
5341	*
5342	* @param a_Name The function name.
5343	*/
5344
5345	#if defined(__GNUC__) && defined(RT_ARCH_X86)
5346	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
5347	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
5348	# define FNIEMOP_DEF(a_Name) \
5349	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
5350	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
5351	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
5352	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
5353	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
5354
5355	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
5356	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
5357	typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
5358	# define FNIEMOP_DEF(a_Name) \
5359	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
5360	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
5361	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
5362	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
5363	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
5364
5365	#elif defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
5366	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
5367	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
5368	# define FNIEMOP_DEF(a_Name) \
5369	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
5370	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
5371	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
5372	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
5373	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
5374
5375	#else
5376	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
5377	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
5378	# define FNIEMOP_DEF(a_Name) \
5379	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
5380	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
5381	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
5382	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
5383	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
5384
5385	#endif
5386	#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
5387
5388	/**
5389	* Call an opcode decoder function.
5390	*
5391	* We're using macors for this so that adding and removing parameters can be
5392	* done as we please. See FNIEMOP_DEF.
5393	*/
5394	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
5395
5396	/**
5397	* Call a common opcode decoder function taking one extra argument.
5398	*
5399	* We're using macors for this so that adding and removing parameters can be
5400	* done as we please. See FNIEMOP_DEF_1.
5401	*/
5402	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
5403
5404	/**
5405	* Call a common opcode decoder function taking one extra argument.
5406	*
5407	* We're using macors for this so that adding and removing parameters can be
5408	* done as we please. See FNIEMOP_DEF_1.
5409	*/
5410	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
5411	/** @} */
5412
5413
5414	/** @name Misc Helpers
5415	* @{ */
5416
5417	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
5418	* due to GCC lacking knowledge about the value range of a switch. */
5419	#if RT_CPLUSPLUS_PREREQ(202000)
5420	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: [[unlikely]] AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
5421	#else
5422	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
5423	#endif
5424
5425	/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
5426	#if RT_CPLUSPLUS_PREREQ(202000)
5427	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: [[unlikely]] AssertFailedReturn(a_RetValue)
5428	#else
5429	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
5430	#endif
5431
5432	/**
5433	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
5434	* occation.
5435	*/
5436	#ifdef LOG_ENABLED
5437	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
5438	do { \
5439	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
5440	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
5441	} while (0)
5442	#else
5443	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
5444	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
5445	#endif
5446
5447	/**
5448	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
5449	* occation using the supplied logger statement.
5450	*
5451	* @param a_LoggerArgs What to log on failure.
5452	*/
5453	#ifdef LOG_ENABLED
5454	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
5455	do { \
5456	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
5457	/LogFunc(a_LoggerArgs);/ \
5458	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
5459	} while (0)
5460	#else
5461	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
5462	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
5463	#endif
5464
5465	/**
5466	* Gets the CPU mode (from fExec) as a IEMMODE value.
5467	*
5468	* @returns IEMMODE
5469	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5470	*/
5471	#define IEM_GET_CPU_MODE(a_pVCpu) ((a_pVCpu)->iem.s.fExec & IEM_F_MODE_CPUMODE_MASK)
5472
5473	/**
5474	* Check if we're currently executing in real or virtual 8086 mode.
5475	*
5476	* @returns @c true if it is, @c false if not.
5477	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5478	*/
5479	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (( ((a_pVCpu)->iem.s.fExec ^ IEM_F_MODE_X86_PROT_MASK) \
5480	& (IEM_F_MODE_X86_V86_MASK \| IEM_F_MODE_X86_PROT_MASK)) != 0)
5481
5482	/**
5483	* Check if we're currently executing in virtual 8086 mode.
5484	*
5485	* @returns @c true if it is, @c false if not.
5486	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5487	*/
5488	#define IEM_IS_V86_MODE(a_pVCpu) (((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_V86_MASK) != 0)
5489
5490	/**
5491	* Check if we're currently executing in long mode.
5492	*
5493	* @returns @c true if it is, @c false if not.
5494	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5495	*/
5496	#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
5497
5498	/**
5499	* Check if we're currently executing in a 16-bit code segment.
5500	*
5501	* @returns @c true if it is, @c false if not.
5502	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5503	*/
5504	#define IEM_IS_16BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_16BIT)
5505
5506	/**
5507	* Check if we're currently executing in a 32-bit code segment.
5508	*
5509	* @returns @c true if it is, @c false if not.
5510	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5511	*/
5512	#define IEM_IS_32BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_32BIT)
5513
5514	/**
5515	* Check if we're currently executing in a 64-bit code segment.
5516	*
5517	* @returns @c true if it is, @c false if not.
5518	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5519	*/
5520	#define IEM_IS_64BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_64BIT)
5521
5522	/**
5523	* Check if we're currently executing in real mode.
5524	*
5525	* @returns @c true if it is, @c false if not.
5526	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5527	*/
5528	#define IEM_IS_REAL_MODE(a_pVCpu) (!((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_PROT_MASK))
5529
5530	/**
5531	* Gets the current protection level (CPL).
5532	*
5533	* @returns 0..3
5534	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5535	*/
5536	#define IEM_GET_CPL(a_pVCpu) (((a_pVCpu)->iem.s.fExec >> IEM_F_X86_CPL_SHIFT) & IEM_F_X86_CPL_SMASK)
5537
5538	/**
5539	* Sets the current protection level (CPL).
5540	*
5541	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5542	*/
5543	#define IEM_SET_CPL(a_pVCpu, a_uCpl) \
5544	do { (a_pVCpu)->iem.s.fExec = ((a_pVCpu)->iem.s.fExec & ~IEM_F_X86_CPL_MASK) \| ((a_uCpl) << IEM_F_X86_CPL_SHIFT); } while (0)
5545
5546	/**
5547	* Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
5548	* @returns PCCPUMFEATURES
5549	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5550	*/
5551	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
5552
5553	/**
5554	* Returns a (const) pointer to the CPUMFEATURES for the host CPU.
5555	* @returns PCCPUMFEATURES
5556	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5557	*/
5558	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
5559
5560	/**
5561	* Evaluates to true if we're presenting an Intel CPU to the guest.
5562	*/
5563	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
5564
5565	/**
5566	* Evaluates to true if we're presenting an AMD CPU to the guest.
5567	*/
5568	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD \|\| (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
5569
5570	/**
5571	* Check if the address is canonical.
5572	*/
5573	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
5574
5575	/** Checks if the ModR/M byte is in register mode or not. */
5576	#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
5577	/** Checks if the ModR/M byte is in memory mode or not. */
5578	#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
5579
5580	/**
5581	* Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
5582	*
5583	* For use during decoding.
5584	*/
5585	#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| (a_pVCpu)->iem.s.uRexReg )
5586	/**
5587	* Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
5588	*
5589	* For use during decoding.
5590	*/
5591	#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) \| (a_pVCpu)->iem.s.uRexB )
5592
5593	/**
5594	* Gets the register (reg) part of a ModR/M encoding, without REX.R.
5595	*
5596	* For use during decoding.
5597	*/
5598	#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
5599	/**
5600	* Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
5601	*
5602	* For use during decoding.
5603	*/
5604	#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
5605
5606	/**
5607	* Gets the register (reg) part of a ModR/M encoding as an extended 8-bit
5608	* register index, with REX.R added in.
5609	*
5610	* For use during decoding.
5611	*
5612	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
5613	*/
5614	#define IEM_GET_MODRM_REG_EX8(a_pVCpu, a_bRm) \
5615	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
5616	\|\| !((a_bRm) & (4 << X86_MODRM_REG_SHIFT)) /* IEM_GET_MODRM_REG(pVCpu, a_bRm) < 4 */ \
5617	? IEM_GET_MODRM_REG(pVCpu, a_bRm) : (((a_bRm) >> X86_MODRM_REG_SHIFT) & 3) \| 16)
5618	/**
5619	* Gets the r/m part of a ModR/M encoding as an extended 8-bit register index,
5620	* with REX.B added in.
5621	*
5622	* For use during decoding.
5623	*
5624	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
5625	*/
5626	#define IEM_GET_MODRM_RM_EX8(a_pVCpu, a_bRm) \
5627	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
5628	\|\| !((a_bRm) & 4) /* IEM_GET_MODRM_RM(pVCpu, a_bRm) < 4 */ \
5629	? IEM_GET_MODRM_RM(pVCpu, a_bRm) : ((a_bRm) & 3) \| 16)
5630
5631	/**
5632	* Combines the prefix REX and ModR/M byte for passing to
5633	* iemOpHlpCalcRmEffAddrThreadedAddr64().
5634	*
5635	* @returns The ModRM byte but with bit 3 set to REX.B and bit 4 to REX.X.
5636	* The two bits are part of the REG sub-field, which isn't needed in
5637	* iemOpHlpCalcRmEffAddrThreadedAddr64().
5638	*
5639	* For use during decoding/recompiling.
5640	*/
5641	#define IEM_GET_MODRM_EX(a_pVCpu, a_bRm) \
5642	( ((a_bRm) & ~X86_MODRM_REG_MASK) \
5643	\| (uint8_t)( (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X)) >> (25 - 3) ) )
5644	AssertCompile(IEM_OP_PRF_REX_B == RT_BIT_32(25));
5645	AssertCompile(IEM_OP_PRF_REX_X == RT_BIT_32(26));
5646
5647	/**
5648	* Gets the effective VEX.VVVV value.
5649	*
5650	* The 4th bit is ignored if not 64-bit code.
5651	* @returns effective V-register value.
5652	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5653	*/
5654	#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
5655	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
5656
5657
5658	/**
5659	* Gets the register (reg) part of a the special 4th register byte used by
5660	* vblendvps and vblendvpd.
5661	*
5662	* For use during decoding.
5663	*/
5664	#define IEM_GET_IMM8_REG(a_pVCpu, a_bRegImm8) \
5665	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_bRegImm8) >> 4 : ((a_bRegImm8) >> 4) & 7)
5666
5667
5668	/**
5669	* Checks if we're executing inside an AMD-V or VT-x guest.
5670	*/
5671	#if defined(VBOX_WITH_NESTED_HWVIRT_VMX) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
5672	# define IEM_IS_IN_GUEST(a_pVCpu) RT_BOOL((a_pVCpu)->iem.s.fExec & IEM_F_X86_CTX_IN_GUEST)
5673	#else
5674	# define IEM_IS_IN_GUEST(a_pVCpu) false
5675	#endif
5676
5677
5678	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5679
5680	/**
5681	* Check if the guest has entered VMX root operation.
5682	*/
5683	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
5684
5685	/**
5686	* Check if the guest has entered VMX non-root operation.
5687	*/
5688	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) ( ((a_pVCpu)->iem.s.fExec & (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST)) \
5689	== (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST) )
5690
5691	/**
5692	* Check if the nested-guest has the given Pin-based VM-execution control set.
5693	*/
5694	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) (CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
5695
5696	/**
5697	* Check if the nested-guest has the given Processor-based VM-execution control set.
5698	*/
5699	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) (CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
5700
5701	/**
5702	* Check if the nested-guest has the given Secondary Processor-based VM-execution
5703	* control set.
5704	*/
5705	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) (CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
5706
5707	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
5708	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
5709
5710	/** Whether a shadow VMCS is present for the given VCPU. */
5711	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
5712
5713	/** Gets the VMXON region pointer. */
5714	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
5715
5716	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
5717	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
5718
5719	/** Whether a current VMCS is present for the given VCPU. */
5720	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
5721
5722	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
5723	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
5724	do \
5725	{ \
5726	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
5727	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
5728	} while (0)
5729
5730	/** Clears any current VMCS for the given VCPU. */
5731	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
5732	do \
5733	{ \
5734	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
5735	} while (0)
5736
5737	/**
5738	* Invokes the VMX VM-exit handler for an instruction intercept.
5739	*/
5740	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
5741	do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
5742
5743	/**
5744	* Invokes the VMX VM-exit handler for an instruction intercept where the
5745	* instruction provides additional VM-exit information.
5746	*/
5747	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
5748	do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
5749
5750	/**
5751	* Invokes the VMX VM-exit handler for a task switch.
5752	*/
5753	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
5754	do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
5755
5756	/**
5757	* Invokes the VMX VM-exit handler for MWAIT.
5758	*/
5759	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
5760	do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
5761
5762	/**
5763	* Invokes the VMX VM-exit handler for EPT faults.
5764	*/
5765	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
5766	do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
5767
5768	/**
5769	* Invokes the VMX VM-exit handler.
5770	*/
5771	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
5772	do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
5773
5774	#else
5775	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
5776	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
5777	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
5778	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
5779	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
5780	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5781	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5782	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5783	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5784	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5785	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
5786
5787	#endif
5788
5789	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5790	/**
5791	* Checks if we're executing a guest using AMD-V.
5792	*/
5793	# define IEM_SVM_IS_IN_GUEST(a_pVCpu) ( (a_pVCpu->iem.s.fExec & (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST)) \
5794	== (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST))
5795	/**
5796	* Check if an SVM control/instruction intercept is set.
5797	*/
5798	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
5799	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
5800
5801	/**
5802	* Check if an SVM read CRx intercept is set.
5803	*/
5804	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
5805	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
5806
5807	/**
5808	* Check if an SVM write CRx intercept is set.
5809	*/
5810	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
5811	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
5812
5813	/**
5814	* Check if an SVM read DRx intercept is set.
5815	*/
5816	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
5817	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
5818
5819	/**
5820	* Check if an SVM write DRx intercept is set.
5821	*/
5822	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
5823	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
5824
5825	/**
5826	* Check if an SVM exception intercept is set.
5827	*/
5828	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
5829	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
5830
5831	/**
5832	* Invokes the SVM \#VMEXIT handler for the nested-guest.
5833	*/
5834	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
5835	do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
5836
5837	/**
5838	* Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
5839	* corresponding decode assist information.
5840	*/
5841	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
5842	do \
5843	{ \
5844	uint64_t uExitInfo1; \
5845	if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
5846	&& (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
5847	uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK \| ((a_iGReg) & 7); \
5848	else \
5849	uExitInfo1 = 0; \
5850	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
5851	} while (0)
5852
5853	/** Check and handles SVM nested-guest instruction intercept and updates
5854	* NRIP if needed.
5855	*/
5856	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
5857	do \
5858	{ \
5859	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
5860	{ \
5861	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
5862	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
5863	} \
5864	} while (0)
5865
5866	/** Checks and handles SVM nested-guest CR0 read intercept. */
5867	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
5868	do \
5869	{ \
5870	if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
5871	{ /* probably likely */ } \
5872	else \
5873	{ \
5874	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
5875	IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
5876	} \
5877	} while (0)
5878
5879	/**
5880	* Updates the NextRIP (NRI) field in the nested-guest VMCB.
5881	*/
5882	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) \
5883	do { \
5884	if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
5885	CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_cbInstr)); \
5886	} while (0)
5887
5888	#else
5889	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
5890	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
5891	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
5892	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
5893	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
5894	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
5895	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
5896	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
5897	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, \
5898	a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
5899	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
5900	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) do { } while (0)
5901
5902	#endif
5903
5904	/** @} */
5905
5906	uint32_t iemCalcExecDbgFlagsSlow(PVMCPUCC pVCpu);
5907	VBOXSTRICTRC iemExecInjectPendingTrap(PVMCPUCC pVCpu);
5908
5909
5910	/**
5911	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
5912	*/
5913	typedef union IEMSELDESC
5914	{
5915	/** The legacy view. */
5916	X86DESC Legacy;
5917	/** The long mode view. */
5918	X86DESC64 Long;
5919	} IEMSELDESC;
5920	/** Pointer to a selector descriptor table entry. */
5921	typedef IEMSELDESC *PIEMSELDESC;
5922
5923	/** @name Raising Exceptions.
5924	* @{ */
5925	VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
5926	uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
5927
5928	VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
5929	uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
5930	#ifdef IEM_WITH_SETJMP
5931	DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
5932	uint32_t fFlags, uint16_t uErr, uint64_t uCr2) IEM_NOEXCEPT_MAY_LONGJMP;
5933	#endif
5934	VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
5935	#ifdef IEM_WITH_SETJMP
5936	DECL_NO_RETURN(void) iemRaiseDivideErrorJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5937	#endif
5938	VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
5939	VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
5940	VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
5941	#ifdef IEM_WITH_SETJMP
5942	DECL_NO_RETURN(void) iemRaiseUndefinedOpcodeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5943	#endif
5944	VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
5945	#ifdef IEM_WITH_SETJMP
5946	DECL_NO_RETURN(void) iemRaiseDeviceNotAvailableJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5947	#endif
5948	VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5949	VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
5950	VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
5951	VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5952	/VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;/
5953	VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5954	VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5955	VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5956	VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5957	VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5958	VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
5959	#ifdef IEM_WITH_SETJMP
5960	DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5961	#endif
5962	VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
5963	VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
5964	VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
5965	#ifdef IEM_WITH_SETJMP
5966	DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
5967	#endif
5968	VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
5969	#ifdef IEM_WITH_SETJMP
5970	DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) IEM_NOEXCEPT_MAY_LONGJMP;
5971	#endif
5972	VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
5973	#ifdef IEM_WITH_SETJMP
5974	DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
5975	#endif
5976	VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) RT_NOEXCEPT;
5977	#ifdef IEM_WITH_SETJMP
5978	DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) IEM_NOEXCEPT_MAY_LONGJMP;
5979	#endif
5980	VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
5981	#ifdef IEM_WITH_SETJMP
5982	DECL_NO_RETURN(void) iemRaiseMathFaultJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5983	#endif
5984	VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu) RT_NOEXCEPT;
5985	#ifdef IEM_WITH_SETJMP
5986	DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5987	#endif
5988	VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
5989	#ifdef IEM_WITH_SETJMP
5990	DECL_NO_RETURN(void) iemRaiseSimdFpExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5991	#endif
5992
5993	void iemLogSyscallRealModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
5994	void iemLogSyscallProtModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
5995
5996	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
5997	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
5998	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
5999
6000	/**
6001	* Macro for calling iemCImplRaiseDivideError().
6002	*
6003	* This is for things that will _always_ decode to an \#DE, taking the
6004	* recompiler into consideration and everything.
6005	*
6006	* @return Strict VBox status code.
6007	*/
6008	#define IEMOP_RAISE_DIVIDE_ERROR_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseDivideError)
6009
6010	/**
6011	* Macro for calling iemCImplRaiseInvalidLockPrefix().
6012	*
6013	* This is for things that will _always_ decode to an \#UD, taking the
6014	* recompiler into consideration and everything.
6015	*
6016	* @return Strict VBox status code.
6017	*/
6018	#define IEMOP_RAISE_INVALID_LOCK_PREFIX_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidLockPrefix)
6019
6020	/**
6021	* Macro for calling iemCImplRaiseInvalidOpcode() for decode/static \#UDs.
6022	*
6023	* This is for things that will _always_ decode to an \#UD, taking the
6024	* recompiler into consideration and everything.
6025	*
6026	* @return Strict VBox status code.
6027	*/
6028	#define IEMOP_RAISE_INVALID_OPCODE_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
6029
6030	/**
6031	* Macro for calling iemCImplRaiseInvalidOpcode() for runtime-style \#UDs.
6032	*
6033	* Using this macro means you've got _buggy_ _code_ and are doing things that
6034	* belongs exclusively in IEMAllCImpl.cpp during decoding.
6035	*
6036	* @return Strict VBox status code.
6037	* @see IEMOP_RAISE_INVALID_OPCODE_RET
6038	*/
6039	#define IEMOP_RAISE_INVALID_OPCODE_RUNTIME_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
6040
6041	/** @} */
6042
6043	/** @name Register Access.
6044	* @{ */
6045	VBOXSTRICTRC iemRegRipRelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
6046	IEMMODE enmEffOpSize) RT_NOEXCEPT;
6047	VBOXSTRICTRC iemRegRipRelativeJumpS16AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int16_t offNextInstr) RT_NOEXCEPT;
6048	VBOXSTRICTRC iemRegRipRelativeJumpS32AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int32_t offNextInstr,
6049	IEMMODE enmEffOpSize) RT_NOEXCEPT;
6050	/** @} */
6051
6052	/** @name FPU access and helpers.
6053	* @{ */
6054	void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
6055	void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6056	void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
6057	void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
6058	void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
6059	void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
6060	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6061	void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
6062	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6063	void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
6064	void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
6065	void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
6066	void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6067	void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
6068	void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6069	void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
6070	void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6071	void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
6072	void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6073	void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
6074	void iemFpuStackPushUnderflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
6075	void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
6076	void iemFpuStackPushOverflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
6077	void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6078	/** @} */
6079
6080	/** @name SSE+AVX SIMD access and helpers.
6081	* @{ */
6082	void iemSseUpdateMxcsr(PVMCPUCC pVCpu, uint32_t fMxcsr) RT_NOEXCEPT;
6083	/** @} */
6084
6085	/** @name Memory access.
6086	* @{ */
6087
6088	/** Report a \#GP instead of \#AC and do not restrict to ring-3 */
6089	#define IEM_MEMMAP_F_ALIGN_GP RT_BIT_32(16)
6090	/** SSE access that should report a \#GP instead of \#AC, unless MXCSR.MM=1
6091	* when it works like normal \#AC. Always used with IEM_MEMMAP_F_ALIGN_GP. */
6092	#define IEM_MEMMAP_F_ALIGN_SSE RT_BIT_32(17)
6093	/** If \#AC is applicable, raise it. Always used with IEM_MEMMAP_F_ALIGN_GP.
6094	* Users include FXSAVE & FXRSTOR. */
6095	#define IEM_MEMMAP_F_ALIGN_GP_OR_AC RT_BIT_32(18)
6096
6097	VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void *ppvMem, uint8_t pbUnmapInfo, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
6098	uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
6099	VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
6100	#ifndef IN_RING3
6101	VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
6102	#endif
6103	void iemMemRollbackAndUnmap(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
6104	void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
6105	VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
6106	VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
6107	VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t cbAccess, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
6108
6109	void iemOpcodeFlushLight(PVMCPUCC pVCpu, uint8_t cbInstr);
6110	void iemOpcodeFlushHeavy(PVMCPUCC pVCpu, uint8_t cbInstr);
6111	#ifdef IEM_WITH_CODE_TLB
6112	void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) IEM_NOEXCEPT_MAY_LONGJMP;
6113	#else
6114	VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
6115	#endif
6116	#ifdef IEM_WITH_SETJMP
6117	uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6118	uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6119	uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6120	uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6121	#else
6122	VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
6123	VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
6124	VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
6125	VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
6126	VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
6127	VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
6128	VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
6129	VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
6130	VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
6131	VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
6132	VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
6133	#endif
6134
6135	VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6136	VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6137	VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6138	VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6139	VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6140	VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6141	VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6142	VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6143	VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6144	VBOXSTRICTRC iemMemFetchDataU128NoAc(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6145	VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6146	VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6147	VBOXSTRICTRC iemMemFetchDataU256NoAc(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6148	VBOXSTRICTRC iemMemFetchDataU256AlignedAvx(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6149	VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
6150	RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
6151	#ifdef IEM_WITH_SETJMP
6152	uint8_t iemMemFetchDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6153	uint16_t iemMemFetchDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6154	uint32_t iemMemFetchDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6155	uint32_t iemMemFetchDataU32NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6156	uint32_t iemMemFlatFetchDataU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6157	uint64_t iemMemFetchDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6158	uint64_t iemMemFetchDataU64NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6159	uint64_t iemMemFetchDataU64AlignedU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6160	void iemMemFetchDataR80SafeJmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6161	void iemMemFetchDataD80SafeJmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6162	void iemMemFetchDataU128SafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6163	void iemMemFetchDataU128NoAcSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6164	void iemMemFetchDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6165	void iemMemFetchDataU256SafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6166	void iemMemFetchDataU256NoAcSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6167	void iemMemFetchDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6168	# if 0 /* these are inlined now */
6169	uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6170	uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6171	uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6172	uint32_t iemMemFlatFetchDataU32Jmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6173	uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6174	uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6175	void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6176	void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6177	void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6178	void iemMemFetchDataU128NoAcJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6179	void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6180	void iemMemFetchDataU256NoAcJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6181	void iemMemFetchDataU256AlignedAvxJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6182	# endif
6183	void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6184	#endif
6185
6186	VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6187	VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6188	VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6189	VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6190	VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
6191
6192	VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
6193	VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
6194	VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
6195	VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
6196	VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
6197	VBOXSTRICTRC iemMemStoreDataU128NoAc(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
6198	VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
6199	VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
6200	VBOXSTRICTRC iemMemStoreDataU256NoAc(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
6201	VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
6202	VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6203	#ifdef IEM_WITH_SETJMP
6204	void iemMemStoreDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
6205	void iemMemStoreDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
6206	void iemMemStoreDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
6207	void iemMemStoreDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
6208	void iemMemStoreDataU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
6209	void iemMemStoreDataU128NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U pu128Value) IEM_NOEXCEPT_MAY_LONGJMP;
6210	void iemMemStoreDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U pu128Value) IEM_NOEXCEPT_MAY_LONGJMP;
6211	void iemMemStoreDataU256SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
6212	void iemMemStoreDataU256NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
6213	void iemMemStoreDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
6214	void iemMemStoreDataR80SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTFLOAT80U pr80Value) IEM_NOEXCEPT_MAY_LONGJMP;
6215	void iemMemStoreDataD80SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTPBCD80U pd80Value) IEM_NOEXCEPT_MAY_LONGJMP;
6216	#if 0
6217	void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
6218	void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
6219	void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
6220	void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
6221	void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
6222	void iemMemStoreDataNoAcU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
6223	void iemMemStoreDataU256NoAcJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
6224	void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
6225	#endif
6226	void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
6227	void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
6228	#endif
6229
6230	#ifdef IEM_WITH_SETJMP
6231	uint8_t iemMemMapDataU8RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6232	uint8_t iemMemMapDataU8AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6233	uint8_t iemMemMapDataU8WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6234	uint8_t const iemMemMapDataU8RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6235	uint16_t iemMemMapDataU16RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6236	uint16_t iemMemMapDataU16AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6237	uint16_t iemMemMapDataU16WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6238	uint16_t const iemMemMapDataU16RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6239	uint32_t iemMemMapDataU32RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6240	uint32_t iemMemMapDataU32AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6241	uint32_t iemMemMapDataU32WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6242	uint32_t const iemMemMapDataU32RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6243	uint64_t iemMemMapDataU64RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6244	uint64_t iemMemMapDataU64AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6245	uint64_t iemMemMapDataU64WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6246	uint64_t const iemMemMapDataU64RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6247	PRTFLOAT80U iemMemMapDataR80RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6248	PRTFLOAT80U iemMemMapDataR80WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6249	PCRTFLOAT80U iemMemMapDataR80RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6250	PRTPBCD80U iemMemMapDataD80RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6251	PRTPBCD80U iemMemMapDataD80WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6252	PCRTPBCD80U iemMemMapDataD80RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6253	PRTUINT128U iemMemMapDataU128RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6254	PRTUINT128U iemMemMapDataU128AtSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6255	PRTUINT128U iemMemMapDataU128WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6256	PCRTUINT128U iemMemMapDataU128RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6257
6258	void iemMemCommitAndUnmapJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
6259	void iemMemCommitAndUnmapRwSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
6260	void iemMemCommitAndUnmapAtSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
6261	void iemMemCommitAndUnmapWoSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
6262	void iemMemCommitAndUnmapRoSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
6263	void iemMemRollbackAndUnmapWoSafe(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
6264	#endif
6265
6266	VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
6267	void *ppvMem, uint8_t pbUnmapInfo, uint64_t *puNewRsp) RT_NOEXCEPT;
6268	VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, uint8_t bUnmapInfo, uint64_t uNewRsp) RT_NOEXCEPT;
6269	VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
6270	VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
6271	VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
6272	VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6273	VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6274	VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6275	VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
6276	VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
6277	void const *ppvMem, uint8_t pbUnmapInfo, uint64_t *puNewRsp) RT_NOEXCEPT;
6278	VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t off, size_t cbMem,
6279	void const *ppvMem, uint8_t pbUnmapInfo, uint64_t uCurNewRsp) RT_NOEXCEPT;
6280	VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
6281	VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
6282	VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
6283	VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
6284	VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6285	VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6286	VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6287
6288	#ifdef IEM_WITH_SETJMP
6289	void iemMemStackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6290	void iemMemStackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6291	void iemMemStackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6292	void iemMemStackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6293	void iemMemStackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6294	void iemMemStackPopGRegU32SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6295	void iemMemStackPopGRegU64SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6296
6297	void iemMemFlat32StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6298	void iemMemFlat32StackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6299	void iemMemFlat32StackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6300	void iemMemFlat32StackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6301	void iemMemFlat32StackPopGRegU32SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6302
6303	void iemMemFlat64StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6304	void iemMemFlat64StackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6305	void iemMemFlat64StackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6306	void iemMemFlat64StackPopGRegU64SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6307
6308	void iemMemStoreStackU16SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6309	void iemMemStoreStackU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6310	void iemMemStoreStackU32SRegSafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6311	void iemMemStoreStackU64SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6312
6313	uint16_t iemMemFetchStackU16SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6314	uint32_t iemMemFetchStackU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6315	uint64_t iemMemFetchStackU64SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6316
6317	#endif
6318
6319	/** @} */
6320
6321	/** @name IEMAllCImpl.cpp
6322	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
6323	* @{ */
6324	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem16, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6325	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem32, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6326	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem64, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6327	IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
6328	IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
6329	IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
6330	IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
6331	IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
6332	IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
6333	IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
6334	IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
6335	typedef IEM_CIMPL_DECL_TYPE_3(FNIEMCIMPLFARBRANCH, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
6336	typedef FNIEMCIMPLFARBRANCH *PFNIEMCIMPLFARBRANCH;
6337	IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
6338	IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
6339	IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
6340	IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
6341	IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
6342	IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
6343	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
6344	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
6345	IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
6346	IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
6347	IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
6348	IEM_CIMPL_PROTO_0(iemCImpl_syscall);
6349	IEM_CIMPL_PROTO_1(iemCImpl_sysret, IEMMODE, enmEffOpSize);
6350	IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
6351	IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
6352	IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
6353	IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
6354	IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
6355	IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
6356	IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
6357	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
6358	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
6359	IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
6360	IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6361	IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
6362	IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6363	IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
6364	IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
6365	IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6366	IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
6367	IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
6368	IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6369	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
6370	IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
6371	IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6372	IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
6373	IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
6374	IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
6375	IEM_CIMPL_PROTO_0(iemCImpl_clts);
6376	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
6377	IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
6378	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
6379	IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
6380	IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
6381	IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
6382	IEM_CIMPL_PROTO_0(iemCImpl_invd);
6383	IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
6384	IEM_CIMPL_PROTO_0(iemCImpl_rsm);
6385	IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
6386	IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
6387	IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
6388	IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
6389	IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
6390	IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
6391	IEM_CIMPL_PROTO_2(iemCImpl_in_eAX_DX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
6392	IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
6393	IEM_CIMPL_PROTO_2(iemCImpl_out_DX_eAX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
6394	IEM_CIMPL_PROTO_0(iemCImpl_cli);
6395	IEM_CIMPL_PROTO_0(iemCImpl_sti);
6396	IEM_CIMPL_PROTO_0(iemCImpl_hlt);
6397	IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
6398	IEM_CIMPL_PROTO_0(iemCImpl_mwait);
6399	IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
6400	IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
6401	IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
6402	IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
6403	IEM_CIMPL_PROTO_0(iemCImpl_daa);
6404	IEM_CIMPL_PROTO_0(iemCImpl_das);
6405	IEM_CIMPL_PROTO_0(iemCImpl_aaa);
6406	IEM_CIMPL_PROTO_0(iemCImpl_aas);
6407	IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
6408	IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
6409	IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
6410	IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
6411	IEM_CIMPL_PROTO_5(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
6412	PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags, uint8_t, bUnmapInfo);
6413	IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6414	IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
6415	IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
6416	IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
6417	IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
6418	IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
6419	IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6420	IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6421	IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6422	IEM_CIMPL_PROTO_2(iemCImpl_vldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6423	IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6424	IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6425	IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6426	IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6427	IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
6428	IEM_CIMPL_PROTO_2(iemCImpl_fxch_underflow, uint8_t, iStReg, uint16_t, uFpuOpcode);
6429	IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, bool, fUCmp, uint32_t, uPopAndFpuOpcode);
6430	IEM_CIMPL_PROTO_2(iemCImpl_rdseed, uint8_t, iReg, IEMMODE, enmEffOpSize);
6431	IEM_CIMPL_PROTO_2(iemCImpl_rdrand, uint8_t, iReg, IEMMODE, enmEffOpSize);
6432	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6433	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6434	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6435	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6436	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6437	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6438	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6439	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6440	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6441	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6442	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6443	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6444	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6445	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6446	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6447	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6448
6449	/** @} */
6450
6451	/** @name IEMAllCImplStrInstr.cpp.h
6452	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
6453	* -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
6454	* @{ */
6455	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
6456	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
6457	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
6458	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
6459	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
6460	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
6461	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
6462	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
6463	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
6464	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6465	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6466
6467	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
6468	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
6469	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
6470	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
6471	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
6472	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
6473	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
6474	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
6475	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
6476	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6477	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6478
6479	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
6480	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
6481	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
6482	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
6483	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
6484	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
6485	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
6486	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
6487	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
6488	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6489	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6490
6491
6492	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
6493	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
6494	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
6495	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
6496	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
6497	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
6498	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
6499	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
6500	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
6501	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6502	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6503
6504	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
6505	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
6506	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
6507	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
6508	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
6509	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
6510	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
6511	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
6512	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
6513	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6514	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6515
6516	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
6517	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
6518	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
6519	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
6520	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
6521	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
6522	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
6523	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
6524	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
6525	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6526	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6527
6528	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
6529	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
6530	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
6531	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
6532	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
6533	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
6534	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
6535	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
6536	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
6537	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6538	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6539
6540
6541	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
6542	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
6543	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
6544	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
6545	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
6546	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
6547	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
6548	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
6549	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
6550	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6551	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6552
6553	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
6554	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
6555	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
6556	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
6557	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
6558	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
6559	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
6560	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
6561	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
6562	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6563	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6564
6565	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
6566	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
6567	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
6568	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
6569	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
6570	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
6571	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
6572	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
6573	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
6574	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6575	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6576
6577	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
6578	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
6579	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
6580	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
6581	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
6582	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
6583	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
6584	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
6585	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
6586	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6587	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6588	/** @} */
6589
6590	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6591	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
6592	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
6593	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
6594	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
6595	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
6596	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
6597	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALKFAST pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
6598	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
6599	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
6600	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
6601	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
6602	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
6603	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
6604	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6605	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6606	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6607	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6608	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6609	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6610	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
6611	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
6612	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
6613	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
6614	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
6615	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
6616	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
6617	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
6618	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
6619	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
6620	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
6621	IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
6622	IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
6623	IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
6624	IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
6625	IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6626	IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6627	IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6628	IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
6629	IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
6630	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
6631	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint64_t *, pu32Dst, uint32_t, u32VmcsField);
6632	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
6633	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
6634	IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
6635	IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
6636	IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
6637	#endif
6638
6639	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
6640	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
6641	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
6642	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
6643	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
6644	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite, uint8_t cbInstr) RT_NOEXCEPT;
6645	IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
6646	IEM_CIMPL_PROTO_0(iemCImpl_vmload);
6647	IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
6648	IEM_CIMPL_PROTO_0(iemCImpl_clgi);
6649	IEM_CIMPL_PROTO_0(iemCImpl_stgi);
6650	IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
6651	IEM_CIMPL_PROTO_0(iemCImpl_skinit);
6652	IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
6653	#endif
6654
6655	IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
6656	IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
6657	IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
6658
6659	extern const PFNIEMOP g_apfnIemInterpretOnlyOneByteMap[256];
6660	extern const PFNIEMOP g_apfnIemInterpretOnlyTwoByteMap[1024];
6661	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f3a[1024];
6662	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f38[1024];
6663	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap1[1024];
6664	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap2[1024];
6665	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap3[1024];
6666
6667	/*
6668	* Recompiler related stuff.
6669	*/
6670	extern const PFNIEMOP g_apfnIemThreadedRecompilerOneByteMap[256];
6671	extern const PFNIEMOP g_apfnIemThreadedRecompilerTwoByteMap[1024];
6672	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f3a[1024];
6673	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f38[1024];
6674	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap1[1024];
6675	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap2[1024];
6676	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap3[1024];
6677
6678	DECLCALLBACK(int) iemTbInit(PVMCC pVM, uint32_t cInitialTbs, uint32_t cMaxTbs,
6679	uint64_t cbInitialExec, uint64_t cbMaxExec, uint32_t cbChunkExec);
6680	void iemThreadedTbObsolete(PVMCPUCC pVCpu, PIEMTB pTb, bool fSafeToFree);
6681	DECLHIDDEN(void) iemTbAllocatorFree(PVMCPUCC pVCpu, PIEMTB pTb);
6682	void iemTbAllocatorProcessDelayedFrees(PVMCPUCC pVCpu, PIEMTBALLOCATOR pTbAllocator);
6683	void iemTbAllocatorFreeupNativeSpace(PVMCPUCC pVCpu, uint32_t cNeededInstrs);
6684	DECLHIDDEN(const char ) iemTbFlagsToString(uint32_t fFlags, char pszBuf, size_t cbBuf) RT_NOEXCEPT;
6685	DECLHIDDEN(void) iemThreadedDisassembleTb(PCIEMTB pTb, PCDBGFINFOHLP pHlp) RT_NOEXCEPT;
6686
6687
6688	/** @todo FNIEMTHREADEDFUNC and friends may need more work... */
6689	#if defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
6690	typedef VBOXSTRICTRC /__attribute__((__nothrow__))/ FNIEMTHREADEDFUNC(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
6691	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
6692	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
6693	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
6694	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
6695	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
6696
6697	#else
6698	typedef VBOXSTRICTRC (FNIEMTHREADEDFUNC)(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
6699	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
6700	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
6701	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
6702	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
6703	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
6704	#endif
6705
6706
6707	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_Nop);
6708	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_LogCpuState);
6709
6710	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_DeferToCImpl0);
6711
6712	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckIrq);
6713	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckMode);
6714	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckHwInstrBps);
6715	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLim);
6716
6717	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodes);
6718	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodes);
6719	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesConsiderCsLim);
6720
6721	/* Branching: */
6722	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndPcAndOpcodes);
6723	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodes);
6724	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodesConsiderCsLim);
6725
6726	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesLoadingTlb);
6727	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlb);
6728	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlbConsiderCsLim);
6729
6730	/* Natural page crossing: */
6731	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesAcrossPageLoadingTlb);
6732	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlb);
6733	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlbConsiderCsLim);
6734
6735	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNextPageLoadingTlb);
6736	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlb);
6737	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlbConsiderCsLim);
6738
6739	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNewPageLoadingTlb);
6740	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlb);
6741	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlbConsiderCsLim);
6742
6743	bool iemThreadedCompileEmitIrqCheckBefore(PVMCPUCC pVCpu, PIEMTB pTb);
6744	bool iemThreadedCompileBeginEmitCallsComplications(PVMCPUCC pVCpu, PIEMTB pTb);
6745
6746	/* Native recompiler public bits: */
6747
6748	DECLHIDDEN(PIEMTB) iemNativeRecompile(PVMCPUCC pVCpu, PIEMTB pTb) RT_NOEXCEPT;
6749	DECLHIDDEN(void) iemNativeDisassembleTb(PVMCPU pVCpu, PCIEMTB pTb, PCDBGFINFOHLP pHlp) RT_NOEXCEPT;
6750	int iemExecMemAllocatorInit(PVMCPU pVCpu, uint64_t cbMax, uint64_t cbInitial, uint32_t cbChunk) RT_NOEXCEPT;
6751	DECLHIDDEN(PIEMNATIVEINSTR) iemExecMemAllocatorAlloc(PVMCPU pVCpu, uint32_t cbReq, PIEMTB pTb, PIEMNATIVEINSTR *ppaExec,
6752	struct IEMNATIVEPERCHUNKCTX const **ppChunkCtx) RT_NOEXCEPT;
6753	DECLHIDDEN(PIEMNATIVEINSTR) iemExecMemAllocatorAllocFromChunk(PVMCPU pVCpu, uint32_t idxChunk, uint32_t cbReq,
6754	PIEMNATIVEINSTR *ppaExec);
6755	DECLHIDDEN(void) iemExecMemAllocatorReadyForUse(PVMCPUCC pVCpu, void *pv, size_t cb) RT_NOEXCEPT;
6756	void iemExecMemAllocatorFree(PVMCPU pVCpu, void *pv, size_t cb) RT_NOEXCEPT;
6757	DECLASM(DECL_NO_RETURN(void)) iemNativeTbLongJmp(void *pvFramePointer, int rc) RT_NOEXCEPT;
6758	DECLHIDDEN(struct IEMNATIVEPERCHUNKCTX const *) iemExecMemGetTbChunkCtx(PVMCPU pVCpu, PCIEMTB pTb);
6759	DECLHIDDEN(struct IEMNATIVEPERCHUNKCTX const *) iemNativeRecompileAttachExecMemChunkCtx(PVMCPU pVCpu, uint32_t idxChunk);
6760
6761	#endif /* !RT_IN_ASSEMBLER - ASM-NOINC-END */
6762
6763
6764	/** @} */
6765
6766	RT_C_DECLS_END
6767
6768	/* ASM-INC: %include "IEMInternalStruct.mac" */
6769
6770	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
6771

注意: 瀏覽 TracBrowser 來幫助您使用儲存庫瀏覽器

source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 105560

以其他格式下載: