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source: vbox/trunk/src/VBox/VMM/include/HMInternal.h@ 80064

最後變更 在這個檔案從80064是 80052,由 vboxsync 提交於 6 年 前

Main: Kicking out 32-bit host support - Some HM bits using VMMSwitcher & CPUMHyper. bugref:9511
  • 屬性 svn:eol-style 設為 native
  • 屬性 svn:keywords 設為 Id Revision
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1/* $Id: HMInternal.h 80052 2019-07-29 20:36:52Z vboxsync $ */
2/** @file
3 * HM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.alldomusa.eu.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VMM_INCLUDED_SRC_include_HMInternal_h
19#define VMM_INCLUDED_SRC_include_HMInternal_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#include <VBox/cdefs.h>
25#include <VBox/types.h>
26#include <VBox/vmm/stam.h>
27#include <VBox/dis.h>
28#include <VBox/vmm/hm.h>
29#include <VBox/vmm/hm_vmx.h>
30#include <VBox/vmm/hm_svm.h>
31#include <VBox/vmm/pgm.h>
32#include <VBox/vmm/cpum.h>
33#include <VBox/vmm/trpm.h>
34#include <iprt/memobj.h>
35#include <iprt/cpuset.h>
36#include <iprt/mp.h>
37#include <iprt/avl.h>
38#include <iprt/string.h>
39
40#if HC_ARCH_BITS == 32 && defined(RT_OS_DARWIN)
41# error "32-bit darwin is no longer supported. Go back to 4.3 or earlier!"
42#endif
43
44#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_64_BITS_GUESTS)
45/* Enable 64 bits guest support. */
46# define VBOX_ENABLE_64_BITS_GUESTS
47#endif
48
49#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
50# define VMX_USE_CACHED_VMCS_ACCESSES
51#endif
52
53/** @def HM_PROFILE_EXIT_DISPATCH
54 * Enables profiling of the VM exit handler dispatching. */
55#if 0 || defined(DOXYGEN_RUNNING)
56# define HM_PROFILE_EXIT_DISPATCH
57#endif
58
59RT_C_DECLS_BEGIN
60
61
62/** @defgroup grp_hm_int Internal
63 * @ingroup grp_hm
64 * @internal
65 * @{
66 */
67
68/** @name HM_CHANGED_XXX
69 * HM CPU-context changed flags.
70 *
71 * These flags are used to keep track of which registers and state has been
72 * modified since they were imported back into the guest-CPU context.
73 *
74 * @{
75 */
76#define HM_CHANGED_HOST_CONTEXT UINT64_C(0x0000000000000001)
77#define HM_CHANGED_GUEST_RIP UINT64_C(0x0000000000000004)
78#define HM_CHANGED_GUEST_RFLAGS UINT64_C(0x0000000000000008)
79
80#define HM_CHANGED_GUEST_RAX UINT64_C(0x0000000000000010)
81#define HM_CHANGED_GUEST_RCX UINT64_C(0x0000000000000020)
82#define HM_CHANGED_GUEST_RDX UINT64_C(0x0000000000000040)
83#define HM_CHANGED_GUEST_RBX UINT64_C(0x0000000000000080)
84#define HM_CHANGED_GUEST_RSP UINT64_C(0x0000000000000100)
85#define HM_CHANGED_GUEST_RBP UINT64_C(0x0000000000000200)
86#define HM_CHANGED_GUEST_RSI UINT64_C(0x0000000000000400)
87#define HM_CHANGED_GUEST_RDI UINT64_C(0x0000000000000800)
88#define HM_CHANGED_GUEST_R8_R15 UINT64_C(0x0000000000001000)
89#define HM_CHANGED_GUEST_GPRS_MASK UINT64_C(0x0000000000001ff0)
90
91#define HM_CHANGED_GUEST_ES UINT64_C(0x0000000000002000)
92#define HM_CHANGED_GUEST_CS UINT64_C(0x0000000000004000)
93#define HM_CHANGED_GUEST_SS UINT64_C(0x0000000000008000)
94#define HM_CHANGED_GUEST_DS UINT64_C(0x0000000000010000)
95#define HM_CHANGED_GUEST_FS UINT64_C(0x0000000000020000)
96#define HM_CHANGED_GUEST_GS UINT64_C(0x0000000000040000)
97#define HM_CHANGED_GUEST_SREG_MASK UINT64_C(0x000000000007e000)
98
99#define HM_CHANGED_GUEST_GDTR UINT64_C(0x0000000000080000)
100#define HM_CHANGED_GUEST_IDTR UINT64_C(0x0000000000100000)
101#define HM_CHANGED_GUEST_LDTR UINT64_C(0x0000000000200000)
102#define HM_CHANGED_GUEST_TR UINT64_C(0x0000000000400000)
103#define HM_CHANGED_GUEST_TABLE_MASK UINT64_C(0x0000000000780000)
104
105#define HM_CHANGED_GUEST_CR0 UINT64_C(0x0000000000800000)
106#define HM_CHANGED_GUEST_CR2 UINT64_C(0x0000000001000000)
107#define HM_CHANGED_GUEST_CR3 UINT64_C(0x0000000002000000)
108#define HM_CHANGED_GUEST_CR4 UINT64_C(0x0000000004000000)
109#define HM_CHANGED_GUEST_CR_MASK UINT64_C(0x0000000007800000)
110
111#define HM_CHANGED_GUEST_APIC_TPR UINT64_C(0x0000000008000000)
112#define HM_CHANGED_GUEST_EFER_MSR UINT64_C(0x0000000010000000)
113
114#define HM_CHANGED_GUEST_DR0_DR3 UINT64_C(0x0000000020000000)
115#define HM_CHANGED_GUEST_DR6 UINT64_C(0x0000000040000000)
116#define HM_CHANGED_GUEST_DR7 UINT64_C(0x0000000080000000)
117#define HM_CHANGED_GUEST_DR_MASK UINT64_C(0x00000000e0000000)
118
119#define HM_CHANGED_GUEST_X87 UINT64_C(0x0000000100000000)
120#define HM_CHANGED_GUEST_SSE_AVX UINT64_C(0x0000000200000000)
121#define HM_CHANGED_GUEST_OTHER_XSAVE UINT64_C(0x0000000400000000)
122#define HM_CHANGED_GUEST_XCRx UINT64_C(0x0000000800000000)
123
124#define HM_CHANGED_GUEST_KERNEL_GS_BASE UINT64_C(0x0000001000000000)
125#define HM_CHANGED_GUEST_SYSCALL_MSRS UINT64_C(0x0000002000000000)
126#define HM_CHANGED_GUEST_SYSENTER_CS_MSR UINT64_C(0x0000004000000000)
127#define HM_CHANGED_GUEST_SYSENTER_EIP_MSR UINT64_C(0x0000008000000000)
128#define HM_CHANGED_GUEST_SYSENTER_ESP_MSR UINT64_C(0x0000010000000000)
129#define HM_CHANGED_GUEST_SYSENTER_MSR_MASK UINT64_C(0x000001c000000000)
130#define HM_CHANGED_GUEST_TSC_AUX UINT64_C(0x0000020000000000)
131#define HM_CHANGED_GUEST_OTHER_MSRS UINT64_C(0x0000040000000000)
132#define HM_CHANGED_GUEST_ALL_MSRS ( HM_CHANGED_GUEST_EFER \
133 | HM_CHANGED_GUEST_KERNEL_GS_BASE \
134 | HM_CHANGED_GUEST_SYSCALL_MSRS \
135 | HM_CHANGED_GUEST_SYSENTER_MSR_MASK \
136 | HM_CHANGED_GUEST_TSC_AUX \
137 | HM_CHANGED_GUEST_OTHER_MSRS)
138
139#define HM_CHANGED_GUEST_HWVIRT UINT64_C(0x0000080000000000)
140#define HM_CHANGED_GUEST_MASK UINT64_C(0x00000ffffffffffc)
141
142#define HM_CHANGED_KEEPER_STATE_MASK UINT64_C(0xffff000000000000)
143
144#define HM_CHANGED_VMX_XCPT_INTERCEPTS UINT64_C(0x0001000000000000)
145#define HM_CHANGED_VMX_GUEST_AUTO_MSRS UINT64_C(0x0002000000000000)
146#define HM_CHANGED_VMX_GUEST_LAZY_MSRS UINT64_C(0x0004000000000000)
147#define HM_CHANGED_VMX_ENTRY_EXIT_CTLS UINT64_C(0x0008000000000000)
148#define HM_CHANGED_VMX_MASK UINT64_C(0x000f000000000000)
149#define HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE ( HM_CHANGED_GUEST_DR_MASK \
150 | HM_CHANGED_VMX_GUEST_LAZY_MSRS)
151
152#define HM_CHANGED_SVM_XCPT_INTERCEPTS UINT64_C(0x0001000000000000)
153#define HM_CHANGED_SVM_MASK UINT64_C(0x0001000000000000)
154#define HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE HM_CHANGED_GUEST_DR_MASK
155
156#define HM_CHANGED_ALL_GUEST ( HM_CHANGED_GUEST_MASK \
157 | HM_CHANGED_KEEPER_STATE_MASK)
158
159/** Mask of what state might have changed when IEM raised an exception.
160 * This is a based on IEM_CPUMCTX_EXTRN_XCPT_MASK. */
161#define HM_CHANGED_RAISED_XCPT_MASK ( HM_CHANGED_GUEST_GPRS_MASK \
162 | HM_CHANGED_GUEST_RIP \
163 | HM_CHANGED_GUEST_RFLAGS \
164 | HM_CHANGED_GUEST_SS \
165 | HM_CHANGED_GUEST_CS \
166 | HM_CHANGED_GUEST_CR0 \
167 | HM_CHANGED_GUEST_CR3 \
168 | HM_CHANGED_GUEST_CR4 \
169 | HM_CHANGED_GUEST_APIC_TPR \
170 | HM_CHANGED_GUEST_EFER_MSR \
171 | HM_CHANGED_GUEST_DR7 \
172 | HM_CHANGED_GUEST_CR2 \
173 | HM_CHANGED_GUEST_SREG_MASK \
174 | HM_CHANGED_GUEST_TABLE_MASK)
175
176#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
177/** Mask of what state might have changed when \#VMEXIT is emulated. */
178# define HM_CHANGED_SVM_VMEXIT_MASK ( HM_CHANGED_GUEST_RSP \
179 | HM_CHANGED_GUEST_RAX \
180 | HM_CHANGED_GUEST_RIP \
181 | HM_CHANGED_GUEST_RFLAGS \
182 | HM_CHANGED_GUEST_CS \
183 | HM_CHANGED_GUEST_SS \
184 | HM_CHANGED_GUEST_DS \
185 | HM_CHANGED_GUEST_ES \
186 | HM_CHANGED_GUEST_GDTR \
187 | HM_CHANGED_GUEST_IDTR \
188 | HM_CHANGED_GUEST_CR_MASK \
189 | HM_CHANGED_GUEST_EFER_MSR \
190 | HM_CHANGED_GUEST_DR6 \
191 | HM_CHANGED_GUEST_DR7 \
192 | HM_CHANGED_GUEST_OTHER_MSRS \
193 | HM_CHANGED_GUEST_HWVIRT \
194 | HM_CHANGED_SVM_MASK \
195 | HM_CHANGED_GUEST_APIC_TPR)
196
197/** Mask of what state might have changed when VMRUN is emulated. */
198# define HM_CHANGED_SVM_VMRUN_MASK HM_CHANGED_SVM_VMEXIT_MASK
199#endif
200#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
201/** Mask of what state might have changed when VM-exit is emulated.
202 *
203 * This is currently unused, but keeping it here in case we can get away a bit more
204 * fine-grained state handling.
205 *
206 * @note Update IEM_CPUMCTX_EXTRN_VMX_VMEXIT_MASK when this changes. */
207# define HM_CHANGED_VMX_VMEXIT_MASK ( HM_CHANGED_GUEST_CR0 | HM_CHANGED_GUEST_CR3 | HM_CHANGED_GUEST_CR4 \
208 | HM_CHANGED_GUEST_DR7 | HM_CHANGED_GUEST_DR6 \
209 | HM_CHANGED_GUEST_EFER_MSR \
210 | HM_CHANGED_GUEST_SYSENTER_MSR_MASK \
211 | HM_CHANGED_GUEST_OTHER_MSRS /* for PAT MSR */ \
212 | HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RSP | HM_CHANGED_GUEST_RFLAGS \
213 | HM_CHANGED_GUEST_SREG_MASK \
214 | HM_CHANGED_GUEST_TR \
215 | HM_CHANGED_GUEST_LDTR | HM_CHANGED_GUEST_GDTR | HM_CHANGED_GUEST_IDTR \
216 | HM_CHANGED_GUEST_HWVIRT )
217#endif
218/** @} */
219
220/** Maximum number of exit reason statistics counters. */
221#define MAX_EXITREASON_STAT 0x100
222#define MASK_EXITREASON_STAT 0xff
223#define MASK_INJECT_IRQ_STAT 0xff
224
225/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
226#define HM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
227/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
228#define HM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2 * PAGE_SIZE + 1)
229/** Total guest mapped memory needed. */
230#define HM_VTX_TOTAL_DEVHEAP_MEM (HM_EPT_IDENTITY_PG_TABLE_SIZE + HM_VTX_TSS_SIZE)
231
232
233/** @name Macros for enabling and disabling preemption.
234 * These are really just for hiding the RTTHREADPREEMPTSTATE and asserting that
235 * preemption has already been disabled when there is no context hook.
236 * @{ */
237#ifdef VBOX_STRICT
238# define HM_DISABLE_PREEMPT(a_pVCpu) \
239 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
240 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD) || VMMR0ThreadCtxHookIsEnabled((a_pVCpu))); \
241 RTThreadPreemptDisable(&PreemptStateInternal)
242#else
243# define HM_DISABLE_PREEMPT(a_pVCpu) \
244 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
245 RTThreadPreemptDisable(&PreemptStateInternal)
246#endif /* VBOX_STRICT */
247#define HM_RESTORE_PREEMPT() do { RTThreadPreemptRestore(&PreemptStateInternal); } while(0)
248/** @} */
249
250
251/** @name HM saved state versions.
252 * @{
253 */
254#define HM_SAVED_STATE_VERSION HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
255#define HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT 6
256#define HM_SAVED_STATE_VERSION_TPR_PATCHING 5
257#define HM_SAVED_STATE_VERSION_NO_TPR_PATCHING 4
258#define HM_SAVED_STATE_VERSION_2_0_X 3
259/** @} */
260
261
262/**
263 * HM physical (host) CPU information.
264 */
265typedef struct HMPHYSCPU
266{
267 /** The CPU ID. */
268 RTCPUID idCpu;
269 /** The VM_HSAVE_AREA (AMD-V) / VMXON region (Intel) memory backing. */
270 RTR0MEMOBJ hMemObj;
271 /** The physical address of the first page in hMemObj (it's a
272 * physcially contigous allocation if it spans multiple pages). */
273 RTHCPHYS HCPhysMemObj;
274 /** The address of the memory (for pfnEnable). */
275 void *pvMemObj;
276 /** Current ASID (AMD-V) / VPID (Intel). */
277 uint32_t uCurrentAsid;
278 /** TLB flush count. */
279 uint32_t cTlbFlushes;
280 /** Whether to flush each new ASID/VPID before use. */
281 bool fFlushAsidBeforeUse;
282 /** Configured for VT-x or AMD-V. */
283 bool fConfigured;
284 /** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
285 bool fIgnoreAMDVInUseError;
286 /** In use by our code. (for power suspend) */
287 bool volatile fInUse;
288#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
289 /** Nested-guest union (put data common to SVM/VMX outside the union). */
290 union
291 {
292 /** Nested-guest SVM data. */
293 struct
294 {
295 /** The active nested-guest MSR permission bitmap memory backing. */
296 RTR0MEMOBJ hNstGstMsrpm;
297 /** The physical address of the first page in hNstGstMsrpm (physcially
298 * contiguous allocation). */
299 RTHCPHYS HCPhysNstGstMsrpm;
300 /** The address of the active nested-guest MSRPM. */
301 void *pvNstGstMsrpm;
302 } svm;
303 /** @todo Nested-VMX. */
304 } n;
305#endif
306} HMPHYSCPU;
307/** Pointer to HMPHYSCPU struct. */
308typedef HMPHYSCPU *PHMPHYSCPU;
309/** Pointer to a const HMPHYSCPU struct. */
310typedef const HMPHYSCPU *PCHMPHYSCPU;
311
312/**
313 * TPR-instruction type.
314 */
315typedef enum
316{
317 HMTPRINSTR_INVALID,
318 HMTPRINSTR_READ,
319 HMTPRINSTR_READ_SHR4,
320 HMTPRINSTR_WRITE_REG,
321 HMTPRINSTR_WRITE_IMM,
322 HMTPRINSTR_JUMP_REPLACEMENT,
323 /** The usual 32-bit paranoia. */
324 HMTPRINSTR_32BIT_HACK = 0x7fffffff
325} HMTPRINSTR;
326
327/**
328 * TPR patch information.
329 */
330typedef struct
331{
332 /** The key is the address of patched instruction. (32 bits GC ptr) */
333 AVLOU32NODECORE Core;
334 /** Original opcode. */
335 uint8_t aOpcode[16];
336 /** Instruction size. */
337 uint32_t cbOp;
338 /** Replacement opcode. */
339 uint8_t aNewOpcode[16];
340 /** Replacement instruction size. */
341 uint32_t cbNewOp;
342 /** Instruction type. */
343 HMTPRINSTR enmType;
344 /** Source operand. */
345 uint32_t uSrcOperand;
346 /** Destination operand. */
347 uint32_t uDstOperand;
348 /** Number of times the instruction caused a fault. */
349 uint32_t cFaults;
350 /** Patch address of the jump replacement. */
351 RTGCPTR32 pJumpTarget;
352} HMTPRPATCH;
353/** Pointer to HMTPRPATCH. */
354typedef HMTPRPATCH *PHMTPRPATCH;
355/** Pointer to a const HMTPRPATCH. */
356typedef const HMTPRPATCH *PCHMTPRPATCH;
357
358
359/**
360 * Makes a HMEXITSTAT::uKey value from a program counter and an exit code.
361 *
362 * @returns 64-bit key
363 * @param a_uPC The RIP + CS.BASE value of the exit.
364 * @param a_uExit The exit code.
365 * @todo Add CPL?
366 */
367#define HMEXITSTAT_MAKE_KEY(a_uPC, a_uExit) (((a_uPC) & UINT64_C(0x0000ffffffffffff)) | (uint64_t)(a_uExit) << 48)
368
369typedef struct HMEXITINFO
370{
371 /** See HMEXITSTAT_MAKE_KEY(). */
372 uint64_t uKey;
373 /** Number of recent hits (depreciates with time). */
374 uint32_t volatile cHits;
375 /** The age + lock. */
376 uint16_t volatile uAge;
377 /** Action or action table index. */
378 uint16_t iAction;
379} HMEXITINFO;
380AssertCompileSize(HMEXITINFO, 16); /* Lots of these guys, so don't add any unnecessary stuff! */
381
382typedef struct HMEXITHISTORY
383{
384 /** The exit timestamp. */
385 uint64_t uTscExit;
386 /** The index of the corresponding HMEXITINFO entry.
387 * UINT32_MAX if none (too many collisions, race, whatever). */
388 uint32_t iExitInfo;
389 /** Figure out later, needed for padding now. */
390 uint32_t uSomeClueOrSomething;
391} HMEXITHISTORY;
392
393/**
394 * Switcher function, HC to the special 64-bit RC.
395 *
396 * @param pVM The cross context VM structure.
397 * @param offCpumVCpu Offset from pVM->cpum to pVM->aCpus[idCpu].cpum.
398 * @returns Return code indicating the action to take.
399 */
400typedef DECLCALLBACK(int) FNHMSWITCHERHC(PVM pVM, uint32_t offCpumVCpu);
401/** Pointer to switcher function. */
402typedef FNHMSWITCHERHC *PFNHMSWITCHERHC;
403
404/** @def HM_UNION_NM
405 * For compilers (like DTrace) that does not grok nameless unions, we have a
406 * little hack to make them palatable.
407 */
408/** @def HM_STRUCT_NM
409 * For compilers (like DTrace) that does not grok nameless structs (it is
410 * non-standard C++), we have a little hack to make them palatable.
411 */
412#ifdef VBOX_FOR_DTRACE_LIB
413# define HM_UNION_NM(a_Nm) a_Nm
414# define HM_STRUCT_NM(a_Nm) a_Nm
415#elif defined(IPRT_WITHOUT_NAMED_UNIONS_AND_STRUCTS)
416# define HM_UNION_NM(a_Nm) a_Nm
417# define HM_STRUCT_NM(a_Nm) a_Nm
418#else
419# define HM_UNION_NM(a_Nm)
420# define HM_STRUCT_NM(a_Nm)
421#endif
422
423/**
424 * HM event.
425 *
426 * VT-x and AMD-V common event injection structure.
427 */
428typedef struct HMEVENT
429{
430 /** Whether the event is pending. */
431 uint32_t fPending;
432 /** The error-code associated with the event. */
433 uint32_t u32ErrCode;
434 /** The length of the instruction in bytes (only relevant for software
435 * interrupts or software exceptions). */
436 uint32_t cbInstr;
437 /** Alignment. */
438 uint32_t u32Padding;
439 /** The encoded event (VM-entry interruption-information for VT-x or EVENTINJ
440 * for SVM). */
441 uint64_t u64IntInfo;
442 /** Guest virtual address if this is a page-fault event. */
443 RTGCUINTPTR GCPtrFaultAddress;
444} HMEVENT;
445/** Pointer to a HMEVENT struct. */
446typedef HMEVENT *PHMEVENT;
447/** Pointer to a const HMEVENT struct. */
448typedef const HMEVENT *PCHMEVENT;
449AssertCompileSizeAlignment(HMEVENT, 8);
450
451/**
452 * HM VM Instance data.
453 * Changes to this must checked against the padding of the hm union in VM!
454 */
455typedef struct HM
456{
457 /** Set when we've initialized VMX or SVM. */
458 bool fInitialized;
459 /** Set if nested paging is enabled. */
460 bool fNestedPaging;
461 /** Set if nested paging is allowed. */
462 bool fAllowNestedPaging;
463 /** Set if large pages are enabled (requires nested paging). */
464 bool fLargePages;
465 /** Set if we can support 64-bit guests or not. */
466 bool fAllow64BitGuests;
467 /** Set when TPR patching is allowed. */
468 bool fTprPatchingAllowed;
469 /** Set when we initialize VT-x or AMD-V once for all CPUs. */
470 bool fGlobalInit;
471 /** Set when TPR patching is active. */
472 bool fTPRPatchingActive;
473 /** Set when the debug facility has breakpoints/events enabled that requires
474 * us to use the debug execution loop in ring-0. */
475 bool fUseDebugLoop;
476 /** Set if hardware APIC virtualization is enabled. */
477 bool fVirtApicRegs;
478 /** Set if posted interrupt processing is enabled. */
479 bool fPostedIntrs;
480 /** Set if indirect branch prediction barrier on VM exit. */
481 bool fIbpbOnVmExit;
482 /** Set if indirect branch prediction barrier on VM entry. */
483 bool fIbpbOnVmEntry;
484 /** Set if level 1 data cache should be flushed on VM entry. */
485 bool fL1dFlushOnVmEntry;
486 /** Set if level 1 data cache should be flushed on EMT scheduling. */
487 bool fL1dFlushOnSched;
488 /** Set if host manages speculation control settings. */
489 bool fSpecCtrlByHost;
490 /** Set if MDS related buffers should be cleared on VM entry. */
491 bool fMdsClearOnVmEntry;
492 /** Set if MDS related buffers should be cleared on EMT scheduling. */
493 bool fMdsClearOnSched;
494 /** Alignment padding. */
495 bool afPaddingMinus1[6];
496
497 /** Maximum ASID allowed. */
498 uint32_t uMaxAsid;
499 /** The maximum number of resumes loops allowed in ring-0 (safety precaution).
500 * This number is set much higher when RTThreadPreemptIsPending is reliable. */
501 uint32_t cMaxResumeLoops;
502
503 /** Host kernel flags that HM might need to know (SUPKERNELFEATURES_XXX). */
504 uint32_t fHostKernelFeatures;
505
506 /** Size of the guest patch memory block. */
507 uint32_t cbGuestPatchMem;
508 /** Guest allocated memory for patching purposes. */
509 RTGCPTR pGuestPatchMem;
510 /** Current free pointer inside the patch block. */
511 RTGCPTR pFreeGuestPatchMem;
512
513#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
514 /** 32 to 64 bits switcher entrypoint. */
515 R0PTRTYPE(PFNHMSWITCHERHC) pfnHost32ToGuest64R0;
516 RTR0PTR pvR0Alignment0;
517#endif
518
519 struct
520 {
521 /** Set by the ring-0 side of HM to indicate VMX is supported by the
522 * CPU. */
523 bool fSupported;
524 /** Set when we've enabled VMX. */
525 bool fEnabled;
526 /** Set if VPID is supported. */
527 bool fVpid;
528 /** Set if VT-x VPID is allowed. */
529 bool fAllowVpid;
530 /** Set if unrestricted guest execution is in use (real and protected mode
531 * without paging). */
532 bool fUnrestrictedGuest;
533 /** Set if unrestricted guest execution is allowed to be used. */
534 bool fAllowUnrestricted;
535 /** Set if the preemption timer is in use or not. */
536 bool fUsePreemptTimer;
537 /** The shift mask employed by the VMX-Preemption timer. */
538 uint8_t cPreemptTimerShift;
539
540 /** Virtual address of the TSS page used for real mode emulation. */
541 R3PTRTYPE(PVBOXTSS) pRealModeTSS;
542 /** Virtual address of the identity page table used for real mode and protected
543 * mode without paging emulation in EPT mode. */
544 R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
545
546 /** Physical address of the APIC-access page. */
547 RTHCPHYS HCPhysApicAccess;
548 /** R0 memory object for the APIC-access page. */
549 RTR0MEMOBJ hMemObjApicAccess;
550 /** Virtual address of the APIC-access page. */
551 R0PTRTYPE(uint8_t *) pbApicAccess;
552
553 /** Physical address of the VMREAD bitmap. */
554 RTHCPHYS HCPhysVmreadBitmap;
555 /** Ring-0 memory object for the VMREAD bitmap. */
556 RTR0MEMOBJ hMemObjVmreadBitmap;
557 /** Pointer to the VMREAD bitmap. */
558 R0PTRTYPE(void *) pvVmreadBitmap;
559
560 /** Physical address of the VMWRITE bitmap. */
561 RTHCPHYS HCPhysVmwriteBitmap;
562 /** Ring-0 memory object for the VMWRITE bitmap. */
563 RTR0MEMOBJ hMemObjVmwriteBitmap;
564 /** Pointer to the VMWRITE bitmap. */
565 R0PTRTYPE(void *) pvVmwriteBitmap;
566
567#ifdef VBOX_WITH_CRASHDUMP_MAGIC
568 /** Physical address of the crash-dump scratch area. */
569 RTHCPHYS HCPhysScratch;
570 /** Ring-0 memory object for the crash-dump scratch area. */
571 RTR0MEMOBJ hMemObjScratch;
572 /** Pointer to the crash-dump scratch bitmap. */
573 R0PTRTYPE(uint8_t *) pbScratch;
574#endif
575
576 /** Tagged-TLB flush type. */
577 VMXTLBFLUSHTYPE enmTlbFlushType;
578 /** Flush type to use for INVEPT. */
579 VMXTLBFLUSHEPT enmTlbFlushEpt;
580 /** Flush type to use for INVVPID. */
581 VMXTLBFLUSHVPID enmTlbFlushVpid;
582
583 /** Pause-loop exiting (PLE) gap in ticks. */
584 uint32_t cPleGapTicks;
585 /** Pause-loop exiting (PLE) window in ticks. */
586 uint32_t cPleWindowTicks;
587 uint32_t u32Alignment0;
588
589 /** Host CR4 value (set by ring-0 VMX init) */
590 uint64_t u64HostCr4;
591 /** Host SMM monitor control (set by ring-0 VMX init) */
592 uint64_t u64HostSmmMonitorCtl;
593 /** Host EFER value (set by ring-0 VMX init) */
594 uint64_t u64HostMsrEfer;
595 /** Whether the CPU supports VMCS fields for swapping EFER. */
596 bool fSupportsVmcsEfer;
597 /** Whether to use VMCS shadowing. */
598 bool fUseVmcsShadowing;
599 uint8_t u8Alignment2[6];
600
601 /** VMX MSR values. */
602 VMXMSRS Msrs;
603
604 /** Host-physical address for a failing VMXON instruction. */
605 RTHCPHYS HCPhysVmxEnableError;
606
607 /** Pointer to the shadow VMCS read-only fields array. */
608 R0PTRTYPE(uint32_t *) paShadowVmcsRoFields;
609 /** Pointer to the shadow VMCS read/write fields array. */
610 R0PTRTYPE(uint32_t *) paShadowVmcsFields;
611 /** Number of elements in the shadow VMCS read-only fields array. */
612 uint32_t cShadowVmcsRoFields;
613 /** Number of elements in the shadow VMCS read-write fields array. */
614 uint32_t cShadowVmcsFields;
615 } vmx;
616
617 struct
618 {
619 /** Set by the ring-0 side of HM to indicate SVM is supported by the
620 * CPU. */
621 bool fSupported;
622 /** Set when we've enabled SVM. */
623 bool fEnabled;
624 /** Set if erratum 170 affects the AMD cpu. */
625 bool fAlwaysFlushTLB;
626 /** Set when the hack to ignore VERR_SVM_IN_USE is active. */
627 bool fIgnoreInUseError;
628 /** Whether to use virtualized VMSAVE/VMLOAD feature. */
629 bool fVirtVmsaveVmload;
630 /** Whether to use virtual GIF feature. */
631 bool fVGif;
632 uint8_t u8Alignment0[2];
633
634 /** Physical address of the IO bitmap (12kb). */
635 RTHCPHYS HCPhysIOBitmap;
636 /** R0 memory object for the IO bitmap (12kb). */
637 RTR0MEMOBJ hMemObjIOBitmap;
638 /** Virtual address of the IO bitmap. */
639 R0PTRTYPE(void *) pvIOBitmap;
640
641 /* HWCR MSR (for diagnostics) */
642 uint64_t u64MsrHwcr;
643
644 /** SVM revision. */
645 uint32_t u32Rev;
646 /** SVM feature bits from cpuid 0x8000000a */
647 uint32_t u32Features;
648
649 /** Pause filter counter. */
650 uint16_t cPauseFilter;
651 /** Pause filter treshold in ticks. */
652 uint16_t cPauseFilterThresholdTicks;
653 uint32_t u32Alignment0;
654 } svm;
655
656 /**
657 * AVL tree with all patches (active or disabled) sorted by guest instruction
658 * address.
659 */
660 AVLOU32TREE PatchTree;
661 uint32_t cPatches;
662 HMTPRPATCH aPatches[64];
663
664 /** Last recorded error code during HM ring-0 init. */
665 int32_t rcInit;
666
667 /** HMR0Init was run */
668 bool fHMR0Init;
669 bool u8Alignment1[3];
670
671 STAMCOUNTER StatTprPatchSuccess;
672 STAMCOUNTER StatTprPatchFailure;
673 STAMCOUNTER StatTprReplaceSuccessCr8;
674 STAMCOUNTER StatTprReplaceSuccessVmc;
675 STAMCOUNTER StatTprReplaceFailure;
676} HM;
677/** Pointer to HM VM instance data. */
678typedef HM *PHM;
679
680AssertCompileMemberAlignment(HM, StatTprPatchSuccess, 8);
681
682/* Maximum number of cached entries. */
683#define VMX_VMCS_CACHE_MAX_ENTRY 128
684
685/**
686 * Cache of a VMCS for batch reads or writes.
687 */
688typedef struct VMXVMCSCACHE
689{
690#ifdef VBOX_WITH_CRASHDUMP_MAGIC
691 /* Magic marker for searching in crash dumps. */
692 uint8_t aMagic[16];
693 uint64_t uMagic;
694 uint64_t u64TimeEntry;
695 uint64_t u64TimeSwitch;
696 uint64_t cResume;
697 uint64_t interPD;
698 uint64_t pSwitcher;
699 uint32_t uPos;
700 uint32_t idCpu;
701#endif
702 /* CR2 is saved here for EPT syncing. */
703 uint64_t cr2;
704 struct
705 {
706 uint32_t cValidEntries;
707 uint32_t uAlignment;
708 uint32_t aField[VMX_VMCS_CACHE_MAX_ENTRY];
709 uint64_t aFieldVal[VMX_VMCS_CACHE_MAX_ENTRY];
710 } Write;
711 struct
712 {
713 uint32_t cValidEntries;
714 uint32_t uAlignment;
715 uint32_t aField[VMX_VMCS_CACHE_MAX_ENTRY];
716 uint64_t aFieldVal[VMX_VMCS_CACHE_MAX_ENTRY];
717 } Read;
718#ifdef VBOX_STRICT
719 struct
720 {
721 RTHCPHYS HCPhysCpuPage;
722 RTHCPHYS HCPhysVmcs;
723 RTGCPTR pCache;
724 RTGCPTR pCtx;
725 } TestIn;
726 struct
727 {
728 RTHCPHYS HCPhysVmcs;
729 RTGCPTR pCache;
730 RTGCPTR pCtx;
731 uint64_t eflags;
732 uint64_t cr8;
733 } TestOut;
734 struct
735 {
736 uint64_t param1;
737 uint64_t param2;
738 uint64_t param3;
739 uint64_t param4;
740 } ScratchPad;
741#endif
742} VMXVMCSCACHE;
743/** Pointer to VMXVMCSCACHE. */
744typedef VMXVMCSCACHE *PVMXVMCSCACHE;
745AssertCompileSizeAlignment(VMXVMCSCACHE, 8);
746
747/**
748 * VMX StartVM function.
749 *
750 * @returns VBox status code (no informational stuff).
751 * @param fResume Whether to use VMRESUME (true) or VMLAUNCH (false).
752 * @param pCtx The CPU register context.
753 * @param pVmcsCache The VMCS batch cache.
754 * @param pVM Pointer to the cross context VM structure.
755 * @param pVCpu Pointer to the cross context per-CPU structure.
756 */
757typedef DECLCALLBACK(int) FNHMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMXVMCSCACHE pVmcsCache, PVM pVM, PVMCPU pVCpu);
758/** Pointer to a VMX StartVM function. */
759typedef R0PTRTYPE(FNHMVMXSTARTVM *) PFNHMVMXSTARTVM;
760
761/** SVM VMRun function. */
762typedef DECLCALLBACK(int) FNHMSVMVMRUN(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
763/** Pointer to a SVM VMRun function. */
764typedef R0PTRTYPE(FNHMSVMVMRUN *) PFNHMSVMVMRUN;
765
766/**
767 * VMX VMCS information.
768 *
769 * This structure provides information maintained for and during the executing of a
770 * guest (or nested-guest) VMCS (VM control structure) using hardware-assisted VMX.
771 */
772typedef struct VMXVMCSINFO
773{
774 /** @name VMLAUNCH/VMRESUME information.
775 * @{ */
776 /** Ring-0 pointer to the hardware-assisted VMX execution function. */
777 PFNHMVMXSTARTVM pfnStartVM;
778#if HC_ARCH_BITS == 32
779 uint32_t u32Alignment0;
780#endif
781 /** @} */
782
783 /** @name VMCS and related data structures.
784 * @{ */
785 /** Host-physical address of the VMCS. */
786 RTHCPHYS HCPhysVmcs;
787 /** R0 memory object for the VMCS. */
788 RTR0MEMOBJ hMemObjVmcs;
789 /** Host-virtual address of the VMCS. */
790 R0PTRTYPE(void *) pvVmcs;
791
792 /** Host-physical address of the shadow VMCS. */
793 RTHCPHYS HCPhysShadowVmcs;
794 /** R0 memory object for the shadow VMCS. */
795 RTR0MEMOBJ hMemObjShadowVmcs;
796 /** Host-virtual address of the shadow VMCS. */
797 R0PTRTYPE(void *) pvShadowVmcs;
798
799 /** Host-physical address of the virtual APIC page. */
800 RTHCPHYS HCPhysVirtApic;
801 /** Alignment. */
802 R0PTRTYPE(void *) pvAlignment0;
803 /** Host-virtual address of the virtual-APIC page. */
804 R0PTRTYPE(uint8_t *) pbVirtApic;
805
806 /** Host-physical address of the MSR bitmap. */
807 RTHCPHYS HCPhysMsrBitmap;
808 /** R0 memory object for the MSR bitmap. */
809 RTR0MEMOBJ hMemObjMsrBitmap;
810 /** Host-virtual address of the MSR bitmap. */
811 R0PTRTYPE(void *) pvMsrBitmap;
812
813 /** Host-physical address of the VM-entry MSR-load area. */
814 RTHCPHYS HCPhysGuestMsrLoad;
815 /** R0 memory object of the VM-entry MSR-load area. */
816 RTR0MEMOBJ hMemObjGuestMsrLoad;
817 /** Host-virtual address of the VM-entry MSR-load area. */
818 R0PTRTYPE(void *) pvGuestMsrLoad;
819
820 /** Host-physical address of the VM-exit MSR-store area. */
821 RTHCPHYS HCPhysGuestMsrStore;
822 /** R0 memory object of the VM-exit MSR-store area. */
823 RTR0MEMOBJ hMemObjGuestMsrStore;
824 /** Host-virtual address of the VM-exit MSR-store area. */
825 R0PTRTYPE(void *) pvGuestMsrStore;
826
827 /** Host-physical address of the VM-exit MSR-load area. */
828 RTHCPHYS HCPhysHostMsrLoad;
829 /** R0 memory object for the VM-exit MSR-load area. */
830 RTR0MEMOBJ hMemObjHostMsrLoad;
831 /** Host-virtual address of the VM-exit MSR-load area. */
832 R0PTRTYPE(void *) pvHostMsrLoad;
833
834 /** Host-physical address of the EPTP. */
835 RTHCPHYS HCPhysEPTP;
836 /** Number of guest MSRs in the VM-entry MSR-load area. */
837 uint32_t cEntryMsrLoad;
838 /** Number of guest MSRs in the VM-exit MSR-store area. */
839 uint32_t cExitMsrStore;
840 /** Number of host MSRs in the VM-exit MSR-load area. */
841 uint32_t cExitMsrLoad;
842 /** Padding. */
843 uint32_t u32Padding0;
844 /** @} */
845
846 /** @name Auxiliary information.
847 * @{ */
848 /** The VMCS launch state, see VMX_V_VMCS_LAUNCH_STATE_XXX. */
849 uint32_t fVmcsState;
850 /** The VMCS launch state of the shadow VMCS, see VMX_V_VMCS_LAUNCH_STATE_XXX. */
851 uint32_t fShadowVmcsState;
852 /** Set if guest was executing in real mode (extra checks). */
853 bool fWasInRealMode;
854 /** Set if the guest switched to 64-bit mode on a 32-bit host. */
855 bool fSwitchedTo64on32Obsolete;
856 /** Padding. */
857 bool afPadding0[6];
858 /** The host CPU for which we have currently exported the host state. */
859 RTCPUID idHostCpu;
860 /** Padding. */
861 uint32_t u32Padding1;
862 /** @} */
863
864 /** @name Cache of execution related VMCS fields.
865 * @{ */
866 /** Pin-based VM-execution controls. */
867 uint32_t u32PinCtls;
868 /** Processor-based VM-execution controls. */
869 uint32_t u32ProcCtls;
870 /** Secondary processor-based VM-execution controls. */
871 uint32_t u32ProcCtls2;
872 /** VM-entry controls. */
873 uint32_t u32EntryCtls;
874 /** VM-exit controls. */
875 uint32_t u32ExitCtls;
876 /** Exception bitmap. */
877 uint32_t u32XcptBitmap;
878 /** CR0 guest/host mask. */
879 uint64_t u64Cr0Mask;
880 /** CR4 guest/host mask. */
881 uint64_t u64Cr4Mask;
882 /** Page-fault exception error-code mask. */
883 uint32_t u32XcptPFMask;
884 /** Page-fault exception error-code match. */
885 uint32_t u32XcptPFMatch;
886 /** TSC offset. */
887 uint64_t u64TscOffset;
888 /** VMCS link pointer. */
889 uint64_t u64VmcsLinkPtr;
890 /** @} */
891
892 /** @name Real-mode emulation state.
893 * @{ */
894 struct
895 {
896 X86DESCATTR AttrCS;
897 X86DESCATTR AttrDS;
898 X86DESCATTR AttrES;
899 X86DESCATTR AttrFS;
900 X86DESCATTR AttrGS;
901 X86DESCATTR AttrSS;
902 X86EFLAGS Eflags;
903 bool fRealOnV86Active;
904 bool afPadding1[3];
905 } RealMode;
906 /** @} */
907
908 /** Padding. */
909 uint64_t au64Padding[2];
910} VMXVMCSINFO;
911/** Pointer to a VMXVMCSINFO struct. */
912typedef VMXVMCSINFO *PVMXVMCSINFO;
913/** Pointer to a const VMXVMCSINFO struct. */
914typedef const VMXVMCSINFO *PCVMXVMCSINFO;
915AssertCompileSizeAlignment(VMXVMCSINFO, 8);
916AssertCompileMemberAlignment(VMXVMCSINFO, fVmcsState, 8);
917AssertCompileMemberAlignment(VMXVMCSINFO, u32PinCtls, 8);
918AssertCompileMemberAlignment(VMXVMCSINFO, u64VmcsLinkPtr, 8);
919
920/**
921 * HM VMCPU Instance data.
922 *
923 * Note! If you change members of this struct, make sure to check if the
924 * assembly counterpart in HMInternal.mac needs to be updated as well.
925 */
926typedef struct HMCPU
927{
928 /** Set when the TLB has been checked until we return from the world switch. */
929 bool volatile fCheckedTLBFlush;
930 /** Set if we need to flush the TLB during the world switch. */
931 bool fForceTLBFlush;
932 /** Set when we're using VT-x or AMD-V at that moment. */
933 bool fActive;
934 /** Whether we've completed the inner HM leave function. */
935 bool fLeaveDone;
936 /** Whether we're using the hyper DR7 or guest DR7. */
937 bool fUsingHyperDR7;
938 /** Set if XCR0 needs to be saved/restored when entering/exiting guest code
939 * execution. */
940 bool fLoadSaveGuestXcr0;
941
942 /** Whether we should use the debug loop because of single stepping or special
943 * debug breakpoints / events are armed. */
944 bool fUseDebugLoop;
945 /** Whether we are currently executing in the debug loop.
946 * Mainly for assertions. */
947 bool fUsingDebugLoop;
948 /** Set if we using the debug loop and wish to intercept RDTSC. */
949 bool fDebugWantRdTscExit;
950 /** Whether we're executing a single instruction. */
951 bool fSingleInstruction;
952 /** Set if we need to clear the trap flag because of single stepping. */
953 bool fClearTrapFlag;
954
955 /** Whether \#UD needs to be intercepted (required by certain GIM providers). */
956 bool fGIMTrapXcptUD;
957 /** Whether \#GP needs to be intercept for mesa driver workaround. */
958 bool fTrapXcptGpForLovelyMesaDrv;
959 uint8_t u8Alignment0[3];
960
961 /** World switch exit counter. */
962 uint32_t volatile cWorldSwitchExits;
963 /** The last CPU we were executing code on (NIL_RTCPUID for the first time). */
964 RTCPUID idLastCpu;
965 /** TLB flush count. */
966 uint32_t cTlbFlushes;
967 /** Current ASID in use by the VM. */
968 uint32_t uCurrentAsid;
969 /** An additional error code used for some gurus. */
970 uint32_t u32HMError;
971 /** The last exit-to-ring-3 reason. */
972 int32_t rcLastExitToR3;
973 /** CPU-context changed flags (see HM_CHANGED_xxx). */
974 uint64_t fCtxChanged;
975
976 union /* no tag! */
977 {
978 /** VT-x data. */
979 struct
980 {
981 /** @name Guest information.
982 * @{ */
983 /** Guest VMCS information. */
984 VMXVMCSINFO VmcsInfo;
985 /** Nested-guest VMCS information. */
986 VMXVMCSINFO VmcsInfoNstGst;
987 /** Whether the nested-guest VMCS was the last current VMCS. */
988 bool fSwitchedToNstGstVmcs;
989 /** Whether the static guest VMCS controls has been merged with the
990 * nested-guest VMCS controls. */
991 bool fMergedNstGstCtls;
992 /** Whether the nested-guest VMCS has been copied to the shadow VMCS. */
993 bool fCopiedNstGstToShadowVmcs;
994 /** Whether flushing the TLB is required due to switching to/from the
995 * nested-geust. */
996 bool fSwitchedNstGstFlushTlb;
997
998 bool fVirtApicPageLocked;
999 /** Alignment. */
1000 bool afAlignment0[3];
1001 /** Cached guest APIC-base MSR for identifying when to map the APIC-access page. */
1002 uint64_t u64GstMsrApicBase;
1003 /** VMCS cache for batched vmread/vmwrites. */
1004 VMXVMCSCACHE VmcsCache;
1005 PGMPAGEMAPLOCK PgMapLockVirtApic;
1006 /** @} */
1007
1008 /** @name Host information.
1009 * @{ */
1010 /** Host LSTAR MSR to restore lazily while leaving VT-x. */
1011 uint64_t u64HostMsrLStar;
1012 /** Host STAR MSR to restore lazily while leaving VT-x. */
1013 uint64_t u64HostMsrStar;
1014 /** Host SF_MASK MSR to restore lazily while leaving VT-x. */
1015 uint64_t u64HostMsrSfMask;
1016 /** Host KernelGS-Base MSR to restore lazily while leaving VT-x. */
1017 uint64_t u64HostMsrKernelGsBase;
1018 /** The mask of lazy MSRs swap/restore state, see VMX_LAZY_MSRS_XXX. */
1019 uint32_t fLazyMsrs;
1020 /** Whether the host MSR values are up-to-date in the auto-load/store MSR area. */
1021 bool fUpdatedHostAutoMsrs;
1022 /** Alignment. */
1023 uint8_t au8Alignment0[3];
1024 /** Which host-state bits to restore before being preempted. */
1025 uint32_t fRestoreHostFlags;
1026 /** Alignment. */
1027 uint32_t u32Alignment0;
1028 /** The host-state restoration structure. */
1029 VMXRESTOREHOST RestoreHost;
1030 /** @} */
1031
1032 /** @name Error reporting and diagnostics.
1033 * @{ */
1034 /** VT-x error-reporting (mainly for ring-3 propagation). */
1035 struct
1036 {
1037 RTHCPHYS HCPhysCurrentVmcs;
1038 uint32_t u32VmcsRev;
1039 uint32_t u32InstrError;
1040 uint32_t u32ExitReason;
1041 uint32_t u32Alignment0;
1042 RTCPUID idEnteredCpu;
1043 RTCPUID idCurrentCpu;
1044 } LastError;
1045 /** @} */
1046 } vmx;
1047
1048 /** SVM data. */
1049 struct
1050 {
1051 /** Ring 0 handlers for VT-x. */
1052 PFNHMSVMVMRUN pfnVMRun;
1053#if HC_ARCH_BITS == 32
1054 uint32_t u32Alignment0;
1055#endif
1056
1057 /** Physical address of the host VMCB which holds additional host-state. */
1058 RTHCPHYS HCPhysVmcbHost;
1059 /** R0 memory object for the host VMCB which holds additional host-state. */
1060 RTR0MEMOBJ hMemObjVmcbHost;
1061 /** Padding. */
1062 R0PTRTYPE(void *) pvPadding;
1063
1064 /** Physical address of the guest VMCB. */
1065 RTHCPHYS HCPhysVmcb;
1066 /** R0 memory object for the guest VMCB. */
1067 RTR0MEMOBJ hMemObjVmcb;
1068 /** Pointer to the guest VMCB. */
1069 R0PTRTYPE(PSVMVMCB) pVmcb;
1070
1071 /** Physical address of the MSR bitmap (8 KB). */
1072 RTHCPHYS HCPhysMsrBitmap;
1073 /** R0 memory object for the MSR bitmap (8 KB). */
1074 RTR0MEMOBJ hMemObjMsrBitmap;
1075 /** Pointer to the MSR bitmap. */
1076 R0PTRTYPE(void *) pvMsrBitmap;
1077
1078 /** Whether VTPR with V_INTR_MASKING set is in effect, indicating
1079 * we should check if the VTPR changed on every VM-exit. */
1080 bool fSyncVTpr;
1081 uint8_t au8Alignment0[7];
1082
1083 /** Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */
1084 uint64_t u64HostTscAux;
1085
1086 /** Cache of the nested-guest's VMCB fields that we modify in order to run the
1087 * nested-guest using AMD-V. This will be restored on \#VMEXIT. */
1088 SVMNESTEDVMCBCACHE NstGstVmcbCache;
1089 } svm;
1090 } HM_UNION_NM(u);
1091
1092 /** Event injection state. */
1093 HMEVENT Event;
1094
1095 /** The PAE PDPEs used with Nested Paging (only valid when
1096 * VMCPU_FF_HM_UPDATE_PAE_PDPES is set). */
1097 X86PDPE aPdpes[4];
1098
1099 /** Current shadow paging mode for updating CR4. */
1100 PGMMODE enmShadowMode;
1101
1102 /** The CPU ID of the CPU currently owning the VMCS. Set in
1103 * HMR0Enter and cleared in HMR0Leave. */
1104 RTCPUID idEnteredCpu;
1105
1106 /** For saving stack space, the disassembler state is allocated here instead of
1107 * on the stack. */
1108 DISCPUSTATE DisState;
1109
1110 STAMPROFILEADV StatEntry;
1111 STAMPROFILEADV StatPreExit;
1112 STAMPROFILEADV StatExitHandling;
1113 STAMPROFILEADV StatExitIO;
1114 STAMPROFILEADV StatExitMovCRx;
1115 STAMPROFILEADV StatExitXcptNmi;
1116 STAMPROFILEADV StatExitVmentry;
1117 STAMPROFILEADV StatImportGuestState;
1118 STAMPROFILEADV StatExportGuestState;
1119 STAMPROFILEADV StatLoadGuestFpuState;
1120 STAMPROFILEADV StatInGC;
1121#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1122 STAMPROFILEADV StatWorldSwitch3264;
1123#endif
1124 STAMPROFILEADV StatPoke;
1125 STAMPROFILEADV StatSpinPoke;
1126 STAMPROFILEADV StatSpinPokeFailed;
1127
1128 STAMCOUNTER StatInjectInterrupt;
1129 STAMCOUNTER StatInjectXcpt;
1130 STAMCOUNTER StatInjectReflect;
1131 STAMCOUNTER StatInjectConvertDF;
1132 STAMCOUNTER StatInjectInterpret;
1133 STAMCOUNTER StatInjectReflectNPF;
1134
1135 STAMCOUNTER StatExitAll;
1136 STAMCOUNTER StatNestedExitAll;
1137 STAMCOUNTER StatExitShadowNM;
1138 STAMCOUNTER StatExitGuestNM;
1139 STAMCOUNTER StatExitShadowPF; /**< Misleading, currently used for MMIO \#PFs as well. */
1140 STAMCOUNTER StatExitShadowPFEM;
1141 STAMCOUNTER StatExitGuestPF;
1142 STAMCOUNTER StatExitGuestUD;
1143 STAMCOUNTER StatExitGuestSS;
1144 STAMCOUNTER StatExitGuestNP;
1145 STAMCOUNTER StatExitGuestTS;
1146 STAMCOUNTER StatExitGuestOF;
1147 STAMCOUNTER StatExitGuestGP;
1148 STAMCOUNTER StatExitGuestDE;
1149 STAMCOUNTER StatExitGuestDF;
1150 STAMCOUNTER StatExitGuestBR;
1151 STAMCOUNTER StatExitGuestAC;
1152 STAMCOUNTER StatExitGuestDB;
1153 STAMCOUNTER StatExitGuestMF;
1154 STAMCOUNTER StatExitGuestBP;
1155 STAMCOUNTER StatExitGuestXF;
1156 STAMCOUNTER StatExitGuestXcpUnk;
1157 STAMCOUNTER StatExitDRxWrite;
1158 STAMCOUNTER StatExitDRxRead;
1159 STAMCOUNTER StatExitCR0Read;
1160 STAMCOUNTER StatExitCR2Read;
1161 STAMCOUNTER StatExitCR3Read;
1162 STAMCOUNTER StatExitCR4Read;
1163 STAMCOUNTER StatExitCR8Read;
1164 STAMCOUNTER StatExitCR0Write;
1165 STAMCOUNTER StatExitCR2Write;
1166 STAMCOUNTER StatExitCR3Write;
1167 STAMCOUNTER StatExitCR4Write;
1168 STAMCOUNTER StatExitCR8Write;
1169 STAMCOUNTER StatExitRdmsr;
1170 STAMCOUNTER StatExitWrmsr;
1171 STAMCOUNTER StatExitClts;
1172 STAMCOUNTER StatExitXdtrAccess;
1173 STAMCOUNTER StatExitLmsw;
1174 STAMCOUNTER StatExitIOWrite;
1175 STAMCOUNTER StatExitIORead;
1176 STAMCOUNTER StatExitIOStringWrite;
1177 STAMCOUNTER StatExitIOStringRead;
1178 STAMCOUNTER StatExitIntWindow;
1179 STAMCOUNTER StatExitExtInt;
1180 STAMCOUNTER StatExitHostNmiInGC;
1181 STAMCOUNTER StatExitHostNmiInGCIpi;
1182 STAMCOUNTER StatExitPreemptTimer;
1183 STAMCOUNTER StatExitTprBelowThreshold;
1184 STAMCOUNTER StatExitTaskSwitch;
1185 STAMCOUNTER StatExitApicAccess;
1186 STAMCOUNTER StatExitReasonNpf;
1187
1188 STAMCOUNTER StatNestedExitReasonNpf;
1189
1190 STAMCOUNTER StatFlushPage;
1191 STAMCOUNTER StatFlushPageManual;
1192 STAMCOUNTER StatFlushPhysPageManual;
1193 STAMCOUNTER StatFlushTlb;
1194 STAMCOUNTER StatFlushTlbNstGst;
1195 STAMCOUNTER StatFlushTlbManual;
1196 STAMCOUNTER StatFlushTlbWorldSwitch;
1197 STAMCOUNTER StatNoFlushTlbWorldSwitch;
1198 STAMCOUNTER StatFlushEntire;
1199 STAMCOUNTER StatFlushAsid;
1200 STAMCOUNTER StatFlushNestedPaging;
1201 STAMCOUNTER StatFlushTlbInvlpgVirt;
1202 STAMCOUNTER StatFlushTlbInvlpgPhys;
1203 STAMCOUNTER StatTlbShootdown;
1204 STAMCOUNTER StatTlbShootdownFlush;
1205
1206 STAMCOUNTER StatSwitchPendingHostIrq;
1207 STAMCOUNTER StatSwitchTprMaskedIrq;
1208 STAMCOUNTER StatSwitchGuestIrq;
1209 STAMCOUNTER StatSwitchHmToR3FF;
1210 STAMCOUNTER StatSwitchVmReq;
1211 STAMCOUNTER StatSwitchPgmPoolFlush;
1212 STAMCOUNTER StatSwitchDma;
1213 STAMCOUNTER StatSwitchExitToR3;
1214 STAMCOUNTER StatSwitchLongJmpToR3;
1215 STAMCOUNTER StatSwitchMaxResumeLoops;
1216 STAMCOUNTER StatSwitchHltToR3;
1217 STAMCOUNTER StatSwitchApicAccessToR3;
1218 STAMCOUNTER StatSwitchPreempt;
1219 STAMCOUNTER StatSwitchNstGstVmexit;
1220
1221 STAMCOUNTER StatTscParavirt;
1222 STAMCOUNTER StatTscOffset;
1223 STAMCOUNTER StatTscIntercept;
1224
1225 STAMCOUNTER StatDRxArmed;
1226 STAMCOUNTER StatDRxContextSwitch;
1227 STAMCOUNTER StatDRxIoCheck;
1228
1229 STAMCOUNTER StatExportMinimal;
1230 STAMCOUNTER StatExportFull;
1231 STAMCOUNTER StatLoadGuestFpu;
1232 STAMCOUNTER StatExportHostState;
1233
1234 STAMCOUNTER StatVmxCheckBadRmSelBase;
1235 STAMCOUNTER StatVmxCheckBadRmSelLimit;
1236 STAMCOUNTER StatVmxCheckBadRmSelAttr;
1237 STAMCOUNTER StatVmxCheckBadV86SelBase;
1238 STAMCOUNTER StatVmxCheckBadV86SelLimit;
1239 STAMCOUNTER StatVmxCheckBadV86SelAttr;
1240 STAMCOUNTER StatVmxCheckRmOk;
1241 STAMCOUNTER StatVmxCheckBadSel;
1242 STAMCOUNTER StatVmxCheckBadRpl;
1243 STAMCOUNTER StatVmxCheckPmOk;
1244
1245#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1246 STAMCOUNTER StatFpu64SwitchBack;
1247 STAMCOUNTER StatDebug64SwitchBack;
1248#endif
1249#ifdef VBOX_WITH_STATISTICS
1250 R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
1251 R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
1252 R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
1253 R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
1254 R3PTRTYPE(PSTAMCOUNTER) paStatNestedExitReason;
1255 R0PTRTYPE(PSTAMCOUNTER) paStatNestedExitReasonR0;
1256#endif
1257#ifdef HM_PROFILE_EXIT_DISPATCH
1258 STAMPROFILEADV StatExitDispatch;
1259#endif
1260} HMCPU;
1261/** Pointer to HM VMCPU instance data. */
1262typedef HMCPU *PHMCPU;
1263AssertCompileMemberAlignment(HMCPU, cWorldSwitchExits, 4);
1264AssertCompileMemberAlignment(HMCPU, fCtxChanged, 8);
1265AssertCompileMemberAlignment(HMCPU, HM_UNION_NM(u.) vmx, 8);
1266AssertCompileMemberAlignment(HMCPU, HM_UNION_NM(u.) svm, 8);
1267AssertCompileMemberAlignment(HMCPU, Event, 8);
1268
1269#ifdef IN_RING0
1270VMMR0_INT_DECL(PHMPHYSCPU) hmR0GetCurrentCpu(void);
1271VMMR0_INT_DECL(int) hmR0EnterCpu(PVMCPU pVCpu);
1272
1273# ifdef VBOX_STRICT
1274VMMR0_INT_DECL(void) hmR0DumpRegs(PVMCPU pVCpu);
1275VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
1276# endif
1277
1278# ifdef VBOX_WITH_KERNEL_USING_XMM
1279DECLASM(int) hmR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMXVMCSCACHE pVmcsCache, PVM pVM,
1280 PVMCPU pVCpu, PFNHMVMXSTARTVM pfnStartVM);
1281DECLASM(int) hmR0SVMRunWrapXMM(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu,
1282 PFNHMSVMVMRUN pfnVMRun);
1283# endif
1284DECLASM(void) hmR0MdsClear(void);
1285#endif /* IN_RING0 */
1286
1287VMM_INT_DECL(int) hmEmulateSvmMovTpr(PVMCPU pVCpu);
1288
1289VMM_INT_DECL(PVMXVMCSINFO) hmGetVmxActiveVmcsInfo(PVMCPU pVCpu);
1290
1291/** @} */
1292
1293RT_C_DECLS_END
1294
1295#endif /* !VMM_INCLUDED_SRC_include_HMInternal_h */
1296
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