HMInternal.h@ 71204

最後變更在這個檔案從71204是 71108,由 vboxsync 提交於 7 年前
Added speculation control settings to API, refined implementation.
屬性 svn:eol-style 設為 `native` 屬性 svn:keywords 設為 `Id Revision`
檔案大小: 44.7 KB

行
1	/* $Id: HMInternal.h 71108 2018-02-22 15:38:35Z vboxsync $ */
2	/** @file
3	* HM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.alldomusa.eu.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___HMInternal_h
19	#define ___HMInternal_h
20
21	#include <VBox/cdefs.h>
22	#include <VBox/types.h>
23	#include <VBox/vmm/em.h>
24	#include <VBox/vmm/stam.h>
25	#include <VBox/dis.h>
26	#include <VBox/vmm/hm.h>
27	#include <VBox/vmm/hm_vmx.h>
28	#include <VBox/vmm/hm_svm.h>
29	#include <VBox/vmm/pgm.h>
30	#include <VBox/vmm/cpum.h>
31	#include <VBox/vmm/trpm.h>
32	#include <iprt/memobj.h>
33	#include <iprt/cpuset.h>
34	#include <iprt/mp.h>
35	#include <iprt/avl.h>
36	#include <iprt/string.h>
37
38	#if defined(RT_OS_DARWIN) && HC_ARCH_BITS == 32
39	# error "32-bit darwin is no longer supported. Go back to 4.3 or earlier!"
40	#endif
41
42	#if HC_ARCH_BITS == 64 \|\| defined (VBOX_WITH_64_BITS_GUESTS)
43	/* Enable 64 bits guest support. */
44	# define VBOX_ENABLE_64_BITS_GUESTS
45	#endif
46
47	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
48	# define VMX_USE_CACHED_VMCS_ACCESSES
49	#endif
50
51	/** @def HM_PROFILE_EXIT_DISPATCH
52	* Enables profiling of the VM exit handler dispatching. */
53	#if 0 \|\| defined(DOXYGEN_RUNNING)
54	# define HM_PROFILE_EXIT_DISPATCH
55	#endif
56
57	RT_C_DECLS_BEGIN
58
59
60	/** @defgroup grp_hm_int Internal
61	* @ingroup grp_hm
62	* @internal
63	* @{
64	*/
65
66	/** @def HMCPU_CF_CLEAR
67	* Clears a HM-context flag.
68	*
69	* @param pVCpu The cross context virtual CPU structure.
70	* @param fFlag The flag to clear.
71	*/
72	#define HMCPU_CF_CLEAR(pVCpu, fFlag) (ASMAtomicUoAndU32(&(pVCpu)->hm.s.fContextUseFlags, ~(fFlag)))
73
74	/** @def HMCPU_CF_SET
75	* Sets a HM-context flag.
76	*
77	* @param pVCpu The cross context virtual CPU structure.
78	* @param fFlag The flag to set.
79	*/
80	#define HMCPU_CF_SET(pVCpu, fFlag) (ASMAtomicUoOrU32(&(pVCpu)->hm.s.fContextUseFlags, (fFlag)))
81
82	/** @def HMCPU_CF_IS_SET
83	* Checks if all the flags in the specified HM-context set is pending.
84	*
85	* @param pVCpu The cross context virtual CPU structure.
86	* @param fFlag The flag to check.
87	*/
88	#define HMCPU_CF_IS_SET(pVCpu, fFlag) ((ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) & (fFlag)) == (fFlag))
89
90	/** @def HMCPU_CF_IS_PENDING
91	* Checks if one or more of the flags in the specified HM-context set is
92	* pending.
93	*
94	* @param pVCpu The cross context virtual CPU structure.
95	* @param fFlags The flags to check for.
96	*/
97	#define HMCPU_CF_IS_PENDING(pVCpu, fFlags) RT_BOOL(ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) & (fFlags))
98
99	/** @def HMCPU_CF_IS_PENDING_ONLY
100	* Checks if -only- one or more of the specified HM-context flags is pending.
101	*
102	* @param pVCpu The cross context virtual CPU structure.
103	* @param fFlags The flags to check for.
104	*/
105	#define HMCPU_CF_IS_PENDING_ONLY(pVCpu, fFlags) !RT_BOOL(ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) & ~(fFlags))
106
107	/** @def HMCPU_CF_IS_SET_ONLY
108	* Checks if -only- all the flags in the specified HM-context set is pending.
109	*
110	* @param pVCpu The cross context virtual CPU structure.
111	* @param fFlags The flags to check for.
112	*/
113	#define HMCPU_CF_IS_SET_ONLY(pVCpu, fFlags) (ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) == (fFlags))
114
115	/** @def HMCPU_CF_RESET_TO
116	* Resets the HM-context flags to the specified value.
117	*
118	* @param pVCpu The cross context virtual CPU structure.
119	* @param fFlags The new value.
120	*/
121	#define HMCPU_CF_RESET_TO(pVCpu, fFlags) (ASMAtomicUoWriteU32(&(pVCpu)->hm.s.fContextUseFlags, (fFlags)))
122
123	/** @def HMCPU_CF_VALUE
124	* Returns the current HM-context flags value.
125	*
126	* @param pVCpu The cross context virtual CPU structure.
127	*/
128	#define HMCPU_CF_VALUE(pVCpu) (ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags))
129
130
131	/** Resets/initializes the VM-exit/\#VMEXIT history array. */
132	#define HMCPU_EXIT_HISTORY_RESET(pVCpu) (memset(&(pVCpu)->hm.s.auExitHistory, 0xff, sizeof((pVCpu)->hm.s.auExitHistory)))
133
134	/** Updates the VM-exit/\#VMEXIT history array. */
135	#define HMCPU_EXIT_HISTORY_ADD(pVCpu, a_ExitReason) \
136	do { \
137	AssertMsg((pVCpu)->hm.s.idxExitHistoryFree < RT_ELEMENTS((pVCpu)->hm.s.auExitHistory), ("%u\n", (pVCpu)->hm.s.idxExitHistoryFree)); \
138	(pVCpu)->hm.s.auExitHistory[(pVCpu)->hm.s.idxExitHistoryFree++] = (uint16_t)(a_ExitReason); \
139	if ((pVCpu)->hm.s.idxExitHistoryFree == RT_ELEMENTS((pVCpu)->hm.s.auExitHistory)) \
140	(pVCpu)->hm.s.idxExitHistoryFree = 0; \
141	(pVCpu)->hm.s.auExitHistory[(pVCpu)->hm.s.idxExitHistoryFree] = UINT16_MAX; \
142	} while (0)
143
144	/** Maximum number of exit reason statistics counters. */
145	#define MAX_EXITREASON_STAT 0x100
146	#define MASK_EXITREASON_STAT 0xff
147	#define MASK_INJECT_IRQ_STAT 0xff
148
149	/** @name HM changed flags.
150	* These flags are used to keep track of which important registers that have
151	* been changed since last they were reset.
152	*
153	* Flags marked "shared" are used for registers that are common to both the host
154	* and guest (i.e. without dedicated VMCS/VMCB fields for guest bits).
155	*
156	* @{
157	*/
158	#define HM_CHANGED_GUEST_CR0 RT_BIT(0) /* Shared */
159	#define HM_CHANGED_GUEST_CR3 RT_BIT(1)
160	#define HM_CHANGED_GUEST_CR4 RT_BIT(2)
161	#define HM_CHANGED_GUEST_GDTR RT_BIT(3)
162	#define HM_CHANGED_GUEST_IDTR RT_BIT(4)
163	#define HM_CHANGED_GUEST_LDTR RT_BIT(5)
164	#define HM_CHANGED_GUEST_TR RT_BIT(6)
165	#define HM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(7)
166	#define HM_CHANGED_GUEST_DEBUG RT_BIT(8) /* Shared */
167	#define HM_CHANGED_GUEST_RIP RT_BIT(9)
168	#define HM_CHANGED_GUEST_RSP RT_BIT(10)
169	#define HM_CHANGED_GUEST_RFLAGS RT_BIT(11)
170	#define HM_CHANGED_GUEST_CR2 RT_BIT(12)
171	#define HM_CHANGED_GUEST_SYSENTER_CS_MSR RT_BIT(13)
172	#define HM_CHANGED_GUEST_SYSENTER_EIP_MSR RT_BIT(14)
173	#define HM_CHANGED_GUEST_SYSENTER_ESP_MSR RT_BIT(15)
174	#define HM_CHANGED_GUEST_EFER_MSR RT_BIT(16)
175	#define HM_CHANGED_GUEST_LAZY_MSRS RT_BIT(17) /* Shared / /* @todo Move this to VT-x specific? */
176	#define HM_CHANGED_GUEST_XCPT_INTERCEPTS RT_BIT(18)
177	/* VT-x specific state. */
178	#define HM_CHANGED_VMX_GUEST_AUTO_MSRS RT_BIT(19)
179	#define HM_CHANGED_VMX_GUEST_ACTIVITY_STATE RT_BIT(20)
180	#define HM_CHANGED_VMX_GUEST_APIC_STATE RT_BIT(21)
181	#define HM_CHANGED_VMX_ENTRY_CTLS RT_BIT(22)
182	#define HM_CHANGED_VMX_EXIT_CTLS RT_BIT(23)
183	/* AMD-V specific state. */
184	#define HM_CHANGED_SVM_GUEST_APIC_STATE RT_BIT(19)
185	#define HM_CHANGED_SVM_RESERVED1 RT_BIT(20)
186	#define HM_CHANGED_SVM_RESERVED2 RT_BIT(21)
187	#define HM_CHANGED_SVM_RESERVED3 RT_BIT(22)
188	#define HM_CHANGED_SVM_RESERVED4 RT_BIT(23)
189
190	#define HM_CHANGED_ALL_GUEST ( HM_CHANGED_GUEST_CR0 \
191	\| HM_CHANGED_GUEST_CR3 \
192	\| HM_CHANGED_GUEST_CR4 \
193	\| HM_CHANGED_GUEST_GDTR \
194	\| HM_CHANGED_GUEST_IDTR \
195	\| HM_CHANGED_GUEST_LDTR \
196	\| HM_CHANGED_GUEST_TR \
197	\| HM_CHANGED_GUEST_SEGMENT_REGS \
198	\| HM_CHANGED_GUEST_DEBUG \
199	\| HM_CHANGED_GUEST_RIP \
200	\| HM_CHANGED_GUEST_RSP \
201	\| HM_CHANGED_GUEST_RFLAGS \
202	\| HM_CHANGED_GUEST_CR2 \
203	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR \
204	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR \
205	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR \
206	\| HM_CHANGED_GUEST_EFER_MSR \
207	\| HM_CHANGED_GUEST_LAZY_MSRS \
208	\| HM_CHANGED_GUEST_XCPT_INTERCEPTS \
209	\| HM_CHANGED_VMX_GUEST_AUTO_MSRS \
210	\| HM_CHANGED_VMX_GUEST_ACTIVITY_STATE \
211	\| HM_CHANGED_VMX_GUEST_APIC_STATE \
212	\| HM_CHANGED_VMX_ENTRY_CTLS \
213	\| HM_CHANGED_VMX_EXIT_CTLS)
214
215	#define HM_CHANGED_HOST_CONTEXT RT_BIT(24)
216
217	/* Bits shared between host and guest. */
218	#define HM_CHANGED_HOST_GUEST_SHARED_STATE ( HM_CHANGED_GUEST_CR0 \
219	\| HM_CHANGED_GUEST_DEBUG \
220	\| HM_CHANGED_GUEST_LAZY_MSRS)
221	/** @} */
222
223	/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
224	#define HM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
225	/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
226	#define HM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2 * PAGE_SIZE + 1)
227	/** Total guest mapped memory needed. */
228	#define HM_VTX_TOTAL_DEVHEAP_MEM (HM_EPT_IDENTITY_PG_TABLE_SIZE + HM_VTX_TSS_SIZE)
229
230
231	/** @name Macros for enabling and disabling preemption.
232	* These are really just for hiding the RTTHREADPREEMPTSTATE and asserting that
233	* preemption has already been disabled when there is no context hook.
234	* @{ */
235	#ifdef VBOX_STRICT
236	# define HM_DISABLE_PREEMPT() \
237	RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
238	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD) \|\| VMMR0ThreadCtxHookIsEnabled(pVCpu)); \
239	RTThreadPreemptDisable(&PreemptStateInternal)
240	#else
241	# define HM_DISABLE_PREEMPT() \
242	RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
243	RTThreadPreemptDisable(&PreemptStateInternal)
244	#endif /* VBOX_STRICT */
245	#define HM_RESTORE_PREEMPT() do { RTThreadPreemptRestore(&PreemptStateInternal); } while(0)
246	/** @} */
247
248
249	/** Enable for TPR guest patching. */
250	#define VBOX_HM_WITH_GUEST_PATCHING
251
252	/** @name HM saved state versions
253	* @{
254	*/
255	#ifdef VBOX_HM_WITH_GUEST_PATCHING
256	# define HM_SAVED_STATE_VERSION 5
257	# define HM_SAVED_STATE_VERSION_NO_PATCHING 4
258	#else
259	# define HM_SAVED_STATE_VERSION 4
260	# define HM_SAVED_STATE_VERSION_NO_PATCHING 4
261	#endif
262	#define HM_SAVED_STATE_VERSION_2_0_X 3
263	/** @} */
264
265	/**
266	* Global per-cpu information. (host)
267	*/
268	typedef struct HMGLOBALCPUINFO
269	{
270	/** The CPU ID. */
271	RTCPUID idCpu;
272	/** The VM_HSAVE_AREA (AMD-V) / VMXON region (Intel) memory backing. */
273	RTR0MEMOBJ hMemObj;
274	/** The physical address of the first page in hMemObj (it's a
275	* physcially contigous allocation if it spans multiple pages). */
276	RTHCPHYS HCPhysMemObj;
277	/** The address of the memory (for pfnEnable). */
278	void *pvMemObj;
279	/** Current ASID (AMD-V) / VPID (Intel). */
280	uint32_t uCurrentAsid;
281	/** TLB flush count. */
282	uint32_t cTlbFlushes;
283	/** Whether to flush each new ASID/VPID before use. */
284	bool fFlushAsidBeforeUse;
285	/** Configured for VT-x or AMD-V. */
286	bool fConfigured;
287	/** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
288	bool fIgnoreAMDVInUseError;
289	/** In use by our code. (for power suspend) */
290	volatile bool fInUse;
291	} HMGLOBALCPUINFO;
292	/** Pointer to the per-cpu global information. */
293	typedef HMGLOBALCPUINFO *PHMGLOBALCPUINFO;
294
295	typedef enum
296	{
297	HMPENDINGIO_INVALID = 0,
298	HMPENDINGIO_PORT_READ,
299	/* not implemented: HMPENDINGIO_STRING_READ, */
300	/* not implemented: HMPENDINGIO_STRING_WRITE, */
301	/** The usual 32-bit paranoia. */
302	HMPENDINGIO_32BIT_HACK = 0x7fffffff
303	} HMPENDINGIO;
304
305
306	typedef enum
307	{
308	HMTPRINSTR_INVALID,
309	HMTPRINSTR_READ,
310	HMTPRINSTR_READ_SHR4,
311	HMTPRINSTR_WRITE_REG,
312	HMTPRINSTR_WRITE_IMM,
313	HMTPRINSTR_JUMP_REPLACEMENT,
314	/** The usual 32-bit paranoia. */
315	HMTPRINSTR_32BIT_HACK = 0x7fffffff
316	} HMTPRINSTR;
317
318	typedef struct
319	{
320	/** The key is the address of patched instruction. (32 bits GC ptr) */
321	AVLOU32NODECORE Core;
322	/** Original opcode. */
323	uint8_t aOpcode[16];
324	/** Instruction size. */
325	uint32_t cbOp;
326	/** Replacement opcode. */
327	uint8_t aNewOpcode[16];
328	/** Replacement instruction size. */
329	uint32_t cbNewOp;
330	/** Instruction type. */
331	HMTPRINSTR enmType;
332	/** Source operand. */
333	uint32_t uSrcOperand;
334	/** Destination operand. */
335	uint32_t uDstOperand;
336	/** Number of times the instruction caused a fault. */
337	uint32_t cFaults;
338	/** Patch address of the jump replacement. */
339	RTGCPTR32 pJumpTarget;
340	} HMTPRPATCH;
341	/** Pointer to HMTPRPATCH. */
342	typedef HMTPRPATCH *PHMTPRPATCH;
343
344
345	/**
346	* Makes a HMEXITSTAT::uKey value from a program counter and an exit code.
347	*
348	* @returns 64-bit key
349	* @param a_uPC The RIP + CS.BASE value of the exit.
350	* @param a_uExit The exit code.
351	* @todo Add CPL?
352	*/
353	#define HMEXITSTAT_MAKE_KEY(a_uPC, a_uExit) (((a_uPC) & UINT64_C(0x0000ffffffffffff)) \| (uint64_t)(a_uExit) << 48)
354
355	typedef struct HMEXITINFO
356	{
357	/** See HMEXITSTAT_MAKE_KEY(). */
358	uint64_t uKey;
359	/** Number of recent hits (depreciates with time). */
360	uint32_t volatile cHits;
361	/** The age + lock. */
362	uint16_t volatile uAge;
363	/** Action or action table index. */
364	uint16_t iAction;
365	} HMEXITINFO;
366	AssertCompileSize(HMEXITINFO, 16); /* Lots of these guys, so don't add any unnecessary stuff! */
367
368	typedef struct HMEXITHISTORY
369	{
370	/** The exit timestamp. */
371	uint64_t uTscExit;
372	/** The index of the corresponding HMEXITINFO entry.
373	* UINT32_MAX if none (too many collisions, race, whatever). */
374	uint32_t iExitInfo;
375	/** Figure out later, needed for padding now. */
376	uint32_t uSomeClueOrSomething;
377	} HMEXITHISTORY;
378
379	/**
380	* Switcher function, HC to the special 64-bit RC.
381	*
382	* @param pVM The cross context VM structure.
383	* @param offCpumVCpu Offset from pVM->cpum to pVM->aCpus[idCpu].cpum.
384	* @returns Return code indicating the action to take.
385	*/
386	typedef DECLCALLBACK(int) FNHMSWITCHERHC(PVM pVM, uint32_t offCpumVCpu);
387	/** Pointer to switcher function. */
388	typedef FNHMSWITCHERHC *PFNHMSWITCHERHC;
389
390	/**
391	* HM VM Instance data.
392	* Changes to this must checked against the padding of the hm union in VM!
393	*/
394	typedef struct HM
395	{
396	/** Set when we've initialized VMX or SVM. */
397	bool fInitialized;
398	/** Set if nested paging is enabled. */
399	bool fNestedPaging;
400	/** Set if nested paging is allowed. */
401	bool fAllowNestedPaging;
402	/** Set if large pages are enabled (requires nested paging). */
403	bool fLargePages;
404	/** Set if we can support 64-bit guests or not. */
405	bool fAllow64BitGuests;
406	/** Set when TPR patching is allowed. */
407	bool fTprPatchingAllowed;
408	/** Set when we initialize VT-x or AMD-V once for all CPUs. */
409	bool fGlobalInit;
410	/** Set when TPR patching is active. */
411	bool fTPRPatchingActive;
412	/** Set when the debug facility has breakpoints/events enabled that requires
413	* us to use the debug execution loop in ring-0. */
414	bool fUseDebugLoop;
415	/** Set if hardware APIC virtualization is enabled. */
416	bool fVirtApicRegs;
417	/** Set if posted interrupt processing is enabled. */
418	bool fPostedIntrs;
419	/** Set if indirect branch prediction barrier on VM exit. */
420	bool fIbpbOnVmExit;
421	/** Set if indirect branch prediction barrier on VM entry. */
422	bool fIbpbOnVmEntry;
423	/** Set if host manages speculation control settings. */
424	bool fSpecCtrlByHost;
425	/** Explicit padding. */
426	bool afPadding[2];
427
428	/** Maximum ASID allowed. */
429	uint32_t uMaxAsid;
430	/** The maximum number of resumes loops allowed in ring-0 (safety precaution).
431	* This number is set much higher when RTThreadPreemptIsPending is reliable. */
432	uint32_t cMaxResumeLoops;
433
434	/** Host kernel flags that HM might need to know (SUPKERNELFEATURES_XXX). */
435	uint32_t fHostKernelFeatures;
436
437	/** Size of the guest patch memory block. */
438	uint32_t cbGuestPatchMem;
439	/** Guest allocated memory for patching purposes. */
440	RTGCPTR pGuestPatchMem;
441	/** Current free pointer inside the patch block. */
442	RTGCPTR pFreeGuestPatchMem;
443
444	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
445	/** 32 to 64 bits switcher entrypoint. */
446	R0PTRTYPE(PFNHMSWITCHERHC) pfnHost32ToGuest64R0;
447	RTR0PTR pvR0Alignment0;
448	#endif
449
450	struct
451	{
452	/** Set by the ring-0 side of HM to indicate VMX is supported by the
453	* CPU. */
454	bool fSupported;
455	/** Set when we've enabled VMX. */
456	bool fEnabled;
457	/** Set if VPID is supported. */
458	bool fVpid;
459	/** Set if VT-x VPID is allowed. */
460	bool fAllowVpid;
461	/** Set if unrestricted guest execution is in use (real and protected mode without paging). */
462	bool fUnrestrictedGuest;
463	/** Set if unrestricted guest execution is allowed to be used. */
464	bool fAllowUnrestricted;
465	/** Whether we're using the preemption timer or not. */
466	bool fUsePreemptTimer;
467	/** The shift mask employed by the VMX-Preemption timer. */
468	uint8_t cPreemptTimerShift;
469
470	/** Virtual address of the TSS page used for real mode emulation. */
471	R3PTRTYPE(PVBOXTSS) pRealModeTSS;
472	/** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
473	R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
474
475	/** Physical address of the APIC-access page. */
476	RTHCPHYS HCPhysApicAccess;
477	/** R0 memory object for the APIC-access page. */
478	RTR0MEMOBJ hMemObjApicAccess;
479	/** Virtual address of the APIC-access page. */
480	R0PTRTYPE(uint8_t *) pbApicAccess;
481
482	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
483	RTHCPHYS HCPhysScratch;
484	RTR0MEMOBJ hMemObjScratch;
485	R0PTRTYPE(uint8_t *) pbScratch;
486	#endif
487
488	/** Internal Id of which flush-handler to use for tagged-TLB entries. */
489	uint32_t uFlushTaggedTlb;
490
491	/** Pause-loop exiting (PLE) gap in ticks. */
492	uint32_t cPleGapTicks;
493	/** Pause-loop exiting (PLE) window in ticks. */
494	uint32_t cPleWindowTicks;
495	uint32_t u32Alignment0;
496
497	/** Host CR4 value (set by ring-0 VMX init) */
498	uint64_t u64HostCr4;
499	/** Host SMM monitor control (set by ring-0 VMX init) */
500	uint64_t u64HostSmmMonitorCtl;
501	/** Host EFER value (set by ring-0 VMX init) */
502	uint64_t u64HostEfer;
503	/** Whether the CPU supports VMCS fields for swapping EFER. */
504	bool fSupportsVmcsEfer;
505	uint8_t u8Alignment2[7];
506
507	/** VMX MSR values. */
508	VMXMSRS Msrs;
509
510	/** Flush types for invept & invvpid; they depend on capabilities. */
511	VMXFLUSHEPT enmFlushEpt;
512	VMXFLUSHVPID enmFlushVpid;
513
514	/** Host-physical address for a failing VMXON instruction. */
515	RTHCPHYS HCPhysVmxEnableError;
516	} vmx;
517
518	struct
519	{
520	/** Set by the ring-0 side of HM to indicate SVM is supported by the
521	* CPU. */
522	bool fSupported;
523	/** Set when we've enabled SVM. */
524	bool fEnabled;
525	/** Set if erratum 170 affects the AMD cpu. */
526	bool fAlwaysFlushTLB;
527	/** Set when the hack to ignore VERR_SVM_IN_USE is active. */
528	bool fIgnoreInUseError;
529	/** Whether to use virtualized VMSAVE/VMLOAD feature. */
530	bool fVirtVmsaveVmload;
531	/** Whether to use virtual GIF feature. */
532	bool fVGif;
533	uint8_t u8Alignment0[2];
534
535	/** Physical address of the IO bitmap (12kb). */
536	RTHCPHYS HCPhysIOBitmap;
537	/** R0 memory object for the IO bitmap (12kb). */
538	RTR0MEMOBJ hMemObjIOBitmap;
539	/** Virtual address of the IO bitmap. */
540	R0PTRTYPE(void *) pvIOBitmap;
541
542	/* HWCR MSR (for diagnostics) */
543	uint64_t u64MsrHwcr;
544
545	/** SVM revision. */
546	uint32_t u32Rev;
547	/** SVM feature bits from cpuid 0x8000000a */
548	uint32_t u32Features;
549
550	/** Pause filter counter. */
551	uint16_t cPauseFilter;
552	/** Pause filter treshold in ticks. */
553	uint16_t cPauseFilterThresholdTicks;
554	uint32_t u32Alignment0;
555	} svm;
556
557	/**
558	* AVL tree with all patches (active or disabled) sorted by guest instruction
559	* address.
560	*/
561	AVLOU32TREE PatchTree;
562	uint32_t cPatches;
563	HMTPRPATCH aPatches[64];
564
565	struct
566	{
567	uint32_t u32AMDFeatureECX;
568	uint32_t u32AMDFeatureEDX;
569	} cpuid;
570
571	/** Saved error from detection */
572	int32_t lLastError;
573
574	/** HMR0Init was run */
575	bool fHMR0Init;
576	bool u8Alignment1[3];
577
578	STAMCOUNTER StatTprPatchSuccess;
579	STAMCOUNTER StatTprPatchFailure;
580	STAMCOUNTER StatTprReplaceSuccessCr8;
581	STAMCOUNTER StatTprReplaceSuccessVmc;
582	STAMCOUNTER StatTprReplaceFailure;
583	} HM;
584	/** Pointer to HM VM instance data. */
585	typedef HM *PHM;
586
587	AssertCompileMemberAlignment(HM, StatTprPatchSuccess, 8);
588
589	/* Maximum number of cached entries. */
590	#define VMCSCACHE_MAX_ENTRY 128
591
592	/**
593	* Structure for storing read and write VMCS actions.
594	*/
595	typedef struct VMCSCACHE
596	{
597	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
598	/* Magic marker for searching in crash dumps. */
599	uint8_t aMagic[16];
600	uint64_t uMagic;
601	uint64_t u64TimeEntry;
602	uint64_t u64TimeSwitch;
603	uint64_t cResume;
604	uint64_t interPD;
605	uint64_t pSwitcher;
606	uint32_t uPos;
607	uint32_t idCpu;
608	#endif
609	/* CR2 is saved here for EPT syncing. */
610	uint64_t cr2;
611	struct
612	{
613	uint32_t cValidEntries;
614	uint32_t uAlignment;
615	uint32_t aField[VMCSCACHE_MAX_ENTRY];
616	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
617	} Write;
618	struct
619	{
620	uint32_t cValidEntries;
621	uint32_t uAlignment;
622	uint32_t aField[VMCSCACHE_MAX_ENTRY];
623	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
624	} Read;
625	#ifdef VBOX_STRICT
626	struct
627	{
628	RTHCPHYS HCPhysCpuPage;
629	RTHCPHYS HCPhysVmcs;
630	RTGCPTR pCache;
631	RTGCPTR pCtx;
632	} TestIn;
633	struct
634	{
635	RTHCPHYS HCPhysVmcs;
636	RTGCPTR pCache;
637	RTGCPTR pCtx;
638	uint64_t eflags;
639	uint64_t cr8;
640	} TestOut;
641	struct
642	{
643	uint64_t param1;
644	uint64_t param2;
645	uint64_t param3;
646	uint64_t param4;
647	} ScratchPad;
648	#endif
649	} VMCSCACHE;
650	/** Pointer to VMCSCACHE. */
651	typedef VMCSCACHE *PVMCSCACHE;
652	AssertCompileSizeAlignment(VMCSCACHE, 8);
653
654	/**
655	* VMX StartVM function.
656	*
657	* @returns VBox status code (no informational stuff).
658	* @param fResume Whether to use VMRESUME (true) or VMLAUNCH (false).
659	* @param pCtx The CPU register context.
660	* @param pCache The VMCS cache.
661	* @param pVM Pointer to the cross context VM structure.
662	* @param pVCpu Pointer to the cross context per-CPU structure.
663	*/
664	typedef DECLCALLBACK(int) FNHMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
665	/** Pointer to a VMX StartVM function. */
666	typedef R0PTRTYPE(FNHMVMXSTARTVM *) PFNHMVMXSTARTVM;
667
668	/** SVM VMRun function. */
669	typedef DECLCALLBACK(int) FNHMSVMVMRUN(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
670	/** Pointer to a SVM VMRun function. */
671	typedef R0PTRTYPE(FNHMSVMVMRUN *) PFNHMSVMVMRUN;
672
673	/**
674	* HM VMCPU Instance data.
675	*
676	* Note! If you change members of this struct, make sure to check if the
677	* assembly counterpart in HMInternal.mac needs to be updated as well.
678	*/
679	typedef struct HMCPU
680	{
681	/** Set if we need to flush the TLB during the world switch. */
682	bool fForceTLBFlush;
683	/** Set when we're using VT-x or AMD-V at that moment. */
684	bool fActive;
685	/** Set when the TLB has been checked until we return from the world switch. */
686	volatile bool fCheckedTLBFlush;
687	/** Whether we've completed the inner HM leave function. */
688	bool fLeaveDone;
689	/** Whether we're using the hyper DR7 or guest DR7. */
690	bool fUsingHyperDR7;
691	/** Whether to preload the guest-FPU state to avoid \#NM VM-exit overhead. */
692	bool fPreloadGuestFpu;
693	/** Set if XCR0 needs to be loaded and saved when entering and exiting guest
694	* code execution. */
695	bool fLoadSaveGuestXcr0;
696
697	/** Whether we should use the debug loop because of single stepping or special
698	* debug breakpoints / events are armed. */
699	bool fUseDebugLoop;
700	/** Whether we are currently executing in the debug loop.
701	* Mainly for assertions. */
702	bool fUsingDebugLoop;
703	/** Set if we using the debug loop and wish to intercept RDTSC. */
704	bool fDebugWantRdTscExit;
705	/** Whether we're executing a single instruction. */
706	bool fSingleInstruction;
707	/** Set if we need to clear the trap flag because of single stepping. */
708	bool fClearTrapFlag;
709
710	/** Whether \#UD needs to be intercepted (required by certain GIM providers). */
711	bool fGIMTrapXcptUD;
712	/** Whether paravirt. hypercalls are enabled. */
713	bool fHypercallsEnabled;
714	uint8_t u8Alignment0[2];
715
716	/** World switch exit counter. */
717	volatile uint32_t cWorldSwitchExits;
718	/** HM_CHANGED_* flags. */
719	volatile uint32_t fContextUseFlags;
720	/** Id of the last cpu we were executing code on (NIL_RTCPUID for the first
721	* time). */
722	RTCPUID idLastCpu;
723	/** TLB flush count. */
724	uint32_t cTlbFlushes;
725	/** Current ASID in use by the VM. */
726	uint32_t uCurrentAsid;
727	/** An additional error code used for some gurus. */
728	uint32_t u32HMError;
729	/** Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */
730	uint64_t u64HostTscAux;
731
732	struct
733	{
734	/** Ring 0 handlers for VT-x. */
735	PFNHMVMXSTARTVM pfnStartVM;
736	#if HC_ARCH_BITS == 32
737	uint32_t u32Alignment0;
738	#endif
739	/** Current VMX_VMCS32_CTRL_PIN_EXEC. */
740	uint32_t u32PinCtls;
741	/** Current VMX_VMCS32_CTRL_PROC_EXEC. */
742	uint32_t u32ProcCtls;
743	/** Current VMX_VMCS32_CTRL_PROC_EXEC2. */
744	uint32_t u32ProcCtls2;
745	/** Current VMX_VMCS32_CTRL_EXIT. */
746	uint32_t u32ExitCtls;
747	/** Current VMX_VMCS32_CTRL_ENTRY. */
748	uint32_t u32EntryCtls;
749
750	/** Current CR0 mask. */
751	uint32_t u32CR0Mask;
752	/** Current CR4 mask. */
753	uint32_t u32CR4Mask;
754	/** Current exception bitmap. */
755	uint32_t u32XcptBitmap;
756	/** The updated-guest-state mask. */
757	volatile uint32_t fUpdatedGuestState;
758	uint32_t u32Alignment1;
759
760	/** Physical address of the VM control structure (VMCS). */
761	RTHCPHYS HCPhysVmcs;
762	/** R0 memory object for the VM control structure (VMCS). */
763	RTR0MEMOBJ hMemObjVmcs;
764	/** Virtual address of the VM control structure (VMCS). */
765	R0PTRTYPE(void *) pvVmcs;
766
767	/** Physical address of the virtual APIC page for TPR caching. */
768	RTHCPHYS HCPhysVirtApic;
769	/** Padding. */
770	R0PTRTYPE(void *) pvAlignment0;
771	/** Virtual address of the virtual APIC page for TPR caching. */
772	R0PTRTYPE(uint8_t *) pbVirtApic;
773
774	/** Physical address of the MSR bitmap. */
775	RTHCPHYS HCPhysMsrBitmap;
776	/** R0 memory object for the MSR bitmap. */
777	RTR0MEMOBJ hMemObjMsrBitmap;
778	/** Virtual address of the MSR bitmap. */
779	R0PTRTYPE(void *) pvMsrBitmap;
780
781	/** Physical address of the VM-entry MSR-load and VM-exit MSR-store area (used
782	* for guest MSRs). */
783	RTHCPHYS HCPhysGuestMsr;
784	/** R0 memory object of the VM-entry MSR-load and VM-exit MSR-store area
785	* (used for guest MSRs). */
786	RTR0MEMOBJ hMemObjGuestMsr;
787	/** Virtual address of the VM-entry MSR-load and VM-exit MSR-store area (used
788	* for guest MSRs). */
789	R0PTRTYPE(void *) pvGuestMsr;
790
791	/** Physical address of the VM-exit MSR-load area (used for host MSRs). */
792	RTHCPHYS HCPhysHostMsr;
793	/** R0 memory object for the VM-exit MSR-load area (used for host MSRs). */
794	RTR0MEMOBJ hMemObjHostMsr;
795	/** Virtual address of the VM-exit MSR-load area (used for host MSRs). */
796	R0PTRTYPE(void *) pvHostMsr;
797
798	/** Current EPTP. */
799	RTHCPHYS HCPhysEPTP;
800
801	/** Number of guest/host MSR pairs in the auto-load/store area. */
802	uint32_t cMsrs;
803	/** Whether the host MSR values are up-to-date in the auto-load/store area. */
804	bool fUpdatedHostMsrs;
805	uint8_t u8Alignment0[3];
806
807	/** Host LSTAR MSR value to restore lazily while leaving VT-x. */
808	uint64_t u64HostLStarMsr;
809	/** Host STAR MSR value to restore lazily while leaving VT-x. */
810	uint64_t u64HostStarMsr;
811	/** Host SF_MASK MSR value to restore lazily while leaving VT-x. */
812	uint64_t u64HostSFMaskMsr;
813	/** Host KernelGS-Base MSR value to restore lazily while leaving VT-x. */
814	uint64_t u64HostKernelGSBaseMsr;
815	/** A mask of which MSRs have been swapped and need restoration. */
816	uint32_t fLazyMsrs;
817	uint32_t u32Alignment2;
818
819	/** The cached APIC-base MSR used for identifying when to map the HC physical APIC-access page. */
820	uint64_t u64MsrApicBase;
821	/** Last use TSC offset value. (cached) */
822	uint64_t u64TSCOffset;
823
824	/** VMCS cache. */
825	VMCSCACHE VMCSCache;
826
827	/** Real-mode emulation state. */
828	struct
829	{
830	X86DESCATTR AttrCS;
831	X86DESCATTR AttrDS;
832	X86DESCATTR AttrES;
833	X86DESCATTR AttrFS;
834	X86DESCATTR AttrGS;
835	X86DESCATTR AttrSS;
836	X86EFLAGS Eflags;
837	uint32_t fRealOnV86Active;
838	} RealMode;
839
840	/** VT-x error-reporting (mainly for ring-3 propagation). */
841	struct
842	{
843	uint64_t u64VMCSPhys;
844	uint32_t u32VMCSRevision;
845	uint32_t u32InstrError;
846	uint32_t u32ExitReason;
847	RTCPUID idEnteredCpu;
848	RTCPUID idCurrentCpu;
849	uint32_t u32Alignment0;
850	} LastError;
851
852	/** Current state of the VMCS. */
853	uint32_t uVmcsState;
854	/** Which host-state bits to restore before being preempted. */
855	uint32_t fRestoreHostFlags;
856	/** The host-state restoration structure. */
857	VMXRESTOREHOST RestoreHost;
858
859	/** Set if guest was executing in real mode (extra checks). */
860	bool fWasInRealMode;
861	/** Set if guest switched to 64-bit mode on a 32-bit host. */
862	bool fSwitchedTo64on32;
863
864	uint8_t u8Alignment1[6];
865	} vmx;
866
867	struct
868	{
869	/** Ring 0 handlers for VT-x. */
870	PFNHMSVMVMRUN pfnVMRun;
871	#if HC_ARCH_BITS == 32
872	uint32_t u32Alignment0;
873	#endif
874
875	/** Physical address of the host VMCB which holds additional host-state. */
876	RTHCPHYS HCPhysVmcbHost;
877	/** R0 memory object for the host VMCB which holds additional host-state. */
878	RTR0MEMOBJ hMemObjVmcbHost;
879	/** Padding. */
880	R0PTRTYPE(void *) pvPadding;
881
882	/** Physical address of the guest VMCB. */
883	RTHCPHYS HCPhysVmcb;
884	/** R0 memory object for the guest VMCB. */
885	RTR0MEMOBJ hMemObjVmcb;
886	/** Pointer to the guest VMCB. */
887	R0PTRTYPE(PSVMVMCB) pVmcb;
888
889	/** Physical address of the MSR bitmap (8 KB). */
890	RTHCPHYS HCPhysMsrBitmap;
891	/** R0 memory object for the MSR bitmap (8 KB). */
892	RTR0MEMOBJ hMemObjMsrBitmap;
893	/** Pointer to the MSR bitmap. */
894	R0PTRTYPE(void *) pvMsrBitmap;
895
896	/** Whether VTPR with V_INTR_MASKING set is in effect, indicating
897	* we should check if the VTPR changed on every VM-exit. */
898	bool fSyncVTpr;
899	uint8_t u8Alignment0[7];
900
901	/** Cache of the nested-guest's VMCB fields that we modify in order to run the
902	* nested-guest using AMD-V. This will be restored on \#VMEXIT. */
903	SVMNESTEDVMCBCACHE NstGstVmcbCache;
904	} svm;
905
906	/** Event injection state. */
907	struct
908	{
909	uint32_t fPending;
910	uint32_t u32ErrCode;
911	uint32_t cbInstr;
912	uint32_t u32Padding; /*< Explicit alignment padding. /
913	uint64_t u64IntInfo;
914	RTGCUINTPTR GCPtrFaultAddress;
915	} Event;
916
917	/** IO Block emulation state. */
918	struct
919	{
920	bool fEnabled;
921	uint8_t u8Align[7];
922
923	/** RIP at the start of the io code we wish to emulate in the recompiler. */
924	RTGCPTR GCPtrFunctionEip;
925
926	uint64_t cr0;
927	} EmulateIoBlock;
928
929	/* */
930	struct
931	{
932	/** Pending IO operation type. */
933	HMPENDINGIO enmType;
934	uint32_t u32Alignment0;
935	RTGCPTR GCPtrRip;
936	RTGCPTR GCPtrRipNext;
937	union
938	{
939	struct
940	{
941	uint32_t uPort;
942	uint32_t uAndVal;
943	uint32_t cbSize;
944	} Port;
945	uint64_t aRaw[2];
946	} s;
947	} PendingIO;
948
949	/** The PAE PDPEs used with Nested Paging (only valid when
950	* VMCPU_FF_HM_UPDATE_PAE_PDPES is set). */
951	X86PDPE aPdpes[4];
952
953	/** Current shadow paging mode. */
954	PGMMODE enmShadowMode;
955
956	/** The CPU ID of the CPU currently owning the VMCS. Set in
957	* HMR0Enter and cleared in HMR0Leave. */
958	RTCPUID idEnteredCpu;
959
960	/** VT-x/AMD-V VM-exit/\#VMXEXIT history, circular array. */
961	uint16_t auExitHistory[31];
962	/** The index of the next free slot in the history array. */
963	uint16_t idxExitHistoryFree;
964
965	/** For saving stack space, the disassembler state is allocated here instead of
966	* on the stack. */
967	DISCPUSTATE DisState;
968
969	STAMPROFILEADV StatEntry;
970	STAMPROFILEADV StatExit1;
971	STAMPROFILEADV StatExit2;
972	STAMPROFILEADV StatExitIO;
973	STAMPROFILEADV StatExitMovCRx;
974	STAMPROFILEADV StatExitXcptNmi;
975	STAMPROFILEADV StatLoadGuestState;
976	STAMPROFILEADV StatInGC;
977
978	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
979	STAMPROFILEADV StatWorldSwitch3264;
980	#endif
981	STAMPROFILEADV StatPoke;
982	STAMPROFILEADV StatSpinPoke;
983	STAMPROFILEADV StatSpinPokeFailed;
984
985	STAMCOUNTER StatInjectInterrupt;
986	STAMCOUNTER StatInjectXcpt;
987	STAMCOUNTER StatInjectPendingReflect;
988	STAMCOUNTER StatInjectPendingInterpret;
989
990	STAMCOUNTER StatExitAll;
991	STAMCOUNTER StatExitShadowNM;
992	STAMCOUNTER StatExitGuestNM;
993	STAMCOUNTER StatExitShadowPF; /*< Misleading, currently used for MMIO \#PFs as well. /
994	STAMCOUNTER StatExitShadowPFEM;
995	STAMCOUNTER StatExitGuestPF;
996	STAMCOUNTER StatExitGuestUD;
997	STAMCOUNTER StatExitGuestSS;
998	STAMCOUNTER StatExitGuestNP;
999	STAMCOUNTER StatExitGuestTS;
1000	STAMCOUNTER StatExitGuestGP;
1001	STAMCOUNTER StatExitGuestDE;
1002	STAMCOUNTER StatExitGuestDB;
1003	STAMCOUNTER StatExitGuestMF;
1004	STAMCOUNTER StatExitGuestBP;
1005	STAMCOUNTER StatExitGuestXF;
1006	STAMCOUNTER StatExitGuestXcpUnk;
1007	STAMCOUNTER StatExitInvlpg;
1008	STAMCOUNTER StatExitInvd;
1009	STAMCOUNTER StatExitWbinvd;
1010	STAMCOUNTER StatExitPause;
1011	STAMCOUNTER StatExitCpuid;
1012	STAMCOUNTER StatExitRdtsc;
1013	STAMCOUNTER StatExitRdtscp;
1014	STAMCOUNTER StatExitRdpmc;
1015	STAMCOUNTER StatExitVmcall;
1016	STAMCOUNTER StatExitRdrand;
1017	STAMCOUNTER StatExitCli;
1018	STAMCOUNTER StatExitSti;
1019	STAMCOUNTER StatExitPushf;
1020	STAMCOUNTER StatExitPopf;
1021	STAMCOUNTER StatExitIret;
1022	STAMCOUNTER StatExitInt;
1023	STAMCOUNTER StatExitCRxWrite[16];
1024	STAMCOUNTER StatExitCRxRead[16];
1025	STAMCOUNTER StatExitDRxWrite;
1026	STAMCOUNTER StatExitDRxRead;
1027	STAMCOUNTER StatExitRdmsr;
1028	STAMCOUNTER StatExitWrmsr;
1029	STAMCOUNTER StatExitClts;
1030	STAMCOUNTER StatExitXdtrAccess;
1031	STAMCOUNTER StatExitHlt;
1032	STAMCOUNTER StatExitMwait;
1033	STAMCOUNTER StatExitMonitor;
1034	STAMCOUNTER StatExitLmsw;
1035	STAMCOUNTER StatExitIOWrite;
1036	STAMCOUNTER StatExitIORead;
1037	STAMCOUNTER StatExitIOStringWrite;
1038	STAMCOUNTER StatExitIOStringRead;
1039	STAMCOUNTER StatExitIntWindow;
1040	STAMCOUNTER StatExitExtInt;
1041	STAMCOUNTER StatExitHostNmiInGC;
1042	STAMCOUNTER StatExitPreemptTimer;
1043	STAMCOUNTER StatExitTprBelowThreshold;
1044	STAMCOUNTER StatExitTaskSwitch;
1045	STAMCOUNTER StatExitMtf;
1046	STAMCOUNTER StatExitApicAccess;
1047	STAMCOUNTER StatPendingHostIrq;
1048
1049	STAMCOUNTER StatFlushPage;
1050	STAMCOUNTER StatFlushPageManual;
1051	STAMCOUNTER StatFlushPhysPageManual;
1052	STAMCOUNTER StatFlushTlb;
1053	STAMCOUNTER StatFlushTlbManual;
1054	STAMCOUNTER StatFlushTlbWorldSwitch;
1055	STAMCOUNTER StatNoFlushTlbWorldSwitch;
1056	STAMCOUNTER StatFlushEntire;
1057	STAMCOUNTER StatFlushAsid;
1058	STAMCOUNTER StatFlushNestedPaging;
1059	STAMCOUNTER StatFlushTlbInvlpgVirt;
1060	STAMCOUNTER StatFlushTlbInvlpgPhys;
1061	STAMCOUNTER StatTlbShootdown;
1062	STAMCOUNTER StatTlbShootdownFlush;
1063
1064	STAMCOUNTER StatSwitchTprMaskedIrq;
1065	STAMCOUNTER StatSwitchGuestIrq;
1066	STAMCOUNTER StatSwitchHmToR3FF;
1067	STAMCOUNTER StatSwitchExitToR3;
1068	STAMCOUNTER StatSwitchLongJmpToR3;
1069	STAMCOUNTER StatSwitchMaxResumeLoops;
1070	STAMCOUNTER StatSwitchHltToR3;
1071	STAMCOUNTER StatSwitchApicAccessToR3;
1072	STAMCOUNTER StatSwitchPreempt;
1073	STAMCOUNTER StatSwitchPreemptSaveHostState;
1074
1075	STAMCOUNTER StatTscParavirt;
1076	STAMCOUNTER StatTscOffset;
1077	STAMCOUNTER StatTscIntercept;
1078
1079	STAMCOUNTER StatExitReasonNpf;
1080	STAMCOUNTER StatDRxArmed;
1081	STAMCOUNTER StatDRxContextSwitch;
1082	STAMCOUNTER StatDRxIoCheck;
1083
1084	STAMCOUNTER StatLoadMinimal;
1085	STAMCOUNTER StatLoadFull;
1086
1087	STAMCOUNTER StatVmxCheckBadRmSelBase;
1088	STAMCOUNTER StatVmxCheckBadRmSelLimit;
1089	STAMCOUNTER StatVmxCheckRmOk;
1090
1091	STAMCOUNTER StatVmxCheckBadSel;
1092	STAMCOUNTER StatVmxCheckBadRpl;
1093	STAMCOUNTER StatVmxCheckBadLdt;
1094	STAMCOUNTER StatVmxCheckBadTr;
1095	STAMCOUNTER StatVmxCheckPmOk;
1096
1097	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1098	STAMCOUNTER StatFpu64SwitchBack;
1099	STAMCOUNTER StatDebug64SwitchBack;
1100	#endif
1101
1102	#ifdef VBOX_WITH_STATISTICS
1103	R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
1104	R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
1105	R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
1106	R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
1107	#endif
1108	#ifdef HM_PROFILE_EXIT_DISPATCH
1109	STAMPROFILEADV StatExitDispatch;
1110	#endif
1111	} HMCPU;
1112	/** Pointer to HM VMCPU instance data. */
1113	typedef HMCPU *PHMCPU;
1114	AssertCompileMemberAlignment(HMCPU, vmx, 8);
1115	AssertCompileMemberAlignment(HMCPU, svm, 8);
1116	AssertCompileMemberAlignment(HMCPU, Event, 8);
1117
1118	#ifdef IN_RING0
1119	VMMR0_INT_DECL(PHMGLOBALCPUINFO) hmR0GetCurrentCpu(void);
1120
1121	# ifdef VBOX_STRICT
1122	VMMR0_INT_DECL(void) hmR0DumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
1123	VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
1124	# else
1125	# define hmR0DumpRegs(a, b ,c) do { } while (0)
1126	# define hmR0DumpDescriptor(a, b, c) do { } while (0)
1127	# endif /* VBOX_STRICT */
1128
1129	# ifdef VBOX_WITH_KERNEL_USING_XMM
1130	DECLASM(int) hmR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu, PFNHMVMXSTARTVM pfnStartVM);
1131	DECLASM(int) hmR0SVMRunWrapXMM(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu, PFNHMSVMVMRUN pfnVMRun);
1132	# endif
1133
1134	#endif /* IN_RING0 */
1135
1136	/** @} */
1137
1138	RT_C_DECLS_END
1139
1140	#endif
1141

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source: vbox/trunk/src/VBox/VMM/include/HMInternal.h@ 71204

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