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source: vbox/trunk/src/VBox/VMM/include/CPUMInternal.mac@ 87600

最後變更 在這個檔案從87600是 87522,由 vboxsync 提交於 4 年 前

VMM/HM: Moved CPUMCTX::fWorldSwitcher to HMR0PERVCPU::fWorldSwitcher. bugref:9453 bugref:9087
  • 屬性 svn:eol-style 設為 native
  • 屬性 svn:keywords 設為 Id Revision
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1; $Id: CPUMInternal.mac 87522 2021-02-01 22:32:33Z vboxsync $
2;; @file
3; CPUM - Internal header file (asm).
4;
5
6;
7; Copyright (C) 2006-2020 Oracle Corporation
8;
9; This file is part of VirtualBox Open Source Edition (OSE), as
10; available from http://www.alldomusa.eu.org. This file is free software;
11; you can redistribute it and/or modify it under the terms of the GNU
12; General Public License (GPL) as published by the Free Software
13; Foundation, in version 2 as it comes in the "COPYING" file of the
14; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16;
17
18%include "VBox/asmdefs.mac"
19%include "VBox/vmm/cpum.mac"
20
21;; Check sanity.
22%ifdef VBOX_WITH_KERNEL_USING_XMM
23 %ifndef IN_RING0
24 %error "What? We've got code assuming VBOX_WITH_KERNEL_USING_XMM is only defined in ring-0!"
25 %endif
26%endif
27
28;; For numeric expressions
29%ifdef RT_ARCH_AMD64
30 %define CPUM_IS_AMD64 1
31%else
32 %define CPUM_IS_AMD64 0
33%endif
34
35
36;;
37; CPU info
38struc CPUMINFO
39 .cMsrRanges resd 1 ; uint32_t
40 .fMsrMask resd 1 ; uint32_t
41 .fMxCsrMask resd 1 ; uint32_t
42 .cCpuIdLeaves resd 1 ; uint32_t
43 .iFirstExtCpuIdLeaf resd 1 ; uint32_t
44 .enmUnknownCpuIdMethod resd 1 ; CPUMUNKNOWNCPUID
45 .DefCpuId resb CPUMCPUID_size ; CPUMCPUID
46 .uScalableBusFreq resq 1 ; uint64_t
47 .paMsrRangesR0 RTR0PTR_RES 1 ; R0PTRTYPE(PCPUMMSRRANGE)
48 .paCpuIdLeavesR0 RTR0PTR_RES 1 ; R0PTRTYPE(PCPUMCPUIDLEAF)
49 .paMsrRangesR3 RTR3PTR_RES 1 ; R3PTRTYPE(PCPUMMSRRANGE)
50 .paCpuIdLeavesR3 RTR3PTR_RES 1 ; R3PTRTYPE(PCPUMCPUIDLEAF)
51endstruc
52
53
54%define CPUM_USED_FPU_HOST RT_BIT(0)
55%define CPUM_USED_FPU_GUEST RT_BIT(10)
56%define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
57%define CPUM_USED_MANUAL_XMM_RESTORE RT_BIT(2)
58%define CPUM_USE_SYSENTER RT_BIT(3)
59%define CPUM_USE_SYSCALL RT_BIT(4)
60%define CPUM_USE_DEBUG_REGS_HOST RT_BIT(5)
61%define CPUM_USED_DEBUG_REGS_HOST RT_BIT(6)
62%define CPUM_USE_DEBUG_REGS_HYPER RT_BIT(7)
63%define CPUM_USED_DEBUG_REGS_HYPER RT_BIT(8)
64%define CPUM_USED_DEBUG_REGS_GUEST RT_BIT(9)
65%define CPUM_USE_FFXSR_LEAKY RT_BIT(19)
66%define CPUM_USE_SUPPORTS_LONGMODE RT_BIT(20)
67
68%define CPUM_HANDLER_DS 1
69%define CPUM_HANDLER_ES 2
70%define CPUM_HANDLER_FS 3
71%define CPUM_HANDLER_GS 4
72%define CPUM_HANDLER_IRET 5
73%define CPUM_HANDLER_TYPEMASK 0ffh
74%define CPUM_HANDLER_CTXCORE_IN_EBP RT_BIT(31)
75
76
77struc CPUM
78 ;...
79 .fHostUseFlags resd 1
80
81 ; CR4 masks
82 .CR4.AndMask resd 1
83 .CR4.OrMask resd 1
84 .u8PortableCpuIdLevel resb 1
85 .fPendingRestore resb 1
86
87 alignb 8
88 .fXStateGuestMask resq 1
89 .fXStateHostMask resq 1
90
91 alignb 64
92 .HostFeatures resb 48
93 .GuestFeatures resb 48
94 .GuestInfo resb RTHCPTR_CB*4 + 4*12
95
96 ; Patch manager saved state compatability CPUID leaf arrays
97 .aGuestCpuIdPatmStd resb 16*6
98 .aGuestCpuIdPatmExt resb 16*10
99 .aGuestCpuIdPatmCentaur resb 16*4
100
101 alignb 8
102 .cMsrWrites resq 1
103 .cMsrWritesToIgnoredBits resq 1
104 .cMsrWritesRaiseGp resq 1
105 .cMsrWritesUnknown resq 1
106 .cMsrReads resq 1
107 .cMsrReadsRaiseGp resq 1
108 .cMsrReadsUnknown resq 1
109endstruc
110
111struc CPUMCPU
112 ;
113 ; Guest context state
114 ; (Identical to the .Hyper chunk below and to CPUMCTX in cpum.mac.)
115 ;
116 .Guest resq 0
117 .Guest.eax resq 1
118 .Guest.ecx resq 1
119 .Guest.edx resq 1
120 .Guest.ebx resq 1
121 .Guest.esp resq 1
122 .Guest.ebp resq 1
123 .Guest.esi resq 1
124 .Guest.edi resq 1
125 .Guest.r8 resq 1
126 .Guest.r9 resq 1
127 .Guest.r10 resq 1
128 .Guest.r11 resq 1
129 .Guest.r12 resq 1
130 .Guest.r13 resq 1
131 .Guest.r14 resq 1
132 .Guest.r15 resq 1
133 .Guest.es.Sel resw 1
134 .Guest.es.PaddingSel resw 1
135 .Guest.es.ValidSel resw 1
136 .Guest.es.fFlags resw 1
137 .Guest.es.u64Base resq 1
138 .Guest.es.u32Limit resd 1
139 .Guest.es.Attr resd 1
140 .Guest.cs.Sel resw 1
141 .Guest.cs.PaddingSel resw 1
142 .Guest.cs.ValidSel resw 1
143 .Guest.cs.fFlags resw 1
144 .Guest.cs.u64Base resq 1
145 .Guest.cs.u32Limit resd 1
146 .Guest.cs.Attr resd 1
147 .Guest.ss.Sel resw 1
148 .Guest.ss.PaddingSel resw 1
149 .Guest.ss.ValidSel resw 1
150 .Guest.ss.fFlags resw 1
151 .Guest.ss.u64Base resq 1
152 .Guest.ss.u32Limit resd 1
153 .Guest.ss.Attr resd 1
154 .Guest.ds.Sel resw 1
155 .Guest.ds.PaddingSel resw 1
156 .Guest.ds.ValidSel resw 1
157 .Guest.ds.fFlags resw 1
158 .Guest.ds.u64Base resq 1
159 .Guest.ds.u32Limit resd 1
160 .Guest.ds.Attr resd 1
161 .Guest.fs.Sel resw 1
162 .Guest.fs.PaddingSel resw 1
163 .Guest.fs.ValidSel resw 1
164 .Guest.fs.fFlags resw 1
165 .Guest.fs.u64Base resq 1
166 .Guest.fs.u32Limit resd 1
167 .Guest.fs.Attr resd 1
168 .Guest.gs.Sel resw 1
169 .Guest.gs.PaddingSel resw 1
170 .Guest.gs.ValidSel resw 1
171 .Guest.gs.fFlags resw 1
172 .Guest.gs.u64Base resq 1
173 .Guest.gs.u32Limit resd 1
174 .Guest.gs.Attr resd 1
175 .Guest.eip resq 1
176 .Guest.eflags resq 1
177 .Guest.cr0 resq 1
178 .Guest.cr2 resq 1
179 .Guest.cr3 resq 1
180 .Guest.cr4 resq 1
181 .Guest.dr resq 8
182 .Guest.gdtrPadding resw 3
183 .Guest.gdtr resw 0
184 .Guest.gdtr.cbGdt resw 1
185 .Guest.gdtr.pGdt resq 1
186 .Guest.idtrPadding resw 3
187 .Guest.idtr resw 0
188 .Guest.idtr.cbIdt resw 1
189 .Guest.idtr.pIdt resq 1
190 .Guest.ldtr.Sel resw 1
191 .Guest.ldtr.PaddingSel resw 1
192 .Guest.ldtr.ValidSel resw 1
193 .Guest.ldtr.fFlags resw 1
194 .Guest.ldtr.u64Base resq 1
195 .Guest.ldtr.u32Limit resd 1
196 .Guest.ldtr.Attr resd 1
197 .Guest.tr.Sel resw 1
198 .Guest.tr.PaddingSel resw 1
199 .Guest.tr.ValidSel resw 1
200 .Guest.tr.fFlags resw 1
201 .Guest.tr.u64Base resq 1
202 .Guest.tr.u32Limit resd 1
203 .Guest.tr.Attr resd 1
204 .Guest.SysEnter.cs resb 8
205 .Guest.SysEnter.eip resb 8
206 .Guest.SysEnter.esp resb 8
207 .Guest.msrEFER resb 8
208 .Guest.msrSTAR resb 8
209 .Guest.msrPAT resb 8
210 .Guest.msrLSTAR resb 8
211 .Guest.msrCSTAR resb 8
212 .Guest.msrSFMASK resb 8
213 .Guest.msrKERNELGSBASE resb 8
214 .Guest.uMsrPadding0 resb 8
215 alignb 8
216 .Guest.aXcr resq 2
217 .Guest.fXStateMask resq 1
218 .Guest.pXStateR0 RTR0PTR_RES 1
219 alignb 8
220 .Guest.pXStateR3 RTR3PTR_RES 1
221 alignb 8
222 .Guest.aoffXState resw 64
223 .Guest.fUsedFpuGuest resb 1
224 alignb 8
225 .Guest.fExtrn resq 1
226 alignb 8
227 .Guest.hwvirt.svm.uMsrHSavePa resq 1
228 .Guest.hwvirt.svm.GCPhysVmcb resq 1
229 .Guest.hwvirt.svm.pVmcbR0 RTR0PTR_RES 1
230 alignb 8
231 .Guest.hwvirt.svm.pVmcbR3 RTR3PTR_RES 1
232 alignb 8
233 .Guest.hwvirt.svm.HostState resb 184
234 .Guest.hwvirt.svm.uPrevPauseTick resq 1
235 .Guest.hwvirt.svm.cPauseFilter resw 1
236 .Guest.hwvirt.svm.cPauseFilterThreshold resw 1
237 .Guest.hwvirt.svm.fInterceptEvents resb 1
238 alignb 8
239 .Guest.hwvirt.svm.pvMsrBitmapR0 RTR0PTR_RES 1
240 alignb 8
241 .Guest.hwvirt.svm.pvMsrBitmapR3 RTR3PTR_RES 1
242 alignb 8
243 .Guest.hwvirt.svm.pvIoBitmapR0 RTR0PTR_RES 1
244 alignb 8
245 .Guest.hwvirt.svm.pvIoBitmapR3 RTR3PTR_RES 1
246 alignb 8
247 .Guest.hwvirt.svm.HCPhysVmcb RTHCPHYS_RES 1
248 .Guest.hwvirt.svm.abPadding0 resb 272
249 .Guest.hwvirt.enmHwvirt resd 1
250 .Guest.hwvirt.fGif resb 1
251 alignb 8
252 .Guest.hwvirt.fLocalForcedActions resd 1
253 alignb 64
254
255 .GuestMsrs resq 0
256 .GuestMsrs.au64 resq 64
257
258 ;
259 ; Other stuff.
260 ;
261 .pNestedVmxPreemptTimerR0 RTR0PTR_RES 1
262 .pNestedVmxPreemptTimerR3 RTR3PTR_RES 1
263
264 .fUseFlags resd 1
265 .fChanged resd 1
266 .u32RetCode resd 1
267
268%ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
269 .fApicDisVectors resd 1
270 .pvApicBase RTR0PTR_RES 1
271 .fX2Apic resb 1
272%else
273 .abPadding3 resb (4 + RTR0PTR_CB + 1)
274%endif
275
276 .fCpuIdApicFeatureVisible resb 1
277
278 .abPadding2 resb (64 - (RTR0PTR_CB + RTR3PTR_CB + 12 + 4 + RTR0PTR_CB + 1 + 1))
279
280 ;
281 ; Host context state
282 ;
283 alignb 64
284 .Host resb 0
285 ;.Host.rax resq 1 - scratch
286 .Host.rbx resq 1
287 ;.Host.rcx resq 1 - scratch
288 ;.Host.rdx resq 1 - scratch
289 .Host.rdi resq 1
290 .Host.rsi resq 1
291 .Host.rbp resq 1
292 .Host.rsp resq 1
293 ;.Host.r8 resq 1 - scratch
294 ;.Host.r9 resq 1 - scratch
295 .Host.r10 resq 1
296 .Host.r11 resq 1
297 .Host.r12 resq 1
298 .Host.r13 resq 1
299 .Host.r14 resq 1
300 .Host.r15 resq 1
301 ;.Host.rip resd 1 - scratch
302 .Host.rflags resq 1
303 .Host.ss resw 1
304 .Host.ssPadding resw 1
305 .Host.gs resw 1
306 .Host.gsPadding resw 1
307 .Host.fs resw 1
308 .Host.fsPadding resw 1
309 .Host.es resw 1
310 .Host.esPadding resw 1
311 .Host.ds resw 1
312 .Host.dsPadding resw 1
313 .Host.cs resw 1
314 .Host.csPadding resw 1
315
316 .Host.cr0Fpu:
317 .Host.cr0 resq 1
318 ;.Host.cr2 resq 1 - scratch
319 .Host.cr3 resq 1
320 .Host.cr4 resq 1
321 .Host.cr8 resq 1
322
323 .Host.dr0 resq 1
324 .Host.dr1 resq 1
325 .Host.dr2 resq 1
326 .Host.dr3 resq 1
327 .Host.dr6 resq 1
328 .Host.dr7 resq 1
329
330 .Host.gdtr resb 10 ; GDT limit + linear address
331 .Host.gdtrPadding resw 1
332 .Host.idtr resb 10 ; IDT limit + linear address
333 .Host.idtrPadding resw 1
334 .Host.ldtr resw 1
335 .Host.ldtrPadding resw 1
336 .Host.tr resw 1
337 .Host.trPadding resw 1
338
339 .Host.SysEnter.cs resq 1
340 .Host.SysEnter.eip resq 1
341 .Host.SysEnter.esp resq 1
342 .Host.FSbase resq 1
343 .Host.GSbase resq 1
344 .Host.efer resq 1
345 .Host.auPadding resb 4
346 alignb RTR0PTR_CB
347 .Host.pXStateR0 RTR0PTR_RES 1
348 .Host.pXStateR3 RTR3PTR_RES 1
349 alignb 8
350 .Host.xcr0 resq 1
351 .Host.fXStateMask resq 1
352
353 ;
354 ; Hypervisor Context.
355 ;
356 alignb 64
357 .Hyper resq 0
358 .Hyper.dr resq 8
359 .Hyper.cr3 resq 1
360 alignb 64
361
362%ifdef VBOX_WITH_CRASHDUMP_MAGIC
363 .aMagic resb 56
364 .uMagic resq 1
365%endif
366endstruc
367
368
369
370%if 0 ; Currently not used anywhere.
371;;
372; Macro for FXSAVE/FXRSTOR leaky behaviour on AMD CPUs, see cpumR3CheckLeakyFpu().
373;
374; Cleans the FPU state, if necessary, before restoring the FPU.
375;
376; This macro ASSUMES CR0.TS is not set!
377;
378; @param xDX Pointer to CPUMCPU.
379; @uses xAX, EFLAGS
380;
381; Changes here should also be reflected in CPUMRCA.asm's copy!
382;
383%macro CLEANFPU 0
384 test dword [xDX + CPUMCPU.fUseFlags], CPUM_USE_FFXSR_LEAKY
385 jz .nothing_to_clean
386
387 xor eax, eax
388 fnstsw ax ; FSW -> AX.
389 test eax, RT_BIT(7) ; If FSW.ES (bit 7) is set, clear it to not cause FPU exceptions
390 ; while clearing & loading the FPU bits in 'clean_fpu' below.
391 jz .clean_fpu
392 fnclex
393
394.clean_fpu:
395 ffree st7 ; Clear FPU stack register(7)'s tag entry to prevent overflow if a wraparound occurs.
396 ; for the upcoming push (load)
397 fild dword [g_r32_Zero xWrtRIP] ; Explicit FPU load to overwrite FIP, FOP, FDP registers in the FPU.
398.nothing_to_clean:
399%endmacro
400%endif ; Unused.
401
402
403;;
404; Makes sure we don't trap (#NM) accessing the FPU.
405;
406; In ring-0 this is a bit of work since we may have try convince the host kernel
407; to do the work for us, also, we must report any CR0 changes back to HMR0VMX
408; via the VINF_CPUM_HOST_CR0_MODIFIED status code.
409;
410; If we end up clearing CR0.TS/EM ourselves in ring-0, we'll save the original
411; value in CPUMCPU.Host.cr0Fpu. If we don't, we'll store zero there. (See also
412; CPUMRZ_RESTORE_CR0_IF_TS_OR_EM_SET.)
413;
414; In raw-mode we will always have to clear TS and it will be recalculated
415; elsewhere and thus needs no saving.
416;
417; @param %1 Register to return the return status code in.
418; @param %2 Temporary scratch register.
419; @param %3 Ring-0 only, register pointing to the CPUMCPU structure
420; of the EMT we're on.
421; @uses EFLAGS, CR0, %1, %2
422;
423%macro CPUMRZ_TOUCH_FPU_CLEAR_CR0_FPU_TRAPS_SET_RC 3
424 ;
425 ; ring-0 - slightly complicated (than old raw-mode).
426 ;
427 xor %1, %1 ; 0 / VINF_SUCCESS. Wishing for no CR0 changes.
428 mov [%3 + CPUMCPU.Host.cr0Fpu], %1
429
430 mov %2, cr0
431 test %2, X86_CR0_TS | X86_CR0_EM ; Make sure its safe to access the FPU state.
432 jz %%no_cr0_change
433
434 %ifdef VMM_R0_TOUCH_FPU
435 ; Touch the state and check that the kernel updated CR0 for us.
436 movdqa xmm0, xmm0
437 mov %2, cr0
438 test %2, X86_CR0_TS | X86_CR0_EM
439 jz %%cr0_changed
440 %endif
441
442 ; Save CR0 and clear them flags ourselves.
443 mov [%3 + CPUMCPU.Host.cr0Fpu], %2
444 and %2, ~(X86_CR0_TS | X86_CR0_EM)
445 mov cr0, %2
446
447%%cr0_changed:
448 mov %1, VINF_CPUM_HOST_CR0_MODIFIED
449%%no_cr0_change:
450%endmacro
451
452
453;;
454; Restore CR0 if CR0.TS or CR0.EM were non-zero in the original state.
455;
456; @param %1 The original state to restore (or zero).
457;
458%macro CPUMRZ_RESTORE_CR0_IF_TS_OR_EM_SET 1
459 test %1, X86_CR0_TS | X86_CR0_EM
460 jz %%skip_cr0_restore
461 mov cr0, %1
462%%skip_cr0_restore:
463%endmacro
464
465
466;;
467; Saves the host state.
468;
469; @uses rax, rdx
470; @param pCpumCpu Define for the register containing the CPUMCPU pointer.
471; @param pXState Define for the register containing the extended state pointer.
472;
473%macro CPUMR0_SAVE_HOST 0
474 ;
475 ; Load a couple of registers we'll use later in all branches.
476 ;
477 %ifdef IN_RING0
478 mov pXState, [pCpumCpu + CPUMCPU.Host.pXStateR0]
479 %else
480 %error "Unsupported context!"
481 %endif
482 mov eax, [pCpumCpu + CPUMCPU.Host.fXStateMask]
483
484 ;
485 ; XSAVE or FXSAVE?
486 ;
487 or eax, eax
488 jz %%host_fxsave
489
490 ; XSAVE
491 mov edx, [pCpumCpu + CPUMCPU.Host.fXStateMask + 4]
492 %ifdef RT_ARCH_AMD64
493 o64 xsave [pXState]
494 %else
495 xsave [pXState]
496 %endif
497 jmp %%host_done
498
499 ; FXSAVE
500%%host_fxsave:
501 %ifdef RT_ARCH_AMD64
502 o64 fxsave [pXState] ; Use explicit REX prefix. See @bugref{6398}.
503 %else
504 fxsave [pXState]
505 %endif
506
507%%host_done:
508%endmacro ; CPUMR0_SAVE_HOST
509
510
511;;
512; Loads the host state.
513;
514; @uses rax, rdx
515; @param pCpumCpu Define for the register containing the CPUMCPU pointer.
516; @param pXState Define for the register containing the extended state pointer.
517;
518%macro CPUMR0_LOAD_HOST 0
519 ;
520 ; Load a couple of registers we'll use later in all branches.
521 ;
522 %ifdef IN_RING0
523 mov pXState, [pCpumCpu + CPUMCPU.Host.pXStateR0]
524 %else
525 %error "Unsupported context!"
526 %endif
527 mov eax, [pCpumCpu + CPUMCPU.Host.fXStateMask]
528
529 ;
530 ; XRSTOR or FXRSTOR?
531 ;
532 or eax, eax
533 jz %%host_fxrstor
534
535 ; XRSTOR
536 mov edx, [pCpumCpu + CPUMCPU.Host.fXStateMask + 4]
537 %ifdef RT_ARCH_AMD64
538 o64 xrstor [pXState]
539 %else
540 xrstor [pXState]
541 %endif
542 jmp %%host_done
543
544 ; FXRSTOR
545%%host_fxrstor:
546 %ifdef RT_ARCH_AMD64
547 o64 fxrstor [pXState] ; Use explicit REX prefix. See @bugref{6398}.
548 %else
549 fxrstor [pXState]
550 %endif
551
552%%host_done:
553%endmacro ; CPUMR0_LOAD_HOST
554
555
556
557;; Macro for XSAVE/FXSAVE for the guest FPU but tries to figure out whether to
558; save the 32-bit FPU state or 64-bit FPU state.
559;
560; @param %1 Pointer to CPUMCPU.
561; @param %2 Pointer to XState.
562; @param %3 Force AMD64
563; @param %4 The instruction to use (xsave or fxsave)
564; @uses xAX, xDX, EFLAGS, 20h of stack.
565;
566%macro SAVE_32_OR_64_FPU 4
567%if CPUM_IS_AMD64 || %3
568 ; Save the guest FPU (32-bit or 64-bit), preserves existing broken state. See @bugref{7138}.
569 test dword [pCpumCpu + CPUMCPU.fUseFlags], CPUM_USE_SUPPORTS_LONGMODE
570 jnz short %%save_long_mode_guest
571%endif
572 %4 [pXState]
573%if CPUM_IS_AMD64 || %3
574 jmp %%save_done_32bit_cs_ds
575
576%%save_long_mode_guest:
577 o64 %4 [pXState]
578
579 xor edx, edx
580 cmp dword [pXState + X86FXSTATE.FPUCS], 0
581 jne short %%save_done
582
583 sub rsp, 20h ; Only need 1ch bytes but keep stack aligned otherwise we #GP(0).
584 fnstenv [rsp]
585 movzx eax, word [rsp + 10h]
586 mov [pXState + X86FXSTATE.FPUCS], eax
587 movzx eax, word [rsp + 18h]
588 add rsp, 20h
589 mov [pXState + X86FXSTATE.FPUDS], eax
590%endif
591%%save_done_32bit_cs_ds:
592 mov edx, X86_FXSTATE_RSVD_32BIT_MAGIC
593%%save_done:
594 mov dword [pXState + X86_OFF_FXSTATE_RSVD], edx
595%endmacro ; SAVE_32_OR_64_FPU
596
597
598;;
599; Save the guest state.
600;
601; @uses rax, rdx
602; @param pCpumCpu Define for the register containing the CPUMCPU pointer.
603; @param pXState Define for the register containing the extended state pointer.
604;
605%macro CPUMR0_SAVE_GUEST 0
606 ;
607 ; Load a couple of registers we'll use later in all branches.
608 ;
609 %ifdef IN_RING0
610 mov pXState, [pCpumCpu + CPUMCPU.Guest.pXStateR0]
611 %else
612 %error "Unsupported context!"
613 %endif
614 mov eax, [pCpumCpu + CPUMCPU.Guest.fXStateMask]
615
616 ;
617 ; XSAVE or FXSAVE?
618 ;
619 or eax, eax
620 jz %%guest_fxsave
621
622 ; XSAVE
623 mov edx, [pCpumCpu + CPUMCPU.Guest.fXStateMask + 4]
624 %ifdef VBOX_WITH_KERNEL_USING_XMM
625 and eax, ~CPUM_VOLATILE_XSAVE_GUEST_COMPONENTS ; Already saved in HMR0A.asm.
626 %endif
627 SAVE_32_OR_64_FPU pCpumCpu, pXState, 0, xsave
628 jmp %%guest_done
629
630 ; FXSAVE
631%%guest_fxsave:
632 SAVE_32_OR_64_FPU pCpumCpu, pXState, 0, fxsave
633
634%%guest_done:
635%endmacro ; CPUMR0_SAVE_GUEST
636
637
638;;
639; Wrapper for selecting 32-bit or 64-bit XRSTOR/FXRSTOR according to what SAVE_32_OR_64_FPU did.
640;
641; @param %1 Pointer to CPUMCPU.
642; @param %2 Pointer to XState.
643; @param %3 Force AMD64.
644; @param %4 The instruction to use (xrstor or fxrstor).
645; @uses xAX, xDX, EFLAGS
646;
647%macro RESTORE_32_OR_64_FPU 4
648%if CPUM_IS_AMD64 || %3
649 ; Restore the guest FPU (32-bit or 64-bit), preserves existing broken state. See @bugref{7138}.
650 test dword [pCpumCpu + CPUMCPU.fUseFlags], CPUM_USE_SUPPORTS_LONGMODE
651 jz %%restore_32bit_fpu
652 cmp dword [pXState + X86_OFF_FXSTATE_RSVD], X86_FXSTATE_RSVD_32BIT_MAGIC
653 jne short %%restore_64bit_fpu
654%%restore_32bit_fpu:
655%endif
656 %4 [pXState]
657%if CPUM_IS_AMD64 || %3
658 ; TODO: Restore XMM8-XMM15!
659 jmp short %%restore_fpu_done
660%%restore_64bit_fpu:
661 o64 %4 [pXState]
662%%restore_fpu_done:
663%endif
664%endmacro ; RESTORE_32_OR_64_FPU
665
666
667;;
668; Loads the guest state.
669;
670; @uses rax, rdx
671; @param pCpumCpu Define for the register containing the CPUMCPU pointer.
672; @param pXState Define for the register containing the extended state pointer.
673;
674%macro CPUMR0_LOAD_GUEST 0
675 ;
676 ; Load a couple of registers we'll use later in all branches.
677 ;
678 %ifdef IN_RING0
679 mov pXState, [pCpumCpu + CPUMCPU.Guest.pXStateR0]
680 %else
681 %error "Unsupported context!"
682 %endif
683 mov eax, [pCpumCpu + CPUMCPU.Guest.fXStateMask]
684
685 ;
686 ; XRSTOR or FXRSTOR?
687 ;
688 or eax, eax
689 jz %%guest_fxrstor
690
691 ; XRSTOR
692 mov edx, [pCpumCpu + CPUMCPU.Guest.fXStateMask + 4]
693 %ifdef VBOX_WITH_KERNEL_USING_XMM
694 and eax, ~CPUM_VOLATILE_XSAVE_GUEST_COMPONENTS ; Will be loaded by HMR0A.asm.
695 %endif
696 RESTORE_32_OR_64_FPU pCpumCpu, pXState, 0, xrstor
697 jmp %%guest_done
698
699 ; FXRSTOR
700%%guest_fxrstor:
701 RESTORE_32_OR_64_FPU pCpumCpu, pXState, 0, fxrstor
702
703%%guest_done:
704%endmacro ; CPUMR0_LOAD_GUEST
705
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