VirtualBox

source: vbox/trunk/src/VBox/VMM/include/CPUMInternal.h@ 50590

最後變更 在這個檔案從50590是 50590,由 vboxsync 提交於 11 年 前

CPUM,VMM: More work related to bus, cpu and tsc frequency info. Should cover older core and p6 as well as p4 now.
  • 屬性 svn:eol-style 設為 native
  • 屬性 svn:keywords 設為 Id
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1/* $Id: CPUMInternal.h 50590 2014-02-25 18:51:23Z vboxsync $ */
2/** @file
3 * CPUM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2012 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.alldomusa.eu.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___CPUMInternal_h
19#define ___CPUMInternal_h
20
21#ifndef VBOX_FOR_DTRACE_LIB
22# include <VBox/cdefs.h>
23# include <VBox/types.h>
24# include <VBox/vmm/stam.h>
25# include <iprt/x86.h>
26#else
27# pragma D depends_on library x86.d
28# pragma D depends_on library cpumctx.d
29#endif
30
31
32
33
34/** @defgroup grp_cpum_int Internals
35 * @ingroup grp_cpum
36 * @internal
37 * @{
38 */
39
40/** Flags and types for CPUM fault handlers
41 * @{ */
42/** Type: Load DS */
43#define CPUM_HANDLER_DS 1
44/** Type: Load ES */
45#define CPUM_HANDLER_ES 2
46/** Type: Load FS */
47#define CPUM_HANDLER_FS 3
48/** Type: Load GS */
49#define CPUM_HANDLER_GS 4
50/** Type: IRET */
51#define CPUM_HANDLER_IRET 5
52/** Type mask. */
53#define CPUM_HANDLER_TYPEMASK 0xff
54/** If set EBP points to the CPUMCTXCORE that's being used. */
55#define CPUM_HANDLER_CTXCORE_IN_EBP RT_BIT(31)
56/** @} */
57
58
59/** Use flags (CPUM::fUseFlags).
60 * (Don't forget to sync this with CPUMInternal.mac !)
61 * @{ */
62/** Used the FPU, SSE or such stuff. */
63#define CPUM_USED_FPU RT_BIT(0)
64/** Used the FPU, SSE or such stuff since last we were in REM.
65 * REM syncing is clearing this, lazy FPU is setting it. */
66#define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
67/** The XMM state was manually restored. (AMD only) */
68#define CPUM_USED_MANUAL_XMM_RESTORE RT_BIT(2)
69
70/** Host OS is using SYSENTER and we must NULL the CS. */
71#define CPUM_USE_SYSENTER RT_BIT(3)
72/** Host OS is using SYSENTER and we must NULL the CS. */
73#define CPUM_USE_SYSCALL RT_BIT(4)
74
75/** Debug registers are used by host and that DR7 and DR6 must be saved and
76 * disabled when switching to raw-mode. */
77#define CPUM_USE_DEBUG_REGS_HOST RT_BIT(5)
78/** Records that we've saved the host DRx registers.
79 * In ring-0 this means all (DR0-7), while in raw-mode context this means DR0-3
80 * since DR6 and DR7 are covered by CPUM_USE_DEBUG_REGS_HOST. */
81#define CPUM_USED_DEBUG_REGS_HOST RT_BIT(6)
82/** Set to indicate that we should save host DR0-7 and load the hypervisor debug
83 * registers in the raw-mode world switchers. (See CPUMRecalcHyperDRx.) */
84#define CPUM_USE_DEBUG_REGS_HYPER RT_BIT(7)
85/** Used in ring-0 to indicate that we have loaded the hypervisor debug
86 * registers. */
87#define CPUM_USED_DEBUG_REGS_HYPER RT_BIT(8)
88/** Used in ring-0 to indicate that we have loaded the guest debug
89 * registers (DR0-3 and maybe DR6) for direct use by the guest.
90 * DR7 (and AMD-V DR6) are handled via the VMCB. */
91#define CPUM_USED_DEBUG_REGS_GUEST RT_BIT(9)
92
93
94/** Sync the FPU state on next entry (32->64 switcher only). */
95#define CPUM_SYNC_FPU_STATE RT_BIT(16)
96/** Sync the debug state on next entry (32->64 switcher only). */
97#define CPUM_SYNC_DEBUG_REGS_GUEST RT_BIT(17)
98/** Sync the debug state on next entry (32->64 switcher only).
99 * Almost the same as CPUM_USE_DEBUG_REGS_HYPER in the raw-mode switchers. */
100#define CPUM_SYNC_DEBUG_REGS_HYPER RT_BIT(18)
101/** Host CPU requires fxsave/fxrstor leaky bit handling. */
102#define CPUM_USE_FFXSR_LEAKY RT_BIT(19)
103/** @} */
104
105/* Sanity check. */
106#ifndef VBOX_FOR_DTRACE_LIB
107#if defined(VBOX_WITH_HYBRID_32BIT_KERNEL) && (HC_ARCH_BITS != 32 || R0_ARCH_BITS != 32)
108# error "VBOX_WITH_HYBRID_32BIT_KERNEL is only for 32 bit builds."
109#endif
110#endif
111
112
113/**
114 * MSR read functions.
115 */
116typedef enum CPUMMSRRDFN
117{
118 /** Invalid zero value. */
119 kCpumMsrRdFn_Invalid = 0,
120 /** Return the CPUMMSRRANGE::uValue. */
121 kCpumMsrRdFn_FixedValue,
122 /** Alias to the MSR range starting at the MSR given by
123 * CPUMMSRRANGE::uValue. Must be used in pair with
124 * kCpumMsrWrFn_MsrAlias. */
125 kCpumMsrRdFn_MsrAlias,
126 /** Write only register, GP all read attempts. */
127 kCpumMsrRdFn_WriteOnly,
128
129 kCpumMsrRdFn_Ia32P5McAddr,
130 kCpumMsrRdFn_Ia32P5McType,
131 kCpumMsrRdFn_Ia32TimestampCounter,
132 kCpumMsrRdFn_Ia32PlatformId, /**< Takes real CPU value for reference. */
133 kCpumMsrRdFn_Ia32ApicBase,
134 kCpumMsrRdFn_Ia32FeatureControl,
135 kCpumMsrRdFn_Ia32BiosSignId, /**< Range value returned. */
136 kCpumMsrRdFn_Ia32SmmMonitorCtl,
137 kCpumMsrRdFn_Ia32PmcN,
138 kCpumMsrRdFn_Ia32MonitorFilterLineSize,
139 kCpumMsrRdFn_Ia32MPerf,
140 kCpumMsrRdFn_Ia32APerf,
141 kCpumMsrRdFn_Ia32MtrrCap, /**< Takes real CPU value for reference. */
142 kCpumMsrRdFn_Ia32MtrrPhysBaseN, /**< Takes register number. */
143 kCpumMsrRdFn_Ia32MtrrPhysMaskN, /**< Takes register number. */
144 kCpumMsrRdFn_Ia32MtrrFixed, /**< Takes CPUMCPU offset. */
145 kCpumMsrRdFn_Ia32MtrrDefType,
146 kCpumMsrRdFn_Ia32Pat,
147 kCpumMsrRdFn_Ia32SysEnterCs,
148 kCpumMsrRdFn_Ia32SysEnterEsp,
149 kCpumMsrRdFn_Ia32SysEnterEip,
150 kCpumMsrRdFn_Ia32McgCap,
151 kCpumMsrRdFn_Ia32McgStatus,
152 kCpumMsrRdFn_Ia32McgCtl,
153 kCpumMsrRdFn_Ia32DebugCtl,
154 kCpumMsrRdFn_Ia32SmrrPhysBase,
155 kCpumMsrRdFn_Ia32SmrrPhysMask,
156 kCpumMsrRdFn_Ia32PlatformDcaCap,
157 kCpumMsrRdFn_Ia32CpuDcaCap,
158 kCpumMsrRdFn_Ia32Dca0Cap,
159 kCpumMsrRdFn_Ia32PerfEvtSelN, /**< Range value indicates the register number. */
160 kCpumMsrRdFn_Ia32PerfStatus, /**< Range value returned. */
161 kCpumMsrRdFn_Ia32PerfCtl, /**< Range value returned. */
162 kCpumMsrRdFn_Ia32FixedCtrN, /**< Takes register number of start of range. */
163 kCpumMsrRdFn_Ia32PerfCapabilities, /**< Takes reference value. */
164 kCpumMsrRdFn_Ia32FixedCtrCtrl,
165 kCpumMsrRdFn_Ia32PerfGlobalStatus, /**< Takes reference value. */
166 kCpumMsrRdFn_Ia32PerfGlobalCtrl,
167 kCpumMsrRdFn_Ia32PerfGlobalOvfCtrl,
168 kCpumMsrRdFn_Ia32PebsEnable,
169 kCpumMsrRdFn_Ia32ClockModulation, /**< Range value returned. */
170 kCpumMsrRdFn_Ia32ThermInterrupt, /**< Range value returned. */
171 kCpumMsrRdFn_Ia32ThermStatus, /**< Range value returned. */
172 kCpumMsrRdFn_Ia32Therm2Ctl, /**< Range value returned. */
173 kCpumMsrRdFn_Ia32MiscEnable, /**< Range value returned. */
174 kCpumMsrRdFn_Ia32McCtlStatusAddrMiscN, /**< Takes bank number. */
175 kCpumMsrRdFn_Ia32McNCtl2, /**< Takes register number of start of range. */
176 kCpumMsrRdFn_Ia32DsArea,
177 kCpumMsrRdFn_Ia32TscDeadline,
178 kCpumMsrRdFn_Ia32X2ApicN,
179 kCpumMsrRdFn_Ia32DebugInterface,
180 kCpumMsrRdFn_Ia32VmxBase, /**< Takes real value as reference. */
181 kCpumMsrRdFn_Ia32VmxPinbasedCtls, /**< Takes real value as reference. */
182 kCpumMsrRdFn_Ia32VmxProcbasedCtls, /**< Takes real value as reference. */
183 kCpumMsrRdFn_Ia32VmxExitCtls, /**< Takes real value as reference. */
184 kCpumMsrRdFn_Ia32VmxEntryCtls, /**< Takes real value as reference. */
185 kCpumMsrRdFn_Ia32VmxMisc, /**< Takes real value as reference. */
186 kCpumMsrRdFn_Ia32VmxCr0Fixed0, /**< Takes real value as reference. */
187 kCpumMsrRdFn_Ia32VmxCr0Fixed1, /**< Takes real value as reference. */
188 kCpumMsrRdFn_Ia32VmxCr4Fixed0, /**< Takes real value as reference. */
189 kCpumMsrRdFn_Ia32VmxCr4Fixed1, /**< Takes real value as reference. */
190 kCpumMsrRdFn_Ia32VmxVmcsEnum, /**< Takes real value as reference. */
191 kCpumMsrRdFn_Ia32VmxProcBasedCtls2, /**< Takes real value as reference. */
192 kCpumMsrRdFn_Ia32VmxEptVpidCap, /**< Takes real value as reference. */
193 kCpumMsrRdFn_Ia32VmxTruePinbasedCtls, /**< Takes real value as reference. */
194 kCpumMsrRdFn_Ia32VmxTrueProcbasedCtls, /**< Takes real value as reference. */
195 kCpumMsrRdFn_Ia32VmxTrueExitCtls, /**< Takes real value as reference. */
196 kCpumMsrRdFn_Ia32VmxTrueEntryCtls, /**< Takes real value as reference. */
197
198 kCpumMsrRdFn_Amd64Efer,
199 kCpumMsrRdFn_Amd64SyscallTarget,
200 kCpumMsrRdFn_Amd64LongSyscallTarget,
201 kCpumMsrRdFn_Amd64CompSyscallTarget,
202 kCpumMsrRdFn_Amd64SyscallFlagMask,
203 kCpumMsrRdFn_Amd64FsBase,
204 kCpumMsrRdFn_Amd64GsBase,
205 kCpumMsrRdFn_Amd64KernelGsBase,
206 kCpumMsrRdFn_Amd64TscAux,
207
208 kCpumMsrRdFn_IntelEblCrPowerOn,
209 kCpumMsrRdFn_IntelP4EbcHardPowerOn,
210 kCpumMsrRdFn_IntelP4EbcSoftPowerOn,
211 kCpumMsrRdFn_IntelP4EbcFrequencyId,
212 kCpumMsrRdFn_IntelP6FsbFrequency, /**< Takes real value as reference. */
213 kCpumMsrRdFn_IntelPlatformInfo,
214 kCpumMsrRdFn_IntelFlexRatio, /**< Takes real value as reference. */
215 kCpumMsrRdFn_IntelPkgCStConfigControl,
216 kCpumMsrRdFn_IntelPmgIoCaptureBase,
217 kCpumMsrRdFn_IntelLastBranchFromToN,
218 kCpumMsrRdFn_IntelLastBranchFromN,
219 kCpumMsrRdFn_IntelLastBranchToN,
220 kCpumMsrRdFn_IntelLastBranchTos,
221 kCpumMsrRdFn_IntelBblCrCtl,
222 kCpumMsrRdFn_IntelBblCrCtl3,
223 kCpumMsrRdFn_IntelI7TemperatureTarget, /**< Range value returned. */
224 kCpumMsrRdFn_IntelI7MsrOffCoreResponseN,/**< Takes register number. */
225 kCpumMsrRdFn_IntelI7MiscPwrMgmt,
226 kCpumMsrRdFn_IntelP6CrN,
227 kCpumMsrRdFn_IntelCpuId1FeatureMaskEcdx,
228 kCpumMsrRdFn_IntelCpuId1FeatureMaskEax,
229 kCpumMsrRdFn_IntelCpuId80000001FeatureMaskEcdx,
230 kCpumMsrRdFn_IntelI7SandyAesNiCtl,
231 kCpumMsrRdFn_IntelI7TurboRatioLimit, /**< Returns range value. */
232 kCpumMsrRdFn_IntelI7LbrSelect,
233 kCpumMsrRdFn_IntelI7SandyErrorControl,
234 kCpumMsrRdFn_IntelI7VirtualLegacyWireCap,/**< Returns range value. */
235 kCpumMsrRdFn_IntelI7PowerCtl,
236 kCpumMsrRdFn_IntelI7SandyPebsNumAlt,
237 kCpumMsrRdFn_IntelI7PebsLdLat,
238 kCpumMsrRdFn_IntelI7PkgCnResidencyN, /**< Takes C-state number. */
239 kCpumMsrRdFn_IntelI7CoreCnResidencyN, /**< Takes C-state number. */
240 kCpumMsrRdFn_IntelI7SandyVrCurrentConfig,/**< Takes real value as reference. */
241 kCpumMsrRdFn_IntelI7SandyVrMiscConfig, /**< Takes real value as reference. */
242 kCpumMsrRdFn_IntelI7SandyRaplPowerUnit, /**< Takes real value as reference. */
243 kCpumMsrRdFn_IntelI7SandyPkgCnIrtlN, /**< Takes real value as reference. */
244 kCpumMsrRdFn_IntelI7SandyPkgC2Residency, /**< Takes real value as reference. */
245 kCpumMsrRdFn_IntelI7RaplPkgPowerLimit, /**< Takes real value as reference. */
246 kCpumMsrRdFn_IntelI7RaplPkgEnergyStatus, /**< Takes real value as reference. */
247 kCpumMsrRdFn_IntelI7RaplPkgPerfStatus, /**< Takes real value as reference. */
248 kCpumMsrRdFn_IntelI7RaplPkgPowerInfo, /**< Takes real value as reference. */
249 kCpumMsrRdFn_IntelI7RaplDramPowerLimit, /**< Takes real value as reference. */
250 kCpumMsrRdFn_IntelI7RaplDramEnergyStatus,/**< Takes real value as reference. */
251 kCpumMsrRdFn_IntelI7RaplDramPerfStatus, /**< Takes real value as reference. */
252 kCpumMsrRdFn_IntelI7RaplDramPowerInfo, /**< Takes real value as reference. */
253 kCpumMsrRdFn_IntelI7RaplPp0PowerLimit, /**< Takes real value as reference. */
254 kCpumMsrRdFn_IntelI7RaplPp0EnergyStatus, /**< Takes real value as reference. */
255 kCpumMsrRdFn_IntelI7RaplPp0Policy, /**< Takes real value as reference. */
256 kCpumMsrRdFn_IntelI7RaplPp0PerfStatus, /**< Takes real value as reference. */
257 kCpumMsrRdFn_IntelI7RaplPp1PowerLimit, /**< Takes real value as reference. */
258 kCpumMsrRdFn_IntelI7RaplPp1EnergyStatus, /**< Takes real value as reference. */
259 kCpumMsrRdFn_IntelI7RaplPp1Policy, /**< Takes real value as reference. */
260 kCpumMsrRdFn_IntelI7IvyConfigTdpNominal, /**< Takes real value as reference. */
261 kCpumMsrRdFn_IntelI7IvyConfigTdpLevel1, /**< Takes real value as reference. */
262 kCpumMsrRdFn_IntelI7IvyConfigTdpLevel2, /**< Takes real value as reference. */
263 kCpumMsrRdFn_IntelI7IvyConfigTdpControl,
264 kCpumMsrRdFn_IntelI7IvyTurboActivationRatio,
265 kCpumMsrRdFn_IntelI7UncPerfGlobalCtrl,
266 kCpumMsrRdFn_IntelI7UncPerfGlobalStatus,
267 kCpumMsrRdFn_IntelI7UncPerfGlobalOvfCtrl,
268 kCpumMsrRdFn_IntelI7UncPerfFixedCtrCtrl,
269 kCpumMsrRdFn_IntelI7UncPerfFixedCtr,
270 kCpumMsrRdFn_IntelI7UncCBoxConfig,
271 kCpumMsrRdFn_IntelI7UncArbPerfCtrN,
272 kCpumMsrRdFn_IntelI7UncArbPerfEvtSelN,
273 kCpumMsrRdFn_IntelCore2EmttmCrTablesN, /**< Range value returned. */
274 kCpumMsrRdFn_IntelCore2SmmCStMiscInfo,
275 kCpumMsrRdFn_IntelCore1ExtConfig,
276 kCpumMsrRdFn_IntelCore1DtsCalControl,
277 kCpumMsrRdFn_IntelCore2PeciControl,
278
279 kCpumMsrRdFn_P6LastBranchFromIp,
280 kCpumMsrRdFn_P6LastBranchToIp,
281 kCpumMsrRdFn_P6LastIntFromIp,
282 kCpumMsrRdFn_P6LastIntToIp,
283
284 kCpumMsrRdFn_AmdFam15hTscRate,
285 kCpumMsrRdFn_AmdFam15hLwpCfg,
286 kCpumMsrRdFn_AmdFam15hLwpCbAddr,
287 kCpumMsrRdFn_AmdFam10hMc4MiscN,
288 kCpumMsrRdFn_AmdK8PerfCtlN,
289 kCpumMsrRdFn_AmdK8PerfCtrN,
290 kCpumMsrRdFn_AmdK8SysCfg, /**< Range value returned. */
291 kCpumMsrRdFn_AmdK8HwCr,
292 kCpumMsrRdFn_AmdK8IorrBaseN,
293 kCpumMsrRdFn_AmdK8IorrMaskN,
294 kCpumMsrRdFn_AmdK8TopOfMemN,
295 kCpumMsrRdFn_AmdK8NbCfg1,
296 kCpumMsrRdFn_AmdK8McXcptRedir,
297 kCpumMsrRdFn_AmdK8CpuNameN,
298 kCpumMsrRdFn_AmdK8HwThermalCtrl, /**< Range value returned. */
299 kCpumMsrRdFn_AmdK8SwThermalCtrl,
300 kCpumMsrRdFn_AmdK8FidVidControl, /**< Range value returned. */
301 kCpumMsrRdFn_AmdK8FidVidStatus, /**< Range value returned. */
302 kCpumMsrRdFn_AmdK8McCtlMaskN,
303 kCpumMsrRdFn_AmdK8SmiOnIoTrapN,
304 kCpumMsrRdFn_AmdK8SmiOnIoTrapCtlSts,
305 kCpumMsrRdFn_AmdK8IntPendingMessage,
306 kCpumMsrRdFn_AmdK8SmiTriggerIoCycle,
307 kCpumMsrRdFn_AmdFam10hMmioCfgBaseAddr,
308 kCpumMsrRdFn_AmdFam10hTrapCtlMaybe,
309 kCpumMsrRdFn_AmdFam10hPStateCurLimit, /**< Returns range value. */
310 kCpumMsrRdFn_AmdFam10hPStateControl, /**< Returns range value. */
311 kCpumMsrRdFn_AmdFam10hPStateStatus, /**< Returns range value. */
312 kCpumMsrRdFn_AmdFam10hPStateN, /**< Returns range value. This isn't an register index! */
313 kCpumMsrRdFn_AmdFam10hCofVidControl, /**< Returns range value. */
314 kCpumMsrRdFn_AmdFam10hCofVidStatus, /**< Returns range value. */
315 kCpumMsrRdFn_AmdFam10hCStateIoBaseAddr,
316 kCpumMsrRdFn_AmdFam10hCpuWatchdogTimer,
317 kCpumMsrRdFn_AmdK8SmmBase,
318 kCpumMsrRdFn_AmdK8SmmAddr,
319 kCpumMsrRdFn_AmdK8SmmMask,
320 kCpumMsrRdFn_AmdK8VmCr,
321 kCpumMsrRdFn_AmdK8IgnNe,
322 kCpumMsrRdFn_AmdK8SmmCtl,
323 kCpumMsrRdFn_AmdK8VmHSavePa,
324 kCpumMsrRdFn_AmdFam10hVmLockKey,
325 kCpumMsrRdFn_AmdFam10hSmmLockKey,
326 kCpumMsrRdFn_AmdFam10hLocalSmiStatus,
327 kCpumMsrRdFn_AmdFam10hOsVisWrkIdLength,
328 kCpumMsrRdFn_AmdFam10hOsVisWrkStatus,
329 kCpumMsrRdFn_AmdFam16hL2IPerfCtlN,
330 kCpumMsrRdFn_AmdFam16hL2IPerfCtrN,
331 kCpumMsrRdFn_AmdFam15hNorthbridgePerfCtlN,
332 kCpumMsrRdFn_AmdFam15hNorthbridgePerfCtrN,
333 kCpumMsrRdFn_AmdK7MicrocodeCtl, /**< Returns range value. */
334 kCpumMsrRdFn_AmdK7ClusterIdMaybe, /**< Returns range value. */
335 kCpumMsrRdFn_AmdK8CpuIdCtlStd07hEbax,
336 kCpumMsrRdFn_AmdK8CpuIdCtlStd06hEcx,
337 kCpumMsrRdFn_AmdK8CpuIdCtlStd01hEdcx,
338 kCpumMsrRdFn_AmdK8CpuIdCtlExt01hEdcx,
339 kCpumMsrRdFn_AmdK8PatchLevel, /**< Returns range value. */
340 kCpumMsrRdFn_AmdK7DebugStatusMaybe,
341 kCpumMsrRdFn_AmdK7BHTraceBaseMaybe,
342 kCpumMsrRdFn_AmdK7BHTracePtrMaybe,
343 kCpumMsrRdFn_AmdK7BHTraceLimitMaybe,
344 kCpumMsrRdFn_AmdK7HardwareDebugToolCfgMaybe,
345 kCpumMsrRdFn_AmdK7FastFlushCountMaybe,
346 kCpumMsrRdFn_AmdK7NodeId,
347 kCpumMsrRdFn_AmdK7DrXAddrMaskN, /**< Takes register index. */
348 kCpumMsrRdFn_AmdK7Dr0DataMatchMaybe,
349 kCpumMsrRdFn_AmdK7Dr0DataMaskMaybe,
350 kCpumMsrRdFn_AmdK7LoadStoreCfg,
351 kCpumMsrRdFn_AmdK7InstrCacheCfg,
352 kCpumMsrRdFn_AmdK7DataCacheCfg,
353 kCpumMsrRdFn_AmdK7BusUnitCfg,
354 kCpumMsrRdFn_AmdK7DebugCtl2Maybe,
355 kCpumMsrRdFn_AmdFam15hFpuCfg,
356 kCpumMsrRdFn_AmdFam15hDecoderCfg,
357 kCpumMsrRdFn_AmdFam10hBusUnitCfg2,
358 kCpumMsrRdFn_AmdFam15hCombUnitCfg,
359 kCpumMsrRdFn_AmdFam15hCombUnitCfg2,
360 kCpumMsrRdFn_AmdFam15hCombUnitCfg3,
361 kCpumMsrRdFn_AmdFam15hExecUnitCfg,
362 kCpumMsrRdFn_AmdFam15hLoadStoreCfg2,
363 kCpumMsrRdFn_AmdFam10hIbsFetchCtl,
364 kCpumMsrRdFn_AmdFam10hIbsFetchLinAddr,
365 kCpumMsrRdFn_AmdFam10hIbsFetchPhysAddr,
366 kCpumMsrRdFn_AmdFam10hIbsOpExecCtl,
367 kCpumMsrRdFn_AmdFam10hIbsOpRip,
368 kCpumMsrRdFn_AmdFam10hIbsOpData,
369 kCpumMsrRdFn_AmdFam10hIbsOpData2,
370 kCpumMsrRdFn_AmdFam10hIbsOpData3,
371 kCpumMsrRdFn_AmdFam10hIbsDcLinAddr,
372 kCpumMsrRdFn_AmdFam10hIbsDcPhysAddr,
373 kCpumMsrRdFn_AmdFam10hIbsCtl,
374 kCpumMsrRdFn_AmdFam14hIbsBrTarget,
375
376 /** End of valid MSR read function indexes. */
377 kCpumMsrRdFn_End
378} CPUMMSRRDFN;
379
380/**
381 * MSR write functions.
382 */
383typedef enum CPUMMSRWRFN
384{
385 /** Invalid zero value. */
386 kCpumMsrWrFn_Invalid = 0,
387 /** Writes are ignored, the fWrGpMask is observed though. */
388 kCpumMsrWrFn_IgnoreWrite,
389 /** Writes cause GP(0) to be raised, the fWrGpMask should be UINT64_MAX. */
390 kCpumMsrWrFn_ReadOnly,
391 /** Alias to the MSR range starting at the MSR given by
392 * CPUMMSRRANGE::uValue. Must be used in pair with
393 * kCpumMsrRdFn_MsrAlias. */
394 kCpumMsrWrFn_MsrAlias,
395
396 kCpumMsrWrFn_Ia32P5McAddr,
397 kCpumMsrWrFn_Ia32P5McType,
398 kCpumMsrWrFn_Ia32TimestampCounter,
399 kCpumMsrWrFn_Ia32ApicBase,
400 kCpumMsrWrFn_Ia32FeatureControl,
401 kCpumMsrWrFn_Ia32BiosSignId,
402 kCpumMsrWrFn_Ia32BiosUpdateTrigger,
403 kCpumMsrWrFn_Ia32SmmMonitorCtl,
404 kCpumMsrWrFn_Ia32PmcN,
405 kCpumMsrWrFn_Ia32MonitorFilterLineSize,
406 kCpumMsrWrFn_Ia32MPerf,
407 kCpumMsrWrFn_Ia32APerf,
408 kCpumMsrWrFn_Ia32MtrrPhysBaseN, /**< Takes register number. */
409 kCpumMsrWrFn_Ia32MtrrPhysMaskN, /**< Takes register number. */
410 kCpumMsrWrFn_Ia32MtrrFixed, /**< Takes CPUMCPU offset. */
411 kCpumMsrWrFn_Ia32MtrrDefType,
412 kCpumMsrWrFn_Ia32Pat,
413 kCpumMsrWrFn_Ia32SysEnterCs,
414 kCpumMsrWrFn_Ia32SysEnterEsp,
415 kCpumMsrWrFn_Ia32SysEnterEip,
416 kCpumMsrWrFn_Ia32McgStatus,
417 kCpumMsrWrFn_Ia32McgCtl,
418 kCpumMsrWrFn_Ia32DebugCtl,
419 kCpumMsrWrFn_Ia32SmrrPhysBase,
420 kCpumMsrWrFn_Ia32SmrrPhysMask,
421 kCpumMsrWrFn_Ia32PlatformDcaCap,
422 kCpumMsrWrFn_Ia32Dca0Cap,
423 kCpumMsrWrFn_Ia32PerfEvtSelN, /**< Range value indicates the register number. */
424 kCpumMsrWrFn_Ia32PerfStatus,
425 kCpumMsrWrFn_Ia32PerfCtl,
426 kCpumMsrWrFn_Ia32FixedCtrN, /**< Takes register number of start of range. */
427 kCpumMsrWrFn_Ia32PerfCapabilities,
428 kCpumMsrWrFn_Ia32FixedCtrCtrl,
429 kCpumMsrWrFn_Ia32PerfGlobalStatus,
430 kCpumMsrWrFn_Ia32PerfGlobalCtrl,
431 kCpumMsrWrFn_Ia32PerfGlobalOvfCtrl,
432 kCpumMsrWrFn_Ia32PebsEnable,
433 kCpumMsrWrFn_Ia32ClockModulation,
434 kCpumMsrWrFn_Ia32ThermInterrupt,
435 kCpumMsrWrFn_Ia32ThermStatus,
436 kCpumMsrWrFn_Ia32Therm2Ctl,
437 kCpumMsrWrFn_Ia32MiscEnable,
438 kCpumMsrWrFn_Ia32McCtlStatusAddrMiscN, /**< Takes bank number. */
439 kCpumMsrWrFn_Ia32McNCtl2, /**< Takes register number of start of range. */
440 kCpumMsrWrFn_Ia32DsArea,
441 kCpumMsrWrFn_Ia32TscDeadline,
442 kCpumMsrWrFn_Ia32X2ApicN,
443 kCpumMsrWrFn_Ia32DebugInterface,
444
445 kCpumMsrWrFn_Amd64Efer,
446 kCpumMsrWrFn_Amd64SyscallTarget,
447 kCpumMsrWrFn_Amd64LongSyscallTarget,
448 kCpumMsrWrFn_Amd64CompSyscallTarget,
449 kCpumMsrWrFn_Amd64SyscallFlagMask,
450 kCpumMsrWrFn_Amd64FsBase,
451 kCpumMsrWrFn_Amd64GsBase,
452 kCpumMsrWrFn_Amd64KernelGsBase,
453 kCpumMsrWrFn_Amd64TscAux,
454 kCpumMsrWrFn_IntelEblCrPowerOn,
455 kCpumMsrWrFn_IntelP4EbcHardPowerOn,
456 kCpumMsrWrFn_IntelP4EbcSoftPowerOn,
457 kCpumMsrWrFn_IntelP4EbcFrequencyId,
458 kCpumMsrWrFn_IntelFlexRatio,
459 kCpumMsrWrFn_IntelPkgCStConfigControl,
460 kCpumMsrWrFn_IntelPmgIoCaptureBase,
461 kCpumMsrWrFn_IntelLastBranchFromToN,
462 kCpumMsrWrFn_IntelLastBranchFromN,
463 kCpumMsrWrFn_IntelLastBranchToN,
464 kCpumMsrWrFn_IntelLastBranchTos,
465 kCpumMsrWrFn_IntelBblCrCtl,
466 kCpumMsrWrFn_IntelBblCrCtl3,
467 kCpumMsrWrFn_IntelI7TemperatureTarget,
468 kCpumMsrWrFn_IntelI7MsrOffCoreResponseN, /**< Takes register number. */
469 kCpumMsrWrFn_IntelI7MiscPwrMgmt,
470 kCpumMsrWrFn_IntelP6CrN,
471 kCpumMsrWrFn_IntelCpuId1FeatureMaskEcdx,
472 kCpumMsrWrFn_IntelCpuId1FeatureMaskEax,
473 kCpumMsrWrFn_IntelCpuId80000001FeatureMaskEcdx,
474 kCpumMsrWrFn_IntelI7SandyAesNiCtl,
475 kCpumMsrWrFn_IntelI7TurboRatioLimit,
476 kCpumMsrWrFn_IntelI7LbrSelect,
477 kCpumMsrWrFn_IntelI7SandyErrorControl,
478 kCpumMsrWrFn_IntelI7PowerCtl,
479 kCpumMsrWrFn_IntelI7SandyPebsNumAlt,
480 kCpumMsrWrFn_IntelI7PebsLdLat,
481 kCpumMsrWrFn_IntelI7SandyVrCurrentConfig,
482 kCpumMsrWrFn_IntelI7SandyVrMiscConfig,
483 kCpumMsrWrFn_IntelI7SandyPkgCnIrtlN,
484 kCpumMsrWrFn_IntelI7RaplPkgPowerLimit,
485 kCpumMsrWrFn_IntelI7RaplDramPowerLimit,
486 kCpumMsrWrFn_IntelI7RaplPp0PowerLimit,
487 kCpumMsrWrFn_IntelI7RaplPp0Policy,
488 kCpumMsrWrFn_IntelI7RaplPp1PowerLimit,
489 kCpumMsrWrFn_IntelI7RaplPp1Policy,
490 kCpumMsrWrFn_IntelI7IvyConfigTdpControl,
491 kCpumMsrWrFn_IntelI7IvyTurboActivationRatio,
492 kCpumMsrWrFn_IntelI7UncPerfGlobalCtrl,
493 kCpumMsrWrFn_IntelI7UncPerfGlobalStatus,
494 kCpumMsrWrFn_IntelI7UncPerfGlobalOvfCtrl,
495 kCpumMsrWrFn_IntelI7UncPerfFixedCtrCtrl,
496 kCpumMsrWrFn_IntelI7UncPerfFixedCtr,
497 kCpumMsrWrFn_IntelI7UncArbPerfCtrN,
498 kCpumMsrWrFn_IntelI7UncArbPerfEvtSelN,
499 kCpumMsrWrFn_IntelCore2EmttmCrTablesN,
500 kCpumMsrWrFn_IntelCore2SmmCStMiscInfo,
501 kCpumMsrWrFn_IntelCore1ExtConfig,
502 kCpumMsrWrFn_IntelCore1DtsCalControl,
503 kCpumMsrWrFn_IntelCore2PeciControl,
504
505 kCpumMsrWrFn_P6LastIntFromIp,
506 kCpumMsrWrFn_P6LastIntToIp,
507
508 kCpumMsrWrFn_AmdFam15hTscRate,
509 kCpumMsrWrFn_AmdFam15hLwpCfg,
510 kCpumMsrWrFn_AmdFam15hLwpCbAddr,
511 kCpumMsrWrFn_AmdFam10hMc4MiscN,
512 kCpumMsrWrFn_AmdK8PerfCtlN,
513 kCpumMsrWrFn_AmdK8PerfCtrN,
514 kCpumMsrWrFn_AmdK8SysCfg,
515 kCpumMsrWrFn_AmdK8HwCr,
516 kCpumMsrWrFn_AmdK8IorrBaseN,
517 kCpumMsrWrFn_AmdK8IorrMaskN,
518 kCpumMsrWrFn_AmdK8TopOfMemN,
519 kCpumMsrWrFn_AmdK8NbCfg1,
520 kCpumMsrWrFn_AmdK8McXcptRedir,
521 kCpumMsrWrFn_AmdK8CpuNameN,
522 kCpumMsrWrFn_AmdK8HwThermalCtrl,
523 kCpumMsrWrFn_AmdK8SwThermalCtrl,
524 kCpumMsrWrFn_AmdK8FidVidControl,
525 kCpumMsrWrFn_AmdK8McCtlMaskN,
526 kCpumMsrWrFn_AmdK8SmiOnIoTrapN,
527 kCpumMsrWrFn_AmdK8SmiOnIoTrapCtlSts,
528 kCpumMsrWrFn_AmdK8IntPendingMessage,
529 kCpumMsrWrFn_AmdK8SmiTriggerIoCycle,
530 kCpumMsrWrFn_AmdFam10hMmioCfgBaseAddr,
531 kCpumMsrWrFn_AmdFam10hTrapCtlMaybe,
532 kCpumMsrWrFn_AmdFam10hPStateControl,
533 kCpumMsrWrFn_AmdFam10hPStateStatus,
534 kCpumMsrWrFn_AmdFam10hPStateN,
535 kCpumMsrWrFn_AmdFam10hCofVidControl,
536 kCpumMsrWrFn_AmdFam10hCofVidStatus,
537 kCpumMsrWrFn_AmdFam10hCStateIoBaseAddr,
538 kCpumMsrWrFn_AmdFam10hCpuWatchdogTimer,
539 kCpumMsrWrFn_AmdK8SmmBase,
540 kCpumMsrWrFn_AmdK8SmmAddr,
541 kCpumMsrWrFn_AmdK8SmmMask,
542 kCpumMsrWrFn_AmdK8VmCr,
543 kCpumMsrWrFn_AmdK8IgnNe,
544 kCpumMsrWrFn_AmdK8SmmCtl,
545 kCpumMsrWrFn_AmdK8VmHSavePa,
546 kCpumMsrWrFn_AmdFam10hVmLockKey,
547 kCpumMsrWrFn_AmdFam10hSmmLockKey,
548 kCpumMsrWrFn_AmdFam10hLocalSmiStatus,
549 kCpumMsrWrFn_AmdFam10hOsVisWrkIdLength,
550 kCpumMsrWrFn_AmdFam10hOsVisWrkStatus,
551 kCpumMsrWrFn_AmdFam16hL2IPerfCtlN,
552 kCpumMsrWrFn_AmdFam16hL2IPerfCtrN,
553 kCpumMsrWrFn_AmdFam15hNorthbridgePerfCtlN,
554 kCpumMsrWrFn_AmdFam15hNorthbridgePerfCtrN,
555 kCpumMsrWrFn_AmdK7MicrocodeCtl,
556 kCpumMsrWrFn_AmdK7ClusterIdMaybe,
557 kCpumMsrWrFn_AmdK8CpuIdCtlStd07hEbax,
558 kCpumMsrWrFn_AmdK8CpuIdCtlStd06hEcx,
559 kCpumMsrWrFn_AmdK8CpuIdCtlStd01hEdcx,
560 kCpumMsrWrFn_AmdK8CpuIdCtlExt01hEdcx,
561 kCpumMsrWrFn_AmdK8PatchLoader,
562 kCpumMsrWrFn_AmdK7DebugStatusMaybe,
563 kCpumMsrWrFn_AmdK7BHTraceBaseMaybe,
564 kCpumMsrWrFn_AmdK7BHTracePtrMaybe,
565 kCpumMsrWrFn_AmdK7BHTraceLimitMaybe,
566 kCpumMsrWrFn_AmdK7HardwareDebugToolCfgMaybe,
567 kCpumMsrWrFn_AmdK7FastFlushCountMaybe,
568 kCpumMsrWrFn_AmdK7NodeId,
569 kCpumMsrWrFn_AmdK7DrXAddrMaskN, /**< Takes register index. */
570 kCpumMsrWrFn_AmdK7Dr0DataMatchMaybe,
571 kCpumMsrWrFn_AmdK7Dr0DataMaskMaybe,
572 kCpumMsrWrFn_AmdK7LoadStoreCfg,
573 kCpumMsrWrFn_AmdK7InstrCacheCfg,
574 kCpumMsrWrFn_AmdK7DataCacheCfg,
575 kCpumMsrWrFn_AmdK7BusUnitCfg,
576 kCpumMsrWrFn_AmdK7DebugCtl2Maybe,
577 kCpumMsrWrFn_AmdFam15hFpuCfg,
578 kCpumMsrWrFn_AmdFam15hDecoderCfg,
579 kCpumMsrWrFn_AmdFam10hBusUnitCfg2,
580 kCpumMsrWrFn_AmdFam15hCombUnitCfg,
581 kCpumMsrWrFn_AmdFam15hCombUnitCfg2,
582 kCpumMsrWrFn_AmdFam15hCombUnitCfg3,
583 kCpumMsrWrFn_AmdFam15hExecUnitCfg,
584 kCpumMsrWrFn_AmdFam15hLoadStoreCfg2,
585 kCpumMsrWrFn_AmdFam10hIbsFetchCtl,
586 kCpumMsrWrFn_AmdFam10hIbsFetchLinAddr,
587 kCpumMsrWrFn_AmdFam10hIbsFetchPhysAddr,
588 kCpumMsrWrFn_AmdFam10hIbsOpExecCtl,
589 kCpumMsrWrFn_AmdFam10hIbsOpRip,
590 kCpumMsrWrFn_AmdFam10hIbsOpData,
591 kCpumMsrWrFn_AmdFam10hIbsOpData2,
592 kCpumMsrWrFn_AmdFam10hIbsOpData3,
593 kCpumMsrWrFn_AmdFam10hIbsDcLinAddr,
594 kCpumMsrWrFn_AmdFam10hIbsDcPhysAddr,
595 kCpumMsrWrFn_AmdFam10hIbsCtl,
596 kCpumMsrWrFn_AmdFam14hIbsBrTarget,
597
598 /** End of valid MSR write function indexes. */
599 kCpumMsrWrFn_End
600} CPUMMSRWRFN;
601
602/**
603 * MSR range.
604 */
605typedef struct CPUMMSRRANGE
606{
607 /** The first MSR. [0] */
608 uint32_t uFirst;
609 /** The last MSR. [4] */
610 uint32_t uLast;
611 /** The read function (CPUMMSRRDFN). [8] */
612 uint16_t enmRdFn;
613 /** The write function (CPUMMSRWRFN). [10] */
614 uint16_t enmWrFn;
615 /** The offset of the 64-bit MSR value relative to the start of CPUMCPU.
616 * UINT16_MAX if not used by the read and write functions. [12] */
617 uint16_t offCpumCpu;
618 /** Reserved for future hacks. [14] */
619 uint16_t fReserved;
620 /** The init/read value. [16]
621 * When enmRdFn is kCpumMsrRdFn_INIT_VALUE, this is the value returned on RDMSR.
622 * offCpumCpu must be UINT16_MAX in that case, otherwise it must be a valid
623 * offset into CPUM. */
624 uint64_t uValue;
625 /** The bits to ignore when writing. [24] */
626 uint64_t fWrIgnMask;
627 /** The bits that will cause a GP(0) when writing. [32]
628 * This is always checked prior to calling the write function. Using
629 * UINT64_MAX effectively marks the MSR as read-only. */
630 uint64_t fWrGpMask;
631 /** The register name, if applicable. [40] */
632 char szName[56];
633
634#ifdef VBOX_WITH_STATISTICS
635 /** The number of reads. */
636 STAMCOUNTER cReads;
637 /** The number of writes. */
638 STAMCOUNTER cWrites;
639 /** The number of times ignored bits were written. */
640 STAMCOUNTER cIgnoredBits;
641 /** The number of GPs generated. */
642 STAMCOUNTER cGps;
643#endif
644} CPUMMSRRANGE;
645#ifdef VBOX_WITH_STATISTICS
646AssertCompileSize(CPUMMSRRANGE, 128);
647#else
648AssertCompileSize(CPUMMSRRANGE, 96);
649#endif
650/** Pointer to an MSR range. */
651typedef CPUMMSRRANGE *PCPUMMSRRANGE;
652/** Pointer to a const MSR range. */
653typedef CPUMMSRRANGE const *PCCPUMMSRRANGE;
654
655
656
657
658/**
659 * CPU features and quirks.
660 * This is mostly exploded CPUID info.
661 */
662typedef struct CPUMFEATURES
663{
664 /** The CPU vendor (CPUMCPUVENDOR). */
665 uint8_t enmCpuVendor;
666 /** The CPU family. */
667 uint8_t uFamily;
668 /** The CPU model. */
669 uint8_t uModel;
670 /** The CPU stepping. */
671 uint8_t uStepping;
672 /** The microarchitecture. */
673 CPUMMICROARCH enmMicroarch;
674 /** The maximum physical address with of the CPU. */
675 uint8_t cMaxPhysAddrWidth;
676 /** Alignment padding. */
677 uint8_t abPadding[3];
678
679 /** Supports MSRs. */
680 uint32_t fMsr : 1;
681 /** Supports the page size extension (4/2 MB pages). */
682 uint32_t fPse : 1;
683 /** Supports 36-bit page size extension (4 MB pages can map memory above
684 * 4GB). */
685 uint32_t fPse36 : 1;
686 /** Supports physical address extension (PAE). */
687 uint32_t fPae : 1;
688 /** Page attribute table (PAT) support (page level cache control). */
689 uint32_t fPat : 1;
690 /** Supports the FXSAVE and FXRSTOR instructions. */
691 uint32_t fFxSaveRstor : 1;
692 /** Intel SYSENTER/SYSEXIT support */
693 uint32_t fSysEnter : 1;
694 /** First generation APIC. */
695 uint32_t fApic : 1;
696 /** Second generation APIC. */
697 uint32_t fX2Apic : 1;
698 /** Hypervisor present. */
699 uint32_t fHypervisorPresent : 1;
700 /** MWAIT & MONITOR instructions supported. */
701 uint32_t fMonitorMWait : 1;
702
703 /** AMD64: Supports long mode. */
704 uint32_t fLongMode : 1;
705 /** AMD64: SYSCALL/SYSRET support. */
706 uint32_t fSysCall : 1;
707 /** AMD64: No-execute page table bit. */
708 uint32_t fNoExecute : 1;
709 /** AMD64: Supports LAHF & SAHF instructions in 64-bit mode. */
710 uint32_t fLahfSahf : 1;
711 /** AMD64: Supports RDTSCP. */
712 uint32_t fRdTscP : 1;
713
714 /** Indicates that FPU instruction and data pointers may leak.
715 * This generally applies to recent AMD CPUs, where the FPU IP and DP pointer
716 * is only saved and restored if an exception is pending. */
717 uint32_t fLeakyFxSR : 1;
718
719 /** Alignment padding. */
720 uint32_t fPadding : 9;
721
722 uint64_t auPadding[2];
723} CPUMFEATURES;
724AssertCompileSize(CPUMFEATURES, 32);
725/** Pointer to a CPU feature structure. */
726typedef CPUMFEATURES *PCPUMFEATURES;
727/** Pointer to a const CPU feature structure. */
728typedef CPUMFEATURES const *PCCPUMFEATURES;
729
730
731/**
732 * CPU info
733 */
734typedef struct CPUMINFO
735{
736 /** The number of MSR ranges (CPUMMSRRANGE) in the array pointed to below. */
737 uint32_t cMsrRanges;
738 /** Mask applied to ECX before looking up the MSR for a RDMSR/WRMSR
739 * instruction. Older hardware has been observed to ignore higher bits. */
740 uint32_t fMsrMask;
741
742 /** The number of CPUID leaves (CPUMCPUIDLEAF) in the array pointed to below. */
743 uint32_t cCpuIdLeaves;
744 /** The index of the first extended CPUID leaf in the array.
745 * Set to cCpuIdLeaves if none present. */
746 uint32_t iFirstExtCpuIdLeaf;
747 /** Alignment padding. */
748 uint32_t uPadding;
749 /** How to handle unknown CPUID leaves. */
750 CPUMUKNOWNCPUID enmUnknownCpuIdMethod;
751 /** For use with CPUMUKNOWNCPUID_DEFAULTS. */
752 CPUMCPUID DefCpuId;
753
754 /** Scalable bus frequency used for reporting other frequencies. */
755 uint64_t uScalableBusFreq;
756
757 /** Pointer to the MSR ranges (ring-0 pointer). */
758 R0PTRTYPE(PCPUMMSRRANGE) paMsrRangesR0;
759 /** Pointer to the CPUID leaves (ring-0 pointer). */
760 R0PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR0;
761
762 /** Pointer to the MSR ranges (ring-3 pointer). */
763 R3PTRTYPE(PCPUMMSRRANGE) paMsrRangesR3;
764 /** Pointer to the CPUID leaves (ring-3 pointer). */
765 R3PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR3;
766
767 /** Pointer to the MSR ranges (raw-mode context pointer). */
768 RCPTRTYPE(PCPUMMSRRANGE) paMsrRangesRC;
769 /** Pointer to the CPUID leaves (raw-mode context pointer). */
770 RCPTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesRC;
771} CPUMINFO;
772/** Pointer to a CPU info structure. */
773typedef CPUMINFO *PCPUMINFO;
774/** Pointer to a const CPU info structure. */
775typedef CPUMINFO const *CPCPUMINFO;
776
777
778/**
779 * The saved host CPU state.
780 *
781 * @remark The special VBOX_WITH_HYBRID_32BIT_KERNEL checks here are for the 10.4.x series
782 * of Mac OS X where the OS is essentially 32-bit but the cpu mode can be 64-bit.
783 */
784typedef struct CPUMHOSTCTX
785{
786 /** FPU state. (16-byte alignment)
787 * @remark On x86, the format isn't necessarily X86FXSTATE (not important). */
788 X86FXSTATE fpu;
789
790 /** General purpose register, selectors, flags and more
791 * @{ */
792#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
793 /** General purpose register ++
794 * { */
795 /*uint64_t rax; - scratch*/
796 uint64_t rbx;
797 /*uint64_t rcx; - scratch*/
798 /*uint64_t rdx; - scratch*/
799 uint64_t rdi;
800 uint64_t rsi;
801 uint64_t rbp;
802 uint64_t rsp;
803 /*uint64_t r8; - scratch*/
804 /*uint64_t r9; - scratch*/
805 uint64_t r10;
806 uint64_t r11;
807 uint64_t r12;
808 uint64_t r13;
809 uint64_t r14;
810 uint64_t r15;
811 /*uint64_t rip; - scratch*/
812 uint64_t rflags;
813#endif
814
815#if HC_ARCH_BITS == 32
816 /*uint32_t eax; - scratch*/
817 uint32_t ebx;
818 /*uint32_t ecx; - scratch*/
819 /*uint32_t edx; - scratch*/
820 uint32_t edi;
821 uint32_t esi;
822 uint32_t ebp;
823 X86EFLAGS eflags;
824 /*uint32_t eip; - scratch*/
825 /* lss pair! */
826 uint32_t esp;
827#endif
828 /** @} */
829
830 /** Selector registers
831 * @{ */
832 RTSEL ss;
833 RTSEL ssPadding;
834 RTSEL gs;
835 RTSEL gsPadding;
836 RTSEL fs;
837 RTSEL fsPadding;
838 RTSEL es;
839 RTSEL esPadding;
840 RTSEL ds;
841 RTSEL dsPadding;
842 RTSEL cs;
843 RTSEL csPadding;
844 /** @} */
845
846#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
847 /** Control registers.
848 * @{ */
849 uint32_t cr0;
850 /*uint32_t cr2; - scratch*/
851 uint32_t cr3;
852 uint32_t cr4;
853 /** @} */
854
855 /** Debug registers.
856 * @{ */
857 uint32_t dr0;
858 uint32_t dr1;
859 uint32_t dr2;
860 uint32_t dr3;
861 uint32_t dr6;
862 uint32_t dr7;
863 /** @} */
864
865 /** Global Descriptor Table register. */
866 X86XDTR32 gdtr;
867 uint16_t gdtrPadding;
868 /** Interrupt Descriptor Table register. */
869 X86XDTR32 idtr;
870 uint16_t idtrPadding;
871 /** The task register. */
872 RTSEL ldtr;
873 RTSEL ldtrPadding;
874 /** The task register. */
875 RTSEL tr;
876 RTSEL trPadding;
877 uint32_t SysEnterPadding;
878
879 /** The sysenter msr registers.
880 * This member is not used by the hypervisor context. */
881 CPUMSYSENTER SysEnter;
882
883 /** MSRs
884 * @{ */
885 uint64_t efer;
886 /** @} */
887
888 /* padding to get 64byte aligned size */
889 uint8_t auPadding[16+32];
890
891#elif HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
892
893 /** Control registers.
894 * @{ */
895 uint64_t cr0;
896 /*uint64_t cr2; - scratch*/
897 uint64_t cr3;
898 uint64_t cr4;
899 uint64_t cr8;
900 /** @} */
901
902 /** Debug registers.
903 * @{ */
904 uint64_t dr0;
905 uint64_t dr1;
906 uint64_t dr2;
907 uint64_t dr3;
908 uint64_t dr6;
909 uint64_t dr7;
910 /** @} */
911
912 /** Global Descriptor Table register. */
913 X86XDTR64 gdtr;
914 uint16_t gdtrPadding;
915 /** Interrupt Descriptor Table register. */
916 X86XDTR64 idtr;
917 uint16_t idtrPadding;
918 /** The task register. */
919 RTSEL ldtr;
920 RTSEL ldtrPadding;
921 /** The task register. */
922 RTSEL tr;
923 RTSEL trPadding;
924
925 /** MSRs
926 * @{ */
927 CPUMSYSENTER SysEnter;
928 uint64_t FSbase;
929 uint64_t GSbase;
930 uint64_t efer;
931 /** @} */
932
933 /* padding to get 32byte aligned size */
934# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
935 uint8_t auPadding[16];
936# else
937 uint8_t auPadding[8+32];
938# endif
939
940#else
941# error HC_ARCH_BITS not defined
942#endif
943} CPUMHOSTCTX;
944/** Pointer to the saved host CPU state. */
945typedef CPUMHOSTCTX *PCPUMHOSTCTX;
946
947
948/**
949 * CPUM Data (part of VM)
950 */
951typedef struct CPUM
952{
953 /** Offset from CPUM to CPUMCPU for the first CPU. */
954 uint32_t offCPUMCPU0;
955
956 /** Use flags.
957 * These flags indicates which CPU features the host uses.
958 */
959 uint32_t fHostUseFlags;
960
961 /** Host CPU Features - ECX */
962 struct
963 {
964 /** edx part */
965 X86CPUIDFEATEDX edx;
966 /** ecx part */
967 X86CPUIDFEATECX ecx;
968 } CPUFeatures;
969 /** Host extended CPU features. */
970 struct
971 {
972 /** edx part */
973 uint32_t edx;
974 /** ecx part */
975 uint32_t ecx;
976 } CPUFeaturesExt;
977
978 /** CR4 mask */
979 struct
980 {
981 uint32_t AndMask; /**< @todo Move these to the per-CPU structure and fix the switchers. Saves a register! */
982 uint32_t OrMask;
983 } CR4;
984
985 /** The (more) portable CPUID level. */
986 uint8_t u8PortableCpuIdLevel;
987 /** Indicates that a state restore is pending.
988 * This is used to verify load order dependencies (PGM). */
989 bool fPendingRestore;
990 uint8_t abPadding[HC_ARCH_BITS == 64 ? 6 : 2];
991
992 /** The standard set of CpuId leaves. */
993 CPUMCPUID aGuestCpuIdStd[6];
994 /** The extended set of CpuId leaves. */
995 CPUMCPUID aGuestCpuIdExt[10];
996 /** The centaur set of CpuId leaves. */
997 CPUMCPUID aGuestCpuIdCentaur[4];
998 /** The hypervisor specific set of CpuId leaves. */
999 CPUMCPUID aGuestCpuIdHyper[4];
1000 /** The default set of CpuId leaves. */
1001 CPUMCPUID GuestCpuIdDef;
1002
1003#if HC_ARCH_BITS == 32
1004 uint8_t abPadding2[4];
1005#endif
1006
1007 /** Guest CPU info. */
1008 CPUMINFO GuestInfo;
1009 /** Guest CPU feature information. */
1010 CPUMFEATURES GuestFeatures;
1011 /** Host CPU feature information. */
1012 CPUMFEATURES HostFeatures;
1013
1014 /** @name MSR statistics.
1015 * @{ */
1016 STAMCOUNTER cMsrWrites;
1017 STAMCOUNTER cMsrWritesToIgnoredBits;
1018 STAMCOUNTER cMsrWritesRaiseGp;
1019 STAMCOUNTER cMsrWritesUnknown;
1020 STAMCOUNTER cMsrReads;
1021 STAMCOUNTER cMsrReadsRaiseGp;
1022 STAMCOUNTER cMsrReadsUnknown;
1023 /** @} */
1024} CPUM;
1025/** Pointer to the CPUM instance data residing in the shared VM structure. */
1026typedef CPUM *PCPUM;
1027
1028/**
1029 * CPUM Data (part of VMCPU)
1030 */
1031typedef struct CPUMCPU
1032{
1033 /**
1034 * Hypervisor context.
1035 * Aligned on a 64-byte boundary.
1036 */
1037 CPUMCTX Hyper;
1038
1039 /**
1040 * Saved host context. Only valid while inside GC.
1041 * Aligned on a 64-byte boundary.
1042 */
1043 CPUMHOSTCTX Host;
1044
1045#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1046 uint8_t aMagic[56];
1047 uint64_t uMagic;
1048#endif
1049
1050 /**
1051 * Guest context.
1052 * Aligned on a 64-byte boundary.
1053 */
1054 CPUMCTX Guest;
1055
1056 /**
1057 * Guest context - misc MSRs
1058 * Aligned on a 64-byte boundary.
1059 */
1060 CPUMCTXMSRS GuestMsrs;
1061
1062 /** Use flags.
1063 * These flags indicates both what is to be used and what has been used.
1064 */
1065 uint32_t fUseFlags;
1066
1067 /** Changed flags.
1068 * These flags indicates to REM (and others) which important guest
1069 * registers which has been changed since last time the flags were cleared.
1070 * See the CPUM_CHANGED_* defines for what we keep track of.
1071 */
1072 uint32_t fChanged;
1073
1074 /** Offset from CPUM to CPUMCPU. */
1075 uint32_t offCPUM;
1076
1077 /** Temporary storage for the return code of the function called in the
1078 * 32-64 switcher. */
1079 uint32_t u32RetCode;
1080
1081#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
1082 /** The address of the APIC mapping, NULL if no APIC.
1083 * Call CPUMR0SetLApic to update this before doing a world switch. */
1084 RTHCPTR pvApicBase;
1085 /** Used by the world switcher code to store which vectors needs restoring on
1086 * the way back. */
1087 uint32_t fApicDisVectors;
1088 /** Set if the CPU has the X2APIC mode enabled.
1089 * Call CPUMR0SetLApic to update this before doing a world switch. */
1090 bool fX2Apic;
1091#else
1092 uint8_t abPadding3[(HC_ARCH_BITS == 64 ? 8 : 4) + 4 + 1];
1093#endif
1094
1095 /** Have we entered raw-mode? */
1096 bool fRawEntered;
1097 /** Have we entered the recompiler? */
1098 bool fRemEntered;
1099
1100 /** Align the structure on a 64-byte boundary. */
1101 uint8_t abPadding2[64 - 16 - (HC_ARCH_BITS == 64 ? 8 : 4) - 4 - 1 - 2];
1102} CPUMCPU;
1103/** Pointer to the CPUMCPU instance data residing in the shared VMCPU structure. */
1104typedef CPUMCPU *PCPUMCPU;
1105
1106#ifndef VBOX_FOR_DTRACE_LIB
1107RT_C_DECLS_BEGIN
1108
1109PCPUMCPUIDLEAF cpumCpuIdGetLeaf(PVM pVM, uint32_t uLeaf, uint32_t uSubLeaf);
1110
1111#ifdef IN_RING3
1112int cpumR3DbgInit(PVM pVM);
1113PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf);
1114bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
1115 PCPUMCPUID pLeagcy);
1116int cpumR3CpuIdInsert(PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves, PCPUMCPUIDLEAF pNewLeaf);
1117void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast);
1118int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCPUMFEATURES pFeatures);
1119int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo);
1120int cpumR3MsrRangesInsert(PCPUMMSRRANGE *ppaMsrRanges, uint32_t *pcMsrRanges, PCCPUMMSRRANGE pNewRange);
1121int cpumR3MsrApplyFudge(PVM pVM);
1122int cpumR3MsrRegStats(PVM pVM);
1123int cpumR3MsrStrictInitChecks(void);
1124PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr);
1125#endif
1126
1127#ifdef IN_RC
1128DECLASM(int) cpumHandleLazyFPUAsm(PCPUMCPU pCPUM);
1129#endif
1130
1131#ifdef IN_RING0
1132DECLASM(int) cpumR0SaveHostRestoreGuestFPUState(PCPUMCPU pCPUM);
1133DECLASM(int) cpumR0SaveGuestRestoreHostFPUState(PCPUMCPU pCPUM);
1134DECLASM(int) cpumR0SaveHostFPUState(PCPUMCPU pCPUM);
1135DECLASM(int) cpumR0RestoreHostFPUState(PCPUMCPU pCPUM);
1136DECLASM(void) cpumR0LoadFPU(PCPUMCTX pCtx);
1137DECLASM(void) cpumR0SaveFPU(PCPUMCTX pCtx);
1138DECLASM(void) cpumR0LoadXMM(PCPUMCTX pCtx);
1139DECLASM(void) cpumR0SaveXMM(PCPUMCTX pCtx);
1140DECLASM(void) cpumR0SetFCW(uint16_t u16FCW);
1141DECLASM(uint16_t) cpumR0GetFCW(void);
1142DECLASM(void) cpumR0SetMXCSR(uint32_t u32MXCSR);
1143DECLASM(uint32_t) cpumR0GetMXCSR(void);
1144DECLASM(void) cpumR0LoadDRx(uint64_t const *pa4Regs);
1145DECLASM(void) cpumR0SaveDRx(uint64_t *pa4Regs);
1146#endif
1147
1148RT_C_DECLS_END
1149#endif /* !VBOX_FOR_DTRACE_LIB */
1150
1151/** @} */
1152
1153#endif
1154
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