| 1 | ; VMM - World Switchers, 32Bit to AMD64.
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| 2 | ;
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| 3 |
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| 4 | ;
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| 5 | ; Copyright (C) 2006-2012 Oracle Corporation
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| 6 | ;
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| 7 | ; This file is part of VirtualBox Open Source Edition (OSE), as
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| 8 | ; available from http://www.alldomusa.eu.org. This file is free software;
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| 9 | ; you can redistribute it and/or modify it under the terms of the GNU
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| 10 | ; General Public License (GPL) as published by the Free Software
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| 11 | ; Foundation, in version 2 as it comes in the "COPYING" file of the
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| 12 | ; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 13 | ; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 14 | ;
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| 15 |
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| 16 | ;%define DEBUG_STUFF 1
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| 17 | ;%define STRICT_IF 1
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| 18 |
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| 19 | ;*******************************************************************************
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| 20 | ;* Defined Constants And Macros *
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| 21 | ;*******************************************************************************
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| 22 |
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| 23 |
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| 24 | ;*******************************************************************************
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| 25 | ;* Header Files *
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| 26 | ;*******************************************************************************
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| 27 | %include "VBox/asmdefs.mac"
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| 28 | %include "VBox/apic.mac"
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| 29 | %include "iprt/x86.mac"
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| 30 | %include "VBox/vmm/cpum.mac"
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| 31 | %include "VBox/vmm/stam.mac"
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| 32 | %include "VBox/vmm/vm.mac"
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| 33 | %include "CPUMInternal.mac"
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| 34 | %include "VMMSwitcher.mac"
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| 35 |
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| 36 |
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| 37 | ;
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| 38 | ; Start the fixup records
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| 39 | ; We collect the fixups in the .data section as we go along
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| 40 | ; It is therefore VITAL that no-one is using the .data section
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| 41 | ; for anything else between 'Start' and 'End'.
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| 42 | ;
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| 43 | BEGINDATA
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| 44 | GLOBALNAME Fixups
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| 45 |
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| 46 |
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| 47 |
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| 48 | BEGINCODE
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| 49 | GLOBALNAME Start
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| 50 |
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| 51 | BITS 32
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| 52 |
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| 53 | ;;
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| 54 | ; The C interface.
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| 55 | ; @param [esp + 04h] Param 1 - VM handle
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| 56 | ; @param [esp + 08h] Param 2 - Offset from VM::CPUM to the CPUMCPU
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| 57 | ; structure for the calling EMT.
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| 58 | ;
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| 59 | BEGINPROC vmmR0ToRawMode
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| 60 | %ifdef DEBUG_STUFF
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| 61 | COM32_S_NEWLINE
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| 62 | COM32_S_CHAR '^'
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| 63 | %endif
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| 64 |
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| 65 | %ifdef VBOX_WITH_STATISTICS
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| 66 | ;
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| 67 | ; Switcher stats.
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| 68 | ;
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| 69 | FIXUP FIX_HC_VM_OFF, 1, VM.StatSwitcherToGC
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| 70 | mov edx, 0ffffffffh
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| 71 | STAM_PROFILE_ADV_START edx
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| 72 | %endif
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| 73 |
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| 74 | push ebp
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| 75 | mov ebp, [esp + 12] ; CPUMCPU offset
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| 76 |
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| 77 | ; turn off interrupts
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| 78 | pushf
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| 79 | cli
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| 80 |
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| 81 | ;
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| 82 | ; Call worker.
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| 83 | ;
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| 84 | FIXUP FIX_HC_CPUM_OFF, 1, 0
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| 85 | mov edx, 0ffffffffh
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| 86 | push cs ; allow for far return and restore cs correctly.
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| 87 | call NAME(vmmR0ToRawModeAsm)
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| 88 |
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| 89 | %ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
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| 90 | CPUM_FROM_CPUMCPU(edx)
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| 91 | ; Restore blocked Local APIC NMI vectors
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| 92 | mov ecx, [edx + CPUM.fApicDisVectors]
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| 93 | mov edx, [edx + CPUM.pvApicBase]
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| 94 | shr ecx, 1
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| 95 | jnc gth_nolint0
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| 96 | and dword [edx + APIC_REG_LVT_LINT0], ~APIC_REG_LVT_MASKED
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| 97 | gth_nolint0:
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| 98 | shr ecx, 1
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| 99 | jnc gth_nolint1
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| 100 | and dword [edx + APIC_REG_LVT_LINT1], ~APIC_REG_LVT_MASKED
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| 101 | gth_nolint1:
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| 102 | shr ecx, 1
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| 103 | jnc gth_nopc
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| 104 | and dword [edx + APIC_REG_LVT_PC], ~APIC_REG_LVT_MASKED
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| 105 | gth_nopc:
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| 106 | shr ecx, 1
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| 107 | jnc gth_notherm
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| 108 | and dword [edx + APIC_REG_LVT_THMR], ~APIC_REG_LVT_MASKED
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| 109 | gth_notherm:
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| 110 | %endif
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| 111 |
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| 112 | ; restore original flags
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| 113 | popf
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| 114 | pop ebp
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| 115 |
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| 116 | %ifdef VBOX_WITH_STATISTICS
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| 117 | ;
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| 118 | ; Switcher stats.
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| 119 | ;
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| 120 | FIXUP FIX_HC_VM_OFF, 1, VM.StatSwitcherToHC
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| 121 | mov edx, 0ffffffffh
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| 122 | STAM_PROFILE_ADV_STOP edx
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| 123 | %endif
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| 124 |
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| 125 | ret
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| 126 |
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| 127 | ENDPROC vmmR0ToRawMode
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| 128 |
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| 129 | ; *****************************************************************************
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| 130 | ; vmmR0ToRawModeAsm
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| 131 | ;
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| 132 | ; Phase one of the switch from host to guest context (host MMU context)
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| 133 | ;
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| 134 | ; INPUT:
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| 135 | ; - edx virtual address of CPUM structure (valid in host context)
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| 136 | ; - ebp offset of the CPUMCPU structure relative to CPUM.
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| 137 | ;
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| 138 | ; USES/DESTROYS:
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| 139 | ; - eax, ecx, edx, esi
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| 140 | ;
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| 141 | ; ASSUMPTION:
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| 142 | ; - current CS and DS selectors are wide open
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| 143 | ;
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| 144 | ; *****************************************************************************
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| 145 | ALIGNCODE(16)
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| 146 | BEGINPROC vmmR0ToRawModeAsm
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| 147 | ;;
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| 148 | ;; Save CPU host context
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| 149 | ;; Skip eax, edx and ecx as these are not preserved over calls.
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| 150 | ;;
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| 151 | CPUMCPU_FROM_CPUM_WITH_OFFSET edx, ebp
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| 152 | %ifdef VBOX_WITH_CRASHDUMP_MAGIC
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| 153 | ; phys address of scratch page
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| 154 | mov eax, dword [edx + CPUMCPU.Guest.dr + 4*8]
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| 155 | mov cr2, eax
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| 156 |
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| 157 | mov dword [edx + CPUMCPU.Guest.dr + 4*8], 1
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| 158 | %endif
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| 159 |
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| 160 | ; general registers.
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| 161 | mov [edx + CPUMCPU.Host.ebx], ebx
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| 162 | mov [edx + CPUMCPU.Host.edi], edi
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| 163 | mov [edx + CPUMCPU.Host.esi], esi
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| 164 | mov [edx + CPUMCPU.Host.esp], esp
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| 165 | mov [edx + CPUMCPU.Host.ebp], ebp
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| 166 | ; selectors.
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| 167 | mov [edx + CPUMCPU.Host.ds], ds
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| 168 | mov [edx + CPUMCPU.Host.es], es
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| 169 | mov [edx + CPUMCPU.Host.fs], fs
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| 170 | mov [edx + CPUMCPU.Host.gs], gs
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| 171 | mov [edx + CPUMCPU.Host.ss], ss
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| 172 | ; special registers.
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| 173 | sldt [edx + CPUMCPU.Host.ldtr]
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| 174 | sidt [edx + CPUMCPU.Host.idtr]
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| 175 | sgdt [edx + CPUMCPU.Host.gdtr]
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| 176 | str [edx + CPUMCPU.Host.tr]
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| 177 |
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| 178 | %ifdef VBOX_WITH_CRASHDUMP_MAGIC
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| 179 | mov dword [edx + CPUMCPU.Guest.dr + 4*8], 2
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| 180 | %endif
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| 181 |
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| 182 | %ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
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| 183 | CPUM_FROM_CPUMCPU_WITH_OFFSET edx, ebp
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| 184 | mov ebx, [edx + CPUM.pvApicBase]
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| 185 | or ebx, ebx
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| 186 | jz htg_noapic
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| 187 | mov eax, [ebx + APIC_REG_LVT_LINT0]
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| 188 | mov ecx, eax
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| 189 | and ecx, (APIC_REG_LVT_MASKED | APIC_REG_LVT_MODE_MASK)
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| 190 | cmp ecx, APIC_REG_LVT_MODE_NMI
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| 191 | jne htg_nolint0
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| 192 | or edi, 0x01
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| 193 | or eax, APIC_REG_LVT_MASKED
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| 194 | mov [ebx + APIC_REG_LVT_LINT0], eax
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| 195 | mov eax, [ebx + APIC_REG_LVT_LINT0] ; write completion
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| 196 | htg_nolint0:
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| 197 | mov eax, [ebx + APIC_REG_LVT_LINT1]
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| 198 | mov ecx, eax
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| 199 | and ecx, (APIC_REG_LVT_MASKED | APIC_REG_LVT_MODE_MASK)
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| 200 | cmp ecx, APIC_REG_LVT_MODE_NMI
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| 201 | jne htg_nolint1
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| 202 | or edi, 0x02
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| 203 | or eax, APIC_REG_LVT_MASKED
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| 204 | mov [ebx + APIC_REG_LVT_LINT1], eax
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| 205 | mov eax, [ebx + APIC_REG_LVT_LINT1] ; write completion
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| 206 | htg_nolint1:
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| 207 | mov eax, [ebx + APIC_REG_LVT_PC]
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| 208 | mov ecx, eax
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| 209 | and ecx, (APIC_REG_LVT_MASKED | APIC_REG_LVT_MODE_MASK)
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| 210 | cmp ecx, APIC_REG_LVT_MODE_NMI
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| 211 | jne htg_nopc
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| 212 | or edi, 0x04
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| 213 | or eax, APIC_REG_LVT_MASKED
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| 214 | mov [ebx + APIC_REG_LVT_PC], eax
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| 215 | mov eax, [ebx + APIC_REG_LVT_PC] ; write completion
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| 216 | htg_nopc:
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| 217 | mov eax, [ebx + APIC_REG_VERSION]
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| 218 | shr eax, 16
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| 219 | cmp al, 5
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| 220 | jb htg_notherm
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| 221 | mov eax, [ebx + APIC_REG_LVT_THMR]
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| 222 | mov ecx, eax
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| 223 | and ecx, (APIC_REG_LVT_MASKED | APIC_REG_LVT_MODE_MASK)
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| 224 | cmp ecx, APIC_REG_LVT_MODE_NMI
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| 225 | jne htg_notherm
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| 226 | or edi, 0x08
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| 227 | or eax, APIC_REG_LVT_MASKED
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| 228 | mov [ebx + APIC_REG_LVT_THMR], eax
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| 229 | mov eax, [ebx + APIC_REG_LVT_THMR] ; write completion
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| 230 | htg_notherm:
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| 231 | mov [edx + CPUM.fApicDisVectors], edi
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| 232 | htg_noapic:
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| 233 | CPUMCPU_FROM_CPUM_WITH_OFFSET edx, ebp
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| 234 | %endif
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| 235 |
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| 236 | ; control registers.
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| 237 | mov eax, cr0
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| 238 | mov [edx + CPUMCPU.Host.cr0], eax
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| 239 | ;Skip cr2; assume host os don't stuff things in cr2. (safe)
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| 240 | mov eax, cr3
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| 241 | mov [edx + CPUMCPU.Host.cr3], eax
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| 242 | mov eax, cr4
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| 243 | mov [edx + CPUMCPU.Host.cr4], eax
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| 244 |
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| 245 | ; save the host EFER msr
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| 246 | mov ebx, edx
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| 247 | mov ecx, MSR_K6_EFER
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| 248 | rdmsr
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| 249 | mov [ebx + CPUMCPU.Host.efer], eax
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| 250 | mov [ebx + CPUMCPU.Host.efer + 4], edx
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| 251 | mov edx, ebx
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| 252 |
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| 253 | %ifdef VBOX_WITH_CRASHDUMP_MAGIC
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| 254 | mov dword [edx + CPUMCPU.Guest.dr + 4*8], 3
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| 255 | %endif
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| 256 |
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| 257 | ; Load new gdt so we can do a far jump after going into 64 bits mode
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| 258 | lgdt [edx + CPUMCPU.Hyper.gdtr]
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| 259 |
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| 260 | %ifdef VBOX_WITH_CRASHDUMP_MAGIC
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| 261 | mov dword [edx + CPUMCPU.Guest.dr + 4*8], 4
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| 262 | %endif
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| 263 |
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| 264 | ;;
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| 265 | ;; Load Intermediate memory context.
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| 266 | ;;
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| 267 | FIXUP SWITCHER_FIX_INTER_CR3_HC, 1
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| 268 | mov eax, 0ffffffffh
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| 269 | mov cr3, eax
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| 270 | DEBUG_CHAR('?')
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| 271 |
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| 272 | ;;
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| 273 | ;; Jump to identity mapped location
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| 274 | ;;
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| 275 | FIXUP FIX_HC_2_ID_NEAR_REL, 1, NAME(IDEnterTarget) - NAME(Start)
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| 276 | jmp near NAME(IDEnterTarget)
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| 277 |
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| 278 |
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| 279 | ; We're now on identity mapped pages!
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| 280 | ALIGNCODE(16)
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| 281 | GLOBALNAME IDEnterTarget
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| 282 | DEBUG_CHAR('2')
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| 283 |
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| 284 | ; 1. Disable paging.
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| 285 | mov ebx, cr0
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| 286 | and ebx, ~X86_CR0_PG
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| 287 | mov cr0, ebx
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| 288 | DEBUG_CHAR('2')
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| 289 |
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| 290 | %ifdef VBOX_WITH_CRASHDUMP_MAGIC
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| 291 | mov eax, cr2
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| 292 | mov dword [eax], 3
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| 293 | %endif
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| 294 |
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| 295 | ; 2. Enable PAE.
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| 296 | mov ecx, cr4
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| 297 | or ecx, X86_CR4_PAE
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| 298 | mov cr4, ecx
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| 299 |
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| 300 | ; 3. Load long mode intermediate CR3.
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| 301 | FIXUP FIX_INTER_AMD64_CR3, 1
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| 302 | mov ecx, 0ffffffffh
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| 303 | mov cr3, ecx
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| 304 | DEBUG_CHAR('3')
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| 305 |
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| 306 | %ifdef VBOX_WITH_CRASHDUMP_MAGIC
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| 307 | mov eax, cr2
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| 308 | mov dword [eax], 4
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| 309 | %endif
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| 310 |
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| 311 | ; 4. Enable long mode.
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| 312 | mov esi, edx
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| 313 | mov ecx, MSR_K6_EFER
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| 314 | rdmsr
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| 315 | FIXUP FIX_EFER_OR_MASK, 1
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| 316 | or eax, 0ffffffffh
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| 317 | and eax, ~(MSR_K6_EFER_FFXSR) ; turn off fast fxsave/fxrstor (skipping xmm regs)
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| 318 | wrmsr
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| 319 | mov edx, esi
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| 320 | DEBUG_CHAR('4')
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| 321 |
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| 322 | %ifdef VBOX_WITH_CRASHDUMP_MAGIC
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| 323 | mov eax, cr2
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| 324 | mov dword [eax], 5
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| 325 | %endif
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| 326 |
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| 327 | ; 5. Enable paging.
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| 328 | or ebx, X86_CR0_PG
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| 329 | ; Disable ring 0 write protection too
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| 330 | and ebx, ~X86_CR0_WRITE_PROTECT
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| 331 | mov cr0, ebx
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| 332 | DEBUG_CHAR('5')
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| 333 |
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| 334 | ; Jump from compatibility mode to 64-bit mode.
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| 335 | FIXUP FIX_ID_FAR32_TO_64BIT_MODE, 1, NAME(IDEnter64Mode) - NAME(Start)
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| 336 | jmp 0ffffh:0fffffffeh
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| 337 |
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| 338 | ;
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| 339 | ; We're in 64-bit mode (ds, ss, es, fs, gs are all bogus).
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| 340 | BITS 64
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| 341 | ALIGNCODE(16)
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| 342 | NAME(IDEnter64Mode):
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| 343 | DEBUG_CHAR('6')
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| 344 | jmp [NAME(pICEnterTarget) wrt rip]
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| 345 |
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| 346 | ; 64-bit jump target
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| 347 | NAME(pICEnterTarget):
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| 348 | FIXUP FIX_HC_64BIT_NOCHECK, 0, NAME(ICEnterTarget) - NAME(Start)
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| 349 | dq 0ffffffffffffffffh
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| 350 |
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| 351 | ; 64-bit pCpum address.
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| 352 | NAME(pCpumIC):
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| 353 | FIXUP FIX_GC_64_BIT_CPUM_OFF, 0, 0
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| 354 | dq 0ffffffffffffffffh
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| 355 |
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| 356 | %ifdef VBOX_WITH_CRASHDUMP_MAGIC
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| 357 | NAME(pMarker):
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| 358 | db 'Switch_marker'
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| 359 | %endif
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| 360 |
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| 361 | ;
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| 362 | ; When we arrive here we're in 64 bits mode in the intermediate context
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| 363 | ;
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| 364 | ALIGNCODE(16)
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| 365 | GLOBALNAME ICEnterTarget
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| 366 | ; Load CPUM pointer into rdx
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| 367 | mov rdx, [NAME(pCpumIC) wrt rip]
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| 368 | CPUMCPU_FROM_CPUM_WITH_OFFSET edx, ebp
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| 369 |
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| 370 | mov rax, cs
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| 371 | mov ds, rax
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| 372 | mov es, rax
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| 373 |
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| 374 | ; Invalidate fs & gs
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| 375 | mov rax, 0
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| 376 | mov fs, rax
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| 377 | mov gs, rax
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| 378 |
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| 379 | %ifdef VBOX_WITH_CRASHDUMP_MAGIC
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| 380 | mov dword [rdx + CPUMCPU.Guest.dr + 4*8], 5
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| 381 | %endif
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| 382 |
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| 383 | ; Setup stack.
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| 384 | DEBUG_CHAR('7')
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| 385 | mov rsp, 0
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| 386 | mov eax, [rdx + CPUMCPU.Hyper.ss.Sel]
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| 387 | mov ss, ax
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| 388 | mov esp, [rdx + CPUMCPU.Hyper.esp]
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| 389 |
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| 390 | %ifdef VBOX_WITH_CRASHDUMP_MAGIC
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| 391 | mov dword [rdx + CPUMCPU.Guest.dr + 4*8], 6
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| 392 | %endif
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| 393 |
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| 394 |
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| 395 | ; load the hypervisor function address
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| 396 | mov r9, [rdx + CPUMCPU.Hyper.eip]
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| 397 |
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| 398 | ; Check if we need to restore the guest FPU state
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| 399 | mov esi, [rdx + CPUMCPU.fUseFlags] ; esi == use flags.
|
|---|
| 400 | test esi, CPUM_SYNC_FPU_STATE
|
|---|
| 401 | jz near gth_fpu_no
|
|---|
| 402 |
|
|---|
| 403 | %ifdef VBOX_WITH_CRASHDUMP_MAGIC
|
|---|
| 404 | mov dword [rdx + CPUMCPU.Guest.dr + 4*8], 7
|
|---|
| 405 | %endif
|
|---|
| 406 |
|
|---|
| 407 | mov rax, cr0
|
|---|
| 408 | mov rcx, rax ; save old CR0
|
|---|
| 409 | and rax, ~(X86_CR0_TS | X86_CR0_EM)
|
|---|
| 410 | mov cr0, rax
|
|---|
| 411 | fxrstor [rdx + CPUMCPU.Guest.fpu]
|
|---|
| 412 | mov cr0, rcx ; and restore old CR0 again
|
|---|
| 413 |
|
|---|
| 414 | and dword [rdx + CPUMCPU.fUseFlags], ~CPUM_SYNC_FPU_STATE
|
|---|
| 415 |
|
|---|
| 416 | gth_fpu_no:
|
|---|
| 417 | ; Check if we need to restore the guest debug state
|
|---|
| 418 | test esi, CPUM_SYNC_DEBUG_STATE
|
|---|
| 419 | jz near gth_debug_no
|
|---|
| 420 |
|
|---|
| 421 | %ifdef VBOX_WITH_CRASHDUMP_MAGIC
|
|---|
| 422 | mov dword [rdx + CPUMCPU.Guest.dr + 4*8], 8
|
|---|
| 423 | %endif
|
|---|
| 424 |
|
|---|
| 425 | mov rax, qword [rdx + CPUMCPU.Guest.dr + 0*8]
|
|---|
| 426 | mov dr0, rax
|
|---|
| 427 | mov rax, qword [rdx + CPUMCPU.Guest.dr + 1*8]
|
|---|
| 428 | mov dr1, rax
|
|---|
| 429 | mov rax, qword [rdx + CPUMCPU.Guest.dr + 2*8]
|
|---|
| 430 | mov dr2, rax
|
|---|
| 431 | mov rax, qword [rdx + CPUMCPU.Guest.dr + 3*8]
|
|---|
| 432 | mov dr3, rax
|
|---|
| 433 | mov rax, qword [rdx + CPUMCPU.Guest.dr + 6*8]
|
|---|
| 434 | mov dr6, rax ; not required for AMD-V
|
|---|
| 435 |
|
|---|
| 436 | and dword [rdx + CPUMCPU.fUseFlags], ~CPUM_SYNC_DEBUG_STATE
|
|---|
| 437 |
|
|---|
| 438 | gth_debug_no:
|
|---|
| 439 |
|
|---|
| 440 | %ifdef VBOX_WITH_CRASHDUMP_MAGIC
|
|---|
| 441 | mov dword [rdx + CPUMCPU.Guest.dr + 4*8], 9
|
|---|
| 442 | %endif
|
|---|
| 443 |
|
|---|
| 444 | ; parameter for all helper functions (pCtx)
|
|---|
| 445 | lea rsi, [rdx + CPUMCPU.Guest.fpu]
|
|---|
| 446 | call r9
|
|---|
| 447 |
|
|---|
| 448 | ; Load CPUM pointer into rdx
|
|---|
| 449 | mov rdx, [NAME(pCpumIC) wrt rip]
|
|---|
| 450 | CPUMCPU_FROM_CPUM_WITH_OFFSET edx, ebp
|
|---|
| 451 |
|
|---|
| 452 | %ifdef VBOX_WITH_CRASHDUMP_MAGIC
|
|---|
| 453 | mov dword [rdx + CPUMCPU.Guest.dr + 4*8], 10
|
|---|
| 454 | %endif
|
|---|
| 455 |
|
|---|
| 456 | ; Save the return code
|
|---|
| 457 | mov dword [rdx + CPUMCPU.u32RetCode], eax
|
|---|
| 458 |
|
|---|
| 459 | ; now let's switch back
|
|---|
| 460 | jmp NAME(vmmRCToHostAsm) ; rax = returncode.
|
|---|
| 461 |
|
|---|
| 462 | ENDPROC vmmR0ToRawModeAsm
|
|---|
| 463 |
|
|---|
| 464 |
|
|---|
| 465 | ;;
|
|---|
| 466 | ; Trampoline for doing a call when starting the hyper visor execution.
|
|---|
| 467 | ;
|
|---|
| 468 | ; Push any arguments to the routine.
|
|---|
| 469 | ; Push the argument frame size (cArg * 4).
|
|---|
| 470 | ; Push the call target (_cdecl convention).
|
|---|
| 471 | ; Push the address of this routine.
|
|---|
| 472 | ;
|
|---|
| 473 | ;
|
|---|
| 474 | BITS 64
|
|---|
| 475 | ALIGNCODE(16)
|
|---|
| 476 | BEGINPROC vmmRCCallTrampoline
|
|---|
| 477 | %ifdef DEBUG_STUFF
|
|---|
| 478 | COM64_S_CHAR 'c'
|
|---|
| 479 | COM64_S_CHAR 't'
|
|---|
| 480 | COM64_S_CHAR '!'
|
|---|
| 481 | %endif
|
|---|
| 482 | int3
|
|---|
| 483 | ENDPROC vmmRCCallTrampoline
|
|---|
| 484 |
|
|---|
| 485 |
|
|---|
| 486 | ;;
|
|---|
| 487 | ; The C interface.
|
|---|
| 488 | ;
|
|---|
| 489 | BITS 64
|
|---|
| 490 | ALIGNCODE(16)
|
|---|
| 491 | BEGINPROC vmmRCToHost
|
|---|
| 492 | %ifdef DEBUG_STUFF
|
|---|
| 493 | push rsi
|
|---|
| 494 | COM_NEWLINE
|
|---|
| 495 | DEBUG_CHAR('b')
|
|---|
| 496 | DEBUG_CHAR('a')
|
|---|
| 497 | DEBUG_CHAR('c')
|
|---|
| 498 | DEBUG_CHAR('k')
|
|---|
| 499 | DEBUG_CHAR('!')
|
|---|
| 500 | COM_NEWLINE
|
|---|
| 501 | pop rsi
|
|---|
| 502 | %endif
|
|---|
| 503 | int3
|
|---|
| 504 | ENDPROC vmmRCToHost
|
|---|
| 505 |
|
|---|
| 506 | ;;
|
|---|
| 507 | ; vmmRCToHostAsm
|
|---|
| 508 | ;
|
|---|
| 509 | ; This is an alternative entry point which we'll be using
|
|---|
| 510 | ; when the we have saved the guest state already or we haven't
|
|---|
| 511 | ; been messing with the guest at all.
|
|---|
| 512 | ;
|
|---|
| 513 | ; @param eax Return code.
|
|---|
| 514 | ; @uses eax, edx, ecx (or it may use them in the future)
|
|---|
| 515 | ;
|
|---|
| 516 | BITS 64
|
|---|
| 517 | ALIGNCODE(16)
|
|---|
| 518 | BEGINPROC vmmRCToHostAsm
|
|---|
| 519 | NAME(vmmRCToHostAsmNoReturn):
|
|---|
| 520 | ;; We're still in the intermediate memory context!
|
|---|
| 521 |
|
|---|
| 522 | ;;
|
|---|
| 523 | ;; Switch to compatibility mode, placing ourselves in identity mapped code.
|
|---|
| 524 | ;;
|
|---|
| 525 | jmp far [NAME(fpIDEnterTarget) wrt rip]
|
|---|
| 526 |
|
|---|
| 527 | ; 16:32 Pointer to IDEnterTarget.
|
|---|
| 528 | NAME(fpIDEnterTarget):
|
|---|
| 529 | FIXUP FIX_ID_32BIT, 0, NAME(IDExitTarget) - NAME(Start)
|
|---|
| 530 | dd 0
|
|---|
| 531 | FIXUP FIX_HYPER_CS, 0
|
|---|
| 532 | dd 0
|
|---|
| 533 |
|
|---|
| 534 | ; We're now on identity mapped pages!
|
|---|
| 535 | ALIGNCODE(16)
|
|---|
| 536 | GLOBALNAME IDExitTarget
|
|---|
| 537 | BITS 32
|
|---|
| 538 | DEBUG_CHAR('1')
|
|---|
| 539 |
|
|---|
| 540 | ; 1. Deactivate long mode by turning off paging.
|
|---|
| 541 | mov ebx, cr0
|
|---|
| 542 | and ebx, ~X86_CR0_PG
|
|---|
| 543 | mov cr0, ebx
|
|---|
| 544 | DEBUG_CHAR('2')
|
|---|
| 545 |
|
|---|
| 546 | ; 2. Load intermediate page table.
|
|---|
| 547 | FIXUP SWITCHER_FIX_INTER_CR3_HC, 1
|
|---|
| 548 | mov edx, 0ffffffffh
|
|---|
| 549 | mov cr3, edx
|
|---|
| 550 | DEBUG_CHAR('3')
|
|---|
| 551 |
|
|---|
| 552 | ; 3. Disable long mode.
|
|---|
| 553 | mov ecx, MSR_K6_EFER
|
|---|
| 554 | rdmsr
|
|---|
| 555 | DEBUG_CHAR('5')
|
|---|
| 556 | and eax, ~(MSR_K6_EFER_LME)
|
|---|
| 557 | wrmsr
|
|---|
| 558 | DEBUG_CHAR('6')
|
|---|
| 559 |
|
|---|
| 560 | %ifndef NEED_PAE_ON_HOST
|
|---|
| 561 | ; 3b. Disable PAE.
|
|---|
| 562 | mov eax, cr4
|
|---|
| 563 | and eax, ~X86_CR4_PAE
|
|---|
| 564 | mov cr4, eax
|
|---|
| 565 | DEBUG_CHAR('7')
|
|---|
| 566 | %endif
|
|---|
| 567 |
|
|---|
| 568 | ; 4. Enable paging.
|
|---|
| 569 | or ebx, X86_CR0_PG
|
|---|
| 570 | mov cr0, ebx
|
|---|
| 571 | jmp short just_a_jump
|
|---|
| 572 | just_a_jump:
|
|---|
| 573 | DEBUG_CHAR('8')
|
|---|
| 574 |
|
|---|
| 575 | ;;
|
|---|
| 576 | ;; 5. Jump to guest code mapping of the code and load the Hypervisor CS.
|
|---|
| 577 | ;;
|
|---|
| 578 | FIXUP FIX_ID_2_HC_NEAR_REL, 1, NAME(ICExitTarget) - NAME(Start)
|
|---|
| 579 | jmp near NAME(ICExitTarget)
|
|---|
| 580 |
|
|---|
| 581 | ;;
|
|---|
| 582 | ;; When we arrive at this label we're at the
|
|---|
| 583 | ;; intermediate mapping of the switching code.
|
|---|
| 584 | ;;
|
|---|
| 585 | BITS 32
|
|---|
| 586 | ALIGNCODE(16)
|
|---|
| 587 | GLOBALNAME ICExitTarget
|
|---|
| 588 | DEBUG_CHAR('8')
|
|---|
| 589 |
|
|---|
| 590 | ; load the hypervisor data selector into ds & es
|
|---|
| 591 | FIXUP FIX_HYPER_DS, 1
|
|---|
| 592 | mov eax, 0ffffh
|
|---|
| 593 | mov ds, eax
|
|---|
| 594 | mov es, eax
|
|---|
| 595 |
|
|---|
| 596 | FIXUP FIX_GC_CPUM_OFF, 1, 0
|
|---|
| 597 | mov edx, 0ffffffffh
|
|---|
| 598 | CPUMCPU_FROM_CPUM_WITH_OFFSET edx, ebp
|
|---|
| 599 | mov esi, [edx + CPUMCPU.Host.cr3]
|
|---|
| 600 | mov cr3, esi
|
|---|
| 601 |
|
|---|
| 602 | ;; now we're in host memory context, let's restore regs
|
|---|
| 603 | FIXUP FIX_HC_CPUM_OFF, 1, 0
|
|---|
| 604 | mov edx, 0ffffffffh
|
|---|
| 605 | CPUMCPU_FROM_CPUM_WITH_OFFSET edx, ebp
|
|---|
| 606 |
|
|---|
| 607 | ; restore the host EFER
|
|---|
| 608 | mov ebx, edx
|
|---|
| 609 | mov ecx, MSR_K6_EFER
|
|---|
| 610 | mov eax, [ebx + CPUMCPU.Host.efer]
|
|---|
| 611 | mov edx, [ebx + CPUMCPU.Host.efer + 4]
|
|---|
| 612 | wrmsr
|
|---|
| 613 | mov edx, ebx
|
|---|
| 614 |
|
|---|
| 615 | ; activate host gdt and idt
|
|---|
| 616 | lgdt [edx + CPUMCPU.Host.gdtr]
|
|---|
| 617 | DEBUG_CHAR('0')
|
|---|
| 618 | lidt [edx + CPUMCPU.Host.idtr]
|
|---|
| 619 | DEBUG_CHAR('1')
|
|---|
| 620 |
|
|---|
| 621 | ; Restore TSS selector; must mark it as not busy before using ltr (!)
|
|---|
| 622 | ; ASSUME that this is supposed to be 'BUSY'. (saves 20-30 ticks on the T42p)
|
|---|
| 623 | movzx eax, word [edx + CPUMCPU.Host.tr] ; eax <- TR
|
|---|
| 624 | and al, 0F8h ; mask away TI and RPL bits, get descriptor offset.
|
|---|
| 625 | add eax, [edx + CPUMCPU.Host.gdtr + 2] ; eax <- GDTR.address + descriptor offset.
|
|---|
| 626 | and dword [eax + 4], ~0200h ; clear busy flag (2nd type2 bit)
|
|---|
| 627 | ltr word [edx + CPUMCPU.Host.tr]
|
|---|
| 628 |
|
|---|
| 629 | ; activate ldt
|
|---|
| 630 | DEBUG_CHAR('2')
|
|---|
| 631 | lldt [edx + CPUMCPU.Host.ldtr]
|
|---|
| 632 |
|
|---|
| 633 | ; Restore segment registers
|
|---|
| 634 | mov eax, [edx + CPUMCPU.Host.ds]
|
|---|
| 635 | mov ds, eax
|
|---|
| 636 | mov eax, [edx + CPUMCPU.Host.es]
|
|---|
| 637 | mov es, eax
|
|---|
| 638 | mov eax, [edx + CPUMCPU.Host.fs]
|
|---|
| 639 | mov fs, eax
|
|---|
| 640 | mov eax, [edx + CPUMCPU.Host.gs]
|
|---|
| 641 | mov gs, eax
|
|---|
| 642 | ; restore stack
|
|---|
| 643 | lss esp, [edx + CPUMCPU.Host.esp]
|
|---|
| 644 |
|
|---|
| 645 | ; Control registers.
|
|---|
| 646 | mov ecx, [edx + CPUMCPU.Host.cr4]
|
|---|
| 647 | mov cr4, ecx
|
|---|
| 648 | mov ecx, [edx + CPUMCPU.Host.cr0]
|
|---|
| 649 | mov cr0, ecx
|
|---|
| 650 | ;mov ecx, [edx + CPUMCPU.Host.cr2] ; assumes this is waste of time.
|
|---|
| 651 | ;mov cr2, ecx
|
|---|
| 652 |
|
|---|
| 653 | ; restore general registers.
|
|---|
| 654 | mov edi, [edx + CPUMCPU.Host.edi]
|
|---|
| 655 | mov esi, [edx + CPUMCPU.Host.esi]
|
|---|
| 656 | mov ebx, [edx + CPUMCPU.Host.ebx]
|
|---|
| 657 | mov ebp, [edx + CPUMCPU.Host.ebp]
|
|---|
| 658 |
|
|---|
| 659 | ; store the return code in eax
|
|---|
| 660 | mov eax, [edx + CPUMCPU.u32RetCode]
|
|---|
| 661 | retf
|
|---|
| 662 | ENDPROC vmmRCToHostAsm
|
|---|
| 663 |
|
|---|
| 664 |
|
|---|
| 665 | GLOBALNAME End
|
|---|
| 666 | ;
|
|---|
| 667 | ; The description string (in the text section).
|
|---|
| 668 | ;
|
|---|
| 669 | NAME(Description):
|
|---|
| 670 | db SWITCHER_DESCRIPTION
|
|---|
| 671 | db 0
|
|---|
| 672 |
|
|---|
| 673 | extern NAME(Relocate)
|
|---|
| 674 |
|
|---|
| 675 | ;
|
|---|
| 676 | ; End the fixup records.
|
|---|
| 677 | ;
|
|---|
| 678 | BEGINDATA
|
|---|
| 679 | db FIX_THE_END ; final entry.
|
|---|
| 680 | GLOBALNAME FixupsEnd
|
|---|
| 681 |
|
|---|
| 682 | ;;
|
|---|
| 683 | ; The switcher definition structure.
|
|---|
| 684 | ALIGNDATA(16)
|
|---|
| 685 | GLOBALNAME Def
|
|---|
| 686 | istruc VMMSWITCHERDEF
|
|---|
| 687 | at VMMSWITCHERDEF.pvCode, RTCCPTR_DEF NAME(Start)
|
|---|
| 688 | at VMMSWITCHERDEF.pvFixups, RTCCPTR_DEF NAME(Fixups)
|
|---|
| 689 | at VMMSWITCHERDEF.pszDesc, RTCCPTR_DEF NAME(Description)
|
|---|
| 690 | at VMMSWITCHERDEF.pfnRelocate, RTCCPTR_DEF NAME(Relocate)
|
|---|
| 691 | at VMMSWITCHERDEF.enmType, dd SWITCHER_TYPE
|
|---|
| 692 | at VMMSWITCHERDEF.cbCode, dd NAME(End) - NAME(Start)
|
|---|
| 693 | at VMMSWITCHERDEF.offR0ToRawMode, dd NAME(vmmR0ToRawMode) - NAME(Start)
|
|---|
| 694 | at VMMSWITCHERDEF.offRCToHost, dd NAME(vmmRCToHost) - NAME(Start)
|
|---|
| 695 | at VMMSWITCHERDEF.offRCCallTrampoline, dd NAME(vmmRCCallTrampoline) - NAME(Start)
|
|---|
| 696 | at VMMSWITCHERDEF.offRCToHostAsm, dd NAME(vmmRCToHostAsm) - NAME(Start)
|
|---|
| 697 | at VMMSWITCHERDEF.offRCToHostAsmNoReturn, dd NAME(vmmRCToHostAsmNoReturn) - NAME(Start)
|
|---|
| 698 | ; disasm help
|
|---|
| 699 | at VMMSWITCHERDEF.offHCCode0, dd 0
|
|---|
| 700 | at VMMSWITCHERDEF.cbHCCode0, dd NAME(IDEnterTarget) - NAME(Start)
|
|---|
| 701 | at VMMSWITCHERDEF.offHCCode1, dd NAME(ICExitTarget) - NAME(Start)
|
|---|
| 702 | at VMMSWITCHERDEF.cbHCCode1, dd NAME(End) - NAME(ICExitTarget)
|
|---|
| 703 | at VMMSWITCHERDEF.offIDCode0, dd NAME(IDEnterTarget) - NAME(Start)
|
|---|
| 704 | at VMMSWITCHERDEF.cbIDCode0, dd NAME(ICEnterTarget) - NAME(IDEnterTarget)
|
|---|
| 705 | at VMMSWITCHERDEF.offIDCode1, dd NAME(IDExitTarget) - NAME(Start)
|
|---|
| 706 | at VMMSWITCHERDEF.cbIDCode1, dd NAME(ICExitTarget) - NAME(Start)
|
|---|
| 707 | at VMMSWITCHERDEF.offGCCode, dd 0
|
|---|
| 708 | at VMMSWITCHERDEF.cbGCCode, dd 0
|
|---|
| 709 |
|
|---|
| 710 | iend
|
|---|
| 711 |
|
|---|
