VMMSwitcher.cpp@ 43864

最後變更在這個檔案從43864是 43864,由 vboxsync 提交於 12 年前
VMM: a few compile fixes for VBOX_WITH_RAW_MODE disabled
屬性 svn:eol-style 設為 `native` 屬性 svn:keywords 設為 `Id Revision`
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1	/* $Id: VMMSwitcher.cpp 43864 2012-11-13 14:16:42Z vboxsync $ */
2	/** @file
3	* VMM - The Virtual Machine Monitor, World Switcher(s).
4	*/
5
6	/*
7	* Copyright (C) 2006-2012 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.alldomusa.eu.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_VMM
22	#include <VBox/vmm/vmm.h>
23	#include <VBox/vmm/pgm.h>
24	#include <VBox/vmm/selm.h>
25	#include <VBox/vmm/mm.h>
26	#include <VBox/sup.h>
27	#include "VMMInternal.h"
28	#include "VMMSwitcher.h"
29	#include <VBox/vmm/vm.h>
30	#include <VBox/dis.h>
31
32	#include <VBox/err.h>
33	#include <VBox/param.h>
34	#include <iprt/assert.h>
35	#include <iprt/alloc.h>
36	#include <iprt/asm.h>
37	#include <iprt/asm-amd64-x86.h>
38	#include <iprt/string.h>
39	#include <iprt/ctype.h>
40
41
42	/*******************************************************************************
43	* Global Variables *
44	*******************************************************************************/
45	/** Array of switcher definitions.
46	* The type and index shall match!
47	*/
48	static PVMMSWITCHERDEF s_apSwitchers[VMMSWITCHER_MAX] =
49	{
50	NULL, /* invalid entry */
51	#ifdef VBOX_WITH_RAW_MODE
52	# ifndef RT_ARCH_AMD64
53	&vmmR3Switcher32BitTo32Bit_Def,
54	&vmmR3Switcher32BitToPAE_Def,
55	&vmmR3Switcher32BitToAMD64_Def,
56	&vmmR3SwitcherPAETo32Bit_Def,
57	&vmmR3SwitcherPAEToPAE_Def,
58	&vmmR3SwitcherPAEToAMD64_Def,
59	NULL, //&vmmR3SwitcherPAETo32Bit_Def,
60	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
61	&vmmR3SwitcherAMD64ToPAE_Def,
62	# else
63	NULL, //&vmmR3SwitcherAMD64ToPAE_Def,
64	# endif
65	NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
66	# else /* RT_ARCH_AMD64 */
67	NULL, //&vmmR3Switcher32BitTo32Bit_Def,
68	NULL, //&vmmR3Switcher32BitToPAE_Def,
69	NULL, //&vmmR3Switcher32BitToAMD64_Def,
70	NULL, //&vmmR3SwitcherPAETo32Bit_Def,
71	NULL, //&vmmR3SwitcherPAEToPAE_Def,
72	NULL, //&vmmR3SwitcherPAEToAMD64_Def,
73	&vmmR3SwitcherAMD64To32Bit_Def,
74	&vmmR3SwitcherAMD64ToPAE_Def,
75	NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
76	# endif /* RT_ARCH_AMD64 */
77	#else /* !VBOX_WITH_RAW_MODE */
78	NULL,
79	NULL,
80	NULL,
81	NULL,
82	NULL,
83	NULL,
84	NULL,
85	NULL,
86	NULL
87	#endif /* !VBOX_WITH_RAW_MODE */
88	};
89
90
91	/**
92	* VMMR3Init worker that initiates the switcher code (aka core code).
93	*
94	* This is core per VM code which might need fixups and/or for ease of use are
95	* put on linear contiguous backing.
96	*
97	* @returns VBox status code.
98	* @param pVM Pointer to the VM.
99	*/
100	int vmmR3SwitcherInit(PVM pVM)
101	{
102	#ifndef VBOX_WITH_RAW_MODE
103	return VINF_SUCCESS;
104	#else
105	/*
106	* Calc the size.
107	*/
108	unsigned cbCoreCode = 0;
109	for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
110	{
111	pVM->vmm.s.aoffSwitchers[iSwitcher] = cbCoreCode;
112	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
113	if (pSwitcher)
114	{
115	AssertRelease((unsigned)pSwitcher->enmType == iSwitcher);
116	cbCoreCode += RT_ALIGN_32(pSwitcher->cbCode + 1, 32);
117	}
118	}
119
120	/*
121	* Allocate contiguous pages for switchers and deal with
122	* conflicts in the intermediate mapping of the code.
123	*/
124	pVM->vmm.s.cbCoreCode = RT_ALIGN_32(cbCoreCode, PAGE_SIZE);
125	pVM->vmm.s.pvCoreCodeR3 = SUPR3ContAlloc(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
126	int rc = VERR_NO_MEMORY;
127	if (pVM->vmm.s.pvCoreCodeR3)
128	{
129	rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
130	if (rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT)
131	{
132	/* try more allocations - Solaris, Linux. */
133	const unsigned cTries = 8234;
134	struct VMMInitBadTry
135	{
136	RTR0PTR pvR0;
137	void *pvR3;
138	RTHCPHYS HCPhys;
139	RTUINT cb;
140	} paBadTries = (struct VMMInitBadTry )RTMemTmpAlloc(sizeof(paBadTries) cTries);
141	AssertReturn(paBadTries, VERR_NO_TMP_MEMORY);
142	unsigned i = 0;
143	do
144	{
145	paBadTries[i].pvR3 = pVM->vmm.s.pvCoreCodeR3;
146	paBadTries[i].pvR0 = pVM->vmm.s.pvCoreCodeR0;
147	paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
148	i++;
149	pVM->vmm.s.pvCoreCodeR0 = NIL_RTR0PTR;
150	pVM->vmm.s.HCPhysCoreCode = NIL_RTHCPHYS;
151	pVM->vmm.s.pvCoreCodeR3 = SUPR3ContAlloc(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
152	if (!pVM->vmm.s.pvCoreCodeR3)
153	break;
154	rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
155	} while ( rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT
156	&& i < cTries - 1);
157
158	/* cleanup */
159	if (RT_FAILURE(rc))
160	{
161	paBadTries[i].pvR3 = pVM->vmm.s.pvCoreCodeR3;
162	paBadTries[i].pvR0 = pVM->vmm.s.pvCoreCodeR0;
163	paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
164	paBadTries[i].cb = pVM->vmm.s.cbCoreCode;
165	i++;
166	LogRel(("Failed to allocated and map core code: rc=%Rrc\n", rc));
167	}
168	while (i-- > 0)
169	{
170	LogRel(("Core code alloc attempt #%d: pvR3=%p pvR0=%p HCPhys=%RHp\n",
171	i, paBadTries[i].pvR3, paBadTries[i].pvR0, paBadTries[i].HCPhys));
172	SUPR3ContFree(paBadTries[i].pvR3, paBadTries[i].cb >> PAGE_SHIFT);
173	}
174	RTMemTmpFree(paBadTries);
175	}
176	}
177	if (RT_SUCCESS(rc))
178	{
179	/*
180	* copy the code.
181	*/
182	for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
183	{
184	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
185	if (pSwitcher)
186	memcpy((uint8_t *)pVM->vmm.s.pvCoreCodeR3 + pVM->vmm.s.aoffSwitchers[iSwitcher],
187	pSwitcher->pvCode, pSwitcher->cbCode);
188	}
189
190	/*
191	* Map the code into the GC address space.
192	*/
193	RTGCPTR GCPtr;
194	rc = MMR3HyperMapHCPhys(pVM, pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.HCPhysCoreCode,
195	cbCoreCode, "Core Code", &GCPtr);
196	if (RT_SUCCESS(rc))
197	{
198	pVM->vmm.s.pvCoreCodeRC = GCPtr;
199	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
200	LogRel(("CoreCode: R3=%RHv R0=%RHv RC=%RRv Phys=%RHp cb=%#x\n",
201	pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.pvCoreCodeR0, pVM->vmm.s.pvCoreCodeRC, pVM->vmm.s.HCPhysCoreCode, pVM->vmm.s.cbCoreCode));
202
203	/*
204	* Finally, PGM probably has selected a switcher already but we need
205	* to get the routine addresses, so we'll reselect it.
206	* This may legally fail so, we're ignoring the rc.
207	*/
208	VMMR3SelectSwitcher(pVM, pVM->vmm.s.enmSwitcher);
209	return rc;
210	}
211
212	/* shit */
213	AssertMsgFailed(("PGMR3Map(,%RRv, %RHp, %#x, 0) failed with rc=%Rrc\n", pVM->vmm.s.pvCoreCodeRC, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, rc));
214	SUPR3ContFree(pVM->vmm.s.pvCoreCodeR3, pVM->vmm.s.cbCoreCode >> PAGE_SHIFT);
215	}
216	else
217	VMSetError(pVM, rc, RT_SRC_POS,
218	N_("Failed to allocate %d bytes of contiguous memory for the world switcher code"),
219	cbCoreCode);
220
221	pVM->vmm.s.pvCoreCodeR3 = NULL;
222	pVM->vmm.s.pvCoreCodeR0 = NIL_RTR0PTR;
223	pVM->vmm.s.pvCoreCodeRC = 0;
224	return rc;
225	#endif
226	}
227
228	/**
229	* Relocate the switchers, called by VMMR#Relocate.
230	*
231	* @param pVM Pointer to the VM.
232	* @param offDelta The relocation delta.
233	*/
234	void vmmR3SwitcherRelocate(PVM pVM, RTGCINTPTR offDelta)
235	{
236	#ifdef VBOX_WITH_RAW_MODE
237	/*
238	* Relocate all the switchers.
239	*/
240	for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
241	{
242	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
243	if (pSwitcher && pSwitcher->pfnRelocate)
244	{
245	unsigned off = pVM->vmm.s.aoffSwitchers[iSwitcher];
246	pSwitcher->pfnRelocate(pVM,
247	pSwitcher,
248	pVM->vmm.s.pvCoreCodeR0 + off,
249	(uint8_t *)pVM->vmm.s.pvCoreCodeR3 + off,
250	pVM->vmm.s.pvCoreCodeRC + off,
251	pVM->vmm.s.HCPhysCoreCode + off);
252	}
253	}
254
255	/*
256	* Recalc the RC address for the current switcher.
257	*/
258	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[pVM->vmm.s.enmSwitcher];
259	RTRCPTR RCPtr = pVM->vmm.s.pvCoreCodeRC + pVM->vmm.s.aoffSwitchers[pVM->vmm.s.enmSwitcher];
260	pVM->vmm.s.pfnRCToHost = RCPtr + pSwitcher->offRCToHost;
261	pVM->vmm.s.pfnCallTrampolineRC = RCPtr + pSwitcher->offRCCallTrampoline;
262	pVM->pfnVMMRCToHostAsm = RCPtr + pSwitcher->offRCToHostAsm;
263	pVM->pfnVMMRCToHostAsmNoReturn = RCPtr + pSwitcher->offRCToHostAsmNoReturn;
264
265	// AssertFailed();
266	#else
267	NOREF(pVM);
268	#endif
269	NOREF(offDelta);
270	}
271
272
273	#ifdef VBOX_WITH_RAW_MODE
274
275	/**
276	* Generic switcher code relocator.
277	*
278	* @param pVM Pointer to the VM.
279	* @param pSwitcher The switcher definition.
280	* @param pu8CodeR3 Pointer to the core code block for the switcher, ring-3 mapping.
281	* @param R0PtrCode Pointer to the core code block for the switcher, ring-0 mapping.
282	* @param GCPtrCode The guest context address corresponding to pu8Code.
283	* @param u32IDCode The identity mapped (ID) address corresponding to pu8Code.
284	* @param SelCS The hypervisor CS selector.
285	* @param SelDS The hypervisor DS selector.
286	* @param SelTSS The hypervisor TSS selector.
287	* @param GCPtrGDT The GC address of the hypervisor GDT.
288	* @param SelCS64 The 64-bit mode hypervisor CS selector.
289	*/
290	static void vmmR3SwitcherGenericRelocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode,
291	RTSEL SelCS, RTSEL SelDS, RTSEL SelTSS, RTGCPTR GCPtrGDT, RTSEL SelCS64)
292	{
293	union
294	{
295	const uint8_t *pu8;
296	const uint16_t *pu16;
297	const uint32_t *pu32;
298	const uint64_t *pu64;
299	const void *pv;
300	uintptr_t u;
301	} u;
302	u.pv = pSwitcher->pvFixups;
303
304	/*
305	* Process fixups.
306	*/
307	uint8_t u8;
308	while ((u8 = *u.pu8++) != FIX_THE_END)
309	{
310	/*
311	* Get the source (where to write the fixup).
312	*/
313	uint32_t offSrc = *u.pu32++;
314	Assert(offSrc < pSwitcher->cbCode);
315	union
316	{
317	uint8_t *pu8;
318	uint16_t *pu16;
319	uint32_t *pu32;
320	uint64_t *pu64;
321	uintptr_t u;
322	} uSrc;
323	uSrc.pu8 = pu8CodeR3 + offSrc;
324
325	/* The fixup target and method depends on the type. */
326	switch (u8)
327	{
328	/*
329	* 32-bit relative, source in HC and target in GC.
330	*/
331	case FIX_HC_2_GC_NEAR_REL:
332	{
333	Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
334	uint32_t offTrg = *u.pu32++;
335	Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
336	*uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (uSrc.u + 4));
337	break;
338	}
339
340	/*
341	* 32-bit relative, source in HC and target in ID.
342	*/
343	case FIX_HC_2_ID_NEAR_REL:
344	{
345	Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
346	uint32_t offTrg = *u.pu32++;
347	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
348	*uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (R0PtrCode + offSrc + 4));
349	break;
350	}
351
352	/*
353	* 32-bit relative, source in GC and target in HC.
354	*/
355	case FIX_GC_2_HC_NEAR_REL:
356	{
357	Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
358	uint32_t offTrg = *u.pu32++;
359	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
360	*uSrc.pu32 = (uint32_t)((R0PtrCode + offTrg) - (GCPtrCode + offSrc + 4));
361	break;
362	}
363
364	/*
365	* 32-bit relative, source in GC and target in ID.
366	*/
367	case FIX_GC_2_ID_NEAR_REL:
368	{
369	AssertMsg(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode, ("%x - %x < %x\n", offSrc, pSwitcher->offGCCode, pSwitcher->cbGCCode));
370	uint32_t offTrg = *u.pu32++;
371	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
372	*uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (GCPtrCode + offSrc + 4));
373	break;
374	}
375
376	/*
377	* 32-bit relative, source in ID and target in HC.
378	*/
379	case FIX_ID_2_HC_NEAR_REL:
380	{
381	Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
382	uint32_t offTrg = *u.pu32++;
383	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
384	*uSrc.pu32 = (uint32_t)((R0PtrCode + offTrg) - (u32IDCode + offSrc + 4));
385	break;
386	}
387
388	/*
389	* 32-bit relative, source in ID and target in HC.
390	*/
391	case FIX_ID_2_GC_NEAR_REL:
392	{
393	Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
394	uint32_t offTrg = *u.pu32++;
395	Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
396	*uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (u32IDCode + offSrc + 4));
397	break;
398	}
399
400	/*
401	* 16:32 far jump, target in GC.
402	*/
403	case FIX_GC_FAR32:
404	{
405	uint32_t offTrg = *u.pu32++;
406	Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
407	*uSrc.pu32++ = (uint32_t)(GCPtrCode + offTrg);
408	*uSrc.pu16++ = SelCS;
409	break;
410	}
411
412	/*
413	* Make 32-bit GC pointer given CPUM offset.
414	*/
415	case FIX_GC_CPUM_OFF:
416	{
417	uint32_t offCPUM = *u.pu32++;
418	Assert(offCPUM < sizeof(pVM->cpum));
419	*uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->cpum) + offCPUM);
420	break;
421	}
422
423	/*
424	* Make 32-bit GC pointer given CPUMCPU offset.
425	*/
426	case FIX_GC_CPUMCPU_OFF:
427	{
428	uint32_t offCPUM = *u.pu32++;
429	Assert(offCPUM < sizeof(pVM->aCpus[0].cpum));
430	*uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->aCpus[0].cpum) + offCPUM);
431	break;
432	}
433
434	/*
435	* Make 32-bit GC pointer given VM offset.
436	*/
437	case FIX_GC_VM_OFF:
438	{
439	uint32_t offVM = *u.pu32++;
440	Assert(offVM < sizeof(VM));
441	*uSrc.pu32 = (uint32_t)(VM_RC_ADDR(pVM, pVM) + offVM);
442	break;
443	}
444
445	/*
446	* Make 32-bit HC pointer given CPUM offset.
447	*/
448	case FIX_HC_CPUM_OFF:
449	{
450	uint32_t offCPUM = *u.pu32++;
451	Assert(offCPUM < sizeof(pVM->cpum));
452	*uSrc.pu32 = (uint32_t)pVM->pVMR0 + RT_OFFSETOF(VM, cpum) + offCPUM;
453	break;
454	}
455
456	/*
457	* Make 32-bit R0 pointer given VM offset.
458	*/
459	case FIX_HC_VM_OFF:
460	{
461	uint32_t offVM = *u.pu32++;
462	Assert(offVM < sizeof(VM));
463	*uSrc.pu32 = (uint32_t)pVM->pVMR0 + offVM;
464	break;
465	}
466
467	/*
468	* Store the 32-Bit CR3 (32-bit) for the intermediate memory context.
469	*/
470	case FIX_INTER_32BIT_CR3:
471	{
472
473	*uSrc.pu32 = PGMGetInter32BitCR3(pVM);
474	break;
475	}
476
477	/*
478	* Store the PAE CR3 (32-bit) for the intermediate memory context.
479	*/
480	case FIX_INTER_PAE_CR3:
481	{
482
483	*uSrc.pu32 = PGMGetInterPaeCR3(pVM);
484	break;
485	}
486
487	/*
488	* Store the AMD64 CR3 (32-bit) for the intermediate memory context.
489	*/
490	case FIX_INTER_AMD64_CR3:
491	{
492
493	*uSrc.pu32 = PGMGetInterAmd64CR3(pVM);
494	break;
495	}
496
497	/*
498	* Store Hypervisor CS (16-bit).
499	*/
500	case FIX_HYPER_CS:
501	{
502	*uSrc.pu16 = SelCS;
503	break;
504	}
505
506	/*
507	* Store Hypervisor DS (16-bit).
508	*/
509	case FIX_HYPER_DS:
510	{
511	*uSrc.pu16 = SelDS;
512	break;
513	}
514
515	/*
516	* Store Hypervisor TSS (16-bit).
517	*/
518	case FIX_HYPER_TSS:
519	{
520	*uSrc.pu16 = SelTSS;
521	break;
522	}
523
524	/*
525	* Store the 32-bit GC address of the 2nd dword of the TSS descriptor (in the GDT).
526	*/
527	case FIX_GC_TSS_GDTE_DW2:
528	{
529	RTGCPTR GCPtr = GCPtrGDT + (SelTSS & ~7) + 4;
530	*uSrc.pu32 = (uint32_t)GCPtr;
531	break;
532	}
533
534	/*
535	* Store the EFER or mask for the 32->64 bit switcher.
536	*/
537	case FIX_EFER_OR_MASK:
538	{
539	uint32_t u32OrMask = MSR_K6_EFER_LME \| MSR_K6_EFER_SCE;
540	/*
541	* We don't care if cpuid 0x8000001 isn't supported as that implies
542	* long mode isn't supported either, so this switched would never be used.
543	*/
544	if (!!(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_NX))
545	u32OrMask \|= MSR_K6_EFER_NXE;
546
547	*uSrc.pu32 = u32OrMask;
548	break;
549	}
550
551	/*
552	* Insert relative jump to specified target it FXSAVE/FXRSTOR isn't supported by the cpu.
553	*/
554	case FIX_NO_FXSAVE_JMP:
555	{
556	uint32_t offTrg = *u.pu32++;
557	Assert(offTrg < pSwitcher->cbCode);
558	if (!CPUMSupportsFXSR(pVM))
559	{
560	uSrc.pu8++ = 0xe9; / jmp rel32 */
561	*uSrc.pu32++ = offTrg - (offSrc + 5);
562	}
563	else
564	{
565	uSrc.pu8++ = ((uint8_t *)pSwitcher->pvCode + offSrc);
566	uSrc.pu32++ = (uint32_t )((uint8_t )pSwitcher->pvCode + offSrc + 1);
567	}
568	break;
569	}
570
571	/*
572	* Insert relative jump to specified target it SYSENTER isn't used by the host.
573	*/
574	case FIX_NO_SYSENTER_JMP:
575	{
576	uint32_t offTrg = *u.pu32++;
577	Assert(offTrg < pSwitcher->cbCode);
578	if (!CPUMIsHostUsingSysEnter(pVM))
579	{
580	uSrc.pu8++ = 0xe9; / jmp rel32 */
581	*uSrc.pu32++ = offTrg - (offSrc + 5);
582	}
583	else
584	{
585	uSrc.pu8++ = ((uint8_t *)pSwitcher->pvCode + offSrc);
586	uSrc.pu32++ = (uint32_t )((uint8_t )pSwitcher->pvCode + offSrc + 1);
587	}
588	break;
589	}
590
591	/*
592	* Insert relative jump to specified target it SYSCALL isn't used by the host.
593	*/
594	case FIX_NO_SYSCALL_JMP:
595	{
596	uint32_t offTrg = *u.pu32++;
597	Assert(offTrg < pSwitcher->cbCode);
598	if (!CPUMIsHostUsingSysCall(pVM))
599	{
600	uSrc.pu8++ = 0xe9; / jmp rel32 */
601	*uSrc.pu32++ = offTrg - (offSrc + 5);
602	}
603	else
604	{
605	uSrc.pu8++ = ((uint8_t *)pSwitcher->pvCode + offSrc);
606	uSrc.pu32++ = (uint32_t )((uint8_t )pSwitcher->pvCode + offSrc + 1);
607	}
608	break;
609	}
610
611	/*
612	* 32-bit HC pointer fixup to (HC) target within the code (32-bit offset).
613	*/
614	case FIX_HC_32BIT:
615	{
616	uint32_t offTrg = *u.pu32++;
617	Assert(offSrc < pSwitcher->cbCode);
618	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
619	*uSrc.pu32 = R0PtrCode + offTrg;
620	break;
621	}
622
623	#if defined(RT_ARCH_AMD64) \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
624	/*
625	* 64-bit HC Code Selector (no argument).
626	*/
627	case FIX_HC_64BIT_CS:
628	{
629	Assert(offSrc < pSwitcher->cbCode);
630	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
631	uSrc.pu16 = 0x80; / KERNEL64_CS from i386/seg.h */
632	# else
633	AssertFatalMsgFailed(("FIX_HC_64BIT_CS not implemented for this host\n"));
634	# endif
635	break;
636	}
637
638	/*
639	* 64-bit HC pointer to the CPUM instance data (no argument).
640	*/
641	case FIX_HC_64BIT_CPUM:
642	{
643	Assert(offSrc < pSwitcher->cbCode);
644	*uSrc.pu64 = pVM->pVMR0 + RT_OFFSETOF(VM, cpum);
645	break;
646	}
647	#endif
648	/*
649	* 64-bit HC pointer fixup to (HC) target within the code (32-bit offset).
650	*/
651	case FIX_HC_64BIT:
652	{
653	uint32_t offTrg = *u.pu32++;
654	Assert(offSrc < pSwitcher->cbCode);
655	Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 \|\| offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
656	*uSrc.pu64 = R0PtrCode + offTrg;
657	break;
658	}
659
660	#ifdef RT_ARCH_X86
661	case FIX_GC_64_BIT_CPUM_OFF:
662	{
663	uint32_t offCPUM = *u.pu32++;
664	Assert(offCPUM < sizeof(pVM->cpum));
665	*uSrc.pu64 = (uint32_t)(VM_RC_ADDR(pVM, &pVM->cpum) + offCPUM);
666	break;
667	}
668	#endif
669
670	/*
671	* 32-bit ID pointer to (ID) target within the code (32-bit offset).
672	*/
673	case FIX_ID_32BIT:
674	{
675	uint32_t offTrg = *u.pu32++;
676	Assert(offSrc < pSwitcher->cbCode);
677	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
678	*uSrc.pu32 = u32IDCode + offTrg;
679	break;
680	}
681
682	/*
683	* 64-bit ID pointer to (ID) target within the code (32-bit offset).
684	*/
685	case FIX_ID_64BIT:
686	case FIX_HC_64BIT_NOCHECK:
687	{
688	uint32_t offTrg = *u.pu32++;
689	Assert(offSrc < pSwitcher->cbCode);
690	Assert(u8 == FIX_HC_64BIT_NOCHECK \|\| offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
691	*uSrc.pu64 = u32IDCode + offTrg;
692	break;
693	}
694
695	/*
696	* Far 16:32 ID pointer to 64-bit mode (ID) target within the code (32-bit offset).
697	*/
698	case FIX_ID_FAR32_TO_64BIT_MODE:
699	{
700	uint32_t offTrg = *u.pu32++;
701	Assert(offSrc < pSwitcher->cbCode);
702	Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 \|\| offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
703	*uSrc.pu32++ = u32IDCode + offTrg;
704	*uSrc.pu16 = SelCS64;
705	AssertRelease(SelCS64);
706	break;
707	}
708
709	#ifdef VBOX_WITH_NMI
710	/*
711	* 32-bit address to the APIC base.
712	*/
713	case FIX_GC_APIC_BASE_32BIT:
714	{
715	*uSrc.pu32 = pVM->vmm.s.GCPtrApicBase;
716	break;
717	}
718	#endif
719
720	default:
721	AssertReleaseMsgFailed(("Unknown fixup %d in switcher %s\n", u8, pSwitcher->pszDesc));
722	break;
723	}
724	}
725
726	#ifdef LOG_ENABLED
727	/*
728	* If Log2 is enabled disassemble the switcher code.
729	*
730	* The switcher code have 1-2 HC parts, 1 GC part and 0-2 ID parts.
731	*/
732	if (LogIs2Enabled())
733	{
734	RTLogPrintf("* Disassembly of switcher %d '%s' %#x bytes *\n"
735	" R0PtrCode = %p\n"
736	" pu8CodeR3 = %p\n"
737	" GCPtrCode = %RGv\n"
738	" u32IDCode = %08x\n"
739	" pVMRC = %RRv\n"
740	" pCPUMRC = %RRv\n"
741	" pVMR3 = %p\n"
742	" pCPUMR3 = %p\n"
743	" GCPtrGDT = %RGv\n"
744	" InterCR3s = %08RHp, %08RHp, %08RHp (32-Bit, PAE, AMD64)\n"
745	" HyperCR3s = %08RHp (32-Bit, PAE & AMD64)\n"
746	" SelCS = %04x\n"
747	" SelDS = %04x\n"
748	" SelCS64 = %04x\n"
749	" SelTSS = %04x\n",
750	pSwitcher->enmType, pSwitcher->pszDesc, pSwitcher->cbCode,
751	R0PtrCode,
752	pu8CodeR3,
753	GCPtrCode,
754	u32IDCode,
755	VM_RC_ADDR(pVM, pVM),
756	VM_RC_ADDR(pVM, &pVM->cpum),
757	pVM,
758	&pVM->cpum,
759	GCPtrGDT,
760	PGMGetInter32BitCR3(pVM), PGMGetInterPaeCR3(pVM), PGMGetInterAmd64CR3(pVM),
761	PGMGetHyperCR3(VMMGetCpu(pVM)),
762	SelCS, SelDS, SelCS64, SelTSS);
763
764	uint32_t offCode = 0;
765	while (offCode < pSwitcher->cbCode)
766	{
767	/*
768	* Figure out where this is.
769	*/
770	const char *pszDesc = NULL;
771	RTUINTPTR uBase;
772	uint32_t cbCode;
773	if (offCode - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0)
774	{
775	pszDesc = "HCCode0";
776	uBase = R0PtrCode;
777	offCode = pSwitcher->offHCCode0;
778	cbCode = pSwitcher->cbHCCode0;
779	}
780	else if (offCode - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1)
781	{
782	pszDesc = "HCCode1";
783	uBase = R0PtrCode;
784	offCode = pSwitcher->offHCCode1;
785	cbCode = pSwitcher->cbHCCode1;
786	}
787	else if (offCode - pSwitcher->offGCCode < pSwitcher->cbGCCode)
788	{
789	pszDesc = "GCCode";
790	uBase = GCPtrCode;
791	offCode = pSwitcher->offGCCode;
792	cbCode = pSwitcher->cbGCCode;
793	}
794	else if (offCode - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0)
795	{
796	pszDesc = "IDCode0";
797	uBase = u32IDCode;
798	offCode = pSwitcher->offIDCode0;
799	cbCode = pSwitcher->cbIDCode0;
800	}
801	else if (offCode - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1)
802	{
803	pszDesc = "IDCode1";
804	uBase = u32IDCode;
805	offCode = pSwitcher->offIDCode1;
806	cbCode = pSwitcher->cbIDCode1;
807	}
808	else
809	{
810	RTLogPrintf(" %04x: %02x '%c' (nowhere)\n",
811	offCode, pu8CodeR3[offCode], RT_C_IS_PRINT(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
812	offCode++;
813	continue;
814	}
815
816	/*
817	* Disassemble it.
818	*/
819	RTLogPrintf(" %s: offCode=%#x cbCode=%#x\n", pszDesc, offCode, cbCode);
820
821	while (cbCode > 0)
822	{
823	/* try label it */
824	if (pSwitcher->offR0ToRawMode == offCode)
825	RTLogPrintf(" *R0ToRawMode:\n");
826	if (pSwitcher->offRCToHost == offCode)
827	RTLogPrintf(" *RCToHost:\n");
828	if (pSwitcher->offRCCallTrampoline == offCode)
829	RTLogPrintf(" *RCCallTrampoline:\n");
830	if (pSwitcher->offRCToHostAsm == offCode)
831	RTLogPrintf(" *RCToHostAsm:\n");
832	if (pSwitcher->offRCToHostAsmNoReturn == offCode)
833	RTLogPrintf(" *RCToHostAsmNoReturn:\n");
834
835	/* disas */
836	uint32_t cbInstr = 0;
837	DISCPUSTATE Cpu;
838	char szDisas[256];
839	int rc = DISInstr(pu8CodeR3 + offCode, DISCPUMODE_32BIT, &Cpu, &cbInstr);
840	if (RT_SUCCESS(rc))
841	{
842	Cpu.uInstrAddr += uBase - (uintptr_t)pu8CodeR3;
843	DISFormatYasmEx(&Cpu, szDisas, sizeof(szDisas),
844	DIS_FMT_FLAGS_ADDR_LEFT \| DIS_FMT_FLAGS_BYTES_LEFT \| DIS_FMT_FLAGS_BYTES_SPACED
845	\| DIS_FMT_FLAGS_RELATIVE_BRANCH,
846	NULL, NULL);
847	}
848	if (RT_SUCCESS(rc))
849	RTLogPrintf(" %04x: %s\n", offCode, szDisas);
850	else
851	{
852	RTLogPrintf(" %04x: %02x '%c' (rc=%Rrc\n",
853	offCode, pu8CodeR3[offCode], RT_C_IS_PRINT(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ', rc);
854	cbInstr = 1;
855	}
856	offCode += cbInstr;
857	cbCode -= RT_MIN(cbInstr, cbCode);
858	}
859	}
860	}
861	#endif
862	}
863
864	/**
865	* Relocator for the 32-Bit to 32-Bit world switcher.
866	*/
867	DECLCALLBACK(void) vmmR3Switcher32BitTo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
868	{
869	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
870	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
871	}
872
873
874	/**
875	* Relocator for the 32-Bit to PAE world switcher.
876	*/
877	DECLCALLBACK(void) vmmR3Switcher32BitToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
878	{
879	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
880	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
881	}
882
883
884	/**
885	* Relocator for the 32-Bit to AMD64 world switcher.
886	*/
887	DECLCALLBACK(void) vmmR3Switcher32BitToAMD64_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
888	{
889	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
890	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
891	}
892
893
894	/**
895	* Relocator for the PAE to 32-Bit world switcher.
896	*/
897	DECLCALLBACK(void) vmmR3SwitcherPAETo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
898	{
899	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
900	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
901	}
902
903
904	/**
905	* Relocator for the PAE to PAE world switcher.
906	*/
907	DECLCALLBACK(void) vmmR3SwitcherPAEToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
908	{
909	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
910	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
911	}
912
913	/**
914	* Relocator for the PAE to AMD64 world switcher.
915	*/
916	DECLCALLBACK(void) vmmR3SwitcherPAEToAMD64_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
917	{
918	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
919	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
920	}
921
922
923	/**
924	* Relocator for the AMD64 to 32-bit world switcher.
925	*/
926	DECLCALLBACK(void) vmmR3SwitcherAMD64To32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
927	{
928	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
929	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
930	}
931
932
933	/**
934	* Relocator for the AMD64 to PAE world switcher.
935	*/
936	DECLCALLBACK(void) vmmR3SwitcherAMD64ToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, RTR0PTR R0PtrCode, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
937	{
938	vmmR3SwitcherGenericRelocate(pVM, pSwitcher, R0PtrCode, pu8CodeR3, GCPtrCode, u32IDCode,
939	SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
940	}
941
942
943	/**
944	* Selects the switcher to be used for switching to raw-mode context.
945	*
946	* @returns VBox status code.
947	* @param pVM Pointer to the VM.
948	* @param enmSwitcher The new switcher.
949	* @remark This function may be called before the VMM is initialized.
950	*/
951	VMMR3_INT_DECL(int) VMMR3SelectSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
952	{
953	/*
954	* Validate input.
955	*/
956	if ( enmSwitcher < VMMSWITCHER_INVALID
957	\|\| enmSwitcher >= VMMSWITCHER_MAX)
958	{
959	AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
960	return VERR_INVALID_PARAMETER;
961	}
962
963	/* Do nothing if the switcher is disabled. */
964	if (pVM->vmm.s.fSwitcherDisabled)
965	return VINF_SUCCESS;
966
967	/*
968	* Select the new switcher.
969	*/
970	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[enmSwitcher];
971	if (pSwitcher)
972	{
973	Log(("VMMR3SelectSwitcher: enmSwitcher %d -> %d %s\n", pVM->vmm.s.enmSwitcher, enmSwitcher, pSwitcher->pszDesc));
974	pVM->vmm.s.enmSwitcher = enmSwitcher;
975
976	RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvCoreCodeR0 type */
977	pVM->vmm.s.pfnR0ToRawMode = pbCodeR0 + pSwitcher->offR0ToRawMode;
978
979	RTRCPTR RCPtr = pVM->vmm.s.pvCoreCodeRC + pVM->vmm.s.aoffSwitchers[enmSwitcher];
980	pVM->vmm.s.pfnRCToHost = RCPtr + pSwitcher->offRCToHost;
981	pVM->vmm.s.pfnCallTrampolineRC = RCPtr + pSwitcher->offRCCallTrampoline;
982	pVM->pfnVMMRCToHostAsm = RCPtr + pSwitcher->offRCToHostAsm;
983	pVM->pfnVMMRCToHostAsmNoReturn = RCPtr + pSwitcher->offRCToHostAsmNoReturn;
984	return VINF_SUCCESS;
985	}
986
987	return VERR_NOT_IMPLEMENTED;
988	}
989
990	#endif /* VBOX_WITH_RAW_MODE */
991
992
993	/**
994	* Disable the switcher logic permanently.
995	*
996	* @returns VBox status code.
997	* @param pVM Pointer to the VM.
998	*/
999	VMMR3_INT_DECL(int) VMMR3DisableSwitcher(PVM pVM)
1000	{
1001	/** @todo r=bird: I would suggest that we create a dummy switcher which just does something like:
1002	* @code
1003	* mov eax, VERR_VMM_DUMMY_SWITCHER
1004	* ret
1005	* @endcode
1006	* And then check for fSwitcherDisabled in VMMR3SelectSwitcher() in order to prevent it from being removed.
1007	*/
1008	pVM->vmm.s.fSwitcherDisabled = true;
1009	return VINF_SUCCESS;
1010	}
1011
1012
1013	/**
1014	* Gets the switcher to be used for switching to GC.
1015	*
1016	* @returns host to guest ring 0 switcher entrypoint
1017	* @param pVM Pointer to the VM.
1018	* @param enmSwitcher The new switcher.
1019	*/
1020	VMMR3_INT_DECL(RTR0PTR) VMMR3GetHostToGuestSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
1021	{
1022	/*
1023	* Validate input.
1024	*/
1025	if ( enmSwitcher < VMMSWITCHER_INVALID
1026	\|\| enmSwitcher >= VMMSWITCHER_MAX)
1027	{
1028	AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
1029	return NIL_RTR0PTR;
1030	}
1031
1032	/*
1033	* Select the new switcher.
1034	*/
1035	PVMMSWITCHERDEF pSwitcher = s_apSwitchers[enmSwitcher];
1036	if (pSwitcher)
1037	{
1038	RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvCoreCodeR0 type */
1039	return pbCodeR0 + pSwitcher->offR0ToRawMode;
1040	}
1041	return NIL_RTR0PTR;
1042	}

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source: vbox/trunk/src/VBox/VMM/VMMR3/VMMSwitcher.cpp@ 43864

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