SELM.cpp@ 45705

最後變更在這個檔案從45705是 45705,由 vboxsync 提交於 12 年前
Retired SELMR3DisableMonitoring.
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1	/* $Id: SELM.cpp 45705 2013-04-24 14:37:42Z vboxsync $ */
2	/** @file
3	* SELM - The Selector Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.alldomusa.eu.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_selm SELM - The Selector Manager
19	*
20	* SELM takes care of GDT, LDT and TSS shadowing in raw-mode, and the injection
21	* of a few hyper selector for the raw-mode context. In the hardware assisted
22	* virtualization mode its only task is to decode entries in the guest GDT or
23	* LDT once in a while.
24	*
25	* @see grp_selm
26	*
27	*
28	* @section seg_selm_shadowing Shadowing
29	*
30	* SELMR3UpdateFromCPUM() and SELMR3SyncTSS() does the bulk synchronization
31	* work. The three structures (GDT, LDT, TSS) are all shadowed wholesale atm.
32	* The idea is to do it in a more on-demand fashion when we get time. There
33	* also a whole bunch of issues with the current synchronization of all three
34	* tables, see notes and todos in the code.
35	*
36	* When the guest makes changes to the GDT we will try update the shadow copy
37	* without involving SELMR3UpdateFromCPUM(), see selmGCSyncGDTEntry().
38	*
39	* When the guest make LDT changes we'll trigger a full resync of the LDT
40	* (SELMR3UpdateFromCPUM()), which, needless to say, isn't optimal.
41	*
42	* The TSS shadowing is limited to the fields we need to care about, namely SS0
43	* and ESP0. The Patch Manager makes use of these. We monitor updates to the
44	* guest TSS and will try keep our SS0 and ESP0 copies up to date this way
45	* rather than go the SELMR3SyncTSS() route.
46	*
47	* When in raw-mode SELM also injects a few extra GDT selectors which are used
48	* by the raw-mode (hyper) context. These start their life at the high end of
49	* the table and will be relocated when the guest tries to make use of them...
50	* Well, that was that idea at least, only the code isn't quite there yet which
51	* is why we have trouble with guests which actually have a full sized GDT.
52	*
53	* So, the summary of the current GDT, LDT and TSS shadowing is that there is a
54	* lot of relatively simple and enjoyable work to be done, see @bugref{3267}.
55	*
56	*/
57
58	/*******************************************************************************
59	* Header Files *
60	*******************************************************************************/
61	#define LOG_GROUP LOG_GROUP_SELM
62	#include <VBox/vmm/selm.h>
63	#include <VBox/vmm/cpum.h>
64	#include <VBox/vmm/stam.h>
65	#include <VBox/vmm/em.h>
66	#include <VBox/vmm/hm.h>
67	#include <VBox/vmm/mm.h>
68	#include <VBox/vmm/ssm.h>
69	#include <VBox/vmm/pgm.h>
70	#include <VBox/vmm/trpm.h>
71	#include <VBox/vmm/dbgf.h>
72	#include "SELMInternal.h"
73	#include <VBox/vmm/vm.h>
74	#include <VBox/err.h>
75	#include <VBox/param.h>
76
77	#include <iprt/assert.h>
78	#include <VBox/log.h>
79	#include <iprt/asm.h>
80	#include <iprt/string.h>
81	#include <iprt/thread.h>
82	#include <iprt/string.h>
83
84	#include "SELMInline.h"
85
86
87	/** SELM saved state version. */
88	#define SELM_SAVED_STATE_VERSION 5
89
90
91	/*******************************************************************************
92	* Internal Functions *
93	*******************************************************************************/
94	static DECLCALLBACK(int) selmR3Save(PVM pVM, PSSMHANDLE pSSM);
95	static DECLCALLBACK(int) selmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
96	static DECLCALLBACK(int) selmR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
97	static DECLCALLBACK(int) selmR3GuestGDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
98	static DECLCALLBACK(int) selmR3GuestLDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
99	static DECLCALLBACK(int) selmR3GuestTSSWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
100	static DECLCALLBACK(void) selmR3InfoGdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
101	static DECLCALLBACK(void) selmR3InfoGdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
102	static DECLCALLBACK(void) selmR3InfoLdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
103	static DECLCALLBACK(void) selmR3InfoLdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
104	//static DECLCALLBACK(void) selmR3InfoTss(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
105	//static DECLCALLBACK(void) selmR3InfoTssGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
106
107
108	/*******************************************************************************
109	* Global Variables *
110	*******************************************************************************/
111	#ifdef LOG_ENABLED
112	/** Segment register names. */
113	static char const g_aszSRegNms[X86_SREG_COUNT][4] = { "ES", "CS", "SS", "DS", "FS", "GS" };
114	#endif
115
116
117	/**
118	* Initializes the SELM.
119	*
120	* @returns VBox status code.
121	* @param pVM Pointer to the VM.
122	*/
123	VMMR3DECL(int) SELMR3Init(PVM pVM)
124	{
125	int rc;
126	LogFlow(("SELMR3Init\n"));
127
128	/*
129	* Assert alignment and sizes.
130	* (The TSS block requires contiguous back.)
131	*/
132	AssertCompile(sizeof(pVM->selm.s) <= sizeof(pVM->selm.padding)); AssertRelease(sizeof(pVM->selm.s) <= sizeof(pVM->selm.padding));
133	AssertCompileMemberAlignment(VM, selm.s, 32); AssertRelease(!(RT_OFFSETOF(VM, selm.s) & 31));
134	#if 0 /* doesn't work */
135	AssertCompile((RT_OFFSETOF(VM, selm.s.Tss) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.Tss));
136	AssertCompile((RT_OFFSETOF(VM, selm.s.TssTrap08) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.TssTrap08));
137	#endif
138	AssertRelease((RT_OFFSETOF(VM, selm.s.Tss) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.Tss));
139	AssertRelease((RT_OFFSETOF(VM, selm.s.TssTrap08) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.TssTrap08));
140	AssertRelease(sizeof(pVM->selm.s.Tss.IntRedirBitmap) == 0x20);
141
142	/*
143	* Init the structure.
144	*/
145	pVM->selm.s.offVM = RT_OFFSETOF(VM, selm);
146	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] = (SELM_GDT_ELEMENTS - 0x1) << 3;
147	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] = (SELM_GDT_ELEMENTS - 0x2) << 3;
148	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] = (SELM_GDT_ELEMENTS - 0x3) << 3;
149	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] = (SELM_GDT_ELEMENTS - 0x4) << 3;
150	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = (SELM_GDT_ELEMENTS - 0x5) << 3;
151
152	if (HMIsRawModeCtxNeeded(pVM))
153	{
154	/*
155	* Allocate GDT table.
156	*/
157	rc = MMR3HyperAllocOnceNoRel(pVM, sizeof(pVM->selm.s.paGdtR3[0]) * SELM_GDT_ELEMENTS,
158	PAGE_SIZE, MM_TAG_SELM, (void **)&pVM->selm.s.paGdtR3);
159	AssertRCReturn(rc, rc);
160
161	/*
162	* Allocate LDT area.
163	*/
164	rc = MMR3HyperAllocOnceNoRel(pVM, _64K + PAGE_SIZE, PAGE_SIZE, MM_TAG_SELM, &pVM->selm.s.pvLdtR3);
165	AssertRCReturn(rc, rc);
166	}
167
168	/*
169	* Init Guest's and Shadow GDT, LDT, TSS changes control variables.
170	*/
171	pVM->selm.s.cbEffGuestGdtLimit = 0;
172	pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
173	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
174	pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
175
176	pVM->selm.s.paGdtRC = NIL_RTRCPTR; /* Must be set in SELMR3Relocate because of monitoring. */
177	pVM->selm.s.pvLdtRC = RTRCPTR_MAX;
178	pVM->selm.s.pvMonShwTssRC = RTRCPTR_MAX;
179	pVM->selm.s.GCSelTss = RTSEL_MAX;
180
181	pVM->selm.s.fSyncTSSRing0Stack = false;
182
183	/* The I/O bitmap starts right after the virtual interrupt redirection
184	bitmap. Outside the TSS on purpose; the CPU will not check it for
185	I/O operations. */
186	pVM->selm.s.Tss.offIoBitmap = sizeof(VBOXTSS);
187	/* bit set to 1 means no redirection */
188	memset(pVM->selm.s.Tss.IntRedirBitmap, 0xff, sizeof(pVM->selm.s.Tss.IntRedirBitmap));
189
190	/*
191	* Register the saved state data unit.
192	*/
193	rc = SSMR3RegisterInternal(pVM, "selm", 1, SELM_SAVED_STATE_VERSION, sizeof(SELM),
194	NULL, NULL, NULL,
195	NULL, selmR3Save, NULL,
196	NULL, selmR3Load, selmR3LoadDone);
197	if (RT_FAILURE(rc))
198	return rc;
199
200	/*
201	* Statistics.
202	*/
203	if (!HMIsEnabled(pVM))
204	{
205	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestGDTHandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/GDTInt", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest GDT.");
206	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestGDTUnhandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/GDTEmu", STAMUNIT_OCCURENCES, "The number of unhandled writes to the Guest GDT.");
207	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestLDT, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/LDT", STAMUNIT_OCCURENCES, "The number of writes to the Guest LDT was detected.");
208	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSHandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSInt", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest TSS.");
209	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSRedir, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSRedir",STAMUNIT_OCCURENCES, "The number of handled redir bitmap writes to the Guest TSS.");
210	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSHandledChanged,STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSIntChg", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest TSS where the R0 stack changed.");
211	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSUnhandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSEmu", STAMUNIT_OCCURENCES, "The number of unhandled writes to the Guest TSS.");
212	STAM_REG(pVM, &pVM->selm.s.StatTSSSync, STAMTYPE_PROFILE, "/PROF/SELM/TSSSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the SELMR3SyncTSS() body.");
213	STAM_REG(pVM, &pVM->selm.s.StatUpdateFromCPUM, STAMTYPE_PROFILE, "/PROF/SELM/UpdateFromCPUM", STAMUNIT_TICKS_PER_CALL, "Profiling of the SELMR3UpdateFromCPUM() body.");
214
215	STAM_REL_REG(pVM, &pVM->selm.s.StatHyperSelsChanged, STAMTYPE_COUNTER, "/SELM/HyperSels/Changed", STAMUNIT_OCCURENCES, "The number of times we had to relocate our hypervisor selectors.");
216	STAM_REL_REG(pVM, &pVM->selm.s.StatScanForHyperSels, STAMTYPE_COUNTER, "/SELM/HyperSels/Scan", STAMUNIT_OCCURENCES, "The number of times we had find free hypervisor selectors.");
217
218	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_ES], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleES", STAMUNIT_OCCURENCES, "Stale ES was detected in UpdateFromCPUM.");
219	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_CS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleCS", STAMUNIT_OCCURENCES, "Stale CS was detected in UpdateFromCPUM.");
220	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_SS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleSS", STAMUNIT_OCCURENCES, "Stale SS was detected in UpdateFromCPUM.");
221	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_DS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleDS", STAMUNIT_OCCURENCES, "Stale DS was detected in UpdateFromCPUM.");
222	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_FS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleFS", STAMUNIT_OCCURENCES, "Stale FS was detected in UpdateFromCPUM.");
223	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_GS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleGS", STAMUNIT_OCCURENCES, "Stale GS was detected in UpdateFromCPUM.");
224
225	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_ES], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleES", STAMUNIT_OCCURENCES, "Already stale ES in UpdateFromCPUM.");
226	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_CS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleCS", STAMUNIT_OCCURENCES, "Already stale CS in UpdateFromCPUM.");
227	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_SS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleSS", STAMUNIT_OCCURENCES, "Already stale SS in UpdateFromCPUM.");
228	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_DS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleDS", STAMUNIT_OCCURENCES, "Already stale DS in UpdateFromCPUM.");
229	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_FS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleFS", STAMUNIT_OCCURENCES, "Already stale FS in UpdateFromCPUM.");
230	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_GS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleGS", STAMUNIT_OCCURENCES, "Already stale GS in UpdateFromCPUM.");
231
232	STAM_REL_REG(pVM, &pVM->selm.s.StatStaleToUnstaleSReg, STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/StaleToUnstale", STAMUNIT_OCCURENCES, "Transitions from stale to unstale UpdateFromCPUM.");
233
234	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_ES], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedES", STAMUNIT_OCCURENCES, "Updated hidden ES values in UpdateFromCPUM.");
235	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_CS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedCS", STAMUNIT_OCCURENCES, "Updated hidden CS values in UpdateFromCPUM.");
236	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_SS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedSS", STAMUNIT_OCCURENCES, "Updated hidden SS values in UpdateFromCPUM.");
237	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_DS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedDS", STAMUNIT_OCCURENCES, "Updated hidden DS values in UpdateFromCPUM.");
238	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_FS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedFS", STAMUNIT_OCCURENCES, "Updated hidden FS values in UpdateFromCPUM.");
239	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_GS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedGS", STAMUNIT_OCCURENCES, "Updated hidden GS values in UpdateFromCPUM.");
240	}
241
242	STAM_REG( pVM, &pVM->selm.s.StatLoadHidSelGst, STAMTYPE_COUNTER, "/SELM/LoadHidSel/LoadedGuest", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: Loaded from guest tables.");
243	STAM_REG( pVM, &pVM->selm.s.StatLoadHidSelShw, STAMTYPE_COUNTER, "/SELM/LoadHidSel/LoadedShadow", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: Loaded from shadow tables.");
244	STAM_REL_REG(pVM, &pVM->selm.s.StatLoadHidSelReadErrors, STAMTYPE_COUNTER, "/SELM/LoadHidSel/GstReadErrors", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: Guest table read errors.");
245	STAM_REL_REG(pVM, &pVM->selm.s.StatLoadHidSelGstNoGood, STAMTYPE_COUNTER, "/SELM/LoadHidSel/NoGoodGuest", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: No good guest table entry.");
246
247	#ifdef VBOX_WITH_RAW_MODE
248	/*
249	* Default action when entering raw mode for the first time
250	*/
251	if (!HMIsEnabled(pVM))
252	{
253	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
254	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
255	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
256	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
257	}
258	#endif
259
260	/*
261	* Register info handlers.
262	*/
263	if (HMIsRawModeCtxNeeded(pVM))
264	{
265	DBGFR3InfoRegisterInternal(pVM, "gdt", "Displays the shadow GDT. No arguments.", &selmR3InfoGdt);
266	DBGFR3InfoRegisterInternal(pVM, "ldt", "Displays the shadow LDT. No arguments.", &selmR3InfoLdt);
267	//DBGFR3InfoRegisterInternal(pVM, "tss", "Displays the shadow TSS. No arguments.", &selmR3InfoTss);
268	}
269	DBGFR3InfoRegisterInternal(pVM, "gdtguest", "Displays the guest GDT. No arguments.", &selmR3InfoGdtGuest);
270	DBGFR3InfoRegisterInternal(pVM, "ldtguest", "Displays the guest LDT. No arguments.", &selmR3InfoLdtGuest);
271	//DBGFR3InfoRegisterInternal(pVM, "tssguest", "Displays the guest TSS. No arguments.", &selmR3InfoTssGuest);
272
273	return rc;
274	}
275
276
277	/**
278	* Finalizes HMA page attributes.
279	*
280	* @returns VBox status code.
281	* @param pVM Pointer to the VM.
282	*/
283	VMMR3DECL(int) SELMR3InitFinalize(PVM pVM)
284	{
285	#ifdef VBOX_WITH_RAW_MODE
286	/** @cfgm{/DoubleFault,bool,false}
287	* Enables catching of double faults in the raw-mode context VMM code. This can
288	* be used when the triple faults or hangs occur and one suspect an unhandled
289	* double fault. This is not enabled by default because it means making the
290	* hyper selectors writeable for all supervisor code, including the guest's.
291	* The double fault is a task switch and thus requires write access to the GDT
292	* of the TSS (to set it busy), to the old TSS (to store state), and to the Trap
293	* 8 TSS for the back link.
294	*/
295	bool f;
296	# if defined(DEBUG_bird)
297	int rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "DoubleFault", &f, true);
298	# else
299	int rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "DoubleFault", &f, false);
300	# endif
301	AssertLogRelRCReturn(rc, rc);
302	if (f && HMIsRawModeCtxNeeded(pVM))
303	{
304	PX86DESC paGdt = pVM->selm.s.paGdtR3;
305	rc = PGMMapSetPage(pVM, MMHyperR3ToRC(pVM, &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> 3]), sizeof(paGdt[0]),
306	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
307	AssertRC(rc);
308	rc = PGMMapSetPage(pVM, MMHyperR3ToRC(pVM, &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3]), sizeof(paGdt[0]),
309	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
310	AssertRC(rc);
311	rc = PGMMapSetPage(pVM, VM_RC_ADDR(pVM, &pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]), sizeof(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]),
312	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
313	AssertRC(rc);
314	rc = PGMMapSetPage(pVM, VM_RC_ADDR(pVM, &pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]), sizeof(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]),
315	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
316	AssertRC(rc);
317	}
318	#endif /* VBOX_WITH_RAW_MODE */
319	return VINF_SUCCESS;
320	}
321
322
323	/**
324	* Setup the hypervisor GDT selectors in our shadow table
325	*
326	* @param pVM Pointer to the VM.
327	*/
328	static void selmR3SetupHyperGDTSelectors(PVM pVM)
329	{
330	PX86DESC paGdt = pVM->selm.s.paGdtR3;
331
332	/*
333	* Set up global code and data descriptors for use in the guest context.
334	* Both are wide open (base 0, limit 4GB)
335	*/
336	PX86DESC pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] >> 3];
337	pDesc->Gen.u16LimitLow = 0xffff;
338	pDesc->Gen.u4LimitHigh = 0xf;
339	pDesc->Gen.u16BaseLow = 0;
340	pDesc->Gen.u8BaseHigh1 = 0;
341	pDesc->Gen.u8BaseHigh2 = 0;
342	pDesc->Gen.u4Type = X86_SEL_TYPE_ER_ACC;
343	pDesc->Gen.u1DescType = 1; /* not system, but code/data */
344	pDesc->Gen.u2Dpl = 0; /* supervisor */
345	pDesc->Gen.u1Present = 1;
346	pDesc->Gen.u1Available = 0;
347	pDesc->Gen.u1Long = 0;
348	pDesc->Gen.u1DefBig = 1; /* def 32 bit */
349	pDesc->Gen.u1Granularity = 1; /* 4KB limit */
350
351	/* data */
352	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] >> 3];
353	pDesc->Gen.u16LimitLow = 0xffff;
354	pDesc->Gen.u4LimitHigh = 0xf;
355	pDesc->Gen.u16BaseLow = 0;
356	pDesc->Gen.u8BaseHigh1 = 0;
357	pDesc->Gen.u8BaseHigh2 = 0;
358	pDesc->Gen.u4Type = X86_SEL_TYPE_RW_ACC;
359	pDesc->Gen.u1DescType = 1; /* not system, but code/data */
360	pDesc->Gen.u2Dpl = 0; /* supervisor */
361	pDesc->Gen.u1Present = 1;
362	pDesc->Gen.u1Available = 0;
363	pDesc->Gen.u1Long = 0;
364	pDesc->Gen.u1DefBig = 1; /* big */
365	pDesc->Gen.u1Granularity = 1; /* 4KB limit */
366
367	/* 64-bit mode code (& data?) */
368	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] >> 3];
369	pDesc->Gen.u16LimitLow = 0xffff;
370	pDesc->Gen.u4LimitHigh = 0xf;
371	pDesc->Gen.u16BaseLow = 0;
372	pDesc->Gen.u8BaseHigh1 = 0;
373	pDesc->Gen.u8BaseHigh2 = 0;
374	pDesc->Gen.u4Type = X86_SEL_TYPE_ER_ACC;
375	pDesc->Gen.u1DescType = 1; /* not system, but code/data */
376	pDesc->Gen.u2Dpl = 0; /* supervisor */
377	pDesc->Gen.u1Present = 1;
378	pDesc->Gen.u1Available = 0;
379	pDesc->Gen.u1Long = 1; /* The Long (L) attribute bit. */
380	pDesc->Gen.u1DefBig = 0; /* With L=1 this must be 0. */
381	pDesc->Gen.u1Granularity = 1; /* 4KB limit */
382
383	/*
384	* TSS descriptor
385	*/
386	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3];
387	RTRCPTR RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
388	pDesc->Gen.u16BaseLow = RT_LOWORD(RCPtrTSS);
389	pDesc->Gen.u8BaseHigh1 = RT_BYTE3(RCPtrTSS);
390	pDesc->Gen.u8BaseHigh2 = RT_BYTE4(RCPtrTSS);
391	pDesc->Gen.u16LimitLow = sizeof(VBOXTSS) - 1;
392	pDesc->Gen.u4LimitHigh = 0;
393	pDesc->Gen.u4Type = X86_SEL_TYPE_SYS_386_TSS_AVAIL;
394	pDesc->Gen.u1DescType = 0; /* system */
395	pDesc->Gen.u2Dpl = 0; /* supervisor */
396	pDesc->Gen.u1Present = 1;
397	pDesc->Gen.u1Available = 0;
398	pDesc->Gen.u1Long = 0;
399	pDesc->Gen.u1DefBig = 0;
400	pDesc->Gen.u1Granularity = 0; /* byte limit */
401
402	/*
403	* TSS descriptor for trap 08
404	*/
405	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> 3];
406	pDesc->Gen.u16LimitLow = sizeof(VBOXTSS) - 1;
407	pDesc->Gen.u4LimitHigh = 0;
408	RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.TssTrap08);
409	pDesc->Gen.u16BaseLow = RT_LOWORD(RCPtrTSS);
410	pDesc->Gen.u8BaseHigh1 = RT_BYTE3(RCPtrTSS);
411	pDesc->Gen.u8BaseHigh2 = RT_BYTE4(RCPtrTSS);
412	pDesc->Gen.u4Type = X86_SEL_TYPE_SYS_386_TSS_AVAIL;
413	pDesc->Gen.u1DescType = 0; /* system */
414	pDesc->Gen.u2Dpl = 0; /* supervisor */
415	pDesc->Gen.u1Present = 1;
416	pDesc->Gen.u1Available = 0;
417	pDesc->Gen.u1Long = 0;
418	pDesc->Gen.u1DefBig = 0;
419	pDesc->Gen.u1Granularity = 0; /* byte limit */
420	}
421
422	/**
423	* Applies relocations to data and code managed by this
424	* component. This function will be called at init and
425	* whenever the VMM need to relocate it self inside the GC.
426	*
427	* @param pVM The VM.
428	*/
429	VMMR3DECL(void) SELMR3Relocate(PVM pVM)
430	{
431	PX86DESC paGdt = pVM->selm.s.paGdtR3;
432	LogFlow(("SELMR3Relocate\n"));
433
434	if (HMIsRawModeCtxNeeded(pVM))
435	{
436	for (VMCPUID i = 0; i < pVM->cCpus; i++)
437	{
438	PVMCPU pVCpu = &pVM->aCpus[i];
439
440	/*
441	* Update GDTR and selector.
442	*/
443	CPUMSetHyperGDTR(pVCpu, MMHyperR3ToRC(pVM, paGdt), SELM_GDT_ELEMENTS * sizeof(paGdt[0]) - 1);
444
445	/** @todo selector relocations should be a separate operation? */
446	CPUMSetHyperCS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS]);
447	CPUMSetHyperDS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
448	CPUMSetHyperES(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
449	CPUMSetHyperSS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
450	CPUMSetHyperTR(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]);
451	}
452
453	selmR3SetupHyperGDTSelectors(pVM);
454
455	/** @todo SELM must be called when any of the CR3s changes during a cpu mode change. */
456	/** @todo PGM knows the proper CR3 values these days, not CPUM. */
457	/*
458	* Update the TSSes.
459	*/
460	/* Only applies to raw mode which supports only 1 VCPU */
461	PVMCPU pVCpu = &pVM->aCpus[0];
462
463	/* Current TSS */
464	pVM->selm.s.Tss.cr3 = PGMGetHyperCR3(pVCpu);
465	pVM->selm.s.Tss.ss0 = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
466	pVM->selm.s.Tss.esp0 = VMMGetStackRC(pVCpu);
467	pVM->selm.s.Tss.cs = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS];
468	pVM->selm.s.Tss.ds = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
469	pVM->selm.s.Tss.es = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
470	pVM->selm.s.Tss.offIoBitmap = sizeof(VBOXTSS);
471
472	/* trap 08 */
473	pVM->selm.s.TssTrap08.cr3 = PGMGetInterRCCR3(pVM, pVCpu); /* this should give use better survival chances. */
474	pVM->selm.s.TssTrap08.ss0 = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
475	pVM->selm.s.TssTrap08.ss = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
476	pVM->selm.s.TssTrap08.esp0 = VMMGetStackRC(pVCpu) - PAGE_SIZE / 2; /* upper half can be analysed this way. */
477	pVM->selm.s.TssTrap08.esp = pVM->selm.s.TssTrap08.esp0;
478	pVM->selm.s.TssTrap08.ebp = pVM->selm.s.TssTrap08.esp0;
479	pVM->selm.s.TssTrap08.cs = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS];
480	pVM->selm.s.TssTrap08.ds = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
481	pVM->selm.s.TssTrap08.es = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
482	pVM->selm.s.TssTrap08.fs = 0;
483	pVM->selm.s.TssTrap08.gs = 0;
484	pVM->selm.s.TssTrap08.selLdt = 0;
485	pVM->selm.s.TssTrap08.eflags = 0x2; /* all cleared */
486	pVM->selm.s.TssTrap08.ecx = VM_RC_ADDR(pVM, &pVM->selm.s.Tss); /* setup ecx to normal Hypervisor TSS address. */
487	pVM->selm.s.TssTrap08.edi = pVM->selm.s.TssTrap08.ecx;
488	pVM->selm.s.TssTrap08.eax = pVM->selm.s.TssTrap08.ecx;
489	pVM->selm.s.TssTrap08.edx = VM_RC_ADDR(pVM, pVM); /* setup edx VM address. */
490	pVM->selm.s.TssTrap08.edi = pVM->selm.s.TssTrap08.edx;
491	pVM->selm.s.TssTrap08.ebx = pVM->selm.s.TssTrap08.edx;
492	pVM->selm.s.TssTrap08.offIoBitmap = sizeof(VBOXTSS);
493	/* TRPM will be updating the eip */
494	}
495
496	if (!HMIsEnabled(pVM))
497	{
498	/*
499	* Update shadow GDT/LDT/TSS write access handlers.
500	*/
501	int rc; NOREF(rc);
502	#ifdef SELM_TRACK_SHADOW_GDT_CHANGES
503	if (pVM->selm.s.paGdtRC != NIL_RTRCPTR)
504	{
505	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.paGdtRC);
506	AssertRC(rc);
507	}
508	pVM->selm.s.paGdtRC = MMHyperR3ToRC(pVM, paGdt);
509	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.paGdtRC,
510	pVM->selm.s.paGdtRC + SELM_GDT_ELEMENTS * sizeof(paGdt[0]) - 1,
511	0, 0, "selmRCShadowGDTWriteHandler", 0, "Shadow GDT write access handler");
512	AssertRC(rc);
513	#endif
514	#ifdef SELM_TRACK_SHADOW_TSS_CHANGES
515	if (pVM->selm.s.pvMonShwTssRC != RTRCPTR_MAX)
516	{
517	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvMonShwTssRC);
518	AssertRC(rc);
519	}
520	pVM->selm.s.pvMonShwTssRC = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
521	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.pvMonShwTssRC,
522	pVM->selm.s.pvMonShwTssRC + sizeof(pVM->selm.s.Tss) - 1,
523	0, 0, "selmRCShadowTSSWriteHandler", 0, "Shadow TSS write access handler");
524	AssertRC(rc);
525	#endif
526
527	/*
528	* Update the GC LDT region handler and address.
529	*/
530	#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
531	if (pVM->selm.s.pvLdtRC != RTRCPTR_MAX)
532	{
533	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvLdtRC);
534	AssertRC(rc);
535	}
536	#endif
537	pVM->selm.s.pvLdtRC = MMHyperR3ToRC(pVM, pVM->selm.s.pvLdtR3);
538	#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
539	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.pvLdtRC,
540	pVM->selm.s.pvLdtRC + _64K + PAGE_SIZE - 1,
541	0, 0, "selmRCShadowLDTWriteHandler", 0, "Shadow LDT write access handler");
542	AssertRC(rc);
543	#endif
544	}
545	}
546
547
548	/**
549	* Terminates the SELM.
550	*
551	* Termination means cleaning up and freeing all resources,
552	* the VM it self is at this point powered off or suspended.
553	*
554	* @returns VBox status code.
555	* @param pVM Pointer to the VM.
556	*/
557	VMMR3DECL(int) SELMR3Term(PVM pVM)
558	{
559	NOREF(pVM);
560	return VINF_SUCCESS;
561	}
562
563
564	/**
565	* The VM is being reset.
566	*
567	* For the SELM component this means that any GDT/LDT/TSS monitors
568	* needs to be removed.
569	*
570	* @param pVM Pointer to the VM.
571	*/
572	VMMR3DECL(void) SELMR3Reset(PVM pVM)
573	{
574	LogFlow(("SELMR3Reset:\n"));
575	VM_ASSERT_EMT(pVM);
576
577	/*
578	* Uninstall guest GDT/LDT/TSS write access handlers.
579	*/
580	int rc = VINF_SUCCESS;
581	if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
582	{
583	#ifdef SELM_TRACK_GUEST_GDT_CHANGES
584	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt);
585	AssertRC(rc);
586	#endif
587	pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
588	pVM->selm.s.GuestGdtr.cbGdt = 0;
589	}
590	pVM->selm.s.fGDTRangeRegistered = false;
591	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
592	{
593	#ifdef SELM_TRACK_GUEST_LDT_CHANGES
594	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
595	AssertRC(rc);
596	#endif
597	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
598	}
599	if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
600	{
601	#ifdef SELM_TRACK_GUEST_TSS_CHANGES
602	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestTss);
603	AssertRC(rc);
604	#endif
605	pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
606	pVM->selm.s.GCSelTss = RTSEL_MAX;
607	}
608
609	/*
610	* Re-initialize other members.
611	*/
612	pVM->selm.s.cbLdtLimit = 0;
613	pVM->selm.s.offLdtHyper = 0;
614	pVM->selm.s.cbMonitoredGuestTss = 0;
615
616	pVM->selm.s.fSyncTSSRing0Stack = false;
617
618	#ifdef VBOX_WITH_RAW_MODE
619	if (!HMIsEnabled(pVM))
620	{
621	/*
622	* Default action when entering raw mode for the first time
623	*/
624	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
625	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
626	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
627	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
628	}
629	#endif
630	}
631
632
633	/**
634	* Execute state save operation.
635	*
636	* @returns VBox status code.
637	* @param pVM Pointer to the VM.
638	* @param pSSM SSM operation handle.
639	*/
640	static DECLCALLBACK(int) selmR3Save(PVM pVM, PSSMHANDLE pSSM)
641	{
642	LogFlow(("selmR3Save:\n"));
643
644	/*
645	* Save the basic bits - fortunately all the other things can be resynced on load.
646	*/
647	PSELM pSelm = &pVM->selm.s;
648
649	SSMR3PutBool(pSSM, HMIsEnabled(pVM));
650	SSMR3PutBool(pSSM, pSelm->fSyncTSSRing0Stack);
651	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS]);
652	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_DS]);
653	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS64]);
654	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS64]); /* reserved for DS64. */
655	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_TSS]);
656	return SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]);
657	}
658
659
660	/**
661	* Execute state load operation.
662	*
663	* @returns VBox status code.
664	* @param pVM Pointer to the VM.
665	* @param pSSM SSM operation handle.
666	* @param uVersion Data layout version.
667	* @param uPass The data pass.
668	*/
669	static DECLCALLBACK(int) selmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
670	{
671	LogFlow(("selmR3Load:\n"));
672	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
673
674	/*
675	* Validate version.
676	*/
677	if (uVersion != SELM_SAVED_STATE_VERSION)
678	{
679	AssertMsgFailed(("selmR3Load: Invalid version uVersion=%d!\n", uVersion));
680	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
681	}
682
683	/*
684	* Do a reset.
685	*/
686	SELMR3Reset(pVM);
687
688	/* Get the monitoring flag. */
689	bool fIgnored;
690	SSMR3GetBool(pSSM, &fIgnored);
691
692	/* Get the TSS state flag. */
693	SSMR3GetBool(pSSM, &pVM->selm.s.fSyncTSSRing0Stack);
694
695	/*
696	* Get the selectors.
697	*/
698	RTSEL SelCS;
699	SSMR3GetSel(pSSM, &SelCS);
700	RTSEL SelDS;
701	SSMR3GetSel(pSSM, &SelDS);
702	RTSEL SelCS64;
703	SSMR3GetSel(pSSM, &SelCS64);
704	RTSEL SelDS64;
705	SSMR3GetSel(pSSM, &SelDS64);
706	RTSEL SelTSS;
707	SSMR3GetSel(pSSM, &SelTSS);
708	RTSEL SelTSSTrap08;
709	SSMR3GetSel(pSSM, &SelTSSTrap08);
710
711	/* Copy the selectors; they will be checked during relocation. */
712	PSELM pSelm = &pVM->selm.s;
713	pSelm->aHyperSel[SELM_HYPER_SEL_CS] = SelCS;
714	pSelm->aHyperSel[SELM_HYPER_SEL_DS] = SelDS;
715	pSelm->aHyperSel[SELM_HYPER_SEL_CS64] = SelCS64;
716	pSelm->aHyperSel[SELM_HYPER_SEL_TSS] = SelTSS;
717	pSelm->aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = SelTSSTrap08;
718
719	return VINF_SUCCESS;
720	}
721
722
723	/**
724	* Sync the GDT, LDT and TSS after loading the state.
725	*
726	* Just to play save, we set the FFs to force syncing before
727	* executing GC code.
728	*
729	* @returns VBox status code.
730	* @param pVM Pointer to the VM.
731	* @param pSSM SSM operation handle.
732	*/
733	static DECLCALLBACK(int) selmR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
734	{
735	#ifdef VBOX_WITH_RAW_MODE
736	if (!HMIsEnabled(pVM))
737	{
738	PVMCPU pVCpu = VMMGetCpu(pVM);
739
740	LogFlow(("selmR3LoadDone:\n"));
741
742	/*
743	* Don't do anything if it's a load failure.
744	*/
745	int rc = SSMR3HandleGetStatus(pSSM);
746	if (RT_FAILURE(rc))
747	return VINF_SUCCESS;
748
749	/*
750	* Do the syncing if we're in protected mode and using raw-mode.
751	*/
752	if (PGMGetGuestMode(pVCpu) != PGMMODE_REAL)
753	{
754	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
755	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
756	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
757	SELMR3UpdateFromCPUM(pVM, pVCpu);
758	}
759
760	/*
761	* Flag everything for resync on next raw mode entry.
762	*/
763	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
764	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
765	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
766	}
767	#endif /VBOX_WITH_RAW_MODE/
768	return VINF_SUCCESS;
769	}
770
771	#ifdef VBOX_WITH_RAW_MODE
772
773	/**
774	* Updates (syncs) the shadow GDT.
775	*
776	* @returns VBox status code.
777	* @param pVM The VM handle.
778	* @param pVCpu The current virtual CPU.
779	*/
780	static int selmR3UpdateShadowGdt(PVM pVM, PVMCPU pVCpu)
781	{
782	Assert(!HMIsEnabled(pVM));
783
784	/*
785	* Always assume the best...
786	*/
787	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
788
789	/* If the GDT was changed, then make sure the LDT is checked too */
790	/** @todo only do this if the actual ldtr selector was changed; this is a bit excessive */
791	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
792	/* Same goes for the TSS selector */
793	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
794
795	/*
796	* Get the GDTR and check if there is anything to do (there usually is).
797	*/
798	VBOXGDTR GDTR;
799	CPUMGetGuestGDTR(pVCpu, &GDTR);
800	if (GDTR.cbGdt < sizeof(X86DESC))
801	{
802	Log(("No GDT entries...\n"));
803	return VINF_SUCCESS;
804	}
805
806	/*
807	* Read the Guest GDT.
808	* ASSUMES that the entire GDT is in memory.
809	*/
810	RTUINT cbEffLimit = GDTR.cbGdt;
811	PX86DESC pGDTE = &pVM->selm.s.paGdtR3[1];
812	int rc = PGMPhysSimpleReadGCPtr(pVCpu, pGDTE, GDTR.pGdt + sizeof(X86DESC), cbEffLimit + 1 - sizeof(X86DESC));
813	if (RT_FAILURE(rc))
814	{
815	/*
816	* Read it page by page.
817	*
818	* Keep track of the last valid page and delay memsets and
819	* adjust cbEffLimit to reflect the effective size. The latter
820	* is something we do in the belief that the guest will probably
821	* never actually commit the last page, thus allowing us to keep
822	* our selectors in the high end of the GDT.
823	*/
824	RTUINT cbLeft = cbEffLimit + 1 - sizeof(X86DESC);
825	RTGCPTR GCPtrSrc = (RTGCPTR)GDTR.pGdt + sizeof(X86DESC);
826	uint8_t pu8Dst = (uint8_t )&pVM->selm.s.paGdtR3[1];
827	uint8_t *pu8DstInvalid = pu8Dst;
828
829	while (cbLeft)
830	{
831	RTUINT cb = PAGE_SIZE - (GCPtrSrc & PAGE_OFFSET_MASK);
832	cb = RT_MIN(cb, cbLeft);
833	rc = PGMPhysSimpleReadGCPtr(pVCpu, pu8Dst, GCPtrSrc, cb);
834	if (RT_SUCCESS(rc))
835	{
836	if (pu8DstInvalid != pu8Dst)
837	RT_BZERO(pu8DstInvalid, pu8Dst - pu8DstInvalid);
838	GCPtrSrc += cb;
839	pu8Dst += cb;
840	pu8DstInvalid = pu8Dst;
841	}
842	else if ( rc == VERR_PAGE_NOT_PRESENT
843	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT)
844	{
845	GCPtrSrc += cb;
846	pu8Dst += cb;
847	}
848	else
849	{
850	AssertLogRelMsgFailed(("Couldn't read GDT at %016RX64, rc=%Rrc!\n", GDTR.pGdt, rc));
851	return VERR_SELM_GDT_READ_ERROR;
852	}
853	cbLeft -= cb;
854	}
855
856	/* any invalid pages at the end? */
857	if (pu8DstInvalid != pu8Dst)
858	{
859	cbEffLimit = pu8DstInvalid - (uint8_t *)pVM->selm.s.paGdtR3 - 1;
860	/* If any GDTEs was invalidated, zero them. */
861	if (cbEffLimit < pVM->selm.s.cbEffGuestGdtLimit)
862	RT_BZERO(pu8DstInvalid + cbEffLimit + 1, pVM->selm.s.cbEffGuestGdtLimit - cbEffLimit);
863	}
864
865	/* keep track of the effective limit. */
866	if (cbEffLimit != pVM->selm.s.cbEffGuestGdtLimit)
867	{
868	Log(("SELMR3UpdateFromCPUM: cbEffGuestGdtLimit=%#x -> %#x (actual %#x)\n",
869	pVM->selm.s.cbEffGuestGdtLimit, cbEffLimit, GDTR.cbGdt));
870	pVM->selm.s.cbEffGuestGdtLimit = cbEffLimit;
871	}
872	}
873
874	/*
875	* Check if the Guest GDT intrudes on our GDT entries.
876	*/
877	/** @todo we should try to minimize relocations by making sure our current selectors can be reused. */
878	RTSEL aHyperSel[SELM_HYPER_SEL_MAX];
879	if (cbEffLimit >= SELM_HYPER_DEFAULT_BASE)
880	{
881	PX86DESC pGDTEStart = pVM->selm.s.paGdtR3;
882	PX86DESC pGDTECur = (PX86DESC)((char *)pGDTEStart + GDTR.cbGdt + 1 - sizeof(X86DESC));
883	int iGDT = 0;
884
885	Log(("Internal SELM GDT conflict: use non-present entries\n"));
886	STAM_REL_COUNTER_INC(&pVM->selm.s.StatScanForHyperSels);
887	while (pGDTECur > pGDTEStart)
888	{
889	/* We can reuse non-present entries */
890	if (!pGDTECur->Gen.u1Present)
891	{
892	aHyperSel[iGDT] = ((uintptr_t)pGDTECur - (uintptr_t)pVM->selm.s.paGdtR3) / sizeof(X86DESC);
893	aHyperSel[iGDT] = aHyperSel[iGDT] << X86_SEL_SHIFT;
894	Log(("SELM: Found unused GDT %04X\n", aHyperSel[iGDT]));
895	iGDT++;
896	if (iGDT >= SELM_HYPER_SEL_MAX)
897	break;
898	}
899
900	pGDTECur--;
901	}
902	if (iGDT != SELM_HYPER_SEL_MAX)
903	{
904	AssertLogRelMsgFailed(("Internal SELM GDT conflict.\n"));
905	return VERR_SELM_GDT_TOO_FULL;
906	}
907	}
908	else
909	{
910	aHyperSel[SELM_HYPER_SEL_CS] = SELM_HYPER_DEFAULT_SEL_CS;
911	aHyperSel[SELM_HYPER_SEL_DS] = SELM_HYPER_DEFAULT_SEL_DS;
912	aHyperSel[SELM_HYPER_SEL_CS64] = SELM_HYPER_DEFAULT_SEL_CS64;
913	aHyperSel[SELM_HYPER_SEL_TSS] = SELM_HYPER_DEFAULT_SEL_TSS;
914	aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = SELM_HYPER_DEFAULT_SEL_TSS_TRAP08;
915	}
916
917	#ifdef VBOX_WITH_SAFE_STR
918	/* Use the guest's TR selector to plug the str virtualization hole. */
919	if (CPUMGetGuestTR(pVCpu, NULL) != 0)
920	{
921	Log(("SELM: Use guest TSS selector %x\n", CPUMGetGuestTR(pVCpu, NULL)));
922	aHyperSel[SELM_HYPER_SEL_TSS] = CPUMGetGuestTR(pVCpu, NULL);
923	}
924	#endif
925
926	/*
927	* Work thru the copied GDT entries adjusting them for correct virtualization.
928	*/
929	PX86DESC pGDTEEnd = (PX86DESC)((char *)pGDTE + cbEffLimit + 1 - sizeof(X86DESC));
930	while (pGDTE < pGDTEEnd)
931	{
932	if (pGDTE->Gen.u1Present)
933	selmGuestToShadowDesc(pVM, pGDTE);
934
935	/* Next GDT entry. */
936	pGDTE++;
937	}
938
939	/*
940	* Check if our hypervisor selectors were changed.
941	*/
942	if ( aHyperSel[SELM_HYPER_SEL_CS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS]
943	\|\| aHyperSel[SELM_HYPER_SEL_DS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]
944	\|\| aHyperSel[SELM_HYPER_SEL_CS64] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64]
945	\|\| aHyperSel[SELM_HYPER_SEL_TSS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]
946	\|\| aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08])
947	{
948	/* Reinitialize our hypervisor GDTs */
949	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] = aHyperSel[SELM_HYPER_SEL_CS];
950	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] = aHyperSel[SELM_HYPER_SEL_DS];
951	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] = aHyperSel[SELM_HYPER_SEL_CS64];
952	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] = aHyperSel[SELM_HYPER_SEL_TSS];
953	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = aHyperSel[SELM_HYPER_SEL_TSS_TRAP08];
954
955	STAM_REL_COUNTER_INC(&pVM->selm.s.StatHyperSelsChanged);
956
957	/*
958	* Do the relocation callbacks to let everyone update their hyper selector dependencies.
959	* (SELMR3Relocate will call selmR3SetupHyperGDTSelectors() for us.)
960	*/
961	VMR3Relocate(pVM, 0);
962	}
963	else
964	#ifdef VBOX_WITH_SAFE_STR
965	if ( cbEffLimit >= SELM_HYPER_DEFAULT_BASE
966	\|\| CPUMGetGuestTR(pVCpu, NULL) != 0) /* Our shadow TR entry was overwritten when we synced the guest's GDT. */
967	#else
968	if (cbEffLimit >= SELM_HYPER_DEFAULT_BASE)
969	#endif
970	/* We overwrote all entries above, so we have to save them again. */
971	selmR3SetupHyperGDTSelectors(pVM);
972
973	/*
974	* Adjust the cached GDT limit.
975	* Any GDT entries which have been removed must be cleared.
976	*/
977	if (pVM->selm.s.GuestGdtr.cbGdt != GDTR.cbGdt)
978	{
979	if (pVM->selm.s.GuestGdtr.cbGdt > GDTR.cbGdt)
980	RT_BZERO(pGDTE, pVM->selm.s.GuestGdtr.cbGdt - GDTR.cbGdt);
981	}
982
983	/*
984	* Check if Guest's GDTR is changed.
985	*/
986	if ( GDTR.pGdt != pVM->selm.s.GuestGdtr.pGdt
987	\|\| GDTR.cbGdt != pVM->selm.s.GuestGdtr.cbGdt)
988	{
989	Log(("SELMR3UpdateFromCPUM: Guest's GDT is changed to pGdt=%016RX64 cbGdt=%08X\n", GDTR.pGdt, GDTR.cbGdt));
990
991	#ifdef SELM_TRACK_GUEST_GDT_CHANGES
992	/*
993	* [Re]Register write virtual handler for guest's GDT.
994	*/
995	if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
996	{
997	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt);
998	AssertRC(rc);
999	}
1000
1001	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE,
1002	GDTR.pGdt, GDTR.pGdt + GDTR.cbGdt /* already inclusive */,
1003	0, selmR3GuestGDTWriteHandler, "selmRCGuestGDTWriteHandler", 0,
1004	"Guest GDT write access handler");
1005	# ifdef VBOX_WITH_RAW_RING1
1006	/** @todo !HACK ALERT!
1007	* Some guest OSes (QNX) share code and the GDT on the same page;
1008	* PGMR3HandlerVirtualRegister doesn't support more than one handler,
1009	* so we kick out the PATM handler as this one is more important.
1010	* Fix this properly in PGMR3HandlerVirtualRegister?
1011	*/
1012	if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1013	{
1014	LogRel(("selmR3UpdateShadowGdt: Virtual handler conflict %RGv -> kick out PATM handler for the higher priority GDT page monitor\n", GDTR.pGdt));
1015	rc = PGMHandlerVirtualDeregister(pVM, GDTR.pGdt & PAGE_BASE_GC_MASK);
1016	AssertRC(rc);
1017
1018	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE,
1019	GDTR.pGdt, GDTR.pGdt + GDTR.cbGdt /* already inclusive */,
1020	0, selmR3GuestGDTWriteHandler, "selmRCGuestGDTWriteHandler", 0,
1021	"Guest GDT write access handler");
1022	}
1023	# endif
1024	if (RT_FAILURE(rc))
1025	return rc;
1026	#endif /* SELM_TRACK_GUEST_GDT_CHANGES */
1027
1028	/* Update saved Guest GDTR. */
1029	pVM->selm.s.GuestGdtr = GDTR;
1030	pVM->selm.s.fGDTRangeRegistered = true;
1031	}
1032
1033	return VINF_SUCCESS;
1034	}
1035
1036
1037	/**
1038	* Updates (syncs) the shadow LDT.
1039	*
1040	* @returns VBox status code.
1041	* @param pVM The VM handle.
1042	* @param pVCpu The current virtual CPU.
1043	*/
1044	static int selmR3UpdateShadowLdt(PVM pVM, PVMCPU pVCpu)
1045	{
1046	int rc = VINF_SUCCESS;
1047	Assert(!HMIsEnabled(pVM));
1048
1049	/*
1050	* Always assume the best...
1051	*/
1052	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
1053
1054	/*
1055	* LDT handling is done similarly to the GDT handling with a shadow
1056	* array. However, since the LDT is expected to be swappable (at least
1057	* some ancient OSes makes it swappable) it must be floating and
1058	* synced on a per-page basis.
1059	*
1060	* Eventually we will change this to be fully on demand. Meaning that
1061	* we will only sync pages containing LDT selectors actually used and
1062	* let the #PF handler lazily sync pages as they are used.
1063	* (This applies to GDT too, when we start making OS/2 fast.)
1064	*/
1065
1066	/*
1067	* First, determine the current LDT selector.
1068	*/
1069	RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
1070	if (!(SelLdt & X86_SEL_MASK_OFF_RPL))
1071	{
1072	/* ldtr = 0 - update hyper LDTR and deregister any active handler. */
1073	CPUMSetHyperLDTR(pVCpu, 0);
1074	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1075	{
1076	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
1077	AssertRC(rc);
1078	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1079	}
1080	pVM->selm.s.cbLdtLimit = 0;
1081	return VINF_SUCCESS;
1082	}
1083
1084	/*
1085	* Get the LDT selector.
1086	*/
1087	/** @todo this is wrong, use CPUMGetGuestLdtrEx */
1088	PX86DESC pDesc = &pVM->selm.s.paGdtR3[SelLdt >> X86_SEL_SHIFT];
1089	RTGCPTR GCPtrLdt = X86DESC_BASE(pDesc);
1090	uint32_t cbLdt = X86DESC_LIMIT_G(pDesc);
1091
1092	/*
1093	* Validate it.
1094	*/
1095	if ( !cbLdt
1096	\|\| SelLdt >= pVM->selm.s.GuestGdtr.cbGdt
1097	\|\| pDesc->Gen.u1DescType
1098	\|\| pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
1099	{
1100	AssertMsg(!cbLdt, ("Invalid LDT %04x!\n", SelLdt));
1101
1102	/* cbLdt > 0:
1103	* This is quite impossible, so we do as most people do when faced with
1104	* the impossible, we simply ignore it.
1105	*/
1106	CPUMSetHyperLDTR(pVCpu, 0);
1107	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1108	{
1109	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
1110	AssertRC(rc);
1111	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1112	}
1113	return VINF_SUCCESS;
1114	}
1115	/** @todo check what intel does about odd limits. */
1116	AssertMsg(RT_ALIGN(cbLdt + 1, sizeof(X86DESC)) == cbLdt + 1 && cbLdt <= 0xffff, ("cbLdt=%d\n", cbLdt));
1117
1118	/*
1119	* Use the cached guest ldt address if the descriptor has already been modified (see below)
1120	* (this is necessary due to redundant LDT updates; see todo above at GDT sync)
1121	*/
1122	if (MMHyperIsInsideArea(pVM, GCPtrLdt))
1123	GCPtrLdt = pVM->selm.s.GCPtrGuestLdt; /* use the old one */
1124
1125
1126	/** @todo Handle only present LDT segments. */
1127	// if (pDesc->Gen.u1Present)
1128	{
1129	/*
1130	* Check if Guest's LDT address/limit is changed.
1131	*/
1132	if ( GCPtrLdt != pVM->selm.s.GCPtrGuestLdt
1133	\|\| cbLdt != pVM->selm.s.cbLdtLimit)
1134	{
1135	Log(("SELMR3UpdateFromCPUM: Guest LDT changed to from %RGv:%04x to %RGv:%04x. (GDTR=%016RX64:%04x)\n",
1136	pVM->selm.s.GCPtrGuestLdt, pVM->selm.s.cbLdtLimit, GCPtrLdt, cbLdt, pVM->selm.s.GuestGdtr.pGdt, pVM->selm.s.GuestGdtr.cbGdt));
1137
1138	#ifdef SELM_TRACK_GUEST_LDT_CHANGES
1139	/*
1140	* [Re]Register write virtual handler for guest's GDT.
1141	* In the event of LDT overlapping something, don't install it just assume it's being updated.
1142	*/
1143	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1144	{
1145	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
1146	AssertRC(rc);
1147	}
1148	# ifdef DEBUG
1149	if (pDesc->Gen.u1Present)
1150	Log(("LDT selector marked not present!!\n"));
1151	# endif
1152	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, GCPtrLdt, GCPtrLdt + cbLdt /* already inclusive */,
1153	0, selmR3GuestLDTWriteHandler, "selmRCGuestLDTWriteHandler", 0, "Guest LDT write access handler");
1154	if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1155	{
1156	/** @todo investigate the various cases where conflicts happen and try avoid them by enh. the instruction emulation. */
1157	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1158	Log(("WARNING: Guest LDT (%RGv:%04x) conflicted with existing access range!! Assumes LDT is begin updated. (GDTR=%016RX64:%04x)\n",
1159	GCPtrLdt, cbLdt, pVM->selm.s.GuestGdtr.pGdt, pVM->selm.s.GuestGdtr.cbGdt));
1160	}
1161	else if (RT_SUCCESS(rc))
1162	pVM->selm.s.GCPtrGuestLdt = GCPtrLdt;
1163	else
1164	{
1165	CPUMSetHyperLDTR(pVCpu, 0);
1166	return rc;
1167	}
1168	#else
1169	pVM->selm.s.GCPtrGuestLdt = GCPtrLdt;
1170	#endif
1171	pVM->selm.s.cbLdtLimit = cbLdt;
1172	}
1173	}
1174
1175	/*
1176	* Calc Shadow LDT base.
1177	*/
1178	unsigned off;
1179	pVM->selm.s.offLdtHyper = off = (GCPtrLdt & PAGE_OFFSET_MASK);
1180	RTGCPTR GCPtrShadowLDT = (RTGCPTR)((RTGCUINTPTR)pVM->selm.s.pvLdtRC + off);
1181	PX86DESC pShadowLDT = (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1182
1183	/*
1184	* Enable the LDT selector in the shadow GDT.
1185	*/
1186	pDesc->Gen.u1Present = 1;
1187	pDesc->Gen.u16BaseLow = RT_LOWORD(GCPtrShadowLDT);
1188	pDesc->Gen.u8BaseHigh1 = RT_BYTE3(GCPtrShadowLDT);
1189	pDesc->Gen.u8BaseHigh2 = RT_BYTE4(GCPtrShadowLDT);
1190	pDesc->Gen.u1Available = 0;
1191	pDesc->Gen.u1Long = 0;
1192	if (cbLdt > 0xffff)
1193	{
1194	cbLdt = 0xffff;
1195	pDesc->Gen.u4LimitHigh = 0;
1196	pDesc->Gen.u16LimitLow = pDesc->Gen.u1Granularity ? 0xf : 0xffff;
1197	}
1198
1199	/*
1200	* Set Hyper LDTR and notify TRPM.
1201	*/
1202	CPUMSetHyperLDTR(pVCpu, SelLdt);
1203
1204	/*
1205	* Loop synchronising the LDT page by page.
1206	*/
1207	/** @todo investigate how intel handle various operations on half present cross page entries. */
1208	off = GCPtrLdt & (sizeof(X86DESC) - 1);
1209	AssertMsg(!off, ("LDT is not aligned on entry size! GCPtrLdt=%08x\n", GCPtrLdt));
1210
1211	/* Note: Do not skip the first selector; unlike the GDT, a zero LDT selector is perfectly valid. */
1212	unsigned cbLeft = cbLdt + 1;
1213	PX86DESC pLDTE = pShadowLDT;
1214	while (cbLeft)
1215	{
1216	/*
1217	* Read a chunk.
1218	*/
1219	unsigned cbChunk = PAGE_SIZE - ((RTGCUINTPTR)GCPtrLdt & PAGE_OFFSET_MASK);
1220	if (cbChunk > cbLeft)
1221	cbChunk = cbLeft;
1222	rc = PGMPhysSimpleReadGCPtr(pVCpu, pShadowLDT, GCPtrLdt, cbChunk);
1223	if (RT_SUCCESS(rc))
1224	{
1225	/*
1226	* Mark page
1227	*/
1228	rc = PGMMapSetPage(pVM, GCPtrShadowLDT & PAGE_BASE_GC_MASK, PAGE_SIZE, X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
1229	AssertRC(rc);
1230
1231	/*
1232	* Loop thru the available LDT entries.
1233	* Figure out where to start and end and the potential cross pageness of
1234	* things adds a little complexity. pLDTE is updated there and not in the
1235	* 'next' part of the loop. The pLDTEEnd is inclusive.
1236	*/
1237	PX86DESC pLDTEEnd = (PX86DESC)((uintptr_t)pShadowLDT + cbChunk) - 1;
1238	if (pLDTE + 1 < pShadowLDT)
1239	pLDTE = (PX86DESC)((uintptr_t)pShadowLDT + off);
1240	while (pLDTE <= pLDTEEnd)
1241	{
1242	if (pLDTE->Gen.u1Present)
1243	selmGuestToShadowDesc(pVM, pLDTE);
1244
1245	/* Next LDT entry. */
1246	pLDTE++;
1247	}
1248	}
1249	else
1250	{
1251	RT_BZERO(pShadowLDT, cbChunk);
1252	AssertMsg(rc == VERR_PAGE_NOT_PRESENT \|\| rc == VERR_PAGE_TABLE_NOT_PRESENT, ("rc=%Rrc\n", rc));
1253	rc = PGMMapSetPage(pVM, GCPtrShadowLDT & PAGE_BASE_GC_MASK, PAGE_SIZE, 0);
1254	AssertRC(rc);
1255	}
1256
1257	/*
1258	* Advance to the next page.
1259	*/
1260	cbLeft -= cbChunk;
1261	GCPtrShadowLDT += cbChunk;
1262	pShadowLDT = (PX86DESC)((char *)pShadowLDT + cbChunk);
1263	GCPtrLdt += cbChunk;
1264	}
1265
1266	return VINF_SUCCESS;
1267	}
1268
1269
1270	/**
1271	* Checks and updates segment selector registers.
1272	*
1273	* @returns VBox strict status code.
1274	* @retval VINF_EM_RESCHEDULE_REM if a stale register was found.
1275	*
1276	* @param pVM The VM handle.
1277	* @param pVCpu The current virtual CPU.
1278	*/
1279	static VBOXSTRICTRC selmR3UpdateSegmentRegisters(PVM pVM, PVMCPU pVCpu)
1280	{
1281	Assert(CPUMIsGuestInProtectedMode(pVCpu));
1282	Assert(!HMIsEnabled(pVM));
1283
1284	/*
1285	* No stale selectors in V8086 mode.
1286	*/
1287	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1288	if (pCtx->eflags.Bits.u1VM)
1289	return VINF_SUCCESS;
1290
1291	/*
1292	* Check for stale selectors and load hidden register bits where they
1293	* are missing.
1294	*/
1295	uint32_t uCpl = CPUMGetGuestCPL(pVCpu);
1296	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1297	PCPUMSELREG paSReg = CPUMCTX_FIRST_SREG(pCtx);
1298	for (uint32_t iSReg = 0; iSReg < X86_SREG_COUNT; iSReg++)
1299	{
1300	RTSEL const Sel = paSReg[iSReg].Sel;
1301	if (Sel & X86_SEL_MASK_OFF_RPL)
1302	{
1303	/* Get the shadow descriptor entry corresponding to this. */
1304	static X86DESC const s_NotPresentDesc = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } };
1305	PCX86DESC pDesc;
1306	if (!(Sel & X86_SEL_LDT))
1307	{
1308	if ((Sel \| (sizeof(*pDesc) - 1)) <= pCtx->gdtr.cbGdt)
1309	pDesc = &pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
1310	else
1311	pDesc = &s_NotPresentDesc;
1312	}
1313	else
1314	{
1315	if ((Sel \| (sizeof(*pDesc) - 1)) <= pVM->selm.s.cbLdtLimit)
1316	pDesc = &((PCX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper))[Sel >> X86_SEL_SHIFT];
1317	else
1318	pDesc = &s_NotPresentDesc;
1319	}
1320
1321	/* Check the segment register. */
1322	if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &paSReg[iSReg]))
1323	{
1324	if (!(paSReg[iSReg].fFlags & CPUMSELREG_FLAGS_STALE))
1325	{
1326	/* Did it go stale? */
1327	if (selmIsSRegStale32(&paSReg[iSReg], pDesc, iSReg))
1328	{
1329	Log2(("SELM: Detected stale %s=%#x (was valid)\n", g_aszSRegNms[iSReg], Sel));
1330	STAM_REL_COUNTER_INC(&pVM->selm.s.aStatDetectedStaleSReg[iSReg]);
1331	paSReg[iSReg].fFlags \|= CPUMSELREG_FLAGS_STALE;
1332	rcStrict = VINF_EM_RESCHEDULE_REM;
1333	}
1334	}
1335	else
1336	{
1337	/* Did it stop being stale? I.e. did the guest change it things
1338	back to the way they were? */
1339	if (!selmIsSRegStale32(&paSReg[iSReg], pDesc, iSReg))
1340	{
1341	STAM_REL_COUNTER_INC(&pVM->selm.s.StatStaleToUnstaleSReg);
1342	paSReg[iSReg].fFlags &= CPUMSELREG_FLAGS_STALE;
1343	}
1344	else
1345	{
1346	Log2(("SELM: Already stale %s=%#x\n", g_aszSRegNms[iSReg], Sel));
1347	STAM_REL_COUNTER_INC(&pVM->selm.s.aStatAlreadyStaleSReg[iSReg]);
1348	rcStrict = VINF_EM_RESCHEDULE_REM;
1349	}
1350	}
1351	}
1352	/* Load the hidden registers if it's a valid descriptor for the
1353	current segment register. */
1354	else if (selmIsShwDescGoodForSReg(&paSReg[iSReg], pDesc, iSReg, uCpl))
1355	{
1356	selmLoadHiddenSRegFromShadowDesc(&paSReg[iSReg], pDesc);
1357	STAM_COUNTER_INC(&pVM->selm.s.aStatUpdatedSReg[iSReg]);
1358	}
1359	/* It's stale. */
1360	else
1361	{
1362	Log2(("SELM: Detected stale %s=%#x (wasn't valid)\n", g_aszSRegNms[iSReg], Sel));
1363	STAM_REL_COUNTER_INC(&pVM->selm.s.aStatDetectedStaleSReg[iSReg]);
1364	paSReg[iSReg].fFlags = CPUMSELREG_FLAGS_STALE;
1365	rcStrict = VINF_EM_RESCHEDULE_REM;
1366	}
1367	}
1368	/* else: 0 selector, ignore. */
1369	}
1370
1371	return rcStrict;
1372	}
1373
1374
1375	/**
1376	* Updates the Guest GDT & LDT virtualization based on current CPU state.
1377	*
1378	* @returns VBox status code.
1379	* @param pVM Pointer to the VM.
1380	* @param pVCpu Pointer to the VMCPU.
1381	*/
1382	VMMR3DECL(VBOXSTRICTRC) SELMR3UpdateFromCPUM(PVM pVM, PVMCPU pVCpu)
1383	{
1384	STAM_PROFILE_START(&pVM->selm.s.StatUpdateFromCPUM, a);
1385	AssertReturn(!HMIsEnabled(pVM), VERR_SELM_HM_IPE);
1386
1387	/*
1388	* GDT sync
1389	*/
1390	int rc;
1391	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_GDT))
1392	{
1393	rc = selmR3UpdateShadowGdt(pVM, pVCpu);
1394	if (RT_FAILURE(rc))
1395	return rc; /* We're toast, so forget the profiling. */
1396	AssertRCSuccess(rc);
1397	}
1398
1399	/*
1400	* TSS sync
1401	*/
1402	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
1403	{
1404	rc = SELMR3SyncTSS(pVM, pVCpu);
1405	if (RT_FAILURE(rc))
1406	return rc;
1407	AssertRCSuccess(rc);
1408	}
1409
1410	/*
1411	* LDT sync
1412	*/
1413	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_LDT))
1414	{
1415	rc = selmR3UpdateShadowLdt(pVM, pVCpu);
1416	if (RT_FAILURE(rc))
1417	return rc;
1418	AssertRCSuccess(rc);
1419	}
1420
1421	/*
1422	* Check selector registers.
1423	*/
1424	VBOXSTRICTRC rcStrict = selmR3UpdateSegmentRegisters(pVM, pVCpu);
1425
1426	STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1427	return rcStrict;
1428	}
1429
1430	#endif /VBOX_WITH_RAW_MODE/
1431
1432	#ifdef SELM_TRACK_GUEST_GDT_CHANGES
1433	/**
1434	* \#PF Handler callback for virtual access handler ranges.
1435	*
1436	* Important to realize that a physical page in a range can have aliases, and
1437	* for ALL and WRITE handlers these will also trigger.
1438	*
1439	* @returns VINF_SUCCESS if the handler have carried out the operation.
1440	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1441	* @param pVM Pointer to the VM.
1442	* @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1443	* @param pvPtr The HC mapping of that address.
1444	* @param pvBuf What the guest is reading/writing.
1445	* @param cbBuf How much it's reading/writing.
1446	* @param enmAccessType The access type.
1447	* @param pvUser User argument.
1448	*/
1449	static DECLCALLBACK(int) selmR3GuestGDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf,
1450	PGMACCESSTYPE enmAccessType, void *pvUser)
1451	{
1452	Assert(enmAccessType == PGMACCESSTYPE_WRITE); NOREF(enmAccessType);
1453	Log(("selmR3GuestGDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf)); NOREF(GCPtr); NOREF(cbBuf);
1454	NOREF(pvPtr); NOREF(pvBuf); NOREF(pvUser);
1455
1456	VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_SELM_SYNC_GDT);
1457	return VINF_PGM_HANDLER_DO_DEFAULT;
1458	}
1459	#endif
1460
1461	#ifdef SELM_TRACK_GUEST_LDT_CHANGES
1462	/**
1463	* \#PF Handler callback for virtual access handler ranges.
1464	*
1465	* Important to realize that a physical page in a range can have aliases, and
1466	* for ALL and WRITE handlers these will also trigger.
1467	*
1468	* @returns VINF_SUCCESS if the handler have carried out the operation.
1469	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1470	* @param pVM Pointer to the VM.
1471	* @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1472	* @param pvPtr The HC mapping of that address.
1473	* @param pvBuf What the guest is reading/writing.
1474	* @param cbBuf How much it's reading/writing.
1475	* @param enmAccessType The access type.
1476	* @param pvUser User argument.
1477	*/
1478	static DECLCALLBACK(int) selmR3GuestLDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf,
1479	PGMACCESSTYPE enmAccessType, void *pvUser)
1480	{
1481	Assert(enmAccessType == PGMACCESSTYPE_WRITE); NOREF(enmAccessType);
1482	Log(("selmR3GuestLDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf)); NOREF(GCPtr); NOREF(cbBuf);
1483	NOREF(pvPtr); NOREF(pvBuf); NOREF(pvUser);
1484
1485	VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_SELM_SYNC_LDT);
1486	return VINF_PGM_HANDLER_DO_DEFAULT;
1487	}
1488	#endif
1489
1490
1491	#ifdef SELM_TRACK_GUEST_TSS_CHANGES
1492	/**
1493	* \#PF Handler callback for virtual access handler ranges.
1494	*
1495	* Important to realize that a physical page in a range can have aliases, and
1496	* for ALL and WRITE handlers these will also trigger.
1497	*
1498	* @returns VINF_SUCCESS if the handler have carried out the operation.
1499	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1500	* @param pVM Pointer to the VM.
1501	* @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1502	* @param pvPtr The HC mapping of that address.
1503	* @param pvBuf What the guest is reading/writing.
1504	* @param cbBuf How much it's reading/writing.
1505	* @param enmAccessType The access type.
1506	* @param pvUser User argument.
1507	*/
1508	static DECLCALLBACK(int) selmR3GuestTSSWriteHandler(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf,
1509	PGMACCESSTYPE enmAccessType, void *pvUser)
1510	{
1511	Assert(enmAccessType == PGMACCESSTYPE_WRITE); NOREF(enmAccessType);
1512	Log(("selmR3GuestTSSWriteHandler: write %.*Rhxs to %RGv size %d\n", RT_MIN(8, cbBuf), pvBuf, GCPtr, cbBuf));
1513	NOREF(pvBuf); NOREF(GCPtr); NOREF(cbBuf); NOREF(pvUser);NOREF(pvPtr);
1514
1515	/** @todo This can be optimized by checking for the ESP0 offset and tracking TR
1516	* reloads in REM (setting VM_FF_SELM_SYNC_TSS if TR is reloaded). We
1517	* should probably also deregister the virtual handler if TR.base/size
1518	* changes while we're in REM. */
1519
1520	VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_SELM_SYNC_TSS);
1521	return VINF_PGM_HANDLER_DO_DEFAULT;
1522	}
1523	#endif
1524
1525	#ifdef VBOX_WITH_RAW_MODE
1526
1527	/**
1528	* Synchronize the shadowed fields in the TSS.
1529	*
1530	* At present we're shadowing the ring-0 stack selector & pointer, and the
1531	* interrupt redirection bitmap (if present). We take the lazy approach wrt to
1532	* REM and this function is called both if REM made any changes to the TSS or
1533	* loaded TR.
1534	*
1535	* @returns VBox status code.
1536	* @param pVM Pointer to the VM.
1537	* @param pVCpu Pointer to the VMCPU.
1538	*/
1539	VMMR3DECL(int) SELMR3SyncTSS(PVM pVM, PVMCPU pVCpu)
1540	{
1541	int rc;
1542	AssertReturnStmt(!HMIsEnabled(pVM), VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS), VINF_SUCCESS);
1543
1544	STAM_PROFILE_START(&pVM->selm.s.StatTSSSync, a);
1545	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_TSS));
1546
1547	/*
1548	* Get TR and extract and store the basic info.
1549	*
1550	* Note! The TSS limit is not checked by the LTR code, so we
1551	* have to be a bit careful with it. We make sure cbTss
1552	* won't be zero if TR is valid and if it's NULL we'll
1553	* make sure cbTss is 0.
1554	*/
1555	/** @todo use the hidden bits, not shadow GDT. */
1556	CPUMSELREGHID trHid;
1557	RTSEL SelTss = CPUMGetGuestTR(pVCpu, &trHid);
1558	RTGCPTR GCPtrTss = trHid.u64Base;
1559	uint32_t cbTss = trHid.u32Limit;
1560	Assert( (SelTss & X86_SEL_MASK_OFF_RPL)
1561	\|\| (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1562	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */));
1563	if (SelTss & X86_SEL_MASK_OFF_RPL)
1564	{
1565	Assert(!(SelTss & X86_SEL_LDT));
1566	Assert(trHid.Attr.n.u1DescType == 0);
1567	Assert( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY
1568	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY);
1569	if (!++cbTss)
1570	cbTss = UINT32_MAX;
1571	}
1572	else
1573	{
1574	Assert( (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1575	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */));
1576	cbTss = 0; /* the reset case. */
1577	}
1578	pVM->selm.s.cbGuestTss = cbTss;
1579	pVM->selm.s.fGuestTss32Bit = trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
1580	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY;
1581
1582	/*
1583	* Figure out the size of what need to monitor.
1584	*/
1585	/* We're not interested in any 16-bit TSSes. */
1586	uint32_t cbMonitoredTss = cbTss;
1587	if ( trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL
1588	&& trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
1589	cbMonitoredTss = 0;
1590
1591	pVM->selm.s.offGuestIoBitmap = 0;
1592	bool fNoRing1Stack = true;
1593	if (cbMonitoredTss)
1594	{
1595	/*
1596	* 32-bit TSS. What we're really keen on is the SS0 and ESP0 fields.
1597	* If VME is enabled we also want to keep an eye on the interrupt
1598	* redirection bitmap.
1599	*/
1600	VBOXTSS Tss;
1601	uint32_t cr4 = CPUMGetGuestCR4(pVCpu);
1602	rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss, GCPtrTss, RT_OFFSETOF(VBOXTSS, IntRedirBitmap));
1603	if ( !(cr4 & X86_CR4_VME)
1604	\|\| ( RT_SUCCESS(rc)
1605	&& Tss.offIoBitmap < sizeof(VBOXTSS) /* too small */
1606	&& Tss.offIoBitmap > cbTss) /* beyond the end / /* @todo not sure how the partial case is handled; probably not allowed. */
1607	)
1608	/* No interrupt redirection bitmap, just ESP0 and SS0. */
1609	cbMonitoredTss = RT_UOFFSETOF(VBOXTSS, padding_ss0);
1610	else if (RT_SUCCESS(rc))
1611	{
1612	/*
1613	* Everything up to and including the interrupt redirection bitmap. Unfortunately
1614	* this can be quite a large chunk. We use to skip it earlier and just hope it
1615	* was kind of static...
1616	*
1617	* Update the virtual interrupt redirection bitmap while we're here.
1618	* (It is located in the 32 bytes before TR:offIoBitmap.)
1619	*/
1620	cbMonitoredTss = Tss.offIoBitmap;
1621	pVM->selm.s.offGuestIoBitmap = Tss.offIoBitmap;
1622
1623	uint32_t offRedirBitmap = Tss.offIoBitmap - sizeof(Tss.IntRedirBitmap);
1624	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pVM->selm.s.Tss.IntRedirBitmap,
1625	GCPtrTss + offRedirBitmap, sizeof(Tss.IntRedirBitmap));
1626	AssertRC(rc);
1627	/** @todo memset the bitmap on failure? */
1628	Log2(("Redirection bitmap:\n"));
1629	Log2(("%.*Rhxd\n", sizeof(Tss.IntRedirBitmap), &pVM->selm.s.Tss.IntRedirBitmap));
1630	}
1631	else
1632	{
1633	cbMonitoredTss = RT_OFFSETOF(VBOXTSS, IntRedirBitmap);
1634	pVM->selm.s.offGuestIoBitmap = 0;
1635	/** @todo memset the bitmap? */
1636	}
1637
1638	/*
1639	* Update the ring 0 stack selector and base address.
1640	*/
1641	if (RT_SUCCESS(rc))
1642	{
1643	# ifdef LOG_ENABLED
1644	if (LogIsEnabled())
1645	{
1646	uint32_t ssr0, espr0;
1647	SELMGetRing1Stack(pVM, &ssr0, &espr0);
1648	if ((ssr0 & ~1) != Tss.ss0 \|\| espr0 != Tss.esp0)
1649	{
1650	RTGCPHYS GCPhys = NIL_RTGCPHYS;
1651	rc = PGMGstGetPage(pVCpu, GCPtrTss, NULL, &GCPhys); AssertRC(rc);
1652	Log(("SELMR3SyncTSS: Updating TSS ring 0 stack to %04X:%08X from %04X:%08X; TSS Phys=%RGp)\n",
1653	Tss.ss0, Tss.esp0, (ssr0 & ~1), espr0, GCPhys));
1654	AssertMsg(ssr0 != Tss.ss0,
1655	("ring-1 leak into TSS.SS0! %04X:%08X from %04X:%08X; TSS Phys=%RGp)\n",
1656	Tss.ss0, Tss.esp0, (ssr0 & ~1), espr0, GCPhys));
1657	}
1658	Log(("offIoBitmap=%#x\n", Tss.offIoBitmap));
1659	}
1660	# endif /* LOG_ENABLED */
1661	AssertMsg(!(Tss.ss0 & 3), ("ring-1 leak into TSS.SS0? %04X:%08X\n", Tss.ss0, Tss.esp0));
1662
1663	/* Update our TSS structure for the guest's ring 1 stack */
1664	selmSetRing1Stack(pVM, Tss.ss0 \| 1, Tss.esp0);
1665	pVM->selm.s.fSyncTSSRing0Stack = fNoRing1Stack = false;
1666
1667	# ifdef VBOX_WITH_RAW_RING1
1668	/* Update our TSS structure for the guest's ring 2 stack */
1669	if (EMIsRawRing1Enabled(pVM))
1670	{
1671	if ( (pVM->selm.s.Tss.ss2 != ((Tss.ss1 & ~2) \| 1))
1672	\|\| pVM->selm.s.Tss.esp2 != Tss.esp1)
1673	Log(("SELMR3SyncTSS: Updating TSS ring 1 stack to %04X:%08X from %04X:%08X\n", Tss.ss1, Tss.esp1, (pVM->selm.s.Tss.ss2 & ~2) \| 1, pVM->selm.s.Tss.esp2));
1674	selmSetRing2Stack(pVM, (Tss.ss1 & ~1) \| 2, Tss.esp1);
1675	}
1676	# endif
1677	}
1678	}
1679
1680	/*
1681	* Flush the ring-1 stack and the direct syscall dispatching if we
1682	* cannot obtain SS0:ESP0.
1683	*/
1684	if (fNoRing1Stack)
1685	{
1686	selmSetRing1Stack(pVM, 0 /* invalid SS */, 0);
1687	pVM->selm.s.fSyncTSSRing0Stack = cbMonitoredTss != 0;
1688
1689	/** @todo handle these dependencies better! */
1690	TRPMR3SetGuestTrapHandler(pVM, 0x2E, TRPM_INVALID_HANDLER);
1691	TRPMR3SetGuestTrapHandler(pVM, 0x80, TRPM_INVALID_HANDLER);
1692	}
1693
1694	/*
1695	* Check for monitor changes and apply them.
1696	*/
1697	if ( GCPtrTss != pVM->selm.s.GCPtrGuestTss
1698	\|\| cbMonitoredTss != pVM->selm.s.cbMonitoredGuestTss)
1699	{
1700	Log(("SELMR3SyncTSS: Guest's TSS is changed to pTss=%RGv cbMonitoredTss=%08X cbGuestTss=%#08x\n",
1701	GCPtrTss, cbMonitoredTss, pVM->selm.s.cbGuestTss));
1702
1703	/* Release the old range first. */
1704	if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
1705	{
1706	rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestTss);
1707	AssertRC(rc);
1708	}
1709
1710	/* Register the write handler if TS != 0. */
1711	if (cbMonitoredTss != 0)
1712	{
1713	# ifdef SELM_TRACK_GUEST_TSS_CHANGES
1714	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, GCPtrTss, GCPtrTss + cbMonitoredTss - 1,
1715	0, selmR3GuestTSSWriteHandler,
1716	"selmRCGuestTSSWriteHandler", 0, "Guest TSS write access handler");
1717	if (RT_FAILURE(rc))
1718	{
1719	# ifdef VBOX_WITH_RAW_RING1
1720	/** @todo !HACK ALERT!
1721	* Some guest OSes (QNX) share code and the TSS on the same page;
1722	* PGMR3HandlerVirtualRegister doesn't support more than one
1723	* handler, so we kick out the PATM handler as this one is more
1724	* important. Fix this properly in PGMR3HandlerVirtualRegister?
1725	*/
1726	if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1727	{
1728	LogRel(("SELMR3SyncTSS: Virtual handler conflict %RGv -> kick out PATM handler for the higher priority TSS page monitor\n", GCPtrTss));
1729	rc = PGMHandlerVirtualDeregister(pVM, GCPtrTss & PAGE_BASE_GC_MASK);
1730	AssertRC(rc);
1731
1732	rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, GCPtrTss, GCPtrTss + cbMonitoredTss - 1,
1733	0, selmR3GuestTSSWriteHandler,
1734	"selmRCGuestTSSWriteHandler", 0, "Guest TSS write access handler");
1735	if (RT_FAILURE(rc))
1736	{
1737	STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1738	return rc;
1739	}
1740	}
1741	# else
1742	STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1743	return rc;
1744	# endif
1745	}
1746	# endif /* SELM_TRACK_GUEST_TSS_CHANGES */
1747
1748	/* Update saved Guest TSS info. */
1749	pVM->selm.s.GCPtrGuestTss = GCPtrTss;
1750	pVM->selm.s.cbMonitoredGuestTss = cbMonitoredTss;
1751	pVM->selm.s.GCSelTss = SelTss;
1752	}
1753	else
1754	{
1755	pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
1756	pVM->selm.s.cbMonitoredGuestTss = 0;
1757	pVM->selm.s.GCSelTss = 0;
1758	}
1759	}
1760
1761	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1762
1763	STAM_PROFILE_STOP(&pVM->selm.s.StatTSSSync, a);
1764	return VINF_SUCCESS;
1765	}
1766
1767
1768	/**
1769	* Compares the Guest GDT and LDT with the shadow tables.
1770	* This is a VBOX_STRICT only function.
1771	*
1772	* @returns VBox status code.
1773	* @param pVM Pointer to the VM.
1774	*/
1775	VMMR3DECL(int) SELMR3DebugCheck(PVM pVM)
1776	{
1777	#ifdef VBOX_STRICT
1778	PVMCPU pVCpu = VMMGetCpu(pVM);
1779	AssertReturn(!HMIsEnabled(pVM), VERR_SELM_HM_IPE);
1780
1781	/*
1782	* Get GDTR and check for conflict.
1783	*/
1784	VBOXGDTR GDTR;
1785	CPUMGetGuestGDTR(pVCpu, &GDTR);
1786	if (GDTR.cbGdt == 0)
1787	return VINF_SUCCESS;
1788
1789	if (GDTR.cbGdt >= (unsigned)(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> X86_SEL_SHIFT))
1790	Log(("SELMR3DebugCheck: guest GDT size forced us to look for unused selectors.\n"));
1791
1792	if (GDTR.cbGdt != pVM->selm.s.GuestGdtr.cbGdt)
1793	Log(("SELMR3DebugCheck: limits have changed! new=%d old=%d\n", GDTR.cbGdt, pVM->selm.s.GuestGdtr.cbGdt));
1794
1795	/*
1796	* Loop thru the GDT checking each entry.
1797	*/
1798	RTGCPTR GCPtrGDTEGuest = GDTR.pGdt;
1799	PX86DESC pGDTE = pVM->selm.s.paGdtR3;
1800	PX86DESC pGDTEEnd = (PX86DESC)((uintptr_t)pGDTE + GDTR.cbGdt);
1801	while (pGDTE < pGDTEEnd)
1802	{
1803	X86DESC GDTEGuest;
1804	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GDTEGuest, GCPtrGDTEGuest, sizeof(GDTEGuest));
1805	if (RT_SUCCESS(rc))
1806	{
1807	if (pGDTE->Gen.u1DescType \|\| pGDTE->Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
1808	{
1809	if ( pGDTE->Gen.u16LimitLow != GDTEGuest.Gen.u16LimitLow
1810	\|\| pGDTE->Gen.u4LimitHigh != GDTEGuest.Gen.u4LimitHigh
1811	\|\| pGDTE->Gen.u16BaseLow != GDTEGuest.Gen.u16BaseLow
1812	\|\| pGDTE->Gen.u8BaseHigh1 != GDTEGuest.Gen.u8BaseHigh1
1813	\|\| pGDTE->Gen.u8BaseHigh2 != GDTEGuest.Gen.u8BaseHigh2
1814	\|\| pGDTE->Gen.u1DefBig != GDTEGuest.Gen.u1DefBig
1815	\|\| pGDTE->Gen.u1DescType != GDTEGuest.Gen.u1DescType)
1816	{
1817	unsigned iGDT = pGDTE - pVM->selm.s.paGdtR3;
1818	SELMR3DumpDescriptor(*pGDTE, iGDT << 3, "SELMR3DebugCheck: GDT mismatch, shadow");
1819	SELMR3DumpDescriptor(GDTEGuest, iGDT << 3, "SELMR3DebugCheck: GDT mismatch, guest");
1820	}
1821	}
1822	}
1823
1824	/* Advance to the next descriptor. */
1825	GCPtrGDTEGuest += sizeof(X86DESC);
1826	pGDTE++;
1827	}
1828
1829
1830	/*
1831	* LDT?
1832	*/
1833	RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
1834	if ((SelLdt & X86_SEL_MASK_OFF_RPL) == 0)
1835	return VINF_SUCCESS;
1836	Assert(!(SelLdt & X86_SEL_LDT));
1837	if (SelLdt > GDTR.cbGdt)
1838	{
1839	Log(("SELMR3DebugCheck: ldt is out of bound SelLdt=%#x\n", SelLdt));
1840	return VERR_SELM_LDT_OUT_OF_BOUNDS;
1841	}
1842	X86DESC LDTDesc;
1843	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &LDTDesc, GDTR.pGdt + (SelLdt & X86_SEL_MASK), sizeof(LDTDesc));
1844	if (RT_FAILURE(rc))
1845	{
1846	Log(("SELMR3DebugCheck: Failed to read LDT descriptor. rc=%d\n", rc));
1847	return rc;
1848	}
1849	RTGCPTR GCPtrLDTEGuest = X86DESC_BASE(&LDTDesc);
1850	uint32_t cbLdt = X86DESC_LIMIT_G(&LDTDesc);
1851
1852	/*
1853	* Validate it.
1854	*/
1855	if (!cbLdt)
1856	return VINF_SUCCESS;
1857	/** @todo check what intel does about odd limits. */
1858	AssertMsg(RT_ALIGN(cbLdt + 1, sizeof(X86DESC)) == cbLdt + 1 && cbLdt <= 0xffff, ("cbLdt=%d\n", cbLdt));
1859	if ( LDTDesc.Gen.u1DescType
1860	\|\| LDTDesc.Gen.u4Type != X86_SEL_TYPE_SYS_LDT
1861	\|\| SelLdt >= pVM->selm.s.GuestGdtr.cbGdt)
1862	{
1863	Log(("SELmR3DebugCheck: Invalid LDT %04x!\n", SelLdt));
1864	return VERR_SELM_INVALID_LDT;
1865	}
1866
1867	/*
1868	* Loop thru the LDT checking each entry.
1869	*/
1870	unsigned off = (GCPtrLDTEGuest & PAGE_OFFSET_MASK);
1871	PX86DESC pLDTE = (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1872	PX86DESC pLDTEEnd = (PX86DESC)((uintptr_t)pGDTE + cbLdt);
1873	while (pLDTE < pLDTEEnd)
1874	{
1875	X86DESC LDTEGuest;
1876	rc = PGMPhysSimpleReadGCPtr(pVCpu, &LDTEGuest, GCPtrLDTEGuest, sizeof(LDTEGuest));
1877	if (RT_SUCCESS(rc))
1878	{
1879	if ( pLDTE->Gen.u16LimitLow != LDTEGuest.Gen.u16LimitLow
1880	\|\| pLDTE->Gen.u4LimitHigh != LDTEGuest.Gen.u4LimitHigh
1881	\|\| pLDTE->Gen.u16BaseLow != LDTEGuest.Gen.u16BaseLow
1882	\|\| pLDTE->Gen.u8BaseHigh1 != LDTEGuest.Gen.u8BaseHigh1
1883	\|\| pLDTE->Gen.u8BaseHigh2 != LDTEGuest.Gen.u8BaseHigh2
1884	\|\| pLDTE->Gen.u1DefBig != LDTEGuest.Gen.u1DefBig
1885	\|\| pLDTE->Gen.u1DescType != LDTEGuest.Gen.u1DescType)
1886	{
1887	unsigned iLDT = pLDTE - (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1888	SELMR3DumpDescriptor(*pLDTE, iLDT << 3, "SELMR3DebugCheck: LDT mismatch, shadow");
1889	SELMR3DumpDescriptor(LDTEGuest, iLDT << 3, "SELMR3DebugCheck: LDT mismatch, guest");
1890	}
1891	}
1892
1893	/* Advance to the next descriptor. */
1894	GCPtrLDTEGuest += sizeof(X86DESC);
1895	pLDTE++;
1896	}
1897
1898	#else /* !VBOX_STRICT */
1899	NOREF(pVM);
1900	#endif /* !VBOX_STRICT */
1901
1902	return VINF_SUCCESS;
1903	}
1904
1905
1906	/**
1907	* Validates the RawR0 TSS values against the one in the Guest TSS.
1908	*
1909	* @returns true if it matches.
1910	* @returns false and assertions on mismatch..
1911	* @param pVM Pointer to the VM.
1912	*/
1913	VMMR3DECL(bool) SELMR3CheckTSS(PVM pVM)
1914	{
1915	#if defined(VBOX_STRICT) && defined(SELM_TRACK_GUEST_TSS_CHANGES)
1916	PVMCPU pVCpu = VMMGetCpu(pVM);
1917
1918	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
1919	return true;
1920
1921	/*
1922	* Get TR and extract the basic info.
1923	*/
1924	CPUMSELREGHID trHid;
1925	RTSEL SelTss = CPUMGetGuestTR(pVCpu, &trHid);
1926	RTGCPTR GCPtrTss = trHid.u64Base;
1927	uint32_t cbTss = trHid.u32Limit;
1928	Assert( (SelTss & X86_SEL_MASK_OFF_RPL)
1929	\|\| (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1930	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */));
1931	if (SelTss & X86_SEL_MASK_OFF_RPL)
1932	{
1933	AssertReturn(!(SelTss & X86_SEL_LDT), false);
1934	AssertReturn(trHid.Attr.n.u1DescType == 0, false);
1935	AssertReturn( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY
1936	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY,
1937	false);
1938	if (!++cbTss)
1939	cbTss = UINT32_MAX;
1940	}
1941	else
1942	{
1943	AssertReturn( (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1944	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */),
1945	false);
1946	cbTss = 0; /* the reset case. */
1947	}
1948	AssertMsgReturn(pVM->selm.s.cbGuestTss == cbTss, ("%#x %#x\n", pVM->selm.s.cbGuestTss, cbTss), false);
1949	AssertMsgReturn(pVM->selm.s.fGuestTss32Bit == ( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
1950	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY),
1951	("%RTbool u4Type=%d\n", pVM->selm.s.fGuestTss32Bit, trHid.Attr.n.u4Type),
1952	false);
1953	AssertMsgReturn( pVM->selm.s.GCSelTss == SelTss
1954	\|\| (!pVM->selm.s.GCSelTss && !(SelTss & X86_SEL_LDT)),
1955	("%#x %#x\n", pVM->selm.s.GCSelTss, SelTss),
1956	false);
1957	AssertMsgReturn( pVM->selm.s.GCPtrGuestTss == GCPtrTss
1958	\|\| (pVM->selm.s.GCPtrGuestTss == RTRCPTR_MAX && !GCPtrTss),
1959	("%#RGv %#RGv\n", pVM->selm.s.GCPtrGuestTss, GCPtrTss),
1960	false);
1961
1962
1963	/*
1964	* Figure out the size of what need to monitor.
1965	*/
1966	/* We're not interested in any 16-bit TSSes. */
1967	uint32_t cbMonitoredTss = cbTss;
1968	if ( trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL
1969	&& trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
1970	cbMonitoredTss = 0;
1971	if (cbMonitoredTss)
1972	{
1973	VBOXTSS Tss;
1974	uint32_t cr4 = CPUMGetGuestCR4(pVCpu);
1975	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss, GCPtrTss, RT_OFFSETOF(VBOXTSS, IntRedirBitmap));
1976	AssertReturn( rc == VINF_SUCCESS
1977	/* Happens early in XP boot during page table switching. */
1978	\|\| ( (rc == VERR_PAGE_TABLE_NOT_PRESENT \|\| rc == VERR_PAGE_NOT_PRESENT)
1979	&& !(CPUMGetGuestEFlags(pVCpu) & X86_EFL_IF)),
1980	false);
1981	if ( !(cr4 & X86_CR4_VME)
1982	\|\| ( RT_SUCCESS(rc)
1983	&& Tss.offIoBitmap < sizeof(VBOXTSS) /* too small */
1984	&& Tss.offIoBitmap > cbTss)
1985	)
1986	cbMonitoredTss = RT_UOFFSETOF(VBOXTSS, padding_ss0);
1987	else if (RT_SUCCESS(rc))
1988	{
1989	cbMonitoredTss = Tss.offIoBitmap;
1990	AssertMsgReturn(pVM->selm.s.offGuestIoBitmap == Tss.offIoBitmap,
1991	("#x %#x\n", pVM->selm.s.offGuestIoBitmap, Tss.offIoBitmap),
1992	false);
1993
1994	/* check the bitmap */
1995	uint32_t offRedirBitmap = Tss.offIoBitmap - sizeof(Tss.IntRedirBitmap);
1996	rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss.IntRedirBitmap,
1997	GCPtrTss + offRedirBitmap, sizeof(Tss.IntRedirBitmap));
1998	AssertRCReturn(rc, false);
1999	AssertMsgReturn(!memcmp(&Tss.IntRedirBitmap[0], &pVM->selm.s.Tss.IntRedirBitmap[0], sizeof(Tss.IntRedirBitmap)),
2000	("offIoBitmap=%#x cbTss=%#x\n"
2001	" Guest: %.32Rhxs\n"
2002	"Shadow: %.32Rhxs\n",
2003	Tss.offIoBitmap, cbTss,
2004	&Tss.IntRedirBitmap[0],
2005	&pVM->selm.s.Tss.IntRedirBitmap[0]),
2006	false);
2007	}
2008	else
2009	cbMonitoredTss = RT_OFFSETOF(VBOXTSS, IntRedirBitmap);
2010
2011	/*
2012	* Check SS0 and ESP0.
2013	*/
2014	if ( !pVM->selm.s.fSyncTSSRing0Stack
2015	&& RT_SUCCESS(rc))
2016	{
2017	if ( Tss.esp0 != pVM->selm.s.Tss.esp1
2018	\|\| Tss.ss0 != (pVM->selm.s.Tss.ss1 & ~1))
2019	{
2020	RTGCPHYS GCPhys;
2021	rc = PGMGstGetPage(pVCpu, GCPtrTss, NULL, &GCPhys); AssertRC(rc);
2022	AssertMsgFailed(("TSS out of sync!! (%04X:%08X vs %04X:%08X (guest)) Tss=%RGv Phys=%RGp\n",
2023	(pVM->selm.s.Tss.ss1 & ~1), pVM->selm.s.Tss.esp1,
2024	Tss.ss1, Tss.esp1, GCPtrTss, GCPhys));
2025	return false;
2026	}
2027	}
2028	AssertMsgReturn(pVM->selm.s.cbMonitoredGuestTss == cbMonitoredTss, ("%#x %#x\n", pVM->selm.s.cbMonitoredGuestTss, cbMonitoredTss), false);
2029	}
2030	else
2031	{
2032	AssertMsgReturn(pVM->selm.s.Tss.ss1 == 0 && pVM->selm.s.Tss.esp1 == 0, ("%04x:%08x\n", pVM->selm.s.Tss.ss1, pVM->selm.s.Tss.esp1), false);
2033	AssertReturn(!pVM->selm.s.fSyncTSSRing0Stack, false);
2034	AssertMsgReturn(pVM->selm.s.cbMonitoredGuestTss == cbMonitoredTss, ("%#x %#x\n", pVM->selm.s.cbMonitoredGuestTss, cbMonitoredTss), false);
2035	}
2036
2037
2038
2039	return true;
2040
2041	#else /* !VBOX_STRICT */
2042	NOREF(pVM);
2043	return true;
2044	#endif /* !VBOX_STRICT */
2045	}
2046
2047
2048	# ifdef VBOX_WITH_SAFE_STR
2049	/**
2050	* Validates the RawR0 TR shadow GDT entry.
2051	*
2052	* @returns true if it matches.
2053	* @returns false and assertions on mismatch..
2054	* @param pVM Pointer to the VM.
2055	*/
2056	VMMR3DECL(bool) SELMR3CheckShadowTR(PVM pVM)
2057	{
2058	# ifdef VBOX_STRICT
2059	PX86DESC paGdt = pVM->selm.s.paGdtR3;
2060
2061	/*
2062	* TSS descriptor
2063	*/
2064	PX86DESC pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3];
2065	RTRCPTR RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
2066
2067	if ( pDesc->Gen.u16BaseLow != RT_LOWORD(RCPtrTSS)
2068	\|\| pDesc->Gen.u8BaseHigh1 != RT_BYTE3(RCPtrTSS)
2069	\|\| pDesc->Gen.u8BaseHigh2 != RT_BYTE4(RCPtrTSS)
2070	\|\| pDesc->Gen.u16LimitLow != sizeof(VBOXTSS) - 1
2071	\|\| pDesc->Gen.u4LimitHigh != 0
2072	\|\| (pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL && pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
2073	\|\| pDesc->Gen.u1DescType != 0 /* system */
2074	\|\| pDesc->Gen.u2Dpl != 0 /* supervisor */
2075	\|\| pDesc->Gen.u1Present != 1
2076	\|\| pDesc->Gen.u1Available != 0
2077	\|\| pDesc->Gen.u1Long != 0
2078	\|\| pDesc->Gen.u1DefBig != 0
2079	\|\| pDesc->Gen.u1Granularity != 0 /* byte limit */
2080	)
2081	{
2082	AssertFailed();
2083	return false;
2084	}
2085	# endif
2086	return true;
2087	}
2088	# endif /* VBOX_WITH_SAFE_STR */
2089
2090	#endif /* VBOX_WITH_RAW_MODE */
2091
2092	/**
2093	* Gets information about a 64-bit selector, SELMR3GetSelectorInfo helper.
2094	*
2095	* See SELMR3GetSelectorInfo for details.
2096	*
2097	* @returns VBox status code, see SELMR3GetSelectorInfo for details.
2098	*
2099	* @param pVCpu Pointer to the VMCPU.
2100	* @param Sel The selector to get info about.
2101	* @param pSelInfo Where to store the information.
2102	*/
2103	static int selmR3GetSelectorInfo64(PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo)
2104	{
2105	/*
2106	* Read it from the guest descriptor table.
2107	*/
2108	/** @todo this is bogus wrt the LDT/GDT limit on long selectors. */
2109	X86DESC64 Desc;
2110	RTGCPTR GCPtrDesc;
2111	if (!(Sel & X86_SEL_LDT))
2112	{
2113	/* GDT */
2114	VBOXGDTR Gdtr;
2115	CPUMGetGuestGDTR(pVCpu, &Gdtr);
2116	if ((Sel \| X86_SEL_RPL_LDT) > Gdtr.cbGdt)
2117	return VERR_INVALID_SELECTOR;
2118	GCPtrDesc = Gdtr.pGdt + (Sel & X86_SEL_MASK);
2119	}
2120	else
2121	{
2122	/* LDT */
2123	uint64_t GCPtrBase;
2124	uint32_t cbLimit;
2125	CPUMGetGuestLdtrEx(pVCpu, &GCPtrBase, &cbLimit);
2126	if ((Sel \| X86_SEL_RPL_LDT) > cbLimit)
2127	return VERR_INVALID_SELECTOR;
2128
2129	/* calc the descriptor location. */
2130	GCPtrDesc = GCPtrBase + (Sel & X86_SEL_MASK);
2131	}
2132
2133	/* read the descriptor. */
2134	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(Desc));
2135	if (RT_FAILURE(rc))
2136	{
2137	rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(X86DESC));
2138	if (RT_FAILURE(rc))
2139	return rc;
2140	Desc.au64[1] = 0;
2141	}
2142
2143	/*
2144	* Extract the base and limit
2145	* (We ignore the present bit here, which is probably a bit silly...)
2146	*/
2147	pSelInfo->Sel = Sel;
2148	pSelInfo->fFlags = DBGFSELINFO_FLAGS_LONG_MODE;
2149	pSelInfo->u.Raw64 = Desc;
2150	if (Desc.Gen.u1DescType)
2151	{
2152	/*
2153	* 64-bit code selectors are wide open, it's not possible to detect
2154	* 64-bit data or stack selectors without also dragging in assumptions
2155	* about current CS (i.e. that's we're executing in 64-bit mode). So,
2156	* the selinfo user needs to deal with this in the context the info is
2157	* used unfortunately.
2158	*/
2159	if ( Desc.Gen.u1Long
2160	&& !Desc.Gen.u1DefBig
2161	&& (Desc.Gen.u4Type & X86_SEL_TYPE_CODE))
2162	{
2163	/* Note! We ignore the segment limit hacks that was added by AMD. */
2164	pSelInfo->GCPtrBase = 0;
2165	pSelInfo->cbLimit = ~(RTGCUINTPTR)0;
2166	}
2167	else
2168	{
2169	pSelInfo->cbLimit = X86DESC_LIMIT_G(&Desc);
2170	pSelInfo->GCPtrBase = X86DESC_BASE(&Desc);
2171	}
2172	pSelInfo->SelGate = 0;
2173	}
2174	else if ( Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_LDT
2175	\|\| Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_TSS_AVAIL
2176	\|\| Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_TSS_BUSY)
2177	{
2178	/* Note. LDT descriptors are weird in long mode, we ignore the footnote
2179	in the AMD manual here as a simplification. */
2180	pSelInfo->GCPtrBase = X86DESC64_BASE(&Desc);
2181	pSelInfo->cbLimit = X86DESC_LIMIT_G(&Desc);
2182	pSelInfo->SelGate = 0;
2183	}
2184	else if ( Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_CALL_GATE
2185	\|\| Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_TRAP_GATE
2186	\|\| Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_INT_GATE)
2187	{
2188	pSelInfo->cbLimit = X86DESC64_BASE(&Desc);
2189	pSelInfo->GCPtrBase = Desc.Gate.u16OffsetLow
2190	\| ((uint32_t)Desc.Gate.u16OffsetHigh << 16)
2191	\| ((uint64_t)Desc.Gate.u32OffsetTop << 32);
2192	pSelInfo->SelGate = Desc.Gate.u16Sel;
2193	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_GATE;
2194	}
2195	else
2196	{
2197	pSelInfo->cbLimit = 0;
2198	pSelInfo->GCPtrBase = 0;
2199	pSelInfo->SelGate = 0;
2200	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_INVALID;
2201	}
2202	if (!Desc.Gen.u1Present)
2203	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_NOT_PRESENT;
2204
2205	return VINF_SUCCESS;
2206	}
2207
2208
2209	/**
2210	* Worker for selmR3GetSelectorInfo32 and SELMR3GetShadowSelectorInfo that
2211	* interprets a legacy descriptor table entry and fills in the selector info
2212	* structure from it.
2213	*
2214	* @param pSelInfo Where to store the selector info. Only the fFlags and
2215	* Sel members have been initialized.
2216	* @param pDesc The legacy descriptor to parse.
2217	*/
2218	DECLINLINE(void) selmR3SelInfoFromDesc32(PDBGFSELINFO pSelInfo, PCX86DESC pDesc)
2219	{
2220	pSelInfo->u.Raw64.au64[1] = 0;
2221	pSelInfo->u.Raw = *pDesc;
2222	if ( pDesc->Gen.u1DescType
2223	\|\| !(pDesc->Gen.u4Type & 4))
2224	{
2225	pSelInfo->cbLimit = X86DESC_LIMIT_G(pDesc);
2226	pSelInfo->GCPtrBase = X86DESC_BASE(pDesc);
2227	pSelInfo->SelGate = 0;
2228	}
2229	else if (pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_UNDEFINED4)
2230	{
2231	pSelInfo->cbLimit = 0;
2232	if (pDesc->Gen.u4Type == X86_SEL_TYPE_SYS_TASK_GATE)
2233	pSelInfo->GCPtrBase = 0;
2234	else
2235	pSelInfo->GCPtrBase = pDesc->Gate.u16OffsetLow
2236	\| (uint32_t)pDesc->Gate.u16OffsetHigh << 16;
2237	pSelInfo->SelGate = pDesc->Gate.u16Sel;
2238	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_GATE;
2239	}
2240	else
2241	{
2242	pSelInfo->cbLimit = 0;
2243	pSelInfo->GCPtrBase = 0;
2244	pSelInfo->SelGate = 0;
2245	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_INVALID;
2246	}
2247	if (!pDesc->Gen.u1Present)
2248	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_NOT_PRESENT;
2249	}
2250
2251
2252	/**
2253	* Gets information about a 64-bit selector, SELMR3GetSelectorInfo helper.
2254	*
2255	* See SELMR3GetSelectorInfo for details.
2256	*
2257	* @returns VBox status code, see SELMR3GetSelectorInfo for details.
2258	*
2259	* @param pVM Pointer to the VM.
2260	* @param pVCpu Pointer to the VMCPU.
2261	* @param Sel The selector to get info about.
2262	* @param pSelInfo Where to store the information.
2263	*/
2264	static int selmR3GetSelectorInfo32(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo)
2265	{
2266	/*
2267	* Read the descriptor entry
2268	*/
2269	pSelInfo->fFlags = 0;
2270	X86DESC Desc;
2271	if ( !(Sel & X86_SEL_LDT)
2272	&& ( pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] == (Sel & X86_SEL_RPL_LDT)
2273	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] == (Sel & X86_SEL_RPL_LDT)
2274	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] == (Sel & X86_SEL_RPL_LDT)
2275	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] == (Sel & X86_SEL_RPL_LDT)
2276	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] == (Sel & X86_SEL_RPL_LDT))
2277	)
2278	{
2279	/*
2280	* Hypervisor descriptor.
2281	*/
2282	pSelInfo->fFlags = DBGFSELINFO_FLAGS_HYPER;
2283	if (CPUMIsGuestInProtectedMode(pVCpu))
2284	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_PROT_MODE;
2285	else
2286	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_REAL_MODE;
2287
2288	Desc = pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
2289	}
2290	else if (CPUMIsGuestInProtectedMode(pVCpu))
2291	{
2292	/*
2293	* Read it from the guest descriptor table.
2294	*/
2295	pSelInfo->fFlags = DBGFSELINFO_FLAGS_PROT_MODE;
2296
2297	RTGCPTR GCPtrDesc;
2298	if (!(Sel & X86_SEL_LDT))
2299	{
2300	/* GDT */
2301	VBOXGDTR Gdtr;
2302	CPUMGetGuestGDTR(pVCpu, &Gdtr);
2303	if ((Sel \| X86_SEL_RPL_LDT) > Gdtr.cbGdt)
2304	return VERR_INVALID_SELECTOR;
2305	GCPtrDesc = Gdtr.pGdt + (Sel & X86_SEL_MASK);
2306	}
2307	else
2308	{
2309	/* LDT */
2310	uint64_t GCPtrBase;
2311	uint32_t cbLimit;
2312	CPUMGetGuestLdtrEx(pVCpu, &GCPtrBase, &cbLimit);
2313	if ((Sel \| X86_SEL_RPL_LDT) > cbLimit)
2314	return VERR_INVALID_SELECTOR;
2315
2316	/* calc the descriptor location. */
2317	GCPtrDesc = GCPtrBase + (Sel & X86_SEL_MASK);
2318	}
2319
2320	/* read the descriptor. */
2321	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(Desc));
2322	if (RT_FAILURE(rc))
2323	return rc;
2324	}
2325	else
2326	{
2327	/*
2328	* We're in real mode.
2329	*/
2330	pSelInfo->Sel = Sel;
2331	pSelInfo->GCPtrBase = Sel << 4;
2332	pSelInfo->cbLimit = 0xffff;
2333	pSelInfo->fFlags = DBGFSELINFO_FLAGS_REAL_MODE;
2334	pSelInfo->u.Raw64.au64[0] = 0;
2335	pSelInfo->u.Raw64.au64[1] = 0;
2336	pSelInfo->SelGate = 0;
2337	return VINF_SUCCESS;
2338	}
2339
2340	/*
2341	* Extract the base and limit or sel:offset for gates.
2342	*/
2343	pSelInfo->Sel = Sel;
2344	selmR3SelInfoFromDesc32(pSelInfo, &Desc);
2345
2346	return VINF_SUCCESS;
2347	}
2348
2349
2350	/**
2351	* Gets information about a selector.
2352	*
2353	* Intended for the debugger mostly and will prefer the guest descriptor tables
2354	* over the shadow ones.
2355	*
2356	* @retval VINF_SUCCESS on success.
2357	* @retval VERR_INVALID_SELECTOR if the selector isn't fully inside the
2358	* descriptor table.
2359	* @retval VERR_SELECTOR_NOT_PRESENT if the LDT is invalid or not present. This
2360	* is not returned if the selector itself isn't present, you have to
2361	* check that for yourself (see DBGFSELINFO::fFlags).
2362	* @retval VERR_PAGE_TABLE_NOT_PRESENT or VERR_PAGE_NOT_PRESENT if the
2363	* pagetable or page backing the selector table wasn't present.
2364	* @returns Other VBox status code on other errors.
2365	*
2366	* @param pVM Pointer to the VM.
2367	* @param pVCpu Pointer to the VMCPU.
2368	* @param Sel The selector to get info about.
2369	* @param pSelInfo Where to store the information.
2370	*/
2371	VMMR3DECL(int) SELMR3GetSelectorInfo(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo)
2372	{
2373	AssertPtr(pSelInfo);
2374	if (CPUMIsGuestInLongMode(pVCpu))
2375	return selmR3GetSelectorInfo64(pVCpu, Sel, pSelInfo);
2376	return selmR3GetSelectorInfo32(pVM, pVCpu, Sel, pSelInfo);
2377	}
2378
2379
2380	/**
2381	* Gets information about a selector from the shadow tables.
2382	*
2383	* This is intended to be faster than the SELMR3GetSelectorInfo() method, but
2384	* requires that the caller ensures that the shadow tables are up to date.
2385	*
2386	* @retval VINF_SUCCESS on success.
2387	* @retval VERR_INVALID_SELECTOR if the selector isn't fully inside the
2388	* descriptor table.
2389	* @retval VERR_SELECTOR_NOT_PRESENT if the LDT is invalid or not present. This
2390	* is not returned if the selector itself isn't present, you have to
2391	* check that for yourself (see DBGFSELINFO::fFlags).
2392	* @retval VERR_PAGE_TABLE_NOT_PRESENT or VERR_PAGE_NOT_PRESENT if the
2393	* pagetable or page backing the selector table wasn't present.
2394	* @returns Other VBox status code on other errors.
2395	*
2396	* @param pVM Pointer to the VM.
2397	* @param Sel The selector to get info about.
2398	* @param pSelInfo Where to store the information.
2399	*
2400	* @remarks Don't use this when in hardware assisted virtualization mode.
2401	*/
2402	VMMR3DECL(int) SELMR3GetShadowSelectorInfo(PVM pVM, RTSEL Sel, PDBGFSELINFO pSelInfo)
2403	{
2404	Assert(pSelInfo);
2405
2406	/*
2407	* Read the descriptor entry
2408	*/
2409	X86DESC Desc;
2410	if (!(Sel & X86_SEL_LDT))
2411	{
2412	/*
2413	* Global descriptor.
2414	*/
2415	Desc = pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
2416	pSelInfo->fFlags = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] == (Sel & X86_SEL_MASK_OFF_RPL)
2417	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] == (Sel & X86_SEL_MASK_OFF_RPL)
2418	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] == (Sel & X86_SEL_MASK_OFF_RPL)
2419	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] == (Sel & X86_SEL_MASK_OFF_RPL)
2420	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] == (Sel & X86_SEL_MASK_OFF_RPL)
2421	? DBGFSELINFO_FLAGS_HYPER
2422	: 0;
2423	/** @todo check that the GDT offset is valid. */
2424	}
2425	else
2426	{
2427	/*
2428	* Local Descriptor.
2429	*/
2430	PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper);
2431	Desc = paLDT[Sel >> X86_SEL_SHIFT];
2432	/** @todo check if the LDT page is actually available. */
2433	/** @todo check that the LDT offset is valid. */
2434	pSelInfo->fFlags = 0;
2435	}
2436	if (CPUMIsGuestInProtectedMode(VMMGetCpu0(pVM)))
2437	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_PROT_MODE;
2438	else
2439	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_REAL_MODE;
2440
2441	/*
2442	* Extract the base and limit or sel:offset for gates.
2443	*/
2444	pSelInfo->Sel = Sel;
2445	selmR3SelInfoFromDesc32(pSelInfo, &Desc);
2446
2447	return VINF_SUCCESS;
2448	}
2449
2450
2451	/**
2452	* Formats a descriptor.
2453	*
2454	* @param Desc Descriptor to format.
2455	* @param Sel Selector number.
2456	* @param pszOutput Output buffer.
2457	* @param cchOutput Size of output buffer.
2458	*/
2459	static void selmR3FormatDescriptor(X86DESC Desc, RTSEL Sel, char *pszOutput, size_t cchOutput)
2460	{
2461	/*
2462	* Make variable description string.
2463	*/
2464	static struct
2465	{
2466	unsigned cch;
2467	const char *psz;
2468	} const aTypes[32] =
2469	{
2470	#define STRENTRY(str) { sizeof(str) - 1, str }
2471	/* system */
2472	STRENTRY("Reserved0 "), /* 0x00 */
2473	STRENTRY("TSS16Avail "), /* 0x01 */
2474	STRENTRY("LDT "), /* 0x02 */
2475	STRENTRY("TSS16Busy "), /* 0x03 */
2476	STRENTRY("Call16 "), /* 0x04 */
2477	STRENTRY("Task "), /* 0x05 */
2478	STRENTRY("Int16 "), /* 0x06 */
2479	STRENTRY("Trap16 "), /* 0x07 */
2480	STRENTRY("Reserved8 "), /* 0x08 */
2481	STRENTRY("TSS32Avail "), /* 0x09 */
2482	STRENTRY("ReservedA "), /* 0x0a */
2483	STRENTRY("TSS32Busy "), /* 0x0b */
2484	STRENTRY("Call32 "), /* 0x0c */
2485	STRENTRY("ReservedD "), /* 0x0d */
2486	STRENTRY("Int32 "), /* 0x0e */
2487	STRENTRY("Trap32 "), /* 0x0f */
2488	/* non system */
2489	STRENTRY("DataRO "), /* 0x10 */
2490	STRENTRY("DataRO Accessed "), /* 0x11 */
2491	STRENTRY("DataRW "), /* 0x12 */
2492	STRENTRY("DataRW Accessed "), /* 0x13 */
2493	STRENTRY("DataDownRO "), /* 0x14 */
2494	STRENTRY("DataDownRO Accessed "), /* 0x15 */
2495	STRENTRY("DataDownRW "), /* 0x16 */
2496	STRENTRY("DataDownRW Accessed "), /* 0x17 */
2497	STRENTRY("CodeEO "), /* 0x18 */
2498	STRENTRY("CodeEO Accessed "), /* 0x19 */
2499	STRENTRY("CodeER "), /* 0x1a */
2500	STRENTRY("CodeER Accessed "), /* 0x1b */
2501	STRENTRY("CodeConfEO "), /* 0x1c */
2502	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
2503	STRENTRY("CodeConfER "), /* 0x1e */
2504	STRENTRY("CodeConfER Accessed ") /* 0x1f */
2505	#undef SYSENTRY
2506	};
2507	#define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
2508	char szMsg[128];
2509	char *psz = &szMsg[0];
2510	unsigned i = Desc.Gen.u1DescType << 4 \| Desc.Gen.u4Type;
2511	memcpy(psz, aTypes[i].psz, aTypes[i].cch);
2512	psz += aTypes[i].cch;
2513
2514	if (Desc.Gen.u1Present)
2515	ADD_STR(psz, "Present ");
2516	else
2517	ADD_STR(psz, "Not-Present ");
2518	if (Desc.Gen.u1Granularity)
2519	ADD_STR(psz, "Page ");
2520	if (Desc.Gen.u1DefBig)
2521	ADD_STR(psz, "32-bit ");
2522	else
2523	ADD_STR(psz, "16-bit ");
2524	#undef ADD_STR
2525	*psz = '\0';
2526
2527	/*
2528	* Limit and Base and format the output.
2529	*/
2530	uint32_t u32Limit = X86DESC_LIMIT_G(&Desc);
2531	uint32_t u32Base = X86DESC_BASE(&Desc);
2532
2533	RTStrPrintf(pszOutput, cchOutput, "%04x - %08x %08x - base=%08x limit=%08x dpl=%d %s",
2534	Sel, Desc.au32[0], Desc.au32[1], u32Base, u32Limit, Desc.Gen.u2Dpl, szMsg);
2535	}
2536
2537
2538	/**
2539	* Dumps a descriptor.
2540	*
2541	* @param Desc Descriptor to dump.
2542	* @param Sel Selector number.
2543	* @param pszMsg Message to prepend the log entry with.
2544	*/
2545	VMMR3DECL(void) SELMR3DumpDescriptor(X86DESC Desc, RTSEL Sel, const char *pszMsg)
2546	{
2547	char szOutput[128];
2548	selmR3FormatDescriptor(Desc, Sel, &szOutput[0], sizeof(szOutput));
2549	Log(("%s: %s\n", pszMsg, szOutput));
2550	NOREF(szOutput[0]);
2551	}
2552
2553
2554	/**
2555	* Display the shadow gdt.
2556	*
2557	* @param pVM Pointer to the VM.
2558	* @param pHlp The info helpers.
2559	* @param pszArgs Arguments, ignored.
2560	*/
2561	static DECLCALLBACK(void) selmR3InfoGdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2562	{
2563	NOREF(pszArgs);
2564	pHlp->pfnPrintf(pHlp, "Shadow GDT (GCAddr=%RRv):\n", MMHyperR3ToRC(pVM, pVM->selm.s.paGdtR3));
2565	for (unsigned iGDT = 0; iGDT < SELM_GDT_ELEMENTS; iGDT++)
2566	{
2567	if (pVM->selm.s.paGdtR3[iGDT].Gen.u1Present)
2568	{
2569	char szOutput[128];
2570	selmR3FormatDescriptor(pVM->selm.s.paGdtR3[iGDT], iGDT << X86_SEL_SHIFT, &szOutput[0], sizeof(szOutput));
2571	const char *psz = "";
2572	if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] >> X86_SEL_SHIFT))
2573	psz = " HyperCS";
2574	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] >> X86_SEL_SHIFT))
2575	psz = " HyperDS";
2576	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] >> X86_SEL_SHIFT))
2577	psz = " HyperCS64";
2578	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> X86_SEL_SHIFT))
2579	psz = " HyperTSS";
2580	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> X86_SEL_SHIFT))
2581	psz = " HyperTSSTrap08";
2582	pHlp->pfnPrintf(pHlp, "%s%s\n", szOutput, psz);
2583	}
2584	}
2585	}
2586
2587
2588	/**
2589	* Display the guest gdt.
2590	*
2591	* @param pVM Pointer to the VM.
2592	* @param pHlp The info helpers.
2593	* @param pszArgs Arguments, ignored.
2594	*/
2595	static DECLCALLBACK(void) selmR3InfoGdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2596	{
2597	/** @todo SMP support! */
2598	PVMCPU pVCpu = &pVM->aCpus[0];
2599
2600	VBOXGDTR GDTR;
2601	CPUMGetGuestGDTR(pVCpu, &GDTR);
2602	RTGCPTR GCPtrGDT = GDTR.pGdt;
2603	unsigned cGDTs = ((unsigned)GDTR.cbGdt + 1) / sizeof(X86DESC);
2604
2605	pHlp->pfnPrintf(pHlp, "Guest GDT (GCAddr=%RGv limit=%x):\n", GCPtrGDT, GDTR.cbGdt);
2606	for (unsigned iGDT = 0; iGDT < cGDTs; iGDT++, GCPtrGDT += sizeof(X86DESC))
2607	{
2608	X86DESC GDTE;
2609	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GDTE, GCPtrGDT, sizeof(GDTE));
2610	if (RT_SUCCESS(rc))
2611	{
2612	if (GDTE.Gen.u1Present)
2613	{
2614	char szOutput[128];
2615	selmR3FormatDescriptor(GDTE, iGDT << X86_SEL_SHIFT, &szOutput[0], sizeof(szOutput));
2616	pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2617	}
2618	}
2619	else if (rc == VERR_PAGE_NOT_PRESENT)
2620	{
2621	if ((GCPtrGDT & PAGE_OFFSET_MASK) + sizeof(X86DESC) - 1 < sizeof(X86DESC))
2622	pHlp->pfnPrintf(pHlp, "%04x - page not present (GCAddr=%RGv)\n", iGDT << X86_SEL_SHIFT, GCPtrGDT);
2623	}
2624	else
2625	pHlp->pfnPrintf(pHlp, "%04x - read error rc=%Rrc GCAddr=%RGv\n", iGDT << X86_SEL_SHIFT, rc, GCPtrGDT);
2626	}
2627	NOREF(pszArgs);
2628	}
2629
2630
2631	/**
2632	* Display the shadow ldt.
2633	*
2634	* @param pVM Pointer to the VM.
2635	* @param pHlp The info helpers.
2636	* @param pszArgs Arguments, ignored.
2637	*/
2638	static DECLCALLBACK(void) selmR3InfoLdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2639	{
2640	unsigned cLDTs = ((unsigned)pVM->selm.s.cbLdtLimit + 1) >> X86_SEL_SHIFT;
2641	PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper);
2642	pHlp->pfnPrintf(pHlp, "Shadow LDT (GCAddr=%RRv limit=%#x):\n", pVM->selm.s.pvLdtRC + pVM->selm.s.offLdtHyper, pVM->selm.s.cbLdtLimit);
2643	for (unsigned iLDT = 0; iLDT < cLDTs; iLDT++)
2644	{
2645	if (paLDT[iLDT].Gen.u1Present)
2646	{
2647	char szOutput[128];
2648	selmR3FormatDescriptor(paLDT[iLDT], (iLDT << X86_SEL_SHIFT) \| X86_SEL_LDT, &szOutput[0], sizeof(szOutput));
2649	pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2650	}
2651	}
2652	NOREF(pszArgs);
2653	}
2654
2655
2656	/**
2657	* Display the guest ldt.
2658	*
2659	* @param pVM Pointer to the VM.
2660	* @param pHlp The info helpers.
2661	* @param pszArgs Arguments, ignored.
2662	*/
2663	static DECLCALLBACK(void) selmR3InfoLdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2664	{
2665	/** @todo SMP support! */
2666	PVMCPU pVCpu = &pVM->aCpus[0];
2667
2668	uint64_t GCPtrLdt;
2669	uint32_t cbLdt;
2670	RTSEL SelLdt = CPUMGetGuestLdtrEx(pVCpu, &GCPtrLdt, &cbLdt);
2671	if (!(SelLdt & X86_SEL_MASK_OFF_RPL))
2672	{
2673	pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x): Null-Selector\n", SelLdt);
2674	return;
2675	}
2676
2677	pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x GCAddr=%RX64 limit=%x):\n", SelLdt, GCPtrLdt, cbLdt);
2678	unsigned cLdts = (cbLdt + 1) >> X86_SEL_SHIFT;
2679	for (unsigned iLdt = 0; iLdt < cLdts; iLdt++, GCPtrLdt += sizeof(X86DESC))
2680	{
2681	X86DESC LdtE;
2682	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &LdtE, GCPtrLdt, sizeof(LdtE));
2683	if (RT_SUCCESS(rc))
2684	{
2685	if (LdtE.Gen.u1Present)
2686	{
2687	char szOutput[128];
2688	selmR3FormatDescriptor(LdtE, (iLdt << X86_SEL_SHIFT) \| X86_SEL_LDT, &szOutput[0], sizeof(szOutput));
2689	pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2690	}
2691	}
2692	else if (rc == VERR_PAGE_NOT_PRESENT)
2693	{
2694	if ((GCPtrLdt & PAGE_OFFSET_MASK) + sizeof(X86DESC) - 1 < sizeof(X86DESC))
2695	pHlp->pfnPrintf(pHlp, "%04x - page not present (GCAddr=%RGv)\n", (iLdt << X86_SEL_SHIFT) \| X86_SEL_LDT, GCPtrLdt);
2696	}
2697	else
2698	pHlp->pfnPrintf(pHlp, "%04x - read error rc=%Rrc GCAddr=%RGv\n", (iLdt << X86_SEL_SHIFT) \| X86_SEL_LDT, rc, GCPtrLdt);
2699	}
2700	NOREF(pszArgs);
2701	}
2702
2703
2704	/**
2705	* Dumps the hypervisor GDT
2706	*
2707	* @param pVM Pointer to the VM.
2708	*/
2709	VMMR3DECL(void) SELMR3DumpHyperGDT(PVM pVM)
2710	{
2711	DBGFR3Info(pVM->pUVM, "gdt", NULL, NULL);
2712	}
2713
2714
2715	/**
2716	* Dumps the hypervisor LDT
2717	*
2718	* @param pVM Pointer to the VM.
2719	*/
2720	VMMR3DECL(void) SELMR3DumpHyperLDT(PVM pVM)
2721	{
2722	DBGFR3Info(pVM->pUVM, "ldt", NULL, NULL);
2723	}
2724
2725
2726	/**
2727	* Dumps the guest GDT
2728	*
2729	* @param pVM Pointer to the VM.
2730	*/
2731	VMMR3DECL(void) SELMR3DumpGuestGDT(PVM pVM)
2732	{
2733	DBGFR3Info(pVM->pUVM, "gdtguest", NULL, NULL);
2734	}
2735
2736
2737	/**
2738	* Dumps the guest LDT
2739	*
2740	* @param pVM Pointer to the VM.
2741	*/
2742	VMMR3DECL(void) SELMR3DumpGuestLDT(PVM pVM)
2743	{
2744	DBGFR3Info(pVM->pUVM, "ldtguest", NULL, NULL);
2745	}
2746

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source: vbox/trunk/src/VBox/VMM/VMMR3/SELM.cpp@ 45705

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