PGMSavedState.cpp@ 38838

最後變更在這個檔案從38838是 38707,由 vboxsync 提交於 14 年前
VMM/VT-x: Fix for PAE guests running on 32-bit hosts or 64-bit hosts where VBoxInternal/PGM/MaxRing3Chunks is used.
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1	/* $Id: PGMSavedState.cpp 38707 2011-09-09 14:10:18Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor, The Saved State Part.
4	*/
5
6	/*
7	* Copyright (C) 2006-2009 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.alldomusa.eu.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_PGM
23	#include <VBox/vmm/pgm.h>
24	#include <VBox/vmm/stam.h>
25	#include <VBox/vmm/ssm.h>
26	#include <VBox/vmm/pdmdrv.h>
27	#include <VBox/vmm/pdmdev.h>
28	#include "PGMInternal.h"
29	#include <VBox/vmm/vm.h>
30	#include "PGMInline.h"
31
32	#include <VBox/param.h>
33	#include <VBox/err.h>
34	#include <VBox/vmm/ftm.h>
35
36	#include <iprt/asm.h>
37	#include <iprt/assert.h>
38	#include <iprt/crc.h>
39	#include <iprt/mem.h>
40	#include <iprt/sha.h>
41	#include <iprt/string.h>
42	#include <iprt/thread.h>
43
44
45	/*******************************************************************************
46	* Defined Constants And Macros *
47	*******************************************************************************/
48	/** Saved state data unit version. */
49	#define PGM_SAVED_STATE_VERSION 14
50	/** Saved state data unit version before the PAE PDPE registers. */
51	#define PGM_SAVED_STATE_VERSION_PRE_PAE 13
52	/** Saved state data unit version after this includes ballooned page flags in
53	* the state (see #5515). */
54	#define PGM_SAVED_STATE_VERSION_BALLOON_BROKEN 12
55	/** Saved state before the balloon change. */
56	#define PGM_SAVED_STATE_VERSION_PRE_BALLOON 11
57	/** Saved state data unit version used during 3.1 development, misses the RAM
58	* config. */
59	#define PGM_SAVED_STATE_VERSION_NO_RAM_CFG 10
60	/** Saved state data unit version for 3.0 (pre teleportation). */
61	#define PGM_SAVED_STATE_VERSION_3_0_0 9
62	/** Saved state data unit version for 2.2.2 and later. */
63	#define PGM_SAVED_STATE_VERSION_2_2_2 8
64	/** Saved state data unit version for 2.2.0. */
65	#define PGM_SAVED_STATE_VERSION_RR_DESC 7
66	/** Saved state data unit version. */
67	#define PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE 6
68
69
70	/** @name Sparse state record types
71	* @{ */
72	/** Zero page. No data. */
73	#define PGM_STATE_REC_RAM_ZERO UINT8_C(0x00)
74	/** Raw page. */
75	#define PGM_STATE_REC_RAM_RAW UINT8_C(0x01)
76	/** Raw MMIO2 page. */
77	#define PGM_STATE_REC_MMIO2_RAW UINT8_C(0x02)
78	/** Zero MMIO2 page. */
79	#define PGM_STATE_REC_MMIO2_ZERO UINT8_C(0x03)
80	/** Virgin ROM page. Followed by protection (8-bit) and the raw bits. */
81	#define PGM_STATE_REC_ROM_VIRGIN UINT8_C(0x04)
82	/** Raw shadowed ROM page. The protection (8-bit) precedes the raw bits. */
83	#define PGM_STATE_REC_ROM_SHW_RAW UINT8_C(0x05)
84	/** Zero shadowed ROM page. The protection (8-bit) is the only payload. */
85	#define PGM_STATE_REC_ROM_SHW_ZERO UINT8_C(0x06)
86	/** ROM protection (8-bit). */
87	#define PGM_STATE_REC_ROM_PROT UINT8_C(0x07)
88	/** Ballooned page. No data. */
89	#define PGM_STATE_REC_RAM_BALLOONED UINT8_C(0x08)
90	/** The last record type. */
91	#define PGM_STATE_REC_LAST PGM_STATE_REC_RAM_BALLOONED
92	/** End marker. */
93	#define PGM_STATE_REC_END UINT8_C(0xff)
94	/** Flag indicating that the data is preceded by the page address.
95	* For RAW pages this is a RTGCPHYS. For MMIO2 and ROM pages this is a 8-bit
96	* range ID and a 32-bit page index.
97	*/
98	#define PGM_STATE_REC_FLAG_ADDR UINT8_C(0x80)
99	/** @} */
100
101	/** The CRC-32 for a zero page. */
102	#define PGM_STATE_CRC32_ZERO_PAGE UINT32_C(0xc71c0011)
103	/** The CRC-32 for a zero half page. */
104	#define PGM_STATE_CRC32_ZERO_HALF_PAGE UINT32_C(0xf1e8ba9e)
105
106
107	/*******************************************************************************
108	* Structures and Typedefs *
109	*******************************************************************************/
110	/** For loading old saved states. (pre-smp) */
111	typedef struct
112	{
113	/** If set no conflict checks are required. (boolean) */
114	bool fMappingsFixed;
115	/** Size of fixed mapping */
116	uint32_t cbMappingFixed;
117	/** Base address (GC) of fixed mapping */
118	RTGCPTR GCPtrMappingFixed;
119	/** A20 gate mask.
120	* Our current approach to A20 emulation is to let REM do it and don't bother
121	* anywhere else. The interesting guests will be operating with it enabled anyway.
122	* But should the need arise, we'll subject physical addresses to this mask. */
123	RTGCPHYS GCPhysA20Mask;
124	/** A20 gate state - boolean! */
125	bool fA20Enabled;
126	/** The guest paging mode. */
127	PGMMODE enmGuestMode;
128	} PGMOLD;
129
130
131	/*******************************************************************************
132	* Global Variables *
133	*******************************************************************************/
134	/** PGM fields to save/load. */
135
136	static const SSMFIELD s_aPGMFields[] =
137	{
138	SSMFIELD_ENTRY( PGM, fMappingsFixed),
139	SSMFIELD_ENTRY_GCPTR( PGM, GCPtrMappingFixed),
140	SSMFIELD_ENTRY( PGM, cbMappingFixed),
141	SSMFIELD_ENTRY( PGM, cBalloonedPages),
142	SSMFIELD_ENTRY_TERM()
143	};
144
145	static const SSMFIELD s_aPGMFieldsPreBalloon[] =
146	{
147	SSMFIELD_ENTRY( PGM, fMappingsFixed),
148	SSMFIELD_ENTRY_GCPTR( PGM, GCPtrMappingFixed),
149	SSMFIELD_ENTRY( PGM, cbMappingFixed),
150	SSMFIELD_ENTRY_TERM()
151	};
152
153	static const SSMFIELD s_aPGMCpuFields[] =
154	{
155	SSMFIELD_ENTRY( PGMCPU, fA20Enabled),
156	SSMFIELD_ENTRY_GCPHYS( PGMCPU, GCPhysA20Mask),
157	SSMFIELD_ENTRY( PGMCPU, enmGuestMode),
158	SSMFIELD_ENTRY( PGMCPU, aGCPhysGstPaePDs[0]),
159	SSMFIELD_ENTRY( PGMCPU, aGCPhysGstPaePDs[1]),
160	SSMFIELD_ENTRY( PGMCPU, aGCPhysGstPaePDs[2]),
161	SSMFIELD_ENTRY( PGMCPU, aGCPhysGstPaePDs[3]),
162	SSMFIELD_ENTRY_TERM()
163	};
164
165	static const SSMFIELD s_aPGMCpuFieldsPrePae[] =
166	{
167	SSMFIELD_ENTRY( PGMCPU, fA20Enabled),
168	SSMFIELD_ENTRY_GCPHYS( PGMCPU, GCPhysA20Mask),
169	SSMFIELD_ENTRY( PGMCPU, enmGuestMode),
170	SSMFIELD_ENTRY_TERM()
171	};
172
173	static const SSMFIELD s_aPGMFields_Old[] =
174	{
175	SSMFIELD_ENTRY( PGMOLD, fMappingsFixed),
176	SSMFIELD_ENTRY_GCPTR( PGMOLD, GCPtrMappingFixed),
177	SSMFIELD_ENTRY( PGMOLD, cbMappingFixed),
178	SSMFIELD_ENTRY( PGMOLD, fA20Enabled),
179	SSMFIELD_ENTRY_GCPHYS( PGMOLD, GCPhysA20Mask),
180	SSMFIELD_ENTRY( PGMOLD, enmGuestMode),
181	SSMFIELD_ENTRY_TERM()
182	};
183
184
185	/**
186	* Find the ROM tracking structure for the given page.
187	*
188	* @returns Pointer to the ROM page structure. NULL if the caller didn't check
189	* that it's a ROM page.
190	* @param pVM The VM handle.
191	* @param GCPhys The address of the ROM page.
192	*/
193	static PPGMROMPAGE pgmR3GetRomPage(PVM pVM, RTGCPHYS GCPhys) /** @todo change this to take a hint. */
194	{
195	for (PPGMROMRANGE pRomRange = pVM->pgm.s.CTX_SUFF(pRomRanges);
196	pRomRange;
197	pRomRange = pRomRange->CTX_SUFF(pNext))
198	{
199	RTGCPHYS off = GCPhys - pRomRange->GCPhys;
200	if (GCPhys - pRomRange->GCPhys < pRomRange->cb)
201	return &pRomRange->aPages[off >> PAGE_SHIFT];
202	}
203	return NULL;
204	}
205
206
207	/**
208	* Prepares the ROM pages for a live save.
209	*
210	* @returns VBox status code.
211	* @param pVM The VM handle.
212	*/
213	static int pgmR3PrepRomPages(PVM pVM)
214	{
215	/*
216	* Initialize the live save tracking in the ROM page descriptors.
217	*/
218	pgmLock(pVM);
219	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
220	{
221	PPGMRAMRANGE pRamHint = NULL;;
222	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
223
224	for (uint32_t iPage = 0; iPage < cPages; iPage++)
225	{
226	pRom->aPages[iPage].LiveSave.u8Prot = (uint8_t)PGMROMPROT_INVALID;
227	pRom->aPages[iPage].LiveSave.fWrittenTo = false;
228	pRom->aPages[iPage].LiveSave.fDirty = true;
229	pRom->aPages[iPage].LiveSave.fDirtiedRecently = true;
230	if (!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED))
231	{
232	if (PGMROMPROT_IS_ROM(pRom->aPages[iPage].enmProt))
233	pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow) && !PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow);
234	else
235	{
236	RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
237	PPGMPAGE pPage;
238	int rc = pgmPhysGetPageWithHintEx(pVM, GCPhys, &pPage, &pRamHint);
239	AssertLogRelMsgRC(rc, ("%Rrc GCPhys=%RGp\n", rc, GCPhys));
240	if (RT_SUCCESS(rc))
241	pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(pPage) && !PGM_PAGE_IS_BALLOONED(pPage);
242	else
243	pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow) && !PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow);
244	}
245	}
246	}
247
248	pVM->pgm.s.LiveSave.Rom.cDirtyPages += cPages;
249	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
250	pVM->pgm.s.LiveSave.Rom.cDirtyPages += cPages;
251	}
252	pgmUnlock(pVM);
253
254	return VINF_SUCCESS;
255	}
256
257
258	/**
259	* Assigns IDs to the ROM ranges and saves them.
260	*
261	* @returns VBox status code.
262	* @param pVM The VM handle.
263	* @param pSSM Saved state handle.
264	*/
265	static int pgmR3SaveRomRanges(PVM pVM, PSSMHANDLE pSSM)
266	{
267	pgmLock(pVM);
268	uint8_t id = 1;
269	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3, id++)
270	{
271	pRom->idSavedState = id;
272	SSMR3PutU8(pSSM, id);
273	SSMR3PutStrZ(pSSM, ""); /* device name */
274	SSMR3PutU32(pSSM, 0); /* device instance */
275	SSMR3PutU8(pSSM, 0); /* region */
276	SSMR3PutStrZ(pSSM, pRom->pszDesc);
277	SSMR3PutGCPhys(pSSM, pRom->GCPhys);
278	int rc = SSMR3PutGCPhys(pSSM, pRom->cb);
279	if (RT_FAILURE(rc))
280	break;
281	}
282	pgmUnlock(pVM);
283	return SSMR3PutU8(pSSM, UINT8_MAX);
284	}
285
286
287	/**
288	* Loads the ROM range ID assignments.
289	*
290	* @returns VBox status code.
291	*
292	* @param pVM The VM handle.
293	* @param pSSM The saved state handle.
294	*/
295	static int pgmR3LoadRomRanges(PVM pVM, PSSMHANDLE pSSM)
296	{
297	PGM_LOCK_ASSERT_OWNER(pVM);
298
299	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
300	pRom->idSavedState = UINT8_MAX;
301
302	for (;;)
303	{
304	/*
305	* Read the data.
306	*/
307	uint8_t id;
308	int rc = SSMR3GetU8(pSSM, &id);
309	if (RT_FAILURE(rc))
310	return rc;
311	if (id == UINT8_MAX)
312	{
313	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
314	AssertLogRelMsg(pRom->idSavedState != UINT8_MAX,
315	("The \"%s\" ROM was not found in the saved state. Probably due to some misconfiguration\n",
316	pRom->pszDesc));
317	return VINF_SUCCESS; /* the end */
318	}
319	AssertLogRelReturn(id != 0, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
320
321	char szDevName[RT_SIZEOFMEMB(PDMDEVREG, szName)];
322	rc = SSMR3GetStrZ(pSSM, szDevName, sizeof(szDevName));
323	AssertLogRelRCReturn(rc, rc);
324
325	uint32_t uInstance;
326	SSMR3GetU32(pSSM, &uInstance);
327	uint8_t iRegion;
328	SSMR3GetU8(pSSM, &iRegion);
329
330	char szDesc[64];
331	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
332	AssertLogRelRCReturn(rc, rc);
333
334	RTGCPHYS GCPhys;
335	SSMR3GetGCPhys(pSSM, &GCPhys);
336	RTGCPHYS cb;
337	rc = SSMR3GetGCPhys(pSSM, &cb);
338	if (RT_FAILURE(rc))
339	return rc;
340	AssertLogRelMsgReturn(!(GCPhys & PAGE_OFFSET_MASK), ("GCPhys=%RGp %s\n", GCPhys, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
341	AssertLogRelMsgReturn(!(cb & PAGE_OFFSET_MASK), ("cb=%RGp %s\n", cb, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
342
343	/*
344	* Locate a matching ROM range.
345	*/
346	AssertLogRelMsgReturn( uInstance == 0
347	&& iRegion == 0
348	&& szDevName[0] == '\0',
349	("GCPhys=%RGp %s\n", GCPhys, szDesc),
350	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
351	PPGMROMRANGE pRom;
352	for (pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
353	{
354	if ( pRom->idSavedState == UINT8_MAX
355	&& !strcmp(pRom->pszDesc, szDesc))
356	{
357	pRom->idSavedState = id;
358	break;
359	}
360	}
361	if (!pRom)
362	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("ROM at %RGp by the name '%s' was not found"), GCPhys, szDesc);
363	} /* forever */
364	}
365
366
367	/**
368	* Scan ROM pages.
369	*
370	* @param pVM The VM handle.
371	*/
372	static void pgmR3ScanRomPages(PVM pVM)
373	{
374	/*
375	* The shadow ROMs.
376	*/
377	pgmLock(pVM);
378	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
379	{
380	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
381	{
382	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
383	for (uint32_t iPage = 0; iPage < cPages; iPage++)
384	{
385	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
386	if (pRomPage->LiveSave.fWrittenTo)
387	{
388	pRomPage->LiveSave.fWrittenTo = false;
389	if (!pRomPage->LiveSave.fDirty)
390	{
391	pRomPage->LiveSave.fDirty = true;
392	pVM->pgm.s.LiveSave.Rom.cReadyPages--;
393	pVM->pgm.s.LiveSave.Rom.cDirtyPages++;
394	}
395	pRomPage->LiveSave.fDirtiedRecently = true;
396	}
397	else
398	pRomPage->LiveSave.fDirtiedRecently = false;
399	}
400	}
401	}
402	pgmUnlock(pVM);
403	}
404
405
406	/**
407	* Takes care of the virgin ROM pages in the first pass.
408	*
409	* This is an attempt at simplifying the handling of ROM pages a little bit.
410	* This ASSUMES that no new ROM ranges will be added and that they won't be
411	* relinked in any way.
412	*
413	* @param pVM The VM handle.
414	* @param pSSM The SSM handle.
415	* @param fLiveSave Whether we're in a live save or not.
416	*/
417	static int pgmR3SaveRomVirginPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave)
418	{
419	if (FTMIsDeltaLoadSaveActive(pVM))
420	return VINF_SUCCESS; /* nothing to do as nothing has changed here */
421
422	pgmLock(pVM);
423	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
424	{
425	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
426	for (uint32_t iPage = 0; iPage < cPages; iPage++)
427	{
428	RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
429	PGMROMPROT enmProt = pRom->aPages[iPage].enmProt;
430
431	/* Get the virgin page descriptor. */
432	PPGMPAGE pPage;
433	if (PGMROMPROT_IS_ROM(enmProt))
434	pPage = pgmPhysGetPage(pVM, GCPhys);
435	else
436	pPage = &pRom->aPages[iPage].Virgin;
437
438	/* Get the page bits. (Cannot use pgmPhysGCPhys2CCPtrInternalReadOnly here!) */
439	int rc = VINF_SUCCESS;
440	char abPage[PAGE_SIZE];
441	if ( !PGM_PAGE_IS_ZERO(pPage)
442	&& !PGM_PAGE_IS_BALLOONED(pPage))
443	{
444	void const *pvPage;
445	rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhys, &pvPage);
446	if (RT_SUCCESS(rc))
447	memcpy(abPage, pvPage, PAGE_SIZE);
448	}
449	else
450	ASMMemZeroPage(abPage);
451	pgmUnlock(pVM);
452	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
453
454	/* Save it. */
455	if (iPage > 0)
456	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_VIRGIN);
457	else
458	{
459	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_VIRGIN \| PGM_STATE_REC_FLAG_ADDR);
460	SSMR3PutU8(pSSM, pRom->idSavedState);
461	SSMR3PutU32(pSSM, iPage);
462	}
463	SSMR3PutU8(pSSM, (uint8_t)enmProt);
464	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
465	if (RT_FAILURE(rc))
466	return rc;
467
468	/* Update state. */
469	pgmLock(pVM);
470	pRom->aPages[iPage].LiveSave.u8Prot = (uint8_t)enmProt;
471	if (fLiveSave)
472	{
473	pVM->pgm.s.LiveSave.Rom.cDirtyPages--;
474	pVM->pgm.s.LiveSave.Rom.cReadyPages++;
475	pVM->pgm.s.LiveSave.cSavedPages++;
476	}
477	}
478	}
479	pgmUnlock(pVM);
480	return VINF_SUCCESS;
481	}
482
483
484	/**
485	* Saves dirty pages in the shadowed ROM ranges.
486	*
487	* Used by pgmR3LiveExecPart2 and pgmR3SaveExecMemory.
488	*
489	* @returns VBox status code.
490	* @param pVM The VM handle.
491	* @param pSSM The SSM handle.
492	* @param fLiveSave Whether it's a live save or not.
493	* @param fFinalPass Whether this is the final pass or not.
494	*/
495	static int pgmR3SaveShadowedRomPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, bool fFinalPass)
496	{
497	if (FTMIsDeltaLoadSaveActive(pVM))
498	return VINF_SUCCESS; /* nothing to do as we deal with those pages separately */
499
500	/*
501	* The Shadowed ROMs.
502	*
503	* ASSUMES that the ROM ranges are fixed.
504	* ASSUMES that all the ROM ranges are mapped.
505	*/
506	pgmLock(pVM);
507	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
508	{
509	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
510	{
511	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
512	uint32_t iPrevPage = cPages;
513	for (uint32_t iPage = 0; iPage < cPages; iPage++)
514	{
515	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
516	if ( !fLiveSave
517	\|\| ( pRomPage->LiveSave.fDirty
518	&& ( ( !pRomPage->LiveSave.fDirtiedRecently
519	&& !pRomPage->LiveSave.fWrittenTo)
520	\|\| fFinalPass
521	)
522	)
523	)
524	{
525	uint8_t abPage[PAGE_SIZE];
526	PGMROMPROT enmProt = pRomPage->enmProt;
527	RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
528	PPGMPAGE pPage = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : pgmPhysGetPage(pVM, GCPhys);
529	bool fZero = PGM_PAGE_IS_ZERO(pPage) \|\| PGM_PAGE_IS_BALLOONED(pPage); Assert(!PGM_PAGE_IS_BALLOONED(pPage)); /* Shouldn't be ballooned. */
530	int rc = VINF_SUCCESS;
531	if (!fZero)
532	{
533	void const *pvPage;
534	rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhys, &pvPage);
535	if (RT_SUCCESS(rc))
536	memcpy(abPage, pvPage, PAGE_SIZE);
537	}
538	if (fLiveSave && RT_SUCCESS(rc))
539	{
540	pRomPage->LiveSave.u8Prot = (uint8_t)enmProt;
541	pRomPage->LiveSave.fDirty = false;
542	pVM->pgm.s.LiveSave.Rom.cReadyPages++;
543	pVM->pgm.s.LiveSave.Rom.cDirtyPages--;
544	pVM->pgm.s.LiveSave.cSavedPages++;
545	}
546	pgmUnlock(pVM);
547	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
548
549	if (iPage - 1U == iPrevPage && iPage > 0)
550	SSMR3PutU8(pSSM, (fZero ? PGM_STATE_REC_ROM_SHW_ZERO : PGM_STATE_REC_ROM_SHW_RAW));
551	else
552	{
553	SSMR3PutU8(pSSM, (fZero ? PGM_STATE_REC_ROM_SHW_ZERO : PGM_STATE_REC_ROM_SHW_RAW) \| PGM_STATE_REC_FLAG_ADDR);
554	SSMR3PutU8(pSSM, pRom->idSavedState);
555	SSMR3PutU32(pSSM, iPage);
556	}
557	rc = SSMR3PutU8(pSSM, (uint8_t)enmProt);
558	if (!fZero)
559	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
560	if (RT_FAILURE(rc))
561	return rc;
562
563	pgmLock(pVM);
564	iPrevPage = iPage;
565	}
566	/*
567	* In the final pass, make sure the protection is in sync.
568	*/
569	else if ( fFinalPass
570	&& pRomPage->LiveSave.u8Prot != pRomPage->enmProt)
571	{
572	PGMROMPROT enmProt = pRomPage->enmProt;
573	pRomPage->LiveSave.u8Prot = (uint8_t)enmProt;
574	pgmUnlock(pVM);
575
576	if (iPage - 1U == iPrevPage && iPage > 0)
577	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_PROT);
578	else
579	{
580	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_PROT \| PGM_STATE_REC_FLAG_ADDR);
581	SSMR3PutU8(pSSM, pRom->idSavedState);
582	SSMR3PutU32(pSSM, iPage);
583	}
584	int rc = SSMR3PutU8(pSSM, (uint8_t)enmProt);
585	if (RT_FAILURE(rc))
586	return rc;
587
588	pgmLock(pVM);
589	iPrevPage = iPage;
590	}
591	}
592	}
593	}
594	pgmUnlock(pVM);
595	return VINF_SUCCESS;
596	}
597
598
599	/**
600	* Cleans up ROM pages after a live save.
601	*
602	* @param pVM The VM handle.
603	*/
604	static void pgmR3DoneRomPages(PVM pVM)
605	{
606	NOREF(pVM);
607	}
608
609
610	/**
611	* Prepares the MMIO2 pages for a live save.
612	*
613	* @returns VBox status code.
614	* @param pVM The VM handle.
615	*/
616	static int pgmR3PrepMmio2Pages(PVM pVM)
617	{
618	/*
619	* Initialize the live save tracking in the MMIO2 ranges.
620	* ASSUME nothing changes here.
621	*/
622	pgmLock(pVM);
623	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
624	{
625	uint32_t const cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
626	pgmUnlock(pVM);
627
628	PPGMLIVESAVEMMIO2PAGE paLSPages = (PPGMLIVESAVEMMIO2PAGE)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMLIVESAVEMMIO2PAGE) * cPages);
629	if (!paLSPages)
630	return VERR_NO_MEMORY;
631	for (uint32_t iPage = 0; iPage < cPages; iPage++)
632	{
633	/* Initialize it as a dirty zero page. */
634	paLSPages[iPage].fDirty = true;
635	paLSPages[iPage].cUnchangedScans = 0;
636	paLSPages[iPage].fZero = true;
637	paLSPages[iPage].u32CrcH1 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
638	paLSPages[iPage].u32CrcH2 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
639	}
640
641	pgmLock(pVM);
642	pMmio2->paLSPages = paLSPages;
643	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages += cPages;
644	}
645	pgmUnlock(pVM);
646	return VINF_SUCCESS;
647	}
648
649
650	/**
651	* Assigns IDs to the MMIO2 ranges and saves them.
652	*
653	* @returns VBox status code.
654	* @param pVM The VM handle.
655	* @param pSSM Saved state handle.
656	*/
657	static int pgmR3SaveMmio2Ranges(PVM pVM, PSSMHANDLE pSSM)
658	{
659	pgmLock(pVM);
660	uint8_t id = 1;
661	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3, id++)
662	{
663	pMmio2->idSavedState = id;
664	SSMR3PutU8(pSSM, id);
665	SSMR3PutStrZ(pSSM, pMmio2->pDevInsR3->pReg->szName);
666	SSMR3PutU32(pSSM, pMmio2->pDevInsR3->iInstance);
667	SSMR3PutU8(pSSM, pMmio2->iRegion);
668	SSMR3PutStrZ(pSSM, pMmio2->RamRange.pszDesc);
669	int rc = SSMR3PutGCPhys(pSSM, pMmio2->RamRange.cb);
670	if (RT_FAILURE(rc))
671	break;
672	}
673	pgmUnlock(pVM);
674	return SSMR3PutU8(pSSM, UINT8_MAX);
675	}
676
677
678	/**
679	* Loads the MMIO2 range ID assignments.
680	*
681	* @returns VBox status code.
682	*
683	* @param pVM The VM handle.
684	* @param pSSM The saved state handle.
685	*/
686	static int pgmR3LoadMmio2Ranges(PVM pVM, PSSMHANDLE pSSM)
687	{
688	PGM_LOCK_ASSERT_OWNER(pVM);
689
690	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
691	pMmio2->idSavedState = UINT8_MAX;
692
693	for (;;)
694	{
695	/*
696	* Read the data.
697	*/
698	uint8_t id;
699	int rc = SSMR3GetU8(pSSM, &id);
700	if (RT_FAILURE(rc))
701	return rc;
702	if (id == UINT8_MAX)
703	{
704	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
705	AssertLogRelMsg(pMmio2->idSavedState != UINT8_MAX, ("%s\n", pMmio2->RamRange.pszDesc));
706	return VINF_SUCCESS; /* the end */
707	}
708	AssertLogRelReturn(id != 0, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
709
710	char szDevName[RT_SIZEOFMEMB(PDMDEVREG, szName)];
711	rc = SSMR3GetStrZ(pSSM, szDevName, sizeof(szDevName));
712	AssertLogRelRCReturn(rc, rc);
713
714	uint32_t uInstance;
715	SSMR3GetU32(pSSM, &uInstance);
716	uint8_t iRegion;
717	SSMR3GetU8(pSSM, &iRegion);
718
719	char szDesc[64];
720	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
721	AssertLogRelRCReturn(rc, rc);
722
723	RTGCPHYS cb;
724	rc = SSMR3GetGCPhys(pSSM, &cb);
725	AssertLogRelMsgReturn(!(cb & PAGE_OFFSET_MASK), ("cb=%RGp %s\n", cb, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
726
727	/*
728	* Locate a matching MMIO2 range.
729	*/
730	PPGMMMIO2RANGE pMmio2;
731	for (pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
732	{
733	if ( pMmio2->idSavedState == UINT8_MAX
734	&& pMmio2->iRegion == iRegion
735	&& pMmio2->pDevInsR3->iInstance == uInstance
736	&& !strcmp(pMmio2->pDevInsR3->pReg->szName, szDevName))
737	{
738	pMmio2->idSavedState = id;
739	break;
740	}
741	}
742	if (!pMmio2)
743	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Failed to locate a MMIO2 range called '%s' owned by %s/%u, region %d"),
744	szDesc, szDevName, uInstance, iRegion);
745
746	/*
747	* Validate the configuration, the size of the MMIO2 region should be
748	* the same.
749	*/
750	if (cb != pMmio2->RamRange.cb)
751	{
752	LogRel(("PGM: MMIO2 region \"%s\" size mismatch: saved=%RGp config=%RGp\n",
753	pMmio2->RamRange.pszDesc, cb, pMmio2->RamRange.cb));
754	if (cb > pMmio2->RamRange.cb) /* bad idea? */
755	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("MMIO2 region \"%s\" size mismatch: saved=%RGp config=%RGp"),
756	pMmio2->RamRange.pszDesc, cb, pMmio2->RamRange.cb);
757	}
758	} /* forever */
759	}
760
761
762	/**
763	* Scans one MMIO2 page.
764	*
765	* @returns True if changed, false if unchanged.
766	*
767	* @param pVM The VM handle
768	* @param pbPage The page bits.
769	* @param pLSPage The live save tracking structure for the page.
770	*
771	*/
772	DECLINLINE(bool) pgmR3ScanMmio2Page(PVM pVM, uint8_t const *pbPage, PPGMLIVESAVEMMIO2PAGE pLSPage)
773	{
774	/*
775	* Special handling of zero pages.
776	*/
777	bool const fZero = pLSPage->fZero;
778	if (fZero)
779	{
780	if (ASMMemIsZeroPage(pbPage))
781	{
782	/* Not modified. */
783	if (pLSPage->fDirty)
784	pLSPage->cUnchangedScans++;
785	return false;
786	}
787
788	pLSPage->fZero = false;
789	pLSPage->u32CrcH1 = RTCrc32(pbPage, PAGE_SIZE / 2);
790	}
791	else
792	{
793	/*
794	* CRC the first half, if it doesn't match the page is dirty and
795	* we won't check the 2nd half (we'll do that next time).
796	*/
797	uint32_t u32CrcH1 = RTCrc32(pbPage, PAGE_SIZE / 2);
798	if (u32CrcH1 == pLSPage->u32CrcH1)
799	{
800	uint32_t u32CrcH2 = RTCrc32(pbPage + PAGE_SIZE / 2, PAGE_SIZE / 2);
801	if (u32CrcH2 == pLSPage->u32CrcH2)
802	{
803	/* Probably not modified. */
804	if (pLSPage->fDirty)
805	pLSPage->cUnchangedScans++;
806	return false;
807	}
808
809	pLSPage->u32CrcH2 = u32CrcH2;
810	}
811	else
812	{
813	pLSPage->u32CrcH1 = u32CrcH1;
814	if ( u32CrcH1 == PGM_STATE_CRC32_ZERO_HALF_PAGE
815	&& ASMMemIsZeroPage(pbPage))
816	{
817	pLSPage->u32CrcH2 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
818	pLSPage->fZero = true;
819	}
820	}
821	}
822
823	/* dirty page path */
824	pLSPage->cUnchangedScans = 0;
825	if (!pLSPage->fDirty)
826	{
827	pLSPage->fDirty = true;
828	pVM->pgm.s.LiveSave.Mmio2.cReadyPages--;
829	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages++;
830	if (fZero)
831	pVM->pgm.s.LiveSave.Mmio2.cZeroPages--;
832	}
833	return true;
834	}
835
836
837	/**
838	* Scan for MMIO2 page modifications.
839	*
840	* @param pVM The VM handle.
841	* @param uPass The pass number.
842	*/
843	static void pgmR3ScanMmio2Pages(PVM pVM, uint32_t uPass)
844	{
845	/*
846	* Since this is a bit expensive we lower the scan rate after a little while.
847	*/
848	if ( ( (uPass & 3) != 0
849	&& uPass > 10)
850	\|\| uPass == SSM_PASS_FINAL)
851	return;
852
853	pgmLock(pVM); /* paranoia */
854	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
855	{
856	PPGMLIVESAVEMMIO2PAGE paLSPages = pMmio2->paLSPages;
857	uint32_t cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
858	pgmUnlock(pVM);
859
860	for (uint32_t iPage = 0; iPage < cPages; iPage++)
861	{
862	uint8_t const pbPage = (uint8_t const )pMmio2->pvR3 + iPage * PAGE_SIZE;
863	pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]);
864	}
865
866	pgmLock(pVM);
867	}
868	pgmUnlock(pVM);
869
870	}
871
872
873	/**
874	* Save quiescent MMIO2 pages.
875	*
876	* @returns VBox status code.
877	* @param pVM The VM handle.
878	* @param pSSM The SSM handle.
879	* @param fLiveSave Whether it's a live save or not.
880	* @param uPass The pass number.
881	*/
882	static int pgmR3SaveMmio2Pages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, uint32_t uPass)
883	{
884	/** @todo implement live saving of MMIO2 pages. (Need some way of telling the
885	* device that we wish to know about changes.) */
886
887	int rc = VINF_SUCCESS;
888	if (uPass == SSM_PASS_FINAL)
889	{
890	/*
891	* The mop up round.
892	*/
893	pgmLock(pVM);
894	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3;
895	pMmio2 && RT_SUCCESS(rc);
896	pMmio2 = pMmio2->pNextR3)
897	{
898	PPGMLIVESAVEMMIO2PAGE paLSPages = pMmio2->paLSPages;
899	uint8_t const pbPage = (uint8_t const )pMmio2->RamRange.pvR3;
900	uint32_t cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
901	uint32_t iPageLast = cPages;
902	for (uint32_t iPage = 0; iPage < cPages; iPage++, pbPage += PAGE_SIZE)
903	{
904	uint8_t u8Type;
905	if (!fLiveSave)
906	u8Type = ASMMemIsZeroPage(pbPage) ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
907	else
908	{
909	/* Try figure if it's a clean page, compare the SHA-1 to be really sure. */
910	if ( !paLSPages[iPage].fDirty
911	&& !pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]))
912	{
913	if (paLSPages[iPage].fZero)
914	continue;
915
916	uint8_t abSha1Hash[RTSHA1_HASH_SIZE];
917	RTSha1(pbPage, PAGE_SIZE, abSha1Hash);
918	if (!memcmp(abSha1Hash, paLSPages[iPage].abSha1Saved, sizeof(abSha1Hash)))
919	continue;
920	}
921	u8Type = paLSPages[iPage].fZero ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
922	pVM->pgm.s.LiveSave.cSavedPages++;
923	}
924
925	if (iPage != 0 && iPage == iPageLast + 1)
926	rc = SSMR3PutU8(pSSM, u8Type);
927	else
928	{
929	SSMR3PutU8(pSSM, u8Type \| PGM_STATE_REC_FLAG_ADDR);
930	SSMR3PutU8(pSSM, pMmio2->idSavedState);
931	rc = SSMR3PutU32(pSSM, iPage);
932	}
933	if (u8Type == PGM_STATE_REC_MMIO2_RAW)
934	rc = SSMR3PutMem(pSSM, pbPage, PAGE_SIZE);
935	if (RT_FAILURE(rc))
936	break;
937	iPageLast = iPage;
938	}
939	}
940	pgmUnlock(pVM);
941	}
942	/*
943	* Reduce the rate after a little while since the current MMIO2 approach is
944	* a bit expensive.
945	* We position it two passes after the scan pass to avoid saving busy pages.
946	*/
947	else if ( uPass <= 10
948	\|\| (uPass & 3) == 2)
949	{
950	pgmLock(pVM);
951	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3;
952	pMmio2 && RT_SUCCESS(rc);
953	pMmio2 = pMmio2->pNextR3)
954	{
955	PPGMLIVESAVEMMIO2PAGE paLSPages = pMmio2->paLSPages;
956	uint8_t const pbPage = (uint8_t const )pMmio2->RamRange.pvR3;
957	uint32_t cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
958	uint32_t iPageLast = cPages;
959	pgmUnlock(pVM);
960
961	for (uint32_t iPage = 0; iPage < cPages; iPage++, pbPage += PAGE_SIZE)
962	{
963	/* Skip clean pages and pages which hasn't quiesced. */
964	if (!paLSPages[iPage].fDirty)
965	continue;
966	if (paLSPages[iPage].cUnchangedScans < 3)
967	continue;
968	if (pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]))
969	continue;
970
971	/* Save it. */
972	bool const fZero = paLSPages[iPage].fZero;
973	uint8_t abPage[PAGE_SIZE];
974	if (!fZero)
975	{
976	memcpy(abPage, pbPage, PAGE_SIZE);
977	RTSha1(abPage, PAGE_SIZE, paLSPages[iPage].abSha1Saved);
978	}
979
980	uint8_t u8Type = paLSPages[iPage].fZero ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
981	if (iPage != 0 && iPage == iPageLast + 1)
982	rc = SSMR3PutU8(pSSM, u8Type);
983	else
984	{
985	SSMR3PutU8(pSSM, u8Type \| PGM_STATE_REC_FLAG_ADDR);
986	SSMR3PutU8(pSSM, pMmio2->idSavedState);
987	rc = SSMR3PutU32(pSSM, iPage);
988	}
989	if (u8Type == PGM_STATE_REC_MMIO2_RAW)
990	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
991	if (RT_FAILURE(rc))
992	break;
993
994	/* Housekeeping. */
995	paLSPages[iPage].fDirty = false;
996	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages--;
997	pVM->pgm.s.LiveSave.Mmio2.cReadyPages++;
998	if (u8Type == PGM_STATE_REC_MMIO2_ZERO)
999	pVM->pgm.s.LiveSave.Mmio2.cZeroPages++;
1000	pVM->pgm.s.LiveSave.cSavedPages++;
1001	iPageLast = iPage;
1002	}
1003
1004	pgmLock(pVM);
1005	}
1006	pgmUnlock(pVM);
1007	}
1008
1009	return rc;
1010	}
1011
1012
1013	/**
1014	* Cleans up MMIO2 pages after a live save.
1015	*
1016	* @param pVM The VM handle.
1017	*/
1018	static void pgmR3DoneMmio2Pages(PVM pVM)
1019	{
1020	/*
1021	* Free the tracking structures for the MMIO2 pages.
1022	* We do the freeing outside the lock in case the VM is running.
1023	*/
1024	pgmLock(pVM);
1025	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
1026	{
1027	void *pvMmio2ToFree = pMmio2->paLSPages;
1028	if (pvMmio2ToFree)
1029	{
1030	pMmio2->paLSPages = NULL;
1031	pgmUnlock(pVM);
1032	MMR3HeapFree(pvMmio2ToFree);
1033	pgmLock(pVM);
1034	}
1035	}
1036	pgmUnlock(pVM);
1037	}
1038
1039
1040	/**
1041	* Prepares the RAM pages for a live save.
1042	*
1043	* @returns VBox status code.
1044	* @param pVM The VM handle.
1045	*/
1046	static int pgmR3PrepRamPages(PVM pVM)
1047	{
1048
1049	/*
1050	* Try allocating tracking structures for the ram ranges.
1051	*
1052	* To avoid lock contention, we leave the lock every time we're allocating
1053	* a new array. This means we'll have to ditch the allocation and start
1054	* all over again if the RAM range list changes in-between.
1055	*
1056	* Note! pgmR3SaveDone will always be called and it is therefore responsible
1057	* for cleaning up.
1058	*/
1059	PPGMRAMRANGE pCur;
1060	pgmLock(pVM);
1061	do
1062	{
1063	for (pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
1064	{
1065	if ( !pCur->paLSPages
1066	&& !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1067	{
1068	uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1069	uint32_t const cPages = pCur->cb >> PAGE_SHIFT;
1070	pgmUnlock(pVM);
1071	PPGMLIVESAVERAMPAGE paLSPages = (PPGMLIVESAVERAMPAGE)MMR3HeapAllocZ(pVM, MM_TAG_PGM, cPages * sizeof(PGMLIVESAVERAMPAGE));
1072	if (!paLSPages)
1073	return VERR_NO_MEMORY;
1074	pgmLock(pVM);
1075	if (pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1076	{
1077	pgmUnlock(pVM);
1078	MMR3HeapFree(paLSPages);
1079	pgmLock(pVM);
1080	break; /* try again */
1081	}
1082	pCur->paLSPages = paLSPages;
1083
1084	/*
1085	* Initialize the array.
1086	*/
1087	uint32_t iPage = cPages;
1088	while (iPage-- > 0)
1089	{
1090	/** @todo yield critsect! (after moving this away from EMT0) */
1091	PCPGMPAGE pPage = &pCur->aPages[iPage];
1092	paLSPages[iPage].cDirtied = 0;
1093	paLSPages[iPage].fDirty = 1; /* everything is dirty at this time */
1094	paLSPages[iPage].fWriteMonitored = 0;
1095	paLSPages[iPage].fWriteMonitoredJustNow = 0;
1096	paLSPages[iPage].u2Reserved = 0;
1097	switch (PGM_PAGE_GET_TYPE(pPage))
1098	{
1099	case PGMPAGETYPE_RAM:
1100	if ( PGM_PAGE_IS_ZERO(pPage)
1101	\|\| PGM_PAGE_IS_BALLOONED(pPage))
1102	{
1103	paLSPages[iPage].fZero = 1;
1104	paLSPages[iPage].fShared = 0;
1105	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1106	paLSPages[iPage].u32Crc = PGM_STATE_CRC32_ZERO_PAGE;
1107	#endif
1108	}
1109	else if (PGM_PAGE_IS_SHARED(pPage))
1110	{
1111	paLSPages[iPage].fZero = 0;
1112	paLSPages[iPage].fShared = 1;
1113	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1114	paLSPages[iPage].u32Crc = UINT32_MAX;
1115	#endif
1116	}
1117	else
1118	{
1119	paLSPages[iPage].fZero = 0;
1120	paLSPages[iPage].fShared = 0;
1121	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1122	paLSPages[iPage].u32Crc = UINT32_MAX;
1123	#endif
1124	}
1125	paLSPages[iPage].fIgnore = 0;
1126	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1127	break;
1128
1129	case PGMPAGETYPE_ROM_SHADOW:
1130	case PGMPAGETYPE_ROM:
1131	{
1132	paLSPages[iPage].fZero = 0;
1133	paLSPages[iPage].fShared = 0;
1134	paLSPages[iPage].fDirty = 0;
1135	paLSPages[iPage].fIgnore = 1;
1136	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1137	paLSPages[iPage].u32Crc = UINT32_MAX;
1138	#endif
1139	pVM->pgm.s.LiveSave.cIgnoredPages++;
1140	break;
1141	}
1142
1143	default:
1144	AssertMsgFailed(("%R[pgmpage]", pPage));
1145	case PGMPAGETYPE_MMIO2:
1146	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1147	paLSPages[iPage].fZero = 0;
1148	paLSPages[iPage].fShared = 0;
1149	paLSPages[iPage].fDirty = 0;
1150	paLSPages[iPage].fIgnore = 1;
1151	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1152	paLSPages[iPage].u32Crc = UINT32_MAX;
1153	#endif
1154	pVM->pgm.s.LiveSave.cIgnoredPages++;
1155	break;
1156
1157	case PGMPAGETYPE_MMIO:
1158	paLSPages[iPage].fZero = 0;
1159	paLSPages[iPage].fShared = 0;
1160	paLSPages[iPage].fDirty = 0;
1161	paLSPages[iPage].fIgnore = 1;
1162	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1163	paLSPages[iPage].u32Crc = UINT32_MAX;
1164	#endif
1165	pVM->pgm.s.LiveSave.cIgnoredPages++;
1166	break;
1167	}
1168	}
1169	}
1170	}
1171	} while (pCur);
1172	pgmUnlock(pVM);
1173
1174	return VINF_SUCCESS;
1175	}
1176
1177
1178	/**
1179	* Saves the RAM configuration.
1180	*
1181	* @returns VBox status code.
1182	* @param pVM The VM handle.
1183	* @param pSSM The saved state handle.
1184	*/
1185	static int pgmR3SaveRamConfig(PVM pVM, PSSMHANDLE pSSM)
1186	{
1187	uint32_t cbRamHole = 0;
1188	int rc = CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
1189	AssertRCReturn(rc, rc);
1190
1191	uint64_t cbRam = 0;
1192	rc = CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRam, 0);
1193	AssertRCReturn(rc, rc);
1194
1195	SSMR3PutU32(pSSM, cbRamHole);
1196	return SSMR3PutU64(pSSM, cbRam);
1197	}
1198
1199
1200	/**
1201	* Loads and verifies the RAM configuration.
1202	*
1203	* @returns VBox status code.
1204	* @param pVM The VM handle.
1205	* @param pSSM The saved state handle.
1206	*/
1207	static int pgmR3LoadRamConfig(PVM pVM, PSSMHANDLE pSSM)
1208	{
1209	uint32_t cbRamHoleCfg = 0;
1210	int rc = CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHoleCfg, MM_RAM_HOLE_SIZE_DEFAULT);
1211	AssertRCReturn(rc, rc);
1212
1213	uint64_t cbRamCfg = 0;
1214	rc = CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRamCfg, 0);
1215	AssertRCReturn(rc, rc);
1216
1217	uint32_t cbRamHoleSaved;
1218	SSMR3GetU32(pSSM, &cbRamHoleSaved);
1219
1220	uint64_t cbRamSaved;
1221	rc = SSMR3GetU64(pSSM, &cbRamSaved);
1222	AssertRCReturn(rc, rc);
1223
1224	if ( cbRamHoleCfg != cbRamHoleSaved
1225	\|\| cbRamCfg != cbRamSaved)
1226	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Ram config mismatch: saved=%RX64/%RX32 config=%RX64/%RX32 (RAM/Hole)"),
1227	cbRamSaved, cbRamHoleSaved, cbRamCfg, cbRamHoleCfg);
1228	return VINF_SUCCESS;
1229	}
1230
1231	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1232
1233	/**
1234	* Calculates the CRC-32 for a RAM page and updates the live save page tracking
1235	* info with it.
1236	*
1237	* @param pVM The VM handle.
1238	* @param pCur The current RAM range.
1239	* @param paLSPages The current array of live save page tracking
1240	* structures.
1241	* @param iPage The page index.
1242	*/
1243	static void pgmR3StateCalcCrc32ForRamPage(PVM pVM, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage)
1244	{
1245	RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1246	void const *pvPage;
1247	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage);
1248	if (RT_SUCCESS(rc))
1249	paLSPages[iPage].u32Crc = RTCrc32(pvPage, PAGE_SIZE);
1250	else
1251	paLSPages[iPage].u32Crc = UINT32_MAX; /* Invalid */
1252	}
1253
1254
1255	/**
1256	* Verifies the CRC-32 for a page given it's raw bits.
1257	*
1258	* @param pvPage The page bits.
1259	* @param pCur The current RAM range.
1260	* @param paLSPages The current array of live save page tracking
1261	* structures.
1262	* @param iPage The page index.
1263	*/
1264	static void pgmR3StateVerifyCrc32ForPage(void const pvPage, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage, const char pszWhere)
1265	{
1266	if (paLSPages[iPage].u32Crc != UINT32_MAX)
1267	{
1268	uint32_t u32Crc = RTCrc32(pvPage, PAGE_SIZE);
1269	Assert( ( !PGM_PAGE_IS_ZERO(&pCur->aPages[iPage])
1270	&& !PGM_PAGE_IS_BALLOONED(&pCur->aPages[iPage]))
1271	\|\| u32Crc == PGM_STATE_CRC32_ZERO_PAGE);
1272	AssertMsg(paLSPages[iPage].u32Crc == u32Crc,
1273	("%08x != %08x for %RGp %R[pgmpage] %s\n", paLSPages[iPage].u32Crc, u32Crc,
1274	pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pCur->aPages[iPage], pszWhere));
1275	}
1276	}
1277
1278
1279	/**
1280	* Verifies the CRC-32 for a RAM page.
1281	*
1282	* @param pVM The VM handle.
1283	* @param pCur The current RAM range.
1284	* @param paLSPages The current array of live save page tracking
1285	* structures.
1286	* @param iPage The page index.
1287	*/
1288	static void pgmR3StateVerifyCrc32ForRamPage(PVM pVM, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage, const char *pszWhere)
1289	{
1290	if (paLSPages[iPage].u32Crc != UINT32_MAX)
1291	{
1292	RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1293	void const *pvPage;
1294	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage);
1295	if (RT_SUCCESS(rc))
1296	pgmR3StateVerifyCrc32ForPage(pvPage, pCur, paLSPages, iPage, pszWhere);
1297	}
1298	}
1299
1300	#endif /* PGMLIVESAVERAMPAGE_WITH_CRC32 */
1301
1302	/**
1303	* Scan for RAM page modifications and reprotect them.
1304	*
1305	* @param pVM The VM handle.
1306	* @param fFinalPass Whether this is the final pass or not.
1307	*/
1308	static void pgmR3ScanRamPages(PVM pVM, bool fFinalPass)
1309	{
1310	/*
1311	* The RAM.
1312	*/
1313	RTGCPHYS GCPhysCur = 0;
1314	PPGMRAMRANGE pCur;
1315	pgmLock(pVM);
1316	do
1317	{
1318	uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1319	for (pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
1320	{
1321	if ( pCur->GCPhysLast > GCPhysCur
1322	&& !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1323	{
1324	PPGMLIVESAVERAMPAGE paLSPages = pCur->paLSPages;
1325	uint32_t cPages = pCur->cb >> PAGE_SHIFT;
1326	uint32_t iPage = GCPhysCur <= pCur->GCPhys ? 0 : (GCPhysCur - pCur->GCPhys) >> PAGE_SHIFT;
1327	GCPhysCur = 0;
1328	for (; iPage < cPages; iPage++)
1329	{
1330	/* Do yield first. */
1331	if ( !fFinalPass
1332	#ifndef PGMLIVESAVERAMPAGE_WITH_CRC32
1333	&& (iPage & 0x7ff) == 0x100
1334	#endif
1335	&& PDMR3CritSectYield(&pVM->pgm.s.CritSect)
1336	&& pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1337	{
1338	GCPhysCur = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1339	break; /* restart */
1340	}
1341
1342	/* Skip already ignored pages. */
1343	if (paLSPages[iPage].fIgnore)
1344	continue;
1345
1346	if (RT_LIKELY(PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) == PGMPAGETYPE_RAM))
1347	{
1348	/*
1349	* A RAM page.
1350	*/
1351	switch (PGM_PAGE_GET_STATE(&pCur->aPages[iPage]))
1352	{
1353	case PGM_PAGE_STATE_ALLOCATED:
1354	/** @todo Optimize this: Don't always re-enable write
1355	* monitoring if the page is known to be very busy. */
1356	if (PGM_PAGE_IS_WRITTEN_TO(&pCur->aPages[iPage]))
1357	{
1358	Assert(paLSPages[iPage].fWriteMonitored);
1359	PGM_PAGE_CLEAR_WRITTEN_TO(pVM, &pCur->aPages[iPage]);
1360	Assert(pVM->pgm.s.cWrittenToPages > 0);
1361	pVM->pgm.s.cWrittenToPages--;
1362	}
1363	else
1364	{
1365	Assert(!paLSPages[iPage].fWriteMonitored);
1366	pVM->pgm.s.LiveSave.Ram.cMonitoredPages++;
1367	}
1368
1369	if (!paLSPages[iPage].fDirty)
1370	{
1371	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1372	if (paLSPages[iPage].fZero)
1373	pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1374	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1375	if (++paLSPages[iPage].cDirtied > PGMLIVSAVEPAGE_MAX_DIRTIED)
1376	paLSPages[iPage].cDirtied = PGMLIVSAVEPAGE_MAX_DIRTIED;
1377	}
1378
1379	pgmPhysPageWriteMonitor(pVM, &pCur->aPages[iPage],
1380	pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1381	paLSPages[iPage].fWriteMonitored = 1;
1382	paLSPages[iPage].fWriteMonitoredJustNow = 1;
1383	paLSPages[iPage].fDirty = 1;
1384	paLSPages[iPage].fZero = 0;
1385	paLSPages[iPage].fShared = 0;
1386	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1387	paLSPages[iPage].u32Crc = UINT32_MAX; /* invalid */
1388	#endif
1389	break;
1390
1391	case PGM_PAGE_STATE_WRITE_MONITORED:
1392	Assert(paLSPages[iPage].fWriteMonitored);
1393	if (PGM_PAGE_GET_WRITE_LOCKS(&pCur->aPages[iPage]) == 0)
1394	{
1395	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1396	if (paLSPages[iPage].fWriteMonitoredJustNow)
1397	pgmR3StateCalcCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1398	else
1399	pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage, "scan");
1400	#endif
1401	paLSPages[iPage].fWriteMonitoredJustNow = 0;
1402	}
1403	else
1404	{
1405	paLSPages[iPage].fWriteMonitoredJustNow = 1;
1406	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1407	paLSPages[iPage].u32Crc = UINT32_MAX; /* invalid */
1408	#endif
1409	if (!paLSPages[iPage].fDirty)
1410	{
1411	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1412	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1413	if (++paLSPages[iPage].cDirtied > PGMLIVSAVEPAGE_MAX_DIRTIED)
1414	paLSPages[iPage].cDirtied = PGMLIVSAVEPAGE_MAX_DIRTIED;
1415	}
1416	}
1417	break;
1418
1419	case PGM_PAGE_STATE_ZERO:
1420	if (!paLSPages[iPage].fZero)
1421	{
1422	if (!paLSPages[iPage].fDirty)
1423	{
1424	paLSPages[iPage].fDirty = 1;
1425	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1426	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1427	}
1428	paLSPages[iPage].fZero = 1;
1429	paLSPages[iPage].fShared = 0;
1430	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1431	paLSPages[iPage].u32Crc = PGM_STATE_CRC32_ZERO_PAGE;
1432	#endif
1433	}
1434	break;
1435
1436	case PGM_PAGE_STATE_BALLOONED:
1437	if (!paLSPages[iPage].fZero)
1438	{
1439	if (!paLSPages[iPage].fDirty)
1440	{
1441	paLSPages[iPage].fDirty = 1;
1442	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1443	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1444	}
1445	paLSPages[iPage].fZero = 1;
1446	paLSPages[iPage].fShared = 0;
1447	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1448	paLSPages[iPage].u32Crc = PGM_STATE_CRC32_ZERO_PAGE;
1449	#endif
1450	}
1451	break;
1452
1453	case PGM_PAGE_STATE_SHARED:
1454	if (!paLSPages[iPage].fShared)
1455	{
1456	if (!paLSPages[iPage].fDirty)
1457	{
1458	paLSPages[iPage].fDirty = 1;
1459	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1460	if (paLSPages[iPage].fZero)
1461	pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1462	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1463	}
1464	paLSPages[iPage].fZero = 0;
1465	paLSPages[iPage].fShared = 1;
1466	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1467	pgmR3StateCalcCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1468	#endif
1469	}
1470	break;
1471	}
1472	}
1473	else
1474	{
1475	/*
1476	* All other types => Ignore the page.
1477	*/
1478	Assert(!paLSPages[iPage].fIgnore); /* skipped before switch */
1479	paLSPages[iPage].fIgnore = 1;
1480	if (paLSPages[iPage].fWriteMonitored)
1481	{
1482	/** @todo this doesn't hold water when we start monitoring MMIO2 and ROM shadow
1483	* pages! */
1484	if (RT_UNLIKELY(PGM_PAGE_GET_STATE(&pCur->aPages[iPage]) == PGM_PAGE_STATE_WRITE_MONITORED))
1485	{
1486	AssertMsgFailed(("%R[pgmpage]", &pCur->aPages[iPage])); /* shouldn't happen. */
1487	PGM_PAGE_SET_STATE(pVM, &pCur->aPages[iPage], PGM_PAGE_STATE_ALLOCATED);
1488	Assert(pVM->pgm.s.cMonitoredPages > 0);
1489	pVM->pgm.s.cMonitoredPages--;
1490	}
1491	if (PGM_PAGE_IS_WRITTEN_TO(&pCur->aPages[iPage]))
1492	{
1493	PGM_PAGE_CLEAR_WRITTEN_TO(pVM, &pCur->aPages[iPage]);
1494	Assert(pVM->pgm.s.cWrittenToPages > 0);
1495	pVM->pgm.s.cWrittenToPages--;
1496	}
1497	pVM->pgm.s.LiveSave.Ram.cMonitoredPages--;
1498	}
1499
1500	/** @todo the counting doesn't quite work out here. fix later? */
1501	if (paLSPages[iPage].fDirty)
1502	pVM->pgm.s.LiveSave.Ram.cDirtyPages--;
1503	else
1504	{
1505	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1506	if (paLSPages[iPage].fZero)
1507	pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1508	}
1509	pVM->pgm.s.LiveSave.cIgnoredPages++;
1510	}
1511	} /* for each page in range */
1512
1513	if (GCPhysCur != 0)
1514	break; /* Yield + ramrange change */
1515	GCPhysCur = pCur->GCPhysLast;
1516	}
1517	} /* for each range */
1518	} while (pCur);
1519	pgmUnlock(pVM);
1520	}
1521
1522
1523	/**
1524	* Save quiescent RAM pages.
1525	*
1526	* @returns VBox status code.
1527	* @param pVM The VM handle.
1528	* @param pSSM The SSM handle.
1529	* @param fLiveSave Whether it's a live save or not.
1530	* @param uPass The pass number.
1531	*/
1532	static int pgmR3SaveRamPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, uint32_t uPass)
1533	{
1534	/*
1535	* The RAM.
1536	*/
1537	RTGCPHYS GCPhysLast = NIL_RTGCPHYS;
1538	RTGCPHYS GCPhysCur = 0;
1539	PPGMRAMRANGE pCur;
1540	bool fFTMDeltaSaveActive = FTMIsDeltaLoadSaveActive(pVM);
1541
1542	pgmLock(pVM);
1543	do
1544	{
1545	uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1546	for (pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
1547	{
1548	if ( pCur->GCPhysLast > GCPhysCur
1549	&& !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1550	{
1551	PPGMLIVESAVERAMPAGE paLSPages = pCur->paLSPages;
1552	uint32_t cPages = pCur->cb >> PAGE_SHIFT;
1553	uint32_t iPage = GCPhysCur <= pCur->GCPhys ? 0 : (GCPhysCur - pCur->GCPhys) >> PAGE_SHIFT;
1554	GCPhysCur = 0;
1555	for (; iPage < cPages; iPage++)
1556	{
1557	/* Do yield first. */
1558	if ( uPass != SSM_PASS_FINAL
1559	&& (iPage & 0x7ff) == 0x100
1560	&& PDMR3CritSectYield(&pVM->pgm.s.CritSect)
1561	&& pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1562	{
1563	GCPhysCur = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1564	break; /* restart */
1565	}
1566
1567	PPGMPAGE pCurPage = &pCur->aPages[iPage];
1568
1569	/*
1570	* Only save pages that haven't changed since last scan and are dirty.
1571	*/
1572	if ( uPass != SSM_PASS_FINAL
1573	&& paLSPages)
1574	{
1575	if (!paLSPages[iPage].fDirty)
1576	continue;
1577	if (paLSPages[iPage].fWriteMonitoredJustNow)
1578	continue;
1579	if (paLSPages[iPage].fIgnore)
1580	continue;
1581	if (PGM_PAGE_GET_TYPE(pCurPage) != PGMPAGETYPE_RAM) /* in case of recent remappings */
1582	continue;
1583	if ( PGM_PAGE_GET_STATE(pCurPage)
1584	!= ( paLSPages[iPage].fZero
1585	? PGM_PAGE_STATE_ZERO
1586	: paLSPages[iPage].fShared
1587	? PGM_PAGE_STATE_SHARED
1588	: PGM_PAGE_STATE_WRITE_MONITORED))
1589	continue;
1590	if (PGM_PAGE_GET_WRITE_LOCKS(&pCur->aPages[iPage]) > 0)
1591	continue;
1592	}
1593	else
1594	{
1595	if ( paLSPages
1596	&& !paLSPages[iPage].fDirty
1597	&& !paLSPages[iPage].fIgnore)
1598	{
1599	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1600	if (PGM_PAGE_GET_TYPE(pCurPage) != PGMPAGETYPE_RAM)
1601	pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage, "save#1");
1602	#endif
1603	continue;
1604	}
1605	if (PGM_PAGE_GET_TYPE(pCurPage) != PGMPAGETYPE_RAM)
1606	continue;
1607	}
1608
1609	/*
1610	* Do the saving outside the PGM critsect since SSM may block on I/O.
1611	*/
1612	int rc;
1613	RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1614	bool fZero = PGM_PAGE_IS_ZERO(pCurPage);
1615	bool fBallooned = PGM_PAGE_IS_BALLOONED(pCurPage);
1616	bool fSkipped = false;
1617
1618	if (!fZero && !fBallooned)
1619	{
1620	/*
1621	* Copy the page and then save it outside the lock (since any
1622	* SSM call may block).
1623	*/
1624	uint8_t abPage[PAGE_SIZE];
1625	void const *pvPage;
1626	rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pCurPage, GCPhys, &pvPage);
1627	if (RT_SUCCESS(rc))
1628	{
1629	memcpy(abPage, pvPage, PAGE_SIZE);
1630	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1631	if (paLSPages)
1632	pgmR3StateVerifyCrc32ForPage(abPage, pCur, paLSPages, iPage, "save#3");
1633	#endif
1634	}
1635	pgmUnlock(pVM);
1636	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
1637
1638	/* Try save some memory when restoring. */
1639	if (!ASMMemIsZeroPage(pvPage))
1640	{
1641	if (fFTMDeltaSaveActive)
1642	{
1643	if ( PGM_PAGE_IS_WRITTEN_TO(pCurPage)
1644	\|\| PGM_PAGE_IS_FT_DIRTY(pCurPage))
1645	{
1646	if (GCPhys == GCPhysLast + PAGE_SIZE)
1647	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_RAW);
1648	else
1649	{
1650	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_RAW \| PGM_STATE_REC_FLAG_ADDR);
1651	SSMR3PutGCPhys(pSSM, GCPhys);
1652	}
1653	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
1654	PGM_PAGE_CLEAR_WRITTEN_TO(pVM, pCurPage);
1655	PGM_PAGE_CLEAR_FT_DIRTY(pCurPage);
1656	}
1657	/* else nothing changed, so skip it. */
1658	else
1659	fSkipped = true;
1660	}
1661	else
1662	{
1663	if (GCPhys == GCPhysLast + PAGE_SIZE)
1664	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_RAW);
1665	else
1666	{
1667	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_RAW \| PGM_STATE_REC_FLAG_ADDR);
1668	SSMR3PutGCPhys(pSSM, GCPhys);
1669	}
1670	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
1671	}
1672	}
1673	else
1674	{
1675	if (GCPhys == GCPhysLast + PAGE_SIZE)
1676	rc = SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_ZERO);
1677	else
1678	{
1679	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_ZERO \| PGM_STATE_REC_FLAG_ADDR);
1680	rc = SSMR3PutGCPhys(pSSM, GCPhys);
1681	}
1682	}
1683	}
1684	else
1685	{
1686	/*
1687	* Dirty zero or ballooned page.
1688	*/
1689	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1690	if (paLSPages)
1691	pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage, "save#2");
1692	#endif
1693	pgmUnlock(pVM);
1694
1695	uint8_t u8RecType = fBallooned ? PGM_STATE_REC_RAM_BALLOONED : PGM_STATE_REC_RAM_ZERO;
1696	if (GCPhys == GCPhysLast + PAGE_SIZE)
1697	rc = SSMR3PutU8(pSSM, u8RecType);
1698	else
1699	{
1700	SSMR3PutU8(pSSM, u8RecType \| PGM_STATE_REC_FLAG_ADDR);
1701	rc = SSMR3PutGCPhys(pSSM, GCPhys);
1702	}
1703	}
1704	if (RT_FAILURE(rc))
1705	return rc;
1706
1707	pgmLock(pVM);
1708	if (!fSkipped)
1709	GCPhysLast = GCPhys;
1710	if (paLSPages)
1711	{
1712	paLSPages[iPage].fDirty = 0;
1713	pVM->pgm.s.LiveSave.Ram.cReadyPages++;
1714	if (fZero)
1715	pVM->pgm.s.LiveSave.Ram.cZeroPages++;
1716	pVM->pgm.s.LiveSave.Ram.cDirtyPages--;
1717	pVM->pgm.s.LiveSave.cSavedPages++;
1718	}
1719	if (idRamRangesGen != pVM->pgm.s.idRamRangesGen)
1720	{
1721	GCPhysCur = GCPhys \| PAGE_OFFSET_MASK;
1722	break; /* restart */
1723	}
1724
1725	} /* for each page in range */
1726
1727	if (GCPhysCur != 0)
1728	break; /* Yield + ramrange change */
1729	GCPhysCur = pCur->GCPhysLast;
1730	}
1731	} /* for each range */
1732	} while (pCur);
1733
1734	pgmUnlock(pVM);
1735
1736	return VINF_SUCCESS;
1737	}
1738
1739
1740	/**
1741	* Cleans up RAM pages after a live save.
1742	*
1743	* @param pVM The VM handle.
1744	*/
1745	static void pgmR3DoneRamPages(PVM pVM)
1746	{
1747	/*
1748	* Free the tracking arrays and disable write monitoring.
1749	*
1750	* Play nice with the PGM lock in case we're called while the VM is still
1751	* running. This means we have to delay the freeing since we wish to use
1752	* paLSPages as an indicator of which RAM ranges which we need to scan for
1753	* write monitored pages.
1754	*/
1755	void *pvToFree = NULL;
1756	PPGMRAMRANGE pCur;
1757	uint32_t cMonitoredPages = 0;
1758	pgmLock(pVM);
1759	do
1760	{
1761	for (pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
1762	{
1763	if (pCur->paLSPages)
1764	{
1765	if (pvToFree)
1766	{
1767	uint32_t idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1768	pgmUnlock(pVM);
1769	MMR3HeapFree(pvToFree);
1770	pvToFree = NULL;
1771	pgmLock(pVM);
1772	if (idRamRangesGen != pVM->pgm.s.idRamRangesGen)
1773	break; /* start over again. */
1774	}
1775
1776	pvToFree = pCur->paLSPages;
1777	pCur->paLSPages = NULL;
1778
1779	uint32_t iPage = pCur->cb >> PAGE_SHIFT;
1780	while (iPage--)
1781	{
1782	PPGMPAGE pPage = &pCur->aPages[iPage];
1783	PGM_PAGE_CLEAR_WRITTEN_TO(pVM, pPage);
1784	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
1785	{
1786	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ALLOCATED);
1787	cMonitoredPages++;
1788	}
1789	}
1790	}
1791	}
1792	} while (pCur);
1793
1794	Assert(pVM->pgm.s.cMonitoredPages >= cMonitoredPages);
1795	if (pVM->pgm.s.cMonitoredPages < cMonitoredPages)
1796	pVM->pgm.s.cMonitoredPages = 0;
1797	else
1798	pVM->pgm.s.cMonitoredPages -= cMonitoredPages;
1799
1800	pgmUnlock(pVM);
1801
1802	MMR3HeapFree(pvToFree);
1803	pvToFree = NULL;
1804	}
1805
1806
1807	/**
1808	* Execute a live save pass.
1809	*
1810	* @returns VBox status code.
1811	*
1812	* @param pVM The VM handle.
1813	* @param pSSM The SSM handle.
1814	*/
1815	static DECLCALLBACK(int) pgmR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1816	{
1817	int rc;
1818
1819	/*
1820	* Save the MMIO2 and ROM range IDs in pass 0.
1821	*/
1822	if (uPass == 0)
1823	{
1824	rc = pgmR3SaveRamConfig(pVM, pSSM);
1825	if (RT_FAILURE(rc))
1826	return rc;
1827	rc = pgmR3SaveRomRanges(pVM, pSSM);
1828	if (RT_FAILURE(rc))
1829	return rc;
1830	rc = pgmR3SaveMmio2Ranges(pVM, pSSM);
1831	if (RT_FAILURE(rc))
1832	return rc;
1833	}
1834	/*
1835	* Reset the page-per-second estimate to avoid inflation by the initial
1836	* load of zero pages. pgmR3LiveVote ASSUMES this is done at pass 7.
1837	*/
1838	else if (uPass == 7)
1839	{
1840	pVM->pgm.s.LiveSave.cSavedPages = 0;
1841	pVM->pgm.s.LiveSave.uSaveStartNS = RTTimeNanoTS();
1842	}
1843
1844	/*
1845	* Do the scanning.
1846	*/
1847	pgmR3ScanRomPages(pVM);
1848	pgmR3ScanMmio2Pages(pVM, uPass);
1849	pgmR3ScanRamPages(pVM, false /fFinalPass/);
1850	pgmR3PoolClearAll(pVM, true /fFlushRemTlb/); /** @todo this could perhaps be optimized a bit. */
1851
1852	/*
1853	* Save the pages.
1854	*/
1855	if (uPass == 0)
1856	rc = pgmR3SaveRomVirginPages( pVM, pSSM, true /fLiveSave/);
1857	else
1858	rc = VINF_SUCCESS;
1859	if (RT_SUCCESS(rc))
1860	rc = pgmR3SaveShadowedRomPages(pVM, pSSM, true /fLiveSave/, false /fFinalPass/);
1861	if (RT_SUCCESS(rc))
1862	rc = pgmR3SaveMmio2Pages( pVM, pSSM, true /fLiveSave/, uPass);
1863	if (RT_SUCCESS(rc))
1864	rc = pgmR3SaveRamPages( pVM, pSSM, true /fLiveSave/, uPass);
1865	SSMR3PutU8(pSSM, PGM_STATE_REC_END); /* (Ignore the rc, SSM takes care of it.) */
1866
1867	return rc;
1868	}
1869
1870
1871	/**
1872	* Votes on whether the live save phase is done or not.
1873	*
1874	* @returns VBox status code.
1875	*
1876	* @param pVM The VM handle.
1877	* @param pSSM The SSM handle.
1878	* @param uPass The data pass.
1879	*/
1880	static DECLCALLBACK(int) pgmR3LiveVote(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1881	{
1882	/*
1883	* Update and calculate parameters used in the decision making.
1884	*/
1885	const uint32_t cHistoryEntries = RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory);
1886
1887	/* update history. */
1888	pgmLock(pVM);
1889	uint32_t const cWrittenToPages = pVM->pgm.s.cWrittenToPages;
1890	pgmUnlock(pVM);
1891	uint32_t const cDirtyNow = pVM->pgm.s.LiveSave.Rom.cDirtyPages
1892	+ pVM->pgm.s.LiveSave.Mmio2.cDirtyPages
1893	+ pVM->pgm.s.LiveSave.Ram.cDirtyPages
1894	+ cWrittenToPages;
1895	uint32_t i = pVM->pgm.s.LiveSave.iDirtyPagesHistory;
1896	pVM->pgm.s.LiveSave.acDirtyPagesHistory[i] = cDirtyNow;
1897	pVM->pgm.s.LiveSave.iDirtyPagesHistory = (i + 1) % cHistoryEntries;
1898
1899	/* calc shortterm average (4 passes). */
1900	AssertCompile(RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory) > 4);
1901	uint64_t cTotal = pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1902	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 1) % cHistoryEntries];
1903	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 2) % cHistoryEntries];
1904	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 3) % cHistoryEntries];
1905	uint32_t const cDirtyPagesShort = cTotal / 4;
1906	pVM->pgm.s.LiveSave.cDirtyPagesShort = cDirtyPagesShort;
1907
1908	/* calc longterm average. */
1909	cTotal = 0;
1910	if (uPass < cHistoryEntries)
1911	for (i = 0; i < cHistoryEntries && i <= uPass; i++)
1912	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1913	else
1914	for (i = 0; i < cHistoryEntries; i++)
1915	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1916	uint32_t const cDirtyPagesLong = cTotal / cHistoryEntries;
1917	pVM->pgm.s.LiveSave.cDirtyPagesLong = cDirtyPagesLong;
1918
1919	/* estimate the speed */
1920	uint64_t cNsElapsed = RTTimeNanoTS() - pVM->pgm.s.LiveSave.uSaveStartNS;
1921	uint32_t cPagesPerSecond = (uint32_t)( pVM->pgm.s.LiveSave.cSavedPages
1922	/ ((long double)cNsElapsed / 1000000000.0) );
1923	pVM->pgm.s.LiveSave.cPagesPerSecond = cPagesPerSecond;
1924
1925	/*
1926	* Try make a decision.
1927	*/
1928	if ( cDirtyPagesShort <= cDirtyPagesLong
1929	&& ( cDirtyNow <= cDirtyPagesShort
1930	\|\| cDirtyNow - cDirtyPagesShort < RT_MIN(cDirtyPagesShort / 8, 16)
1931	)
1932	)
1933	{
1934	if (uPass > 10)
1935	{
1936	uint32_t cMsLeftShort = (uint32_t)(cDirtyPagesShort / (long double)cPagesPerSecond * 1000.0);
1937	uint32_t cMsLeftLong = (uint32_t)(cDirtyPagesLong / (long double)cPagesPerSecond * 1000.0);
1938	uint32_t cMsMaxDowntime = SSMR3HandleMaxDowntime(pSSM);
1939	if (cMsMaxDowntime < 32)
1940	cMsMaxDowntime = 32;
1941	if ( ( cMsLeftLong <= cMsMaxDowntime
1942	&& cMsLeftShort < cMsMaxDowntime)
1943	\|\| cMsLeftShort < cMsMaxDowntime / 2
1944	)
1945	{
1946	Log(("pgmR3LiveVote: VINF_SUCCESS - pass=%d cDirtyPagesShort=%u\|%ums cDirtyPagesLong=%u\|%ums cMsMaxDowntime=%u\n",
1947	uPass, cDirtyPagesShort, cMsLeftShort, cDirtyPagesLong, cMsLeftLong, cMsMaxDowntime));
1948	return VINF_SUCCESS;
1949	}
1950	}
1951	else
1952	{
1953	if ( ( cDirtyPagesShort <= 128
1954	&& cDirtyPagesLong <= 1024)
1955	\|\| cDirtyPagesLong <= 256
1956	)
1957	{
1958	Log(("pgmR3LiveVote: VINF_SUCCESS - pass=%d cDirtyPagesShort=%u cDirtyPagesLong=%u\n", uPass, cDirtyPagesShort, cDirtyPagesLong));
1959	return VINF_SUCCESS;
1960	}
1961	}
1962	}
1963
1964	/*
1965	* Come up with a completion percentage. Currently this is a simple
1966	* dirty page (long term) vs. total pages ratio + some pass trickery.
1967	*/
1968	unsigned uPctDirty = (unsigned)( (long double)cDirtyPagesLong
1969	/ (pVM->pgm.s.cAllPages - pVM->pgm.s.LiveSave.cIgnoredPages - pVM->pgm.s.cZeroPages) );
1970	if (uPctDirty <= 100)
1971	SSMR3HandleReportLivePercent(pSSM, RT_MIN(100 - uPctDirty, uPass * 2));
1972	else
1973	AssertMsgFailed(("uPctDirty=%u cDirtyPagesLong=%#x cAllPages=%#x cIgnoredPages=%#x cZeroPages=%#x\n",
1974	uPctDirty, cDirtyPagesLong, pVM->pgm.s.cAllPages, pVM->pgm.s.LiveSave.cIgnoredPages, pVM->pgm.s.cZeroPages));
1975
1976	return VINF_SSM_VOTE_FOR_ANOTHER_PASS;
1977	}
1978
1979
1980	/**
1981	* Prepare for a live save operation.
1982	*
1983	* This will attempt to allocate and initialize the tracking structures. It
1984	* will also prepare for write monitoring of pages and initialize PGM::LiveSave.
1985	* pgmR3SaveDone will do the cleanups.
1986	*
1987	* @returns VBox status code.
1988	*
1989	* @param pVM The VM handle.
1990	* @param pSSM The SSM handle.
1991	*/
1992	static DECLCALLBACK(int) pgmR3LivePrep(PVM pVM, PSSMHANDLE pSSM)
1993	{
1994	/*
1995	* Indicate that we will be using the write monitoring.
1996	*/
1997	pgmLock(pVM);
1998	/** @todo find a way of mediating this when more users are added. */
1999	if (pVM->pgm.s.fPhysWriteMonitoringEngaged)
2000	{
2001	pgmUnlock(pVM);
2002	AssertLogRelFailedReturn(VERR_INTERNAL_ERROR_2);
2003	}
2004	pVM->pgm.s.fPhysWriteMonitoringEngaged = true;
2005	pgmUnlock(pVM);
2006
2007	/*
2008	* Initialize the statistics.
2009	*/
2010	pVM->pgm.s.LiveSave.Rom.cReadyPages = 0;
2011	pVM->pgm.s.LiveSave.Rom.cDirtyPages = 0;
2012	pVM->pgm.s.LiveSave.Mmio2.cReadyPages = 0;
2013	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages = 0;
2014	pVM->pgm.s.LiveSave.Ram.cReadyPages = 0;
2015	pVM->pgm.s.LiveSave.Ram.cDirtyPages = 0;
2016	pVM->pgm.s.LiveSave.cIgnoredPages = 0;
2017	pVM->pgm.s.LiveSave.fActive = true;
2018	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory); i++)
2019	pVM->pgm.s.LiveSave.acDirtyPagesHistory[i] = UINT32_MAX / 2;
2020	pVM->pgm.s.LiveSave.iDirtyPagesHistory = 0;
2021	pVM->pgm.s.LiveSave.cSavedPages = 0;
2022	pVM->pgm.s.LiveSave.uSaveStartNS = RTTimeNanoTS();
2023	pVM->pgm.s.LiveSave.cPagesPerSecond = 8192;
2024
2025	/*
2026	* Per page type.
2027	*/
2028	int rc = pgmR3PrepRomPages(pVM);
2029	if (RT_SUCCESS(rc))
2030	rc = pgmR3PrepMmio2Pages(pVM);
2031	if (RT_SUCCESS(rc))
2032	rc = pgmR3PrepRamPages(pVM);
2033	return rc;
2034	}
2035
2036
2037	/**
2038	* Execute state save operation.
2039	*
2040	* @returns VBox status code.
2041	* @param pVM VM Handle.
2042	* @param pSSM SSM operation handle.
2043	*/
2044	static DECLCALLBACK(int) pgmR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
2045	{
2046	int rc = VINF_SUCCESS;
2047	PPGM pPGM = &pVM->pgm.s;
2048
2049	/*
2050	* Lock PGM and set the no-more-writes indicator.
2051	*/
2052	pgmLock(pVM);
2053	pVM->pgm.s.fNoMorePhysWrites = true;
2054
2055	/*
2056	* Save basic data (required / unaffected by relocation).
2057	*/
2058	bool const fMappingsFixed = pVM->pgm.s.fMappingsFixed;
2059	pVM->pgm.s.fMappingsFixed \|= pVM->pgm.s.fMappingsFixedRestored;
2060	SSMR3PutStruct(pSSM, pPGM, &s_aPGMFields[0]);
2061	pVM->pgm.s.fMappingsFixed = fMappingsFixed;
2062
2063	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2064	rc = SSMR3PutStruct(pSSM, &pVM->aCpus[idCpu].pgm.s, &s_aPGMCpuFields[0]);
2065
2066	/*
2067	* Save the (remainder of the) memory.
2068	*/
2069	if (RT_SUCCESS(rc))
2070	{
2071	if (pVM->pgm.s.LiveSave.fActive)
2072	{
2073	pgmR3ScanRomPages(pVM);
2074	pgmR3ScanMmio2Pages(pVM, SSM_PASS_FINAL);
2075	pgmR3ScanRamPages(pVM, true /fFinalPass/);
2076
2077	rc = pgmR3SaveShadowedRomPages( pVM, pSSM, true /fLiveSave/, true /fFinalPass/);
2078	if (RT_SUCCESS(rc))
2079	rc = pgmR3SaveMmio2Pages( pVM, pSSM, true /fLiveSave/, SSM_PASS_FINAL);
2080	if (RT_SUCCESS(rc))
2081	rc = pgmR3SaveRamPages( pVM, pSSM, true /fLiveSave/, SSM_PASS_FINAL);
2082	}
2083	else
2084	{
2085	rc = pgmR3SaveRamConfig(pVM, pSSM);
2086	if (RT_SUCCESS(rc))
2087	rc = pgmR3SaveRomRanges(pVM, pSSM);
2088	if (RT_SUCCESS(rc))
2089	rc = pgmR3SaveMmio2Ranges(pVM, pSSM);
2090	if (RT_SUCCESS(rc))
2091	rc = pgmR3SaveRomVirginPages( pVM, pSSM, false /fLiveSave/);
2092	if (RT_SUCCESS(rc))
2093	rc = pgmR3SaveShadowedRomPages(pVM, pSSM, false /fLiveSave/, true /fFinalPass/);
2094	if (RT_SUCCESS(rc))
2095	rc = pgmR3SaveMmio2Pages( pVM, pSSM, false /fLiveSave/, SSM_PASS_FINAL);
2096	if (RT_SUCCESS(rc))
2097	rc = pgmR3SaveRamPages( pVM, pSSM, false /fLiveSave/, SSM_PASS_FINAL);
2098	}
2099	SSMR3PutU8(pSSM, PGM_STATE_REC_END); /* (Ignore the rc, SSM takes of it.) */
2100	}
2101
2102	pgmUnlock(pVM);
2103	return rc;
2104	}
2105
2106
2107	/**
2108	* Cleans up after an save state operation.
2109	*
2110	* @returns VBox status code.
2111	* @param pVM VM Handle.
2112	* @param pSSM SSM operation handle.
2113	*/
2114	static DECLCALLBACK(int) pgmR3SaveDone(PVM pVM, PSSMHANDLE pSSM)
2115	{
2116	/*
2117	* Do per page type cleanups first.
2118	*/
2119	if (pVM->pgm.s.LiveSave.fActive)
2120	{
2121	pgmR3DoneRomPages(pVM);
2122	pgmR3DoneMmio2Pages(pVM);
2123	pgmR3DoneRamPages(pVM);
2124	}
2125
2126	/*
2127	* Clear the live save indicator and disengage write monitoring.
2128	*/
2129	pgmLock(pVM);
2130	pVM->pgm.s.LiveSave.fActive = false;
2131	/** @todo this is blindly assuming that we're the only user of write
2132	* monitoring. Fix this when more users are added. */
2133	pVM->pgm.s.fPhysWriteMonitoringEngaged = false;
2134	pgmUnlock(pVM);
2135
2136	return VINF_SUCCESS;
2137	}
2138
2139
2140	/**
2141	* Prepare state load operation.
2142	*
2143	* @returns VBox status code.
2144	* @param pVM VM Handle.
2145	* @param pSSM SSM operation handle.
2146	*/
2147	static DECLCALLBACK(int) pgmR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2148	{
2149	/*
2150	* Call the reset function to make sure all the memory is cleared.
2151	*/
2152	PGMR3Reset(pVM);
2153	pVM->pgm.s.LiveSave.fActive = false;
2154	NOREF(pSSM);
2155	return VINF_SUCCESS;
2156	}
2157
2158
2159	/**
2160	* Load an ignored page.
2161	*
2162	* @returns VBox status code.
2163	* @param pSSM The saved state handle.
2164	*/
2165	static int pgmR3LoadPageToDevNullOld(PSSMHANDLE pSSM)
2166	{
2167	uint8_t abPage[PAGE_SIZE];
2168	return SSMR3GetMem(pSSM, &abPage[0], sizeof(abPage));
2169	}
2170
2171
2172	/**
2173	* Loads a page without any bits in the saved state, i.e. making sure it's
2174	* really zero.
2175	*
2176	* @returns VBox status code.
2177	* @param pVM The VM handle.
2178	* @param uType The page type or PGMPAGETYPE_INVALID (old saved
2179	* state).
2180	* @param pPage The guest page tracking structure.
2181	* @param GCPhys The page address.
2182	* @param pRam The ram range (logging).
2183	*/
2184	static int pgmR3LoadPageZeroOld(PVM pVM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2185	{
2186	if ( PGM_PAGE_GET_TYPE(pPage) != uType
2187	&& uType != PGMPAGETYPE_INVALID)
2188	return VERR_SSM_UNEXPECTED_DATA;
2189
2190	/* I think this should be sufficient. */
2191	if ( !PGM_PAGE_IS_ZERO(pPage)
2192	&& !PGM_PAGE_IS_BALLOONED(pPage))
2193	return VERR_SSM_UNEXPECTED_DATA;
2194
2195	NOREF(pVM);
2196	NOREF(GCPhys);
2197	NOREF(pRam);
2198	return VINF_SUCCESS;
2199	}
2200
2201
2202	/**
2203	* Loads a page from the saved state.
2204	*
2205	* @returns VBox status code.
2206	* @param pVM The VM handle.
2207	* @param pSSM The SSM handle.
2208	* @param uType The page type or PGMPAGETYEP_INVALID (old saved
2209	* state).
2210	* @param pPage The guest page tracking structure.
2211	* @param GCPhys The page address.
2212	* @param pRam The ram range (logging).
2213	*/
2214	static int pgmR3LoadPageBitsOld(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2215	{
2216	/*
2217	* Match up the type, dealing with MMIO2 aliases (dropped).
2218	*/
2219	AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == uType
2220	\|\| uType == PGMPAGETYPE_INVALID
2221	/* kudge for the expanded PXE bios (r67885) - #5687: */
2222	\|\| ( uType == PGMPAGETYPE_RAM
2223	&& GCPhys >= 0xed000
2224	&& GCPhys <= 0xeffff
2225	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_ROM)
2226	,
2227	("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc),
2228	VERR_SSM_UNEXPECTED_DATA);
2229
2230	/*
2231	* Load the page.
2232	*/
2233	void *pvPage;
2234	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvPage);
2235	if (RT_SUCCESS(rc))
2236	rc = SSMR3GetMem(pSSM, pvPage, PAGE_SIZE);
2237
2238	return rc;
2239	}
2240
2241
2242	/**
2243	* Loads a page (counter part to pgmR3SavePage).
2244	*
2245	* @returns VBox status code, fully bitched errors.
2246	* @param pVM The VM handle.
2247	* @param pSSM The SSM handle.
2248	* @param uType The page type.
2249	* @param pPage The page.
2250	* @param GCPhys The page address.
2251	* @param pRam The RAM range (for error messages).
2252	*/
2253	static int pgmR3LoadPageOld(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2254	{
2255	uint8_t uState;
2256	int rc = SSMR3GetU8(pSSM, &uState);
2257	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s rc=%Rrc\n", pPage, GCPhys, pRam->pszDesc, rc), rc);
2258	if (uState == 0 /* zero */)
2259	rc = pgmR3LoadPageZeroOld(pVM, uType, pPage, GCPhys, pRam);
2260	else if (uState == 1)
2261	rc = pgmR3LoadPageBitsOld(pVM, pSSM, uType, pPage, GCPhys, pRam);
2262	else
2263	rc = VERR_INTERNAL_ERROR;
2264	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] uState=%d uType=%d GCPhys=%RGp %s rc=%Rrc\n",
2265	pPage, uState, uType, GCPhys, pRam->pszDesc, rc),
2266	rc);
2267	return VINF_SUCCESS;
2268	}
2269
2270
2271	/**
2272	* Loads a shadowed ROM page.
2273	*
2274	* @returns VBox status code, errors are fully bitched.
2275	* @param pVM The VM handle.
2276	* @param pSSM The saved state handle.
2277	* @param pPage The page.
2278	* @param GCPhys The page address.
2279	* @param pRam The RAM range (for error messages).
2280	*/
2281	static int pgmR3LoadShadowedRomPageOld(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2282	{
2283	/*
2284	* Load and set the protection first, then load the two pages, the first
2285	* one is the active the other is the passive.
2286	*/
2287	PPGMROMPAGE pRomPage = pgmR3GetRomPage(pVM, GCPhys);
2288	AssertLogRelMsgReturn(pRomPage, ("GCPhys=%RGp %s\n", GCPhys, pRam->pszDesc), VERR_INTERNAL_ERROR);
2289
2290	uint8_t uProt;
2291	int rc = SSMR3GetU8(pSSM, &uProt);
2292	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc), rc);
2293	PGMROMPROT enmProt = (PGMROMPROT)uProt;
2294	AssertLogRelMsgReturn( enmProt >= PGMROMPROT_INVALID
2295	&& enmProt < PGMROMPROT_END,
2296	("enmProt=%d pPage=%R[pgmpage] GCPhys=%#x %s\n", enmProt, pPage, GCPhys, pRam->pszDesc),
2297	VERR_SSM_UNEXPECTED_DATA);
2298
2299	if (pRomPage->enmProt != enmProt)
2300	{
2301	rc = PGMR3PhysRomProtect(pVM, GCPhys, PAGE_SIZE, enmProt);
2302	AssertLogRelRCReturn(rc, rc);
2303	AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_INTERNAL_ERROR);
2304	}
2305
2306	PPGMPAGE pPageActive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
2307	PPGMPAGE pPagePassive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2308	uint8_t u8ActiveType = PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM : PGMPAGETYPE_ROM_SHADOW;
2309	uint8_t u8PassiveType= PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM_SHADOW : PGMPAGETYPE_ROM;
2310
2311	/** @todo this isn't entirely correct as long as pgmPhysGCPhys2CCPtrInternal is
2312	* used down the line (will the 2nd page will be written to the first
2313	* one because of a false TLB hit since the TLB is using GCPhys and
2314	* doesn't check the HCPhys of the desired page). */
2315	rc = pgmR3LoadPageOld(pVM, pSSM, u8ActiveType, pPage, GCPhys, pRam);
2316	if (RT_SUCCESS(rc))
2317	{
2318	pPageActive = pPage;
2319	rc = pgmR3LoadPageOld(pVM, pSSM, u8PassiveType, pPagePassive, GCPhys, pRam);
2320	}
2321	return rc;
2322	}
2323
2324	/**
2325	* Ram range flags and bits for older versions of the saved state.
2326	*
2327	* @returns VBox status code.
2328	*
2329	* @param pVM The VM handle
2330	* @param pSSM The SSM handle.
2331	* @param uVersion The saved state version.
2332	*/
2333	static int pgmR3LoadMemoryOld(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
2334	{
2335	PPGM pPGM = &pVM->pgm.s;
2336
2337	/*
2338	* Ram range flags and bits.
2339	*/
2340	uint32_t i = 0;
2341	for (PPGMRAMRANGE pRam = pPGM->pRamRangesXR3; ; pRam = pRam->pNextR3, i++)
2342	{
2343	/* Check the sequence number / separator. */
2344	uint32_t u32Sep;
2345	int rc = SSMR3GetU32(pSSM, &u32Sep);
2346	if (RT_FAILURE(rc))
2347	return rc;
2348	if (u32Sep == ~0U)
2349	break;
2350	if (u32Sep != i)
2351	{
2352	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2353	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2354	}
2355	AssertLogRelReturn(pRam, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2356
2357	/* Get the range details. */
2358	RTGCPHYS GCPhys;
2359	SSMR3GetGCPhys(pSSM, &GCPhys);
2360	RTGCPHYS GCPhysLast;
2361	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2362	RTGCPHYS cb;
2363	SSMR3GetGCPhys(pSSM, &cb);
2364	uint8_t fHaveBits;
2365	rc = SSMR3GetU8(pSSM, &fHaveBits);
2366	if (RT_FAILURE(rc))
2367	return rc;
2368	if (fHaveBits & ~1)
2369	{
2370	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2371	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2372	}
2373	size_t cchDesc = 0;
2374	char szDesc[256];
2375	szDesc[0] = '\0';
2376	if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2377	{
2378	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2379	if (RT_FAILURE(rc))
2380	return rc;
2381	/* Since we've modified the description strings in r45878, only compare
2382	them if the saved state is more recent. */
2383	if (uVersion != PGM_SAVED_STATE_VERSION_RR_DESC)
2384	cchDesc = strlen(szDesc);
2385	}
2386
2387	/*
2388	* Match it up with the current range.
2389	*
2390	* Note there is a hack for dealing with the high BIOS mapping
2391	* in the old saved state format, this means we might not have
2392	* a 1:1 match on success.
2393	*/
2394	if ( ( GCPhys != pRam->GCPhys
2395	\|\| GCPhysLast != pRam->GCPhysLast
2396	\|\| cb != pRam->cb
2397	\|\| ( cchDesc
2398	&& strcmp(szDesc, pRam->pszDesc)) )
2399	/* Hack for PDMDevHlpPhysReserve(pDevIns, 0xfff80000, 0x80000, "High ROM Region"); */
2400	&& ( uVersion != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE
2401	\|\| GCPhys != UINT32_C(0xfff80000)
2402	\|\| GCPhysLast != UINT32_C(0xffffffff)
2403	\|\| pRam->GCPhysLast != GCPhysLast
2404	\|\| pRam->GCPhys < GCPhys
2405	\|\| !fHaveBits)
2406	)
2407	{
2408	LogRel(("Ram range: %RGp-%RGp %RGp bytes %s %s\n"
2409	"State : %RGp-%RGp %RGp bytes %s %s\n",
2410	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits", pRam->pszDesc,
2411	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits", szDesc));
2412	/*
2413	* If we're loading a state for debugging purpose, don't make a fuss if
2414	* the MMIO and ROM stuff isn't 100% right, just skip the mismatches.
2415	*/
2416	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2417	\|\| GCPhys < 8 * _1M)
2418	return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2419	N_("RAM range mismatch; saved={%RGp-%RGp %RGp bytes %s %s} config={%RGp-%RGp %RGp bytes %s %s}"),
2420	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits", szDesc,
2421	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits", pRam->pszDesc);
2422
2423	AssertMsgFailed(("debug skipping not implemented, sorry\n"));
2424	continue;
2425	}
2426
2427	uint32_t cPages = (GCPhysLast - GCPhys + 1) >> PAGE_SHIFT;
2428	if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2429	{
2430	/*
2431	* Load the pages one by one.
2432	*/
2433	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2434	{
2435	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2436	PPGMPAGE pPage = &pRam->aPages[iPage];
2437	uint8_t uType;
2438	rc = SSMR3GetU8(pSSM, &uType);
2439	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] iPage=%#x GCPhysPage=%#x %s\n", pPage, iPage, GCPhysPage, pRam->pszDesc), rc);
2440	if (uType == PGMPAGETYPE_ROM_SHADOW)
2441	rc = pgmR3LoadShadowedRomPageOld(pVM, pSSM, pPage, GCPhysPage, pRam);
2442	else
2443	rc = pgmR3LoadPageOld(pVM, pSSM, uType, pPage, GCPhysPage, pRam);
2444	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2445	}
2446	}
2447	else
2448	{
2449	/*
2450	* Old format.
2451	*/
2452
2453	/* Of the page flags, pick up MMIO2 and ROM/RESERVED for the !fHaveBits case.
2454	The rest is generally irrelevant and wrong since the stuff have to match registrations. */
2455	uint32_t fFlags = 0;
2456	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2457	{
2458	uint16_t u16Flags;
2459	rc = SSMR3GetU16(pSSM, &u16Flags);
2460	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2461	fFlags \|= u16Flags;
2462	}
2463
2464	/* Load the bits */
2465	if ( !fHaveBits
2466	&& GCPhysLast < UINT32_C(0xe0000000))
2467	{
2468	/*
2469	* Dynamic chunks.
2470	*/
2471	const uint32_t cPagesInChunk = (110241024) >> PAGE_SHIFT;
2472	AssertLogRelMsgReturn(cPages % cPagesInChunk == 0,
2473	("cPages=%#x cPagesInChunk=%#x\n", cPages, cPagesInChunk, pRam->GCPhys, pRam->pszDesc),
2474	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2475
2476	for (uint32_t iPage = 0; iPage < cPages; /* incremented by inner loop */ )
2477	{
2478	uint8_t fPresent;
2479	rc = SSMR3GetU8(pSSM, &fPresent);
2480	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2481	AssertLogRelMsgReturn(fPresent == (uint8_t)true \|\| fPresent == (uint8_t)false,
2482	("fPresent=%#x iPage=%#x GCPhys=%#x %s\n", fPresent, iPage, pRam->GCPhys, pRam->pszDesc),
2483	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2484
2485	for (uint32_t iChunkPage = 0; iChunkPage < cPagesInChunk; iChunkPage++, iPage++)
2486	{
2487	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2488	PPGMPAGE pPage = &pRam->aPages[iPage];
2489	if (fPresent)
2490	{
2491	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO)
2492	rc = pgmR3LoadPageToDevNullOld(pSSM);
2493	else
2494	rc = pgmR3LoadPageBitsOld(pVM, pSSM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2495	}
2496	else
2497	rc = pgmR3LoadPageZeroOld(pVM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2498	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2499	}
2500	}
2501	}
2502	else if (pRam->pvR3)
2503	{
2504	/*
2505	* MMIO2.
2506	*/
2507	AssertLogRelMsgReturn((fFlags & 0x0f) == RT_BIT(3) /MM_RAM_FLAGS_MMIO2/,
2508	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2509	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2510	AssertLogRelMsgReturn(pRam->pvR3,
2511	("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc),
2512	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2513
2514	rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2515	AssertLogRelMsgRCReturn(rc, ("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc), rc);
2516	}
2517	else if (GCPhysLast < UINT32_C(0xfff80000))
2518	{
2519	/*
2520	* PCI MMIO, no pages saved.
2521	*/
2522	}
2523	else
2524	{
2525	/*
2526	* Load the 0xfff80000..0xffffffff BIOS range.
2527	* It starts with X reserved pages that we have to skip over since
2528	* the RAMRANGE create by the new code won't include those.
2529	*/
2530	AssertLogRelMsgReturn( !(fFlags & RT_BIT(3) /MM_RAM_FLAGS_MMIO2/)
2531	&& (fFlags & RT_BIT(0) /MM_RAM_FLAGS_RESERVED/),
2532	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2533	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2534	AssertLogRelMsgReturn(GCPhys == UINT32_C(0xfff80000),
2535	("GCPhys=%RGp pRamRange{GCPhys=%#x %s}\n", GCPhys, pRam->GCPhys, pRam->pszDesc),
2536	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2537
2538	/* Skip wasted reserved pages before the ROM. */
2539	while (GCPhys < pRam->GCPhys)
2540	{
2541	rc = pgmR3LoadPageToDevNullOld(pSSM);
2542	GCPhys += PAGE_SIZE;
2543	}
2544
2545	/* Load the bios pages. */
2546	cPages = pRam->cb >> PAGE_SHIFT;
2547	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2548	{
2549	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2550	PPGMPAGE pPage = &pRam->aPages[iPage];
2551
2552	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_ROM,
2553	("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, GCPhys),
2554	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2555	rc = pgmR3LoadPageBitsOld(pVM, pSSM, PGMPAGETYPE_ROM, pPage, GCPhysPage, pRam);
2556	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2557	}
2558	}
2559	}
2560	}
2561
2562	return VINF_SUCCESS;
2563	}
2564
2565
2566	/**
2567	* Worker for pgmR3Load and pgmR3LoadLocked.
2568	*
2569	* @returns VBox status code.
2570	*
2571	* @param pVM The VM handle.
2572	* @param pSSM The SSM handle.
2573	* @param uVersion The PGM saved state unit version.
2574	* @param uPass The pass number.
2575	*
2576	* @todo This needs splitting up if more record types or code twists are
2577	* added...
2578	*/
2579	static int pgmR3LoadMemory(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2580	{
2581	/*
2582	* Process page records until we hit the terminator.
2583	*/
2584	RTGCPHYS GCPhys = NIL_RTGCPHYS;
2585	PPGMRAMRANGE pRamHint = NULL;
2586	uint8_t id = UINT8_MAX;
2587	uint32_t iPage = UINT32_MAX - 10;
2588	PPGMROMRANGE pRom = NULL;
2589	PPGMMMIO2RANGE pMmio2 = NULL;
2590
2591	/*
2592	* We batch up pages that should be freed instead of calling GMM for
2593	* each and every one of them. Note that we'll lose the pages in most
2594	* failure paths - this should probably be addressed one day.
2595	*/
2596	uint32_t cPendingPages = 0;
2597	PGMMFREEPAGESREQ pReq;
2598	int rc = GMMR3FreePagesPrepare(pVM, &pReq, 128 /* batch size */, GMMACCOUNT_BASE);
2599	AssertLogRelRCReturn(rc, rc);
2600
2601	for (;;)
2602	{
2603	/*
2604	* Get the record type and flags.
2605	*/
2606	uint8_t u8;
2607	rc = SSMR3GetU8(pSSM, &u8);
2608	if (RT_FAILURE(rc))
2609	return rc;
2610	if (u8 == PGM_STATE_REC_END)
2611	{
2612	/*
2613	* Finish off any pages pending freeing.
2614	*/
2615	if (cPendingPages)
2616	{
2617	Log(("pgmR3LoadMemory: GMMR3FreePagesPerform pVM=%p cPendingPages=%u\n", pVM, cPendingPages));
2618	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2619	AssertLogRelRCReturn(rc, rc);
2620	}
2621	GMMR3FreePagesCleanup(pReq);
2622	return VINF_SUCCESS;
2623	}
2624	AssertLogRelMsgReturn((u8 & ~PGM_STATE_REC_FLAG_ADDR) <= PGM_STATE_REC_LAST, ("%#x\n", u8), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2625	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2626	{
2627	/*
2628	* RAM page.
2629	*/
2630	case PGM_STATE_REC_RAM_ZERO:
2631	case PGM_STATE_REC_RAM_RAW:
2632	case PGM_STATE_REC_RAM_BALLOONED:
2633	{
2634	/*
2635	* Get the address and resolve it into a page descriptor.
2636	*/
2637	if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2638	GCPhys += PAGE_SIZE;
2639	else
2640	{
2641	rc = SSMR3GetGCPhys(pSSM, &GCPhys);
2642	if (RT_FAILURE(rc))
2643	return rc;
2644	}
2645	AssertLogRelMsgReturn(!(GCPhys & PAGE_OFFSET_MASK), ("%RGp\n", GCPhys), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2646
2647	PPGMPAGE pPage;
2648	rc = pgmPhysGetPageWithHintEx(pVM, GCPhys, &pPage, &pRamHint);
2649	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc %RGp\n", rc, GCPhys), rc);
2650
2651	/*
2652	* Take action according to the record type.
2653	*/
2654	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2655	{
2656	case PGM_STATE_REC_RAM_ZERO:
2657	{
2658	if (PGM_PAGE_IS_ZERO(pPage))
2659	break;
2660
2661	/* Ballooned pages must be unmarked (live snapshot and
2662	teleportation scenarios). */
2663	if (PGM_PAGE_IS_BALLOONED(pPage))
2664	{
2665	Assert(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM);
2666	if (uVersion == PGM_SAVED_STATE_VERSION_BALLOON_BROKEN)
2667	break;
2668	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO);
2669	break;
2670	}
2671
2672	AssertLogRelMsgReturn(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED, ("GCPhys=%RGp %R[pgmpage]\n", GCPhys, pPage), VERR_INTERNAL_ERROR_5);
2673
2674	/* If this is a ROM page, we must clear it and not try
2675	free it... */
2676	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_ROM
2677	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_ROM_SHADOW)
2678	{
2679	void *pvDstPage;
2680	rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvDstPage);
2681	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp %R[pgmpage] rc=%Rrc\n", GCPhys, pPage, rc), rc);
2682	ASMMemZeroPage(pvDstPage);
2683	}
2684	/* Free it only if it's not part of a previously
2685	allocated large page (no need to clear the page). */
2686	else if ( PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE
2687	&& PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE_DISABLED)
2688	{
2689	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, GCPhys);
2690	AssertRCReturn(rc, rc);
2691	}
2692	/** @todo handle large pages (see #5545) */
2693	break;
2694	}
2695
2696	case PGM_STATE_REC_RAM_BALLOONED:
2697	{
2698	Assert(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM);
2699	if (PGM_PAGE_IS_BALLOONED(pPage))
2700	break;
2701
2702	/* We don't map ballooned pages in our shadow page tables, let's
2703	just free it if allocated and mark as ballooned. See #5515. */
2704	if (PGM_PAGE_IS_ALLOCATED(pPage))
2705	{
2706	/** @todo handle large pages + ballooning when it works. (see #5515, #5545). */
2707	AssertLogRelMsgReturn( PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE
2708	&& PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE_DISABLED,
2709	("GCPhys=%RGp %R[pgmpage]\n", GCPhys, pPage), VERR_INTERNAL_ERROR_5);
2710
2711	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, GCPhys);
2712	AssertRCReturn(rc, rc);
2713	}
2714	Assert(PGM_PAGE_IS_ZERO(pPage));
2715	PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_BALLOONED);
2716	break;
2717	}
2718
2719	case PGM_STATE_REC_RAM_RAW:
2720	{
2721	void *pvDstPage;
2722	rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvDstPage);
2723	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp %R[pgmpage] rc=%Rrc\n", GCPhys, pPage, rc), rc);
2724	rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2725	if (RT_FAILURE(rc))
2726	return rc;
2727	break;
2728	}
2729
2730	default:
2731	AssertMsgFailedReturn(("%#x\n", u8), VERR_INTERNAL_ERROR);
2732	}
2733	id = UINT8_MAX;
2734	break;
2735	}
2736
2737	/*
2738	* MMIO2 page.
2739	*/
2740	case PGM_STATE_REC_MMIO2_RAW:
2741	case PGM_STATE_REC_MMIO2_ZERO:
2742	{
2743	/*
2744	* Get the ID + page number and resolved that into a MMIO2 page.
2745	*/
2746	if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2747	iPage++;
2748	else
2749	{
2750	SSMR3GetU8(pSSM, &id);
2751	rc = SSMR3GetU32(pSSM, &iPage);
2752	if (RT_FAILURE(rc))
2753	return rc;
2754	}
2755	if ( !pMmio2
2756	\|\| pMmio2->idSavedState != id)
2757	{
2758	for (pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
2759	if (pMmio2->idSavedState == id)
2760	break;
2761	AssertLogRelMsgReturn(pMmio2, ("id=%#u iPage=%#x\n", id, iPage), VERR_INTERNAL_ERROR);
2762	}
2763	AssertLogRelMsgReturn(iPage < (pMmio2->RamRange.cb >> PAGE_SHIFT), ("iPage=%#x cb=%RGp %s\n", iPage, pMmio2->RamRange.cb, pMmio2->RamRange.pszDesc), VERR_INTERNAL_ERROR);
2764	void pvDstPage = (uint8_t )pMmio2->RamRange.pvR3 + ((size_t)iPage << PAGE_SHIFT);
2765
2766	/*
2767	* Load the page bits.
2768	*/
2769	if ((u8 & ~PGM_STATE_REC_FLAG_ADDR) == PGM_STATE_REC_MMIO2_ZERO)
2770	ASMMemZeroPage(pvDstPage);
2771	else
2772	{
2773	rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2774	if (RT_FAILURE(rc))
2775	return rc;
2776	}
2777	GCPhys = NIL_RTGCPHYS;
2778	break;
2779	}
2780
2781	/*
2782	* ROM pages.
2783	*/
2784	case PGM_STATE_REC_ROM_VIRGIN:
2785	case PGM_STATE_REC_ROM_SHW_RAW:
2786	case PGM_STATE_REC_ROM_SHW_ZERO:
2787	case PGM_STATE_REC_ROM_PROT:
2788	{
2789	/*
2790	* Get the ID + page number and resolved that into a ROM page descriptor.
2791	*/
2792	if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2793	iPage++;
2794	else
2795	{
2796	SSMR3GetU8(pSSM, &id);
2797	rc = SSMR3GetU32(pSSM, &iPage);
2798	if (RT_FAILURE(rc))
2799	return rc;
2800	}
2801	if ( !pRom
2802	\|\| pRom->idSavedState != id)
2803	{
2804	for (pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
2805	if (pRom->idSavedState == id)
2806	break;
2807	AssertLogRelMsgReturn(pRom, ("id=%#u iPage=%#x\n", id, iPage), VERR_INTERNAL_ERROR);
2808	}
2809	AssertLogRelMsgReturn(iPage < (pRom->cb >> PAGE_SHIFT), ("iPage=%#x cb=%RGp %s\n", iPage, pRom->cb, pRom->pszDesc), VERR_INTERNAL_ERROR);
2810	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
2811	GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
2812
2813	/*
2814	* Get and set the protection.
2815	*/
2816	uint8_t u8Prot;
2817	rc = SSMR3GetU8(pSSM, &u8Prot);
2818	if (RT_FAILURE(rc))
2819	return rc;
2820	PGMROMPROT enmProt = (PGMROMPROT)u8Prot;
2821	AssertLogRelMsgReturn(enmProt > PGMROMPROT_INVALID && enmProt < PGMROMPROT_END, ("GCPhys=%RGp enmProt=%d\n", GCPhys, enmProt), VERR_INTERNAL_ERROR);
2822
2823	if (enmProt != pRomPage->enmProt)
2824	{
2825	if (RT_UNLIKELY(!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)))
2826	return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2827	N_("Protection change of unshadowed ROM page: GCPhys=%RGp enmProt=%d %s"),
2828	GCPhys, enmProt, pRom->pszDesc);
2829	rc = PGMR3PhysRomProtect(pVM, GCPhys, PAGE_SIZE, enmProt);
2830	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp rc=%Rrc\n", GCPhys, rc), rc);
2831	AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_INTERNAL_ERROR);
2832	}
2833	if ((u8 & ~PGM_STATE_REC_FLAG_ADDR) == PGM_STATE_REC_ROM_PROT)
2834	break; /* done */
2835
2836	/*
2837	* Get the right page descriptor.
2838	*/
2839	PPGMPAGE pRealPage;
2840	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2841	{
2842	case PGM_STATE_REC_ROM_VIRGIN:
2843	if (!PGMROMPROT_IS_ROM(enmProt))
2844	pRealPage = &pRomPage->Virgin;
2845	else
2846	pRealPage = NULL;
2847	break;
2848
2849	case PGM_STATE_REC_ROM_SHW_RAW:
2850	case PGM_STATE_REC_ROM_SHW_ZERO:
2851	if (RT_UNLIKELY(!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)))
2852	return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2853	N_("Shadowed / non-shadowed page type mismatch: GCPhys=%RGp enmProt=%d %s"),
2854	GCPhys, enmProt, pRom->pszDesc);
2855	if (PGMROMPROT_IS_ROM(enmProt))
2856	pRealPage = &pRomPage->Shadow;
2857	else
2858	pRealPage = NULL;
2859	break;
2860
2861	default: AssertLogRelFailedReturn(VERR_INTERNAL_ERROR); /* shut up gcc */
2862	}
2863	if (!pRealPage)
2864	{
2865	rc = pgmPhysGetPageWithHintEx(pVM, GCPhys, &pRealPage, &pRamHint);
2866	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc %RGp\n", rc, GCPhys), rc);
2867	}
2868
2869	/*
2870	* Make it writable and map it (if necessary).
2871	*/
2872	void *pvDstPage = NULL;
2873	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2874	{
2875	case PGM_STATE_REC_ROM_SHW_ZERO:
2876	if ( PGM_PAGE_IS_ZERO(pRealPage)
2877	\|\| PGM_PAGE_IS_BALLOONED(pRealPage))
2878	break;
2879	/** @todo implement zero page replacing. */
2880	/* fall thru */
2881	case PGM_STATE_REC_ROM_VIRGIN:
2882	case PGM_STATE_REC_ROM_SHW_RAW:
2883	{
2884	rc = pgmPhysPageMakeWritableAndMap(pVM, pRealPage, GCPhys, &pvDstPage);
2885	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp rc=%Rrc\n", GCPhys, rc), rc);
2886	break;
2887	}
2888	}
2889
2890	/*
2891	* Load the bits.
2892	*/
2893	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2894	{
2895	case PGM_STATE_REC_ROM_SHW_ZERO:
2896	if (pvDstPage)
2897	ASMMemZeroPage(pvDstPage);
2898	break;
2899
2900	case PGM_STATE_REC_ROM_VIRGIN:
2901	case PGM_STATE_REC_ROM_SHW_RAW:
2902	rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2903	if (RT_FAILURE(rc))
2904	return rc;
2905	break;
2906	}
2907	GCPhys = NIL_RTGCPHYS;
2908	break;
2909	}
2910
2911	/*
2912	* Unknown type.
2913	*/
2914	default:
2915	AssertLogRelMsgFailedReturn(("%#x\n", u8), VERR_INTERNAL_ERROR);
2916	}
2917	} /* forever */
2918	}
2919
2920
2921	/**
2922	* Worker for pgmR3Load.
2923	*
2924	* @returns VBox status code.
2925	*
2926	* @param pVM The VM handle.
2927	* @param pSSM The SSM handle.
2928	* @param uVersion The saved state version.
2929	*/
2930	static int pgmR3LoadFinalLocked(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
2931	{
2932	PPGM pPGM = &pVM->pgm.s;
2933	int rc;
2934	uint32_t u32Sep;
2935
2936	/*
2937	* Load basic data (required / unaffected by relocation).
2938	*/
2939	if (uVersion >= PGM_SAVED_STATE_VERSION_3_0_0)
2940	{
2941	if (uVersion > PGM_SAVED_STATE_VERSION_PRE_BALLOON)
2942	rc = SSMR3GetStruct(pSSM, pPGM, &s_aPGMFields[0]);
2943	else
2944	rc = SSMR3GetStruct(pSSM, pPGM, &s_aPGMFieldsPreBalloon[0]);
2945
2946	AssertLogRelRCReturn(rc, rc);
2947
2948	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2949	{
2950	if (uVersion <= PGM_SAVED_STATE_VERSION_PRE_PAE)
2951	rc = SSMR3GetStruct(pSSM, &pVM->aCpus[i].pgm.s, &s_aPGMCpuFieldsPrePae[0]);
2952	else
2953	rc = SSMR3GetStruct(pSSM, &pVM->aCpus[i].pgm.s, &s_aPGMCpuFields[0]);
2954	AssertLogRelRCReturn(rc, rc);
2955	}
2956	}
2957	else if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2958	{
2959	AssertRelease(pVM->cCpus == 1);
2960
2961	PGMOLD pgmOld;
2962	rc = SSMR3GetStruct(pSSM, &pgmOld, &s_aPGMFields_Old[0]);
2963	AssertLogRelRCReturn(rc, rc);
2964
2965	pPGM->fMappingsFixed = pgmOld.fMappingsFixed;
2966	pPGM->GCPtrMappingFixed = pgmOld.GCPtrMappingFixed;
2967	pPGM->cbMappingFixed = pgmOld.cbMappingFixed;
2968
2969	pVM->aCpus[0].pgm.s.fA20Enabled = pgmOld.fA20Enabled;
2970	pVM->aCpus[0].pgm.s.GCPhysA20Mask = pgmOld.GCPhysA20Mask;
2971	pVM->aCpus[0].pgm.s.enmGuestMode = pgmOld.enmGuestMode;
2972	}
2973	else
2974	{
2975	AssertRelease(pVM->cCpus == 1);
2976
2977	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2978	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2979	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2980
2981	uint32_t cbRamSizeIgnored;
2982	rc = SSMR3GetU32(pSSM, &cbRamSizeIgnored);
2983	if (RT_FAILURE(rc))
2984	return rc;
2985	SSMR3GetGCPhys(pSSM, &pVM->aCpus[0].pgm.s.GCPhysA20Mask);
2986
2987	uint32_t u32 = 0;
2988	SSMR3GetUInt(pSSM, &u32);
2989	pVM->aCpus[0].pgm.s.fA20Enabled = !!u32;
2990	SSMR3GetUInt(pSSM, &pVM->aCpus[0].pgm.s.fSyncFlags);
2991	RTUINT uGuestMode;
2992	SSMR3GetUInt(pSSM, &uGuestMode);
2993	pVM->aCpus[0].pgm.s.enmGuestMode = (PGMMODE)uGuestMode;
2994
2995	/* check separator. */
2996	SSMR3GetU32(pSSM, &u32Sep);
2997	if (RT_FAILURE(rc))
2998	return rc;
2999	if (u32Sep != (uint32_t)~0)
3000	{
3001	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
3002	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
3003	}
3004	}
3005
3006	/*
3007	* The guest mappings - skipped now, see re-fixation in the caller.
3008	*/
3009	if (uVersion <= PGM_SAVED_STATE_VERSION_PRE_PAE)
3010	{
3011	for (uint32_t i = 0; ; i++)
3012	{
3013	rc = SSMR3GetU32(pSSM, &u32Sep); /* sequence number */
3014	if (RT_FAILURE(rc))
3015	return rc;
3016	if (u32Sep == ~0U)
3017	break;
3018	AssertMsgReturn(u32Sep == i, ("u32Sep=%#x i=%#x\n", u32Sep, i), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
3019
3020	char szDesc[256];
3021	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
3022	if (RT_FAILURE(rc))
3023	return rc;
3024	RTGCPTR GCPtrIgnore;
3025	SSMR3GetGCPtr(pSSM, &GCPtrIgnore); /* GCPtr */
3026	rc = SSMR3GetGCPtr(pSSM, &GCPtrIgnore); /* cPTs */
3027	if (RT_FAILURE(rc))
3028	return rc;
3029	}
3030	}
3031
3032	/*
3033	* Load the RAM contents.
3034	*/
3035	if (uVersion > PGM_SAVED_STATE_VERSION_3_0_0)
3036	{
3037	if (!pVM->pgm.s.LiveSave.fActive)
3038	{
3039	if (uVersion > PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
3040	{
3041	rc = pgmR3LoadRamConfig(pVM, pSSM);
3042	if (RT_FAILURE(rc))
3043	return rc;
3044	}
3045	rc = pgmR3LoadRomRanges(pVM, pSSM);
3046	if (RT_FAILURE(rc))
3047	return rc;
3048	rc = pgmR3LoadMmio2Ranges(pVM, pSSM);
3049	if (RT_FAILURE(rc))
3050	return rc;
3051	}
3052
3053	rc = pgmR3LoadMemory(pVM, pSSM, uVersion, SSM_PASS_FINAL);
3054	}
3055	else
3056	rc = pgmR3LoadMemoryOld(pVM, pSSM, uVersion);
3057
3058	/* Refresh balloon accounting. */
3059	if (pVM->pgm.s.cBalloonedPages)
3060	{
3061	Log(("pgmR3LoadFinalLocked: pVM=%p cBalloonedPages=%#x\n", pVM, pVM->pgm.s.cBalloonedPages));
3062	rc = GMMR3BalloonedPages(pVM, GMMBALLOONACTION_INFLATE, pVM->pgm.s.cBalloonedPages);
3063	AssertRCReturn(rc, rc);
3064	}
3065	return rc;
3066	}
3067
3068
3069	/**
3070	* Execute state load operation.
3071	*
3072	* @returns VBox status code.
3073	* @param pVM VM Handle.
3074	* @param pSSM SSM operation handle.
3075	* @param uVersion Data layout version.
3076	* @param uPass The data pass.
3077	*/
3078	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3079	{
3080	int rc;
3081	PPGM pPGM = &pVM->pgm.s;
3082
3083	/*
3084	* Validate version.
3085	*/
3086	if ( ( uPass != SSM_PASS_FINAL
3087	&& uVersion != PGM_SAVED_STATE_VERSION
3088	&& uVersion != PGM_SAVED_STATE_VERSION_PRE_PAE
3089	&& uVersion != PGM_SAVED_STATE_VERSION_BALLOON_BROKEN
3090	&& uVersion != PGM_SAVED_STATE_VERSION_PRE_BALLOON
3091	&& uVersion != PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
3092	\|\| ( uVersion != PGM_SAVED_STATE_VERSION
3093	&& uVersion != PGM_SAVED_STATE_VERSION_PRE_PAE
3094	&& uVersion != PGM_SAVED_STATE_VERSION_BALLOON_BROKEN
3095	&& uVersion != PGM_SAVED_STATE_VERSION_PRE_BALLOON
3096	&& uVersion != PGM_SAVED_STATE_VERSION_NO_RAM_CFG
3097	&& uVersion != PGM_SAVED_STATE_VERSION_3_0_0
3098	&& uVersion != PGM_SAVED_STATE_VERSION_2_2_2
3099	&& uVersion != PGM_SAVED_STATE_VERSION_RR_DESC
3100	&& uVersion != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE)
3101	)
3102	{
3103	AssertMsgFailed(("pgmR3Load: Invalid version uVersion=%d (current %d)!\n", uVersion, PGM_SAVED_STATE_VERSION));
3104	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3105	}
3106
3107	/*
3108	* Do the loading while owning the lock because a bunch of the functions
3109	* we're using requires this.
3110	*/
3111	if (uPass != SSM_PASS_FINAL)
3112	{
3113	pgmLock(pVM);
3114	if (uPass != 0)
3115	rc = pgmR3LoadMemory(pVM, pSSM, uVersion, uPass);
3116	else
3117	{
3118	pVM->pgm.s.LiveSave.fActive = true;
3119	if (uVersion > PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
3120	rc = pgmR3LoadRamConfig(pVM, pSSM);
3121	else
3122	rc = VINF_SUCCESS;
3123	if (RT_SUCCESS(rc))
3124	rc = pgmR3LoadRomRanges(pVM, pSSM);
3125	if (RT_SUCCESS(rc))
3126	rc = pgmR3LoadMmio2Ranges(pVM, pSSM);
3127	if (RT_SUCCESS(rc))
3128	rc = pgmR3LoadMemory(pVM, pSSM, uVersion, uPass);
3129	}
3130	pgmUnlock(pVM);
3131	}
3132	else
3133	{
3134	pgmLock(pVM);
3135	rc = pgmR3LoadFinalLocked(pVM, pSSM, uVersion);
3136	pVM->pgm.s.LiveSave.fActive = false;
3137	pgmUnlock(pVM);
3138	if (RT_SUCCESS(rc))
3139	{
3140	/*
3141	* We require a full resync now.
3142	*/
3143	for (VMCPUID i = 0; i < pVM->cCpus; i++)
3144	{
3145	PVMCPU pVCpu = &pVM->aCpus[i];
3146	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
3147	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3148	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
3149	/** @todo For guest PAE, we might get the wrong
3150	* aGCPhysGstPaePDs values now. We should used the
3151	* saved ones... Postponing this since it nothing new
3152	* and PAE/PDPTR needs some general readjusting, see
3153	* @bugref{#5880}. */
3154	}
3155
3156	pgmR3HandlerPhysicalUpdateAll(pVM);
3157
3158	/*
3159	* Change the paging mode and restore PGMCPU::GCPhysCR3.
3160	* (The latter requires the CPUM state to be restored already.)
3161	*/
3162	if (CPUMR3IsStateRestorePending(pVM))
3163	return SSMR3SetLoadError(pSSM, VERR_WRONG_ORDER, RT_SRC_POS,
3164	N_("PGM was unexpectedly restored before CPUM"));
3165
3166	for (VMCPUID i = 0; i < pVM->cCpus; i++)
3167	{
3168	PVMCPU pVCpu = &pVM->aCpus[i];
3169
3170	rc = PGMR3ChangeMode(pVM, pVCpu, pVCpu->pgm.s.enmGuestMode);
3171	AssertLogRelRCReturn(rc, rc);
3172
3173	/* Update pVM->pgm.s.GCPhysCR3. */
3174	Assert(pVCpu->pgm.s.GCPhysCR3 == NIL_RTGCPHYS \|\| FTMIsDeltaLoadSaveActive(pVM));
3175	RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVCpu);
3176	if ( pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE
3177	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE_NX
3178	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_AMD64
3179	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
3180	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
3181	else
3182	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
3183	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
3184
3185	/* Update the PSE, NX flags and validity masks. */
3186	pVCpu->pgm.s.fGst32BitPageSizeExtension = CPUMIsGuestPageSizeExtEnabled(pVCpu);
3187	PGMNotifyNxeChanged(pVCpu, CPUMIsGuestNXEnabled(pVCpu));
3188	}
3189
3190	/*
3191	* Try re-fixate the guest mappings.
3192	*/
3193	pVM->pgm.s.fMappingsFixedRestored = false;
3194	if ( pVM->pgm.s.fMappingsFixed
3195	&& pgmMapAreMappingsEnabled(pVM))
3196	{
3197	RTGCPTR GCPtrFixed = pVM->pgm.s.GCPtrMappingFixed;
3198	uint32_t cbFixed = pVM->pgm.s.cbMappingFixed;
3199	pVM->pgm.s.fMappingsFixed = false;
3200
3201	uint32_t cbRequired;
3202	int rc2 = PGMR3MappingsSize(pVM, &cbRequired); AssertRC(rc2);
3203	if ( RT_SUCCESS(rc2)
3204	&& cbRequired > cbFixed)
3205	rc2 = VERR_OUT_OF_RANGE;
3206	if (RT_SUCCESS(rc2))
3207	rc2 = pgmR3MappingsFixInternal(pVM, GCPtrFixed, cbFixed);
3208	if (RT_FAILURE(rc2))
3209	{
3210	LogRel(("PGM: Unable to re-fixate the guest mappings at %RGv-%RGv: rc=%Rrc (cbRequired=%#x)\n",
3211	GCPtrFixed, GCPtrFixed + cbFixed, rc2, cbRequired));
3212	pVM->pgm.s.fMappingsFixed = false;
3213	pVM->pgm.s.fMappingsFixedRestored = true;
3214	pVM->pgm.s.GCPtrMappingFixed = GCPtrFixed;
3215	pVM->pgm.s.cbMappingFixed = cbFixed;
3216	}
3217	}
3218	else
3219	{
3220	/* We used to set fixed + disabled while we only use disabled now,
3221	so wipe the state to avoid any confusion. */
3222	pVM->pgm.s.fMappingsFixed = false;
3223	pVM->pgm.s.GCPtrMappingFixed = NIL_RTGCPTR;
3224	pVM->pgm.s.cbMappingFixed = 0;
3225	}
3226
3227	/*
3228	* If we have floating mappings, do a CR3 sync now to make sure the HMA
3229	* doesn't conflict with guest code / data and thereby cause trouble
3230	* when restoring other components like PATM.
3231	*/
3232	if (pgmMapAreMappingsFloating(pVM))
3233	{
3234	PVMCPU pVCpu = &pVM->aCpus[0];
3235	rc = PGMSyncCR3(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu), true);
3236	if (RT_FAILURE(rc))
3237	return SSMR3SetLoadError(pSSM, VERR_WRONG_ORDER, RT_SRC_POS,
3238	N_("PGMSyncCR3 failed unexpectedly with rc=%Rrc"), rc);
3239
3240	/* Make sure to re-sync before executing code. */
3241	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
3242	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3243	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
3244	}
3245	}
3246	}
3247
3248	return rc;
3249	}
3250
3251
3252	/**
3253	* Registers the saved state callbacks with SSM.
3254	*
3255	* @returns VBox status code.
3256	* @param pVM Pointer to VM structure.
3257	* @param cbRam The RAM size.
3258	*/
3259	int pgmR3InitSavedState(PVM pVM, uint64_t cbRam)
3260	{
3261	return SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
3262	pgmR3LivePrep, pgmR3LiveExec, pgmR3LiveVote,
3263	NULL, pgmR3SaveExec, pgmR3SaveDone,
3264	pgmR3LoadPrep, pgmR3Load, NULL);
3265	}
3266

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source: vbox/trunk/src/VBox/VMM/VMMR3/PGMSavedState.cpp@ 38838

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