NEMR3Native-linux.cpp@ 92521

最後變更在這個檔案從92521是 92520,由 vboxsync 提交於 3 年前
VMM/NEM-linux,EM: The interrupt injection code in emR3ForcedActions is ASSUMING that no interrupt state is external when it's considering calling TRPMR3InjectEvent. So, make sure the NEM-linux code import this state when returning to the EM loop and make sure we don't try inject more than one interrupt at a time. bugref:9044
屬性 svn:eol-style 設為 `native` 屬性 svn:keywords 設為 `Author Date Id Revision`
檔案大小: 104.9 KB

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1	/* $Id: NEMR3Native-linux.cpp 92520 2021-11-20 02:19:53Z vboxsync $ */
2	/** @file
3	* NEM - Native execution manager, native ring-3 Linux backend.
4	*/
5
6	/*
7	* Copyright (C) 2021 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.alldomusa.eu.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_NEM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include <VBox/vmm/nem.h>
25	#include <VBox/vmm/iem.h>
26	#include <VBox/vmm/em.h>
27	#include <VBox/vmm/apic.h>
28	#include <VBox/vmm/pdm.h>
29	#include <VBox/vmm/trpm.h>
30	#include "NEMInternal.h"
31	#include <VBox/vmm/vmcc.h>
32
33	#include <iprt/alloca.h>
34	#include <iprt/string.h>
35	#include <iprt/system.h>
36
37	#include <errno.h>
38	#include <unistd.h>
39	#include <sys/ioctl.h>
40	#include <sys/fcntl.h>
41	#include <sys/mman.h>
42	#include <linux/kvm.h>
43
44	/*
45	* Supply stuff missing from the kvm.h on the build box.
46	*/
47	#ifndef KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON /* since 5.4 */
48	# define KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON 4
49	#endif
50
51
52
53	/**
54	* Worker for nemR3NativeInit that gets the hypervisor capabilities.
55	*
56	* @returns VBox status code.
57	* @param pVM The cross context VM structure.
58	* @param pErrInfo Where to always return error info.
59	*/
60	static int nemR3LnxInitCheckCapabilities(PVM pVM, PRTERRINFO pErrInfo)
61	{
62	AssertReturn(pVM->nem.s.fdVm != -1, RTErrInfoSet(pErrInfo, VERR_WRONG_ORDER, "Wrong initalization order"));
63
64	/*
65	* Capabilities.
66	*/
67	static const struct
68	{
69	const char *pszName;
70	int iCap;
71	uint32_t offNem : 24;
72	uint32_t cbNem : 3;
73	uint32_t fReqNonZero : 1;
74	uint32_t uReserved : 4;
75	} s_aCaps[] =
76	{
77	#define CAP_ENTRY__L(a_Define) { #a_Define, a_Define, UINT32_C(0x00ffffff), 0, 0, 0 }
78	#define CAP_ENTRY__S(a_Define, a_Member) { #a_Define, a_Define, RT_UOFFSETOF(NEM, a_Member), RT_SIZEOFMEMB(NEM, a_Member), 0, 0 }
79	#define CAP_ENTRY_MS(a_Define, a_Member) { #a_Define, a_Define, RT_UOFFSETOF(NEM, a_Member), RT_SIZEOFMEMB(NEM, a_Member), 1, 0 }
80	#define CAP_ENTRY__U(a_Number) { "KVM_CAP_" #a_Number, a_Number, UINT32_C(0x00ffffff), 0, 0, 0 }
81	#define CAP_ENTRY_ML(a_Number) { "KVM_CAP_" #a_Number, a_Number, UINT32_C(0x00ffffff), 0, 1, 0 }
82
83	CAP_ENTRY__L(KVM_CAP_IRQCHIP), /* 0 */
84	CAP_ENTRY_ML(KVM_CAP_HLT),
85	CAP_ENTRY__L(KVM_CAP_MMU_SHADOW_CACHE_CONTROL),
86	CAP_ENTRY_ML(KVM_CAP_USER_MEMORY),
87	CAP_ENTRY__L(KVM_CAP_SET_TSS_ADDR),
88	CAP_ENTRY__U(5),
89	CAP_ENTRY__L(KVM_CAP_VAPIC),
90	CAP_ENTRY__L(KVM_CAP_EXT_CPUID),
91	CAP_ENTRY__L(KVM_CAP_CLOCKSOURCE),
92	CAP_ENTRY__L(KVM_CAP_NR_VCPUS),
93	CAP_ENTRY_MS(KVM_CAP_NR_MEMSLOTS, cMaxMemSlots), /* 10 */
94	CAP_ENTRY__L(KVM_CAP_PIT),
95	CAP_ENTRY__L(KVM_CAP_NOP_IO_DELAY),
96	CAP_ENTRY__L(KVM_CAP_PV_MMU),
97	CAP_ENTRY__L(KVM_CAP_MP_STATE),
98	CAP_ENTRY__L(KVM_CAP_COALESCED_MMIO),
99	CAP_ENTRY__L(KVM_CAP_SYNC_MMU),
100	CAP_ENTRY__U(17),
101	CAP_ENTRY__L(KVM_CAP_IOMMU),
102	CAP_ENTRY__U(19), /* Buggy KVM_CAP_JOIN_MEMORY_REGIONS? */
103	CAP_ENTRY__U(20), /* Mon-working KVM_CAP_DESTROY_MEMORY_REGION? */
104	CAP_ENTRY__L(KVM_CAP_DESTROY_MEMORY_REGION_WORKS), /* 21 */
105	CAP_ENTRY__L(KVM_CAP_USER_NMI),
106	#ifdef __KVM_HAVE_GUEST_DEBUG
107	CAP_ENTRY__L(KVM_CAP_SET_GUEST_DEBUG),
108	#endif
109	#ifdef __KVM_HAVE_PIT
110	CAP_ENTRY__L(KVM_CAP_REINJECT_CONTROL),
111	#endif
112	CAP_ENTRY__L(KVM_CAP_IRQ_ROUTING),
113	CAP_ENTRY__L(KVM_CAP_IRQ_INJECT_STATUS),
114	CAP_ENTRY__U(27),
115	CAP_ENTRY__U(28),
116	CAP_ENTRY__L(KVM_CAP_ASSIGN_DEV_IRQ),
117	CAP_ENTRY__L(KVM_CAP_JOIN_MEMORY_REGIONS_WORKS), /* 30 */
118	#ifdef __KVM_HAVE_MCE
119	CAP_ENTRY__L(KVM_CAP_MCE),
120	#endif
121	CAP_ENTRY__L(KVM_CAP_IRQFD),
122	#ifdef __KVM_HAVE_PIT
123	CAP_ENTRY__L(KVM_CAP_PIT2),
124	#endif
125	CAP_ENTRY__L(KVM_CAP_SET_BOOT_CPU_ID),
126	#ifdef __KVM_HAVE_PIT_STATE2
127	CAP_ENTRY__L(KVM_CAP_PIT_STATE2),
128	#endif
129	CAP_ENTRY__L(KVM_CAP_IOEVENTFD),
130	CAP_ENTRY__L(KVM_CAP_SET_IDENTITY_MAP_ADDR),
131	#ifdef __KVM_HAVE_XEN_HVM
132	CAP_ENTRY__L(KVM_CAP_XEN_HVM),
133	#endif
134	CAP_ENTRY_ML(KVM_CAP_ADJUST_CLOCK),
135	CAP_ENTRY__L(KVM_CAP_INTERNAL_ERROR_DATA), /* 40 */
136	#ifdef __KVM_HAVE_VCPU_EVENTS
137	CAP_ENTRY_ML(KVM_CAP_VCPU_EVENTS),
138	#else
139	CAP_ENTRY_MU(41),
140	#endif
141	CAP_ENTRY__L(KVM_CAP_S390_PSW),
142	CAP_ENTRY__L(KVM_CAP_PPC_SEGSTATE),
143	CAP_ENTRY__L(KVM_CAP_HYPERV),
144	CAP_ENTRY__L(KVM_CAP_HYPERV_VAPIC),
145	CAP_ENTRY__L(KVM_CAP_HYPERV_SPIN),
146	CAP_ENTRY__L(KVM_CAP_PCI_SEGMENT),
147	CAP_ENTRY__L(KVM_CAP_PPC_PAIRED_SINGLES),
148	CAP_ENTRY__L(KVM_CAP_INTR_SHADOW),
149	#ifdef __KVM_HAVE_DEBUGREGS
150	CAP_ENTRY__L(KVM_CAP_DEBUGREGS), /* 50 */
151	#endif
152	CAP_ENTRY__S(KVM_CAP_X86_ROBUST_SINGLESTEP, fRobustSingleStep),
153	CAP_ENTRY__L(KVM_CAP_PPC_OSI),
154	CAP_ENTRY__L(KVM_CAP_PPC_UNSET_IRQ),
155	CAP_ENTRY__L(KVM_CAP_ENABLE_CAP),
156	#ifdef __KVM_HAVE_XSAVE
157	CAP_ENTRY_ML(KVM_CAP_XSAVE),
158	#else
159	CAP_ENTRY_MU(55),
160	#endif
161	#ifdef __KVM_HAVE_XCRS
162	CAP_ENTRY_ML(KVM_CAP_XCRS),
163	#else
164	CAP_ENTRY_MU(56),
165	#endif
166	CAP_ENTRY__L(KVM_CAP_PPC_GET_PVINFO),
167	CAP_ENTRY__L(KVM_CAP_PPC_IRQ_LEVEL),
168	CAP_ENTRY__L(KVM_CAP_ASYNC_PF),
169	CAP_ENTRY__L(KVM_CAP_TSC_CONTROL), /* 60 */
170	CAP_ENTRY__L(KVM_CAP_GET_TSC_KHZ),
171	CAP_ENTRY__L(KVM_CAP_PPC_BOOKE_SREGS),
172	CAP_ENTRY__L(KVM_CAP_SPAPR_TCE),
173	CAP_ENTRY__L(KVM_CAP_PPC_SMT),
174	CAP_ENTRY__L(KVM_CAP_PPC_RMA),
175	CAP_ENTRY__L(KVM_CAP_MAX_VCPUS),
176	CAP_ENTRY__L(KVM_CAP_PPC_HIOR),
177	CAP_ENTRY__L(KVM_CAP_PPC_PAPR),
178	CAP_ENTRY__L(KVM_CAP_SW_TLB),
179	CAP_ENTRY__L(KVM_CAP_ONE_REG), /* 70 */
180	CAP_ENTRY__L(KVM_CAP_S390_GMAP),
181	CAP_ENTRY__L(KVM_CAP_TSC_DEADLINE_TIMER),
182	CAP_ENTRY__L(KVM_CAP_S390_UCONTROL),
183	CAP_ENTRY__L(KVM_CAP_SYNC_REGS),
184	CAP_ENTRY__L(KVM_CAP_PCI_2_3),
185	CAP_ENTRY__L(KVM_CAP_KVMCLOCK_CTRL),
186	CAP_ENTRY__L(KVM_CAP_SIGNAL_MSI),
187	CAP_ENTRY__L(KVM_CAP_PPC_GET_SMMU_INFO),
188	CAP_ENTRY__L(KVM_CAP_S390_COW),
189	CAP_ENTRY__L(KVM_CAP_PPC_ALLOC_HTAB), /* 80 */
190	CAP_ENTRY__L(KVM_CAP_READONLY_MEM),
191	CAP_ENTRY__L(KVM_CAP_IRQFD_RESAMPLE),
192	CAP_ENTRY__L(KVM_CAP_PPC_BOOKE_WATCHDOG),
193	CAP_ENTRY__L(KVM_CAP_PPC_HTAB_FD),
194	CAP_ENTRY__L(KVM_CAP_S390_CSS_SUPPORT),
195	CAP_ENTRY__L(KVM_CAP_PPC_EPR),
196	CAP_ENTRY__L(KVM_CAP_ARM_PSCI),
197	CAP_ENTRY__L(KVM_CAP_ARM_SET_DEVICE_ADDR),
198	CAP_ENTRY__L(KVM_CAP_DEVICE_CTRL),
199	CAP_ENTRY__L(KVM_CAP_IRQ_MPIC), /* 90 */
200	CAP_ENTRY__L(KVM_CAP_PPC_RTAS),
201	CAP_ENTRY__L(KVM_CAP_IRQ_XICS),
202	CAP_ENTRY__L(KVM_CAP_ARM_EL1_32BIT),
203	CAP_ENTRY__L(KVM_CAP_SPAPR_MULTITCE),
204	CAP_ENTRY__L(KVM_CAP_EXT_EMUL_CPUID),
205	CAP_ENTRY__L(KVM_CAP_HYPERV_TIME),
206	CAP_ENTRY__L(KVM_CAP_IOAPIC_POLARITY_IGNORED),
207	CAP_ENTRY__L(KVM_CAP_ENABLE_CAP_VM),
208	CAP_ENTRY__L(KVM_CAP_S390_IRQCHIP),
209	CAP_ENTRY__L(KVM_CAP_IOEVENTFD_NO_LENGTH), /* 100 */
210	CAP_ENTRY__L(KVM_CAP_VM_ATTRIBUTES),
211	CAP_ENTRY__L(KVM_CAP_ARM_PSCI_0_2),
212	CAP_ENTRY__L(KVM_CAP_PPC_FIXUP_HCALL),
213	CAP_ENTRY__L(KVM_CAP_PPC_ENABLE_HCALL),
214	CAP_ENTRY__L(KVM_CAP_CHECK_EXTENSION_VM),
215	CAP_ENTRY__L(KVM_CAP_S390_USER_SIGP),
216	CAP_ENTRY__L(KVM_CAP_S390_VECTOR_REGISTERS),
217	CAP_ENTRY__L(KVM_CAP_S390_MEM_OP),
218	CAP_ENTRY__L(KVM_CAP_S390_USER_STSI),
219	CAP_ENTRY__L(KVM_CAP_S390_SKEYS), /* 110 */
220	CAP_ENTRY__L(KVM_CAP_MIPS_FPU),
221	CAP_ENTRY__L(KVM_CAP_MIPS_MSA),
222	CAP_ENTRY__L(KVM_CAP_S390_INJECT_IRQ),
223	CAP_ENTRY__L(KVM_CAP_S390_IRQ_STATE),
224	CAP_ENTRY__L(KVM_CAP_PPC_HWRNG),
225	CAP_ENTRY__L(KVM_CAP_DISABLE_QUIRKS),
226	CAP_ENTRY__L(KVM_CAP_X86_SMM),
227	CAP_ENTRY__L(KVM_CAP_MULTI_ADDRESS_SPACE),
228	CAP_ENTRY__L(KVM_CAP_GUEST_DEBUG_HW_BPS),
229	CAP_ENTRY__L(KVM_CAP_GUEST_DEBUG_HW_WPS), /* 120 */
230	CAP_ENTRY__L(KVM_CAP_SPLIT_IRQCHIP),
231	CAP_ENTRY__L(KVM_CAP_IOEVENTFD_ANY_LENGTH),
232	CAP_ENTRY__L(KVM_CAP_HYPERV_SYNIC),
233	CAP_ENTRY__L(KVM_CAP_S390_RI),
234	CAP_ENTRY__L(KVM_CAP_SPAPR_TCE_64),
235	CAP_ENTRY__L(KVM_CAP_ARM_PMU_V3),
236	CAP_ENTRY__L(KVM_CAP_VCPU_ATTRIBUTES),
237	CAP_ENTRY__L(KVM_CAP_MAX_VCPU_ID),
238	CAP_ENTRY__L(KVM_CAP_X2APIC_API),
239	CAP_ENTRY__L(KVM_CAP_S390_USER_INSTR0), /* 130 */
240	CAP_ENTRY__L(KVM_CAP_MSI_DEVID),
241	CAP_ENTRY__L(KVM_CAP_PPC_HTM),
242	CAP_ENTRY__L(KVM_CAP_SPAPR_RESIZE_HPT),
243	CAP_ENTRY__L(KVM_CAP_PPC_MMU_RADIX),
244	CAP_ENTRY__L(KVM_CAP_PPC_MMU_HASH_V3),
245	CAP_ENTRY__L(KVM_CAP_IMMEDIATE_EXIT),
246	CAP_ENTRY__L(KVM_CAP_MIPS_VZ),
247	CAP_ENTRY__L(KVM_CAP_MIPS_TE),
248	CAP_ENTRY__L(KVM_CAP_MIPS_64BIT),
249	CAP_ENTRY__L(KVM_CAP_S390_GS), /* 140 */
250	CAP_ENTRY__L(KVM_CAP_S390_AIS),
251	CAP_ENTRY__L(KVM_CAP_SPAPR_TCE_VFIO),
252	CAP_ENTRY__L(KVM_CAP_X86_DISABLE_EXITS),
253	CAP_ENTRY__L(KVM_CAP_ARM_USER_IRQ),
254	CAP_ENTRY__L(KVM_CAP_S390_CMMA_MIGRATION),
255	CAP_ENTRY__L(KVM_CAP_PPC_FWNMI),
256	CAP_ENTRY__L(KVM_CAP_PPC_SMT_POSSIBLE),
257	CAP_ENTRY__L(KVM_CAP_HYPERV_SYNIC2),
258	CAP_ENTRY__L(KVM_CAP_HYPERV_VP_INDEX),
259	CAP_ENTRY__L(KVM_CAP_S390_AIS_MIGRATION), /* 150 */
260	CAP_ENTRY__L(KVM_CAP_PPC_GET_CPU_CHAR),
261	CAP_ENTRY__L(KVM_CAP_S390_BPB),
262	CAP_ENTRY__L(KVM_CAP_GET_MSR_FEATURES),
263	CAP_ENTRY__L(KVM_CAP_HYPERV_EVENTFD),
264	CAP_ENTRY__L(KVM_CAP_HYPERV_TLBFLUSH),
265	CAP_ENTRY__L(KVM_CAP_S390_HPAGE_1M),
266	CAP_ENTRY__L(KVM_CAP_NESTED_STATE),
267	CAP_ENTRY__L(KVM_CAP_ARM_INJECT_SERROR_ESR),
268	CAP_ENTRY__L(KVM_CAP_MSR_PLATFORM_INFO),
269	CAP_ENTRY__L(KVM_CAP_PPC_NESTED_HV), /* 160 */
270	CAP_ENTRY__L(KVM_CAP_HYPERV_SEND_IPI),
271	CAP_ENTRY__L(KVM_CAP_COALESCED_PIO),
272	CAP_ENTRY__L(KVM_CAP_HYPERV_ENLIGHTENED_VMCS),
273	CAP_ENTRY__L(KVM_CAP_EXCEPTION_PAYLOAD),
274	CAP_ENTRY__L(KVM_CAP_ARM_VM_IPA_SIZE),
275	CAP_ENTRY__L(KVM_CAP_MANUAL_DIRTY_LOG_PROTECT),
276	CAP_ENTRY__L(KVM_CAP_HYPERV_CPUID),
277	CAP_ENTRY__L(KVM_CAP_MANUAL_DIRTY_LOG_PROTECT2),
278	CAP_ENTRY__L(KVM_CAP_PPC_IRQ_XIVE),
279	CAP_ENTRY__L(KVM_CAP_ARM_SVE), /* 170 */
280	CAP_ENTRY__L(KVM_CAP_ARM_PTRAUTH_ADDRESS),
281	CAP_ENTRY__L(KVM_CAP_ARM_PTRAUTH_GENERIC),
282	CAP_ENTRY__L(KVM_CAP_PMU_EVENT_FILTER),
283	CAP_ENTRY__L(KVM_CAP_ARM_IRQ_LINE_LAYOUT_2),
284	CAP_ENTRY__L(KVM_CAP_HYPERV_DIRECT_TLBFLUSH),
285	CAP_ENTRY__L(KVM_CAP_PPC_GUEST_DEBUG_SSTEP),
286	CAP_ENTRY__L(KVM_CAP_ARM_NISV_TO_USER),
287	CAP_ENTRY__L(KVM_CAP_ARM_INJECT_EXT_DABT),
288	CAP_ENTRY__L(KVM_CAP_S390_VCPU_RESETS),
289	CAP_ENTRY__L(KVM_CAP_S390_PROTECTED), /* 180 */
290	CAP_ENTRY__L(KVM_CAP_PPC_SECURE_GUEST),
291	CAP_ENTRY__L(KVM_CAP_HALT_POLL),
292	CAP_ENTRY__L(KVM_CAP_ASYNC_PF_INT),
293	CAP_ENTRY__L(KVM_CAP_LAST_CPU),
294	CAP_ENTRY__L(KVM_CAP_SMALLER_MAXPHYADDR),
295	CAP_ENTRY__L(KVM_CAP_S390_DIAG318),
296	CAP_ENTRY__L(KVM_CAP_STEAL_TIME),
297	CAP_ENTRY_ML(KVM_CAP_X86_USER_SPACE_MSR), /* (since 5.10) */
298	CAP_ENTRY_ML(KVM_CAP_X86_MSR_FILTER),
299	CAP_ENTRY__L(KVM_CAP_ENFORCE_PV_FEATURE_CPUID), /* 190 */
300	CAP_ENTRY__L(KVM_CAP_SYS_HYPERV_CPUID),
301	CAP_ENTRY__L(KVM_CAP_DIRTY_LOG_RING),
302	CAP_ENTRY__L(KVM_CAP_X86_BUS_LOCK_EXIT),
303	CAP_ENTRY__L(KVM_CAP_PPC_DAWR1),
304	CAP_ENTRY__L(KVM_CAP_SET_GUEST_DEBUG2),
305	CAP_ENTRY__L(KVM_CAP_SGX_ATTRIBUTE),
306	CAP_ENTRY__L(KVM_CAP_VM_COPY_ENC_CONTEXT_FROM),
307	CAP_ENTRY__L(KVM_CAP_PTP_KVM),
308	CAP_ENTRY__U(199),
309	CAP_ENTRY__U(200),
310	CAP_ENTRY__U(201),
311	CAP_ENTRY__U(202),
312	CAP_ENTRY__U(203),
313	CAP_ENTRY__U(204),
314	CAP_ENTRY__U(205),
315	CAP_ENTRY__U(206),
316	CAP_ENTRY__U(207),
317	CAP_ENTRY__U(208),
318	CAP_ENTRY__U(209),
319	CAP_ENTRY__U(210),
320	CAP_ENTRY__U(211),
321	CAP_ENTRY__U(212),
322	CAP_ENTRY__U(213),
323	CAP_ENTRY__U(214),
324	CAP_ENTRY__U(215),
325	CAP_ENTRY__U(216),
326	};
327
328	LogRel(("NEM: KVM capabilities (system):\n"));
329	int rcRet = VINF_SUCCESS;
330	for (unsigned i = 0; i < RT_ELEMENTS(s_aCaps); i++)
331	{
332	int rc = ioctl(pVM->nem.s.fdVm, KVM_CHECK_EXTENSION, s_aCaps[i].iCap);
333	if (rc >= 10)
334	LogRel(("NEM: %36s: %#x (%d)\n", s_aCaps[i].pszName, rc, rc));
335	else if (rc >= 0)
336	LogRel(("NEM: %36s: %d\n", s_aCaps[i].pszName, rc));
337	else
338	LogRel(("NEM: %s failed: %d/%d\n", s_aCaps[i].pszName, rc, errno));
339	switch (s_aCaps[i].cbNem)
340	{
341	case 0:
342	break;
343	case 1:
344	{
345	uint8_t puValue = (uint8_t )&pVM->nem.padding[s_aCaps[i].offNem];
346	AssertReturn(s_aCaps[i].offNem <= sizeof(NEM) - sizeof(*puValue), VERR_NEM_IPE_0);
347	*puValue = (uint8_t)rc;
348	AssertLogRelMsg((int)*puValue == rc, ("%s: %#x\n", s_aCaps[i].pszName, rc));
349	break;
350	}
351	case 2:
352	{
353	uint16_t puValue = (uint16_t )&pVM->nem.padding[s_aCaps[i].offNem];
354	AssertReturn(s_aCaps[i].offNem <= sizeof(NEM) - sizeof(*puValue), VERR_NEM_IPE_0);
355	*puValue = (uint16_t)rc;
356	AssertLogRelMsg((int)*puValue == rc, ("%s: %#x\n", s_aCaps[i].pszName, rc));
357	break;
358	}
359	case 4:
360	{
361	uint32_t puValue = (uint32_t )&pVM->nem.padding[s_aCaps[i].offNem];
362	AssertReturn(s_aCaps[i].offNem <= sizeof(NEM) - sizeof(*puValue), VERR_NEM_IPE_0);
363	*puValue = (uint32_t)rc;
364	AssertLogRelMsg((int)*puValue == rc, ("%s: %#x\n", s_aCaps[i].pszName, rc));
365	break;
366	}
367	default:
368	rcRet = RTErrInfoSetF(pErrInfo, VERR_NEM_IPE_0, "s_aCaps[%u] is bad: cbNem=%#x - %s",
369	i, s_aCaps[i].pszName, s_aCaps[i].cbNem);
370	AssertFailedReturn(rcRet);
371	}
372
373	/*
374	* Is a require non-zero entry zero or failing?
375	*/
376	if (s_aCaps[i].fReqNonZero && rc <= 0)
377	rcRet = RTERRINFO_LOG_REL_ADD_F(pErrInfo, VERR_NEM_MISSING_FEATURE,
378	"Required capability '%s' is missing!", s_aCaps[i].pszName);
379	}
380
381	/*
382	* Get per VCpu KVM_RUN MMAP area size.
383	*/
384	int rc = ioctl(pVM->nem.s.fdKvm, KVM_GET_VCPU_MMAP_SIZE, 0UL);
385	if ((unsigned)rc < _64M)
386	{
387	pVM->nem.s.cbVCpuMmap = (uint32_t)rc;
388	LogRel(("NEM: %36s: %#x (%d)\n", "KVM_GET_VCPU_MMAP_SIZE", rc, rc));
389	}
390	else if (rc < 0)
391	rcRet = RTERRINFO_LOG_REL_ADD_F(pErrInfo, VERR_NEM_MISSING_FEATURE, "KVM_GET_VCPU_MMAP_SIZE failed: %d", errno);
392	else
393	rcRet = RTERRINFO_LOG_REL_ADD_F(pErrInfo, VERR_NEM_INIT_FAILED, "Odd KVM_GET_VCPU_MMAP_SIZE value: %#x (%d)", rc, rc);
394
395	/*
396	* Init the slot ID bitmap.
397	*/
398	ASMBitSet(&pVM->nem.s.bmSlotIds[0], 0); /* don't use slot 0 */
399	if (pVM->nem.s.cMaxMemSlots < _32K)
400	ASMBitSetRange(&pVM->nem.s.bmSlotIds[0], pVM->nem.s.cMaxMemSlots, _32K);
401	ASMBitSet(&pVM->nem.s.bmSlotIds[0], _32K - 1); /* don't use the last slot */
402
403	return rcRet;
404	}
405
406
407	/**
408	* Does the early setup of a KVM VM.
409	*
410	* @returns VBox status code.
411	* @param pVM The cross context VM structure.
412	* @param pErrInfo Where to always return error info.
413	*/
414	static int nemR3LnxInitSetupVm(PVM pVM, PRTERRINFO pErrInfo)
415	{
416	AssertReturn(pVM->nem.s.fdVm != -1, RTErrInfoSet(pErrInfo, VERR_WRONG_ORDER, "Wrong initalization order"));
417
418	/*
419	* Create the VCpus.
420	*/
421	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
422	{
423	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
424
425	/* Create it. */
426	pVCpu->nem.s.fdVCpu = ioctl(pVM->nem.s.fdVm, KVM_CREATE_VCPU, (unsigned long)idCpu);
427	if (pVCpu->nem.s.fdVCpu < 0)
428	return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS,
429	"KVM_CREATE_VCPU failed for VCpu #%u: %d", idCpu, errno);
430
431	/* Map the KVM_RUN area. */
432	pVCpu->nem.s.pRun = (struct kvm_run *)mmap(NULL, pVM->nem.s.cbVCpuMmap, PROT_READ \| PROT_WRITE, MAP_SHARED,
433	pVCpu->nem.s.fdVCpu, 0 /offset/);
434	if ((void *)pVCpu->nem.s.pRun == MAP_FAILED)
435	return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS, "mmap failed for VCpu #%u: %d", idCpu, errno);
436
437	/* We want all x86 registers and events on each exit. */
438	pVCpu->nem.s.pRun->kvm_valid_regs = KVM_SYNC_X86_REGS \| KVM_SYNC_X86_SREGS \| KVM_SYNC_X86_EVENTS;
439	}
440	return VINF_SUCCESS;
441	}
442
443
444	/** @callback_method_impl{FNVMMEMTRENDEZVOUS} */
445	static DECLCALLBACK(VBOXSTRICTRC) nemR3LnxFixThreadPoke(PVM pVM, PVMCPU pVCpu, void *pvUser)
446	{
447	RT_NOREF(pVM, pvUser);
448	int rc = RTThreadControlPokeSignal(pVCpu->hThread, true /fEnable/);
449	AssertLogRelRC(rc);
450	return VINF_SUCCESS;
451	}
452
453
454	/**
455	* Try initialize the native API.
456	*
457	* This may only do part of the job, more can be done in
458	* nemR3NativeInitAfterCPUM() and nemR3NativeInitCompleted().
459	*
460	* @returns VBox status code.
461	* @param pVM The cross context VM structure.
462	* @param fFallback Whether we're in fallback mode or use-NEM mode. In
463	* the latter we'll fail if we cannot initialize.
464	* @param fForced Whether the HMForced flag is set and we should
465	* fail if we cannot initialize.
466	*/
467	int nemR3NativeInit(PVM pVM, bool fFallback, bool fForced)
468	{
469	RT_NOREF(pVM, fFallback, fForced);
470	/*
471	* Some state init.
472	*/
473	pVM->nem.s.fdKvm = -1;
474	pVM->nem.s.fdVm = -1;
475	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
476	{
477	PNEMCPU pNemCpu = &pVM->apCpusR3[idCpu]->nem.s;
478	pNemCpu->fdVCpu = -1;
479	}
480
481	/*
482	* Error state.
483	* The error message will be non-empty on failure and 'rc' will be set too.
484	*/
485	RTERRINFOSTATIC ErrInfo;
486	PRTERRINFO pErrInfo = RTErrInfoInitStatic(&ErrInfo);
487
488	/*
489	* Open kvm subsystem so we can issue system ioctls.
490	*/
491	int rc;
492	int fdKvm = open("/dev/kvm", O_RDWR \| O_CLOEXEC);
493	if (fdKvm >= 0)
494	{
495	pVM->nem.s.fdKvm = fdKvm;
496
497	/*
498	* Create an empty VM since it is recommended we check capabilities on
499	* the VM rather than the system descriptor.
500	*/
501	int fdVm = ioctl(fdKvm, KVM_CREATE_VM, 0UL /* Type must be zero on x86 */);
502	if (fdVm >= 0)
503	{
504	pVM->nem.s.fdVm = fdVm;
505
506	/*
507	* Check capabilities.
508	*/
509	rc = nemR3LnxInitCheckCapabilities(pVM, pErrInfo);
510	if (RT_SUCCESS(rc))
511	{
512	/*
513	* Set up the VM (more on this later).
514	*/
515	rc = nemR3LnxInitSetupVm(pVM, pErrInfo);
516	if (RT_SUCCESS(rc))
517	{
518	/*
519	* Set ourselves as the execution engine and make config adjustments.
520	*/
521	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_NATIVE_API);
522	Log(("NEM: Marked active!\n"));
523	PGMR3EnableNemMode(pVM);
524
525	/*
526	* Register release statistics
527	*/
528	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
529	{
530	PNEMCPU pNemCpu = &pVM->apCpusR3[idCpu]->nem.s;
531	STAMR3RegisterF(pVM, &pNemCpu->StatImportOnDemand, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of on-demand state imports", "/NEM/CPU%u/ImportOnDemand", idCpu);
532	STAMR3RegisterF(pVM, &pNemCpu->StatImportOnReturn, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of state imports on loop return", "/NEM/CPU%u/ImportOnReturn", idCpu);
533	STAMR3RegisterF(pVM, &pNemCpu->StatImportOnReturnSkipped, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of skipped state imports on loop return", "/NEM/CPU%u/ImportOnReturnSkipped", idCpu);
534	STAMR3RegisterF(pVM, &pNemCpu->StatImportPendingInterrupt, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of times an interrupt was pending when importing from KVM", "/NEM/CPU%u/ImportPendingInterrupt", idCpu);
535	STAMR3RegisterF(pVM, &pNemCpu->StatExportPendingInterrupt, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of times an interrupt was pending when exporting to KVM", "/NEM/CPU%u/ExportPendingInterrupt", idCpu);
536	STAMR3RegisterF(pVM, &pNemCpu->StatQueryCpuTick, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TSC queries", "/NEM/CPU%u/QueryCpuTick", idCpu);
537	STAMR3RegisterF(pVM, &pNemCpu->StatExitTotal, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "All exits", "/NEM/CPU%u/Exit", idCpu);
538	STAMR3RegisterF(pVM, &pNemCpu->StatExitIo, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_IO", "/NEM/CPU%u/Exit/Io", idCpu);
539	STAMR3RegisterF(pVM, &pNemCpu->StatExitMmio, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_MMIO", "/NEM/CPU%u/Exit/Mmio", idCpu);
540	STAMR3RegisterF(pVM, &pNemCpu->StatExitSetTpr, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_SET_TRP", "/NEM/CPU%u/Exit/SetTpr", idCpu);
541	STAMR3RegisterF(pVM, &pNemCpu->StatExitTprAccess, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_TPR_ACCESS", "/NEM/CPU%u/Exit/TprAccess", idCpu);
542	STAMR3RegisterF(pVM, &pNemCpu->StatExitRdMsr, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_RDMSR", "/NEM/CPU%u/Exit/RdMsr", idCpu);
543	STAMR3RegisterF(pVM, &pNemCpu->StatExitWrMsr, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_WRMSR", "/NEM/CPU%u/Exit/WrMsr", idCpu);
544	STAMR3RegisterF(pVM, &pNemCpu->StatExitIrqWindowOpen, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_IRQ_WINDOWS_OPEN", "/NEM/CPU%u/Exit/IrqWindowOpen", idCpu);
545	STAMR3RegisterF(pVM, &pNemCpu->StatExitHalt, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_HLT", "/NEM/CPU%u/Exit/Hlt", idCpu);
546	STAMR3RegisterF(pVM, &pNemCpu->StatExitIntr, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_INTR", "/NEM/CPU%u/Exit/Intr", idCpu);
547	STAMR3RegisterF(pVM, &pNemCpu->StatExitHypercall, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_HYPERCALL", "/NEM/CPU%u/Exit/Hypercall", idCpu);
548	STAMR3RegisterF(pVM, &pNemCpu->StatExitDebug, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_DEBUG", "/NEM/CPU%u/Exit/Debug", idCpu);
549	STAMR3RegisterF(pVM, &pNemCpu->StatExitBusLock, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_BUS_LOCK", "/NEM/CPU%u/Exit/BusLock", idCpu);
550	STAMR3RegisterF(pVM, &pNemCpu->StatExitInternalErrorEmulation, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_INTERNAL_ERROR/EMULATION", "/NEM/CPU%u/Exit/InternalErrorEmulation", idCpu);
551	STAMR3RegisterF(pVM, &pNemCpu->StatExitInternalErrorFatal, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_INTERNAL_ERROR/*", "/NEM/CPU%u/Exit/InternalErrorFatal", idCpu);
552	}
553
554	/*
555	* Make RTThreadPoke work again (disabled for avoiding unnecessary
556	* critical section issues in ring-0).
557	*/
558	VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ALL_AT_ONCE, nemR3LnxFixThreadPoke, NULL);
559
560	/*
561	* Success.
562	*/
563	return VINF_SUCCESS;
564	}
565
566	/*
567	* Bail out.
568	*/
569	}
570	close(fdVm);
571	pVM->nem.s.fdVm = -1;
572	}
573	else
574	rc = RTErrInfoSetF(pErrInfo, VERR_NEM_VM_CREATE_FAILED, "KVM_CREATE_VM failed: %u", errno);
575	close(fdKvm);
576	pVM->nem.s.fdKvm = -1;
577	}
578	else if (errno == EACCES)
579	rc = RTErrInfoSet(pErrInfo, VERR_ACCESS_DENIED, "Do not have access to open /dev/kvm for reading & writing.");
580	else if (errno == ENOENT)
581	rc = RTErrInfoSet(pErrInfo, VERR_NOT_SUPPORTED, "KVM is not availble (/dev/kvm does not exist)");
582	else
583	rc = RTErrInfoSetF(pErrInfo, RTErrConvertFromErrno(errno), "Failed to open '/dev/kvm': %u", errno);
584
585	/*
586	* We only fail if in forced mode, otherwise just log the complaint and return.
587	*/
588	Assert(RTErrInfoIsSet(pErrInfo));
589	if ( (fForced \|\| !fFallback)
590	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NATIVE_API)
591	return VMSetError(pVM, RT_SUCCESS_NP(rc) ? VERR_NEM_NOT_AVAILABLE : rc, RT_SRC_POS, "%s", pErrInfo->pszMsg);
592	LogRel(("NEM: Not available: %s\n", pErrInfo->pszMsg));
593	return VINF_SUCCESS;
594	}
595
596
597	/**
598	* This is called after CPUMR3Init is done.
599	*
600	* @returns VBox status code.
601	* @param pVM The VM handle..
602	*/
603	int nemR3NativeInitAfterCPUM(PVM pVM)
604	{
605	/*
606	* Validate sanity.
607	*/
608	AssertReturn(pVM->nem.s.fdKvm >= 0, VERR_WRONG_ORDER);
609	AssertReturn(pVM->nem.s.fdVm >= 0, VERR_WRONG_ORDER);
610	AssertReturn(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API, VERR_WRONG_ORDER);
611
612	/** @todo */
613
614	return VINF_SUCCESS;
615	}
616
617
618	/**
619	* Update the CPUID leaves for a VCPU.
620	*
621	* The KVM_SET_CPUID2 call replaces any previous leaves, so we have to redo
622	* everything when there really just are single bit changes.
623	*/
624	static int nemR3LnxUpdateCpuIdsLeaves(PVM pVM, PVMCPU pVCpu)
625	{
626	uint32_t cLeaves = 0;
627	PCCPUMCPUIDLEAF const paLeaves = CPUMR3CpuIdGetPtr(pVM, &cLeaves);
628	struct kvm_cpuid2 pReq = (struct kvm_cpuid2 )alloca(RT_UOFFSETOF_DYN(struct kvm_cpuid2, entries[cLeaves + 2]));
629
630	pReq->nent = cLeaves;
631	pReq->padding = 0;
632
633	for (uint32_t i = 0; i < cLeaves; i++)
634	{
635	CPUMGetGuestCpuId(pVCpu, paLeaves[i].uLeaf, paLeaves[i].uSubLeaf,
636	&pReq->entries[i].eax,
637	&pReq->entries[i].ebx,
638	&pReq->entries[i].ecx,
639	&pReq->entries[i].edx);
640	pReq->entries[i].function = paLeaves[i].uLeaf;
641	pReq->entries[i].index = paLeaves[i].uSubLeaf;
642	pReq->entries[i].flags = !paLeaves[i].fSubLeafMask ? 0 : KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
643	pReq->entries[i].padding[0] = 0;
644	pReq->entries[i].padding[1] = 0;
645	pReq->entries[i].padding[2] = 0;
646	}
647
648	int rcLnx = ioctl(pVCpu->nem.s.fdVCpu, KVM_SET_CPUID2, pReq);
649	AssertLogRelMsgReturn(rcLnx == 0, ("rcLnx=%d errno=%d cLeaves=%#x\n", rcLnx, errno, cLeaves), RTErrConvertFromErrno(errno));
650
651	return VINF_SUCCESS;
652	}
653
654
655	int nemR3NativeInitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
656	{
657	/*
658	* Configure CPUIDs after ring-3 init has been done.
659	*/
660	if (enmWhat == VMINITCOMPLETED_RING3)
661	{
662	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
663	{
664	int rc = nemR3LnxUpdateCpuIdsLeaves(pVM, pVM->apCpusR3[idCpu]);
665	AssertRCReturn(rc, rc);
666	}
667	}
668
669	return VINF_SUCCESS;
670	}
671
672
673	int nemR3NativeTerm(PVM pVM)
674	{
675	/*
676	* Per-cpu data
677	*/
678	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
679	{
680	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
681
682	if (pVCpu->nem.s.fdVCpu != -1)
683	{
684	close(pVCpu->nem.s.fdVCpu);
685	pVCpu->nem.s.fdVCpu = -1;
686	}
687	if (pVCpu->nem.s.pRun)
688	{
689	munmap(pVCpu->nem.s.pRun, pVM->nem.s.cbVCpuMmap);
690	pVCpu->nem.s.pRun = NULL;
691	}
692	}
693
694	/*
695	* Global data.
696	*/
697	if (pVM->nem.s.fdVm != -1)
698	{
699	close(pVM->nem.s.fdVm);
700	pVM->nem.s.fdVm = -1;
701	}
702
703	if (pVM->nem.s.fdKvm != -1)
704	{
705	close(pVM->nem.s.fdKvm);
706	pVM->nem.s.fdKvm = -1;
707	}
708	return VINF_SUCCESS;
709	}
710
711
712	/**
713	* VM reset notification.
714	*
715	* @param pVM The cross context VM structure.
716	*/
717	void nemR3NativeReset(PVM pVM)
718	{
719	RT_NOREF(pVM);
720	}
721
722
723	/**
724	* Reset CPU due to INIT IPI or hot (un)plugging.
725	*
726	* @param pVCpu The cross context virtual CPU structure of the CPU being
727	* reset.
728	* @param fInitIpi Whether this is the INIT IPI or hot (un)plugging case.
729	*/
730	void nemR3NativeResetCpu(PVMCPU pVCpu, bool fInitIpi)
731	{
732	RT_NOREF(pVCpu, fInitIpi);
733	}
734
735
736	/*********************************************************************************************************************************
737	* Memory management *
738	*********************************************************************************************************************************/
739
740
741	/**
742	* Allocates a memory slot ID.
743	*
744	* @returns Slot ID on success, UINT16_MAX on failure.
745	*/
746	static uint16_t nemR3LnxMemSlotIdAlloc(PVM pVM)
747	{
748	/* Use the hint first. */
749	uint16_t idHint = pVM->nem.s.idPrevSlot;
750	if (idHint < _32K - 1)
751	{
752	int32_t idx = ASMBitNextClear(&pVM->nem.s.bmSlotIds, _32K, idHint);
753	Assert(idx < _32K);
754	if (idx > 0 && !ASMAtomicBitTestAndSet(&pVM->nem.s.bmSlotIds, idx))
755	return pVM->nem.s.idPrevSlot = (uint16_t)idx;
756	}
757
758	/*
759	* Search the whole map from the start.
760	*/
761	int32_t idx = ASMBitFirstClear(&pVM->nem.s.bmSlotIds, _32K);
762	Assert(idx < _32K);
763	if (idx > 0 && !ASMAtomicBitTestAndSet(&pVM->nem.s.bmSlotIds, idx))
764	return pVM->nem.s.idPrevSlot = (uint16_t)idx;
765
766	Assert(idx < 0 /shouldn't trigger unless there is a race /);
767	return UINT16_MAX; /* caller is expected to assert. */
768	}
769
770
771	/**
772	* Frees a memory slot ID
773	*/
774	static void nemR3LnxMemSlotIdFree(PVM pVM, uint16_t idSlot)
775	{
776	if (RT_LIKELY(idSlot < _32K && ASMAtomicBitTestAndClear(&pVM->nem.s.bmSlotIds, idSlot)))
777	{ /likely/ }
778	else
779	AssertMsgFailed(("idSlot=%u (%#x)\n", idSlot, idSlot));
780	}
781
782
783
784	VMMR3_INT_DECL(int) NEMR3NotifyPhysRamRegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvR3,
785	uint8_t pu2State, uint32_t puNemRange)
786	{
787	uint16_t idSlot = nemR3LnxMemSlotIdAlloc(pVM);
788	AssertLogRelReturn(idSlot < _32K, VERR_NEM_MAP_PAGES_FAILED);
789
790	Log5(("NEMR3NotifyPhysRamRegister: %RGp LB %RGp, pvR3=%p pu2State=%p (%d) puNemRange=%p (%d) - idSlot=%#x\n",
791	GCPhys, cb, pvR3, pu2State, pu2State, puNemRange, *puNemRange, idSlot));
792
793	struct kvm_userspace_memory_region Region;
794	Region.slot = idSlot;
795	Region.flags = 0;
796	Region.guest_phys_addr = GCPhys;
797	Region.memory_size = cb;
798	Region.userspace_addr = (uintptr_t)pvR3;
799
800	int rc = ioctl(pVM->nem.s.fdVm, KVM_SET_USER_MEMORY_REGION, &Region);
801	if (rc == 0)
802	{
803	*pu2State = 0;
804	*puNemRange = idSlot;
805	return VINF_SUCCESS;
806	}
807
808	LogRel(("NEMR3NotifyPhysRamRegister: %RGp LB %RGp, pvR3=%p, idSlot=%#x failed: %u/%u\n", GCPhys, cb, pvR3, idSlot, rc, errno));
809	nemR3LnxMemSlotIdFree(pVM, idSlot);
810	return VERR_NEM_MAP_PAGES_FAILED;
811	}
812
813
814	VMMR3_INT_DECL(bool) NEMR3IsMmio2DirtyPageTrackingSupported(PVM pVM)
815	{
816	RT_NOREF(pVM);
817	return true;
818	}
819
820
821	VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExMapEarly(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags,
822	void pvRam, void pvMmio2, uint8_t pu2State, uint32_t puNemRange)
823	{
824	Log5(("NEMR3NotifyPhysMmioExMapEarly: %RGp LB %RGp fFlags=%#x pvRam=%p pvMmio2=%p pu2State=%p (%d) puNemRange=%p (%#x)\n",
825	GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State, pu2State, puNemRange, puNemRange ? puNemRange : UINT32_MAX));
826	RT_NOREF(pvRam);
827
828	if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE)
829	{
830	/** @todo implement splitting and whatnot of ranges if we want to be 100%
831	* conforming (just modify RAM registrations in MM.cpp to test). */
832	AssertLogRelMsgFailedReturn(("%RGp LB %RGp fFlags=%#x pvRam=%p pvMmio2=%p\n", GCPhys, cb, fFlags, pvRam, pvMmio2),
833	VERR_NEM_MAP_PAGES_FAILED);
834	}
835
836	/*
837	* Register MMIO2.
838	*/
839	if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2)
840	{
841	AssertReturn(pvMmio2, VERR_NEM_MAP_PAGES_FAILED);
842	AssertReturn(puNemRange, VERR_NEM_MAP_PAGES_FAILED);
843
844	uint16_t idSlot = nemR3LnxMemSlotIdAlloc(pVM);
845	AssertLogRelReturn(idSlot < _32K, VERR_NEM_MAP_PAGES_FAILED);
846
847	struct kvm_userspace_memory_region Region;
848	Region.slot = idSlot;
849	Region.flags = fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_TRACK_DIRTY_PAGES ? KVM_MEM_LOG_DIRTY_PAGES : 0;
850	Region.guest_phys_addr = GCPhys;
851	Region.memory_size = cb;
852	Region.userspace_addr = (uintptr_t)pvMmio2;
853
854	int rc = ioctl(pVM->nem.s.fdVm, KVM_SET_USER_MEMORY_REGION, &Region);
855	if (rc == 0)
856	{
857	*pu2State = 0;
858	*puNemRange = idSlot;
859	Log5(("NEMR3NotifyPhysMmioExMapEarly: %RGp LB %RGp fFlags=%#x pvMmio2=%p - idSlot=%#x\n",
860	GCPhys, cb, fFlags, pvMmio2, idSlot));
861	return VINF_SUCCESS;
862	}
863
864	nemR3LnxMemSlotIdFree(pVM, idSlot);
865	AssertLogRelMsgFailedReturn(("%RGp LB %RGp fFlags=%#x, pvMmio2=%p, idSlot=%#x failed: %u/%u\n",
866	GCPhys, cb, fFlags, pvMmio2, idSlot, errno, rc),
867	VERR_NEM_MAP_PAGES_FAILED);
868	}
869
870	/* MMIO, don't care. */
871	*pu2State = 0;
872	*puNemRange = UINT32_MAX;
873	return VINF_SUCCESS;
874	}
875
876
877	VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExMapLate(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags,
878	void pvRam, void pvMmio2, uint32_t *puNemRange)
879	{
880	RT_NOREF(pVM, GCPhys, cb, fFlags, pvRam, pvMmio2, puNemRange);
881	return VINF_SUCCESS;
882	}
883
884
885	VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExUnmap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags, void *pvRam,
886	void pvMmio2, uint8_t pu2State, uint32_t *puNemRange)
887	{
888	Log5(("NEMR3NotifyPhysMmioExUnmap: %RGp LB %RGp fFlags=%#x pvRam=%p pvMmio2=%p pu2State=%p puNemRange=%p (%#x)\n",
889	GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State, puNemRange, *puNemRange));
890	RT_NOREF(pVM, GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State);
891
892	if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE)
893	{
894	/** @todo implement splitting and whatnot of ranges if we want to be 100%
895	* conforming (just modify RAM registrations in MM.cpp to test). */
896	AssertLogRelMsgFailedReturn(("%RGp LB %RGp fFlags=%#x pvRam=%p pvMmio2=%p\n", GCPhys, cb, fFlags, pvRam, pvMmio2),
897	VERR_NEM_UNMAP_PAGES_FAILED);
898	}
899
900	if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2)
901	{
902	uint32_t const idSlot = *puNemRange;
903	AssertReturn(idSlot > 0 && idSlot < _32K, VERR_NEM_IPE_4);
904	AssertReturn(ASMBitTest(pVM->nem.s.bmSlotIds, idSlot), VERR_NEM_IPE_4);
905
906	struct kvm_userspace_memory_region Region;
907	Region.slot = idSlot;
908	Region.flags = 0;
909	Region.guest_phys_addr = GCPhys;
910	Region.memory_size = 0; /* this deregisters it. */
911	Region.userspace_addr = (uintptr_t)pvMmio2;
912
913	int rc = ioctl(pVM->nem.s.fdVm, KVM_SET_USER_MEMORY_REGION, &Region);
914	if (rc == 0)
915	{
916	if (pu2State)
917	*pu2State = 0;
918	*puNemRange = UINT32_MAX;
919	nemR3LnxMemSlotIdFree(pVM, idSlot);
920	return VINF_SUCCESS;
921	}
922
923	AssertLogRelMsgFailedReturn(("%RGp LB %RGp fFlags=%#x, pvMmio2=%p, idSlot=%#x failed: %u/%u\n",
924	GCPhys, cb, fFlags, pvMmio2, idSlot, errno, rc),
925	VERR_NEM_UNMAP_PAGES_FAILED);
926	}
927
928	if (pu2State)
929	*pu2State = UINT8_MAX;
930	return VINF_SUCCESS;
931	}
932
933
934	VMMR3_INT_DECL(int) NEMR3PhysMmio2QueryAndResetDirtyBitmap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t uNemRange,
935	void *pvBitmap, size_t cbBitmap)
936	{
937	AssertReturn(uNemRange > 0 && uNemRange < _32K, VERR_NEM_IPE_4);
938	AssertReturn(ASMBitTest(pVM->nem.s.bmSlotIds, uNemRange), VERR_NEM_IPE_4);
939
940	RT_NOREF(GCPhys, cbBitmap);
941
942	struct kvm_dirty_log DirtyLog;
943	DirtyLog.slot = uNemRange;
944	DirtyLog.padding1 = 0;
945	DirtyLog.dirty_bitmap = pvBitmap;
946
947	int rc = ioctl(pVM->nem.s.fdVm, KVM_GET_DIRTY_LOG, &DirtyLog);
948	AssertLogRelMsgReturn(rc == 0, ("%RGp LB %RGp idSlot=%#x failed: %u/%u\n", GCPhys, cb, uNemRange, errno, rc),
949	VERR_NEM_QUERY_DIRTY_BITMAP_FAILED);
950
951	return VINF_SUCCESS;
952	}
953
954
955	VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterEarly(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvPages, uint32_t fFlags,
956	uint8_t pu2State, uint32_t puNemRange)
957	{
958	Log5(("NEMR3NotifyPhysRomRegisterEarly: %RGp LB %RGp pvPages=%p fFlags=%#x\n", GCPhys, cb, pvPages, fFlags));
959	*pu2State = UINT8_MAX;
960
961	/* Don't support puttint ROM where there is already RAM. For
962	now just shuffle the registrations till it works... */
963	AssertLogRelMsgReturn(!(fFlags & NEM_NOTIFY_PHYS_ROM_F_REPLACE), ("%RGp LB %RGp fFlags=%#x\n", GCPhys, cb, fFlags),
964	VERR_NEM_MAP_PAGES_FAILED);
965
966	/** @todo figure out how to do shadow ROMs. */
967
968	/*
969	* We only allocate a slot number here in case we need to use it to
970	* fend of physical handler fun.
971	*/
972	uint16_t idSlot = nemR3LnxMemSlotIdAlloc(pVM);
973	AssertLogRelReturn(idSlot < _32K, VERR_NEM_MAP_PAGES_FAILED);
974
975	*pu2State = 0;
976	*puNemRange = idSlot;
977	Log5(("NEMR3NotifyPhysRomRegisterEarly: %RGp LB %RGp fFlags=%#x pvPages=%p - idSlot=%#x\n",
978	GCPhys, cb, fFlags, pvPages, idSlot));
979	RT_NOREF(GCPhys, cb, fFlags, pvPages);
980	return VINF_SUCCESS;
981	}
982
983
984	VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterLate(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvPages,
985	uint32_t fFlags, uint8_t pu2State, uint32_t puNemRange)
986	{
987	Log5(("NEMR3NotifyPhysRomRegisterLate: %RGp LB %RGp pvPages=%p fFlags=%#x pu2State=%p (%d) puNemRange=%p (%#x)\n",
988	GCPhys, cb, pvPages, fFlags, pu2State, pu2State, puNemRange, puNemRange));
989
990	AssertPtrReturn(pvPages, VERR_NEM_IPE_5);
991
992	uint32_t const idSlot = *puNemRange;
993	AssertReturn(idSlot > 0 && idSlot < _32K, VERR_NEM_IPE_4);
994	AssertReturn(ASMBitTest(pVM->nem.s.bmSlotIds, idSlot), VERR_NEM_IPE_4);
995
996	*pu2State = UINT8_MAX;
997
998	/*
999	* Do the actual setting of the user pages here now that we've
1000	* got a valid pvPages (typically isn't available during the early
1001	* notification, unless we're replacing RAM).
1002	*/
1003	struct kvm_userspace_memory_region Region;
1004	Region.slot = idSlot;
1005	Region.flags = 0;
1006	Region.guest_phys_addr = GCPhys;
1007	Region.memory_size = cb;
1008	Region.userspace_addr = (uintptr_t)pvPages;
1009
1010	int rc = ioctl(pVM->nem.s.fdVm, KVM_SET_USER_MEMORY_REGION, &Region);
1011	if (rc == 0)
1012	{
1013	*pu2State = 0;
1014	Log5(("NEMR3NotifyPhysRomRegisterEarly: %RGp LB %RGp fFlags=%#x pvPages=%p - idSlot=%#x\n",
1015	GCPhys, cb, fFlags, pvPages, idSlot));
1016	return VINF_SUCCESS;
1017	}
1018	AssertLogRelMsgFailedReturn(("%RGp LB %RGp fFlags=%#x, pvPages=%p, idSlot=%#x failed: %u/%u\n",
1019	GCPhys, cb, fFlags, pvPages, idSlot, errno, rc),
1020	VERR_NEM_MAP_PAGES_FAILED);
1021	}
1022
1023
1024	/**
1025	* Called when the A20 state changes.
1026	*
1027	* @param pVCpu The CPU the A20 state changed on.
1028	* @param fEnabled Whether it was enabled (true) or disabled.
1029	*/
1030	VMMR3_INT_DECL(void) NEMR3NotifySetA20(PVMCPU pVCpu, bool fEnabled)
1031	{
1032	Log(("nemR3NativeNotifySetA20: fEnabled=%RTbool\n", fEnabled));
1033	Assert(VM_IS_NEM_ENABLED(pVCpu->CTX_SUFF(pVM)));
1034	RT_NOREF(pVCpu, fEnabled);
1035	}
1036
1037
1038	VMM_INT_DECL(void) NEMHCNotifyHandlerPhysicalDeregister(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb,
1039	RTR3PTR pvMemR3, uint8_t *pu2State)
1040	{
1041	Log5(("NEMHCNotifyHandlerPhysicalDeregister: %RGp LB %RGp enmKind=%d pvMemR3=%p pu2State=%p (%d)\n",
1042	GCPhys, cb, enmKind, pvMemR3, pu2State, *pu2State));
1043
1044	*pu2State = UINT8_MAX;
1045	RT_NOREF(pVM, enmKind, GCPhys, cb, pvMemR3);
1046	}
1047
1048
1049	void nemHCNativeNotifyHandlerPhysicalRegister(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb)
1050	{
1051	Log5(("nemHCNativeNotifyHandlerPhysicalRegister: %RGp LB %RGp enmKind=%d\n", GCPhys, cb, enmKind));
1052	RT_NOREF(pVM, enmKind, GCPhys, cb);
1053	}
1054
1055
1056	void nemHCNativeNotifyHandlerPhysicalModify(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhysOld,
1057	RTGCPHYS GCPhysNew, RTGCPHYS cb, bool fRestoreAsRAM)
1058	{
1059	Log5(("nemHCNativeNotifyHandlerPhysicalModify: %RGp LB %RGp -> %RGp enmKind=%d fRestoreAsRAM=%d\n",
1060	GCPhysOld, cb, GCPhysNew, enmKind, fRestoreAsRAM));
1061	RT_NOREF(pVM, enmKind, GCPhysOld, GCPhysNew, cb, fRestoreAsRAM);
1062	}
1063
1064
1065	int nemHCNativeNotifyPhysPageAllocated(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhys, uint32_t fPageProt,
1066	PGMPAGETYPE enmType, uint8_t *pu2State)
1067	{
1068	Log5(("nemHCNativeNotifyPhysPageAllocated: %RGp HCPhys=%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
1069	GCPhys, HCPhys, fPageProt, enmType, *pu2State));
1070	RT_NOREF(pVM, GCPhys, HCPhys, fPageProt, enmType, pu2State);
1071	return VINF_SUCCESS;
1072	}
1073
1074
1075	VMM_INT_DECL(void) NEMHCNotifyPhysPageProtChanged(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhys, RTR3PTR pvR3, uint32_t fPageProt,
1076	PGMPAGETYPE enmType, uint8_t *pu2State)
1077	{
1078	Log5(("NEMHCNotifyPhysPageProtChanged: %RGp HCPhys=%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
1079	GCPhys, HCPhys, fPageProt, enmType, *pu2State));
1080	Assert(VM_IS_NEM_ENABLED(pVM));
1081	RT_NOREF(pVM, GCPhys, HCPhys, pvR3, fPageProt, enmType, pu2State);
1082
1083	}
1084
1085
1086	VMM_INT_DECL(void) NEMHCNotifyPhysPageChanged(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhysPrev, RTHCPHYS HCPhysNew,
1087	RTR3PTR pvNewR3, uint32_t fPageProt, PGMPAGETYPE enmType, uint8_t *pu2State)
1088	{
1089	Log5(("nemHCNativeNotifyPhysPageChanged: %RGp HCPhys=%RHp->%RHp pvNewR3=%p fPageProt=%#x enmType=%d *pu2State=%d\n",
1090	GCPhys, HCPhysPrev, HCPhysNew, pvNewR3, fPageProt, enmType, *pu2State));
1091	Assert(VM_IS_NEM_ENABLED(pVM));
1092	RT_NOREF(pVM, GCPhys, HCPhysPrev, HCPhysNew, pvNewR3, fPageProt, enmType, pu2State);
1093	}
1094
1095
1096	/*********************************************************************************************************************************
1097	* CPU State *
1098	*********************************************************************************************************************************/
1099
1100	/**
1101	* Worker that imports selected state from KVM.
1102	*/
1103	static int nemHCLnxImportState(PVMCPUCC pVCpu, uint64_t fWhat, PCPUMCTX pCtx, struct kvm_run *pRun)
1104	{
1105	fWhat &= pVCpu->cpum.GstCtx.fExtrn;
1106	if (!fWhat)
1107	return VINF_SUCCESS;
1108
1109	/*
1110	* Stuff that goes into kvm_run::s.regs.regs:
1111	*/
1112	if (fWhat & (CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS \| CPUMCTX_EXTRN_GPRS_MASK))
1113	{
1114	if (fWhat & CPUMCTX_EXTRN_RIP)
1115	pCtx->rip = pRun->s.regs.regs.rip;
1116	if (fWhat & CPUMCTX_EXTRN_RFLAGS)
1117	pCtx->rflags.u = pRun->s.regs.regs.rflags;
1118
1119	if (fWhat & CPUMCTX_EXTRN_RAX)
1120	pCtx->rax = pRun->s.regs.regs.rax;
1121	if (fWhat & CPUMCTX_EXTRN_RCX)
1122	pCtx->rcx = pRun->s.regs.regs.rcx;
1123	if (fWhat & CPUMCTX_EXTRN_RDX)
1124	pCtx->rdx = pRun->s.regs.regs.rdx;
1125	if (fWhat & CPUMCTX_EXTRN_RBX)
1126	pCtx->rbx = pRun->s.regs.regs.rbx;
1127	if (fWhat & CPUMCTX_EXTRN_RSP)
1128	pCtx->rsp = pRun->s.regs.regs.rsp;
1129	if (fWhat & CPUMCTX_EXTRN_RBP)
1130	pCtx->rbp = pRun->s.regs.regs.rbp;
1131	if (fWhat & CPUMCTX_EXTRN_RSI)
1132	pCtx->rsi = pRun->s.regs.regs.rsi;
1133	if (fWhat & CPUMCTX_EXTRN_RDI)
1134	pCtx->rdi = pRun->s.regs.regs.rdi;
1135	if (fWhat & CPUMCTX_EXTRN_R8_R15)
1136	{
1137	pCtx->r8 = pRun->s.regs.regs.r8;
1138	pCtx->r9 = pRun->s.regs.regs.r9;
1139	pCtx->r10 = pRun->s.regs.regs.r10;
1140	pCtx->r11 = pRun->s.regs.regs.r11;
1141	pCtx->r12 = pRun->s.regs.regs.r12;
1142	pCtx->r13 = pRun->s.regs.regs.r13;
1143	pCtx->r14 = pRun->s.regs.regs.r14;
1144	pCtx->r15 = pRun->s.regs.regs.r15;
1145	}
1146	}
1147
1148	/*
1149	* Stuff that goes into kvm_run::s.regs.sregs:
1150	*/
1151	/** @todo apic_base */
1152
1153	bool fMaybeChangedMode = false;
1154	bool fUpdateCr3 = false;
1155	if (fWhat & ( CPUMCTX_EXTRN_SREG_MASK \| CPUMCTX_EXTRN_TABLE_MASK \| CPUMCTX_EXTRN_CR_MASK
1156	\| CPUMCTX_EXTRN_EFER \| CPUMCTX_EXTRN_APIC_TPR))
1157	{
1158	/** @todo what about Attr.n.u4LimitHigh? */
1159	#define NEM_LNX_IMPORT_SEG(a_CtxSeg, a_KvmSeg) do { \
1160	(a_CtxSeg).u64Base = (a_KvmSeg).base; \
1161	(a_CtxSeg).u32Limit = (a_KvmSeg).limit; \
1162	(a_CtxSeg).ValidSel = (a_CtxSeg).Sel = (a_KvmSeg).selector; \
1163	(a_CtxSeg).Attr.n.u4Type = (a_KvmSeg).type; \
1164	(a_CtxSeg).Attr.n.u1DescType = (a_KvmSeg).s; \
1165	(a_CtxSeg).Attr.n.u2Dpl = (a_KvmSeg).dpl; \
1166	(a_CtxSeg).Attr.n.u1Present = (a_KvmSeg).present; \
1167	(a_CtxSeg).Attr.n.u1Available = (a_KvmSeg).avl; \
1168	(a_CtxSeg).Attr.n.u1Long = (a_KvmSeg).l; \
1169	(a_CtxSeg).Attr.n.u1DefBig = (a_KvmSeg).db; \
1170	(a_CtxSeg).Attr.n.u1Granularity = (a_KvmSeg).g; \
1171	(a_CtxSeg).Attr.n.u1Unusable = (a_KvmSeg).unusable; \
1172	(a_CtxSeg).fFlags = CPUMSELREG_FLAGS_VALID; \
1173	CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &(a_CtxSeg)); \
1174	} while (0)
1175
1176	if (fWhat & CPUMCTX_EXTRN_SREG_MASK)
1177	{
1178	if (fWhat & CPUMCTX_EXTRN_ES)
1179	NEM_LNX_IMPORT_SEG(pCtx->es, pRun->s.regs.sregs.es);
1180	if (fWhat & CPUMCTX_EXTRN_CS)
1181	NEM_LNX_IMPORT_SEG(pCtx->cs, pRun->s.regs.sregs.cs);
1182	if (fWhat & CPUMCTX_EXTRN_SS)
1183	NEM_LNX_IMPORT_SEG(pCtx->ss, pRun->s.regs.sregs.ss);
1184	if (fWhat & CPUMCTX_EXTRN_DS)
1185	NEM_LNX_IMPORT_SEG(pCtx->ds, pRun->s.regs.sregs.ds);
1186	if (fWhat & CPUMCTX_EXTRN_FS)
1187	NEM_LNX_IMPORT_SEG(pCtx->fs, pRun->s.regs.sregs.fs);
1188	if (fWhat & CPUMCTX_EXTRN_GS)
1189	NEM_LNX_IMPORT_SEG(pCtx->gs, pRun->s.regs.sregs.gs);
1190	}
1191	if (fWhat & CPUMCTX_EXTRN_TABLE_MASK)
1192	{
1193	if (fWhat & CPUMCTX_EXTRN_GDTR)
1194	{
1195	pCtx->gdtr.pGdt = pRun->s.regs.sregs.gdt.base;
1196	pCtx->gdtr.cbGdt = pRun->s.regs.sregs.gdt.limit;
1197	}
1198	if (fWhat & CPUMCTX_EXTRN_IDTR)
1199	{
1200	pCtx->idtr.pIdt = pRun->s.regs.sregs.idt.base;
1201	pCtx->idtr.cbIdt = pRun->s.regs.sregs.idt.limit;
1202	}
1203	if (fWhat & CPUMCTX_EXTRN_LDTR)
1204	NEM_LNX_IMPORT_SEG(pCtx->ldtr, pRun->s.regs.sregs.ldt);
1205	if (fWhat & CPUMCTX_EXTRN_TR)
1206	NEM_LNX_IMPORT_SEG(pCtx->tr, pRun->s.regs.sregs.tr);
1207	}
1208	if (fWhat & CPUMCTX_EXTRN_CR_MASK)
1209	{
1210	if (fWhat & CPUMCTX_EXTRN_CR0)
1211	{
1212	if (pVCpu->cpum.GstCtx.cr0 != pRun->s.regs.sregs.cr0)
1213	{
1214	CPUMSetGuestCR0(pVCpu, pRun->s.regs.sregs.cr0);
1215	fMaybeChangedMode = true;
1216	}
1217	}
1218	if (fWhat & CPUMCTX_EXTRN_CR2)
1219	pCtx->cr2 = pRun->s.regs.sregs.cr2;
1220	if (fWhat & CPUMCTX_EXTRN_CR3)
1221	{
1222	if (pCtx->cr3 != pRun->s.regs.sregs.cr3)
1223	{
1224	CPUMSetGuestCR3(pVCpu, pRun->s.regs.sregs.cr3);
1225	fUpdateCr3 = true;
1226	}
1227	}
1228	if (fWhat & CPUMCTX_EXTRN_CR4)
1229	{
1230	if (pCtx->cr4 != pRun->s.regs.sregs.cr4)
1231	{
1232	CPUMSetGuestCR4(pVCpu, pRun->s.regs.sregs.cr4);
1233	fMaybeChangedMode = true;
1234	}
1235	}
1236	}
1237	if (fWhat & CPUMCTX_EXTRN_APIC_TPR)
1238	APICSetTpr(pVCpu, (uint8_t)pRun->s.regs.sregs.cr8 << 4);
1239	if (fWhat & CPUMCTX_EXTRN_EFER)
1240	{
1241	if (pCtx->msrEFER != pRun->s.regs.sregs.efer)
1242	{
1243	Log7(("NEM/%u: MSR EFER changed %RX64 -> %RX64\n", pVCpu->idCpu, pVCpu->cpum.GstCtx.msrEFER, pRun->s.regs.sregs.efer));
1244	if ((pRun->s.regs.sregs.efer ^ pVCpu->cpum.GstCtx.msrEFER) & MSR_K6_EFER_NXE)
1245	PGMNotifyNxeChanged(pVCpu, RT_BOOL(pRun->s.regs.sregs.efer & MSR_K6_EFER_NXE));
1246	pCtx->msrEFER = pRun->s.regs.sregs.efer;
1247	fMaybeChangedMode = true;
1248	}
1249	}
1250
1251	/** @todo apic_base */
1252	#undef NEM_LNX_IMPORT_SEG
1253	}
1254
1255	/*
1256	* Debug registers.
1257	*/
1258	if (fWhat & CPUMCTX_EXTRN_DR_MASK)
1259	{
1260	struct kvm_debugregs DbgRegs = {{0}};
1261	int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_GET_DEBUGREGS, &DbgRegs);
1262	AssertMsgReturn(rc == 0, ("rc=%d errno=%d\n", rc, errno), VERR_NEM_IPE_3);
1263
1264	if (fWhat & CPUMCTX_EXTRN_DR0_DR3)
1265	{
1266	pCtx->dr[0] = DbgRegs.db[0];
1267	pCtx->dr[1] = DbgRegs.db[1];
1268	pCtx->dr[2] = DbgRegs.db[2];
1269	pCtx->dr[3] = DbgRegs.db[3];
1270	}
1271	if (fWhat & CPUMCTX_EXTRN_DR6)
1272	pCtx->dr[6] = DbgRegs.dr6;
1273	if (fWhat & CPUMCTX_EXTRN_DR7)
1274	pCtx->dr[7] = DbgRegs.dr7;
1275	}
1276
1277	/*
1278	* FPU, SSE, AVX, ++.
1279	*/
1280	if (fWhat & (CPUMCTX_EXTRN_X87 \| CPUMCTX_EXTRN_SSE_AVX \| CPUMCTX_EXTRN_OTHER_XSAVE \| CPUMCTX_EXTRN_XCRx))
1281	{
1282	if (fWhat & (CPUMCTX_EXTRN_X87 \| CPUMCTX_EXTRN_SSE_AVX \| CPUMCTX_EXTRN_OTHER_XSAVE))
1283	{
1284	fWhat \|= CPUMCTX_EXTRN_X87 \| CPUMCTX_EXTRN_SSE_AVX \| CPUMCTX_EXTRN_OTHER_XSAVE; /* we do all or nothing at all */
1285
1286	AssertCompile(sizeof(pCtx->XState) >= sizeof(struct kvm_xsave));
1287	int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_GET_XSAVE, &pCtx->XState);
1288	AssertMsgReturn(rc == 0, ("rc=%d errno=%d\n", rc, errno), VERR_NEM_IPE_3);
1289	}
1290
1291	if (fWhat & CPUMCTX_EXTRN_XCRx)
1292	{
1293	struct kvm_xcrs Xcrs =
1294	{ /.nr_xcrs = / 2,
1295	/.flags = / 0,
1296	/.xcrs= / {
1297	{ /.xcr =/ 0, /.reserved=/ 0, /.value=/ pCtx->aXcr[0] },
1298	{ /.xcr =/ 1, /.reserved=/ 0, /.value=/ pCtx->aXcr[1] },
1299	}
1300	};
1301
1302	int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_GET_XCRS, &Xcrs);
1303	AssertMsgReturn(rc == 0, ("rc=%d errno=%d\n", rc, errno), VERR_NEM_IPE_3);
1304
1305	pCtx->aXcr[0] = Xcrs.xcrs[0].value;
1306	pCtx->aXcr[1] = Xcrs.xcrs[1].value;
1307	}
1308	}
1309
1310	/*
1311	* MSRs.
1312	*/
1313	if (fWhat & ( CPUMCTX_EXTRN_KERNEL_GS_BASE \| CPUMCTX_EXTRN_SYSCALL_MSRS \| CPUMCTX_EXTRN_SYSENTER_MSRS
1314	\| CPUMCTX_EXTRN_TSC_AUX \| CPUMCTX_EXTRN_OTHER_MSRS))
1315	{
1316	union
1317	{
1318	struct kvm_msrs Core;
1319	uint64_t padding[2 + sizeof(struct kvm_msr_entry) * 32];
1320	} uBuf;
1321	uint64_t *pauDsts[32];
1322	uint32_t iMsr = 0;
1323	PCPUMCTXMSRS const pCtxMsrs = CPUMQueryGuestCtxMsrsPtr(pVCpu);
1324
1325	#define ADD_MSR(a_Msr, a_uValue) do { \
1326	Assert(iMsr < 32); \
1327	uBuf.Core.entries[iMsr].index = (a_Msr); \
1328	uBuf.Core.entries[iMsr].reserved = 0; \
1329	uBuf.Core.entries[iMsr].data = UINT64_MAX; \
1330	pauDsts[iMsr] = &(a_uValue); \
1331	iMsr += 1; \
1332	} while (0)
1333
1334	if (fWhat & CPUMCTX_EXTRN_KERNEL_GS_BASE)
1335	ADD_MSR(MSR_K8_KERNEL_GS_BASE, pCtx->msrKERNELGSBASE);
1336	if (fWhat & CPUMCTX_EXTRN_SYSCALL_MSRS)
1337	{
1338	ADD_MSR(MSR_K6_STAR, pCtx->msrSTAR);
1339	ADD_MSR(MSR_K8_LSTAR, pCtx->msrLSTAR);
1340	ADD_MSR(MSR_K8_CSTAR, pCtx->msrCSTAR);
1341	ADD_MSR(MSR_K8_SF_MASK, pCtx->msrSFMASK);
1342	}
1343	if (fWhat & CPUMCTX_EXTRN_SYSENTER_MSRS)
1344	{
1345	ADD_MSR(MSR_IA32_SYSENTER_CS, pCtx->SysEnter.cs);
1346	ADD_MSR(MSR_IA32_SYSENTER_EIP, pCtx->SysEnter.eip);
1347	ADD_MSR(MSR_IA32_SYSENTER_ESP, pCtx->SysEnter.esp);
1348	}
1349	if (fWhat & CPUMCTX_EXTRN_TSC_AUX)
1350	ADD_MSR(MSR_K8_TSC_AUX, pCtxMsrs->msr.TscAux);
1351	if (fWhat & CPUMCTX_EXTRN_OTHER_MSRS)
1352	{
1353	ADD_MSR(MSR_IA32_CR_PAT, pCtx->msrPAT);
1354	/** @todo What do we _have_ to add here?
1355	* We also have: Mttr, MiscEnable, FeatureControl. /
1356	}
1357
1358	uBuf.Core.pad = 0;
1359	uBuf.Core.nmsrs = iMsr;
1360	int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_GET_MSRS, &uBuf);
1361	AssertMsgReturn(rc == (int)iMsr,
1362	("rc=%d iMsr=%d (->%#x) errno=%d\n",
1363	rc, iMsr, (uint32_t)rc < iMsr ? uBuf.Core.entries[rc].index : 0, errno),
1364	VERR_NEM_IPE_3);
1365
1366	while (iMsr-- > 0)
1367	*pauDsts[iMsr] = uBuf.Core.entries[iMsr].data;
1368	#undef ADD_MSR
1369	}
1370
1371	/*
1372	* Interruptibility state and pending interrupts.
1373	*/
1374	if (fWhat & (CPUMCTX_EXTRN_INHIBIT_INT \| CPUMCTX_EXTRN_INHIBIT_NMI))
1375	{
1376	fWhat \|= CPUMCTX_EXTRN_INHIBIT_INT \| CPUMCTX_EXTRN_INHIBIT_NMI; /* always do both, see export and interrupt FF handling */
1377
1378	struct kvm_vcpu_events KvmEvents = {0};
1379	int rcLnx = ioctl(pVCpu->nem.s.fdVCpu, KVM_GET_VCPU_EVENTS, &KvmEvents);
1380	AssertLogRelMsgReturn(rcLnx == 0, ("rcLnx=%d errno=%d\n", rcLnx, errno), VERR_NEM_IPE_3);
1381
1382	if (pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_RIP)
1383	pVCpu->cpum.GstCtx.rip = pRun->s.regs.regs.rip;
1384
1385	if (KvmEvents.interrupt.shadow)
1386	EMSetInhibitInterruptsPC(pVCpu, pVCpu->cpum.GstCtx.rip);
1387	else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
1388	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1389
1390	if (KvmEvents.nmi.masked)
1391	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
1392	else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1393	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
1394
1395	if (KvmEvents.interrupt.injected)
1396	{
1397	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportPendingInterrupt);
1398	TRPMAssertTrap(pVCpu, KvmEvents.interrupt.nr, !KvmEvents.interrupt.soft ? TRPM_HARDWARE_INT : TRPM_SOFTWARE_INT);
1399	}
1400
1401	Assert(KvmEvents.nmi.injected == 0);
1402	Assert(KvmEvents.nmi.pending == 0);
1403	}
1404
1405	/*
1406	* Update the external mask.
1407	*/
1408	pCtx->fExtrn &= ~fWhat;
1409	pVCpu->cpum.GstCtx.fExtrn &= ~fWhat;
1410	if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL))
1411	pVCpu->cpum.GstCtx.fExtrn = 0;
1412
1413	/*
1414	* We sometimes need to update PGM on the guest status.
1415	*/
1416	if (!fMaybeChangedMode && !fUpdateCr3)
1417	{ /* likely */ }
1418	else
1419	{
1420	/*
1421	* Make sure we got all the state PGM might need.
1422	*/
1423	Log7(("nemHCLnxImportState: fMaybeChangedMode=%d fUpdateCr3=%d fExtrnNeeded=%#RX64\n", fMaybeChangedMode, fUpdateCr3,
1424	pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_CR0 \| CPUMCTX_EXTRN_CR4 \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_EFER) ));
1425	if (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_CR0 \| CPUMCTX_EXTRN_CR4 \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_EFER))
1426	{
1427	if (pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_CR0)
1428	{
1429	if (pVCpu->cpum.GstCtx.cr0 != pRun->s.regs.sregs.cr0)
1430	{
1431	CPUMSetGuestCR0(pVCpu, pRun->s.regs.sregs.cr0);
1432	fMaybeChangedMode = true;
1433	}
1434	}
1435	if (pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_CR3)
1436	{
1437	if (pCtx->cr3 != pRun->s.regs.sregs.cr3)
1438	{
1439	CPUMSetGuestCR3(pVCpu, pRun->s.regs.sregs.cr3);
1440	fUpdateCr3 = true;
1441	}
1442	}
1443	if (pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_CR4)
1444	{
1445	if (pCtx->cr4 != pRun->s.regs.sregs.cr4)
1446	{
1447	CPUMSetGuestCR4(pVCpu, pRun->s.regs.sregs.cr4);
1448	fMaybeChangedMode = true;
1449	}
1450	}
1451	if (fWhat & CPUMCTX_EXTRN_EFER)
1452	{
1453	if (pCtx->msrEFER != pRun->s.regs.sregs.efer)
1454	{
1455	Log7(("NEM/%u: MSR EFER changed %RX64 -> %RX64\n", pVCpu->idCpu, pVCpu->cpum.GstCtx.msrEFER, pRun->s.regs.sregs.efer));
1456	if ((pRun->s.regs.sregs.efer ^ pVCpu->cpum.GstCtx.msrEFER) & MSR_K6_EFER_NXE)
1457	PGMNotifyNxeChanged(pVCpu, RT_BOOL(pRun->s.regs.sregs.efer & MSR_K6_EFER_NXE));
1458	pCtx->msrEFER = pRun->s.regs.sregs.efer;
1459	fMaybeChangedMode = true;
1460	}
1461	}
1462
1463	pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_CR0 \| CPUMCTX_EXTRN_CR4 \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_EFER);
1464	if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL))
1465	pVCpu->cpum.GstCtx.fExtrn = 0;
1466	}
1467
1468	/*
1469	* Notify PGM about the changes.
1470	*/
1471	if (fMaybeChangedMode)
1472	{
1473	int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
1474	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_NEM_IPE_1);
1475	}
1476
1477	if (fUpdateCr3)
1478	{
1479	int rc = PGMUpdateCR3(pVCpu, pVCpu->cpum.GstCtx.cr3, false /fPdpesMapped/);
1480	if (rc == VINF_SUCCESS)
1481	{ /* likely */ }
1482	else
1483	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_NEM_IPE_2);
1484	}
1485	}
1486
1487	return VINF_SUCCESS;
1488	}
1489
1490
1491	/**
1492	* Interface for importing state on demand (used by IEM).
1493	*
1494	* @returns VBox status code.
1495	* @param pVCpu The cross context CPU structure.
1496	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
1497	*/
1498	VMM_INT_DECL(int) NEMImportStateOnDemand(PVMCPUCC pVCpu, uint64_t fWhat)
1499	{
1500	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnDemand);
1501	return nemHCLnxImportState(pVCpu, fWhat, &pVCpu->cpum.GstCtx, pVCpu->nem.s.pRun);
1502	}
1503
1504
1505	/**
1506	* Exports state to KVM.
1507	*/
1508	static int nemHCLnxExportState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, struct kvm_run *pRun)
1509	{
1510	uint64_t const fExtrn = ~pCtx->fExtrn & CPUMCTX_EXTRN_ALL;
1511	Assert((~fExtrn & CPUMCTX_EXTRN_ALL) != CPUMCTX_EXTRN_ALL);
1512
1513	/*
1514	* Stuff that goes into kvm_run::s.regs.regs:
1515	*/
1516	if (fExtrn & (CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS \| CPUMCTX_EXTRN_GPRS_MASK))
1517	{
1518	if (fExtrn & CPUMCTX_EXTRN_RIP)
1519	pRun->s.regs.regs.rip = pCtx->rip;
1520	if (fExtrn & CPUMCTX_EXTRN_RFLAGS)
1521	pRun->s.regs.regs.rflags = pCtx->rflags.u;
1522
1523	if (fExtrn & CPUMCTX_EXTRN_RAX)
1524	pRun->s.regs.regs.rax = pCtx->rax;
1525	if (fExtrn & CPUMCTX_EXTRN_RCX)
1526	pRun->s.regs.regs.rcx = pCtx->rcx;
1527	if (fExtrn & CPUMCTX_EXTRN_RDX)
1528	pRun->s.regs.regs.rdx = pCtx->rdx;
1529	if (fExtrn & CPUMCTX_EXTRN_RBX)
1530	pRun->s.regs.regs.rbx = pCtx->rbx;
1531	if (fExtrn & CPUMCTX_EXTRN_RSP)
1532	pRun->s.regs.regs.rsp = pCtx->rsp;
1533	if (fExtrn & CPUMCTX_EXTRN_RBP)
1534	pRun->s.regs.regs.rbp = pCtx->rbp;
1535	if (fExtrn & CPUMCTX_EXTRN_RSI)
1536	pRun->s.regs.regs.rsi = pCtx->rsi;
1537	if (fExtrn & CPUMCTX_EXTRN_RDI)
1538	pRun->s.regs.regs.rdi = pCtx->rdi;
1539	if (fExtrn & CPUMCTX_EXTRN_R8_R15)
1540	{
1541	pRun->s.regs.regs.r8 = pCtx->r8;
1542	pRun->s.regs.regs.r9 = pCtx->r9;
1543	pRun->s.regs.regs.r10 = pCtx->r10;
1544	pRun->s.regs.regs.r11 = pCtx->r11;
1545	pRun->s.regs.regs.r12 = pCtx->r12;
1546	pRun->s.regs.regs.r13 = pCtx->r13;
1547	pRun->s.regs.regs.r14 = pCtx->r14;
1548	pRun->s.regs.regs.r15 = pCtx->r15;
1549	}
1550	pRun->kvm_dirty_regs \|= KVM_SYNC_X86_REGS;
1551	}
1552
1553	/*
1554	* Stuff that goes into kvm_run::s.regs.sregs:
1555	*/
1556	/** @todo apic_base */
1557	if (fExtrn & ( CPUMCTX_EXTRN_SREG_MASK \| CPUMCTX_EXTRN_TABLE_MASK \| CPUMCTX_EXTRN_CR_MASK
1558	\| CPUMCTX_EXTRN_EFER \| CPUMCTX_EXTRN_APIC_TPR))
1559	{
1560	#define NEM_LNX_EXPORT_SEG(a_KvmSeg, a_CtxSeg) do { \
1561	(a_KvmSeg).base = (a_CtxSeg).u64Base; \
1562	(a_KvmSeg).limit = (a_CtxSeg).u32Limit; \
1563	(a_KvmSeg).selector = (a_CtxSeg).Sel; \
1564	(a_KvmSeg).type = (a_CtxSeg).Attr.n.u4Type; \
1565	(a_KvmSeg).s = (a_CtxSeg).Attr.n.u1DescType; \
1566	(a_KvmSeg).dpl = (a_CtxSeg).Attr.n.u2Dpl; \
1567	(a_KvmSeg).present = (a_CtxSeg).Attr.n.u1Present; \
1568	(a_KvmSeg).avl = (a_CtxSeg).Attr.n.u1Available; \
1569	(a_KvmSeg).l = (a_CtxSeg).Attr.n.u1Long; \
1570	(a_KvmSeg).db = (a_CtxSeg).Attr.n.u1DefBig; \
1571	(a_KvmSeg).g = (a_CtxSeg).Attr.n.u1Granularity; \
1572	(a_KvmSeg).unusable = (a_CtxSeg).Attr.n.u1Unusable; \
1573	(a_KvmSeg).padding = 0; \
1574	} while (0)
1575
1576	if (fExtrn & CPUMCTX_EXTRN_SREG_MASK)
1577	{
1578	if (fExtrn & CPUMCTX_EXTRN_ES)
1579	NEM_LNX_EXPORT_SEG(pRun->s.regs.sregs.es, pCtx->es);
1580	if (fExtrn & CPUMCTX_EXTRN_CS)
1581	NEM_LNX_EXPORT_SEG(pRun->s.regs.sregs.cs, pCtx->cs);
1582	if (fExtrn & CPUMCTX_EXTRN_SS)
1583	NEM_LNX_EXPORT_SEG(pRun->s.regs.sregs.ss, pCtx->ss);
1584	if (fExtrn & CPUMCTX_EXTRN_DS)
1585	NEM_LNX_EXPORT_SEG(pRun->s.regs.sregs.ds, pCtx->ds);
1586	if (fExtrn & CPUMCTX_EXTRN_FS)
1587	NEM_LNX_EXPORT_SEG(pRun->s.regs.sregs.fs, pCtx->fs);
1588	if (fExtrn & CPUMCTX_EXTRN_GS)
1589	NEM_LNX_EXPORT_SEG(pRun->s.regs.sregs.gs, pCtx->gs);
1590	}
1591	if (fExtrn & CPUMCTX_EXTRN_TABLE_MASK)
1592	{
1593	if (fExtrn & CPUMCTX_EXTRN_GDTR)
1594	{
1595	pRun->s.regs.sregs.gdt.base = pCtx->gdtr.pGdt;
1596	pRun->s.regs.sregs.gdt.limit = pCtx->gdtr.cbGdt;
1597	pRun->s.regs.sregs.gdt.padding[0] = 0;
1598	pRun->s.regs.sregs.gdt.padding[1] = 0;
1599	pRun->s.regs.sregs.gdt.padding[2] = 0;
1600	}
1601	if (fExtrn & CPUMCTX_EXTRN_IDTR)
1602	{
1603	pRun->s.regs.sregs.idt.base = pCtx->idtr.pIdt;
1604	pRun->s.regs.sregs.idt.limit = pCtx->idtr.cbIdt;
1605	pRun->s.regs.sregs.idt.padding[0] = 0;
1606	pRun->s.regs.sregs.idt.padding[1] = 0;
1607	pRun->s.regs.sregs.idt.padding[2] = 0;
1608	}
1609	if (fExtrn & CPUMCTX_EXTRN_LDTR)
1610	NEM_LNX_EXPORT_SEG(pRun->s.regs.sregs.ldt, pCtx->ldtr);
1611	if (fExtrn & CPUMCTX_EXTRN_TR)
1612	NEM_LNX_EXPORT_SEG(pRun->s.regs.sregs.tr, pCtx->tr);
1613	}
1614	if (fExtrn & CPUMCTX_EXTRN_CR_MASK)
1615	{
1616	if (fExtrn & CPUMCTX_EXTRN_CR0)
1617	pRun->s.regs.sregs.cr0 = pCtx->cr0;
1618	if (fExtrn & CPUMCTX_EXTRN_CR2)
1619	pRun->s.regs.sregs.cr2 = pCtx->cr2;
1620	if (fExtrn & CPUMCTX_EXTRN_CR3)
1621	pRun->s.regs.sregs.cr3 = pCtx->cr3;
1622	if (fExtrn & CPUMCTX_EXTRN_CR4)
1623	pRun->s.regs.sregs.cr4 = pCtx->cr4;
1624	}
1625	if (fExtrn & CPUMCTX_EXTRN_APIC_TPR)
1626	pRun->s.regs.sregs.cr8 = CPUMGetGuestCR8(pVCpu);
1627	if (fExtrn & CPUMCTX_EXTRN_EFER)
1628	pRun->s.regs.sregs.efer = pCtx->msrEFER;
1629
1630	/** @todo apic_base */
1631
1632	RT_ZERO(pRun->s.regs.sregs.interrupt_bitmap); /* this is an alternative interrupt injection interface */
1633
1634	pRun->kvm_dirty_regs \|= KVM_SYNC_X86_SREGS;
1635	}
1636
1637	/*
1638	* Debug registers.
1639	*/
1640	if (fExtrn & CPUMCTX_EXTRN_DR_MASK)
1641	{
1642	struct kvm_debugregs DbgRegs = {{0}};
1643
1644	if ((fExtrn & CPUMCTX_EXTRN_DR_MASK) != CPUMCTX_EXTRN_DR_MASK)
1645	{
1646	/* Partial debug state, we must get DbgRegs first so we can merge: */
1647	int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_GET_DEBUGREGS, &DbgRegs);
1648	AssertMsgReturn(rc == 0, ("rc=%d errno=%d\n", rc, errno), VERR_NEM_IPE_3);
1649	}
1650
1651	if (fExtrn & CPUMCTX_EXTRN_DR0_DR3)
1652	{
1653	DbgRegs.db[0] = pCtx->dr[0];
1654	DbgRegs.db[1] = pCtx->dr[1];
1655	DbgRegs.db[2] = pCtx->dr[2];
1656	DbgRegs.db[3] = pCtx->dr[3];
1657	}
1658	if (fExtrn & CPUMCTX_EXTRN_DR6)
1659	DbgRegs.dr6 = pCtx->dr[6];
1660	if (fExtrn & CPUMCTX_EXTRN_DR7)
1661	DbgRegs.dr7 = pCtx->dr[7];
1662
1663	int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_SET_DEBUGREGS, &DbgRegs);
1664	AssertMsgReturn(rc == 0, ("rc=%d errno=%d\n", rc, errno), VERR_NEM_IPE_3);
1665	}
1666
1667	/*
1668	* FPU, SSE, AVX, ++.
1669	*/
1670	if (fExtrn & (CPUMCTX_EXTRN_X87 \| CPUMCTX_EXTRN_SSE_AVX \| CPUMCTX_EXTRN_OTHER_XSAVE \| CPUMCTX_EXTRN_XCRx))
1671	{
1672	if (fExtrn & (CPUMCTX_EXTRN_X87 \| CPUMCTX_EXTRN_SSE_AVX \| CPUMCTX_EXTRN_OTHER_XSAVE))
1673	{
1674	/** @todo could IEM just grab state partial control in some situations? */
1675	Assert( (fExtrn & (CPUMCTX_EXTRN_X87 \| CPUMCTX_EXTRN_SSE_AVX \| CPUMCTX_EXTRN_OTHER_XSAVE))
1676	== (CPUMCTX_EXTRN_X87 \| CPUMCTX_EXTRN_SSE_AVX \| CPUMCTX_EXTRN_OTHER_XSAVE)); /* no partial states */
1677
1678	AssertCompile(sizeof(pCtx->XState) >= sizeof(struct kvm_xsave));
1679	int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_SET_XSAVE, &pCtx->XState);
1680	AssertMsgReturn(rc == 0, ("rc=%d errno=%d\n", rc, errno), VERR_NEM_IPE_3);
1681	}
1682
1683	if (fExtrn & CPUMCTX_EXTRN_XCRx)
1684	{
1685	struct kvm_xcrs Xcrs =
1686	{ /.nr_xcrs = / 2,
1687	/.flags = / 0,
1688	/.xcrs= / {
1689	{ /.xcr =/ 0, /.reserved=/ 0, /.value=/ pCtx->aXcr[0] },
1690	{ /.xcr =/ 1, /.reserved=/ 0, /.value=/ pCtx->aXcr[1] },
1691	}
1692	};
1693
1694	int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_SET_XCRS, &Xcrs);
1695	AssertMsgReturn(rc == 0, ("rc=%d errno=%d\n", rc, errno), VERR_NEM_IPE_3);
1696	}
1697	}
1698
1699	/*
1700	* MSRs.
1701	*/
1702	if (fExtrn & ( CPUMCTX_EXTRN_KERNEL_GS_BASE \| CPUMCTX_EXTRN_SYSCALL_MSRS \| CPUMCTX_EXTRN_SYSENTER_MSRS
1703	\| CPUMCTX_EXTRN_TSC_AUX \| CPUMCTX_EXTRN_OTHER_MSRS))
1704	{
1705	union
1706	{
1707	struct kvm_msrs Core;
1708	uint64_t padding[2 + sizeof(struct kvm_msr_entry) * 32];
1709	} uBuf;
1710	uint32_t iMsr = 0;
1711	PCPUMCTXMSRS const pCtxMsrs = CPUMQueryGuestCtxMsrsPtr(pVCpu);
1712
1713	#define ADD_MSR(a_Msr, a_uValue) do { \
1714	Assert(iMsr < 32); \
1715	uBuf.Core.entries[iMsr].index = (a_Msr); \
1716	uBuf.Core.entries[iMsr].reserved = 0; \
1717	uBuf.Core.entries[iMsr].data = (a_uValue); \
1718	iMsr += 1; \
1719	} while (0)
1720
1721	if (fExtrn & CPUMCTX_EXTRN_KERNEL_GS_BASE)
1722	ADD_MSR(MSR_K8_KERNEL_GS_BASE, pCtx->msrKERNELGSBASE);
1723	if (fExtrn & CPUMCTX_EXTRN_SYSCALL_MSRS)
1724	{
1725	ADD_MSR(MSR_K6_STAR, pCtx->msrSTAR);
1726	ADD_MSR(MSR_K8_LSTAR, pCtx->msrLSTAR);
1727	ADD_MSR(MSR_K8_CSTAR, pCtx->msrCSTAR);
1728	ADD_MSR(MSR_K8_SF_MASK, pCtx->msrSFMASK);
1729	}
1730	if (fExtrn & CPUMCTX_EXTRN_SYSENTER_MSRS)
1731	{
1732	ADD_MSR(MSR_IA32_SYSENTER_CS, pCtx->SysEnter.cs);
1733	ADD_MSR(MSR_IA32_SYSENTER_EIP, pCtx->SysEnter.eip);
1734	ADD_MSR(MSR_IA32_SYSENTER_ESP, pCtx->SysEnter.esp);
1735	}
1736	if (fExtrn & CPUMCTX_EXTRN_TSC_AUX)
1737	ADD_MSR(MSR_K8_TSC_AUX, pCtxMsrs->msr.TscAux);
1738	if (fExtrn & CPUMCTX_EXTRN_OTHER_MSRS)
1739	{
1740	ADD_MSR(MSR_IA32_CR_PAT, pCtx->msrPAT);
1741	/** @todo What do we _have_ to add here?
1742	* We also have: Mttr, MiscEnable, FeatureControl. /
1743	}
1744
1745	uBuf.Core.pad = 0;
1746	uBuf.Core.nmsrs = iMsr;
1747	int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_SET_MSRS, &uBuf);
1748	AssertMsgReturn(rc == (int)iMsr,
1749	("rc=%d iMsr=%d (->%#x) errno=%d\n",
1750	rc, iMsr, (uint32_t)rc < iMsr ? uBuf.Core.entries[rc].index : 0, errno),
1751	VERR_NEM_IPE_3);
1752	}
1753
1754	/*
1755	* Interruptibility state.
1756	*
1757	* Note! This I/O control function sets most fields passed in, so when
1758	* raising an interrupt, NMI, SMI or exception, this must be done
1759	* by the code doing the rasing or we'll overwrite it here.
1760	*/
1761	if (fExtrn & (CPUMCTX_EXTRN_INHIBIT_INT \| CPUMCTX_EXTRN_INHIBIT_NMI))
1762	{
1763	Assert( (fExtrn & (CPUMCTX_EXTRN_INHIBIT_INT \| CPUMCTX_EXTRN_INHIBIT_NMI))
1764	== (CPUMCTX_EXTRN_INHIBIT_INT \| CPUMCTX_EXTRN_INHIBIT_NMI));
1765
1766	struct kvm_vcpu_events KvmEvents = {0};
1767
1768	KvmEvents.flags = KVM_VCPUEVENT_VALID_SHADOW;
1769	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
1770	{
1771	if (pRun->s.regs.regs.rip == EMGetInhibitInterruptsPC(pVCpu))
1772	KvmEvents.interrupt.shadow = KVM_X86_SHADOW_INT_MOV_SS \| KVM_X86_SHADOW_INT_STI;
1773	else
1774	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1775	}
1776
1777	/* No flag - this is updated unconditionally. */
1778	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1779	KvmEvents.nmi.masked = 1;
1780
1781	if (TRPMHasTrap(pVCpu))
1782	{
1783	TRPMEVENT enmType = TRPM_32BIT_HACK;
1784	uint8_t bTrapNo = 0;
1785	TRPMQueryTrap(pVCpu, &bTrapNo, &enmType);
1786	Log(("nemHCLnxExportState: Pending trap: bTrapNo=%#x enmType=%d\n", bTrapNo, enmType));
1787	if ( enmType == TRPM_HARDWARE_INT
1788	\|\| enmType == TRPM_SOFTWARE_INT)
1789	{
1790	KvmEvents.interrupt.soft = enmType == TRPM_SOFTWARE_INT;
1791	KvmEvents.interrupt.nr = bTrapNo;
1792	KvmEvents.interrupt.injected = 1;
1793	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExportPendingInterrupt);
1794	TRPMResetTrap(pVCpu);
1795	}
1796	else
1797	AssertFailed();
1798	}
1799
1800	int rcLnx = ioctl(pVCpu->nem.s.fdVCpu, KVM_SET_VCPU_EVENTS, &KvmEvents);
1801	AssertLogRelMsgReturn(rcLnx == 0, ("rcLnx=%d errno=%d\n", rcLnx, errno), VERR_NEM_IPE_3);
1802	}
1803
1804	/*
1805	* KVM now owns all the state.
1806	*/
1807	pCtx->fExtrn = CPUMCTX_EXTRN_KEEPER_NEM \| CPUMCTX_EXTRN_ALL;
1808
1809	RT_NOREF(pVM);
1810	return VINF_SUCCESS;
1811	}
1812
1813
1814	/**
1815	* Query the CPU tick counter and optionally the TSC_AUX MSR value.
1816	*
1817	* @returns VBox status code.
1818	* @param pVCpu The cross context CPU structure.
1819	* @param pcTicks Where to return the CPU tick count.
1820	* @param puAux Where to return the TSC_AUX register value.
1821	*/
1822	VMM_INT_DECL(int) NEMHCQueryCpuTick(PVMCPUCC pVCpu, uint64_t pcTicks, uint32_t puAux)
1823	{
1824	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatQueryCpuTick);
1825	// KVM_GET_CLOCK?
1826	RT_NOREF(pVCpu, pcTicks, puAux);
1827	return VINF_SUCCESS;
1828	}
1829
1830
1831	/**
1832	* Resumes CPU clock (TSC) on all virtual CPUs.
1833	*
1834	* This is called by TM when the VM is started, restored, resumed or similar.
1835	*
1836	* @returns VBox status code.
1837	* @param pVM The cross context VM structure.
1838	* @param pVCpu The cross context CPU structure of the calling EMT.
1839	* @param uPausedTscValue The TSC value at the time of pausing.
1840	*/
1841	VMM_INT_DECL(int) NEMHCResumeCpuTickOnAll(PVMCC pVM, PVMCPUCC pVCpu, uint64_t uPausedTscValue)
1842	{
1843	// KVM_SET_CLOCK?
1844	RT_NOREF(pVM, pVCpu, uPausedTscValue);
1845	return VINF_SUCCESS;
1846	}
1847
1848
1849	VMM_INT_DECL(uint32_t) NEMHCGetFeatures(PVMCC pVM)
1850	{
1851	RT_NOREF(pVM);
1852	return NEM_FEAT_F_NESTED_PAGING
1853	\| NEM_FEAT_F_FULL_GST_EXEC
1854	\| NEM_FEAT_F_XSAVE_XRSTOR;
1855	}
1856
1857
1858
1859	/*********************************************************************************************************************************
1860	* Execution *
1861	*********************************************************************************************************************************/
1862
1863
1864	VMMR3_INT_DECL(bool) NEMR3CanExecuteGuest(PVM pVM, PVMCPU pVCpu)
1865	{
1866	/*
1867	* Only execute when the A20 gate is enabled as I cannot immediately
1868	* spot any A20 support in KVM.
1869	*/
1870	RT_NOREF(pVM);
1871	Assert(VM_IS_NEM_ENABLED(pVM));
1872	return PGMPhysIsA20Enabled(pVCpu);
1873	}
1874
1875
1876	bool nemR3NativeSetSingleInstruction(PVM pVM, PVMCPU pVCpu, bool fEnable)
1877	{
1878	NOREF(pVM); NOREF(pVCpu); NOREF(fEnable);
1879	return false;
1880	}
1881
1882
1883	/**
1884	* Forced flag notification call from VMEmt.cpp.
1885	*
1886	* This is only called when pVCpu is in the VMCPUSTATE_STARTED_EXEC_NEM state.
1887	*
1888	* @param pVM The cross context VM structure.
1889	* @param pVCpu The cross context virtual CPU structure of the CPU
1890	* to be notified.
1891	* @param fFlags Notification flags, VMNOTIFYFF_FLAGS_XXX.
1892	*/
1893	void nemR3NativeNotifyFF(PVM pVM, PVMCPU pVCpu, uint32_t fFlags)
1894	{
1895	int rc = RTThreadPoke(pVCpu->hThread);
1896	LogFlow(("nemR3NativeNotifyFF: #%u -> %Rrc\n", pVCpu->idCpu, rc));
1897	AssertRC(rc);
1898	RT_NOREF(pVM, fFlags);
1899	}
1900
1901
1902	/**
1903	* Deals with pending interrupt FFs prior to executing guest code.
1904	*/
1905	static VBOXSTRICTRC nemHCLnxHandleInterruptFF(PVM pVM, PVMCPU pVCpu, struct kvm_run *pRun)
1906	{
1907	RT_NOREF_PV(pVM);
1908
1909	/*
1910	* Do not doing anything if TRPM has something pending already as we can
1911	* only inject one event per KVM_RUN call. This can only happend if we
1912	* can directly from the loop in EM, so the inhibit bits must be internal.
1913	*/
1914	if (!TRPMHasTrap(pVCpu))
1915	{ /* semi likely */ }
1916	else
1917	{
1918	Assert(!(pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_INHIBIT_INT \| CPUMCTX_EXTRN_INHIBIT_NMI)));
1919	Log8(("nemHCLnxHandleInterruptFF: TRPM has an pending event already\n"));
1920	return VINF_SUCCESS;
1921	}
1922
1923	/*
1924	* First update APIC. We ASSUME this won't need TPR/CR8.
1925	*/
1926	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
1927	{
1928	APICUpdatePendingInterrupts(pVCpu);
1929	if (!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC
1930	\| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI))
1931	return VINF_SUCCESS;
1932	}
1933
1934	/*
1935	* We don't currently implement SMIs.
1936	*/
1937	AssertReturn(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_SMI), VERR_NEM_IPE_0);
1938
1939	/*
1940	* In KVM the CPUMCTX_EXTRN_INHIBIT_INT and CPUMCTX_EXTRN_INHIBIT_NMI states
1941	* are tied together with interrupt and NMI delivery, so we must get and
1942	* synchronize these all in one go and set both CPUMCTX_EXTRN_INHIBIT_XXX flags.
1943	* If we don't we may lose the interrupt/NMI we marked pending here when the
1944	* state is exported again before execution.
1945	*/
1946	struct kvm_vcpu_events KvmEvents = {0};
1947	int rcLnx = ioctl(pVCpu->nem.s.fdVCpu, KVM_GET_VCPU_EVENTS, &KvmEvents);
1948	AssertLogRelMsgReturn(rcLnx == 0, ("rcLnx=%d errno=%d\n", rcLnx, errno), VERR_NEM_IPE_5);
1949
1950	if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_RIP))
1951	pRun->s.regs.regs.rip = pVCpu->cpum.GstCtx.rip;
1952
1953	KvmEvents.flags \|= KVM_VCPUEVENT_VALID_SHADOW;
1954	if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_INHIBIT_INT))
1955	{
1956	if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
1957	KvmEvents.interrupt.shadow = 0;
1958	else if (EMGetInhibitInterruptsPC(pVCpu) == pRun->s.regs.regs.rip)
1959	KvmEvents.interrupt.shadow = KVM_X86_SHADOW_INT_MOV_SS \| KVM_X86_SHADOW_INT_STI;
1960	else
1961	{
1962	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1963	KvmEvents.interrupt.shadow = 0;
1964	}
1965	}
1966	else if (KvmEvents.interrupt.shadow)
1967	EMSetInhibitInterruptsPC(pVCpu, pRun->s.regs.regs.rip);
1968	else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
1969	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1970
1971	if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_INHIBIT_NMI))
1972	KvmEvents.nmi.masked = VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS) ? 1 : 0;
1973	else if (KvmEvents.nmi.masked)
1974	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
1975	else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1976	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
1977
1978	/* KVM will own the INT + NMI inhibit state soon: */
1979	pVCpu->cpum.GstCtx.fExtrn = (pVCpu->cpum.GstCtx.fExtrn & ~CPUMCTX_EXTRN_KEEPER_MASK)
1980	\| CPUMCTX_EXTRN_KEEPER_NEM \| CPUMCTX_EXTRN_INHIBIT_INT \| CPUMCTX_EXTRN_INHIBIT_NMI;
1981
1982	/*
1983	* NMI? Try deliver it first.
1984	*/
1985	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI))
1986	{
1987	#if 0
1988	int rcLnx = ioctl(pVCpu->nem.s.fdVm, KVM_NMI, 0UL);
1989	AssertLogRelMsgReturn(rcLnx == 0, ("rcLnx=%d errno=%d\n", rcLnx, errno), VERR_NEM_IPE_5);
1990	#else
1991	KvmEvents.flags \|= KVM_VCPUEVENT_VALID_NMI_PENDING;
1992	KvmEvents.nmi.pending = 1;
1993	#endif
1994	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
1995	Log8(("Queuing NMI on %u\n", pVCpu->idCpu));
1996	}
1997
1998	/*
1999	* APIC or PIC interrupt?
2000	*/
2001	if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC))
2002	{
2003	if (pRun->s.regs.regs.rflags & X86_EFL_IF)
2004	{
2005	if (KvmEvents.interrupt.shadow == 0)
2006	{
2007	/*
2008	* If CR8 is in KVM, update the VBox copy so PDMGetInterrupt will
2009	* work correctly.
2010	*/
2011	if (pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_APIC_TPR)
2012	APICSetTpr(pVCpu, (uint8_t)pRun->cr8 << 4);
2013
2014	uint8_t bInterrupt;
2015	int rc = PDMGetInterrupt(pVCpu, &bInterrupt);
2016	if (RT_SUCCESS(rc))
2017	{
2018	Assert(KvmEvents.interrupt.injected == false);
2019	#if 0
2020	int rcLnx = ioctl(pVCpu->nem.s.fdVm, KVM_INTERRUPT, (unsigned long)bInterrupt);
2021	AssertLogRelMsgReturn(rcLnx == 0, ("rcLnx=%d errno=%d\n", rcLnx, errno), VERR_NEM_IPE_5);
2022	#else
2023	KvmEvents.interrupt.nr = bInterrupt;
2024	KvmEvents.interrupt.soft = false;
2025	KvmEvents.interrupt.injected = true;
2026	#endif
2027	Log8(("Queuing interrupt %#x on %u: %04x:%08RX64 efl=%#x\n", bInterrupt, pVCpu->idCpu,
2028	pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.eflags));
2029	}
2030	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR) /** @todo this isn't extremely efficient if we get a lot of exits... */
2031	Log8(("VERR_APIC_INTR_MASKED_BY_TPR\n")); /* We'll get a TRP exit - no interrupt window needed. */
2032	else
2033	Log8(("PDMGetInterrupt failed -> %Rrc\n", rc));
2034	}
2035	else
2036	{
2037	pRun->request_interrupt_window = 1;
2038	Log8(("Interrupt window pending on %u (#2)\n", pVCpu->idCpu));
2039	}
2040	}
2041	else
2042	{
2043	pRun->request_interrupt_window = 1;
2044	Log8(("Interrupt window pending on %u (#1)\n", pVCpu->idCpu));
2045	}
2046	}
2047
2048	/*
2049	* Now, update the state.
2050	*/
2051	/** @todo skip when possible... */
2052	rcLnx = ioctl(pVCpu->nem.s.fdVCpu, KVM_SET_VCPU_EVENTS, &KvmEvents);
2053	AssertLogRelMsgReturn(rcLnx == 0, ("rcLnx=%d errno=%d\n", rcLnx, errno), VERR_NEM_IPE_5);
2054
2055	return VINF_SUCCESS;
2056	}
2057
2058
2059	/**
2060	* Handles KVM_EXIT_INTERNAL_ERROR.
2061	*/
2062	static VBOXSTRICTRC nemR3LnxHandleInternalError(PVMCPU pVCpu, struct kvm_run *pRun)
2063	{
2064	Log(("NEM: KVM_EXIT_INTERNAL_ERROR! suberror=%#x (%d) ndata=%u data=%.*Rhxs\n", pRun->internal.suberror,
2065	pRun->internal.suberror, pRun->internal.ndata, sizeof(pRun->internal.data), &pRun->internal.data[0]));
2066
2067	EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, KVM_EXIT_INTERNAL_ERROR),
2068	pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());
2069
2070	/*
2071	* Deal with each suberror, returning if we don't want IEM to handle it.
2072	*/
2073	switch (pRun->internal.suberror)
2074	{
2075	case KVM_INTERNAL_ERROR_EMULATION:
2076	{
2077	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitInternalErrorEmulation);
2078	break;
2079	}
2080
2081	case KVM_INTERNAL_ERROR_SIMUL_EX:
2082	case KVM_INTERNAL_ERROR_DELIVERY_EV:
2083	case KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON:
2084	default:
2085	{
2086	const char *pszName;
2087	switch (pRun->internal.suberror)
2088	{
2089	case KVM_INTERNAL_ERROR_EMULATION: pszName = "KVM_INTERNAL_ERROR_EMULATION"; break;
2090	case KVM_INTERNAL_ERROR_SIMUL_EX: pszName = "KVM_INTERNAL_ERROR_SIMUL_EX"; break;
2091	case KVM_INTERNAL_ERROR_DELIVERY_EV: pszName = "KVM_INTERNAL_ERROR_DELIVERY_EV"; break;
2092	case KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON: pszName = "KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON"; break;
2093	default: pszName = "unknown"; break;
2094	}
2095	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitInternalErrorFatal);
2096	LogRel(("NEM: KVM_EXIT_INTERNAL_ERROR! suberror=%#x (%s) ndata=%u data=%.*Rhxs\n", pRun->internal.suberror, pszName,
2097	pRun->internal.ndata, sizeof(pRun->internal.data), &pRun->internal.data[0]));
2098	return VERR_NEM_IPE_0;
2099	}
2100	}
2101
2102	/*
2103	* Execute instruction in IEM and try get on with it.
2104	*/
2105	Log2(("nemR3LnxHandleInternalError: Executing instruction at %04x:%08RX64 in IEM\n",
2106	pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip));
2107	VBOXSTRICTRC rcStrict = nemHCLnxImportState(pVCpu,
2108	IEM_CPUMCTX_EXTRN_MUST_MASK \| CPUMCTX_EXTRN_INHIBIT_INT
2109	\| CPUMCTX_EXTRN_INHIBIT_NMI,
2110	&pVCpu->cpum.GstCtx, pRun);
2111	if (RT_SUCCESS(rcStrict))
2112	rcStrict = IEMExecOne(pVCpu);
2113	return rcStrict;
2114	}
2115
2116
2117	/**
2118	* Handles KVM_EXIT_IO.
2119	*/
2120	static VBOXSTRICTRC nemHCLnxHandleExitIo(PVMCC pVM, PVMCPUCC pVCpu, struct kvm_run *pRun)
2121	{
2122	/*
2123	* Input validation.
2124	*/
2125	Assert(pRun->io.count > 0);
2126	Assert(pRun->io.size == 1 \|\| pRun->io.size == 2 \|\| pRun->io.size == 4);
2127	Assert(pRun->io.direction == KVM_EXIT_IO_IN \|\| pRun->io.direction == KVM_EXIT_IO_OUT);
2128	Assert(pRun->io.data_offset < pVM->nem.s.cbVCpuMmap);
2129	Assert(pRun->io.data_offset + pRun->io.size * pRun->io.count <= pVM->nem.s.cbVCpuMmap);
2130
2131	/*
2132	* We cannot actually act on the exit history here, because the I/O port
2133	* exit is stateful and the instruction will be completed in the next
2134	* KVM_RUN call. There seems no way to avoid this.
2135	*/
2136	EMHistoryAddExit(pVCpu,
2137	pRun->io.count == 1
2138	? ( pRun->io.direction == KVM_EXIT_IO_IN
2139	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_READ)
2140	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_WRITE))
2141	: ( pRun->io.direction == KVM_EXIT_IO_IN
2142	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_STR_READ)
2143	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_STR_WRITE)),
2144	pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());
2145
2146	/*
2147	* Do the requested job.
2148	*/
2149	VBOXSTRICTRC rcStrict;
2150	RTPTRUNION uPtrData;
2151	uPtrData.pu8 = (uint8_t *)pRun + pRun->io.data_offset;
2152	if (pRun->io.count == 1)
2153	{
2154	if (pRun->io.direction == KVM_EXIT_IO_IN)
2155	{
2156	uint32_t uValue = 0;
2157	rcStrict = IOMIOPortRead(pVM, pVCpu, pRun->io.port, &uValue, pRun->io.size);
2158	Log4(("IOExit/%u: %04x:%08RX64: IN %#x LB %u -> %#x, rcStrict=%Rrc\n",
2159	pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip,
2160	pRun->io.port, pRun->io.size, uValue, VBOXSTRICTRC_VAL(rcStrict) ));
2161	if (IOM_SUCCESS(rcStrict))
2162	{
2163	if (pRun->io.size == 4)
2164	*uPtrData.pu32 = uValue;
2165	else if (pRun->io.size == 2)
2166	*uPtrData.pu16 = (uint16_t)uValue;
2167	else
2168	*uPtrData.pu8 = (uint8_t)uValue;
2169	}
2170	}
2171	else
2172	{
2173	uint32_t const uValue = pRun->io.size == 4 ? *uPtrData.pu32
2174	: pRun->io.size == 2 ? *uPtrData.pu16
2175	: *uPtrData.pu8;
2176	rcStrict = IOMIOPortWrite(pVM, pVCpu, pRun->io.port, uValue, pRun->io.size);
2177	Log4(("IOExit/%u: %04x:%08RX64: OUT %#x, %#x LB %u rcStrict=%Rrc\n",
2178	pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip,
2179	pRun->io.port, uValue, pRun->io.size, VBOXSTRICTRC_VAL(rcStrict) ));
2180	}
2181	}
2182	else
2183	{
2184	uint32_t cTransfers = pRun->io.count;
2185	if (pRun->io.direction == KVM_EXIT_IO_IN)
2186	{
2187	rcStrict = IOMIOPortReadString(pVM, pVCpu, pRun->io.port, uPtrData.pv, &cTransfers, pRun->io.size);
2188	Log4(("IOExit/%u: %04x:%08RX64: REP INS %#x LB %u * %#x times -> rcStrict=%Rrc cTransfers=%d\n",
2189	pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip,
2190	pRun->io.port, pRun->io.size, pRun->io.count, VBOXSTRICTRC_VAL(rcStrict), cTransfers ));
2191	}
2192	else
2193	{
2194	rcStrict = IOMIOPortWriteString(pVM, pVCpu, pRun->io.port, uPtrData.pv, &cTransfers, pRun->io.size);
2195	Log4(("IOExit/%u: %04x:%08RX64: REP OUTS %#x LB %u * %#x times -> rcStrict=%Rrc cTransfers=%d\n",
2196	pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip,
2197	pRun->io.port, pRun->io.size, pRun->io.count, VBOXSTRICTRC_VAL(rcStrict), cTransfers ));
2198	}
2199	Assert(cTransfers == 0);
2200	}
2201	return rcStrict;
2202	}
2203
2204
2205	/**
2206	* Handles KVM_EXIT_MMIO.
2207	*/
2208	static VBOXSTRICTRC nemHCLnxHandleExitMmio(PVMCC pVM, PVMCPUCC pVCpu, struct kvm_run *pRun)
2209	{
2210	/*
2211	* Input validation.
2212	*/
2213	Assert(pRun->mmio.len <= sizeof(pRun->mmio.data));
2214	Assert(pRun->mmio.is_write <= 1);
2215
2216	/*
2217	* We cannot actually act on the exit history here, because the MMIO port
2218	* exit is stateful and the instruction will be completed in the next
2219	* KVM_RUN call. There seems no way to circumvent this.
2220	*/
2221	EMHistoryAddExit(pVCpu,
2222	pRun->mmio.is_write
2223	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MMIO_WRITE)
2224	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MMIO_READ),
2225	pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());
2226
2227	/*
2228	* Do the requested job.
2229	*/
2230	VBOXSTRICTRC rcStrict;
2231	if (pRun->mmio.is_write)
2232	{
2233	rcStrict = PGMPhysWrite(pVM, pRun->mmio.phys_addr, pRun->mmio.data, pRun->mmio.len, PGMACCESSORIGIN_HM);
2234	Log4(("MmioExit/%u: %04x:%08RX64: WRITE %#x LB %u, %.*Rhxs -> rcStrict=%Rrc\n",
2235	pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip,
2236	pRun->mmio.phys_addr, pRun->mmio.len, pRun->mmio.len, pRun->mmio.data, VBOXSTRICTRC_VAL(rcStrict) ));
2237	}
2238	else
2239	{
2240	rcStrict = PGMPhysRead(pVM, pRun->mmio.phys_addr, pRun->mmio.data, pRun->mmio.len, PGMACCESSORIGIN_HM);
2241	Log4(("MmioExit/%u: %04x:%08RX64: READ %#x LB %u -> %.*Rhxs rcStrict=%Rrc\n",
2242	pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip,
2243	pRun->mmio.phys_addr, pRun->mmio.len, pRun->mmio.len, pRun->mmio.data, VBOXSTRICTRC_VAL(rcStrict) ));
2244	}
2245	return rcStrict;
2246	}
2247
2248
2249	static VBOXSTRICTRC nemHCLnxHandleExit(PVMCC pVM, PVMCPUCC pVCpu, struct kvm_run *pRun)
2250	{
2251	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitTotal);
2252	switch (pRun->exit_reason)
2253	{
2254	case KVM_EXIT_EXCEPTION:
2255	AssertFailed();
2256	break;
2257
2258	case KVM_EXIT_IO:
2259	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitIo);
2260	return nemHCLnxHandleExitIo(pVM, pVCpu, pRun);
2261
2262	case KVM_EXIT_MMIO:
2263	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitMmio);
2264	return nemHCLnxHandleExitMmio(pVM, pVCpu, pRun);
2265
2266	case KVM_EXIT_IRQ_WINDOW_OPEN:
2267	EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, KVM_EXIT_IRQ_WINDOW_OPEN),
2268	pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());
2269	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitIrqWindowOpen);
2270	Log5(("IrqWinOpen/%u: %d\n", pVCpu->idCpu, pRun->request_interrupt_window));
2271	pRun->request_interrupt_window = 0;
2272	return VINF_SUCCESS;
2273
2274	case KVM_EXIT_SET_TPR:
2275	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitSetTpr);
2276	AssertFailed();
2277	break;
2278
2279	case KVM_EXIT_TPR_ACCESS:
2280	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitTprAccess);
2281	AssertFailed();
2282	break;
2283
2284	case KVM_EXIT_X86_RDMSR:
2285	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitRdMsr);
2286	AssertFailed();
2287	break;
2288
2289	case KVM_EXIT_X86_WRMSR:
2290	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitWrMsr);
2291	AssertFailed();
2292	break;
2293
2294	case KVM_EXIT_HLT:
2295	EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, KVM_EXIT_HLT),
2296	pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());
2297	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitHalt);
2298	Log5(("Halt/%u\n", pVCpu->idCpu));
2299	return VINF_EM_HALT;
2300
2301	case KVM_EXIT_INTR: /* EINTR */
2302	EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, KVM_EXIT_INTR),
2303	pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());
2304	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitIntr);
2305	Log5(("Intr/%u\n", pVCpu->idCpu));
2306	return VINF_SUCCESS;
2307
2308	case KVM_EXIT_HYPERCALL:
2309	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitHypercall);
2310	AssertFailed();
2311	break;
2312
2313	case KVM_EXIT_DEBUG:
2314	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitDebug);
2315	AssertFailed();
2316	break;
2317
2318	case KVM_EXIT_SYSTEM_EVENT:
2319	AssertFailed();
2320	break;
2321	case KVM_EXIT_IOAPIC_EOI:
2322	AssertFailed();
2323	break;
2324	case KVM_EXIT_HYPERV:
2325	AssertFailed();
2326	break;
2327
2328	case KVM_EXIT_DIRTY_RING_FULL:
2329	AssertFailed();
2330	break;
2331	case KVM_EXIT_AP_RESET_HOLD:
2332	AssertFailed();
2333	break;
2334	case KVM_EXIT_X86_BUS_LOCK:
2335	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitBusLock);
2336	AssertFailed();
2337	break;
2338
2339
2340	case KVM_EXIT_SHUTDOWN:
2341	AssertFailed();
2342	break;
2343
2344	case KVM_EXIT_FAIL_ENTRY:
2345	LogRel(("NEM: KVM_EXIT_FAIL_ENTRY! hardware_entry_failure_reason=%#x cpu=%#x\n",
2346	pRun->fail_entry.hardware_entry_failure_reason, pRun->fail_entry.cpu));
2347	return VERR_NEM_IPE_1;
2348
2349	case KVM_EXIT_INTERNAL_ERROR:
2350	/* we're counting sub-reasons inside the function. */
2351	return nemR3LnxHandleInternalError(pVCpu, pRun);
2352
2353	/*
2354	* Foreign and unknowns.
2355	*/
2356	case KVM_EXIT_NMI:
2357	AssertLogRelMsgFailedReturn(("KVM_EXIT_NMI on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2358	case KVM_EXIT_EPR:
2359	AssertLogRelMsgFailedReturn(("KVM_EXIT_EPR on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2360	case KVM_EXIT_WATCHDOG:
2361	AssertLogRelMsgFailedReturn(("KVM_EXIT_WATCHDOG on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2362	case KVM_EXIT_ARM_NISV:
2363	AssertLogRelMsgFailedReturn(("KVM_EXIT_ARM_NISV on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2364	case KVM_EXIT_S390_STSI:
2365	AssertLogRelMsgFailedReturn(("KVM_EXIT_S390_STSI on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2366	case KVM_EXIT_S390_TSCH:
2367	AssertLogRelMsgFailedReturn(("KVM_EXIT_S390_TSCH on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2368	case KVM_EXIT_OSI:
2369	AssertLogRelMsgFailedReturn(("KVM_EXIT_OSI on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2370	case KVM_EXIT_PAPR_HCALL:
2371	AssertLogRelMsgFailedReturn(("KVM_EXIT_PAPR_HCALL on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2372	case KVM_EXIT_S390_UCONTROL:
2373	AssertLogRelMsgFailedReturn(("KVM_EXIT_S390_UCONTROL on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2374	case KVM_EXIT_DCR:
2375	AssertLogRelMsgFailedReturn(("KVM_EXIT_DCR on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2376	case KVM_EXIT_S390_SIEIC:
2377	AssertLogRelMsgFailedReturn(("KVM_EXIT_S390_SIEIC on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2378	case KVM_EXIT_S390_RESET:
2379	AssertLogRelMsgFailedReturn(("KVM_EXIT_S390_RESET on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2380	case KVM_EXIT_UNKNOWN:
2381	AssertLogRelMsgFailedReturn(("KVM_EXIT_UNKNOWN on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2382	case KVM_EXIT_XEN:
2383	AssertLogRelMsgFailedReturn(("KVM_EXIT_XEN on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2384	default:
2385	AssertLogRelMsgFailedReturn(("Unknown exit reason %u on VCpu #%u at %04x:%RX64!\n", pRun->exit_reason, pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2386	}
2387
2388	RT_NOREF(pVM, pVCpu, pRun);
2389	return VERR_NOT_IMPLEMENTED;
2390	}
2391
2392
2393	VBOXSTRICTRC nemR3NativeRunGC(PVM pVM, PVMCPU pVCpu)
2394	{
2395	/*
2396	* Try switch to NEM runloop state.
2397	*/
2398	if (VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED))
2399	{ /* likely */ }
2400	else
2401	{
2402	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED);
2403	LogFlow(("NEM/%u: returning immediately because canceled\n", pVCpu->idCpu));
2404	return VINF_SUCCESS;
2405	}
2406
2407	/*
2408	* The run loop.
2409	*/
2410	struct kvm_run * const pRun = pVCpu->nem.s.pRun;
2411	const bool fSingleStepping = DBGFIsStepping(pVCpu);
2412	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
2413	for (unsigned iLoop = 0;; iLoop++)
2414	{
2415	/*
2416	* Pending interrupts or such? Need to check and deal with this prior
2417	* to the state syncing.
2418	*/
2419	if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC
2420	\| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI))
2421	{
2422	/* Try inject interrupt. */
2423	rcStrict = nemHCLnxHandleInterruptFF(pVM, pVCpu, pRun);
2424	if (rcStrict == VINF_SUCCESS)
2425	{ /* likely */ }
2426	else
2427	{
2428	LogFlow(("NEM/%u: breaking: nemHCLnxHandleInterruptFF -> %Rrc\n", pVCpu->idCpu, VBOXSTRICTRC_VAL(rcStrict) ));
2429	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnStatus);
2430	break;
2431	}
2432	}
2433
2434	/*
2435	* Do not execute in KVM if the A20 isn't enabled.
2436	*/
2437	if (PGMPhysIsA20Enabled(pVCpu))
2438	{ /* likely */ }
2439	else
2440	{
2441	rcStrict = VINF_EM_RESCHEDULE_REM;
2442	LogFlow(("NEM/%u: breaking: A20 disabled\n", pVCpu->idCpu));
2443	break;
2444	}
2445
2446	/*
2447	* Ensure KVM has the whole state.
2448	*/
2449	if ((pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL) != CPUMCTX_EXTRN_ALL)
2450	{
2451	int rc2 = nemHCLnxExportState(pVM, pVCpu, &pVCpu->cpum.GstCtx, pRun);
2452	AssertRCReturn(rc2, rc2);
2453	}
2454
2455	/*
2456	* Poll timers and run for a bit.
2457	*
2458	* With the VID approach (ring-0 or ring-3) we can specify a timeout here,
2459	* so we take the time of the next timer event and uses that as a deadline.
2460	* The rounding heuristics are "tuned" so that rhel5 (1K timer) will boot fine.
2461	*/
2462	/** @todo See if we cannot optimize this TMTimerPollGIP by only redoing
2463	* the whole polling job when timers have changed... */
2464	uint64_t offDeltaIgnored;
2465	uint64_t const nsNextTimerEvt = TMTimerPollGIP(pVM, pVCpu, &offDeltaIgnored); NOREF(nsNextTimerEvt);
2466	if ( !VM_FF_IS_ANY_SET(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
2467	&& !VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
2468	{
2469	if (VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM_WAIT, VMCPUSTATE_STARTED_EXEC_NEM))
2470	{
2471	LogFlow(("NEM/%u: Entry @ %04x:%08RX64 IF=%d EFL=%#RX64 SS:RSP=%04x:%08RX64 cr0=%RX64\n",
2472	pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip,
2473	!!(pRun->s.regs.regs.rflags & X86_EFL_IF), pRun->s.regs.regs.rflags,
2474	pRun->s.regs.sregs.ss.selector, pRun->s.regs.regs.rsp, pRun->s.regs.sregs.cr0));
2475	TMNotifyStartOfExecution(pVM, pVCpu);
2476
2477	int rcLnx = ioctl(pVCpu->nem.s.fdVCpu, KVM_RUN, 0UL);
2478
2479	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED_EXEC_NEM_WAIT);
2480	TMNotifyEndOfExecution(pVM, pVCpu, ASMReadTSC());
2481
2482	#ifdef LOG_ENABLED
2483	if (LogIsFlowEnabled())
2484	{
2485	struct kvm_mp_state MpState = {UINT32_MAX};
2486	ioctl(pVCpu->nem.s.fdVCpu, KVM_GET_MP_STATE, &MpState);
2487	LogFlow(("NEM/%u: Exit @ %04x:%08RX64 IF=%d EFL=%#RX64 CR8=%#x Reason=%#x IrqReady=%d Flags=%#x %#lx\n", pVCpu->idCpu,
2488	pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip, pRun->if_flag,
2489	pRun->s.regs.regs.rflags, pRun->s.regs.sregs.cr8, pRun->exit_reason,
2490	pRun->ready_for_interrupt_injection, pRun->flags, MpState.mp_state));
2491	}
2492	#endif
2493	if (RT_LIKELY(rcLnx == 0 \|\| errno == EINTR))
2494	{
2495	/*
2496	* Deal with the message.
2497	*/
2498	rcStrict = nemHCLnxHandleExit(pVM, pVCpu, pRun);
2499	if (rcStrict == VINF_SUCCESS)
2500	{ /* hopefully likely */ }
2501	else
2502	{
2503	LogFlow(("NEM/%u: breaking: nemHCLnxHandleExit -> %Rrc\n", pVCpu->idCpu, VBOXSTRICTRC_VAL(rcStrict) ));
2504	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnStatus);
2505	break;
2506	}
2507	}
2508	else
2509	{
2510	int rc2 = RTErrConvertFromErrno(errno);
2511	AssertLogRelMsgFailedReturn(("KVM_RUN failed: rcLnx=%d errno=%u rc=%Rrc\n", rcLnx, errno, rc2), rc2);
2512	}
2513
2514	/*
2515	* If no relevant FFs are pending, loop.
2516	*/
2517	if ( !VM_FF_IS_ANY_SET( pVM, !fSingleStepping ? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
2518	&& !VMCPU_FF_IS_ANY_SET(pVCpu, !fSingleStepping ? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
2519	continue;
2520
2521	/** @todo Try handle pending flags, not just return to EM loops. Take care
2522	* not to set important RCs here unless we've handled an exit. */
2523	LogFlow(("NEM/%u: breaking: pending FF (%#x / %#RX64)\n",
2524	pVCpu->idCpu, pVM->fGlobalForcedActions, (uint64_t)pVCpu->fLocalForcedActions));
2525	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnFFPost);
2526	}
2527	else
2528	{
2529	LogFlow(("NEM/%u: breaking: canceled %d (pre exec)\n", pVCpu->idCpu, VMCPU_GET_STATE(pVCpu) ));
2530	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnCancel);
2531	}
2532	}
2533	else
2534	{
2535	LogFlow(("NEM/%u: breaking: pending FF (pre exec)\n", pVCpu->idCpu));
2536	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnFFPre);
2537	}
2538	break;
2539	} /* the run loop */
2540
2541
2542	/*
2543	* If the CPU is running, make sure to stop it before we try sync back the
2544	* state and return to EM. We don't sync back the whole state if we can help it.
2545	*/
2546	if (!VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_NEM))
2547	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED);
2548
2549	if (pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL)
2550	{
2551	/* Try anticipate what we might need. */
2552	uint64_t fImport = CPUMCTX_EXTRN_INHIBIT_INT \| CPUMCTX_EXTRN_INHIBIT_NMI /* Required for processing APIC,PIC,NMI & SMI FFs. */
2553	\| IEM_CPUMCTX_EXTRN_MUST_MASK /?/;
2554	if ( (rcStrict >= VINF_EM_FIRST && rcStrict <= VINF_EM_LAST)
2555	\|\| RT_FAILURE(rcStrict))
2556	fImport = CPUMCTX_EXTRN_ALL;
2557	# ifdef IN_RING0 /* Ring-3 I/O port access optimizations: */
2558	else if ( rcStrict == VINF_IOM_R3_IOPORT_COMMIT_WRITE
2559	\|\| rcStrict == VINF_EM_PENDING_R3_IOPORT_WRITE)
2560	fImport = CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RFLAGS;
2561	else if (rcStrict == VINF_EM_PENDING_R3_IOPORT_READ)
2562	fImport = CPUMCTX_EXTRN_RAX \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RFLAGS;
2563	# endif
2564	else if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC \| VMCPU_FF_INTERRUPT_APIC
2565	\| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI))
2566	fImport \|= IEM_CPUMCTX_EXTRN_XCPT_MASK;
2567
2568	if (pVCpu->cpum.GstCtx.fExtrn & fImport)
2569	{
2570	int rc2 = nemHCLnxImportState(pVCpu, fImport, &pVCpu->cpum.GstCtx, pRun);
2571	if (RT_SUCCESS(rc2))
2572	pVCpu->cpum.GstCtx.fExtrn &= ~fImport;
2573	else if (RT_SUCCESS(rcStrict))
2574	rcStrict = rc2;
2575	if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL))
2576	pVCpu->cpum.GstCtx.fExtrn = 0;
2577	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturn);
2578	}
2579	else
2580	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturnSkipped);
2581	}
2582	else
2583	{
2584	pVCpu->cpum.GstCtx.fExtrn = 0;
2585	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturnSkipped);
2586	}
2587
2588	LogFlow(("NEM/%u: %04x:%08RX64 efl=%#08RX64 => %Rrc\n", pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
2589	pVCpu->cpum.GstCtx.rflags, VBOXSTRICTRC_VAL(rcStrict) ));
2590	return rcStrict;
2591	}
2592
2593
2594	/** @page pg_nem_linux NEM/linux - Native Execution Manager, Linux.
2595	*
2596	* This is using KVM.
2597	*
2598	*/
2599

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source: vbox/trunk/src/VBox/VMM/VMMR3/NEMR3Native-linux.cpp@ 92521

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