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source: vbox/trunk/src/VBox/VMM/VMMR3/NEMR3Native-darwin-armv8.cpp@ 105693

最後變更 在這個檔案從105693是 105693,由 vboxsync 提交於 7 月 前

VMMArm/NEMR3Native-darwin-armv8: Some preliminary code to support the new nested virtualization (EL2) support with the upcoming Sequioa (15.0) on M3 hardware, not yet working, bugref:10747 [doxygen]
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1/* $Id: NEMR3Native-darwin-armv8.cpp 105693 2024-08-15 13:05:42Z vboxsync $ */
2/** @file
3 * NEM - Native execution manager, native ring-3 macOS backend using Hypervisor.framework, ARMv8 variant.
4 *
5 * Log group 2: Exit logging.
6 * Log group 3: Log context on exit.
7 * Log group 5: Ring-3 memory management
8 */
9
10/*
11 * Copyright (C) 2023 Oracle and/or its affiliates.
12 *
13 * This file is part of VirtualBox base platform packages, as
14 * available from https://www.alldomusa.eu.org.
15 *
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License
18 * as published by the Free Software Foundation, in version 3 of the
19 * License.
20 *
21 * This program is distributed in the hope that it will be useful, but
22 * WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
24 * General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, see <https://www.gnu.org/licenses>.
28 *
29 * SPDX-License-Identifier: GPL-3.0-only
30 */
31
32
33/*********************************************************************************************************************************
34* Header Files *
35*********************************************************************************************************************************/
36#define LOG_GROUP LOG_GROUP_NEM
37#define VMCPU_INCL_CPUM_GST_CTX
38#include <VBox/vmm/nem.h>
39#include <VBox/vmm/iem.h>
40#include <VBox/vmm/em.h>
41#include <VBox/vmm/gic.h>
42#include <VBox/vmm/pdm.h>
43#include <VBox/vmm/dbgftrace.h>
44#include <VBox/vmm/gcm.h>
45#include "NEMInternal.h"
46#include <VBox/vmm/vmcc.h>
47#include <VBox/vmm/vmm.h>
48#include <VBox/gic.h>
49#include "dtrace/VBoxVMM.h"
50
51#include <iprt/armv8.h>
52#include <iprt/asm.h>
53#include <iprt/asm-arm.h>
54#include <iprt/asm-math.h>
55#include <iprt/ldr.h>
56#include <iprt/mem.h>
57#include <iprt/path.h>
58#include <iprt/string.h>
59#include <iprt/system.h>
60#include <iprt/utf16.h>
61
62#include <iprt/formats/arm-psci.h>
63
64#include <mach/mach_time.h>
65#include <mach/kern_return.h>
66
67#include <Hypervisor/Hypervisor.h>
68
69
70/*********************************************************************************************************************************
71* Defined Constants And Macros *
72*********************************************************************************************************************************/
73
74
75/*********************************************************************************************************************************
76* Structures and Typedefs *
77*********************************************************************************************************************************/
78
79#if MAC_OS_X_VERSION_MIN_REQUIRED < 150000
80
81/* Since 15.0+ */
82typedef enum hv_gic_distributor_reg_t : uint16_t
83{
84 HV_GIC_DISTRIBUTOR_REG_GICD_CTLR,
85 HV_GIC_DISTRIBUTOR_REG_GICD_ICACTIVER0
86 /** @todo */
87} hv_gic_distributor_reg_t;
88
89
90typedef enum hv_gic_icc_reg_t : uint16_t
91{
92 HV_GIC_ICC_REG_AP0R0_EL1
93 /** @todo */
94} hv_gic_icc_reg_t;
95
96
97typedef enum hv_gic_ich_reg_t : uint16_t
98{
99 HV_GIC_ICH_REG_AP0R0_EL2
100 /** @todo */
101} hv_gic_ich_reg_t;
102
103
104typedef enum hv_gic_icv_reg_t : uint16_t
105{
106 HV_GIC_ICV_REG_AP0R0_EL1
107 /** @todo */
108} hv_gic_icv_reg_t;
109
110
111typedef enum hv_gic_msi_reg_t : uint16_t
112{
113 HV_GIC_REG_GICM_SET_SPI_NSR
114 /** @todo */
115} hv_gic_msi_reg_t;
116
117
118typedef enum hv_gic_redistributor_reg_t : uint16_t
119{
120 HV_GIC_REDISTRIBUTOR_REG_GICR_ICACTIVER0
121 /** @todo */
122} hv_gic_redistributor_reg_t;
123
124
125typedef enum hv_gic_intid_t : uint16_t
126{
127 HV_GIC_INT_EL1_PHYSICAL_TIMER = 23,
128 HV_GIC_INT_EL1_VIRTUAL_TIMER = 25,
129 HV_GIC_INT_EL2_PHYSICAL_TIMER = 26,
130 HV_GIC_INT_MAINTENANCE = 27,
131 HV_GIC_INT_PERFORMANCE_MONITOR = 30
132} hv_gic_intid_t;
133
134#endif
135
136typedef hv_return_t FN_HV_VM_CONFIG_GET_EL2_SUPPORTED(bool *el2_supported);
137typedef hv_return_t FN_HV_VM_CONFIG_GET_EL2_ENABLED(hv_vm_config_t config, bool *el2_enabled);
138typedef hv_return_t FN_HV_VM_CONFIG_SET_EL2_ENABLED(hv_vm_config_t config, bool el2_enabled);
139
140typedef struct hv_gic_config_s *hv_gic_config_t;
141typedef hv_return_t FN_HV_GIC_CREATE(hv_gic_config_t gic_config);
142typedef hv_return_t FN_HV_GIC_RESET(void);
143typedef hv_gic_config_t FN_HV_GIC_CONFIG_CREATE(void);
144typedef hv_return_t FN_HV_GIC_CONFIG_SET_DISTRIBUTOR_BASE(hv_gic_config_t config, hv_ipa_t distributor_base_address);
145typedef hv_return_t FN_HV_GIC_CONFIG_SET_REDISTRIBUTOR_BASE(hv_gic_config_t config, hv_ipa_t redistributor_base_address);
146typedef hv_return_t FN_HV_GIC_CONFIG_SET_MSI_REGION_BASE(hv_gic_config_t config, hv_ipa_t msi_region_base_address);
147typedef hv_return_t FN_HV_GIC_CONFIG_SET_MSI_INTERRUPT_RANGE(hv_gic_config_t config, uint32_t msi_intid_base, uint32_t msi_intid_count);
148
149typedef hv_return_t FN_HV_GIC_GET_REDISTRIBUTOR_BASE(hv_vcpu_t vcpu, hv_ipa_t *redistributor_base_address);
150typedef hv_return_t FN_HV_GIC_GET_REDISTRIBUTOR_REGION_SIZE(size_t *redistributor_region_size);
151typedef hv_return_t FN_HV_GIC_GET_REDISTRIBUTOR_SIZE(size_t *redistributor_size);
152typedef hv_return_t FN_HV_GIC_GET_DISTRIBUTOR_SIZE(size_t *distributor_size);
153typedef hv_return_t FN_HV_GIC_GET_DISTRIBUTOR_BASE_ALIGNMENT(size_t *distributor_base_alignment);
154typedef hv_return_t FN_HV_GIC_GET_REDISTRIBUTOR_BASE_ALIGNMENT(size_t *redistributor_base_alignment);
155typedef hv_return_t FN_HV_GIC_GET_MSI_REGION_BASE_ALIGNMENT(size_t *msi_region_base_alignment);
156typedef hv_return_t FN_HV_GIC_GET_MSI_REGION_SIZE(size_t *msi_region_size);
157typedef hv_return_t FN_HV_GIC_GET_SPI_INTERRUPT_RANGE(uint32_t *spi_intid_base, uint32_t *spi_intid_count);
158
159typedef struct hv_gic_state_s *hv_gic_state_t;
160typedef hv_gic_state_t FN_HV_GIC_STATE_CREATE(void);
161typedef hv_return_t FN_HV_GIC_SET_STATE(const void *gic_state_data, size_t gic_state_size);
162typedef hv_return_t FN_HV_GIC_STATE_GET_SIZE(hv_gic_state_t state, size_t *gic_state_size);
163typedef hv_return_t FN_HV_GIC_STATE_GET_DATA(hv_gic_state_t state, void *gic_state_data);
164
165typedef hv_return_t FN_HV_GIC_SEND_MSI(hv_ipa_t address, uint32_t intid);
166typedef hv_return_t FN_HV_GIC_SET_SPI(uint32_t intid, bool level);
167
168typedef hv_return_t FN_HV_GIC_GET_DISTRIBUTOR_REG(hv_gic_distributor_reg_t reg, uint64_t *value);
169typedef hv_return_t FN_HV_GIC_GET_MSI_REG(hv_gic_msi_reg_t reg, uint64_t *value);
170typedef hv_return_t FN_HV_GIC_GET_ICC_REG(hv_vcpu_t vcpu, hv_gic_icc_reg_t reg, uint64_t *value);
171typedef hv_return_t FN_HV_GIC_GET_ICH_REG(hv_vcpu_t vcpu, hv_gic_ich_reg_t reg, uint64_t *value);
172typedef hv_return_t FN_HV_GIC_GET_ICV_REG(hv_vcpu_t vcpu, hv_gic_icv_reg_t reg, uint64_t *value);
173typedef hv_return_t FN_HV_GIC_GET_REDISTRIBUTOR_REG(hv_vcpu_t vcpu, hv_gic_redistributor_reg_t reg, uint64_t *value);
174
175typedef hv_return_t FN_HV_GIC_SET_DISTRIBUTOR_REG(hv_gic_distributor_reg_t reg, uint64_t value);
176typedef hv_return_t FN_HV_GIC_SET_MSI_REG(hv_gic_msi_reg_t reg, uint64_t value);
177typedef hv_return_t FN_HV_GIC_SET_ICC_REG(hv_vcpu_t vcpu, hv_gic_icc_reg_t reg, uint64_t value);
178typedef hv_return_t FN_HV_GIC_SET_ICH_REG(hv_vcpu_t vcpu, hv_gic_ich_reg_t reg, uint64_t value);
179typedef hv_return_t FN_HV_GIC_SET_ICV_REG(hv_vcpu_t vcpu, hv_gic_icv_reg_t reg, uint64_t value);
180typedef hv_return_t FN_HV_GIC_SET_REDISTRIBUTOR_REG(hv_vcpu_t vcpu, hv_gic_redistributor_reg_t reg, uint64_t value);
181
182typedef hv_return_t FN_HV_GIC_GET_INTID(hv_gic_intid_t interrupt, uint32_t *intid);
183
184
185/*********************************************************************************************************************************
186* Global Variables *
187*********************************************************************************************************************************/
188/** @name Optional APIs imported from Hypervisor.framework.
189 * @{ */
190static FN_HV_VM_CONFIG_GET_EL2_SUPPORTED *g_pfnHvVmConfigGetEl2Supported = NULL; /* Since 15.0 */
191static FN_HV_VM_CONFIG_GET_EL2_ENABLED *g_pfnHvVmConfigGetEl2Enabled = NULL; /* Since 15.0 */
192static FN_HV_VM_CONFIG_SET_EL2_ENABLED *g_pfnHvVmConfigSetEl2Enabled = NULL; /* Since 15.0 */
193
194static FN_HV_GIC_CREATE *g_pfnHvGicCreate = NULL; /* Since 15.0 */
195static FN_HV_GIC_RESET *g_pfnHvGicReset = NULL; /* Since 15.0 */
196static FN_HV_GIC_CONFIG_CREATE *g_pfnHvGicConfigCreate = NULL; /* Since 15.0 */
197static FN_HV_GIC_CONFIG_SET_DISTRIBUTOR_BASE *g_pfnHvGicConfigSetDistributorBase = NULL; /* Since 15.0 */
198static FN_HV_GIC_CONFIG_SET_REDISTRIBUTOR_BASE *g_pfnHvGicConfigSetRedistributorBase = NULL; /* Since 15.0 */
199static FN_HV_GIC_CONFIG_SET_MSI_REGION_BASE *g_pfnHvGicConfigSetMsiRegionBase = NULL; /* Since 15.0 */
200static FN_HV_GIC_CONFIG_SET_MSI_INTERRUPT_RANGE *g_pfnHvGicConfigSetMsiInterruptRange = NULL; /* Since 15.0 */
201static FN_HV_GIC_GET_REDISTRIBUTOR_BASE *g_pfnHvGicGetRedistributorBase = NULL; /* Since 15.0 */
202static FN_HV_GIC_GET_REDISTRIBUTOR_REGION_SIZE *g_pfnHvGicGetRedistributorRegionSize = NULL; /* Since 15.0 */
203static FN_HV_GIC_GET_REDISTRIBUTOR_SIZE *g_pfnHvGicGetRedistributorSize = NULL; /* Since 15.0 */
204static FN_HV_GIC_GET_DISTRIBUTOR_SIZE *g_pfnHvGicGetDistributorSize = NULL; /* Since 15.0 */
205static FN_HV_GIC_GET_DISTRIBUTOR_BASE_ALIGNMENT *g_pfnHvGicGetDistributorBaseAlignment = NULL; /* Since 15.0 */
206static FN_HV_GIC_GET_REDISTRIBUTOR_BASE_ALIGNMENT *g_pfnHvGicGetRedistributorBaseAlignment = NULL; /* Since 15.0 */
207static FN_HV_GIC_GET_MSI_REGION_BASE_ALIGNMENT *g_pfnHvGicGetMsiRegionBaseAlignment = NULL; /* Since 15.0 */
208static FN_HV_GIC_GET_MSI_REGION_SIZE *g_pfnHvGicGetMsiRegionSize = NULL; /* Since 15.0 */
209static FN_HV_GIC_GET_SPI_INTERRUPT_RANGE *g_pfnHvGicGetSpiInterruptRange = NULL; /* Since 15.0 */
210static FN_HV_GIC_STATE_CREATE *g_pfnHvGicStateCreate = NULL; /* Since 15.0 */
211static FN_HV_GIC_SET_STATE *g_pfnHvGicSetState = NULL; /* Since 15.0 */
212static FN_HV_GIC_STATE_GET_SIZE *g_pfnHvGicStateGetSize = NULL; /* Since 15.0 */
213static FN_HV_GIC_STATE_GET_DATA *g_pfnHvGicStateGetData = NULL; /* Since 15.0 */
214static FN_HV_GIC_SEND_MSI *g_pfnHvGicSendMsi = NULL; /* Since 15.0 */
215static FN_HV_GIC_SET_SPI *g_pfnHvGicSetSpi = NULL; /* Since 15.0 */
216static FN_HV_GIC_GET_DISTRIBUTOR_REG *g_pfnHvGicGetDistributorReg = NULL; /* Since 15.0 */
217static FN_HV_GIC_GET_MSI_REG *g_pfnHvGicGetMsiReg = NULL; /* Since 15.0 */
218static FN_HV_GIC_GET_ICC_REG *g_pfnHvGicGetIccReg = NULL; /* Since 15.0 */
219static FN_HV_GIC_GET_ICH_REG *g_pfnHvGicGetIchReg = NULL; /* Since 15.0 */
220static FN_HV_GIC_GET_ICV_REG *g_pfnHvGicGetIcvReg = NULL; /* Since 15.0 */
221static FN_HV_GIC_GET_REDISTRIBUTOR_REG *g_pfnHvGicGetRedistributorReg = NULL; /* Since 15.0 */
222static FN_HV_GIC_SET_DISTRIBUTOR_REG *g_pfnHvGicSetDistributorReg = NULL; /* Since 15.0 */
223static FN_HV_GIC_SET_MSI_REG *g_pfnHvGicSetMsiReg = NULL; /* Since 15.0 */
224static FN_HV_GIC_SET_ICC_REG *g_pfnHvGicSetIccReg = NULL; /* Since 15.0 */
225static FN_HV_GIC_SET_ICH_REG *g_pfnHvGicSetIchReg = NULL; /* Since 15.0 */
226static FN_HV_GIC_SET_ICV_REG *g_pfnHvGicSetIcvReg = NULL; /* Since 15.0 */
227static FN_HV_GIC_SET_REDISTRIBUTOR_REG *g_pfnHvGicSetRedistributorReg = NULL; /* Since 15.0 */
228static FN_HV_GIC_GET_INTID *g_pfnHvGicGetIntid = NULL; /* Since 15.0 */
229/** @} */
230
231
232/**
233 * Import instructions.
234 */
235static const struct
236{
237 void **ppfn; /**< The function pointer variable. */
238 const char *pszName; /**< The function name. */
239} g_aImports[] =
240{
241#define NEM_DARWIN_IMPORT(a_Pfn, a_Name) { (void **)&(a_Pfn), #a_Name }
242 NEM_DARWIN_IMPORT(g_pfnHvVmConfigGetEl2Supported, hv_vm_config_get_el2_supported),
243 NEM_DARWIN_IMPORT(g_pfnHvVmConfigGetEl2Enabled, hv_vm_config_get_el2_enabled),
244 NEM_DARWIN_IMPORT(g_pfnHvVmConfigSetEl2Enabled, hv_vm_config_set_el2_enabled),
245
246 NEM_DARWIN_IMPORT(g_pfnHvGicCreate, hv_gic_create),
247 NEM_DARWIN_IMPORT(g_pfnHvGicReset, hv_gic_reset),
248 NEM_DARWIN_IMPORT(g_pfnHvGicConfigCreate, hv_gic_config_create),
249 NEM_DARWIN_IMPORT(g_pfnHvGicConfigSetDistributorBase, hv_gic_config_set_distributor_base),
250 NEM_DARWIN_IMPORT(g_pfnHvGicConfigSetRedistributorBase, hv_gic_config_set_redistributor_base),
251 NEM_DARWIN_IMPORT(g_pfnHvGicConfigSetMsiRegionBase, hv_gic_config_set_msi_region_base),
252 NEM_DARWIN_IMPORT(g_pfnHvGicConfigSetMsiInterruptRange, hv_gic_config_set_msi_interrupt_range),
253 NEM_DARWIN_IMPORT(g_pfnHvGicGetRedistributorBase, hv_gic_get_redistributor_base),
254 NEM_DARWIN_IMPORT(g_pfnHvGicGetRedistributorRegionSize, hv_gic_get_redistributor_region_size),
255 NEM_DARWIN_IMPORT(g_pfnHvGicGetRedistributorSize, hv_gic_get_redistributor_size),
256 NEM_DARWIN_IMPORT(g_pfnHvGicGetDistributorSize, hv_gic_get_distributor_size),
257 NEM_DARWIN_IMPORT(g_pfnHvGicGetDistributorBaseAlignment, hv_gic_get_distributor_base_alignment),
258 NEM_DARWIN_IMPORT(g_pfnHvGicGetRedistributorBaseAlignment, hv_gic_get_redistributor_base_alignment),
259 NEM_DARWIN_IMPORT(g_pfnHvGicGetMsiRegionBaseAlignment, hv_gic_get_msi_region_base_alignment),
260 NEM_DARWIN_IMPORT(g_pfnHvGicGetMsiRegionSize, hv_gic_get_msi_region_size),
261 NEM_DARWIN_IMPORT(g_pfnHvGicGetSpiInterruptRange, hv_gic_get_spi_interrupt_range),
262 NEM_DARWIN_IMPORT(g_pfnHvGicStateCreate, hv_gic_state_create),
263 NEM_DARWIN_IMPORT(g_pfnHvGicSetState, hv_gic_set_state),
264 NEM_DARWIN_IMPORT(g_pfnHvGicStateGetSize, hv_gic_state_get_size),
265 NEM_DARWIN_IMPORT(g_pfnHvGicStateGetData, hv_gic_state_get_data),
266 NEM_DARWIN_IMPORT(g_pfnHvGicSendMsi, hv_gic_send_msi),
267 NEM_DARWIN_IMPORT(g_pfnHvGicSetSpi, hv_gic_set_spi),
268 NEM_DARWIN_IMPORT(g_pfnHvGicGetDistributorReg, hv_gic_get_distributor_reg),
269 NEM_DARWIN_IMPORT(g_pfnHvGicGetMsiReg, hv_gic_get_msi_reg),
270 NEM_DARWIN_IMPORT(g_pfnHvGicGetIccReg, hv_gic_get_icc_reg),
271 NEM_DARWIN_IMPORT(g_pfnHvGicGetIchReg, hv_gic_get_ich_reg),
272 NEM_DARWIN_IMPORT(g_pfnHvGicGetIcvReg, hv_gic_get_icv_reg),
273 NEM_DARWIN_IMPORT(g_pfnHvGicGetRedistributorReg, hv_gic_get_redistributor_reg),
274 NEM_DARWIN_IMPORT(g_pfnHvGicSetDistributorReg, hv_gic_set_distributor_reg),
275 NEM_DARWIN_IMPORT(g_pfnHvGicSetMsiReg, hv_gic_set_msi_reg),
276 NEM_DARWIN_IMPORT(g_pfnHvGicSetIccReg, hv_gic_set_icc_reg),
277 NEM_DARWIN_IMPORT(g_pfnHvGicSetIchReg, hv_gic_set_ich_reg),
278 NEM_DARWIN_IMPORT(g_pfnHvGicSetIcvReg, hv_gic_set_icv_reg),
279 NEM_DARWIN_IMPORT(g_pfnHvGicSetRedistributorReg, hv_gic_set_redistributor_reg),
280 NEM_DARWIN_IMPORT(g_pfnHvGicGetIntid, hv_gic_get_intid)
281#undef NEM_DARWIN_IMPORT
282};
283
284
285/*
286 * Let the preprocessor alias the APIs to import variables for better autocompletion.
287 */
288#ifndef IN_SLICKEDIT
289# define hv_vm_config_get_el2_supported g_pfnHvVmConfigGetEl2Supported
290# define hv_vm_config_get_el2_enabled g_pfnHvVmConfigGetEl2Enabled
291# define hv_vm_config_set_el2_enabled g_pfnHvVmConfigSetEl2Enabled
292
293# define hv_gic_create g_pfnHvGicCreate
294# define hv_gic_reset g_pfnHvGicReset
295# define hv_gic_config_create g_pfnHvGicConfigCreate
296# define hv_gic_config_set_distributor_base g_pfnHvGicConfigSetDistributorBase
297# define hv_gic_config_set_redistributor_base g_pfnHvGicConfigSetRedistributorBase
298# define hv_gic_config_set_msi_region_base g_pfnHvGicConfigSetMsiRegionBase
299# define hv_gic_config_set_msi_interrupt_range g_pfnHvGicConfigSetMsiInterruptRange
300# define hv_gic_get_redistributor_base g_pfnHvGicGetRedistributorBase
301# define hv_gic_get_redistributor_region_size g_pfnHvGicGetRedistributorRegionSize
302# define hv_gic_get_redistributor_size g_pfnHvGicGetRedistributorSize
303# define hv_gic_get_distributor_size g_pfnHvGicGetDistributorSize
304# define hv_gic_get_distributor_base_alignment g_pfnHvGicGetDistributorBaseAlignment
305# define hv_gic_get_redistributor_base_alignment g_pfnHvGicGetRedistributorBaseAlignment
306# define hv_gic_get_msi_region_base_alignment g_pfnHvGicGetMsiRegionBaseAlignment
307# define hv_gic_get_msi_region_size g_pfnHvGicGetMsiRegionSize
308# define hv_gic_get_spi_interrupt_range g_pfnHvGicGetSpiInterruptRange
309# define hv_gic_state_create g_pfnHvGicStateCreate
310# define hv_gic_set_state g_pfnHvGicSetState
311# define hv_gic_state_get_size g_pfnHvGicStateGetSize
312# define hv_gic_state_get_data g_pfnHvGicStateGetData
313# define hv_gic_send_msi g_pfnHvGicSendMsi
314# define hv_gic_set_spi g_pfnHvGicSetSpi
315# define hv_gic_get_distributor_reg g_pfnHvGicGetDistributorReg
316# define hv_gic_get_msi_reg g_pfnHvGicGetMsiReg
317# define hv_gic_get_icc_reg g_pfnHvGicGetIccReg
318# define hv_gic_get_ich_reg g_pfnHvGicGetIchReg
319# define hv_gic_get_icv_reg g_pfnHvGicGetIcvReg
320# define hv_gic_get_redistributor_reg g_pfnHvGicGetRedistributorReg
321# define hv_gic_set_distributor_reg g_pfnHvGicSetDistributorReg
322# define hv_gic_set_msi_reg g_pfnHvGicSetMsiReg
323# define hv_gic_set_icc_reg g_pfnHvGicSetIccReg
324# define hv_gic_set_ich_reg g_pfnHvGicSetIchReg
325# define hv_gic_set_icv_reg g_pfnHvGicSetIcvReg
326# define hv_gic_set_redistributor_reg g_pfnHvGicSetRedistributorReg
327# define hv_gic_get_intid g_pfnHvGicGetIntid
328#endif
329
330
331/** The general registers. */
332static const struct
333{
334 hv_reg_t enmHvReg;
335 uint32_t fCpumExtrn;
336 uint32_t offCpumCtx;
337} s_aCpumRegs[] =
338{
339#define CPUM_GREG_EMIT_X0_X3(a_Idx) { HV_REG_X ## a_Idx, CPUMCTX_EXTRN_X ## a_Idx, RT_UOFFSETOF(CPUMCTX, aGRegs[a_Idx].x) }
340#define CPUM_GREG_EMIT_X4_X28(a_Idx) { HV_REG_X ## a_Idx, CPUMCTX_EXTRN_X4_X28, RT_UOFFSETOF(CPUMCTX, aGRegs[a_Idx].x) }
341 CPUM_GREG_EMIT_X0_X3(0),
342 CPUM_GREG_EMIT_X0_X3(1),
343 CPUM_GREG_EMIT_X0_X3(2),
344 CPUM_GREG_EMIT_X0_X3(3),
345 CPUM_GREG_EMIT_X4_X28(4),
346 CPUM_GREG_EMIT_X4_X28(5),
347 CPUM_GREG_EMIT_X4_X28(6),
348 CPUM_GREG_EMIT_X4_X28(7),
349 CPUM_GREG_EMIT_X4_X28(8),
350 CPUM_GREG_EMIT_X4_X28(9),
351 CPUM_GREG_EMIT_X4_X28(10),
352 CPUM_GREG_EMIT_X4_X28(11),
353 CPUM_GREG_EMIT_X4_X28(12),
354 CPUM_GREG_EMIT_X4_X28(13),
355 CPUM_GREG_EMIT_X4_X28(14),
356 CPUM_GREG_EMIT_X4_X28(15),
357 CPUM_GREG_EMIT_X4_X28(16),
358 CPUM_GREG_EMIT_X4_X28(17),
359 CPUM_GREG_EMIT_X4_X28(18),
360 CPUM_GREG_EMIT_X4_X28(19),
361 CPUM_GREG_EMIT_X4_X28(20),
362 CPUM_GREG_EMIT_X4_X28(21),
363 CPUM_GREG_EMIT_X4_X28(22),
364 CPUM_GREG_EMIT_X4_X28(23),
365 CPUM_GREG_EMIT_X4_X28(24),
366 CPUM_GREG_EMIT_X4_X28(25),
367 CPUM_GREG_EMIT_X4_X28(26),
368 CPUM_GREG_EMIT_X4_X28(27),
369 CPUM_GREG_EMIT_X4_X28(28),
370 { HV_REG_FP, CPUMCTX_EXTRN_FP, RT_UOFFSETOF(CPUMCTX, aGRegs[29].x) },
371 { HV_REG_LR, CPUMCTX_EXTRN_LR, RT_UOFFSETOF(CPUMCTX, aGRegs[30].x) },
372 { HV_REG_PC, CPUMCTX_EXTRN_PC, RT_UOFFSETOF(CPUMCTX, Pc.u64) },
373 { HV_REG_FPCR, CPUMCTX_EXTRN_FPCR, RT_UOFFSETOF(CPUMCTX, fpcr) },
374 { HV_REG_FPSR, CPUMCTX_EXTRN_FPSR, RT_UOFFSETOF(CPUMCTX, fpsr) }
375#undef CPUM_GREG_EMIT_X0_X3
376#undef CPUM_GREG_EMIT_X4_X28
377};
378/** SIMD/FP registers. */
379static const struct
380{
381 hv_simd_fp_reg_t enmHvReg;
382 uint32_t offCpumCtx;
383} s_aCpumFpRegs[] =
384{
385#define CPUM_VREG_EMIT(a_Idx) { HV_SIMD_FP_REG_Q ## a_Idx, RT_UOFFSETOF(CPUMCTX, aVRegs[a_Idx].v) }
386 CPUM_VREG_EMIT(0),
387 CPUM_VREG_EMIT(1),
388 CPUM_VREG_EMIT(2),
389 CPUM_VREG_EMIT(3),
390 CPUM_VREG_EMIT(4),
391 CPUM_VREG_EMIT(5),
392 CPUM_VREG_EMIT(6),
393 CPUM_VREG_EMIT(7),
394 CPUM_VREG_EMIT(8),
395 CPUM_VREG_EMIT(9),
396 CPUM_VREG_EMIT(10),
397 CPUM_VREG_EMIT(11),
398 CPUM_VREG_EMIT(12),
399 CPUM_VREG_EMIT(13),
400 CPUM_VREG_EMIT(14),
401 CPUM_VREG_EMIT(15),
402 CPUM_VREG_EMIT(16),
403 CPUM_VREG_EMIT(17),
404 CPUM_VREG_EMIT(18),
405 CPUM_VREG_EMIT(19),
406 CPUM_VREG_EMIT(20),
407 CPUM_VREG_EMIT(21),
408 CPUM_VREG_EMIT(22),
409 CPUM_VREG_EMIT(23),
410 CPUM_VREG_EMIT(24),
411 CPUM_VREG_EMIT(25),
412 CPUM_VREG_EMIT(26),
413 CPUM_VREG_EMIT(27),
414 CPUM_VREG_EMIT(28),
415 CPUM_VREG_EMIT(29),
416 CPUM_VREG_EMIT(30),
417 CPUM_VREG_EMIT(31)
418#undef CPUM_VREG_EMIT
419};
420/** Debug system registers. */
421static const struct
422{
423 hv_sys_reg_t enmHvReg;
424 uint32_t offCpumCtx;
425} s_aCpumDbgRegs[] =
426{
427#define CPUM_DBGREG_EMIT(a_BorW, a_Idx) \
428 { HV_SYS_REG_DBG ## a_BorW ## CR ## a_Idx ## _EL1, RT_UOFFSETOF(CPUMCTX, a ## a_BorW ## p[a_Idx].Ctrl.u64) }, \
429 { HV_SYS_REG_DBG ## a_BorW ## VR ## a_Idx ## _EL1, RT_UOFFSETOF(CPUMCTX, a ## a_BorW ## p[a_Idx].Value.u64) }
430 /* Breakpoint registers. */
431 CPUM_DBGREG_EMIT(B, 0),
432 CPUM_DBGREG_EMIT(B, 1),
433 CPUM_DBGREG_EMIT(B, 2),
434 CPUM_DBGREG_EMIT(B, 3),
435 CPUM_DBGREG_EMIT(B, 4),
436 CPUM_DBGREG_EMIT(B, 5),
437 CPUM_DBGREG_EMIT(B, 6),
438 CPUM_DBGREG_EMIT(B, 7),
439 CPUM_DBGREG_EMIT(B, 8),
440 CPUM_DBGREG_EMIT(B, 9),
441 CPUM_DBGREG_EMIT(B, 10),
442 CPUM_DBGREG_EMIT(B, 11),
443 CPUM_DBGREG_EMIT(B, 12),
444 CPUM_DBGREG_EMIT(B, 13),
445 CPUM_DBGREG_EMIT(B, 14),
446 CPUM_DBGREG_EMIT(B, 15),
447 /* Watchpoint registers. */
448 CPUM_DBGREG_EMIT(W, 0),
449 CPUM_DBGREG_EMIT(W, 1),
450 CPUM_DBGREG_EMIT(W, 2),
451 CPUM_DBGREG_EMIT(W, 3),
452 CPUM_DBGREG_EMIT(W, 4),
453 CPUM_DBGREG_EMIT(W, 5),
454 CPUM_DBGREG_EMIT(W, 6),
455 CPUM_DBGREG_EMIT(W, 7),
456 CPUM_DBGREG_EMIT(W, 8),
457 CPUM_DBGREG_EMIT(W, 9),
458 CPUM_DBGREG_EMIT(W, 10),
459 CPUM_DBGREG_EMIT(W, 11),
460 CPUM_DBGREG_EMIT(W, 12),
461 CPUM_DBGREG_EMIT(W, 13),
462 CPUM_DBGREG_EMIT(W, 14),
463 CPUM_DBGREG_EMIT(W, 15),
464 { HV_SYS_REG_MDSCR_EL1, RT_UOFFSETOF(CPUMCTX, Mdscr.u64) }
465#undef CPUM_DBGREG_EMIT
466};
467/** PAuth key system registers. */
468static const struct
469{
470 hv_sys_reg_t enmHvReg;
471 uint32_t offCpumCtx;
472} s_aCpumPAuthKeyRegs[] =
473{
474 { HV_SYS_REG_APDAKEYLO_EL1, RT_UOFFSETOF(CPUMCTX, Apda.Low.u64) },
475 { HV_SYS_REG_APDAKEYHI_EL1, RT_UOFFSETOF(CPUMCTX, Apda.High.u64) },
476 { HV_SYS_REG_APDBKEYLO_EL1, RT_UOFFSETOF(CPUMCTX, Apdb.Low.u64) },
477 { HV_SYS_REG_APDBKEYHI_EL1, RT_UOFFSETOF(CPUMCTX, Apdb.High.u64) },
478 { HV_SYS_REG_APGAKEYLO_EL1, RT_UOFFSETOF(CPUMCTX, Apga.Low.u64) },
479 { HV_SYS_REG_APGAKEYHI_EL1, RT_UOFFSETOF(CPUMCTX, Apga.High.u64) },
480 { HV_SYS_REG_APIAKEYLO_EL1, RT_UOFFSETOF(CPUMCTX, Apia.Low.u64) },
481 { HV_SYS_REG_APIAKEYHI_EL1, RT_UOFFSETOF(CPUMCTX, Apia.High.u64) },
482 { HV_SYS_REG_APIBKEYLO_EL1, RT_UOFFSETOF(CPUMCTX, Apib.Low.u64) },
483 { HV_SYS_REG_APIBKEYHI_EL1, RT_UOFFSETOF(CPUMCTX, Apib.High.u64) }
484};
485/** System registers. */
486static const struct
487{
488 hv_sys_reg_t enmHvReg;
489 uint32_t fCpumExtrn;
490 uint32_t offCpumCtx;
491} s_aCpumSysRegs[] =
492{
493 { HV_SYS_REG_SP_EL0, CPUMCTX_EXTRN_SP, RT_UOFFSETOF(CPUMCTX, aSpReg[0].u64) },
494 { HV_SYS_REG_SP_EL1, CPUMCTX_EXTRN_SP, RT_UOFFSETOF(CPUMCTX, aSpReg[1].u64) },
495 { HV_SYS_REG_SPSR_EL1, CPUMCTX_EXTRN_SPSR, RT_UOFFSETOF(CPUMCTX, Spsr.u64) },
496 { HV_SYS_REG_ELR_EL1, CPUMCTX_EXTRN_ELR, RT_UOFFSETOF(CPUMCTX, Elr.u64) },
497 { HV_SYS_REG_SCTLR_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR, RT_UOFFSETOF(CPUMCTX, Sctlr.u64) },
498 { HV_SYS_REG_TCR_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR, RT_UOFFSETOF(CPUMCTX, Tcr.u64) },
499 { HV_SYS_REG_TTBR0_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR, RT_UOFFSETOF(CPUMCTX, Ttbr0.u64) },
500 { HV_SYS_REG_TTBR1_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR, RT_UOFFSETOF(CPUMCTX, Ttbr1.u64) },
501 { HV_SYS_REG_VBAR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, VBar.u64) },
502 { HV_SYS_REG_AFSR0_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Afsr0.u64) },
503 { HV_SYS_REG_AFSR1_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Afsr1.u64) },
504 { HV_SYS_REG_AMAIR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Amair.u64) },
505 { HV_SYS_REG_CNTKCTL_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, CntKCtl.u64) },
506 { HV_SYS_REG_CONTEXTIDR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, ContextIdr.u64) },
507 { HV_SYS_REG_CPACR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Cpacr.u64) },
508 { HV_SYS_REG_CSSELR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Csselr.u64) },
509 { HV_SYS_REG_ESR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Esr.u64) },
510 { HV_SYS_REG_FAR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Far.u64) },
511 { HV_SYS_REG_MAIR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Mair.u64) },
512 { HV_SYS_REG_PAR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Par.u64) },
513 { HV_SYS_REG_TPIDRRO_EL0, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, TpIdrRoEl0.u64) },
514 { HV_SYS_REG_TPIDR_EL0, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, aTpIdr[0].u64) },
515 { HV_SYS_REG_TPIDR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, aTpIdr[1].u64) },
516 { HV_SYS_REG_MDCCINT_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, MDccInt.u64) }
517
518};
519/** EL2 support system registers. */
520static const struct
521{
522 uint16_t idSysReg;
523 uint32_t offCpumCtx;
524} s_aCpumEl2SysRegs[] =
525{
526 { ARMV8_AARCH64_SYSREG_CNTHCTL_EL2, RT_UOFFSETOF(CPUMCTX, CntHCtlEl2.u64) },
527 { ARMV8_AARCH64_SYSREG_CNTHP_CTL_EL2, RT_UOFFSETOF(CPUMCTX, CntHpCtlEl2.u64) },
528 { ARMV8_AARCH64_SYSREG_CNTHP_CVAL_EL2, RT_UOFFSETOF(CPUMCTX, CntHpCValEl2.u64) },
529 { ARMV8_AARCH64_SYSREG_CNTHP_TVAL_EL2, RT_UOFFSETOF(CPUMCTX, CntHpTValEl2.u64) },
530 { ARMV8_AARCH64_SYSREG_CNTVOFF_EL2, RT_UOFFSETOF(CPUMCTX, CntVOffEl2.u64) },
531 { ARMV8_AARCH64_SYSREG_CPTR_EL2, RT_UOFFSETOF(CPUMCTX, CptrEl2.u64) },
532 { ARMV8_AARCH64_SYSREG_ELR_EL2, RT_UOFFSETOF(CPUMCTX, ElrEl2.u64) },
533 { ARMV8_AARCH64_SYSREG_ESR_EL2, RT_UOFFSETOF(CPUMCTX, EsrEl2.u64) },
534 { ARMV8_AARCH64_SYSREG_FAR_EL2, RT_UOFFSETOF(CPUMCTX, FarEl2.u64) },
535 { ARMV8_AARCH64_SYSREG_HCR_EL2, RT_UOFFSETOF(CPUMCTX, HcrEl2.u64) },
536 { ARMV8_AARCH64_SYSREG_HPFAR_EL2, RT_UOFFSETOF(CPUMCTX, HpFarEl2.u64) },
537 { ARMV8_AARCH64_SYSREG_MAIR_EL2, RT_UOFFSETOF(CPUMCTX, MairEl2.u64) },
538 //{ ARMV8_AARCH64_SYSREG_MDCR_EL2, RT_UOFFSETOF(CPUMCTX, MdcrEl2.u64) },
539 { ARMV8_AARCH64_SYSREG_SCTLR_EL2, RT_UOFFSETOF(CPUMCTX, SctlrEl2.u64) },
540 { ARMV8_AARCH64_SYSREG_SPSR_EL2, RT_UOFFSETOF(CPUMCTX, SpsrEl2.u64) },
541 { ARMV8_AARCH64_SYSREG_SP_EL2, RT_UOFFSETOF(CPUMCTX, SpEl2.u64) },
542 { ARMV8_AARCH64_SYSREG_TCR_EL2, RT_UOFFSETOF(CPUMCTX, TcrEl2.u64) },
543 { ARMV8_AARCH64_SYSREG_TPIDR_EL2, RT_UOFFSETOF(CPUMCTX, TpidrEl2.u64) },
544 { ARMV8_AARCH64_SYSREG_TTBR0_EL2, RT_UOFFSETOF(CPUMCTX, Ttbr0El2.u64) },
545 { ARMV8_AARCH64_SYSREG_TTBR1_EL2, RT_UOFFSETOF(CPUMCTX, Ttbr1El2.u64) },
546 { ARMV8_AARCH64_SYSREG_VBAR_EL2, RT_UOFFSETOF(CPUMCTX, VBarEl2.u64) },
547 { ARMV8_AARCH64_SYSREG_VMPIDR_EL2, RT_UOFFSETOF(CPUMCTX, VMpidrEl2.u64) },
548 { ARMV8_AARCH64_SYSREG_VPIDR_EL2, RT_UOFFSETOF(CPUMCTX, VPidrEl2.u64) },
549 { ARMV8_AARCH64_SYSREG_VTCR_EL2, RT_UOFFSETOF(CPUMCTX, VTcrEl2.u64) },
550 { ARMV8_AARCH64_SYSREG_VTTBR_EL2, RT_UOFFSETOF(CPUMCTX, VTtbrEl2.u64) }
551};
552/** ID registers. */
553static const struct
554{
555 hv_feature_reg_t enmHvReg;
556 uint32_t offIdStruct;
557} s_aIdRegs[] =
558{
559 { HV_FEATURE_REG_ID_AA64DFR0_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Dfr0El1) },
560 { HV_FEATURE_REG_ID_AA64DFR1_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Dfr1El1) },
561 { HV_FEATURE_REG_ID_AA64ISAR0_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Isar0El1) },
562 { HV_FEATURE_REG_ID_AA64ISAR1_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Isar1El1) },
563 { HV_FEATURE_REG_ID_AA64MMFR0_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Mmfr0El1) },
564 { HV_FEATURE_REG_ID_AA64MMFR1_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Mmfr1El1) },
565 { HV_FEATURE_REG_ID_AA64MMFR2_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Mmfr2El1) },
566 { HV_FEATURE_REG_ID_AA64PFR0_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Pfr0El1) },
567 { HV_FEATURE_REG_ID_AA64PFR1_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Pfr1El1) },
568 { HV_FEATURE_REG_CLIDR_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegClidrEl1) },
569 { HV_FEATURE_REG_CTR_EL0, RT_UOFFSETOF(CPUMIDREGS, u64RegCtrEl0) },
570 { HV_FEATURE_REG_DCZID_EL0, RT_UOFFSETOF(CPUMIDREGS, u64RegDczidEl0) }
571};
572
573
574/*********************************************************************************************************************************
575* Internal Functions *
576*********************************************************************************************************************************/
577
578
579/**
580 * Converts a HV return code to a VBox status code.
581 *
582 * @returns VBox status code.
583 * @param hrc The HV return code to convert.
584 */
585DECLINLINE(int) nemR3DarwinHvSts2Rc(hv_return_t hrc)
586{
587 if (hrc == HV_SUCCESS)
588 return VINF_SUCCESS;
589
590 switch (hrc)
591 {
592 case HV_ERROR: return VERR_INVALID_STATE;
593 case HV_BUSY: return VERR_RESOURCE_BUSY;
594 case HV_BAD_ARGUMENT: return VERR_INVALID_PARAMETER;
595 case HV_NO_RESOURCES: return VERR_OUT_OF_RESOURCES;
596 case HV_NO_DEVICE: return VERR_NOT_FOUND;
597 case HV_UNSUPPORTED: return VERR_NOT_SUPPORTED;
598 }
599
600 return VERR_IPE_UNEXPECTED_STATUS;
601}
602
603
604/**
605 * Returns a human readable string of the given exception class.
606 *
607 * @returns Pointer to the string matching the given EC.
608 * @param u32Ec The exception class to return the string for.
609 */
610static const char *nemR3DarwinEsrEl2EcStringify(uint32_t u32Ec)
611{
612 switch (u32Ec)
613 {
614#define ARMV8_EC_CASE(a_Ec) case a_Ec: return #a_Ec
615 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_UNKNOWN);
616 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_TRAPPED_WFX);
617 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_15);
618 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCRR_MRRC_COPROC15);
619 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_14);
620 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_LDC_STC);
621 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_SME_SVE_NEON);
622 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_VMRS);
623 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_PA_INSN);
624 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_LS64_EXCEPTION);
625 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MRRC_COPROC14);
626 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_BTI_BRANCH_TARGET_EXCEPTION);
627 ARMV8_EC_CASE(ARMV8_ESR_EL2_ILLEGAL_EXECUTION_STATE);
628 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_SVC_INSN);
629 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_HVC_INSN);
630 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_SMC_INSN);
631 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_SVC_INSN);
632 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_HVC_INSN);
633 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_SMC_INSN);
634 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_SYS_INSN);
635 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_SVE_TRAPPED);
636 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_PAUTH_NV_TRAPPED_ERET_ERETAA_ERETAB);
637 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_TME_TSTART_INSN_EXCEPTION);
638 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_FPAC_PA_INSN_FAILURE_EXCEPTION);
639 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_SME_TRAPPED_SME_ACCESS);
640 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_RME_GRANULE_PROT_CHECK_EXCEPTION);
641 ARMV8_EC_CASE(ARMV8_ESR_EL2_INSN_ABORT_FROM_LOWER_EL);
642 ARMV8_EC_CASE(ARMV8_ESR_EL2_INSN_ABORT_FROM_EL2);
643 ARMV8_EC_CASE(ARMV8_ESR_EL2_PC_ALIGNMENT_EXCEPTION);
644 ARMV8_EC_CASE(ARMV8_ESR_EL2_DATA_ABORT_FROM_LOWER_EL);
645 ARMV8_EC_CASE(ARMV8_ESR_EL2_DATA_ABORT_FROM_EL2);
646 ARMV8_EC_CASE(ARMV8_ESR_EL2_SP_ALIGNMENT_EXCEPTION);
647 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_MOPS_EXCEPTION);
648 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_FP_EXCEPTION);
649 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_FP_EXCEPTION);
650 ARMV8_EC_CASE(ARMV8_ESR_EL2_SERROR_INTERRUPT);
651 ARMV8_EC_CASE(ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_LOWER_EL);
652 ARMV8_EC_CASE(ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_EL2);
653 ARMV8_EC_CASE(ARMV8_ESR_EL2_SS_EXCEPTION_FROM_LOWER_EL);
654 ARMV8_EC_CASE(ARMV8_ESR_EL2_SS_EXCEPTION_FROM_EL2);
655 ARMV8_EC_CASE(ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_LOWER_EL);
656 ARMV8_EC_CASE(ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_EL2);
657 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_BKPT_INSN);
658 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_VEC_CATCH_EXCEPTION);
659 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_BRK_INSN);
660#undef ARMV8_EC_CASE
661 default:
662 break;
663 }
664
665 return "<INVALID>";
666}
667
668
669/**
670 * Resolves a NEM page state from the given protection flags.
671 *
672 * @returns NEM page state.
673 * @param fPageProt The page protection flags.
674 */
675DECLINLINE(uint8_t) nemR3DarwinPageStateFromProt(uint32_t fPageProt)
676{
677 switch (fPageProt)
678 {
679 case NEM_PAGE_PROT_NONE:
680 return NEM_DARWIN_PAGE_STATE_UNMAPPED;
681 case NEM_PAGE_PROT_READ | NEM_PAGE_PROT_EXECUTE:
682 return NEM_DARWIN_PAGE_STATE_RX;
683 case NEM_PAGE_PROT_READ | NEM_PAGE_PROT_WRITE:
684 return NEM_DARWIN_PAGE_STATE_RW;
685 case NEM_PAGE_PROT_READ | NEM_PAGE_PROT_WRITE | NEM_PAGE_PROT_EXECUTE:
686 return NEM_DARWIN_PAGE_STATE_RWX;
687 default:
688 break;
689 }
690
691 AssertLogRelMsgFailed(("Invalid combination of page protection flags %#x, can't map to page state!\n", fPageProt));
692 return NEM_DARWIN_PAGE_STATE_UNMAPPED;
693}
694
695
696/**
697 * Unmaps the given guest physical address range (page aligned).
698 *
699 * @returns VBox status code.
700 * @param pVM The cross context VM structure.
701 * @param GCPhys The guest physical address to start unmapping at.
702 * @param cb The size of the range to unmap in bytes.
703 * @param pu2State Where to store the new state of the unmappd page, optional.
704 */
705DECLINLINE(int) nemR3DarwinUnmap(PVM pVM, RTGCPHYS GCPhys, size_t cb, uint8_t *pu2State)
706{
707 if (*pu2State <= NEM_DARWIN_PAGE_STATE_UNMAPPED)
708 {
709 Log5(("nemR3DarwinUnmap: %RGp == unmapped\n", GCPhys));
710 *pu2State = NEM_DARWIN_PAGE_STATE_UNMAPPED;
711 return VINF_SUCCESS;
712 }
713
714 LogFlowFunc(("Unmapping %RGp LB %zu\n", GCPhys, cb));
715 hv_return_t hrc = hv_vm_unmap(GCPhys, cb);
716 if (RT_LIKELY(hrc == HV_SUCCESS))
717 {
718 STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPage);
719 if (pu2State)
720 *pu2State = NEM_DARWIN_PAGE_STATE_UNMAPPED;
721 Log5(("nemR3DarwinUnmap: %RGp => unmapped\n", GCPhys));
722 return VINF_SUCCESS;
723 }
724
725 STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPageFailed);
726 LogRel(("nemR3DarwinUnmap(%RGp): failed! hrc=%#x\n",
727 GCPhys, hrc));
728 return VERR_NEM_IPE_6;
729}
730
731
732/**
733 * Maps a given guest physical address range backed by the given memory with the given
734 * protection flags.
735 *
736 * @returns VBox status code.
737 * @param pVM The cross context VM structure.
738 * @param GCPhys The guest physical address to start mapping.
739 * @param pvRam The R3 pointer of the memory to back the range with.
740 * @param cb The size of the range, page aligned.
741 * @param fPageProt The page protection flags to use for this range, combination of NEM_PAGE_PROT_XXX
742 * @param pu2State Where to store the state for the new page, optional.
743 */
744DECLINLINE(int) nemR3DarwinMap(PVM pVM, RTGCPHYS GCPhys, const void *pvRam, size_t cb, uint32_t fPageProt, uint8_t *pu2State)
745{
746 LogFlowFunc(("Mapping %RGp LB %zu fProt=%#x\n", GCPhys, cb, fPageProt));
747
748 Assert(fPageProt != NEM_PAGE_PROT_NONE);
749 RT_NOREF(pVM);
750
751 hv_memory_flags_t fHvMemProt = 0;
752 if (fPageProt & NEM_PAGE_PROT_READ)
753 fHvMemProt |= HV_MEMORY_READ;
754 if (fPageProt & NEM_PAGE_PROT_WRITE)
755 fHvMemProt |= HV_MEMORY_WRITE;
756 if (fPageProt & NEM_PAGE_PROT_EXECUTE)
757 fHvMemProt |= HV_MEMORY_EXEC;
758
759 hv_return_t hrc = hv_vm_map((void *)pvRam, GCPhys, cb, fHvMemProt);
760 if (hrc == HV_SUCCESS)
761 {
762 if (pu2State)
763 *pu2State = nemR3DarwinPageStateFromProt(fPageProt);
764 return VINF_SUCCESS;
765 }
766
767 return nemR3DarwinHvSts2Rc(hrc);
768}
769
770
771/**
772 * Changes the protection flags for the given guest physical address range.
773 *
774 * @returns VBox status code.
775 * @param GCPhys The guest physical address to start mapping.
776 * @param cb The size of the range, page aligned.
777 * @param fPageProt The page protection flags to use for this range, combination of NEM_PAGE_PROT_XXX
778 * @param pu2State Where to store the state for the new page, optional.
779 */
780DECLINLINE(int) nemR3DarwinProtect(RTGCPHYS GCPhys, size_t cb, uint32_t fPageProt, uint8_t *pu2State)
781{
782 hv_memory_flags_t fHvMemProt = 0;
783 if (fPageProt & NEM_PAGE_PROT_READ)
784 fHvMemProt |= HV_MEMORY_READ;
785 if (fPageProt & NEM_PAGE_PROT_WRITE)
786 fHvMemProt |= HV_MEMORY_WRITE;
787 if (fPageProt & NEM_PAGE_PROT_EXECUTE)
788 fHvMemProt |= HV_MEMORY_EXEC;
789
790 hv_return_t hrc = hv_vm_protect(GCPhys, cb, fHvMemProt);
791 if (hrc == HV_SUCCESS)
792 {
793 if (pu2State)
794 *pu2State = nemR3DarwinPageStateFromProt(fPageProt);
795 return VINF_SUCCESS;
796 }
797
798 LogRel(("nemR3DarwinProtect(%RGp,%zu,%#x): failed! hrc=%#x\n",
799 GCPhys, cb, fPageProt, hrc));
800 return nemR3DarwinHvSts2Rc(hrc);
801}
802
803
804#ifdef LOG_ENABLED
805/**
806 * Logs the current CPU state.
807 */
808static void nemR3DarwinLogState(PVMCC pVM, PVMCPUCC pVCpu)
809{
810 if (LogIs3Enabled())
811 {
812 char szRegs[4096];
813 DBGFR3RegPrintf(pVM->pUVM, pVCpu->idCpu, &szRegs[0], sizeof(szRegs),
814 "x0=%016VR{x0} x1=%016VR{x1} x2=%016VR{x2} x3=%016VR{x3}\n"
815 "x4=%016VR{x4} x5=%016VR{x5} x6=%016VR{x6} x7=%016VR{x7}\n"
816 "x8=%016VR{x8} x9=%016VR{x9} x10=%016VR{x10} x11=%016VR{x11}\n"
817 "x12=%016VR{x12} x13=%016VR{x13} x14=%016VR{x14} x15=%016VR{x15}\n"
818 "x16=%016VR{x16} x17=%016VR{x17} x18=%016VR{x18} x19=%016VR{x19}\n"
819 "x20=%016VR{x20} x21=%016VR{x21} x22=%016VR{x22} x23=%016VR{x23}\n"
820 "x24=%016VR{x24} x25=%016VR{x25} x26=%016VR{x26} x27=%016VR{x27}\n"
821 "x28=%016VR{x28} x29=%016VR{x29} x30=%016VR{x30}\n"
822 "pc=%016VR{pc} pstate=%016VR{pstate}\n"
823 "sp_el0=%016VR{sp_el0} sp_el1=%016VR{sp_el1} elr_el1=%016VR{elr_el1}\n"
824 "sctlr_el1=%016VR{sctlr_el1} tcr_el1=%016VR{tcr_el1}\n"
825 "ttbr0_el1=%016VR{ttbr0_el1} ttbr1_el1=%016VR{ttbr1_el1}\n"
826 "vbar_el1=%016VR{vbar_el1}\n"
827 );
828 char szInstr[256]; RT_ZERO(szInstr);
829#if 0
830 DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, 0, 0,
831 DBGF_DISAS_FLAGS_CURRENT_GUEST | DBGF_DISAS_FLAGS_DEFAULT_MODE,
832 szInstr, sizeof(szInstr), NULL);
833#endif
834 Log3(("%s%s\n", szRegs, szInstr));
835
836 if (pVM->nem.s.fEl2Enabled)
837 {
838 DBGFR3RegPrintf(pVM->pUVM, pVCpu->idCpu, &szRegs[0], sizeof(szRegs),
839 "sp_el2=%016VR{sp_el2} elr_el2=%016VR{elr_el2}\n"
840 "spsr_el2=%016VR{spsr_el2} tpidr_el2=%016VR{tpidr_el2}\n"
841 "sctlr_el2=%016VR{sctlr_el2} tcr_el2=%016VR{tcr_el2}\n"
842 "ttbr0_el2=%016VR{ttbr0_el2} ttbr1_el2=%016VR{ttbr1_el2}\n"
843 "esr_el2=%016VR{esr_el2} far_el2=%016VR{far_el2}\n"
844 "hcr_el2=%016VR{hcr_el2} tcr_el2=%016VR{tcr_el2}\n"
845 "vbar_el2=%016VR{vbar_el2} cptr_el2=%016VR{cptr_el2}\n"
846 );
847 }
848 Log3(("%s%s\n", szRegs));
849 }
850}
851#endif /* LOG_ENABLED */
852
853
854static int nemR3DarwinCopyStateFromHv(PVMCC pVM, PVMCPUCC pVCpu, uint64_t fWhat)
855{
856 RT_NOREF(pVM);
857
858 hv_return_t hrc = hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CTL_EL0, &pVCpu->cpum.GstCtx.CntvCtlEl0);
859 if (hrc == HV_SUCCESS)
860 hrc = hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CVAL_EL0, &pVCpu->cpum.GstCtx.CntvCValEl0);
861
862 if ( hrc == HV_SUCCESS
863 && (fWhat & (CPUMCTX_EXTRN_GPRS_MASK | CPUMCTX_EXTRN_PC | CPUMCTX_EXTRN_FPCR | CPUMCTX_EXTRN_FPSR)))
864 {
865 for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumRegs); i++)
866 {
867 if (s_aCpumRegs[i].fCpumExtrn & fWhat)
868 {
869 uint64_t *pu64 = (uint64_t *)((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumRegs[i].offCpumCtx);
870 hrc |= hv_vcpu_get_reg(pVCpu->nem.s.hVCpu, s_aCpumRegs[i].enmHvReg, pu64);
871 }
872 }
873 }
874
875 if ( hrc == HV_SUCCESS
876 && (fWhat & CPUMCTX_EXTRN_V0_V31))
877 {
878 /* SIMD/FP registers. */
879 for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumFpRegs); i++)
880 {
881 hv_simd_fp_uchar16_t *pu128 = (hv_simd_fp_uchar16_t *)((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumFpRegs[i].offCpumCtx);
882 hrc |= hv_vcpu_get_simd_fp_reg(pVCpu->nem.s.hVCpu, s_aCpumFpRegs[i].enmHvReg, pu128);
883 }
884 }
885
886 if ( hrc == HV_SUCCESS
887 && (fWhat & CPUMCTX_EXTRN_SYSREG_DEBUG))
888 {
889 /* Debug registers. */
890 for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumDbgRegs); i++)
891 {
892 uint64_t *pu64 = (uint64_t *)((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumDbgRegs[i].offCpumCtx);
893 hrc |= hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumDbgRegs[i].enmHvReg, pu64);
894 }
895 }
896
897 if ( hrc == HV_SUCCESS
898 && (fWhat & CPUMCTX_EXTRN_SYSREG_PAUTH_KEYS))
899 {
900 /* Debug registers. */
901 for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumPAuthKeyRegs); i++)
902 {
903 uint64_t *pu64 = (uint64_t *)((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumPAuthKeyRegs[i].offCpumCtx);
904 hrc |= hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumPAuthKeyRegs[i].enmHvReg, pu64);
905 }
906 }
907
908 if ( hrc == HV_SUCCESS
909 && (fWhat & (CPUMCTX_EXTRN_SPSR | CPUMCTX_EXTRN_ELR | CPUMCTX_EXTRN_SP | CPUMCTX_EXTRN_SCTLR_TCR_TTBR | CPUMCTX_EXTRN_SYSREG_MISC)))
910 {
911 /* System registers. */
912 for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumSysRegs); i++)
913 {
914 if (s_aCpumSysRegs[i].fCpumExtrn & fWhat)
915 {
916 uint64_t *pu64 = (uint64_t *)((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumSysRegs[i].offCpumCtx);
917 hrc |= hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumSysRegs[i].enmHvReg, pu64);
918 }
919 }
920 }
921
922 if ( hrc == HV_SUCCESS
923 && (fWhat & CPUMCTX_EXTRN_SYSREG_EL2)
924 && pVM->nem.s.fEl2Enabled)
925 {
926 for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumEl2SysRegs); i++)
927 {
928 uint64_t *pu64 = (uint64_t *)((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumEl2SysRegs[i].offCpumCtx);
929 hrc |= hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, (hv_sys_reg_t)s_aCpumEl2SysRegs[i].idSysReg, pu64);
930 }
931 }
932
933 if ( hrc == HV_SUCCESS
934 && (fWhat & CPUMCTX_EXTRN_PSTATE))
935 {
936 uint64_t u64Tmp;
937 hrc |= hv_vcpu_get_reg(pVCpu->nem.s.hVCpu, HV_REG_CPSR, &u64Tmp);
938 if (hrc == HV_SUCCESS)
939 pVCpu->cpum.GstCtx.fPState = (uint32_t)u64Tmp;
940 }
941
942 /* Almost done, just update extern flags. */
943 pVCpu->cpum.GstCtx.fExtrn &= ~fWhat;
944 if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL))
945 pVCpu->cpum.GstCtx.fExtrn = 0;
946
947 return nemR3DarwinHvSts2Rc(hrc);
948}
949
950
951/**
952 * Exports the guest state to HV for execution.
953 *
954 * @returns VBox status code.
955 * @param pVM The cross context VM structure.
956 * @param pVCpu The cross context virtual CPU structure of the
957 * calling EMT.
958 */
959static int nemR3DarwinExportGuestState(PVMCC pVM, PVMCPUCC pVCpu)
960{
961 RT_NOREF(pVM);
962 hv_return_t hrc = HV_SUCCESS;
963
964 if ( (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_GPRS_MASK | CPUMCTX_EXTRN_PC | CPUMCTX_EXTRN_FPCR | CPUMCTX_EXTRN_FPSR))
965 != (CPUMCTX_EXTRN_GPRS_MASK | CPUMCTX_EXTRN_PC | CPUMCTX_EXTRN_FPCR | CPUMCTX_EXTRN_FPSR))
966 {
967 for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumRegs); i++)
968 {
969 if (!(s_aCpumRegs[i].fCpumExtrn & pVCpu->cpum.GstCtx.fExtrn))
970 {
971 uint64_t *pu64 = (uint64_t *)((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumRegs[i].offCpumCtx);
972 hrc |= hv_vcpu_set_reg(pVCpu->nem.s.hVCpu, s_aCpumRegs[i].enmHvReg, *pu64);
973 }
974 }
975 }
976
977 if ( hrc == HV_SUCCESS
978 && !(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_V0_V31))
979 {
980 /* SIMD/FP registers. */
981 for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumFpRegs); i++)
982 {
983 hv_simd_fp_uchar16_t *pu128 = (hv_simd_fp_uchar16_t *)((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumFpRegs[i].offCpumCtx);
984 hrc |= hv_vcpu_set_simd_fp_reg(pVCpu->nem.s.hVCpu, s_aCpumFpRegs[i].enmHvReg, *pu128);
985 }
986 }
987
988 if ( hrc == HV_SUCCESS
989 && !(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_SYSREG_DEBUG))
990 {
991 /* Debug registers. */
992 for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumDbgRegs); i++)
993 {
994 uint64_t *pu64 = (uint64_t *)((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumDbgRegs[i].offCpumCtx);
995 hrc |= hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumDbgRegs[i].enmHvReg, *pu64);
996 }
997 }
998
999 if ( hrc == HV_SUCCESS
1000 && !(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_SYSREG_PAUTH_KEYS))
1001 {
1002 /* Debug registers. */
1003 for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumPAuthKeyRegs); i++)
1004 {
1005 uint64_t *pu64 = (uint64_t *)((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumPAuthKeyRegs[i].offCpumCtx);
1006 hrc |= hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumPAuthKeyRegs[i].enmHvReg, *pu64);
1007 }
1008 }
1009
1010 if ( hrc == HV_SUCCESS
1011 && (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_SPSR | CPUMCTX_EXTRN_ELR | CPUMCTX_EXTRN_SP | CPUMCTX_EXTRN_SCTLR_TCR_TTBR | CPUMCTX_EXTRN_SYSREG_MISC))
1012 != (CPUMCTX_EXTRN_SPSR | CPUMCTX_EXTRN_ELR | CPUMCTX_EXTRN_SP | CPUMCTX_EXTRN_SCTLR_TCR_TTBR | CPUMCTX_EXTRN_SYSREG_MISC))
1013 {
1014 /* System registers. */
1015 for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumSysRegs); i++)
1016 {
1017 if (!(s_aCpumSysRegs[i].fCpumExtrn & pVCpu->cpum.GstCtx.fExtrn))
1018 {
1019 uint64_t *pu64 = (uint64_t *)((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumSysRegs[i].offCpumCtx);
1020 hrc |= hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumSysRegs[i].enmHvReg, *pu64);
1021 }
1022 }
1023 }
1024
1025 if ( hrc == HV_SUCCESS
1026 && !(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_SYSREG_EL2)
1027 && pVM->nem.s.fEl2Enabled)
1028 {
1029 for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumEl2SysRegs); i++)
1030 {
1031 uint64_t *pu64 = (uint64_t *)((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumEl2SysRegs[i].offCpumCtx);
1032 hrc |= hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, (hv_sys_reg_t)s_aCpumEl2SysRegs[i].idSysReg, *pu64);
1033 Assert(hrc == HV_SUCCESS);
1034 }
1035 }
1036
1037 if ( hrc == HV_SUCCESS
1038 && !(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_PSTATE))
1039 hrc = hv_vcpu_set_reg(pVCpu->nem.s.hVCpu, HV_REG_CPSR, pVCpu->cpum.GstCtx.fPState);
1040
1041 pVCpu->cpum.GstCtx.fExtrn |= CPUMCTX_EXTRN_ALL | CPUMCTX_EXTRN_KEEPER_NEM;
1042 return nemR3DarwinHvSts2Rc(hrc);
1043}
1044
1045
1046/**
1047 * Worker for nemR3NativeInit that loads the Hypervisor.framework shared library.
1048 *
1049 * @returns VBox status code.
1050 * @param pErrInfo Where to always return error info.
1051 */
1052static int nemR3DarwinLoadHv(PRTERRINFO pErrInfo)
1053{
1054 RTLDRMOD hMod = NIL_RTLDRMOD;
1055 static const char *s_pszHvPath = "/System/Library/Frameworks/Hypervisor.framework/Hypervisor";
1056
1057 int rc = RTLdrLoadEx(s_pszHvPath, &hMod, RTLDRLOAD_FLAGS_NO_UNLOAD | RTLDRLOAD_FLAGS_NO_SUFFIX, pErrInfo);
1058 if (RT_SUCCESS(rc))
1059 {
1060 for (unsigned i = 0; i < RT_ELEMENTS(g_aImports); i++)
1061 {
1062 int rc2 = RTLdrGetSymbol(hMod, g_aImports[i].pszName, (void **)g_aImports[i].ppfn);
1063 if (RT_SUCCESS(rc2))
1064 {
1065 LogRel(("NEM: info: Found optional import Hypervisor!%s.\n",
1066 g_aImports[i].pszName));
1067 }
1068 else
1069 {
1070 *g_aImports[i].ppfn = NULL;
1071
1072 LogRel(("NEM: info: Failed to import Hypervisor!%s: %Rrc\n",
1073 g_aImports[i].pszName, rc2));
1074 }
1075 }
1076 if (RT_SUCCESS(rc))
1077 {
1078 Assert(!RTErrInfoIsSet(pErrInfo));
1079 }
1080
1081 RTLdrClose(hMod);
1082 }
1083 else
1084 {
1085 RTErrInfoAddF(pErrInfo, rc, "Failed to load Hypervisor.framwork: %s: %Rrc", s_pszHvPath, rc);
1086 rc = VERR_NEM_INIT_FAILED;
1087 }
1088
1089 return rc;
1090}
1091
1092
1093/**
1094 * Dumps some GIC information to the release log.
1095 */
1096static void nemR3DarwinDumpGicInfo(void)
1097{
1098 size_t val = 0;
1099 hv_return_t hrc = hv_gic_get_redistributor_size(&val);
1100 LogRel(("GICNem: hv_gic_get_redistributor_size() -> hrc=%#x / size=%zu\n", hrc, val));
1101 hrc = hv_gic_get_distributor_size(&val);
1102 LogRel(("GICNem: hv_gic_get_distributor_size() -> hrc=%#x / size=%zu\n", hrc, val));
1103 hrc = hv_gic_get_distributor_base_alignment(&val);
1104 LogRel(("GICNem: hv_gic_get_distributor_base_alignment() -> hrc=%#x / size=%zu\n", hrc, val));
1105 hrc = hv_gic_get_redistributor_base_alignment(&val);
1106 LogRel(("GICNem: hv_gic_get_redistributor_base_alignment() -> hrc=%#x / size=%zu\n", hrc, val));
1107 hrc = hv_gic_get_msi_region_base_alignment(&val);
1108 LogRel(("GICNem: hv_gic_get_msi_region_base_alignment() -> hrc=%#x / size=%zu\n", hrc, val));
1109 hrc = hv_gic_get_msi_region_size(&val);
1110 LogRel(("GICNem: hv_gic_get_msi_region_size() -> hrc=%#x / size=%zu\n", hrc, val));
1111 uint32_t u32SpiIntIdBase = 0;
1112 uint32_t cSpiIntIds = 0;
1113 hrc = hv_gic_get_spi_interrupt_range(&u32SpiIntIdBase, &cSpiIntIds);
1114 LogRel(("GICNem: hv_gic_get_spi_interrupt_range() -> hrc=%#x / SpiIntIdBase=%u, cSpiIntIds=%u\n", hrc, u32SpiIntIdBase, cSpiIntIds));
1115
1116 uint32_t u32IntId = 0;
1117 hrc = hv_gic_get_intid(HV_GIC_INT_EL1_PHYSICAL_TIMER, &u32IntId);
1118 LogRel(("GICNem: hv_gic_get_intid(HV_GIC_INT_EL1_PHYSICAL_TIMER) -> hrc=%#x / IntId=%u\n", hrc, u32IntId));
1119 hrc = hv_gic_get_intid(HV_GIC_INT_EL1_VIRTUAL_TIMER, &u32IntId);
1120 LogRel(("GICNem: hv_gic_get_intid(HV_GIC_INT_EL1_VIRTUAL_TIMER) -> hrc=%#x / IntId=%u\n", hrc, u32IntId));
1121 hrc = hv_gic_get_intid(HV_GIC_INT_EL2_PHYSICAL_TIMER, &u32IntId);
1122 LogRel(("GICNem: hv_gic_get_intid(HV_GIC_INT_EL2_PHYSICAL_TIMER) -> hrc=%#x / IntId=%u\n", hrc, u32IntId));
1123 hrc = hv_gic_get_intid(HV_GIC_INT_MAINTENANCE, &u32IntId);
1124 LogRel(("GICNem: hv_gic_get_intid(HV_GIC_INT_MAINTENANCE) -> hrc=%#x / IntId=%u\n", hrc, u32IntId));
1125 hrc = hv_gic_get_intid(HV_GIC_INT_PERFORMANCE_MONITOR, &u32IntId);
1126 LogRel(("GICNem: hv_gic_get_intid(HV_GIC_INT_PERFORMANCE_MONITOR) -> hrc=%#x / IntId=%u\n", hrc, u32IntId));
1127}
1128
1129
1130/**
1131 * Sets the given SPI inside the in-kernel KVM GIC.
1132 *
1133 * @returns VBox status code.
1134 * @param pVM The VM instance.
1135 * @param uIntId The SPI ID to update.
1136 * @param fAsserted Flag whether the interrupt is asserted (true) or not (false).
1137 */
1138VMMR3_INT_DECL(int) GICR3NemSpiSet(PVMCC pVM, uint32_t uIntId, bool fAsserted)
1139{
1140 RT_NOREF(pVM);
1141 Assert(hv_gic_set_spi);
1142
1143 hv_return_t hrc = hv_gic_set_spi(uIntId + GIC_INTID_RANGE_SPI_START, fAsserted);
1144 return nemR3DarwinHvSts2Rc(hrc);
1145}
1146
1147
1148/**
1149 * Sets the given PPI inside the in-kernel KVM GIC.
1150 *
1151 * @returns VBox status code.
1152 * @param pVCpu The vCPU for whih the PPI state is updated.
1153 * @param uIntId The PPI ID to update.
1154 * @param fAsserted Flag whether the interrupt is asserted (true) or not (false).
1155 */
1156VMMR3_INT_DECL(int) GICR3NemPpiSet(PVMCPUCC pVCpu, uint32_t uIntId, bool fAsserted)
1157{
1158 RT_NOREF(pVCpu, uIntId, fAsserted);
1159
1160 /* Should never be called as the PPIs are handled entirely in Hypervisor.framework/AppleHV. */
1161 AssertFailed();
1162 return VERR_NEM_IPE_9;
1163}
1164
1165
1166static int nemR3DarwinGicCreate(PVM pVM)
1167{
1168 nemR3DarwinDumpGicInfo();
1169
1170 //PCFGMNODE pGicDev = CFGMR3GetChild(CFGMR3GetRoot(pVM), "Devices/gic/0");
1171 PCFGMNODE pGicCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "Devices/gic-nem/0/Config");
1172
1173 hv_gic_config_t hGicCfg = hv_gic_config_create();
1174
1175 /*
1176 * Query the MMIO ranges.
1177 */
1178 RTGCPHYS GCPhysMmioBaseDist = 0;
1179 int rc = CFGMR3QueryU64(pGicCfg, "DistributorMmioBase", &GCPhysMmioBaseDist);
1180 if (RT_FAILURE(rc))
1181 return VMSetError(pVM, rc, RT_SRC_POS,
1182 "Configuration error: Failed to get the \"DistributorMmioBase\" value\n");
1183
1184 RTGCPHYS GCPhysMmioBaseReDist = 0;
1185 rc = CFGMR3QueryU64(pGicCfg, "RedistributorMmioBase", &GCPhysMmioBaseReDist);
1186 if (RT_FAILURE(rc))
1187 return VMSetError(pVM, rc, RT_SRC_POS,
1188 "Configuration error: Failed to get the \"RedistributorMmioBase\" value\n");
1189
1190 hv_return_t hrc = hv_gic_config_set_distributor_base(hGicCfg, GCPhysMmioBaseDist);
1191 if (hrc != HV_SUCCESS)
1192 return nemR3DarwinHvSts2Rc(hrc);
1193
1194 hrc = hv_gic_config_set_redistributor_base(hGicCfg, GCPhysMmioBaseReDist);
1195 if (hrc != HV_SUCCESS)
1196 return nemR3DarwinHvSts2Rc(hrc);
1197
1198 hrc = hv_gic_create(hGicCfg);
1199 os_release(hGicCfg);
1200 if (hrc != HV_SUCCESS)
1201 return nemR3DarwinHvSts2Rc(hrc);
1202
1203 /* Make sure the device is not instantiated as Hypervisor.framework provides it. */
1204 //CFGMR3RemoveNode(pGicDev);
1205 return rc;
1206}
1207
1208
1209/**
1210 * Try initialize the native API.
1211 *
1212 * This may only do part of the job, more can be done in
1213 * nemR3NativeInitAfterCPUM() and nemR3NativeInitCompleted().
1214 *
1215 * @returns VBox status code.
1216 * @param pVM The cross context VM structure.
1217 * @param fFallback Whether we're in fallback mode or use-NEM mode. In
1218 * the latter we'll fail if we cannot initialize.
1219 * @param fForced Whether the HMForced flag is set and we should
1220 * fail if we cannot initialize.
1221 */
1222int nemR3NativeInit(PVM pVM, bool fFallback, bool fForced)
1223{
1224 AssertReturn(!pVM->nem.s.fCreatedVm, VERR_WRONG_ORDER);
1225
1226 /*
1227 * Some state init.
1228 */
1229 PCFGMNODE pCfgNem = CFGMR3GetChild(CFGMR3GetRoot(pVM), "NEM/");
1230 RT_NOREF(pCfgNem);
1231
1232 /*
1233 * Error state.
1234 * The error message will be non-empty on failure and 'rc' will be set too.
1235 */
1236 RTERRINFOSTATIC ErrInfo;
1237 PRTERRINFO pErrInfo = RTErrInfoInitStatic(&ErrInfo);
1238
1239 /* Resolve optional imports */
1240 int rc = nemR3DarwinLoadHv(pErrInfo);
1241 if (RT_FAILURE(rc))
1242 return rc;
1243
1244 /*
1245 * Need to enable nested virt here if supported and reset the CFGM value to false
1246 * if not supported. This ASSUMES that NEM is initialized before CPUM.
1247 */
1248 PCFGMNODE pCfgCpum = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/");
1249 hv_vm_config_t hVmCfg = hv_vm_config_create();
1250
1251 if (hv_vm_config_get_el2_supported)
1252 {
1253 bool fHvEl2Supported = false;
1254 hv_return_t hrc = hv_vm_config_get_el2_supported(&fHvEl2Supported);
1255 if ( hrc == HV_SUCCESS
1256 && fHvEl2Supported)
1257 {
1258 /** @cfgm{/CPUM/NestedHWVirt, bool, false}
1259 * Whether to expose the hardware virtualization (EL2/VHE) feature to the guest.
1260 * The default is false. Only supported on M3 and later and macOS 15.0+ (Sonoma).
1261 */
1262 bool fNestedHWVirt = false;
1263 rc = CFGMR3QueryBoolDef(pCfgCpum, "NestedHWVirt", &fNestedHWVirt, false);
1264 AssertLogRelRCReturn(rc, rc);
1265 if (fNestedHWVirt)
1266 {
1267 hrc = hv_vm_config_set_el2_enabled(hVmCfg, fNestedHWVirt);
1268 if (hrc != HV_SUCCESS)
1269 return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
1270 "Cannot enable nested virtualization (hrc=%#x)!\n", hrc);
1271 else
1272 {
1273 pVM->nem.s.fEl2Enabled = true;
1274 LogRel(("NEM: Enabled nested virtualization (EL2) support\n"));
1275 }
1276 }
1277 }
1278 else
1279 {
1280 /* Ensure nested virt is not set. */
1281 rc = CFGMR3RemoveValue(pCfgCpum, "NestedHWVirt");
1282
1283 LogRel(("NEM: The host doesn't supported nested virtualization! (hrc=%#x fHvEl2Supported=%RTbool)\n",
1284 hrc, fHvEl2Supported));
1285 }
1286 }
1287 else
1288 {
1289 /* Ensure nested virt is not set. */
1290 rc = CFGMR3RemoveValue(pCfgCpum, "NestedHWVirt");
1291 LogRel(("NEM: Hypervisor.framework doesn't supported nested virtualization!\n"));
1292 }
1293
1294 hv_return_t hrc = hv_vm_create(hVmCfg);
1295 os_release(hVmCfg);
1296 if (hrc == HV_SUCCESS)
1297 {
1298 pVM->nem.s.fCreatedVm = true;
1299 pVM->nem.s.u64CntFrqHz = ASMReadCntFrqEl0();
1300
1301 /* Will be initialized in NEMHCResumeCpuTickOnAll() before executing guest code. */
1302 pVM->nem.s.u64VTimerOff = 0;
1303
1304 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_NATIVE_API);
1305 Log(("NEM: Marked active!\n"));
1306 PGMR3EnableNemMode(pVM);
1307 }
1308 else
1309 rc = RTErrInfoSetF(pErrInfo, VERR_NEM_INIT_FAILED,
1310 "hv_vm_create() failed: %#x", hrc);
1311
1312 /*
1313 * We only fail if in forced mode, otherwise just log the complaint and return.
1314 */
1315 Assert(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API || RTErrInfoIsSet(pErrInfo));
1316 if ( (fForced || !fFallback)
1317 && pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NATIVE_API)
1318 return VMSetError(pVM, RT_SUCCESS_NP(rc) ? VERR_NEM_NOT_AVAILABLE : rc, RT_SRC_POS, "%s", pErrInfo->pszMsg);
1319
1320 if (RTErrInfoIsSet(pErrInfo))
1321 LogRel(("NEM: Not available: %s\n", pErrInfo->pszMsg));
1322 return VINF_SUCCESS;
1323}
1324
1325
1326/**
1327 * Worker to create the vCPU handle on the EMT running it later on (as required by HV).
1328 *
1329 * @returns VBox status code
1330 * @param pVM The VM handle.
1331 * @param pVCpu The vCPU handle.
1332 * @param idCpu ID of the CPU to create.
1333 */
1334static DECLCALLBACK(int) nemR3DarwinNativeInitVCpuOnEmt(PVM pVM, PVMCPU pVCpu, VMCPUID idCpu)
1335{
1336 if (idCpu == 0)
1337 {
1338 Assert(pVM->nem.s.hVCpuCfg == NULL);
1339
1340 /* Create a new vCPU config and query the ID registers. */
1341 pVM->nem.s.hVCpuCfg = hv_vcpu_config_create();
1342 if (!pVM->nem.s.hVCpuCfg)
1343 return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS,
1344 "Call to hv_vcpu_config_create failed on vCPU %u", idCpu);
1345
1346 /* Query ID registers and hand them to CPUM. */
1347 CPUMIDREGS IdRegs; RT_ZERO(IdRegs);
1348 for (uint32_t i = 0; i < RT_ELEMENTS(s_aIdRegs); i++)
1349 {
1350 uint64_t *pu64 = (uint64_t *)((uint8_t *)&IdRegs + s_aIdRegs[i].offIdStruct);
1351 hv_return_t hrc = hv_vcpu_config_get_feature_reg(pVM->nem.s.hVCpuCfg, s_aIdRegs[i].enmHvReg, pu64);
1352 if (hrc != HV_SUCCESS)
1353 return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS,
1354 "Call to hv_vcpu_get_feature_reg(, %#x, ) failed: %#x (%Rrc)", hrc, nemR3DarwinHvSts2Rc(hrc));
1355 }
1356
1357 int rc = CPUMR3PopulateFeaturesByIdRegisters(pVM, &IdRegs);
1358 if (RT_FAILURE(rc))
1359 return rc;
1360 }
1361
1362 hv_return_t hrc = hv_vcpu_create(&pVCpu->nem.s.hVCpu, &pVCpu->nem.s.pHvExit, pVM->nem.s.hVCpuCfg);
1363 if (hrc != HV_SUCCESS)
1364 return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS,
1365 "Call to hv_vcpu_create failed on vCPU %u: %#x (%Rrc)", idCpu, hrc, nemR3DarwinHvSts2Rc(hrc));
1366
1367 hrc = hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_MPIDR_EL1, idCpu);
1368 if (hrc != HV_SUCCESS)
1369 return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS,
1370 "Setting MPIDR_EL1 failed on vCPU %u: %#x (%Rrc)", idCpu, hrc, nemR3DarwinHvSts2Rc(hrc));
1371
1372 return VINF_SUCCESS;
1373}
1374
1375
1376/**
1377 * Worker to destroy the vCPU handle on the EMT running it later on (as required by HV).
1378 *
1379 * @returns VBox status code.
1380 * @param pVM The VM handle.
1381 * @param pVCpu The vCPU handle.
1382 */
1383static DECLCALLBACK(int) nemR3DarwinNativeTermVCpuOnEmt(PVM pVM, PVMCPU pVCpu)
1384{
1385 hv_return_t hrc = hv_vcpu_destroy(pVCpu->nem.s.hVCpu);
1386 Assert(hrc == HV_SUCCESS); RT_NOREF(hrc);
1387
1388 if (pVCpu->idCpu == 0)
1389 {
1390 os_release(pVM->nem.s.hVCpuCfg);
1391 pVM->nem.s.hVCpuCfg = NULL;
1392 }
1393 return VINF_SUCCESS;
1394}
1395
1396
1397/**
1398 * This is called after CPUMR3Init is done.
1399 *
1400 * @returns VBox status code.
1401 * @param pVM The VM handle..
1402 */
1403int nemR3NativeInitAfterCPUM(PVM pVM)
1404{
1405 /*
1406 * Validate sanity.
1407 */
1408 AssertReturn(!pVM->nem.s.fCreatedEmts, VERR_WRONG_ORDER);
1409 AssertReturn(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API, VERR_WRONG_ORDER);
1410
1411 /* Need to create the GIC here before any vCPU is created according to the Apple docs. */
1412 if (hv_gic_create)
1413 {
1414 int rc = nemR3DarwinGicCreate(pVM);
1415 if (RT_FAILURE(rc))
1416 return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS, "Creating the GIC failed: %Rrc", rc);
1417 }
1418
1419 /*
1420 * Setup the EMTs.
1421 */
1422 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1423 {
1424 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1425
1426 int rc = VMR3ReqCallWait(pVM, idCpu, (PFNRT)nemR3DarwinNativeInitVCpuOnEmt, 3, pVM, pVCpu, idCpu);
1427 if (RT_FAILURE(rc))
1428 {
1429 /* Rollback. */
1430 while (idCpu--)
1431 VMR3ReqCallWait(pVM, idCpu, (PFNRT)nemR3DarwinNativeTermVCpuOnEmt, 2, pVM, pVCpu);
1432
1433 return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS, "Call to hv_vcpu_create failed: %Rrc", rc);
1434 }
1435 }
1436
1437 pVM->nem.s.fCreatedEmts = true;
1438 return VINF_SUCCESS;
1439}
1440
1441
1442int nemR3NativeInitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
1443{
1444 RT_NOREF(pVM, enmWhat);
1445 return VINF_SUCCESS;
1446}
1447
1448
1449int nemR3NativeTerm(PVM pVM)
1450{
1451 /*
1452 * Delete the VM.
1453 */
1454
1455 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu--)
1456 {
1457 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1458
1459 /*
1460 * Apple's documentation states that the vCPU should be destroyed
1461 * on the thread running the vCPU but as all the other EMTs are gone
1462 * at this point, destroying the VM would hang.
1463 *
1464 * We seem to be at luck here though as destroying apparently works
1465 * from EMT(0) as well.
1466 */
1467 hv_return_t hrc = hv_vcpu_destroy(pVCpu->nem.s.hVCpu);
1468 Assert(hrc == HV_SUCCESS); RT_NOREF(hrc);
1469 }
1470
1471 pVM->nem.s.fCreatedEmts = false;
1472 if (pVM->nem.s.fCreatedVm)
1473 {
1474 hv_return_t hrc = hv_vm_destroy();
1475 if (hrc != HV_SUCCESS)
1476 LogRel(("NEM: hv_vm_destroy() failed with %#x\n", hrc));
1477
1478 pVM->nem.s.fCreatedVm = false;
1479 }
1480 return VINF_SUCCESS;
1481}
1482
1483
1484/**
1485 * VM reset notification.
1486 *
1487 * @param pVM The cross context VM structure.
1488 */
1489void nemR3NativeReset(PVM pVM)
1490{
1491 RT_NOREF(pVM);
1492}
1493
1494
1495/**
1496 * Reset CPU due to INIT IPI or hot (un)plugging.
1497 *
1498 * @param pVCpu The cross context virtual CPU structure of the CPU being
1499 * reset.
1500 * @param fInitIpi Whether this is the INIT IPI or hot (un)plugging case.
1501 */
1502void nemR3NativeResetCpu(PVMCPU pVCpu, bool fInitIpi)
1503{
1504 RT_NOREF(pVCpu, fInitIpi);
1505}
1506
1507
1508/**
1509 * Returns the byte size from the given access SAS value.
1510 *
1511 * @returns Number of bytes to transfer.
1512 * @param uSas The SAS value to convert.
1513 */
1514DECLINLINE(size_t) nemR3DarwinGetByteCountFromSas(uint8_t uSas)
1515{
1516 switch (uSas)
1517 {
1518 case ARMV8_EC_ISS_DATA_ABRT_SAS_BYTE: return sizeof(uint8_t);
1519 case ARMV8_EC_ISS_DATA_ABRT_SAS_HALFWORD: return sizeof(uint16_t);
1520 case ARMV8_EC_ISS_DATA_ABRT_SAS_WORD: return sizeof(uint32_t);
1521 case ARMV8_EC_ISS_DATA_ABRT_SAS_DWORD: return sizeof(uint64_t);
1522 default:
1523 AssertReleaseFailed();
1524 }
1525
1526 return 0;
1527}
1528
1529
1530/**
1531 * Sets the given general purpose register to the given value.
1532 *
1533 * @param pVCpu The cross context virtual CPU structure of the
1534 * calling EMT.
1535 * @param uReg The register index.
1536 * @param f64BitReg Flag whether to operate on a 64-bit or 32-bit register.
1537 * @param fSignExtend Flag whether to sign extend the value.
1538 * @param u64Val The value.
1539 */
1540DECLINLINE(void) nemR3DarwinSetGReg(PVMCPU pVCpu, uint8_t uReg, bool f64BitReg, bool fSignExtend, uint64_t u64Val)
1541{
1542 AssertReturnVoid(uReg < 31);
1543
1544 if (f64BitReg)
1545 pVCpu->cpum.GstCtx.aGRegs[uReg].x = fSignExtend ? (int64_t)u64Val : u64Val;
1546 else
1547 pVCpu->cpum.GstCtx.aGRegs[uReg].w = fSignExtend ? (int32_t)u64Val : u64Val; /** @todo Does this clear the upper half on real hardware? */
1548
1549 /* Mark the register as not extern anymore. */
1550 switch (uReg)
1551 {
1552 case 0:
1553 pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_X0;
1554 break;
1555 case 1:
1556 pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_X1;
1557 break;
1558 case 2:
1559 pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_X2;
1560 break;
1561 case 3:
1562 pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_X3;
1563 break;
1564 default:
1565 AssertRelease(!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_X4_X28));
1566 /** @todo We need to import all missing registers in order to clear this flag (or just set it in HV from here). */
1567 }
1568}
1569
1570
1571/**
1572 * Gets the given general purpose register and returns the value.
1573 *
1574 * @returns Value from the given register.
1575 * @param pVCpu The cross context virtual CPU structure of the
1576 * calling EMT.
1577 * @param uReg The register index.
1578 */
1579DECLINLINE(uint64_t) nemR3DarwinGetGReg(PVMCPU pVCpu, uint8_t uReg)
1580{
1581 AssertReturn(uReg <= ARMV8_AARCH64_REG_ZR, 0);
1582
1583 if (uReg == ARMV8_AARCH64_REG_ZR)
1584 return 0;
1585
1586 /** @todo Import the register if extern. */
1587 AssertRelease(!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_GPRS_MASK));
1588
1589 return pVCpu->cpum.GstCtx.aGRegs[uReg].x;
1590}
1591
1592
1593/**
1594 * Works on the data abort exception (which will be a MMIO access most of the time).
1595 *
1596 * @returns VBox strict status code.
1597 * @param pVM The cross context VM structure.
1598 * @param pVCpu The cross context virtual CPU structure of the
1599 * calling EMT.
1600 * @param uIss The instruction specific syndrome value.
1601 * @param fInsn32Bit Flag whether the exception was caused by a 32-bit or 16-bit instruction.
1602 * @param GCPtrDataAbrt The virtual GC address causing the data abort.
1603 * @param GCPhysDataAbrt The physical GC address which caused the data abort.
1604 */
1605static VBOXSTRICTRC nemR3DarwinHandleExitExceptionDataAbort(PVM pVM, PVMCPU pVCpu, uint32_t uIss, bool fInsn32Bit,
1606 RTGCPTR GCPtrDataAbrt, RTGCPHYS GCPhysDataAbrt)
1607{
1608 bool fIsv = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_ISV);
1609 bool fL2Fault = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_S1PTW);
1610 bool fWrite = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_WNR);
1611 bool f64BitReg = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_SF);
1612 bool fSignExtend = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_SSE);
1613 uint8_t uReg = ARMV8_EC_ISS_DATA_ABRT_SRT_GET(uIss);
1614 uint8_t uAcc = ARMV8_EC_ISS_DATA_ABRT_SAS_GET(uIss);
1615 size_t cbAcc = nemR3DarwinGetByteCountFromSas(uAcc);
1616 LogFlowFunc(("fIsv=%RTbool fL2Fault=%RTbool fWrite=%RTbool f64BitReg=%RTbool fSignExtend=%RTbool uReg=%u uAcc=%u GCPtrDataAbrt=%RGv GCPhysDataAbrt=%RGp\n",
1617 fIsv, fL2Fault, fWrite, f64BitReg, fSignExtend, uReg, uAcc, GCPtrDataAbrt, GCPhysDataAbrt));
1618
1619 RT_NOREF(fL2Fault, GCPtrDataAbrt);
1620
1621 if (fWrite)
1622 {
1623 /*
1624 * Check whether this is one of the dirty tracked regions, mark it as dirty
1625 * and enable write support for this region again.
1626 *
1627 * This is required for proper VRAM tracking or the display might not get updated
1628 * and it is impossible to use the PGM generic facility as it operates on guest page sizes
1629 * but setting protection flags with Hypervisor.framework works only host page sized regions, so
1630 * we have to cook our own. Additionally the VRAM region is marked as prefetchable (write-back)
1631 * which doesn't produce a valid instruction syndrome requiring restarting the instruction after enabling
1632 * write access again (due to a missing interpreter right now).
1633 */
1634 for (uint32_t idSlot = 0; idSlot < RT_ELEMENTS(pVM->nem.s.aMmio2DirtyTracking); idSlot++)
1635 {
1636 PNEMHVMMIO2REGION pMmio2Region = &pVM->nem.s.aMmio2DirtyTracking[idSlot];
1637
1638 if ( GCPhysDataAbrt >= pMmio2Region->GCPhysStart
1639 && GCPhysDataAbrt <= pMmio2Region->GCPhysLast)
1640 {
1641 pMmio2Region->fDirty = true;
1642
1643 uint8_t u2State;
1644 int rc = nemR3DarwinProtect(pMmio2Region->GCPhysStart, pMmio2Region->GCPhysLast - pMmio2Region->GCPhysStart + 1,
1645 NEM_PAGE_PROT_READ | NEM_PAGE_PROT_EXECUTE | NEM_PAGE_PROT_WRITE, &u2State);
1646
1647 /* Restart the instruction if there is no instruction syndrome available. */
1648 if (RT_FAILURE(rc) || !fIsv)
1649 return rc;
1650 }
1651 }
1652 }
1653
1654 AssertReturn(fIsv, VERR_NOT_SUPPORTED); /** @todo Implement using IEM when this should occur. */
1655
1656 EMHistoryAddExit(pVCpu,
1657 fWrite
1658 ? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MMIO_WRITE)
1659 : EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MMIO_READ),
1660 pVCpu->cpum.GstCtx.Pc.u64, ASMReadTSC());
1661
1662 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1663 uint64_t u64Val = 0;
1664 if (fWrite)
1665 {
1666 u64Val = nemR3DarwinGetGReg(pVCpu, uReg);
1667 rcStrict = PGMPhysWrite(pVM, GCPhysDataAbrt, &u64Val, cbAcc, PGMACCESSORIGIN_HM);
1668 Log4(("MmioExit/%u: %08RX64: WRITE %#x LB %u, %.*Rhxs -> rcStrict=%Rrc\n",
1669 pVCpu->idCpu, pVCpu->cpum.GstCtx.Pc.u64, GCPhysDataAbrt, cbAcc, cbAcc,
1670 &u64Val, VBOXSTRICTRC_VAL(rcStrict) ));
1671 }
1672 else
1673 {
1674 rcStrict = PGMPhysRead(pVM, GCPhysDataAbrt, &u64Val, cbAcc, PGMACCESSORIGIN_HM);
1675 Log4(("MmioExit/%u: %08RX64: READ %#x LB %u -> %.*Rhxs rcStrict=%Rrc\n",
1676 pVCpu->idCpu, pVCpu->cpum.GstCtx.Pc.u64, GCPhysDataAbrt, cbAcc, cbAcc,
1677 &u64Val, VBOXSTRICTRC_VAL(rcStrict) ));
1678 if (rcStrict == VINF_SUCCESS)
1679 nemR3DarwinSetGReg(pVCpu, uReg, f64BitReg, fSignExtend, u64Val);
1680 }
1681
1682 if (rcStrict == VINF_SUCCESS)
1683 pVCpu->cpum.GstCtx.Pc.u64 += fInsn32Bit ? sizeof(uint32_t) : sizeof(uint16_t);
1684
1685 return rcStrict;
1686}
1687
1688
1689/**
1690 * Works on the trapped MRS, MSR and system instruction exception.
1691 *
1692 * @returns VBox strict status code.
1693 * @param pVM The cross context VM structure.
1694 * @param pVCpu The cross context virtual CPU structure of the
1695 * calling EMT.
1696 * @param uIss The instruction specific syndrome value.
1697 * @param fInsn32Bit Flag whether the exception was caused by a 32-bit or 16-bit instruction.
1698 */
1699static VBOXSTRICTRC nemR3DarwinHandleExitExceptionTrappedSysInsn(PVM pVM, PVMCPU pVCpu, uint32_t uIss, bool fInsn32Bit)
1700{
1701 bool fRead = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION_IS_READ(uIss);
1702 uint8_t uCRm = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM_GET(uIss);
1703 uint8_t uReg = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT_GET(uIss);
1704 uint8_t uCRn = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN_GET(uIss);
1705 uint8_t uOp1 = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1_GET(uIss);
1706 uint8_t uOp2 = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2_GET(uIss);
1707 uint8_t uOp0 = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0_GET(uIss);
1708 uint16_t idSysReg = ARMV8_AARCH64_SYSREG_ID_CREATE(uOp0, uOp1, uCRn, uCRm, uOp2);
1709 LogFlowFunc(("fRead=%RTbool uCRm=%u uReg=%u uCRn=%u uOp1=%u uOp2=%u uOp0=%u idSysReg=%#x\n",
1710 fRead, uCRm, uReg, uCRn, uOp1, uOp2, uOp0, idSysReg));
1711
1712 /** @todo EMEXITTYPE_MSR_READ/EMEXITTYPE_MSR_WRITE are misnomers. */
1713 EMHistoryAddExit(pVCpu,
1714 fRead
1715 ? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_READ)
1716 : EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_WRITE),
1717 pVCpu->cpum.GstCtx.Pc.u64, ASMReadTSC());
1718
1719 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1720 uint64_t u64Val = 0;
1721 if (fRead)
1722 {
1723 RT_NOREF(pVM);
1724 rcStrict = CPUMQueryGuestSysReg(pVCpu, idSysReg, &u64Val);
1725 Log4(("SysInsnExit/%u: %08RX64: READ %u:%u:%u:%u:%u -> %#RX64 rcStrict=%Rrc\n",
1726 pVCpu->idCpu, pVCpu->cpum.GstCtx.Pc.u64, uOp0, uOp1, uCRn, uCRm, uOp2, u64Val,
1727 VBOXSTRICTRC_VAL(rcStrict) ));
1728 if (rcStrict == VINF_SUCCESS)
1729 nemR3DarwinSetGReg(pVCpu, uReg, true /*f64BitReg*/, false /*fSignExtend*/, u64Val);
1730 }
1731 else
1732 {
1733 u64Val = nemR3DarwinGetGReg(pVCpu, uReg);
1734 rcStrict = CPUMSetGuestSysReg(pVCpu, idSysReg, u64Val);
1735 Log4(("SysInsnExit/%u: %08RX64: WRITE %u:%u:%u:%u:%u %#RX64 -> rcStrict=%Rrc\n",
1736 pVCpu->idCpu, pVCpu->cpum.GstCtx.Pc.u64, uOp0, uOp1, uCRn, uCRm, uOp2, u64Val,
1737 VBOXSTRICTRC_VAL(rcStrict) ));
1738 }
1739
1740 if (rcStrict == VINF_SUCCESS)
1741 pVCpu->cpum.GstCtx.Pc.u64 += fInsn32Bit ? sizeof(uint32_t) : sizeof(uint16_t);
1742
1743 return rcStrict;
1744}
1745
1746
1747/**
1748 * Works on the trapped HVC instruction exception.
1749 *
1750 * @returns VBox strict status code.
1751 * @param pVM The cross context VM structure.
1752 * @param pVCpu The cross context virtual CPU structure of the
1753 * calling EMT.
1754 * @param uIss The instruction specific syndrome value.
1755 * @param fAdvancePc Flag whether to advance the guest program counter.
1756 */
1757static VBOXSTRICTRC nemR3DarwinHandleExitExceptionTrappedHvcInsn(PVM pVM, PVMCPU pVCpu, uint32_t uIss, bool fAdvancePc = false)
1758{
1759 uint16_t u16Imm = ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM_GET(uIss);
1760 LogFlowFunc(("u16Imm=%#RX16\n", u16Imm));
1761
1762#if 0 /** @todo For later */
1763 EMHistoryAddExit(pVCpu,
1764 fRead
1765 ? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_READ)
1766 : EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_WRITE),
1767 pVCpu->cpum.GstCtx.Pc.u64, ASMReadTSC());
1768#endif
1769
1770 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1771 if (u16Imm == 0)
1772 {
1773 /** @todo Raise exception to EL1 if PSCI not configured. */
1774 /** @todo Need a generic mechanism here to pass this to, GIM maybe?. */
1775 uint32_t uFunId = pVCpu->cpum.GstCtx.aGRegs[ARMV8_AARCH64_REG_X0].w;
1776 bool fHvc64 = RT_BOOL(uFunId & ARM_SMCCC_FUNC_ID_64BIT); RT_NOREF(fHvc64);
1777 uint32_t uEntity = ARM_SMCCC_FUNC_ID_ENTITY_GET(uFunId);
1778 uint32_t uFunNum = ARM_SMCCC_FUNC_ID_NUM_GET(uFunId);
1779 if (uEntity == ARM_SMCCC_FUNC_ID_ENTITY_STD_SEC_SERVICE)
1780 {
1781 switch (uFunNum)
1782 {
1783 case ARM_PSCI_FUNC_ID_PSCI_VERSION:
1784 nemR3DarwinSetGReg(pVCpu, ARMV8_AARCH64_REG_X0, false /*f64BitReg*/, false /*fSignExtend*/, ARM_PSCI_FUNC_ID_PSCI_VERSION_SET(1, 2));
1785 break;
1786 case ARM_PSCI_FUNC_ID_SYSTEM_OFF:
1787 rcStrict = VMR3PowerOff(pVM->pUVM);
1788 break;
1789 case ARM_PSCI_FUNC_ID_SYSTEM_RESET:
1790 case ARM_PSCI_FUNC_ID_SYSTEM_RESET2:
1791 {
1792 bool fHaltOnReset;
1793 int rc = CFGMR3QueryBool(CFGMR3GetChild(CFGMR3GetRoot(pVM), "PDM"), "HaltOnReset", &fHaltOnReset);
1794 if (RT_SUCCESS(rc) && fHaltOnReset)
1795 {
1796 Log(("nemR3DarwinHandleExitExceptionTrappedHvcInsn: Halt On Reset!\n"));
1797 rc = VINF_EM_HALT;
1798 }
1799 else
1800 {
1801 /** @todo pVM->pdm.s.fResetFlags = fFlags; */
1802 VM_FF_SET(pVM, VM_FF_RESET);
1803 rc = VINF_EM_RESET;
1804 }
1805 break;
1806 }
1807 case ARM_PSCI_FUNC_ID_CPU_ON:
1808 {
1809 uint64_t u64TgtCpu = nemR3DarwinGetGReg(pVCpu, ARMV8_AARCH64_REG_X1);
1810 RTGCPHYS GCPhysExecAddr = nemR3DarwinGetGReg(pVCpu, ARMV8_AARCH64_REG_X2);
1811 uint64_t u64CtxId = nemR3DarwinGetGReg(pVCpu, ARMV8_AARCH64_REG_X3);
1812 VMMR3CpuOn(pVM, u64TgtCpu & 0xff, GCPhysExecAddr, u64CtxId);
1813 nemR3DarwinSetGReg(pVCpu, ARMV8_AARCH64_REG_X0, true /*f64BitReg*/, false /*fSignExtend*/, ARM_PSCI_STS_SUCCESS);
1814 break;
1815 }
1816 case ARM_PSCI_FUNC_ID_PSCI_FEATURES:
1817 {
1818 uint32_t u32FunNum = (uint32_t)nemR3DarwinGetGReg(pVCpu, ARMV8_AARCH64_REG_X1);
1819 switch (u32FunNum)
1820 {
1821 case ARM_PSCI_FUNC_ID_PSCI_VERSION:
1822 case ARM_PSCI_FUNC_ID_SYSTEM_OFF:
1823 case ARM_PSCI_FUNC_ID_SYSTEM_RESET:
1824 case ARM_PSCI_FUNC_ID_SYSTEM_RESET2:
1825 case ARM_PSCI_FUNC_ID_CPU_ON:
1826 case ARM_PSCI_FUNC_ID_MIGRATE_INFO_TYPE:
1827 nemR3DarwinSetGReg(pVCpu, ARMV8_AARCH64_REG_X0,
1828 false /*f64BitReg*/, false /*fSignExtend*/,
1829 (uint64_t)ARM_PSCI_STS_SUCCESS);
1830 break;
1831 default:
1832 nemR3DarwinSetGReg(pVCpu, ARMV8_AARCH64_REG_X0,
1833 false /*f64BitReg*/, false /*fSignExtend*/,
1834 (uint64_t)ARM_PSCI_STS_NOT_SUPPORTED);
1835 }
1836 break;
1837 }
1838 case ARM_PSCI_FUNC_ID_MIGRATE_INFO_TYPE:
1839 nemR3DarwinSetGReg(pVCpu, ARMV8_AARCH64_REG_X0, false /*f64BitReg*/, false /*fSignExtend*/, ARM_PSCI_MIGRATE_INFO_TYPE_TOS_NOT_PRESENT);
1840 break;
1841 default:
1842 nemR3DarwinSetGReg(pVCpu, ARMV8_AARCH64_REG_X0, false /*f64BitReg*/, false /*fSignExtend*/, (uint64_t)ARM_PSCI_STS_NOT_SUPPORTED);
1843 }
1844 }
1845 else
1846 nemR3DarwinSetGReg(pVCpu, ARMV8_AARCH64_REG_X0, false /*f64BitReg*/, false /*fSignExtend*/, (uint64_t)ARM_PSCI_STS_NOT_SUPPORTED);
1847 }
1848 /** @todo What to do if immediate is != 0? */
1849
1850 if ( rcStrict == VINF_SUCCESS
1851 && fAdvancePc)
1852 pVCpu->cpum.GstCtx.Pc.u64 += sizeof(uint32_t);
1853
1854 return rcStrict;
1855}
1856
1857
1858/**
1859 * Handles an exception VM exit.
1860 *
1861 * @returns VBox strict status code.
1862 * @param pVM The cross context VM structure.
1863 * @param pVCpu The cross context virtual CPU structure of the
1864 * calling EMT.
1865 * @param pExit Pointer to the exit information.
1866 */
1867static VBOXSTRICTRC nemR3DarwinHandleExitException(PVM pVM, PVMCPU pVCpu, const hv_vcpu_exit_t *pExit)
1868{
1869 uint32_t uEc = ARMV8_ESR_EL2_EC_GET(pExit->exception.syndrome);
1870 uint32_t uIss = ARMV8_ESR_EL2_ISS_GET(pExit->exception.syndrome);
1871 bool fInsn32Bit = ARMV8_ESR_EL2_IL_IS_32BIT(pExit->exception.syndrome);
1872
1873 LogFlowFunc(("pVM=%p pVCpu=%p{.idCpu=%u} uEc=%u{%s} uIss=%#RX32 fInsn32Bit=%RTbool\n",
1874 pVM, pVCpu, pVCpu->idCpu, uEc, nemR3DarwinEsrEl2EcStringify(uEc), uIss, fInsn32Bit));
1875
1876 switch (uEc)
1877 {
1878 case ARMV8_ESR_EL2_DATA_ABORT_FROM_LOWER_EL:
1879 return nemR3DarwinHandleExitExceptionDataAbort(pVM, pVCpu, uIss, fInsn32Bit, pExit->exception.virtual_address,
1880 pExit->exception.physical_address);
1881 case ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_SYS_INSN:
1882 return nemR3DarwinHandleExitExceptionTrappedSysInsn(pVM, pVCpu, uIss, fInsn32Bit);
1883 case ARMV8_ESR_EL2_EC_AARCH64_HVC_INSN:
1884 return nemR3DarwinHandleExitExceptionTrappedHvcInsn(pVM, pVCpu, uIss);
1885 case ARMV8_ESR_EL2_EC_AARCH64_SMC_INSN:
1886 return nemR3DarwinHandleExitExceptionTrappedHvcInsn(pVM, pVCpu, uIss, true);
1887 case ARMV8_ESR_EL2_EC_TRAPPED_WFX:
1888 {
1889 /* No need to halt if there is an interrupt pending already. */
1890 if (VMCPU_FF_IS_ANY_SET(pVCpu, (VMCPU_FF_INTERRUPT_IRQ | VMCPU_FF_INTERRUPT_FIQ)))
1891 return VINF_SUCCESS;
1892
1893 /* Set the vTimer expiration in order to get out of the halt at the right point in time. */
1894 if ( (pVCpu->cpum.GstCtx.CntvCtlEl0 & ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE)
1895 && !(pVCpu->cpum.GstCtx.CntvCtlEl0 & ARMV8_CNTV_CTL_EL0_AARCH64_IMASK))
1896 {
1897 uint64_t cTicksVTimer = mach_absolute_time() - pVM->nem.s.u64VTimerOff;
1898
1899 /* Check whether it expired and start executing guest code. */
1900 if (cTicksVTimer >= pVCpu->cpum.GstCtx.CntvCValEl0)
1901 return VINF_SUCCESS;
1902
1903 uint64_t cTicksVTimerToExpire = pVCpu->cpum.GstCtx.CntvCValEl0 - cTicksVTimer;
1904 uint64_t cNanoSecsVTimerToExpire = ASMMultU64ByU32DivByU32(cTicksVTimerToExpire, RT_NS_1SEC, (uint32_t)pVM->nem.s.u64CntFrqHz);
1905
1906 /*
1907 * Our halt method doesn't work with sub millisecond granularity at the moment causing a huge slowdown
1908 * + scheduling overhead which would increase the wakeup latency.
1909 * So only halt when the threshold is exceeded (needs more experimentation but 5ms turned out to be a good compromise
1910 * between CPU load when the guest is idle and performance).
1911 */
1912 if (cNanoSecsVTimerToExpire < 2 * RT_NS_1MS)
1913 return VINF_SUCCESS;
1914
1915 LogFlowFunc(("Set vTimer activation to cNanoSecsVTimerToExpire=%#RX64 (CntvCValEl0=%#RX64, u64VTimerOff=%#RX64 cTicksVTimer=%#RX64 u64CntFrqHz=%#RX64)\n",
1916 cNanoSecsVTimerToExpire, pVCpu->cpum.GstCtx.CntvCValEl0, pVM->nem.s.u64VTimerOff, cTicksVTimer, pVM->nem.s.u64CntFrqHz));
1917 TMCpuSetVTimerNextActivation(pVCpu, cNanoSecsVTimerToExpire);
1918 }
1919 else
1920 TMCpuSetVTimerNextActivation(pVCpu, UINT64_MAX);
1921
1922 return VINF_EM_HALT;
1923 }
1924 case ARMV8_ESR_EL2_EC_UNKNOWN:
1925 default:
1926 LogRel(("NEM/Darwin: Unknown Exception Class in syndrome: uEc=%u{%s} uIss=%#RX32 fInsn32Bit=%RTbool\n",
1927 uEc, nemR3DarwinEsrEl2EcStringify(uEc), uIss, fInsn32Bit));
1928 AssertReleaseFailed();
1929 return VERR_NOT_IMPLEMENTED;
1930 }
1931
1932 return VINF_SUCCESS;
1933}
1934
1935
1936/**
1937 * Handles an exit from hv_vcpu_run().
1938 *
1939 * @returns VBox strict status code.
1940 * @param pVM The cross context VM structure.
1941 * @param pVCpu The cross context virtual CPU structure of the
1942 * calling EMT.
1943 */
1944static VBOXSTRICTRC nemR3DarwinHandleExit(PVM pVM, PVMCPU pVCpu)
1945{
1946 int rc = nemR3DarwinCopyStateFromHv(pVM, pVCpu, CPUMCTX_EXTRN_ALL);
1947 if (RT_FAILURE(rc))
1948 return rc;
1949
1950#ifdef LOG_ENABLED
1951 if (LogIs3Enabled())
1952 nemR3DarwinLogState(pVM, pVCpu);
1953#endif
1954
1955 hv_vcpu_exit_t *pExit = pVCpu->nem.s.pHvExit;
1956 switch (pExit->reason)
1957 {
1958 case HV_EXIT_REASON_CANCELED:
1959 return VINF_EM_RAW_INTERRUPT;
1960 case HV_EXIT_REASON_EXCEPTION:
1961 return nemR3DarwinHandleExitException(pVM, pVCpu, pExit);
1962 case HV_EXIT_REASON_VTIMER_ACTIVATED:
1963 {
1964 LogFlowFunc(("vTimer got activated\n"));
1965 TMCpuSetVTimerNextActivation(pVCpu, UINT64_MAX);
1966 pVCpu->nem.s.fVTimerActivated = true;
1967 return GICPpiSet(pVCpu, pVM->nem.s.u32GicPpiVTimer, true /*fAsserted*/);
1968 }
1969 default:
1970 AssertReleaseFailed();
1971 break;
1972 }
1973
1974 return VERR_INVALID_STATE;
1975}
1976
1977
1978/**
1979 * Runs the guest once until an exit occurs.
1980 *
1981 * @returns HV status code.
1982 * @param pVM The cross context VM structure.
1983 * @param pVCpu The cross context virtual CPU structure.
1984 */
1985static hv_return_t nemR3DarwinRunGuest(PVM pVM, PVMCPU pVCpu)
1986{
1987 TMNotifyStartOfExecution(pVM, pVCpu);
1988
1989 hv_return_t hrc = hv_vcpu_run(pVCpu->nem.s.hVCpu);
1990
1991 TMNotifyEndOfExecution(pVM, pVCpu, ASMReadTSC());
1992
1993 return hrc;
1994}
1995
1996
1997/**
1998 * Prepares the VM to run the guest.
1999 *
2000 * @returns Strict VBox status code.
2001 * @param pVM The cross context VM structure.
2002 * @param pVCpu The cross context virtual CPU structure.
2003 * @param fSingleStepping Flag whether we run in single stepping mode.
2004 */
2005static VBOXSTRICTRC nemR3DarwinPreRunGuest(PVM pVM, PVMCPU pVCpu, bool fSingleStepping)
2006{
2007#ifdef LOG_ENABLED
2008 bool fIrq = false;
2009 bool fFiq = false;
2010
2011 if (LogIs3Enabled())
2012 nemR3DarwinLogState(pVM, pVCpu);
2013#endif
2014
2015 /** @todo */ RT_NOREF(fSingleStepping);
2016 int rc = nemR3DarwinExportGuestState(pVM, pVCpu);
2017 AssertRCReturn(rc, rc);
2018
2019 /* Check whether the vTimer interrupt was handled by the guest and we can unmask the vTimer. */
2020 if (pVCpu->nem.s.fVTimerActivated)
2021 {
2022 /* Read the CNTV_CTL_EL0 register. */
2023 uint64_t u64CntvCtl = 0;
2024
2025 hv_return_t hrc = hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CTL_EL0, &u64CntvCtl);
2026 AssertRCReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
2027
2028 if ( (u64CntvCtl & (ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE | ARMV8_CNTV_CTL_EL0_AARCH64_IMASK | ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS))
2029 != (ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE | ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS))
2030 {
2031 /* Clear the interrupt. */
2032 GICPpiSet(pVCpu, pVM->nem.s.u32GicPpiVTimer, false /*fAsserted*/);
2033
2034 pVCpu->nem.s.fVTimerActivated = false;
2035 hrc = hv_vcpu_set_vtimer_mask(pVCpu->nem.s.hVCpu, false /*vtimer_is_masked*/);
2036 AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
2037 }
2038 }
2039
2040 /* Set the pending interrupt state. */
2041 hv_return_t hrc = HV_SUCCESS;
2042 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_IRQ))
2043 {
2044 hrc = hv_vcpu_set_pending_interrupt(pVCpu->nem.s.hVCpu, HV_INTERRUPT_TYPE_IRQ, true);
2045 AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
2046#ifdef LOG_ENABLED
2047 fIrq = true;
2048#endif
2049 }
2050 else
2051 {
2052 hrc = hv_vcpu_set_pending_interrupt(pVCpu->nem.s.hVCpu, HV_INTERRUPT_TYPE_IRQ, false);
2053 AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
2054 }
2055
2056 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_FIQ))
2057 {
2058 hrc = hv_vcpu_set_pending_interrupt(pVCpu->nem.s.hVCpu, HV_INTERRUPT_TYPE_FIQ, true);
2059 AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
2060#ifdef LOG_ENABLED
2061 fFiq = true;
2062#endif
2063 }
2064 else
2065 {
2066 hrc = hv_vcpu_set_pending_interrupt(pVCpu->nem.s.hVCpu, HV_INTERRUPT_TYPE_FIQ, false);
2067 AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
2068 }
2069
2070 LogFlowFunc(("Running vCPU [%s,%s]\n", fIrq ? "I" : "nI", fFiq ? "F" : "nF"));
2071 pVCpu->nem.s.fEventPending = false;
2072 return VINF_SUCCESS;
2073}
2074
2075
2076/**
2077 * The normal runloop (no debugging features enabled).
2078 *
2079 * @returns Strict VBox status code.
2080 * @param pVM The cross context VM structure.
2081 * @param pVCpu The cross context virtual CPU structure.
2082 */
2083static VBOXSTRICTRC nemR3DarwinRunGuestNormal(PVM pVM, PVMCPU pVCpu)
2084{
2085 /*
2086 * The run loop.
2087 *
2088 * Current approach to state updating to use the sledgehammer and sync
2089 * everything every time. This will be optimized later.
2090 */
2091
2092 /* Update the vTimer offset after resuming if instructed. */
2093 if (pVCpu->nem.s.fVTimerOffUpdate)
2094 {
2095 hv_return_t hrc = hv_vcpu_set_vtimer_offset(pVCpu->nem.s.hVCpu, pVM->nem.s.u64VTimerOff);
2096 if (hrc != HV_SUCCESS)
2097 return nemR3DarwinHvSts2Rc(hrc);
2098
2099 pVCpu->nem.s.fVTimerOffUpdate = false;
2100
2101 hrc = hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CTL_EL0, pVCpu->cpum.GstCtx.CntvCtlEl0);
2102 if (hrc == HV_SUCCESS)
2103 hrc = hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CVAL_EL0, pVCpu->cpum.GstCtx.CntvCValEl0);
2104 if (hrc != HV_SUCCESS)
2105 return nemR3DarwinHvSts2Rc(hrc);
2106 }
2107
2108 /*
2109 * Poll timers and run for a bit.
2110 */
2111 /** @todo See if we cannot optimize this TMTimerPollGIP by only redoing
2112 * the whole polling job when timers have changed... */
2113 uint64_t offDeltaIgnored;
2114 uint64_t const nsNextTimerEvt = TMTimerPollGIP(pVM, pVCpu, &offDeltaIgnored); NOREF(nsNextTimerEvt);
2115 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
2116 for (unsigned iLoop = 0;; iLoop++)
2117 {
2118 rcStrict = nemR3DarwinPreRunGuest(pVM, pVCpu, false /* fSingleStepping */);
2119 if (rcStrict != VINF_SUCCESS)
2120 break;
2121
2122 hv_return_t hrc = nemR3DarwinRunGuest(pVM, pVCpu);
2123 if (hrc == HV_SUCCESS)
2124 {
2125 /*
2126 * Deal with the message.
2127 */
2128 rcStrict = nemR3DarwinHandleExit(pVM, pVCpu);
2129 if (rcStrict == VINF_SUCCESS)
2130 { /* hopefully likely */ }
2131 else
2132 {
2133 LogFlow(("NEM/%u: breaking: nemR3DarwinHandleExit -> %Rrc\n", pVCpu->idCpu, VBOXSTRICTRC_VAL(rcStrict) ));
2134 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnStatus);
2135 break;
2136 }
2137 }
2138 else
2139 {
2140 AssertLogRelMsgFailedReturn(("hv_vcpu_run()) failed for CPU #%u: %#x \n",
2141 pVCpu->idCpu, hrc), VERR_NEM_IPE_0);
2142 }
2143 } /* the run loop */
2144
2145 return rcStrict;
2146}
2147
2148
2149VBOXSTRICTRC nemR3NativeRunGC(PVM pVM, PVMCPU pVCpu)
2150{
2151#ifdef LOG_ENABLED
2152 if (LogIs3Enabled())
2153 nemR3DarwinLogState(pVM, pVCpu);
2154#endif
2155
2156 AssertReturn(NEMR3CanExecuteGuest(pVM, pVCpu), VERR_NEM_IPE_9);
2157
2158 if (RT_UNLIKELY(!pVCpu->nem.s.fIdRegsSynced))
2159 {
2160 /*
2161 * Sync the guest ID registers which are per VM once (they are readonly and stay constant during VM lifetime).
2162 * Need to do it here and not during the init because loading a saved state might change the ID registers from what
2163 * done in the call to CPUMR3PopulateFeaturesByIdRegisters().
2164 */
2165 static const struct
2166 {
2167 const char *pszIdReg;
2168 hv_sys_reg_t enmHvReg;
2169 uint32_t offIdStruct;
2170 } s_aSysIdRegs[] =
2171 {
2172#define ID_SYS_REG_CREATE(a_IdReg, a_CpumIdReg) { #a_IdReg, HV_SYS_REG_##a_IdReg, RT_UOFFSETOF(CPUMIDREGS, a_CpumIdReg) }
2173 ID_SYS_REG_CREATE(ID_AA64DFR0_EL1, u64RegIdAa64Dfr0El1),
2174 ID_SYS_REG_CREATE(ID_AA64DFR1_EL1, u64RegIdAa64Dfr1El1),
2175 ID_SYS_REG_CREATE(ID_AA64ISAR0_EL1, u64RegIdAa64Isar0El1),
2176 ID_SYS_REG_CREATE(ID_AA64ISAR1_EL1, u64RegIdAa64Isar1El1),
2177 ID_SYS_REG_CREATE(ID_AA64MMFR0_EL1, u64RegIdAa64Mmfr0El1),
2178 ID_SYS_REG_CREATE(ID_AA64MMFR1_EL1, u64RegIdAa64Mmfr1El1),
2179 ID_SYS_REG_CREATE(ID_AA64MMFR2_EL1, u64RegIdAa64Mmfr2El1),
2180 ID_SYS_REG_CREATE(ID_AA64PFR0_EL1, u64RegIdAa64Pfr0El1),
2181 ID_SYS_REG_CREATE(ID_AA64PFR1_EL1, u64RegIdAa64Pfr1El1),
2182#undef ID_SYS_REG_CREATE
2183 };
2184
2185 PCCPUMIDREGS pIdRegsGst = NULL;
2186 int rc = CPUMR3QueryGuestIdRegs(pVM, &pIdRegsGst);
2187 AssertRCReturn(rc, rc);
2188
2189 for (uint32_t i = 0; i < RT_ELEMENTS(s_aSysIdRegs); i++)
2190 {
2191 uint64_t *pu64 = (uint64_t *)((uint8_t *)pIdRegsGst + s_aSysIdRegs[i].offIdStruct);
2192 hv_return_t hrc = hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, s_aSysIdRegs[i].enmHvReg, *pu64);
2193 if (hrc != HV_SUCCESS)
2194 return VMSetError(pVM, VERR_NEM_SET_REGISTERS_FAILED, RT_SRC_POS,
2195 "Setting %s failed on vCPU %u: %#x (%Rrc)", s_aSysIdRegs[i].pszIdReg, pVCpu->idCpu, hrc, nemR3DarwinHvSts2Rc(hrc));
2196 }
2197
2198 pVCpu->nem.s.fIdRegsSynced = true;
2199 }
2200
2201 /*
2202 * Try switch to NEM runloop state.
2203 */
2204 if (VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED))
2205 { /* likely */ }
2206 else
2207 {
2208 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED);
2209 LogFlow(("NEM/%u: returning immediately because canceled\n", pVCpu->idCpu));
2210 return VINF_SUCCESS;
2211 }
2212
2213 VBOXSTRICTRC rcStrict;
2214#if 0
2215 if ( !pVCpu->nem.s.fUseDebugLoop
2216 && !nemR3DarwinAnyExpensiveProbesEnabled()
2217 && !DBGFIsStepping(pVCpu)
2218 && !pVCpu->CTX_SUFF(pVM)->dbgf.ro.cEnabledInt3Breakpoints)
2219#endif
2220 rcStrict = nemR3DarwinRunGuestNormal(pVM, pVCpu);
2221#if 0
2222 else
2223 rcStrict = nemR3DarwinRunGuestDebug(pVM, pVCpu);
2224#endif
2225
2226 if (rcStrict == VINF_EM_RAW_TO_R3)
2227 rcStrict = VINF_SUCCESS;
2228
2229 /*
2230 * Convert any pending HM events back to TRPM due to premature exits.
2231 *
2232 * This is because execution may continue from IEM and we would need to inject
2233 * the event from there (hence place it back in TRPM).
2234 */
2235 if (pVCpu->nem.s.fEventPending)
2236 {
2237 /** @todo */
2238 }
2239
2240
2241 if (!VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_NEM))
2242 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED);
2243
2244 if (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_ALL))
2245 {
2246 /* Try anticipate what we might need. */
2247 uint64_t fImport = NEM_DARWIN_CPUMCTX_EXTRN_MASK_FOR_IEM;
2248 if ( (rcStrict >= VINF_EM_FIRST && rcStrict <= VINF_EM_LAST)
2249 || RT_FAILURE(rcStrict))
2250 fImport = CPUMCTX_EXTRN_ALL;
2251 else if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_IRQ | VMCPU_FF_INTERRUPT_FIQ
2252 | VMCPU_FF_INTERRUPT_NMI | VMCPU_FF_INTERRUPT_SMI))
2253 fImport |= IEM_CPUMCTX_EXTRN_XCPT_MASK;
2254
2255 if (pVCpu->cpum.GstCtx.fExtrn & fImport)
2256 {
2257 /* Only import what is external currently. */
2258 int rc2 = nemR3DarwinCopyStateFromHv(pVM, pVCpu, fImport);
2259 if (RT_SUCCESS(rc2))
2260 pVCpu->cpum.GstCtx.fExtrn &= ~fImport;
2261 else if (RT_SUCCESS(rcStrict))
2262 rcStrict = rc2;
2263 if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL))
2264 pVCpu->cpum.GstCtx.fExtrn = 0;
2265 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturn);
2266 }
2267 else
2268 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturnSkipped);
2269 }
2270 else
2271 {
2272 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturnSkipped);
2273 pVCpu->cpum.GstCtx.fExtrn = 0;
2274 }
2275
2276 return rcStrict;
2277}
2278
2279
2280VMMR3_INT_DECL(bool) NEMR3CanExecuteGuest(PVM pVM, PVMCPU pVCpu)
2281{
2282 RT_NOREF(pVM, pVCpu);
2283 return true; /** @todo Are there any cases where we have to emulate? */
2284}
2285
2286
2287bool nemR3NativeSetSingleInstruction(PVM pVM, PVMCPU pVCpu, bool fEnable)
2288{
2289 VMCPU_ASSERT_EMT(pVCpu);
2290 bool fOld = pVCpu->nem.s.fSingleInstruction;
2291 pVCpu->nem.s.fSingleInstruction = fEnable;
2292 pVCpu->nem.s.fUseDebugLoop = fEnable || pVM->nem.s.fUseDebugLoop;
2293 return fOld;
2294}
2295
2296
2297void nemR3NativeNotifyFF(PVM pVM, PVMCPU pVCpu, uint32_t fFlags)
2298{
2299 LogFlowFunc(("pVM=%p pVCpu=%p fFlags=%#x\n", pVM, pVCpu, fFlags));
2300
2301 RT_NOREF(pVM, fFlags);
2302
2303 hv_return_t hrc = hv_vcpus_exit(&pVCpu->nem.s.hVCpu, 1);
2304 if (hrc != HV_SUCCESS)
2305 LogRel(("NEM: hv_vcpus_exit(%u, 1) failed with %#x\n", pVCpu->nem.s.hVCpu, hrc));
2306}
2307
2308
2309DECLHIDDEN(bool) nemR3NativeNotifyDebugEventChanged(PVM pVM, bool fUseDebugLoop)
2310{
2311 RT_NOREF(pVM, fUseDebugLoop);
2312 //AssertReleaseFailed();
2313 return false;
2314}
2315
2316
2317DECLHIDDEN(bool) nemR3NativeNotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu, bool fUseDebugLoop)
2318{
2319 RT_NOREF(pVM, pVCpu, fUseDebugLoop);
2320 return fUseDebugLoop;
2321}
2322
2323
2324VMMR3_INT_DECL(int) NEMR3NotifyPhysRamRegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvR3,
2325 uint8_t *pu2State, uint32_t *puNemRange)
2326{
2327 RT_NOREF(pVM, puNemRange);
2328
2329 Log5(("NEMR3NotifyPhysRamRegister: %RGp LB %RGp, pvR3=%p\n", GCPhys, cb, pvR3));
2330#if defined(VBOX_WITH_PGM_NEM_MODE)
2331 if (pvR3)
2332 {
2333 int rc = nemR3DarwinMap(pVM, GCPhys, pvR3, cb, NEM_PAGE_PROT_READ | NEM_PAGE_PROT_WRITE | NEM_PAGE_PROT_EXECUTE, pu2State);
2334 if (RT_FAILURE(rc))
2335 {
2336 LogRel(("NEMR3NotifyPhysRamRegister: GCPhys=%RGp LB %RGp pvR3=%p rc=%Rrc\n", GCPhys, cb, pvR3, rc));
2337 return VERR_NEM_MAP_PAGES_FAILED;
2338 }
2339 }
2340 return VINF_SUCCESS;
2341#else
2342 RT_NOREF(pVM, GCPhys, cb, pvR3);
2343 return VERR_NEM_MAP_PAGES_FAILED;
2344#endif
2345}
2346
2347
2348VMMR3_INT_DECL(bool) NEMR3IsMmio2DirtyPageTrackingSupported(PVM pVM)
2349{
2350 RT_NOREF(pVM);
2351 return true;
2352}
2353
2354
2355VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExMapEarly(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags,
2356 void *pvRam, void *pvMmio2, uint8_t *pu2State, uint32_t *puNemRange)
2357{
2358 RT_NOREF(pvRam);
2359
2360 Log5(("NEMR3NotifyPhysMmioExMapEarly: %RGp LB %RGp fFlags=%#x pvRam=%p pvMmio2=%p pu2State=%p (%d)\n",
2361 GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State, *pu2State));
2362
2363#if defined(VBOX_WITH_PGM_NEM_MODE)
2364 /*
2365 * Unmap the RAM we're replacing.
2366 */
2367 if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE)
2368 {
2369 int rc = nemR3DarwinUnmap(pVM, GCPhys, cb, pu2State);
2370 if (RT_SUCCESS(rc))
2371 { /* likely */ }
2372 else if (pvMmio2)
2373 LogRel(("NEMR3NotifyPhysMmioExMapEarly: GCPhys=%RGp LB %RGp fFlags=%#x: Unmap -> rc=%Rc(ignored)\n",
2374 GCPhys, cb, fFlags, rc));
2375 else
2376 {
2377 LogRel(("NEMR3NotifyPhysMmioExMapEarly: GCPhys=%RGp LB %RGp fFlags=%#x: Unmap -> rc=%Rrc\n",
2378 GCPhys, cb, fFlags, rc));
2379 return VERR_NEM_UNMAP_PAGES_FAILED;
2380 }
2381 }
2382
2383 /*
2384 * Map MMIO2 if any.
2385 */
2386 if (pvMmio2)
2387 {
2388 Assert(fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2);
2389
2390 /* We need to set up our own dirty tracking due to Hypervisor.framework only working on host page sized aligned regions. */
2391 uint32_t fProt = NEM_PAGE_PROT_READ | NEM_PAGE_PROT_EXECUTE;
2392 if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_TRACK_DIRTY_PAGES)
2393 {
2394 /* Find a slot for dirty tracking. */
2395 PNEMHVMMIO2REGION pMmio2Region = NULL;
2396 uint32_t idSlot;
2397 for (idSlot = 0; idSlot < RT_ELEMENTS(pVM->nem.s.aMmio2DirtyTracking); idSlot++)
2398 {
2399 if ( pVM->nem.s.aMmio2DirtyTracking[idSlot].GCPhysStart == 0
2400 && pVM->nem.s.aMmio2DirtyTracking[idSlot].GCPhysLast == 0)
2401 {
2402 pMmio2Region = &pVM->nem.s.aMmio2DirtyTracking[idSlot];
2403 break;
2404 }
2405 }
2406
2407 if (!pMmio2Region)
2408 {
2409 LogRel(("NEMR3NotifyPhysMmioExMapEarly: Out of dirty tracking structures -> VERR_NEM_MAP_PAGES_FAILED\n"));
2410 return VERR_NEM_MAP_PAGES_FAILED;
2411 }
2412
2413 pMmio2Region->GCPhysStart = GCPhys;
2414 pMmio2Region->GCPhysLast = GCPhys + cb - 1;
2415 pMmio2Region->fDirty = false;
2416 *puNemRange = idSlot;
2417 }
2418 else
2419 fProt |= NEM_PAGE_PROT_WRITE;
2420
2421 int rc = nemR3DarwinMap(pVM, GCPhys, pvMmio2, cb, fProt, pu2State);
2422 if (RT_FAILURE(rc))
2423 {
2424 LogRel(("NEMR3NotifyPhysMmioExMapEarly: GCPhys=%RGp LB %RGp fFlags=%#x pvMmio2=%p: Map -> rc=%Rrc\n",
2425 GCPhys, cb, fFlags, pvMmio2, rc));
2426 return VERR_NEM_MAP_PAGES_FAILED;
2427 }
2428 }
2429 else
2430 Assert(!(fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2));
2431
2432#else
2433 RT_NOREF(pVM, GCPhys, cb, pvRam, pvMmio2);
2434 *pu2State = (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE) ? UINT8_MAX : NEM_DARWIN_PAGE_STATE_UNMAPPED;
2435#endif
2436 return VINF_SUCCESS;
2437}
2438
2439
2440VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExMapLate(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags,
2441 void *pvRam, void *pvMmio2, uint32_t *puNemRange)
2442{
2443 RT_NOREF(pVM, GCPhys, cb, fFlags, pvRam, pvMmio2, puNemRange);
2444 return VINF_SUCCESS;
2445}
2446
2447
2448VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExUnmap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags, void *pvRam,
2449 void *pvMmio2, uint8_t *pu2State, uint32_t *puNemRange)
2450{
2451 RT_NOREF(pVM, puNemRange);
2452
2453 Log5(("NEMR3NotifyPhysMmioExUnmap: %RGp LB %RGp fFlags=%#x pvRam=%p pvMmio2=%p pu2State=%p uNemRange=%#x (%#x)\n",
2454 GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State, puNemRange, *puNemRange));
2455
2456 int rc = VINF_SUCCESS;
2457#if defined(VBOX_WITH_PGM_NEM_MODE)
2458 /*
2459 * Unmap the MMIO2 pages.
2460 */
2461 /** @todo If we implement aliasing (MMIO2 page aliased into MMIO range),
2462 * we may have more stuff to unmap even in case of pure MMIO... */
2463 if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2)
2464 {
2465 rc = nemR3DarwinUnmap(pVM, GCPhys, cb, pu2State);
2466 if (RT_FAILURE(rc))
2467 {
2468 LogRel2(("NEMR3NotifyPhysMmioExUnmap: GCPhys=%RGp LB %RGp fFlags=%#x: Unmap -> rc=%Rrc\n",
2469 GCPhys, cb, fFlags, rc));
2470 rc = VERR_NEM_UNMAP_PAGES_FAILED;
2471 }
2472
2473 if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_TRACK_DIRTY_PAGES)
2474 {
2475 /* Reset tracking structure. */
2476 uint32_t idSlot = *puNemRange;
2477 *puNemRange = UINT32_MAX;
2478
2479 Assert(idSlot < RT_ELEMENTS(pVM->nem.s.aMmio2DirtyTracking));
2480 pVM->nem.s.aMmio2DirtyTracking[idSlot].GCPhysStart = 0;
2481 pVM->nem.s.aMmio2DirtyTracking[idSlot].GCPhysLast = 0;
2482 pVM->nem.s.aMmio2DirtyTracking[idSlot].fDirty = false;
2483 }
2484 }
2485
2486 /* Ensure the page is masked as unmapped if relevant. */
2487 Assert(!pu2State || *pu2State == NEM_DARWIN_PAGE_STATE_UNMAPPED);
2488
2489 /*
2490 * Restore the RAM we replaced.
2491 */
2492 if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE)
2493 {
2494 AssertPtr(pvRam);
2495 rc = nemR3DarwinMap(pVM, GCPhys, pvRam, cb, NEM_PAGE_PROT_READ | NEM_PAGE_PROT_WRITE | NEM_PAGE_PROT_EXECUTE, pu2State);
2496 if (RT_SUCCESS(rc))
2497 { /* likely */ }
2498 else
2499 {
2500 LogRel(("NEMR3NotifyPhysMmioExUnmap: GCPhys=%RGp LB %RGp pvMmio2=%p rc=%Rrc\n", GCPhys, cb, pvMmio2, rc));
2501 rc = VERR_NEM_MAP_PAGES_FAILED;
2502 }
2503 }
2504
2505 RT_NOREF(pvMmio2);
2506#else
2507 RT_NOREF(pVM, GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State);
2508 if (pu2State)
2509 *pu2State = UINT8_MAX;
2510 rc = VERR_NEM_UNMAP_PAGES_FAILED;
2511#endif
2512 return rc;
2513}
2514
2515
2516VMMR3_INT_DECL(int) NEMR3PhysMmio2QueryAndResetDirtyBitmap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t uNemRange,
2517 void *pvBitmap, size_t cbBitmap)
2518{
2519 LogFlowFunc(("NEMR3PhysMmio2QueryAndResetDirtyBitmap: %RGp LB %RGp UnemRange=%u\n", GCPhys, cb, uNemRange));
2520 Assert(uNemRange < RT_ELEMENTS(pVM->nem.s.aMmio2DirtyTracking));
2521
2522 /* Keep it simple for now and mark everything as dirty if it is. */
2523 int rc = VINF_SUCCESS;
2524 if (pVM->nem.s.aMmio2DirtyTracking[uNemRange].fDirty)
2525 {
2526 ASMBitSetRange(pvBitmap, 0, cbBitmap * 8);
2527
2528 pVM->nem.s.aMmio2DirtyTracking[uNemRange].fDirty = false;
2529 /* Restore as RX only. */
2530 uint8_t u2State;
2531 rc = nemR3DarwinProtect(GCPhys, cb, NEM_PAGE_PROT_READ | NEM_PAGE_PROT_EXECUTE, &u2State);
2532 }
2533 else
2534 ASMBitClearRange(pvBitmap, 0, cbBitmap * 8);
2535
2536 return rc;
2537}
2538
2539
2540VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterEarly(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvPages, uint32_t fFlags,
2541 uint8_t *pu2State, uint32_t *puNemRange)
2542{
2543 RT_NOREF(pVM, GCPhys, cb, pvPages, fFlags, puNemRange);
2544
2545 Log5(("NEMR3NotifyPhysRomRegisterEarly: %RGp LB %RGp pvPages=%p fFlags=%#x\n", GCPhys, cb, pvPages, fFlags));
2546 *pu2State = UINT8_MAX;
2547 *puNemRange = 0;
2548 return VINF_SUCCESS;
2549}
2550
2551
2552VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterLate(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvPages,
2553 uint32_t fFlags, uint8_t *pu2State, uint32_t *puNemRange)
2554{
2555 Log5(("NEMR3NotifyPhysRomRegisterLate: %RGp LB %RGp pvPages=%p fFlags=%#x pu2State=%p (%d) puNemRange=%p (%#x)\n",
2556 GCPhys, cb, pvPages, fFlags, pu2State, *pu2State, puNemRange, *puNemRange));
2557 *pu2State = UINT8_MAX;
2558
2559#if defined(VBOX_WITH_PGM_NEM_MODE)
2560 /*
2561 * (Re-)map readonly.
2562 */
2563 AssertPtrReturn(pvPages, VERR_INVALID_POINTER);
2564
2565 int rc = nemR3DarwinUnmap(pVM, GCPhys, cb, pu2State);
2566 AssertRC(rc);
2567
2568 rc = nemR3DarwinMap(pVM, GCPhys, pvPages, cb, NEM_PAGE_PROT_READ | NEM_PAGE_PROT_EXECUTE, pu2State);
2569 if (RT_FAILURE(rc))
2570 {
2571 LogRel(("nemR3NativeNotifyPhysRomRegisterLate: GCPhys=%RGp LB %RGp pvPages=%p fFlags=%#x rc=%Rrc\n",
2572 GCPhys, cb, pvPages, fFlags, rc));
2573 return VERR_NEM_MAP_PAGES_FAILED;
2574 }
2575 RT_NOREF(fFlags, puNemRange);
2576 return VINF_SUCCESS;
2577#else
2578 RT_NOREF(pVM, GCPhys, cb, pvPages, fFlags, puNemRange);
2579 return VERR_NEM_MAP_PAGES_FAILED;
2580#endif
2581}
2582
2583
2584VMM_INT_DECL(void) NEMHCNotifyHandlerPhysicalDeregister(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb,
2585 RTR3PTR pvMemR3, uint8_t *pu2State)
2586{
2587 Log5(("NEMHCNotifyHandlerPhysicalDeregister: %RGp LB %RGp enmKind=%d pvMemR3=%p pu2State=%p (%d)\n",
2588 GCPhys, cb, enmKind, pvMemR3, pu2State, *pu2State));
2589
2590 *pu2State = UINT8_MAX;
2591#if defined(VBOX_WITH_PGM_NEM_MODE)
2592 if (pvMemR3)
2593 {
2594 /* Unregister what was there before. */
2595 int rc = nemR3DarwinUnmap(pVM, GCPhys, cb, pu2State);
2596 AssertRC(rc);
2597
2598 rc = nemR3DarwinMap(pVM, GCPhys, pvMemR3, cb, NEM_PAGE_PROT_READ | NEM_PAGE_PROT_WRITE | NEM_PAGE_PROT_EXECUTE, pu2State);
2599 AssertLogRelMsgRC(rc, ("NEMHCNotifyHandlerPhysicalDeregister: nemR3DarwinMap(,%p,%RGp,%RGp,) -> %Rrc\n",
2600 pvMemR3, GCPhys, cb, rc));
2601 }
2602 RT_NOREF(enmKind);
2603#else
2604 RT_NOREF(pVM, enmKind, GCPhys, cb, pvMemR3);
2605 AssertFailed();
2606#endif
2607}
2608
2609
2610VMMR3_INT_DECL(void) NEMR3NotifySetA20(PVMCPU pVCpu, bool fEnabled)
2611{
2612 Log(("NEMR3NotifySetA20: fEnabled=%RTbool\n", fEnabled));
2613 RT_NOREF(pVCpu, fEnabled);
2614}
2615
2616
2617void nemHCNativeNotifyHandlerPhysicalRegister(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb)
2618{
2619 Log5(("nemHCNativeNotifyHandlerPhysicalRegister: %RGp LB %RGp enmKind=%d\n", GCPhys, cb, enmKind));
2620 NOREF(pVM); NOREF(enmKind); NOREF(GCPhys); NOREF(cb);
2621}
2622
2623
2624void nemHCNativeNotifyHandlerPhysicalModify(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhysOld,
2625 RTGCPHYS GCPhysNew, RTGCPHYS cb, bool fRestoreAsRAM)
2626{
2627 Log5(("nemHCNativeNotifyHandlerPhysicalModify: %RGp LB %RGp -> %RGp enmKind=%d fRestoreAsRAM=%d\n",
2628 GCPhysOld, cb, GCPhysNew, enmKind, fRestoreAsRAM));
2629 NOREF(pVM); NOREF(enmKind); NOREF(GCPhysOld); NOREF(GCPhysNew); NOREF(cb); NOREF(fRestoreAsRAM);
2630}
2631
2632
2633int nemHCNativeNotifyPhysPageAllocated(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhys, uint32_t fPageProt,
2634 PGMPAGETYPE enmType, uint8_t *pu2State)
2635{
2636 Log5(("nemHCNativeNotifyPhysPageAllocated: %RGp HCPhys=%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
2637 GCPhys, HCPhys, fPageProt, enmType, *pu2State));
2638 RT_NOREF(pVM, GCPhys, HCPhys, fPageProt, enmType, pu2State);
2639
2640 AssertFailed();
2641 return VINF_SUCCESS;
2642}
2643
2644
2645VMM_INT_DECL(void) NEMHCNotifyPhysPageProtChanged(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhys, RTR3PTR pvR3, uint32_t fPageProt,
2646 PGMPAGETYPE enmType, uint8_t *pu2State)
2647{
2648 Log5(("NEMHCNotifyPhysPageProtChanged: %RGp HCPhys=%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
2649 GCPhys, HCPhys, fPageProt, enmType, *pu2State));
2650 RT_NOREF(pVM, GCPhys, HCPhys, pvR3, fPageProt, enmType, pu2State);
2651}
2652
2653
2654VMM_INT_DECL(void) NEMHCNotifyPhysPageChanged(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhysPrev, RTHCPHYS HCPhysNew,
2655 RTR3PTR pvNewR3, uint32_t fPageProt, PGMPAGETYPE enmType, uint8_t *pu2State)
2656{
2657 Log5(("NEMHCNotifyPhysPageChanged: %RGp HCPhys=%RHp->%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
2658 GCPhys, HCPhysPrev, HCPhysNew, fPageProt, enmType, *pu2State));
2659 RT_NOREF(pVM, GCPhys, HCPhysPrev, HCPhysNew, pvNewR3, fPageProt, enmType, pu2State);
2660
2661 AssertFailed();
2662}
2663
2664
2665/**
2666 * Interface for importing state on demand (used by IEM).
2667 *
2668 * @returns VBox status code.
2669 * @param pVCpu The cross context CPU structure.
2670 * @param fWhat What to import, CPUMCTX_EXTRN_XXX.
2671 */
2672VMM_INT_DECL(int) NEMImportStateOnDemand(PVMCPUCC pVCpu, uint64_t fWhat)
2673{
2674 LogFlowFunc(("pVCpu=%p fWhat=%RX64\n", pVCpu, fWhat));
2675 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnDemand);
2676
2677 return nemR3DarwinCopyStateFromHv(pVCpu->pVMR3, pVCpu, fWhat);
2678}
2679
2680
2681/**
2682 * Query the CPU tick counter and optionally the TSC_AUX MSR value.
2683 *
2684 * @returns VBox status code.
2685 * @param pVCpu The cross context CPU structure.
2686 * @param pcTicks Where to return the CPU tick count.
2687 * @param puAux Where to return the TSC_AUX register value.
2688 */
2689VMM_INT_DECL(int) NEMHCQueryCpuTick(PVMCPUCC pVCpu, uint64_t *pcTicks, uint32_t *puAux)
2690{
2691 LogFlowFunc(("pVCpu=%p pcTicks=%RX64 puAux=%RX32\n", pVCpu, pcTicks, puAux));
2692 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatQueryCpuTick);
2693
2694 if (puAux)
2695 *puAux = 0;
2696 *pcTicks = mach_absolute_time() - pVCpu->pVMR3->nem.s.u64VTimerOff; /* This is the host timer minus the offset. */
2697 return VINF_SUCCESS;
2698}
2699
2700
2701/**
2702 * Resumes CPU clock (TSC) on all virtual CPUs.
2703 *
2704 * This is called by TM when the VM is started, restored, resumed or similar.
2705 *
2706 * @returns VBox status code.
2707 * @param pVM The cross context VM structure.
2708 * @param pVCpu The cross context CPU structure of the calling EMT.
2709 * @param uPausedTscValue The TSC value at the time of pausing.
2710 */
2711VMM_INT_DECL(int) NEMHCResumeCpuTickOnAll(PVMCC pVM, PVMCPUCC pVCpu, uint64_t uPausedTscValue)
2712{
2713 LogFlowFunc(("pVM=%p pVCpu=%p uPausedTscValue=%RX64\n", pVM, pVCpu, uPausedTscValue));
2714 VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_VM_THREAD_NOT_EMT);
2715 AssertReturn(VM_IS_NEM_ENABLED(pVM), VERR_NEM_IPE_9);
2716
2717 /*
2718 * Calculate the new offset, first get the new TSC value with the old vTimer offset and then adjust the
2719 * the new offset to let the guest not notice the pause.
2720 */
2721 uint64_t u64TscNew = mach_absolute_time() - pVCpu->pVMR3->nem.s.u64VTimerOff;
2722 Assert(u64TscNew >= uPausedTscValue);
2723 LogFlowFunc(("u64VTimerOffOld=%#RX64 u64TscNew=%#RX64 u64VTimerValuePaused=%#RX64 -> u64VTimerOff=%#RX64\n",
2724 pVM->nem.s.u64VTimerOff, u64TscNew, uPausedTscValue,
2725 pVM->nem.s.u64VTimerOff + (u64TscNew - uPausedTscValue)));
2726
2727 pVM->nem.s.u64VTimerOff += u64TscNew - uPausedTscValue;
2728
2729 /*
2730 * Set the flag to update the vTimer offset when the vCPU resumes for the first time
2731 * (needs to be done on the actual EMT).
2732 */
2733 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2734 {
2735 PVMCPUCC pVCpuDst = pVM->apCpusR3[idCpu];
2736 pVCpuDst->nem.s.fVTimerOffUpdate = true;
2737 }
2738
2739 return VINF_SUCCESS;
2740}
2741
2742
2743/**
2744 * Returns features supported by the NEM backend.
2745 *
2746 * @returns Flags of features supported by the native NEM backend.
2747 * @param pVM The cross context VM structure.
2748 */
2749VMM_INT_DECL(uint32_t) NEMHCGetFeatures(PVMCC pVM)
2750{
2751 RT_NOREF(pVM);
2752 /*
2753 * Apple's Hypervisor.framework is not supported if the CPU doesn't support nested paging
2754 * and unrestricted guest execution support so we can safely return these flags here always.
2755 */
2756 return NEM_FEAT_F_NESTED_PAGING | NEM_FEAT_F_FULL_GST_EXEC | NEM_FEAT_F_XSAVE_XRSTOR;
2757}
2758
2759
2760/** @page pg_nem_darwin NEM/darwin - Native Execution Manager, macOS.
2761 *
2762 * @todo Add notes as the implementation progresses...
2763 */
2764
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