VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/HWACCM.cpp@ 41985

最後變更 在這個檔案從41985是 41965,由 vboxsync 提交於 13 年 前

VMM: ran scm. Mostly svn:keywords changes (adding Revision).
  • 屬性 svn:eol-style 設為 native
  • 屬性 svn:keywords 設為 Id Revision
檔案大小: 136.3 KB
行 
1/* $Id: HWACCM.cpp 41965 2012-06-29 02:52:49Z vboxsync $ */
2/** @file
3 * HWACCM - Intel/AMD VM Hardware Support Manager
4 */
5
6/*
7 * Copyright (C) 2006-2012 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.alldomusa.eu.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_HWACCM
22#include <VBox/vmm/cpum.h>
23#include <VBox/vmm/stam.h>
24#include <VBox/vmm/mm.h>
25#include <VBox/vmm/pdmapi.h>
26#include <VBox/vmm/pgm.h>
27#include <VBox/vmm/ssm.h>
28#include <VBox/vmm/trpm.h>
29#include <VBox/vmm/dbgf.h>
30#include <VBox/vmm/iom.h>
31#include <VBox/vmm/patm.h>
32#include <VBox/vmm/csam.h>
33#include <VBox/vmm/selm.h>
34#ifdef VBOX_WITH_REM
35# include <VBox/vmm/rem.h>
36#endif
37#include <VBox/vmm/hwacc_vmx.h>
38#include <VBox/vmm/hwacc_svm.h>
39#include "HWACCMInternal.h"
40#include <VBox/vmm/vm.h>
41#include <VBox/err.h>
42#include <VBox/param.h>
43
44#include <iprt/assert.h>
45#include <VBox/log.h>
46#include <iprt/asm.h>
47#include <iprt/asm-amd64-x86.h>
48#include <iprt/string.h>
49#include <iprt/env.h>
50#include <iprt/thread.h>
51
52/*******************************************************************************
53* Global Variables *
54*******************************************************************************/
55#ifdef VBOX_WITH_STATISTICS
56# define EXIT_REASON(def, val, str) #def " - " #val " - " str
57# define EXIT_REASON_NIL() NULL
58/** Exit reason descriptions for VT-x, used to describe statistics. */
59static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
60{
61 EXIT_REASON(VMX_EXIT_EXCEPTION , 0, "Exception or non-maskable interrupt (NMI)."),
62 EXIT_REASON(VMX_EXIT_EXTERNAL_IRQ , 1, "External interrupt."),
63 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
64 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
65 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
66 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
67 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
68 EXIT_REASON(VMX_EXIT_IRQ_WINDOW , 7, "Interrupt window."),
69 EXIT_REASON_NIL(),
70 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
71 EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest software attempted to execute CPUID."),
72 EXIT_REASON_NIL(),
73 EXIT_REASON(VMX_EXIT_HLT , 12, "Guest software attempted to execute HLT."),
74 EXIT_REASON(VMX_EXIT_INVD , 13, "Guest software attempted to execute INVD."),
75 EXIT_REASON(VMX_EXIT_INVPG , 14, "Guest software attempted to execute INVPG."),
76 EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest software attempted to execute RDPMC."),
77 EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest software attempted to execute RDTSC."),
78 EXIT_REASON(VMX_EXIT_RSM , 17, "Guest software attempted to execute RSM in SMM."),
79 EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest software executed VMCALL."),
80 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest software executed VMCLEAR."),
81 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest software executed VMLAUNCH."),
82 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest software executed VMPTRLD."),
83 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest software executed VMPTRST."),
84 EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest software executed VMREAD."),
85 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest software executed VMRESUME."),
86 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest software executed VMWRITE."),
87 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest software executed VMXOFF."),
88 EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest software executed VMXON."),
89 EXIT_REASON(VMX_EXIT_CRX_MOVE , 28, "Control-register accesses."),
90 EXIT_REASON(VMX_EXIT_DRX_MOVE , 29, "Debug-register accesses."),
91 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
92 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR. Guest software attempted to execute RDMSR."),
93 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR. Guest software attempted to execute WRMSR."),
94 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
95 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
96 EXIT_REASON_NIL(),
97 EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest software executed MWAIT."),
98 EXIT_REASON(VMX_EXIT_MTF , 37, "Monitor Trap Flag."),
99 EXIT_REASON_NIL(),
100 EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest software attempted to execute MONITOR."),
101 EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest software attempted to execute PAUSE."),
102 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
103 EXIT_REASON_NIL(),
104 EXIT_REASON(VMX_EXIT_TPR , 43, "TPR below threshold. Guest software executed MOV to CR8."),
105 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest software attempted to access memory at a physical address on the APIC-access page."),
106 EXIT_REASON_NIL(),
107 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT."),
108 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR."),
109 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
110 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
111 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT. Guest software attempted to execute INVEPT."),
112 EXIT_REASON_NIL(),
113 EXIT_REASON(VMX_EXIT_PREEMPTION_TIMER , 52, "VMX-preemption timer expired. The preemption timer counted down to zero."),
114 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID. Guest software attempted to execute INVVPID."),
115 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD. Guest software attempted to execute WBINVD."),
116 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV. Guest software attempted to execute XSETBV."),
117 EXIT_REASON_NIL()
118};
119/** Exit reason descriptions for AMD-V, used to describe statistics. */
120static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
121{
122 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
123 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
124 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
125 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
126 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
127 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
128 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
129 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
130 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
131 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
132 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
133 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
134 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
135 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
136 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
137 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
138 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
139 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
140 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
141 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
142 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
143 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
144 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
145 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
146 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
147 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
148 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
149 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
150 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
151 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
152 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
153 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
154 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
155 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
156 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
157 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
158 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
159 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
160 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
161 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
162 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
163 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
164 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
165 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
166 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
167 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
168 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
169 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
170 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
171 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
172 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
173 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
174 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
175 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
176 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
177 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
178 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
179 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
180 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
181 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
182 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
183 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
184 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
185 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
186 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (0x0)."),
187 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (0x1)."),
188 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (0x2)."),
189 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (0x3)."),
190 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (0x4)."),
191 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (0x5)."),
192 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (0x6)."),
193 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (0x7)."),
194 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (0x8)."),
195 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (0x9)."),
196 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (0xA)."),
197 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (0xB)."),
198 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (0xC)."),
199 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (0xD)."),
200 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (0xE)."),
201 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0xF)."),
202 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (0x10)."),
203 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (0x11)."),
204 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (0x12)."),
205 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (0x13)."),
206 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
207 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
208 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
209 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
210 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
211 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
212 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
213 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
214 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
215 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
216 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
217 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
218 EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt."),
219 EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt."),
220 EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt."),
221 EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal."),
222 EXIT_REASON(SVM_EXIT_VINTR ,100, "Virtual interrupt."),
223 EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
224 EXIT_REASON(SVM_EXIT_IDTR_READ ,102, "Read IDTR"),
225 EXIT_REASON(SVM_EXIT_GDTR_READ ,103, "Read GDTR"),
226 EXIT_REASON(SVM_EXIT_LDTR_READ ,104, "Read LDTR."),
227 EXIT_REASON(SVM_EXIT_TR_READ ,105, "Read TR."),
228 EXIT_REASON(SVM_EXIT_TR_READ ,106, "Write IDTR."),
229 EXIT_REASON(SVM_EXIT_TR_READ ,107, "Write GDTR."),
230 EXIT_REASON(SVM_EXIT_TR_READ ,108, "Write LDTR."),
231 EXIT_REASON(SVM_EXIT_TR_READ ,109, "Write TR."),
232 EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
233 EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
234 EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
235 EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
236 EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
237 EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
238 EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
239 EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
240 EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
241 EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
242 EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
243 EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
244 EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
245 EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port (EXITINFO1 field provides more information)."),
246 EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
247 EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
248 EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt"),
249 EXIT_REASON(SVM_EXIT_SHUTDOWN ,127, "Shutdown."),
250 EXIT_REASON(SVM_EXIT_VMRUN ,128, "VMRUN instruction."),
251 EXIT_REASON(SVM_EXIT_VMMCALL ,129, "VMCALL instruction."),
252 EXIT_REASON(SVM_EXIT_VMLOAD ,130, "VMLOAD instruction."),
253 EXIT_REASON(SVM_EXIT_VMSAVE ,131, "VMSAVE instruction."),
254 EXIT_REASON(SVM_EXIT_STGI ,132, "STGI instruction."),
255 EXIT_REASON(SVM_EXIT_CLGI ,133, "CLGI instruction."),
256 EXIT_REASON(SVM_EXIT_SKINIT ,134, "SKINIT instruction."),
257 EXIT_REASON(SVM_EXIT_RDTSCP ,135, "RDTSCP instruction."),
258 EXIT_REASON(SVM_EXIT_ICEBP ,136, "ICEBP instruction."),
259 EXIT_REASON(SVM_EXIT_WBINVD ,137, "WBINVD instruction."),
260 EXIT_REASON(SVM_EXIT_MONITOR ,138, "MONITOR instruction."),
261 EXIT_REASON(SVM_EXIT_MWAIT_UNCOND ,139, "MWAIT instruction unconditional."),
262 EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
263 EXIT_REASON(SVM_EXIT_NPF ,1024, "Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault)."),
264 EXIT_REASON_NIL()
265};
266# undef EXIT_REASON
267# undef EXIT_REASON_NIL
268#endif /* VBOX_WITH_STATISTICS */
269
270/*******************************************************************************
271* Internal Functions *
272*******************************************************************************/
273static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
274static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
275static int hwaccmR3InitCPU(PVM pVM);
276static int hwaccmR3InitFinalizeR0(PVM pVM);
277static int hwaccmR3TermCPU(PVM pVM);
278
279
280/**
281 * Initializes the HWACCM.
282 *
283 * @returns VBox status code.
284 * @param pVM Pointer to the VM.
285 */
286VMMR3DECL(int) HWACCMR3Init(PVM pVM)
287{
288 LogFlow(("HWACCMR3Init\n"));
289
290 /*
291 * Assert alignment and sizes.
292 */
293 AssertCompileMemberAlignment(VM, hwaccm.s, 32);
294 AssertCompile(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
295
296 /* Some structure checks. */
297 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
298 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
299 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
300
301 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
302 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.TR) == 0x490, ("guest.TR offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.TR)));
303 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8CPL) == 0x4CB, ("guest.u8CPL offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8CPL)));
304 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64EFER) == 0x4D0, ("guest.u64EFER offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64EFER)));
305 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64CR4) == 0x548, ("guest.u64CR4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64CR4)));
306 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64RIP) == 0x578, ("guest.u64RIP offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64RIP)));
307 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64RSP) == 0x5D8, ("guest.u64RSP offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64RSP)));
308 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64CR2) == 0x640, ("guest.u64CR2 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64CR2)));
309 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64GPAT) == 0x668, ("guest.u64GPAT offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64GPAT)));
310 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64LASTEXCPTO) == 0x690, ("guest.u64LASTEXCPTO offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64LASTEXCPTO)));
311 AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
312
313
314 /*
315 * Register the saved state data unit.
316 */
317 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
318 NULL, NULL, NULL,
319 NULL, hwaccmR3Save, NULL,
320 NULL, hwaccmR3Load, NULL);
321 if (RT_FAILURE(rc))
322 return rc;
323
324 /* Misc initialisation. */
325 pVM->hwaccm.s.vmx.fSupported = false;
326 pVM->hwaccm.s.svm.fSupported = false;
327 pVM->hwaccm.s.vmx.fEnabled = false;
328 pVM->hwaccm.s.svm.fEnabled = false;
329
330 pVM->hwaccm.s.fNestedPaging = false;
331 pVM->hwaccm.s.fLargePages = false;
332
333 /* Disabled by default. */
334 pVM->fHWACCMEnabled = false;
335
336 /*
337 * Check CFGM options.
338 */
339 PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
340 PCFGMNODE pHWVirtExt = CFGMR3GetChild(pRoot, "HWVirtExt/");
341 /* Nested paging: disabled by default. */
342 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, false);
343 AssertRC(rc);
344
345 /* Large pages: disabled by default. */
346 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableLargePages", &pVM->hwaccm.s.fLargePages, false);
347 AssertRC(rc);
348
349 /* VT-x VPID: disabled by default. */
350 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableVPID", &pVM->hwaccm.s.vmx.fAllowVPID, false);
351 AssertRC(rc);
352
353 /* HWACCM support must be explicitely enabled in the configuration file. */
354 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Enabled", &pVM->hwaccm.s.fAllowed, false);
355 AssertRC(rc);
356
357 /* TPR patching for 32 bits (Windows) guests with IO-APIC: disabled by default. */
358 rc = CFGMR3QueryBoolDef(pHWVirtExt, "TPRPatchingEnabled", &pVM->hwaccm.s.fTRPPatchingAllowed, false);
359 AssertRC(rc);
360
361#ifdef RT_OS_DARWIN
362 if (VMMIsHwVirtExtForced(pVM) != pVM->hwaccm.s.fAllowed)
363#else
364 if (VMMIsHwVirtExtForced(pVM) && !pVM->hwaccm.s.fAllowed)
365#endif
366 {
367 AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
368 VMMIsHwVirtExtForced(pVM), pVM->hwaccm.s.fAllowed));
369 return VERR_HWACCM_CONFIG_MISMATCH;
370 }
371
372 if (VMMIsHwVirtExtForced(pVM))
373 pVM->fHWACCMEnabled = true;
374
375#if HC_ARCH_BITS == 32
376 /*
377 * 64-bit mode is configurable and it depends on both the kernel mode and VT-x.
378 * (To use the default, don't set 64bitEnabled in CFGM.)
379 */
380 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, false);
381 AssertLogRelRCReturn(rc, rc);
382 if (pVM->hwaccm.s.fAllow64BitGuests)
383 {
384# ifdef RT_OS_DARWIN
385 if (!VMMIsHwVirtExtForced(pVM))
386# else
387 if (!pVM->hwaccm.s.fAllowed)
388# endif
389 return VM_SET_ERROR(pVM, VERR_INVALID_PARAMETER, "64-bit guest support was requested without also enabling HWVirtEx (VT-x/AMD-V).");
390 }
391#else
392 /*
393 * On 64-bit hosts 64-bit guest support is enabled by default, but allow this to be overridden
394 * via VBoxInternal/HWVirtExt/64bitEnabled=0. (ConsoleImpl2.cpp doesn't set this to false for 64-bit.)*
395 */
396 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, true);
397 AssertLogRelRCReturn(rc, rc);
398#endif
399
400
401 /*
402 * Determine the init method for AMD-V and VT-x; either one global init for each host CPU
403 * or local init each time we wish to execute guest code.
404 *
405 * Default false for Mac OS X and Windows due to the higher risk of conflicts with other hypervisors.
406 */
407 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Exclusive", &pVM->hwaccm.s.fGlobalInit,
408#if defined(RT_OS_DARWIN) || defined(RT_OS_WINDOWS)
409 false
410#else
411 true
412#endif
413 );
414
415 /* Max number of resume loops. */
416 rc = CFGMR3QueryU32Def(pHWVirtExt, "MaxResumeLoops", &pVM->hwaccm.s.cMaxResumeLoops, 0 /* set by R0 later */);
417 AssertRC(rc);
418
419 return rc;
420}
421
422
423/**
424 * Initializes the per-VCPU HWACCM.
425 *
426 * @returns VBox status code.
427 * @param pVM Pointer to the VM.
428 */
429static int hwaccmR3InitCPU(PVM pVM)
430{
431 LogFlow(("HWACCMR3InitCPU\n"));
432
433 for (VMCPUID i = 0; i < pVM->cCpus; i++)
434 {
435 PVMCPU pVCpu = &pVM->aCpus[i];
436
437 pVCpu->hwaccm.s.fActive = false;
438 }
439
440#ifdef VBOX_WITH_STATISTICS
441 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRPatchSuccess, STAMTYPE_COUNTER, "/HWACCM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
442 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRPatchFailure, STAMTYPE_COUNTER, "/HWACCM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
443 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRReplaceSuccess, STAMTYPE_COUNTER, "/HWACCM/TPR/Replace/Success",STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
444 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRReplaceFailure, STAMTYPE_COUNTER, "/HWACCM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
445
446 /*
447 * Statistics.
448 */
449 for (VMCPUID i = 0; i < pVM->cCpus; i++)
450 {
451 PVMCPU pVCpu = &pVM->aCpus[i];
452 int rc;
453
454 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of RTMpPokeCpu",
455 "/PROF/HWACCM/CPU%d/Poke", i);
456 AssertRC(rc);
457 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of poke wait",
458 "/PROF/HWACCM/CPU%d/PokeWait", i);
459 AssertRC(rc);
460 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of poke wait when RTMpPokeCpu fails",
461 "/PROF/HWACCM/CPU%d/PokeWaitFailed", i);
462 AssertRC(rc);
463 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry",
464 "/PROF/HWACCM/CPU%d/SwitchToGC", i);
465 AssertRC(rc);
466 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 1",
467 "/PROF/HWACCM/CPU%d/SwitchFromGC_1", i);
468 AssertRC(rc);
469 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 2",
470 "/PROF/HWACCM/CPU%d/SwitchFromGC_2", i);
471 AssertRC(rc);
472# if 1 /* temporary for tracking down darwin holdup. */
473 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - I/O",
474 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub1", i);
475 AssertRC(rc);
476 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - CRx RWs",
477 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub2", i);
478 AssertRC(rc);
479 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - Exceptions",
480 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub3", i);
481 AssertRC(rc);
482# endif
483 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch",
484 "/PROF/HWACCM/CPU%d/InGC", i);
485 AssertRC(rc);
486
487# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
488 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher",
489 "/PROF/HWACCM/CPU%d/Switcher3264", i);
490 AssertRC(rc);
491# endif
492
493# define HWACCM_REG_COUNTER(a, b) \
494 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
495 AssertRC(rc);
496
497 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowNM, "/HWACCM/CPU%d/Exit/Trap/Shw/#NM");
498 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNM, "/HWACCM/CPU%d/Exit/Trap/Gst/#NM");
499 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowPF, "/HWACCM/CPU%d/Exit/Trap/Shw/#PF");
500 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowPFEM, "/HWACCM/CPU%d/Exit/Trap/Shw/#PF-EM");
501 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestPF, "/HWACCM/CPU%d/Exit/Trap/Gst/#PF");
502 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestUD, "/HWACCM/CPU%d/Exit/Trap/Gst/#UD");
503 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestSS, "/HWACCM/CPU%d/Exit/Trap/Gst/#SS");
504 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNP, "/HWACCM/CPU%d/Exit/Trap/Gst/#NP");
505 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestGP, "/HWACCM/CPU%d/Exit/Trap/Gst/#GP");
506 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestMF, "/HWACCM/CPU%d/Exit/Trap/Gst/#MF");
507 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDE, "/HWACCM/CPU%d/Exit/Trap/Gst/#DE");
508 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDB, "/HWACCM/CPU%d/Exit/Trap/Gst/#DB");
509 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestBP, "/HWACCM/CPU%d/Exit/Trap/Gst/#BP");
510 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestXF, "/HWACCM/CPU%d/Exit/Trap/Gst/#XF");
511 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestXcpUnk, "/HWACCM/CPU%d/Exit/Trap/Gst/Other");
512 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvpg, "/HWACCM/CPU%d/Exit/Instr/Invlpg");
513 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvd, "/HWACCM/CPU%d/Exit/Instr/Invd");
514 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCpuid, "/HWACCM/CPU%d/Exit/Instr/Cpuid");
515 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdtsc, "/HWACCM/CPU%d/Exit/Instr/Rdtsc");
516 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdpmc, "/HWACCM/CPU%d/Exit/Instr/Rdpmc");
517 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdmsr, "/HWACCM/CPU%d/Exit/Instr/Rdmsr");
518 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitWrmsr, "/HWACCM/CPU%d/Exit/Instr/Wrmsr");
519 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMwait, "/HWACCM/CPU%d/Exit/Instr/Mwait");
520 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMonitor, "/HWACCM/CPU%d/Exit/Instr/Monitor");
521 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxWrite, "/HWACCM/CPU%d/Exit/Instr/DR/Write");
522 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxRead, "/HWACCM/CPU%d/Exit/Instr/DR/Read");
523 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCLTS, "/HWACCM/CPU%d/Exit/Instr/CLTS");
524 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitLMSW, "/HWACCM/CPU%d/Exit/Instr/LMSW");
525 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCli, "/HWACCM/CPU%d/Exit/Instr/Cli");
526 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitSti, "/HWACCM/CPU%d/Exit/Instr/Sti");
527 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPushf, "/HWACCM/CPU%d/Exit/Instr/Pushf");
528 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPopf, "/HWACCM/CPU%d/Exit/Instr/Popf");
529 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIret, "/HWACCM/CPU%d/Exit/Instr/Iret");
530 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInt, "/HWACCM/CPU%d/Exit/Instr/Int");
531 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitHlt, "/HWACCM/CPU%d/Exit/Instr/Hlt");
532 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOWrite, "/HWACCM/CPU%d/Exit/IO/Write");
533 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIORead, "/HWACCM/CPU%d/Exit/IO/Read");
534 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringWrite, "/HWACCM/CPU%d/Exit/IO/WriteString");
535 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringRead, "/HWACCM/CPU%d/Exit/IO/ReadString");
536 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIrqWindow, "/HWACCM/CPU%d/Exit/IrqWindow");
537 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMaxResume, "/HWACCM/CPU%d/Exit/MaxResume");
538 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPreemptPending, "/HWACCM/CPU%d/Exit/PreemptPending");
539 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMTF, "/HWACCM/CPU%d/Exit/MonitorTrapFlag");
540
541 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchGuestIrq, "/HWACCM/CPU%d/Switch/IrqPending");
542 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchToR3, "/HWACCM/CPU%d/Switch/ToR3");
543
544 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntInject, "/HWACCM/CPU%d/Irq/Inject");
545 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntReinject, "/HWACCM/CPU%d/Irq/Reinject");
546 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatPendingHostIrq, "/HWACCM/CPU%d/Irq/PendingOnHost");
547
548 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPage, "/HWACCM/CPU%d/Flush/Page");
549 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageManual, "/HWACCM/CPU%d/Flush/Page/Virt");
550 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPhysPageManual, "/HWACCM/CPU%d/Flush/Page/Phys");
551 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLB, "/HWACCM/CPU%d/Flush/TLB");
552 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBManual, "/HWACCM/CPU%d/Flush/TLB/Manual");
553 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBCRxChange, "/HWACCM/CPU%d/Flush/TLB/CRx");
554 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageInvlpg, "/HWACCM/CPU%d/Flush/Page/Invlpg");
555 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Switch");
556 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Skipped");
557 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushASID, "/HWACCM/CPU%d/Flush/TLB/ASID");
558 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBInvlpga, "/HWACCM/CPU%d/Flush/TLB/PhysInvl");
559 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdown, "/HWACCM/CPU%d/Flush/Shootdown/Page");
560 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdownFlush, "/HWACCM/CPU%d/Flush/Shootdown/TLB");
561
562 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCOffset, "/HWACCM/CPU%d/TSC/Offset");
563 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCIntercept, "/HWACCM/CPU%d/TSC/Intercept");
564 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCInterceptOverFlow, "/HWACCM/CPU%d/TSC/InterceptOverflow");
565
566 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxArmed, "/HWACCM/CPU%d/Debug/Armed");
567 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxContextSwitch, "/HWACCM/CPU%d/Debug/ContextSwitch");
568 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxIOCheck, "/HWACCM/CPU%d/Debug/IOCheck");
569
570 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatLoadMinimal, "/HWACCM/CPU%d/Load/Minimal");
571 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatLoadFull, "/HWACCM/CPU%d/Load/Full");
572
573#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
574 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFpu64SwitchBack, "/HWACCM/CPU%d/Switch64/Fpu");
575 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDebug64SwitchBack, "/HWACCM/CPU%d/Switch64/Debug");
576#endif
577
578 for (unsigned j = 0; j < RT_ELEMENTS(pVCpu->hwaccm.s.StatExitCRxWrite); j++)
579 {
580 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx writes",
581 "/HWACCM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
582 AssertRC(rc);
583 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx reads",
584 "/HWACCM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
585 AssertRC(rc);
586 }
587
588#undef HWACCM_REG_COUNTER
589
590 pVCpu->hwaccm.s.paStatExitReason = NULL;
591
592 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hwaccm.s.paStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatExitReason);
593 AssertRC(rc);
594 if (RT_SUCCESS(rc))
595 {
596 const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
597 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
598 {
599 if (papszDesc[j])
600 {
601 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
602 papszDesc[j], "/HWACCM/CPU%d/Exit/Reason/%02x", i, j);
603 AssertRC(rc);
604 }
605 }
606 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Nested page fault", "/HWACCM/CPU%d/Exit/Reason/#NPF", i);
607 AssertRC(rc);
608 }
609 pVCpu->hwaccm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatExitReason);
610# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
611 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
612# else
613 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR);
614# endif
615
616 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatInjectedIrqs);
617 AssertRCReturn(rc, rc);
618 pVCpu->hwaccm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatInjectedIrqs);
619# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
620 Assert(pVCpu->hwaccm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
621# else
622 Assert(pVCpu->hwaccm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
623# endif
624 for (unsigned j = 0; j < 255; j++)
625 STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Forwarded interrupts.",
626 (j < 0x20) ? "/HWACCM/CPU%d/Interrupt/Trap/%02X" : "/HWACCM/CPU%d/Interrupt/IRQ/%02X", i, j);
627
628 }
629#endif /* VBOX_WITH_STATISTICS */
630
631#ifdef VBOX_WITH_CRASHDUMP_MAGIC
632 /* Magic marker for searching in crash dumps. */
633 for (VMCPUID i = 0; i < pVM->cCpus; i++)
634 {
635 PVMCPU pVCpu = &pVM->aCpus[i];
636
637 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
638 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
639 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
640 }
641#endif
642 return VINF_SUCCESS;
643}
644
645
646/**
647 * Called when a init phase has completed.
648 *
649 * @returns VBox status code.
650 * @param pVM The VM.
651 * @param enmWhat The phase that completed.
652 */
653VMMR3_INT_DECL(int) HWACCMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
654{
655 switch (enmWhat)
656 {
657 case VMINITCOMPLETED_RING3:
658 return hwaccmR3InitCPU(pVM);
659 case VMINITCOMPLETED_RING0:
660 return hwaccmR3InitFinalizeR0(pVM);
661 default:
662 return VINF_SUCCESS;
663 }
664}
665
666
667/**
668 * Turns off normal raw mode features.
669 *
670 * @param pVM Pointer to the VM.
671 */
672static void hwaccmR3DisableRawMode(PVM pVM)
673{
674 /* Disable PATM & CSAM. */
675 PATMR3AllowPatching(pVM, false);
676 CSAMDisableScanning(pVM);
677
678 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
679 SELMR3DisableMonitoring(pVM);
680 TRPMR3DisableMonitoring(pVM);
681
682 /* Disable the switcher code (safety precaution). */
683 VMMR3DisableSwitcher(pVM);
684
685 /* Disable mapping of the hypervisor into the shadow page table. */
686 PGMR3MappingsDisable(pVM);
687
688 /* Disable the switcher */
689 VMMR3DisableSwitcher(pVM);
690
691 /* Reinit the paging mode to force the new shadow mode. */
692 for (VMCPUID i = 0; i < pVM->cCpus; i++)
693 {
694 PVMCPU pVCpu = &pVM->aCpus[i];
695
696 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
697 }
698}
699
700
701/**
702 * Initialize VT-x or AMD-V.
703 *
704 * @returns VBox status code.
705 * @param pVM Pointer to the VM.
706 */
707static int hwaccmR3InitFinalizeR0(PVM pVM)
708{
709 int rc;
710
711 /*
712 * Hack to allow users to work around broken BIOSes that incorrectly set EFER.SVME, which makes us believe somebody else
713 * is already using AMD-V.
714 */
715 if ( !pVM->hwaccm.s.vmx.fSupported
716 && !pVM->hwaccm.s.svm.fSupported
717 && pVM->hwaccm.s.lLastError == VERR_SVM_IN_USE /* implies functional AMD-V */
718 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
719 {
720 LogRel(("HWACCM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
721 pVM->hwaccm.s.svm.fSupported = true;
722 pVM->hwaccm.s.svm.fIgnoreInUseError = true;
723 }
724 else
725 if ( !pVM->hwaccm.s.vmx.fSupported
726 && !pVM->hwaccm.s.svm.fSupported)
727 {
728 LogRel(("HWACCM: No VT-x or AMD-V CPU extension found. Reason %Rrc\n", pVM->hwaccm.s.lLastError));
729 LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
730
731 if (VMMIsHwVirtExtForced(pVM))
732 {
733 switch (pVM->hwaccm.s.lLastError)
734 {
735 case VERR_VMX_NO_VMX:
736 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
737 case VERR_VMX_IN_VMX_ROOT_MODE:
738 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor.");
739 case VERR_SVM_IN_USE:
740 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor.");
741 case VERR_SVM_NO_SVM:
742 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available.");
743 case VERR_SVM_DISABLED:
744 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS.");
745 default:
746 return pVM->hwaccm.s.lLastError;
747 }
748 }
749 return VINF_SUCCESS;
750 }
751
752 if (pVM->hwaccm.s.vmx.fSupported)
753 {
754 rc = SUPR3QueryVTxSupported();
755 if (RT_FAILURE(rc))
756 {
757#ifdef RT_OS_LINUX
758 LogRel(("HWACCM: The host kernel does not support VT-x -- Linux 2.6.13 or newer required!\n"));
759#else
760 LogRel(("HWACCM: The host kernel does not support VT-x!\n"));
761#endif
762 if ( pVM->cCpus > 1
763 || VMMIsHwVirtExtForced(pVM))
764 return rc;
765
766 /* silently fall back to raw mode */
767 return VINF_SUCCESS;
768 }
769 }
770
771 if (!pVM->hwaccm.s.fAllowed)
772 return VINF_SUCCESS; /* nothing to do */
773
774 /* Enable VT-x or AMD-V on all host CPUs. */
775 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_ENABLE, 0, NULL);
776 if (RT_FAILURE(rc))
777 {
778 LogRel(("HWACCMR3InitFinalize: SUPR3CallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Rrc\n", rc));
779 return rc;
780 }
781 Assert(!pVM->fHWACCMEnabled || VMMIsHwVirtExtForced(pVM));
782
783 pVM->hwaccm.s.fHasIoApic = PDMHasIoApic(pVM);
784 /* No TPR patching is required when the IO-APIC is not enabled for this VM. (Main should have taken care of this already) */
785 if (!pVM->hwaccm.s.fHasIoApic)
786 {
787 Assert(!pVM->hwaccm.s.fTRPPatchingAllowed); /* paranoia */
788 pVM->hwaccm.s.fTRPPatchingAllowed = false;
789 }
790
791 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
792 if (pVM->hwaccm.s.vmx.fSupported)
793 {
794 Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
795
796 if ( pVM->hwaccm.s.fInitialized == false
797 && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
798 {
799 uint64_t val;
800 RTGCPHYS GCPhys = 0;
801
802 LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
803 LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
804 LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
805 LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
806 LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
807 LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
808 LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
809 LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
810
811 LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
812 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
813 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
814 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
815 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
816 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
817 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
818 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI\n"));
819 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
820 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER\n"));
821 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
822 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
823 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT *must* be set\n"));
824 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
825 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT *must* be set\n"));
826 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
827 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI *must* be set\n"));
828 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
829 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER *must* be set\n"));
830
831 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
832 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
833 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
834 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
835 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
836 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
837 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
838 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
839 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
840 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
841 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
842 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
843 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
844 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
845 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
846 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
847 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
848 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
849 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
850 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
851 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
852 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
853 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
854 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
855 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
856 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
857 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
858 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT\n"));
859 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
860 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
861 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
862 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
863 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
864 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
865 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
866 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
867 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
868 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
869 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
870 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
871 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
872 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
873 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
874 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
875
876 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
877 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
878 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT *must* be set\n"));
879 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
880 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET *must* be set\n"));
881 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
882 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT *must* be set\n"));
883 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
884 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT *must* be set\n"));
885 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
886 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT *must* be set\n"));
887 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
888 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT *must* be set\n"));
889 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
890 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT *must* be set\n"));
891 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
892 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT *must* be set\n"));
893 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
894 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT *must* be set\n"));
895 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
896 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT *must* be set\n"));
897 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
898 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT *must* be set\n"));
899 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
900 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW *must* be set\n"));
901 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
902 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT *must* be set\n"));
903 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
904 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT *must* be set\n"));
905 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
906 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT *must* be set\n"));
907 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
908 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS *must* be set\n"));
909 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
910 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG *must* be set\n"));
911 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
912 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS *must* be set\n"));
913 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
914 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT *must* be set\n"));
915 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
916 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT *must* be set\n"));
917 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
918 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL *must* be set\n"));
919
920 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
921 {
922 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
923 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
924 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
925 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
926 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
927 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
928 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
929 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT\n"));
930 if (val & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT)
931 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT\n"));
932 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
933 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC\n"));
934 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
935 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
936 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
937 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
938 if (val & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE)
939 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE\n"));
940 if (val & VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT)
941 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT\n"));
942
943 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
944 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
945 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC *must* be set\n"));
946 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
947 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT *must* be set\n"));
948 if (val & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT)
949 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT *must* be set\n"));
950 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
951 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC *must* be set\n"));
952 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
953 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT *must* be set\n"));
954 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
955 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID *must* be set\n"));
956 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
957 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT *must* be set\n"));
958 if (val & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE)
959 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE *must* be set\n"));
960 if (val & VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT)
961 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT *must* be set\n"));
962 }
963
964 LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
965 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
966 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
967 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
968 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
969 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
970 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
971 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
972 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
973 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
974 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
975 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
976 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
977 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
978 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
979 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
980 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
981 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
982 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG *must* be set\n"));
983 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
984 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE *must* be set\n"));
985 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
986 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM *must* be set\n"));
987 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
988 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON *must* be set\n"));
989 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
990 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR *must* be set\n"));
991 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
992 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR *must* be set\n"));
993 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
994 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR *must* be set\n"));
995
996 LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
997 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
998 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
999 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
1000 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
1001 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
1002 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
1003 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
1004 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
1005 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
1006 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
1007 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
1008 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
1009 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
1010 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
1011 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
1012 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
1013 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
1014 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
1015 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
1016 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG *must* be set\n"));
1017 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
1018 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 *must* be set\n"));
1019 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
1020 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ *must* be set\n"));
1021 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
1022 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR *must* be set\n"));
1023 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
1024 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR *must* be set\n"));
1025 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
1026 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR *must* be set\n"));
1027 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
1028 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR *must* be set\n"));
1029 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
1030 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER *must* be set\n"));
1031
1032 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
1033 {
1034 LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
1035
1036 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
1037 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
1038 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
1039 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
1040 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
1041 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
1042 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
1043 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
1044 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
1045 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
1046 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
1047 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
1048 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
1049 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
1050 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
1051 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
1052 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
1053 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
1054 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
1055 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
1056 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
1057 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
1058 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
1059 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
1060 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
1061 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
1062 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
1063 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
1064 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
1065 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
1066 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
1067 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
1068 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
1069 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
1070 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
1071 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
1072 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_SINGLE_CONTEXT)
1073 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_SINGLE_CONTEXT\n"));
1074 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL_CONTEXTS)
1075 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL_CONTEXTS\n"));
1076 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
1077 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
1078 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV_ADDR)
1079 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV_ADDR\n"));
1080 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_SINGLE_CONTEXT)
1081 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_SINGLE_CONTEXT\n"));
1082 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL_CONTEXTS)
1083 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL_CONTEXTS\n"));
1084 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_SINGLE_CONTEXT_RETAIN_GLOBALS)
1085 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_SINGLE_CONTEXT_RETAIN_GLOBALS\n"));
1086 }
1087
1088 LogRel(("HWACCM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
1089 if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc) == pVM->hwaccm.s.vmx.cPreemptTimerShift)
1090 LogRel(("HWACCM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1091 else
1092 LogRel(("HWACCM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x - erratum detected, using %x instead\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc), pVM->hwaccm.s.vmx.cPreemptTimerShift));
1093 LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1094 LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1095 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1096 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1097
1098 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
1099 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
1100 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
1101 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
1102 LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
1103
1104 LogRel(("HWACCM: TPR shadow physaddr = %RHp\n", pVM->hwaccm.s.vmx.pAPICPhys));
1105
1106 /* Paranoia */
1107 AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc) >= 512);
1108
1109 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1110 {
1111 LogRel(("HWACCM: VCPU%d: MSR bitmap physaddr = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pMSRBitmapPhys));
1112 LogRel(("HWACCM: VCPU%d: VMCS physaddr = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.HCPhysVMCS));
1113 }
1114
1115 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
1116 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
1117
1118 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
1119 pVM->hwaccm.s.vmx.fVPID = pVM->hwaccm.s.vmx.fAllowVPID;
1120
1121 /* Unrestricted guest execution relies on EPT. */
1122 if ( pVM->hwaccm.s.fNestedPaging
1123 && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE))
1124 {
1125 pVM->hwaccm.s.vmx.fUnrestrictedGuest = true;
1126 }
1127
1128 /* Only try once. */
1129 pVM->hwaccm.s.fInitialized = true;
1130
1131 if (!pVM->hwaccm.s.vmx.fUnrestrictedGuest)
1132 {
1133 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1134 rc = PDMR3VMMDevHeapAlloc(pVM, HWACCM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hwaccm.s.vmx.pRealModeTSS);
1135 if (RT_SUCCESS(rc))
1136 {
1137 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
1138 ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
1139 pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
1140 /* Bit set to 0 means redirection enabled. */
1141 memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
1142 /* Allow all port IO, so the VT-x IO intercepts do their job. */
1143 memset(pVM->hwaccm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
1144 *((unsigned char *)pVM->hwaccm.s.vmx.pRealModeTSS + HWACCM_VTX_TSS_SIZE - 2) = 0xff;
1145
1146 /*
1147 * Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
1148 * real and protected mode without paging with EPT.
1149 */
1150 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hwaccm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1151 for (unsigned i = 0; i < X86_PG_ENTRIES; i++)
1152 {
1153 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1154 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS | X86_PDE4M_G;
1155 }
1156
1157 /* We convert it here every time as pci regions could be reconfigured. */
1158 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
1159 AssertRC(rc);
1160 LogRel(("HWACCM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
1161
1162 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1163 AssertRC(rc);
1164 LogRel(("HWACCM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
1165 }
1166 else
1167 {
1168 LogRel(("HWACCM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1169 pVM->hwaccm.s.vmx.pRealModeTSS = NULL;
1170 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1171 }
1172 }
1173
1174 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1175 AssertRC(rc);
1176 if (rc == VINF_SUCCESS)
1177 {
1178 pVM->fHWACCMEnabled = true;
1179 pVM->hwaccm.s.vmx.fEnabled = true;
1180 hwaccmR3DisableRawMode(pVM);
1181
1182 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1183#ifdef VBOX_ENABLE_64_BITS_GUESTS
1184 if (pVM->hwaccm.s.fAllow64BitGuests)
1185 {
1186 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1187 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1188 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1189 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1190 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1191 }
1192 else
1193 /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE (we reuse the host EFER in the switcher) */
1194 /* Todo: this needs to be fixed properly!! */
1195 if ( CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE)
1196 && (pVM->hwaccm.s.vmx.hostEFER & MSR_K6_EFER_NXE))
1197 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1198
1199 LogRel((pVM->hwaccm.s.fAllow64BitGuests
1200 ? "HWACCM: 32-bit and 64-bit guests supported.\n"
1201 : "HWACCM: 32-bit guests supported.\n"));
1202#else
1203 LogRel(("HWACCM: 32-bit guests supported.\n"));
1204#endif
1205 LogRel(("HWACCM: VMX enabled!\n"));
1206 if (pVM->hwaccm.s.fNestedPaging)
1207 {
1208 LogRel(("HWACCM: Enabled nested paging\n"));
1209 LogRel(("HWACCM: EPT root page = %RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));
1210 if (pVM->hwaccm.s.vmx.fUnrestrictedGuest)
1211 LogRel(("HWACCM: Unrestricted guest execution enabled!\n"));
1212
1213#if HC_ARCH_BITS == 64
1214 if (pVM->hwaccm.s.fLargePages)
1215 {
1216 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1217 PGMSetLargePageUsage(pVM, true);
1218 LogRel(("HWACCM: Large page support enabled!\n"));
1219 }
1220#endif
1221 LogRel(("HWACCM: enmFlushEPT %d\n", pVM->hwaccm.s.vmx.enmFlushEPT));
1222 }
1223 else
1224 Assert(!pVM->hwaccm.s.vmx.fUnrestrictedGuest);
1225
1226 if (pVM->hwaccm.s.vmx.fVPID)
1227 {
1228 LogRel(("HWACCM: Enabled VPID\n"));
1229 LogRel(("HWACCM: enmFlushVPID %d\n", pVM->hwaccm.s.vmx.enmFlushVPID));
1230 }
1231 else if (pVM->hwaccm.s.vmx.enmFlushVPID == VMX_FLUSH_VPID_NOT_SUPPORTED)
1232 LogRel(("HWACCM: Ignoring VPID capabilities of CPU.\n"));
1233
1234 /* TPR patching status logging. */
1235 if (pVM->hwaccm.s.fTRPPatchingAllowed)
1236 {
1237 if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1238 && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
1239 {
1240 pVM->hwaccm.s.fTRPPatchingAllowed = false; /* not necessary as we have a hardware solution. */
1241 LogRel(("HWACCM: TPR Patching not required (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC).\n"));
1242 }
1243 else
1244 {
1245 uint32_t u32Eax, u32Dummy;
1246
1247 /* TPR patching needs access to the MSR_K8_LSTAR msr. */
1248 ASMCpuId(0x80000000, &u32Eax, &u32Dummy, &u32Dummy, &u32Dummy);
1249 if ( u32Eax < 0x80000001
1250 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE))
1251 {
1252 pVM->hwaccm.s.fTRPPatchingAllowed = false;
1253 LogRel(("HWACCM: TPR patching disabled (long mode not supported).\n"));
1254 }
1255 }
1256 }
1257 LogRel(("HWACCM: TPR Patching %s.\n", (pVM->hwaccm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1258
1259 /*
1260 * Check for preemption timer config override and log the state of it.
1261 */
1262 if (pVM->hwaccm.s.vmx.fUsePreemptTimer)
1263 {
1264 PCFGMNODE pCfgHwAccM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HWACCM");
1265 int rc2 = CFGMR3QueryBoolDef(pCfgHwAccM, "UsePreemptTimer", &pVM->hwaccm.s.vmx.fUsePreemptTimer, true);
1266 AssertLogRelRC(rc2);
1267 }
1268 if (pVM->hwaccm.s.vmx.fUsePreemptTimer)
1269 LogRel(("HWACCM: Using the VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hwaccm.s.vmx.cPreemptTimerShift));
1270 }
1271 else
1272 {
1273 LogRel(("HWACCM: VMX setup failed with rc=%Rrc!\n", rc));
1274 LogRel(("HWACCM: Last instruction error %x\n", pVM->aCpus[0].hwaccm.s.vmx.lasterror.ulInstrError));
1275 pVM->fHWACCMEnabled = false;
1276 }
1277 }
1278 }
1279 else
1280 if (pVM->hwaccm.s.svm.fSupported)
1281 {
1282 Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
1283
1284 if (pVM->hwaccm.s.fInitialized == false)
1285 {
1286 /* Erratum 170 which requires a forced TLB flush for each world switch:
1287 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
1288 *
1289 * All BH-G1/2 and DH-G1/2 models include a fix:
1290 * Athlon X2: 0x6b 1/2
1291 * 0x68 1/2
1292 * Athlon 64: 0x7f 1
1293 * 0x6f 2
1294 * Sempron: 0x7f 1/2
1295 * 0x6f 2
1296 * 0x6c 2
1297 * 0x7c 2
1298 * Turion 64: 0x68 2
1299 *
1300 */
1301 uint32_t u32Dummy;
1302 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
1303 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
1304 u32BaseFamily= (u32Version >> 8) & 0xf;
1305 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
1306 u32Model = ((u32Version >> 4) & 0xf);
1307 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
1308 u32Stepping = u32Version & 0xf;
1309 if ( u32Family == 0xf
1310 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
1311 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
1312 {
1313 LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
1314 }
1315
1316 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
1317 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
1318 LogRel(("HWACCM: AMD HWCR MSR = %RX64\n", pVM->hwaccm.s.svm.msrHWCR));
1319 LogRel(("HWACCM: AMD-V revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
1320 LogRel(("HWACCM: AMD-V max ASID = %d\n", pVM->hwaccm.s.uMaxASID));
1321 LogRel(("HWACCM: AMD-V features = %X\n", pVM->hwaccm.s.svm.u32Features));
1322 static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1323 {
1324#define FLAG_NAME(a_Define) { a_Define, #a_Define }
1325 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1326 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1327 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1328 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1329 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1330 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1331 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1332 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST),
1333 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE),
1334 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1335 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1336#undef FLAG_NAME
1337 };
1338 uint32_t fSvmFeatures = pVM->hwaccm.s.svm.u32Features;
1339 for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1340 if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1341 {
1342 LogRel(("HWACCM: %s\n", s_aSvmFeatures[i].pszName));
1343 fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1344 }
1345 if (fSvmFeatures)
1346 for (unsigned iBit = 0; iBit < 32; iBit++)
1347 if (RT_BIT_32(iBit) & fSvmFeatures)
1348 LogRel(("HWACCM: Reserved bit %u\n", iBit));
1349
1350 /* Only try once. */
1351 pVM->hwaccm.s.fInitialized = true;
1352
1353 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1354 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
1355
1356 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1357 AssertRC(rc);
1358 if (rc == VINF_SUCCESS)
1359 {
1360 pVM->fHWACCMEnabled = true;
1361 pVM->hwaccm.s.svm.fEnabled = true;
1362
1363 if (pVM->hwaccm.s.fNestedPaging)
1364 {
1365 LogRel(("HWACCM: Enabled nested paging\n"));
1366#if HC_ARCH_BITS == 64
1367 if (pVM->hwaccm.s.fLargePages)
1368 {
1369 /* Use large (2 MB) pages for our nested paging PDEs where possible. */
1370 PGMSetLargePageUsage(pVM, true);
1371 LogRel(("HWACCM: Large page support enabled!\n"));
1372 }
1373#endif
1374 }
1375
1376 hwaccmR3DisableRawMode(pVM);
1377 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1378 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1379 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1380#ifdef VBOX_ENABLE_64_BITS_GUESTS
1381 if (pVM->hwaccm.s.fAllow64BitGuests)
1382 {
1383 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1384 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1385 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1386 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1387 }
1388 else
1389 /* Turn on NXE if PAE has been enabled. */
1390 if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1391 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1392#endif
1393
1394 LogRel((pVM->hwaccm.s.fAllow64BitGuests
1395 ? "HWACCM: 32-bit and 64-bit guest supported.\n"
1396 : "HWACCM: 32-bit guest supported.\n"));
1397
1398 LogRel(("HWACCM: TPR Patching %s.\n", (pVM->hwaccm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1399 }
1400 else
1401 {
1402 pVM->fHWACCMEnabled = false;
1403 }
1404 }
1405 }
1406 if (pVM->fHWACCMEnabled)
1407 LogRel(("HWACCM: VT-x/AMD-V init method: %s\n", (pVM->hwaccm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
1408 RTLogRelSetBuffering(fOldBuffered);
1409 return VINF_SUCCESS;
1410}
1411
1412
1413/**
1414 * Applies relocations to data and code managed by this
1415 * component. This function will be called at init and
1416 * whenever the VMM need to relocate it self inside the GC.
1417 *
1418 * @param pVM The VM.
1419 */
1420VMMR3DECL(void) HWACCMR3Relocate(PVM pVM)
1421{
1422 Log(("HWACCMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1423
1424 /* Fetch the current paging mode during the relocate callback during state loading. */
1425 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1426 {
1427 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1428 {
1429 PVMCPU pVCpu = &pVM->aCpus[i];
1430
1431 pVCpu->hwaccm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1432 Assert(pVCpu->hwaccm.s.vmx.enmCurrGuestMode == PGMGetGuestMode(pVCpu));
1433 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMGetGuestMode(pVCpu);
1434 }
1435 }
1436#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1437 if (pVM->fHWACCMEnabled)
1438 {
1439 int rc;
1440 switch (PGMGetHostMode(pVM))
1441 {
1442 case PGMMODE_32_BIT:
1443 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1444 break;
1445
1446 case PGMMODE_PAE:
1447 case PGMMODE_PAE_NX:
1448 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1449 break;
1450
1451 default:
1452 AssertFailed();
1453 break;
1454 }
1455 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hwaccm.s.pfnVMXGCStartVM64);
1456 AssertReleaseMsgRC(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc));
1457
1458 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hwaccm.s.pfnSVMGCVMRun64);
1459 AssertReleaseMsgRC(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc));
1460
1461 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestFPU64", &pVM->hwaccm.s.pfnSaveGuestFPU64);
1462 AssertReleaseMsgRC(rc, ("HWACCMSetupFPU64 -> rc=%Rrc\n", rc));
1463
1464 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestDebug64", &pVM->hwaccm.s.pfnSaveGuestDebug64);
1465 AssertReleaseMsgRC(rc, ("HWACCMSetupDebug64 -> rc=%Rrc\n", rc));
1466
1467# ifdef DEBUG
1468 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMTestSwitcher64", &pVM->hwaccm.s.pfnTest64);
1469 AssertReleaseMsgRC(rc, ("HWACCMTestSwitcher64 -> rc=%Rrc\n", rc));
1470# endif
1471 }
1472#endif
1473 return;
1474}
1475
1476
1477/**
1478 * Checks if hardware accelerated raw mode is allowed.
1479 *
1480 * @returns true if hardware acceleration is allowed, otherwise false.
1481 * @param pVM Pointer to the VM.
1482 */
1483VMMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
1484{
1485 return pVM->hwaccm.s.fAllowed;
1486}
1487
1488
1489/**
1490 * Notification callback which is called whenever there is a chance that a CR3
1491 * value might have changed.
1492 *
1493 * This is called by PGM.
1494 *
1495 * @param pVM Pointer to the VM.
1496 * @param pVCpu Pointer to the VMCPU.
1497 * @param enmShadowMode New shadow paging mode.
1498 * @param enmGuestMode New guest paging mode.
1499 */
1500VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1501{
1502 /* Ignore page mode changes during state loading. */
1503 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1504 return;
1505
1506 pVCpu->hwaccm.s.enmShadowMode = enmShadowMode;
1507
1508 if ( pVM->hwaccm.s.vmx.fEnabled
1509 && pVM->fHWACCMEnabled)
1510 {
1511 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1512 && enmGuestMode >= PGMMODE_PROTECTED)
1513 {
1514 PCPUMCTX pCtx;
1515
1516 pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1517
1518 /* After a real mode switch to protected mode we must force
1519 CPL to 0. Our real mode emulation had to set it to 3. */
1520 pCtx->ss.Attr.n.u2Dpl = 0;
1521 }
1522 }
1523
1524 if (pVCpu->hwaccm.s.vmx.enmCurrGuestMode != enmGuestMode)
1525 {
1526 /* Keep track of paging mode changes. */
1527 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = pVCpu->hwaccm.s.vmx.enmCurrGuestMode;
1528 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = enmGuestMode;
1529
1530 /* Did we miss a change, because all code was executed in the recompiler? */
1531 if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == enmGuestMode)
1532 {
1533 Log(("HWACCMR3PagingModeChanged missed %s->%s transition (prev %s)\n", PGMGetModeName(pVCpu->hwaccm.s.vmx.enmPrevGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode)));
1534 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = pVCpu->hwaccm.s.vmx.enmPrevGuestMode;
1535 }
1536 }
1537
1538 /* Reset the contents of the read cache. */
1539 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1540 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1541 pCache->Read.aFieldVal[j] = 0;
1542}
1543
1544
1545/**
1546 * Terminates the HWACCM.
1547 *
1548 * Termination means cleaning up and freeing all resources,
1549 * the VM itself is, at this point, powered off or suspended.
1550 *
1551 * @returns VBox status code.
1552 * @param pVM Pointer to the VM.
1553 */
1554VMMR3DECL(int) HWACCMR3Term(PVM pVM)
1555{
1556 if (pVM->hwaccm.s.vmx.pRealModeTSS)
1557 {
1558 PDMR3VMMDevHeapFree(pVM, pVM->hwaccm.s.vmx.pRealModeTSS);
1559 pVM->hwaccm.s.vmx.pRealModeTSS = 0;
1560 }
1561 hwaccmR3TermCPU(pVM);
1562 return 0;
1563}
1564
1565
1566/**
1567 * Terminates the per-VCPU HWACCM.
1568 *
1569 * @returns VBox status code.
1570 * @param pVM Pointer to the VM.
1571 */
1572static int hwaccmR3TermCPU(PVM pVM)
1573{
1574 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1575 {
1576 PVMCPU pVCpu = &pVM->aCpus[i]; NOREF(pVCpu);
1577
1578#ifdef VBOX_WITH_STATISTICS
1579 if (pVCpu->hwaccm.s.paStatExitReason)
1580 {
1581 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatExitReason);
1582 pVCpu->hwaccm.s.paStatExitReason = NULL;
1583 pVCpu->hwaccm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1584 }
1585 if (pVCpu->hwaccm.s.paStatInjectedIrqs)
1586 {
1587 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatInjectedIrqs);
1588 pVCpu->hwaccm.s.paStatInjectedIrqs = NULL;
1589 pVCpu->hwaccm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1590 }
1591#endif
1592
1593#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1594 memset(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic));
1595 pVCpu->hwaccm.s.vmx.VMCSCache.uMagic = 0;
1596 pVCpu->hwaccm.s.vmx.VMCSCache.uPos = 0xffffffff;
1597#endif
1598 }
1599 return 0;
1600}
1601
1602
1603/**
1604 * Resets a virtual CPU.
1605 *
1606 * Used by HWACCMR3Reset and CPU hot plugging.
1607 *
1608 * @param pVCpu The CPU to reset.
1609 */
1610VMMR3DECL(void) HWACCMR3ResetCpu(PVMCPU pVCpu)
1611{
1612 /* On first entry we'll sync everything. */
1613 pVCpu->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1614
1615 pVCpu->hwaccm.s.vmx.cr0_mask = 0;
1616 pVCpu->hwaccm.s.vmx.cr4_mask = 0;
1617
1618 pVCpu->hwaccm.s.fActive = false;
1619 pVCpu->hwaccm.s.Event.fPending = false;
1620
1621 /* Reset state information for real-mode emulation in VT-x. */
1622 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
1623 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = PGMMODE_REAL;
1624 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1625
1626 /* Reset the contents of the read cache. */
1627 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1628 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1629 pCache->Read.aFieldVal[j] = 0;
1630
1631#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1632 /* Magic marker for searching in crash dumps. */
1633 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1634 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1635#endif
1636}
1637
1638
1639/**
1640 * The VM is being reset.
1641 *
1642 * For the HWACCM component this means that any GDT/LDT/TSS monitors
1643 * needs to be removed.
1644 *
1645 * @param pVM Pointer to the VM.
1646 */
1647VMMR3DECL(void) HWACCMR3Reset(PVM pVM)
1648{
1649 LogFlow(("HWACCMR3Reset:\n"));
1650
1651 if (pVM->fHWACCMEnabled)
1652 hwaccmR3DisableRawMode(pVM);
1653
1654 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1655 {
1656 PVMCPU pVCpu = &pVM->aCpus[i];
1657
1658 HWACCMR3ResetCpu(pVCpu);
1659 }
1660
1661 /* Clear all patch information. */
1662 pVM->hwaccm.s.pGuestPatchMem = 0;
1663 pVM->hwaccm.s.pFreeGuestPatchMem = 0;
1664 pVM->hwaccm.s.cbGuestPatchMem = 0;
1665 pVM->hwaccm.s.cPatches = 0;
1666 pVM->hwaccm.s.PatchTree = 0;
1667 pVM->hwaccm.s.fTPRPatchingActive = false;
1668 ASMMemZero32(pVM->hwaccm.s.aPatches, sizeof(pVM->hwaccm.s.aPatches));
1669}
1670
1671
1672/**
1673 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1674 *
1675 * @returns VBox strict status code.
1676 * @param pVM Pointer to the VM.
1677 * @param pVCpu The VMCPU for the EMT we're being called on.
1678 * @param pvUser Unused.
1679 */
1680DECLCALLBACK(VBOXSTRICTRC) hwaccmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1681{
1682 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1683
1684 /* Only execute the handler on the VCPU the original patch request was issued. */
1685 if (pVCpu->idCpu != idCpu)
1686 return VINF_SUCCESS;
1687
1688 Log(("hwaccmR3RemovePatches\n"));
1689 for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
1690 {
1691 uint8_t abInstr[15];
1692 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
1693 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1694 int rc;
1695
1696#ifdef LOG_ENABLED
1697 char szOutput[256];
1698
1699 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1700 szOutput, sizeof(szOutput), NULL);
1701 if (RT_SUCCESS(rc))
1702 Log(("Patched instr: %s\n", szOutput));
1703#endif
1704
1705 /* Check if the instruction is still the same. */
1706 rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
1707 if (rc != VINF_SUCCESS)
1708 {
1709 Log(("Patched code removed? (rc=%Rrc0\n", rc));
1710 continue; /* swapped out or otherwise removed; skip it. */
1711 }
1712
1713 if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1714 {
1715 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1716 continue; /* skip it. */
1717 }
1718
1719 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1720 AssertRC(rc);
1721
1722#ifdef LOG_ENABLED
1723 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1724 szOutput, sizeof(szOutput), NULL);
1725 if (RT_SUCCESS(rc))
1726 Log(("Original instr: %s\n", szOutput));
1727#endif
1728 }
1729 pVM->hwaccm.s.cPatches = 0;
1730 pVM->hwaccm.s.PatchTree = 0;
1731 pVM->hwaccm.s.pFreeGuestPatchMem = pVM->hwaccm.s.pGuestPatchMem;
1732 pVM->hwaccm.s.fTPRPatchingActive = false;
1733 return VINF_SUCCESS;
1734}
1735
1736
1737/**
1738 * Worker for enabling patching in a VT-x/AMD-V guest.
1739 *
1740 * @returns VBox status code.
1741 * @param pVM Pointer to the VM.
1742 * @param idCpu VCPU to execute hwaccmR3RemovePatches on.
1743 * @param pPatchMem Patch memory range.
1744 * @param cbPatchMem Size of the memory range.
1745 */
1746static int hwaccmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
1747{
1748 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hwaccmR3RemovePatches, (void *)(uintptr_t)idCpu);
1749 AssertRC(rc);
1750
1751 pVM->hwaccm.s.pGuestPatchMem = pPatchMem;
1752 pVM->hwaccm.s.pFreeGuestPatchMem = pPatchMem;
1753 pVM->hwaccm.s.cbGuestPatchMem = cbPatchMem;
1754 return VINF_SUCCESS;
1755}
1756
1757
1758/**
1759 * Enable patching in a VT-x/AMD-V guest
1760 *
1761 * @returns VBox status code.
1762 * @param pVM Pointer to the VM.
1763 * @param pPatchMem Patch memory range.
1764 * @param cbPatchMem Size of the memory range.
1765 */
1766VMMR3DECL(int) HWACMMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1767{
1768 VM_ASSERT_EMT(pVM);
1769 Log(("HWACMMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1770 if (pVM->cCpus > 1)
1771 {
1772 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
1773 int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
1774 (PFNRT)hwaccmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1775 AssertRC(rc);
1776 return rc;
1777 }
1778 return hwaccmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1779}
1780
1781
1782/**
1783 * Disable patching in a VT-x/AMD-V guest.
1784 *
1785 * @returns VBox status code.
1786 * @param pVM Pointer to the VM.
1787 * @param pPatchMem Patch memory range.
1788 * @param cbPatchMem Size of the memory range.
1789 */
1790VMMR3DECL(int) HWACMMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1791{
1792 Log(("HWACMMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1793
1794 Assert(pVM->hwaccm.s.pGuestPatchMem == pPatchMem);
1795 Assert(pVM->hwaccm.s.cbGuestPatchMem == cbPatchMem);
1796
1797 /* @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
1798 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hwaccmR3RemovePatches, (void *)(uintptr_t)VMMGetCpuId(pVM));
1799 AssertRC(rc);
1800
1801 pVM->hwaccm.s.pGuestPatchMem = 0;
1802 pVM->hwaccm.s.pFreeGuestPatchMem = 0;
1803 pVM->hwaccm.s.cbGuestPatchMem = 0;
1804 pVM->hwaccm.s.fTPRPatchingActive = false;
1805 return VINF_SUCCESS;
1806}
1807
1808
1809/**
1810 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1811 *
1812 * @returns VBox strict status code.
1813 * @param pVM Pointer to the VM.
1814 * @param pVCpu The VMCPU for the EMT we're being called on.
1815 * @param pvUser User specified CPU context.
1816 *
1817 */
1818DECLCALLBACK(VBOXSTRICTRC) hwaccmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1819{
1820 /*
1821 * Only execute the handler on the VCPU the original patch request was
1822 * issued. (The other CPU(s) might not yet have switched to protected
1823 * mode, nor have the correct memory context.)
1824 */
1825 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1826 if (pVCpu->idCpu != idCpu)
1827 return VINF_SUCCESS;
1828
1829 /*
1830 * We're racing other VCPUs here, so don't try patch the instruction twice
1831 * and make sure there is still room for our patch record.
1832 */
1833 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1834 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1835 if (pPatch)
1836 {
1837 Log(("hwaccmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
1838 return VINF_SUCCESS;
1839 }
1840 uint32_t const idx = pVM->hwaccm.s.cPatches;
1841 if (idx >= RT_ELEMENTS(pVM->hwaccm.s.aPatches))
1842 {
1843 Log(("hwaccmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
1844 return VINF_SUCCESS;
1845 }
1846 pPatch = &pVM->hwaccm.s.aPatches[idx];
1847
1848 Log(("hwaccmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
1849
1850 /*
1851 * Disassembler the instruction and get cracking.
1852 */
1853 DBGFR3DisasInstrCurrentLog(pVCpu, "hwaccmR3ReplaceTprInstr");
1854 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
1855 uint32_t cbOp;
1856 int rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1857 AssertRC(rc);
1858 if ( rc == VINF_SUCCESS
1859 && pDis->pCurInstr->uOpcode == OP_MOV
1860 && cbOp >= 3)
1861 {
1862 static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
1863
1864 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1865 AssertRC(rc);
1866
1867 pPatch->cbOp = cbOp;
1868
1869 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
1870 {
1871 /* write. */
1872 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
1873 {
1874 pPatch->enmType = HWACCMTPRINSTR_WRITE_REG;
1875 pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
1876 Log(("hwaccmR3ReplaceTprInstr: HWACCMTPRINSTR_WRITE_REG %u\n", pDis->Param2.Base.idxGenReg));
1877 }
1878 else
1879 {
1880 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
1881 pPatch->enmType = HWACCMTPRINSTR_WRITE_IMM;
1882 pPatch->uSrcOperand = pDis->Param2.uValue;
1883 Log(("hwaccmR3ReplaceTprInstr: HWACCMTPRINSTR_WRITE_IMM %#llx\n", pDis->Param2.uValue));
1884 }
1885 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
1886 AssertRC(rc);
1887
1888 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
1889 pPatch->cbNewOp = sizeof(s_abVMMCall);
1890 }
1891 else
1892 {
1893 /*
1894 * TPR Read.
1895 *
1896 * Found:
1897 * mov eax, dword [fffe0080] (5 bytes)
1898 * Check if next instruction is:
1899 * shr eax, 4
1900 */
1901 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
1902
1903 uint8_t const idxMmioReg = pDis->Param1.Base.idxGenReg;
1904 uint8_t const cbOpMmio = cbOp;
1905 uint64_t const uSavedRip = pCtx->rip;
1906
1907 pCtx->rip += cbOp;
1908 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1909 DBGFR3DisasInstrCurrentLog(pVCpu, "Following read");
1910 pCtx->rip = uSavedRip;
1911
1912 if ( rc == VINF_SUCCESS
1913 && pDis->pCurInstr->uOpcode == OP_SHR
1914 && pDis->Param1.fUse == DISUSE_REG_GEN32
1915 && pDis->Param1.Base.idxGenReg == idxMmioReg
1916 && pDis->Param2.fUse == DISUSE_IMMEDIATE8
1917 && pDis->Param2.uValue == 4
1918 && cbOpMmio + cbOp < sizeof(pVM->hwaccm.s.aPatches[idx].aOpcode))
1919 {
1920 uint8_t abInstr[15];
1921
1922 /* Replacing two instructions now. */
1923 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
1924 AssertRC(rc);
1925
1926 pPatch->cbOp = cbOpMmio + cbOp;
1927
1928 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
1929 abInstr[0] = 0xF0;
1930 abInstr[1] = 0x0F;
1931 abInstr[2] = 0x20;
1932 abInstr[3] = 0xC0 | pDis->Param1.Base.idxGenReg;
1933 for (unsigned i = 4; i < pPatch->cbOp; i++)
1934 abInstr[i] = 0x90; /* nop */
1935
1936 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
1937 AssertRC(rc);
1938
1939 memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
1940 pPatch->cbNewOp = pPatch->cbOp;
1941
1942 Log(("Acceptable read/shr candidate!\n"));
1943 pPatch->enmType = HWACCMTPRINSTR_READ_SHR4;
1944 }
1945 else
1946 {
1947 pPatch->enmType = HWACCMTPRINSTR_READ;
1948 pPatch->uDstOperand = idxMmioReg;
1949
1950 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
1951 AssertRC(rc);
1952
1953 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
1954 pPatch->cbNewOp = sizeof(s_abVMMCall);
1955 Log(("hwaccmR3ReplaceTprInstr: HWACCMTPRINSTR_READ %u\n", pPatch->uDstOperand));
1956 }
1957 }
1958
1959 pPatch->Core.Key = pCtx->eip;
1960 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
1961 AssertRC(rc);
1962
1963 pVM->hwaccm.s.cPatches++;
1964 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRReplaceSuccess);
1965 return VINF_SUCCESS;
1966 }
1967
1968 /*
1969 * Save invalid patch, so we will not try again.
1970 */
1971 Log(("hwaccmR3ReplaceTprInstr: Failed to patch instr!\n"));
1972 pPatch->Core.Key = pCtx->eip;
1973 pPatch->enmType = HWACCMTPRINSTR_INVALID;
1974 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
1975 AssertRC(rc);
1976 pVM->hwaccm.s.cPatches++;
1977 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRReplaceFailure);
1978 return VINF_SUCCESS;
1979}
1980
1981
1982/**
1983 * Callback to patch a TPR instruction (jump to generated code).
1984 *
1985 * @returns VBox strict status code.
1986 * @param pVM Pointer to the VM.
1987 * @param pVCpu The VMCPU for the EMT we're being called on.
1988 * @param pvUser User specified CPU context.
1989 *
1990 */
1991DECLCALLBACK(VBOXSTRICTRC) hwaccmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1992{
1993 /*
1994 * Only execute the handler on the VCPU the original patch request was
1995 * issued. (The other CPU(s) might not yet have switched to protected
1996 * mode, nor have the correct memory context.)
1997 */
1998 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1999 if (pVCpu->idCpu != idCpu)
2000 return VINF_SUCCESS;
2001
2002 /*
2003 * We're racing other VCPUs here, so don't try patch the instruction twice
2004 * and make sure there is still room for our patch record.
2005 */
2006 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2007 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2008 if (pPatch)
2009 {
2010 Log(("hwaccmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2011 return VINF_SUCCESS;
2012 }
2013 uint32_t const idx = pVM->hwaccm.s.cPatches;
2014 if (idx >= RT_ELEMENTS(pVM->hwaccm.s.aPatches))
2015 {
2016 Log(("hwaccmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2017 return VINF_SUCCESS;
2018 }
2019 pPatch = &pVM->hwaccm.s.aPatches[idx];
2020
2021 Log(("hwaccmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2022 DBGFR3DisasInstrCurrentLog(pVCpu, "hwaccmR3PatchTprInstr");
2023
2024 /*
2025 * Disassemble the instruction and get cracking.
2026 */
2027 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
2028 uint32_t cbOp;
2029 int rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
2030 AssertRC(rc);
2031 if ( rc == VINF_SUCCESS
2032 && pDis->pCurInstr->uOpcode == OP_MOV
2033 && cbOp >= 5)
2034 {
2035 uint8_t aPatch[64];
2036 uint32_t off = 0;
2037
2038 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2039 AssertRC(rc);
2040
2041 pPatch->cbOp = cbOp;
2042 pPatch->enmType = HWACCMTPRINSTR_JUMP_REPLACEMENT;
2043
2044 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2045 {
2046 /*
2047 * TPR write:
2048 *
2049 * push ECX [51]
2050 * push EDX [52]
2051 * push EAX [50]
2052 * xor EDX,EDX [31 D2]
2053 * mov EAX,EAX [89 C0]
2054 * or
2055 * mov EAX,0000000CCh [B8 CC 00 00 00]
2056 * mov ECX,0C0000082h [B9 82 00 00 C0]
2057 * wrmsr [0F 30]
2058 * pop EAX [58]
2059 * pop EDX [5A]
2060 * pop ECX [59]
2061 * jmp return_address [E9 return_address]
2062 *
2063 */
2064 bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
2065
2066 aPatch[off++] = 0x51; /* push ecx */
2067 aPatch[off++] = 0x52; /* push edx */
2068 if (!fUsesEax)
2069 aPatch[off++] = 0x50; /* push eax */
2070 aPatch[off++] = 0x31; /* xor edx, edx */
2071 aPatch[off++] = 0xD2;
2072 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2073 {
2074 if (!fUsesEax)
2075 {
2076 aPatch[off++] = 0x89; /* mov eax, src_reg */
2077 aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
2078 }
2079 }
2080 else
2081 {
2082 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2083 aPatch[off++] = 0xB8; /* mov eax, immediate */
2084 *(uint32_t *)&aPatch[off] = pDis->Param2.uValue;
2085 off += sizeof(uint32_t);
2086 }
2087 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2088 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2089 off += sizeof(uint32_t);
2090
2091 aPatch[off++] = 0x0F; /* wrmsr */
2092 aPatch[off++] = 0x30;
2093 if (!fUsesEax)
2094 aPatch[off++] = 0x58; /* pop eax */
2095 aPatch[off++] = 0x5A; /* pop edx */
2096 aPatch[off++] = 0x59; /* pop ecx */
2097 }
2098 else
2099 {
2100 /*
2101 * TPR read:
2102 *
2103 * push ECX [51]
2104 * push EDX [52]
2105 * push EAX [50]
2106 * mov ECX,0C0000082h [B9 82 00 00 C0]
2107 * rdmsr [0F 32]
2108 * mov EAX,EAX [89 C0]
2109 * pop EAX [58]
2110 * pop EDX [5A]
2111 * pop ECX [59]
2112 * jmp return_address [E9 return_address]
2113 *
2114 */
2115 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2116
2117 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2118 aPatch[off++] = 0x51; /* push ecx */
2119 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2120 aPatch[off++] = 0x52; /* push edx */
2121 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2122 aPatch[off++] = 0x50; /* push eax */
2123
2124 aPatch[off++] = 0x31; /* xor edx, edx */
2125 aPatch[off++] = 0xD2;
2126
2127 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2128 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2129 off += sizeof(uint32_t);
2130
2131 aPatch[off++] = 0x0F; /* rdmsr */
2132 aPatch[off++] = 0x32;
2133
2134 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2135 {
2136 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2137 aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
2138 }
2139
2140 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2141 aPatch[off++] = 0x58; /* pop eax */
2142 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2143 aPatch[off++] = 0x5A; /* pop edx */
2144 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2145 aPatch[off++] = 0x59; /* pop ecx */
2146 }
2147 aPatch[off++] = 0xE9; /* jmp return_address */
2148 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hwaccm.s.pFreeGuestPatchMem + off + 4);
2149 off += sizeof(RTRCUINTPTR);
2150
2151 if (pVM->hwaccm.s.pFreeGuestPatchMem + off <= pVM->hwaccm.s.pGuestPatchMem + pVM->hwaccm.s.cbGuestPatchMem)
2152 {
2153 /* Write new code to the patch buffer. */
2154 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hwaccm.s.pFreeGuestPatchMem, aPatch, off);
2155 AssertRC(rc);
2156
2157#ifdef LOG_ENABLED
2158 uint32_t cbCurInstr;
2159 for (RTGCPTR GCPtrInstr = pVM->hwaccm.s.pFreeGuestPatchMem;
2160 GCPtrInstr < pVM->hwaccm.s.pFreeGuestPatchMem + off;
2161 GCPtrInstr += RT_MAX(cbCurInstr, 1))
2162 {
2163 char szOutput[256];
2164 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2165 szOutput, sizeof(szOutput), &cbCurInstr);
2166 if (RT_SUCCESS(rc))
2167 Log(("Patch instr %s\n", szOutput));
2168 else
2169 Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2170 }
2171#endif
2172
2173 pPatch->aNewOpcode[0] = 0xE9;
2174 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hwaccm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2175
2176 /* Overwrite the TPR instruction with a jump. */
2177 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2178 AssertRC(rc);
2179
2180 DBGFR3DisasInstrCurrentLog(pVCpu, "Jump");
2181
2182 pVM->hwaccm.s.pFreeGuestPatchMem += off;
2183 pPatch->cbNewOp = 5;
2184
2185 pPatch->Core.Key = pCtx->eip;
2186 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2187 AssertRC(rc);
2188
2189 pVM->hwaccm.s.cPatches++;
2190 pVM->hwaccm.s.fTPRPatchingActive = true;
2191 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRPatchSuccess);
2192 return VINF_SUCCESS;
2193 }
2194
2195 Log(("Ran out of space in our patch buffer!\n"));
2196 }
2197 else
2198 Log(("hwaccmR3PatchTprInstr: Failed to patch instr!\n"));
2199
2200
2201 /*
2202 * Save invalid patch, so we will not try again.
2203 */
2204 pPatch = &pVM->hwaccm.s.aPatches[idx];
2205 pPatch->Core.Key = pCtx->eip;
2206 pPatch->enmType = HWACCMTPRINSTR_INVALID;
2207 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2208 AssertRC(rc);
2209 pVM->hwaccm.s.cPatches++;
2210 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRPatchFailure);
2211 return VINF_SUCCESS;
2212}
2213
2214
2215/**
2216 * Attempt to patch TPR mmio instructions.
2217 *
2218 * @returns VBox status code.
2219 * @param pVM Pointer to the VM.
2220 * @param pVCpu Pointer to the VMCPU.
2221 * @param pCtx Pointer to the guest CPU context.
2222 */
2223VMMR3DECL(int) HWACCMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2224{
2225 NOREF(pCtx);
2226 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2227 pVM->hwaccm.s.pGuestPatchMem ? hwaccmR3PatchTprInstr : hwaccmR3ReplaceTprInstr,
2228 (void *)(uintptr_t)pVCpu->idCpu);
2229 AssertRC(rc);
2230 return rc;
2231}
2232
2233
2234/**
2235 * Force execution of the current IO code in the recompiler.
2236 *
2237 * @returns VBox status code.
2238 * @param pVM Pointer to the VM.
2239 * @param pCtx Partial VM execution context.
2240 */
2241VMMR3DECL(int) HWACCMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
2242{
2243 PVMCPU pVCpu = VMMGetCpu(pVM);
2244
2245 Assert(pVM->fHWACCMEnabled);
2246 Log(("HWACCMR3EmulateIoBlock\n"));
2247
2248 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
2249 if (HWACCMCanEmulateIoBlockEx(pCtx))
2250 {
2251 Log(("HWACCMR3EmulateIoBlock -> enabled\n"));
2252 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = true;
2253 pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
2254 pVCpu->hwaccm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2255 return VINF_EM_RESCHEDULE_REM;
2256 }
2257 return VINF_SUCCESS;
2258}
2259
2260
2261/**
2262 * Checks if we can currently use hardware accelerated raw mode.
2263 *
2264 * @returns true if we can currently use hardware acceleration, otherwise false.
2265 * @param pVM Pointer to the VM.
2266 * @param pCtx Partial VM execution context.
2267 */
2268VMMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2269{
2270 PVMCPU pVCpu = VMMGetCpu(pVM);
2271
2272 Assert(pVM->fHWACCMEnabled);
2273
2274 /* If we're still executing the IO code, then return false. */
2275 if ( RT_UNLIKELY(pVCpu->hwaccm.s.EmulateIoBlock.fEnabled)
2276 && pCtx->rip < pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2277 && pCtx->rip > pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2278 && pCtx->cr0 == pVCpu->hwaccm.s.EmulateIoBlock.cr0)
2279 return false;
2280
2281 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = false;
2282
2283 /* AMD-V supports real & protected mode with or without paging. */
2284 if (pVM->hwaccm.s.svm.fEnabled)
2285 {
2286 pVCpu->hwaccm.s.fActive = true;
2287 return true;
2288 }
2289
2290 pVCpu->hwaccm.s.fActive = false;
2291
2292 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2293 Assert((pVM->hwaccm.s.vmx.fUnrestrictedGuest && !pVM->hwaccm.s.vmx.pRealModeTSS) || (!pVM->hwaccm.s.vmx.fUnrestrictedGuest && pVM->hwaccm.s.vmx.pRealModeTSS));
2294
2295 bool fSupportsRealMode = pVM->hwaccm.s.vmx.fUnrestrictedGuest || PDMVMMDevHeapIsEnabled(pVM);
2296 if (!pVM->hwaccm.s.vmx.fUnrestrictedGuest)
2297 {
2298 /*
2299 * The VMM device heap is a requirement for emulating real mode or protected mode without paging with the unrestricted
2300 * guest execution feature i missing (VT-x only).
2301 */
2302 if (fSupportsRealMode)
2303 {
2304 if (CPUMIsGuestInRealModeEx(pCtx))
2305 {
2306 /* VT-x will not allow high selector bases in v86 mode; fall
2307 back to the recompiler in that case.
2308 The base must also be equal to (sel << 4). */
2309 if ( ( pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
2310 && pCtx->cs.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
2311 || (pCtx->cs.u32Limit != 0xffff)
2312 || (pCtx->ds.u32Limit != 0xffff)
2313 || (pCtx->es.u32Limit != 0xffff)
2314 || (pCtx->ss.u32Limit != 0xffff)
2315 || (pCtx->fs.u32Limit != 0xffff)
2316 || (pCtx->gs.u32Limit != 0xffff)
2317 || pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
2318 || pCtx->es.Sel != (pCtx->es.u64Base >> 4)
2319 || pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
2320 || pCtx->gs.Sel != (pCtx->gs.u64Base >> 4)
2321 || pCtx->ss.Sel != (pCtx->ss.u64Base >> 4))
2322 {
2323 return false;
2324 }
2325 }
2326 else
2327 {
2328 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
2329 /* Verify the requirements for executing code in protected
2330 mode. VT-x can't handle the CPU state right after a switch
2331 from real to protected mode. (all sorts of RPL & DPL assumptions) */
2332 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
2333 && enmGuestMode >= PGMMODE_PROTECTED)
2334 {
2335 if ( (pCtx->cs.Sel & X86_SEL_RPL)
2336 || (pCtx->ds.Sel & X86_SEL_RPL)
2337 || (pCtx->es.Sel & X86_SEL_RPL)
2338 || (pCtx->fs.Sel & X86_SEL_RPL)
2339 || (pCtx->gs.Sel & X86_SEL_RPL)
2340 || (pCtx->ss.Sel & X86_SEL_RPL))
2341 {
2342 return false;
2343 }
2344 }
2345 /* VT-x also chokes on invalid tr or ldtr selectors (minix) */
2346 if ( pCtx->gdtr.cbGdt
2347 && ( pCtx->tr.Sel > pCtx->gdtr.cbGdt
2348 || pCtx->ldtr.Sel > pCtx->gdtr.cbGdt))
2349 {
2350 return false;
2351 }
2352 }
2353 }
2354 else
2355 {
2356 if ( !CPUMIsGuestInLongModeEx(pCtx)
2357 && !pVM->hwaccm.s.vmx.fUnrestrictedGuest)
2358 {
2359 /** @todo This should (probably) be set on every excursion to the REM,
2360 * however it's too risky right now. So, only apply it when we go
2361 * back to REM for real mode execution. (The XP hack below doesn't
2362 * work reliably without this.)
2363 * Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HWACCM. */
2364 pVM->aCpus[0].hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2365
2366 if ( !pVM->hwaccm.s.fNestedPaging /* requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap*/
2367 || CPUMIsGuestInRealModeEx(pCtx)) /* requires a fake TSS for real mode - stored in the VMM device heap */
2368 return false;
2369
2370 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2371 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr.Sel == 0)
2372 return false;
2373
2374 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2375 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2376 * hidden registers (possible recompiler bug; see load_seg_vm) */
2377 if (pCtx->cs.Attr.n.u1Present == 0)
2378 return false;
2379 if (pCtx->ss.Attr.n.u1Present == 0)
2380 return false;
2381
2382 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2383 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2384 /** @todo This check is actually wrong, it doesn't take the direction of the
2385 * stack segment into account. But, it does the job for now. */
2386 if (pCtx->rsp >= pCtx->ss.u32Limit)
2387 return false;
2388#if 0
2389 if ( pCtx->cs.Sel >= pCtx->gdtr.cbGdt
2390 || pCtx->ss.Sel >= pCtx->gdtr.cbGdt
2391 || pCtx->ds.Sel >= pCtx->gdtr.cbGdt
2392 || pCtx->es.Sel >= pCtx->gdtr.cbGdt
2393 || pCtx->fs.Sel >= pCtx->gdtr.cbGdt
2394 || pCtx->gs.Sel >= pCtx->gdtr.cbGdt)
2395 return false;
2396#endif
2397 }
2398 }
2399 }
2400
2401 if (pVM->hwaccm.s.vmx.fEnabled)
2402 {
2403 uint32_t mask;
2404
2405 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2406 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
2407 /* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
2408 mask &= ~X86_CR0_NE;
2409
2410 if (fSupportsRealMode)
2411 {
2412 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2413 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2414 }
2415 else
2416 {
2417 /* We support protected mode without paging using identity mapping. */
2418 mask &= ~X86_CR0_PG;
2419 }
2420 if ((pCtx->cr0 & mask) != mask)
2421 return false;
2422
2423 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2424 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
2425 if ((pCtx->cr0 & mask) != 0)
2426 return false;
2427
2428 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2429 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
2430 mask &= ~X86_CR4_VMXE;
2431 if ((pCtx->cr4 & mask) != mask)
2432 return false;
2433
2434 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2435 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
2436 if ((pCtx->cr4 & mask) != 0)
2437 return false;
2438
2439 pVCpu->hwaccm.s.fActive = true;
2440 return true;
2441 }
2442
2443 return false;
2444}
2445
2446
2447/**
2448 * Checks if we need to reschedule due to VMM device heap changes.
2449 *
2450 * @returns true if a reschedule is required, otherwise false.
2451 * @param pVM Pointer to the VM.
2452 * @param pCtx VM execution context.
2453 */
2454VMMR3DECL(bool) HWACCMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
2455{
2456 /*
2457 * The VMM device heap is a requirement for emulating real mode or protected mode without paging
2458 * when the unrestricted guest execution feature is missing (VT-x only).
2459 */
2460 if ( pVM->hwaccm.s.vmx.fEnabled
2461 && !pVM->hwaccm.s.vmx.fUnrestrictedGuest
2462 && !CPUMIsGuestInPagedProtectedModeEx(pCtx)
2463 && !PDMVMMDevHeapIsEnabled(pVM)
2464 && (pVM->hwaccm.s.fNestedPaging || CPUMIsGuestInRealModeEx(pCtx)))
2465 return true;
2466
2467 return false;
2468}
2469
2470
2471/**
2472 * Notification from EM about a rescheduling into hardware assisted execution
2473 * mode.
2474 *
2475 * @param pVCpu Pointer to the current VMCPU.
2476 */
2477VMMR3DECL(void) HWACCMR3NotifyScheduled(PVMCPU pVCpu)
2478{
2479 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2480}
2481
2482
2483/**
2484 * Notification from EM about returning from instruction emulation (REM / EM).
2485 *
2486 * @param pVCpu Pointer to the VMCPU.
2487 */
2488VMMR3DECL(void) HWACCMR3NotifyEmulated(PVMCPU pVCpu)
2489{
2490 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2491}
2492
2493
2494/**
2495 * Checks if we are currently using hardware accelerated raw mode.
2496 *
2497 * @returns true if hardware acceleration is being used, otherwise false.
2498 * @param pVCpu Pointer to the VMCPU.
2499 */
2500VMMR3DECL(bool) HWACCMR3IsActive(PVMCPU pVCpu)
2501{
2502 return pVCpu->hwaccm.s.fActive;
2503}
2504
2505
2506/**
2507 * Checks if we are currently using nested paging.
2508 *
2509 * @returns true if nested paging is being used, otherwise false.
2510 * @param pVM Pointer to the VM.
2511 */
2512VMMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
2513{
2514 return pVM->hwaccm.s.fNestedPaging;
2515}
2516
2517
2518/**
2519 * Checks if we are currently using VPID in VT-x mode.
2520 *
2521 * @returns true if VPID is being used, otherwise false.
2522 * @param pVM Pointer to the VM.
2523 */
2524VMMR3DECL(bool) HWACCMR3IsVPIDActive(PVM pVM)
2525{
2526 return pVM->hwaccm.s.vmx.fVPID;
2527}
2528
2529
2530/**
2531 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
2532 *
2533 * @returns true if an internal event is pending, otherwise false.
2534 * @param pVM Pointer to the VM.
2535 */
2536VMMR3DECL(bool) HWACCMR3IsEventPending(PVMCPU pVCpu)
2537{
2538 return HWACCMIsEnabled(pVCpu->pVMR3) && pVCpu->hwaccm.s.Event.fPending;
2539}
2540
2541
2542/**
2543 * Checks if the VMX-preemption timer is being used.
2544 *
2545 * @returns true if the VMX-preemption timer is being used, otherwise false.
2546 * @param pVM Pointer to the VM.
2547 */
2548VMMR3DECL(bool) HWACCMR3IsVmxPreemptionTimerUsed(PVM pVM)
2549{
2550 return HWACCMIsEnabled(pVM)
2551 && pVM->hwaccm.s.vmx.fEnabled
2552 && pVM->hwaccm.s.vmx.fUsePreemptTimer;
2553}
2554
2555
2556/**
2557 * Restart an I/O instruction that was refused in ring-0
2558 *
2559 * @returns Strict VBox status code. Informational status codes other than the one documented
2560 * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2561 * @retval VINF_SUCCESS Success.
2562 * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2563 * status code must be passed on to EM.
2564 * @retval VERR_NOT_FOUND if no pending I/O instruction.
2565 *
2566 * @param pVM Pointer to the VM.
2567 * @param pVCpu Pointer to the VMCPU.
2568 * @param pCtx Pointer to the guest CPU context.
2569 */
2570VMMR3DECL(VBOXSTRICTRC) HWACCMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2571{
2572 HWACCMPENDINGIO enmType = pVCpu->hwaccm.s.PendingIO.enmType;
2573
2574 pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_INVALID;
2575
2576 if ( pVCpu->hwaccm.s.PendingIO.GCPtrRip != pCtx->rip
2577 || enmType == HWACCMPENDINGIO_INVALID)
2578 return VERR_NOT_FOUND;
2579
2580 VBOXSTRICTRC rcStrict;
2581 switch (enmType)
2582 {
2583 case HWACCMPENDINGIO_PORT_READ:
2584 {
2585 uint32_t uAndVal = pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal;
2586 uint32_t u32Val = 0;
2587
2588 rcStrict = IOMIOPortRead(pVM, pVCpu->hwaccm.s.PendingIO.s.Port.uPort,
2589 &u32Val,
2590 pVCpu->hwaccm.s.PendingIO.s.Port.cbSize);
2591 if (IOM_SUCCESS(rcStrict))
2592 {
2593 /* Write back to the EAX register. */
2594 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2595 pCtx->rip = pVCpu->hwaccm.s.PendingIO.GCPtrRipNext;
2596 }
2597 break;
2598 }
2599
2600 case HWACCMPENDINGIO_PORT_WRITE:
2601 rcStrict = IOMIOPortWrite(pVM, pVCpu->hwaccm.s.PendingIO.s.Port.uPort,
2602 pCtx->eax & pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal,
2603 pVCpu->hwaccm.s.PendingIO.s.Port.cbSize);
2604 if (IOM_SUCCESS(rcStrict))
2605 pCtx->rip = pVCpu->hwaccm.s.PendingIO.GCPtrRipNext;
2606 break;
2607
2608 default:
2609 AssertLogRelFailedReturn(VERR_HM_UNKNOWN_IO_INSTRUCTION);
2610 }
2611
2612 return rcStrict;
2613}
2614
2615
2616/**
2617 * Inject an NMI into a running VM (only VCPU 0!)
2618 *
2619 * @returns boolean
2620 * @param pVM Pointer to the VM.
2621 */
2622VMMR3DECL(int) HWACCMR3InjectNMI(PVM pVM)
2623{
2624 VMCPU_FF_SET(&pVM->aCpus[0], VMCPU_FF_INTERRUPT_NMI);
2625 return VINF_SUCCESS;
2626}
2627
2628
2629/**
2630 * Check fatal VT-x/AMD-V error and produce some meaningful
2631 * log release message.
2632 *
2633 * @param pVM Pointer to the VM.
2634 * @param iStatusCode VBox status code.
2635 */
2636VMMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode)
2637{
2638 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2639 {
2640 switch(iStatusCode)
2641 {
2642 case VERR_VMX_INVALID_VMCS_FIELD:
2643 break;
2644
2645 case VERR_VMX_INVALID_VMCS_PTR:
2646 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hwaccm.s.vmx.HCPhysVMCS));
2647 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulVMCSRevision));
2648 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idEnteredCpu));
2649 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idCurrentCpu));
2650 break;
2651
2652 case VERR_VMX_UNABLE_TO_START_VM:
2653 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
2654 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
2655#if 0 /* @todo dump the current control fields to the release log */
2656 if (pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
2657 {
2658
2659 }
2660#endif
2661 break;
2662
2663 case VERR_VMX_UNABLE_TO_RESUME_VM:
2664 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
2665 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
2666 break;
2667
2668 case VERR_VMX_INVALID_VMXON_PTR:
2669 break;
2670 }
2671 }
2672}
2673
2674
2675/**
2676 * Execute state save operation.
2677 *
2678 * @returns VBox status code.
2679 * @param pVM Pointer to the VM.
2680 * @param pSSM SSM operation handle.
2681 */
2682static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
2683{
2684 int rc;
2685
2686 Log(("hwaccmR3Save:\n"));
2687
2688 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2689 {
2690 /*
2691 * Save the basic bits - fortunately all the other things can be resynced on load.
2692 */
2693 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.fPending);
2694 AssertRCReturn(rc, rc);
2695 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.errCode);
2696 AssertRCReturn(rc, rc);
2697 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hwaccm.s.Event.intInfo);
2698 AssertRCReturn(rc, rc);
2699
2700 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode);
2701 AssertRCReturn(rc, rc);
2702 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode);
2703 AssertRCReturn(rc, rc);
2704 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode);
2705 AssertRCReturn(rc, rc);
2706 }
2707#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2708 rc = SSMR3PutGCPtr(pSSM, pVM->hwaccm.s.pGuestPatchMem);
2709 AssertRCReturn(rc, rc);
2710 rc = SSMR3PutGCPtr(pSSM, pVM->hwaccm.s.pFreeGuestPatchMem);
2711 AssertRCReturn(rc, rc);
2712 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.cbGuestPatchMem);
2713 AssertRCReturn(rc, rc);
2714
2715 /* Store all the guest patch records too. */
2716 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.cPatches);
2717 AssertRCReturn(rc, rc);
2718
2719 for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
2720 {
2721 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
2722
2723 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
2724 AssertRCReturn(rc, rc);
2725
2726 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2727 AssertRCReturn(rc, rc);
2728
2729 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
2730 AssertRCReturn(rc, rc);
2731
2732 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2733 AssertRCReturn(rc, rc);
2734
2735 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
2736 AssertRCReturn(rc, rc);
2737
2738 AssertCompileSize(HWACCMTPRINSTR, 4);
2739 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
2740 AssertRCReturn(rc, rc);
2741
2742 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
2743 AssertRCReturn(rc, rc);
2744
2745 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
2746 AssertRCReturn(rc, rc);
2747
2748 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
2749 AssertRCReturn(rc, rc);
2750
2751 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
2752 AssertRCReturn(rc, rc);
2753 }
2754#endif
2755 return VINF_SUCCESS;
2756}
2757
2758
2759/**
2760 * Execute state load operation.
2761 *
2762 * @returns VBox status code.
2763 * @param pVM Pointer to the VM.
2764 * @param pSSM SSM operation handle.
2765 * @param uVersion Data layout version.
2766 * @param uPass The data pass.
2767 */
2768static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2769{
2770 int rc;
2771
2772 Log(("hwaccmR3Load:\n"));
2773 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2774
2775 /*
2776 * Validate version.
2777 */
2778 if ( uVersion != HWACCM_SSM_VERSION
2779 && uVersion != HWACCM_SSM_VERSION_NO_PATCHING
2780 && uVersion != HWACCM_SSM_VERSION_2_0_X)
2781 {
2782 AssertMsgFailed(("hwaccmR3Load: Invalid version uVersion=%d!\n", uVersion));
2783 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2784 }
2785 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2786 {
2787 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.fPending);
2788 AssertRCReturn(rc, rc);
2789 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.errCode);
2790 AssertRCReturn(rc, rc);
2791 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hwaccm.s.Event.intInfo);
2792 AssertRCReturn(rc, rc);
2793
2794 if (uVersion >= HWACCM_SSM_VERSION_NO_PATCHING)
2795 {
2796 uint32_t val;
2797
2798 rc = SSMR3GetU32(pSSM, &val);
2799 AssertRCReturn(rc, rc);
2800 pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode = (PGMMODE)val;
2801
2802 rc = SSMR3GetU32(pSSM, &val);
2803 AssertRCReturn(rc, rc);
2804 pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode = (PGMMODE)val;
2805
2806 rc = SSMR3GetU32(pSSM, &val);
2807 AssertRCReturn(rc, rc);
2808 pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode = (PGMMODE)val;
2809 }
2810 }
2811#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2812 if (uVersion > HWACCM_SSM_VERSION_NO_PATCHING)
2813 {
2814 rc = SSMR3GetGCPtr(pSSM, &pVM->hwaccm.s.pGuestPatchMem);
2815 AssertRCReturn(rc, rc);
2816 rc = SSMR3GetGCPtr(pSSM, &pVM->hwaccm.s.pFreeGuestPatchMem);
2817 AssertRCReturn(rc, rc);
2818 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.cbGuestPatchMem);
2819 AssertRCReturn(rc, rc);
2820
2821 /* Fetch all TPR patch records. */
2822 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.cPatches);
2823 AssertRCReturn(rc, rc);
2824
2825 for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
2826 {
2827 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
2828
2829 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
2830 AssertRCReturn(rc, rc);
2831
2832 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2833 AssertRCReturn(rc, rc);
2834
2835 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
2836 AssertRCReturn(rc, rc);
2837
2838 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2839 AssertRCReturn(rc, rc);
2840
2841 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
2842 AssertRCReturn(rc, rc);
2843
2844 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
2845 AssertRCReturn(rc, rc);
2846
2847 if (pPatch->enmType == HWACCMTPRINSTR_JUMP_REPLACEMENT)
2848 pVM->hwaccm.s.fTPRPatchingActive = true;
2849
2850 Assert(pPatch->enmType == HWACCMTPRINSTR_JUMP_REPLACEMENT || pVM->hwaccm.s.fTPRPatchingActive == false);
2851
2852 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
2853 AssertRCReturn(rc, rc);
2854
2855 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
2856 AssertRCReturn(rc, rc);
2857
2858 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
2859 AssertRCReturn(rc, rc);
2860
2861 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
2862 AssertRCReturn(rc, rc);
2863
2864 Log(("hwaccmR3Load: patch %d\n", i));
2865 Log(("Key = %x\n", pPatch->Core.Key));
2866 Log(("cbOp = %d\n", pPatch->cbOp));
2867 Log(("cbNewOp = %d\n", pPatch->cbNewOp));
2868 Log(("type = %d\n", pPatch->enmType));
2869 Log(("srcop = %d\n", pPatch->uSrcOperand));
2870 Log(("dstop = %d\n", pPatch->uDstOperand));
2871 Log(("cFaults = %d\n", pPatch->cFaults));
2872 Log(("target = %x\n", pPatch->pJumpTarget));
2873 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2874 AssertRC(rc);
2875 }
2876 }
2877#endif
2878
2879 /* Recheck all VCPUs if we can go straight into hwaccm execution mode. */
2880 if (HWACCMIsEnabled(pVM))
2881 {
2882 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2883 {
2884 PVMCPU pVCpu = &pVM->aCpus[i];
2885
2886 HWACCMR3CanExecuteGuest(pVM, CPUMQueryGuestCtxPtr(pVCpu));
2887 }
2888 }
2889 return VINF_SUCCESS;
2890}
2891
注意: 瀏覽 TracBrowser 來幫助您使用儲存庫瀏覽器

© 2025 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette