EMRaw.cpp@ 47815

最後變更在這個檔案從47815是 47788,由 vboxsync 提交於 12 年前
EM/HM: Try execute single instructions in IEM before asking REM.
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1	/* $Id: EMRaw.cpp 47788 2013-08-16 09:00:23Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor / Manager - software virtualization
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.alldomusa.eu.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_EM
23	#include <VBox/vmm/em.h>
24	#include <VBox/vmm/vmm.h>
25	#include <VBox/vmm/patm.h>
26	#include <VBox/vmm/csam.h>
27	#include <VBox/vmm/selm.h>
28	#include <VBox/vmm/trpm.h>
29	#include <VBox/vmm/iem.h>
30	#include <VBox/vmm/iom.h>
31	#include <VBox/vmm/dbgf.h>
32	#include <VBox/vmm/pgm.h>
33	#ifdef VBOX_WITH_REM
34	# include <VBox/vmm/rem.h>
35	#endif
36	#include <VBox/vmm/tm.h>
37	#include <VBox/vmm/mm.h>
38	#include <VBox/vmm/ssm.h>
39	#include <VBox/vmm/pdmapi.h>
40	#include <VBox/vmm/pdmcritsect.h>
41	#include <VBox/vmm/pdmqueue.h>
42	#include <VBox/vmm/patm.h>
43	#include "EMInternal.h"
44	#include <VBox/vmm/vm.h>
45	#include <VBox/vmm/cpumdis.h>
46	#include <VBox/dis.h>
47	#include <VBox/disopcode.h>
48	#include <VBox/vmm/dbgf.h>
49	#include "VMMTracing.h"
50
51	#include <VBox/log.h>
52	#include <iprt/asm.h>
53	#include <iprt/string.h>
54	#include <iprt/stream.h>
55
56
57
58	/*******************************************************************************
59	* Internal Functions *
60	*******************************************************************************/
61	static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
62	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS);
63	static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu);
64	static int emR3RawPatchTrap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int gcret);
65	static int emR3RawPrivileged(PVM pVM, PVMCPU pVCpu);
66	static int emR3RawExecuteIOInstruction(PVM pVM, PVMCPU pVCpu);
67	static int emR3RawRingSwitch(PVM pVM, PVMCPU pVCpu);
68
69	#define EMHANDLERC_WITH_PATM
70	#define emR3ExecuteInstruction emR3RawExecuteInstruction
71	#define emR3ExecuteIOInstruction emR3RawExecuteIOInstruction
72	#include "EMHandleRCTmpl.h"
73
74
75
76	#ifdef VBOX_WITH_STATISTICS
77	/**
78	* Just a braindead function to keep track of cli addresses.
79	* @param pVM Pointer to the VM.
80	* @param pVMCPU Pointer to the VMCPU.
81	* @param GCPtrInstr The EIP of the cli instruction.
82	*/
83	static void emR3RecordCli(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtrInstr)
84	{
85	PCLISTAT pRec;
86
87	pRec = (PCLISTAT)RTAvlGCPtrGet(&pVCpu->em.s.pCliStatTree, GCPtrInstr);
88	if (!pRec)
89	{
90	/* New cli instruction; insert into the tree. */
91	pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
92	Assert(pRec);
93	if (!pRec)
94	return;
95	pRec->Core.Key = GCPtrInstr;
96
97	char szCliStatName[32];
98	RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%RGv", GCPtrInstr);
99	STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
100
101	bool fRc = RTAvlGCPtrInsert(&pVCpu->em.s.pCliStatTree, &pRec->Core);
102	Assert(fRc); NOREF(fRc);
103	}
104	STAM_COUNTER_INC(&pRec->Counter);
105	STAM_COUNTER_INC(&pVCpu->em.s.StatTotalClis);
106	}
107	#endif /* VBOX_WITH_STATISTICS */
108
109
110
111	/**
112	* Resumes executing hypervisor after a debug event.
113	*
114	* This is kind of special since our current guest state is
115	* potentially out of sync.
116	*
117	* @returns VBox status code.
118	* @param pVM Pointer to the VM.
119	* @param pVCpu Pointer to the VMCPU.
120	*/
121	int emR3RawResumeHyper(PVM pVM, PVMCPU pVCpu)
122	{
123	int rc;
124	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
125	Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER);
126	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pCtx->cs.Sel, pCtx->eip, pCtx->eflags));
127
128	/*
129	* Resume execution.
130	*/
131	CPUMRawEnter(pVCpu, NULL);
132	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) \| X86_EFL_RF);
133	rc = VMMR3ResumeHyper(pVM, pVCpu);
134	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Rrc\n", pCtx->cs.Sel, pCtx->eip, pCtx->eflags, rc));
135	rc = CPUMRawLeave(pVCpu, NULL, rc);
136	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
137
138	/*
139	* Deal with the return code.
140	*/
141	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
142	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
143	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
144	return rc;
145	}
146
147
148	/**
149	* Steps rawmode.
150	*
151	* @returns VBox status code.
152	* @param pVM Pointer to the VM.
153	* @param pVCpu Pointer to the VMCPU.
154	*/
155	int emR3RawStep(PVM pVM, PVMCPU pVCpu)
156	{
157	Assert( pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER
158	\|\| pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
159	\|\| pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
160	int rc;
161	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
162	bool fGuest = pVCpu->em.s.enmState != EMSTATE_DEBUG_HYPER;
163	#ifndef DEBUG_sander
164	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVCpu) : CPUMGetHyperCS(pVCpu),
165	fGuest ? CPUMGetGuestEIP(pVCpu) : CPUMGetHyperEIP(pVCpu), fGuest ? CPUMGetGuestEFlags(pVCpu) : CPUMGetHyperEFlags(pVCpu)));
166	#endif
167	if (fGuest)
168	{
169	/*
170	* Check vital forced actions, but ignore pending interrupts and timers.
171	*/
172	if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
173	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
174	{
175	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
176	VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
177	if (rc != VINF_SUCCESS)
178	return rc;
179	}
180
181	/*
182	* Set flags for single stepping.
183	*/
184	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) \| X86_EFL_TF \| X86_EFL_RF);
185	}
186	else
187	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) \| X86_EFL_TF \| X86_EFL_RF);
188
189	/*
190	* Single step.
191	* We do not start time or anything, if anything we should just do a few nanoseconds.
192	*/
193	CPUMRawEnter(pVCpu, NULL);
194	do
195	{
196	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER)
197	rc = VMMR3ResumeHyper(pVM, pVCpu);
198	else
199	rc = VMMR3RawRunGC(pVM, pVCpu);
200	#ifndef DEBUG_sander
201	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Rrc\n", fGuest ? CPUMGetGuestCS(pVCpu) : CPUMGetHyperCS(pVCpu),
202	fGuest ? CPUMGetGuestEIP(pVCpu) : CPUMGetHyperEIP(pVCpu), fGuest ? CPUMGetGuestEFlags(pVCpu) : CPUMGetHyperEFlags(pVCpu), rc));
203	#endif
204	} while ( rc == VINF_SUCCESS
205	\|\| rc == VINF_EM_RAW_INTERRUPT);
206	rc = CPUMRawLeave(pVCpu, NULL, rc);
207	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
208
209	/*
210	* Make sure the trap flag is cleared.
211	* (Too bad if the guest is trying to single step too.)
212	*/
213	if (fGuest)
214	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
215	else
216	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) & ~X86_EFL_TF);
217
218	/*
219	* Deal with the return codes.
220	*/
221	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
222	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
223	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
224	return rc;
225	}
226
227
228	#ifdef DEBUG
229
230
231	int emR3SingleStepExecRaw(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
232	{
233	int rc = VINF_SUCCESS;
234	EMSTATE enmOldState = pVCpu->em.s.enmState;
235	pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
236
237	Log(("Single step BEGIN:\n"));
238	for (uint32_t i = 0; i < cIterations; i++)
239	{
240	DBGFR3PrgStep(pVCpu);
241	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "RSS");
242	rc = emR3RawStep(pVM, pVCpu);
243	if ( rc != VINF_SUCCESS
244	&& rc != VINF_EM_DBG_STEPPED)
245	break;
246	}
247	Log(("Single step END: rc=%Rrc\n", rc));
248	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
249	pVCpu->em.s.enmState = enmOldState;
250	return rc;
251	}
252
253	#endif /* DEBUG */
254
255
256	/**
257	* Executes one (or perhaps a few more) instruction(s).
258	*
259	* @returns VBox status code suitable for EM.
260	*
261	* @param pVM Pointer to the VM.
262	* @param pVCpu Pointer to the VMCPU.
263	* @param rcGC GC return code
264	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
265	* instruction and prefix the log output with this text.
266	*/
267	#ifdef LOG_ENABLED
268	static int emR3RawExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC, const char *pszPrefix)
269	#else
270	static int emR3RawExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC)
271	#endif
272	{
273	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
274	int rc;
275
276	/*
277	*
278	* The simple solution is to use the recompiler.
279	* The better solution is to disassemble the current instruction and
280	* try handle as many as possible without using REM.
281	*
282	*/
283
284	#ifdef LOG_ENABLED
285	/*
286	* Disassemble the instruction if requested.
287	*/
288	if (pszPrefix)
289	{
290	DBGFR3_INFO_LOG(pVM, "cpumguest", pszPrefix);
291	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, pszPrefix);
292	}
293	#endif /* LOG_ENABLED */
294
295	/*
296	* PATM is making life more interesting.
297	* We cannot hand anything to REM which has an EIP inside patch code. So, we'll
298	* tell PATM there is a trap in this code and have it take the appropriate actions
299	* to allow us execute the code in REM.
300	*/
301	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
302	{
303	Log(("emR3RawExecuteInstruction: In patch block. eip=%RRv\n", (RTRCPTR)pCtx->eip));
304
305	RTGCPTR pNewEip;
306	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
307	switch (rc)
308	{
309	/*
310	* It's not very useful to emulate a single instruction and then go back to raw
311	* mode; just execute the whole block until IF is set again.
312	*/
313	case VINF_SUCCESS:
314	Log(("emR3RawExecuteInstruction: Executing instruction starting at new address %RGv IF=%d VMIF=%x\n",
315	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
316	pCtx->eip = pNewEip;
317	Assert(pCtx->eip);
318
319	if (pCtx->eflags.Bits.u1IF)
320	{
321	/*
322	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
323	*/
324	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
325	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
326	}
327	else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
328	{
329	/* special case: iret, that sets IF, detected a pending irq/event */
330	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIRET");
331	}
332	return VINF_EM_RESCHEDULE_REM;
333
334	/*
335	* One instruction.
336	*/
337	case VINF_PATCH_EMULATE_INSTR:
338	Log(("emR3RawExecuteInstruction: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
339	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
340	pCtx->eip = pNewEip;
341	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
342
343	/*
344	* The patch was disabled, hand it to the REM.
345	*/
346	case VERR_PATCH_DISABLED:
347	Log(("emR3RawExecuteInstruction: Disabled patch -> new eip %RGv IF=%d VMIF=%x\n",
348	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
349	pCtx->eip = pNewEip;
350	if (pCtx->eflags.Bits.u1IF)
351	{
352	/*
353	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
354	*/
355	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
356	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
357	}
358	return VINF_EM_RESCHEDULE_REM;
359
360	/* Force continued patch exection; usually due to write monitored stack. */
361	case VINF_PATCH_CONTINUE:
362	return VINF_SUCCESS;
363
364	default:
365	AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap\n", rc));
366	return VERR_IPE_UNEXPECTED_STATUS;
367	}
368	}
369
370	STAM_PROFILE_START(&pVCpu->em.s.StatREMEmu, a);
371	Log(("EMINS: %04x:%RGv RSP=%RGv\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip, (RTGCPTR)pCtx->rsp));
372	#ifdef VBOX_WITH_REM
373	EMRemLock(pVM);
374	/* Flush the recompiler TLB if the VCPU has changed. */
375	if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
376	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
377	pVM->em.s.idLastRemCpu = pVCpu->idCpu;
378
379	rc = REMR3EmulateInstruction(pVM, pVCpu);
380	EMRemUnlock(pVM);
381	#else
382	rc = VBOXSTRICTRC_TODO(IEMExecOne(pVCpu));
383	#endif
384	STAM_PROFILE_STOP(&pVCpu->em.s.StatREMEmu, a);
385
386	return rc;
387	}
388
389
390	/**
391	* Executes one (or perhaps a few more) instruction(s).
392	* This is just a wrapper for discarding pszPrefix in non-logging builds.
393	*
394	* @returns VBox status code suitable for EM.
395	* @param pVM Pointer to the VM.
396	* @param pVCpu Pointer to the VMCPU.
397	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
398	* instruction and prefix the log output with this text.
399	* @param rcGC GC return code
400	*/
401	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC)
402	{
403	#ifdef LOG_ENABLED
404	return emR3RawExecuteInstructionWorker(pVM, pVCpu, rcGC, pszPrefix);
405	#else
406	return emR3RawExecuteInstructionWorker(pVM, pVCpu, rcGC);
407	#endif
408	}
409
410	/**
411	* Executes one (or perhaps a few more) IO instruction(s).
412	*
413	* @returns VBox status code suitable for EM.
414	* @param pVM Pointer to the VM.
415	* @param pVCpu Pointer to the VMCPU.
416	*/
417	static int emR3RawExecuteIOInstruction(PVM pVM, PVMCPU pVCpu)
418	{
419	#ifdef VBOX_WITH_FIRST_IEM_STEP
420	STAM_PROFILE_START(&pVCpu->em.s.StatIOEmu, a);
421
422	/* Hand it over to the interpreter. */
423	VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
424	LogFlow(("emR3RawExecuteIOInstruction: %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
425	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIoIem);
426	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
427	return VBOXSTRICTRC_TODO(rcStrict);
428
429	#else
430	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
431
432	STAM_PROFILE_START(&pVCpu->em.s.StatIOEmu, a);
433
434	/** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
435	* as io instructions tend to come in packages of more than one
436	*/
437	DISCPUSTATE Cpu;
438	int rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "IO EMU");
439	if (RT_SUCCESS(rc))
440	{
441	VBOXSTRICTRC rcStrict = VINF_EM_RAW_EMULATE_INSTR;
442
443	if (!(Cpu.fPrefix & (DISPREFIX_REP \| DISPREFIX_REPNE)))
444	{
445	switch (Cpu.pCurInstr->uOpcode)
446	{
447	case OP_IN:
448	{
449	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
450	rcStrict = IOMInterpretIN(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu);
451	break;
452	}
453
454	case OP_OUT:
455	{
456	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
457	rcStrict = IOMInterpretOUT(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu);
458	break;
459	}
460	}
461	}
462	else if (Cpu.fPrefix & DISPREFIX_REP)
463	{
464	switch (Cpu.pCurInstr->uOpcode)
465	{
466	case OP_INSB:
467	case OP_INSWD:
468	{
469	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
470	rcStrict = IOMInterpretINS(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu);
471	break;
472	}
473
474	case OP_OUTSB:
475	case OP_OUTSWD:
476	{
477	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
478	rcStrict = IOMInterpretOUTS(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu);
479	break;
480	}
481	}
482	}
483
484	/*
485	* Handled the I/O return codes.
486	* (The unhandled cases end up with rcStrict == VINF_EM_RAW_EMULATE_INSTR.)
487	*/
488	if (IOM_SUCCESS(rcStrict))
489	{
490	pCtx->rip += Cpu.cbInstr;
491	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
492	return VBOXSTRICTRC_TODO(rcStrict);
493	}
494
495	if (rcStrict == VINF_EM_RAW_GUEST_TRAP)
496	{
497	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
498	rcStrict = emR3RawGuestTrap(pVM, pVCpu);
499	return VBOXSTRICTRC_TODO(rcStrict);
500	}
501	AssertMsg(rcStrict != VINF_TRPM_XCPT_DISPATCHED, ("Handle VINF_TRPM_XCPT_DISPATCHED\n"));
502
503	if (RT_FAILURE(rcStrict))
504	{
505	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
506	return VBOXSTRICTRC_TODO(rcStrict);
507	}
508	AssertMsg(rcStrict == VINF_EM_RAW_EMULATE_INSTR \|\| rcStrict == VINF_EM_RESCHEDULE_REM, ("rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
509	}
510	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
511	return emR3RawExecuteInstruction(pVM, pVCpu, "IO: ");
512	#endif
513	}
514
515
516	/**
517	* Handle a guest context trap.
518	*
519	* @returns VBox status code suitable for EM.
520	* @param pVM Pointer to the VM.
521	* @param pVCpu Pointer to the VMCPU.
522	*/
523	static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu)
524	{
525	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
526
527	/*
528	* Get the trap info.
529	*/
530	uint8_t u8TrapNo;
531	TRPMEVENT enmType;
532	RTGCUINT uErrorCode;
533	RTGCUINTPTR uCR2;
534	int rc = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrorCode, &uCR2, NULL /* pu8InstrLen */);
535	if (RT_FAILURE(rc))
536	{
537	AssertReleaseMsgFailed(("No trap! (rc=%Rrc)\n", rc));
538	return rc;
539	}
540
541
542	#if 1 /* Experimental: Review, disable if it causes trouble. */
543	/*
544	* Handle traps in patch code first.
545	*
546	* We catch a few of these cases in RC before returning to R3 (#PF, #GP, #BP)
547	* but several traps isn't handled specially by TRPM in RC and we end up here
548	* instead. One example is #DE.
549	*/
550	uint32_t uCpl = CPUMGetGuestCPL(pVCpu);
551	if ( uCpl == 0
552	&& PATMIsPatchGCAddr(pVM, pCtx->eip))
553	{
554	LogFlow(("emR3RawGuestTrap: trap %#x in patch code; eip=%08x\n", u8TrapNo, pCtx->eip));
555	return emR3RawPatchTrap(pVM, pVCpu, pCtx, rc);
556	}
557	#endif
558
559	/*
560	* If the guest gate is marked unpatched, then we will check again if we can patch it.
561	* (This assumes that we've already tried and failed to dispatch the trap in
562	* RC for the gates that already has been patched. Which is true for most high
563	* volume traps, because these are handled specially, but not for odd ones like #DE.)
564	*/
565	if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) == TRPM_INVALID_HANDLER)
566	{
567	CSAMR3CheckGates(pVM, u8TrapNo, 1);
568	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8TrapNo, TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER));
569
570	/* If it was successful, then we could go back to raw mode. */
571	if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER)
572	{
573	/* Must check pending forced actions as our IDT or GDT might be out of sync. */
574	rc = EMR3CheckRawForcedActions(pVM, pVCpu);
575	AssertRCReturn(rc, rc);
576
577	TRPMERRORCODE enmError = uErrorCode != ~0U
578	? TRPM_TRAP_HAS_ERRORCODE
579	: TRPM_TRAP_NO_ERRORCODE;
580	rc = TRPMForwardTrap(pVCpu, CPUMCTX2CORE(pCtx), u8TrapNo, uErrorCode, enmError, TRPM_TRAP, -1);
581	if (rc == VINF_SUCCESS /* Don't use RT_SUCCESS */)
582	{
583	TRPMResetTrap(pVCpu);
584	return VINF_EM_RESCHEDULE_RAW;
585	}
586	AssertMsg(rc == VINF_EM_RAW_GUEST_TRAP, ("%Rrc\n", rc));
587	}
588	}
589
590	/*
591	* Scan kernel code that traps; we might not get another chance.
592	*/
593	/** @todo move this up before the dispatching? */
594	if ( (pCtx->ss.Sel & X86_SEL_RPL) <= 1
595	&& !pCtx->eflags.Bits.u1VM)
596	{
597	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
598	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
599	}
600
601	/*
602	* Trap specific handling.
603	*/
604	if (u8TrapNo == 6) /* (#UD) Invalid opcode. */
605	{
606	/*
607	* If MONITOR & MWAIT are supported, then interpret them here.
608	*/
609	DISCPUSTATE cpu;
610	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &cpu, "Guest Trap (#UD): ");
611	if ( RT_SUCCESS(rc)
612	&& (cpu.pCurInstr->uOpcode == OP_MONITOR \|\| cpu.pCurInstr->uOpcode == OP_MWAIT))
613	{
614	uint32_t u32Dummy, u32Features, u32ExtFeatures;
615	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Features);
616	if (u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR)
617	{
618	rc = TRPMResetTrap(pVCpu);
619	AssertRC(rc);
620
621	rc = VBOXSTRICTRC_TODO(EMInterpretInstructionDisasState(pVCpu, &cpu, CPUMCTX2CORE(pCtx), 0, EMCODETYPE_SUPERVISOR));
622	if (RT_SUCCESS(rc))
623	return rc;
624	return emR3RawExecuteInstruction(pVM, pVCpu, "Monitor: ");
625	}
626	}
627	}
628	else if (u8TrapNo == 13) /* (#GP) Privileged exception */
629	{
630	/*
631	* Handle I/O bitmap?
632	*/
633	/** @todo We're not supposed to be here with a false guest trap concerning
634	* I/O access. We can easily handle those in RC. */
635	DISCPUSTATE cpu;
636	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &cpu, "Guest Trap: ");
637	if ( RT_SUCCESS(rc)
638	&& (cpu.pCurInstr->fOpType & DISOPTYPE_PORTIO))
639	{
640	/*
641	* We should really check the TSS for the IO bitmap, but it's not like this
642	* lazy approach really makes things worse.
643	*/
644	rc = TRPMResetTrap(pVCpu);
645	AssertRC(rc);
646	return emR3RawExecuteInstruction(pVM, pVCpu, "IO Guest Trap: ");
647	}
648	}
649
650	#ifdef LOG_ENABLED
651	DBGFR3_INFO_LOG(pVM, "cpumguest", "Guest trap");
652	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Guest trap");
653
654	/* Get guest page information. */
655	uint64_t fFlags = 0;
656	RTGCPHYS GCPhys = 0;
657	int rc2 = PGMGstGetPage(pVCpu, uCR2, &fFlags, &GCPhys);
658	Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%RGp fFlags=%08llx %s %s %s%s rc2=%d\n",
659	pCtx->cs.Sel, pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0,
660	(enmType == TRPM_SOFTWARE_INT) ? " software" : "", GCPhys, fFlags,
661	fFlags & X86_PTE_P ? "P " : "NP", fFlags & X86_PTE_US ? "U" : "S",
662	fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G ? " G" : "", rc2));
663	#endif
664
665	/*
666	* #PG has CR2.
667	* (Because of stuff like above we must set CR2 in a delayed fashion.)
668	*/
669	if (u8TrapNo == 14 /* #PG */)
670	pCtx->cr2 = uCR2;
671
672	return VINF_EM_RESCHEDULE_REM;
673	}
674
675
676	/**
677	* Handle a ring switch trap.
678	* Need to do statistics and to install patches. The result is going to REM.
679	*
680	* @returns VBox status code suitable for EM.
681	* @param pVM Pointer to the VM.
682	* @param pVCpu Pointer to the VMCPU.
683	*/
684	static int emR3RawRingSwitch(PVM pVM, PVMCPU pVCpu)
685	{
686	int rc;
687	DISCPUSTATE Cpu;
688	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
689
690	/*
691	* sysenter, syscall & callgate
692	*/
693	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "RSWITCH: ");
694	if (RT_SUCCESS(rc))
695	{
696	if (Cpu.pCurInstr->uOpcode == OP_SYSENTER)
697	{
698	if (pCtx->SysEnter.cs != 0)
699	{
700	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
701	CPUMGetGuestCodeBits(pVCpu) == 32 ? PATMFL_CODE32 : 0);
702	if (RT_SUCCESS(rc))
703	{
704	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Patched sysenter instruction");
705	return VINF_EM_RESCHEDULE_RAW;
706	}
707	}
708	}
709
710	#ifdef VBOX_WITH_STATISTICS
711	switch (Cpu.pCurInstr->uOpcode)
712	{
713	case OP_SYSENTER:
714	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysEnter);
715	break;
716	case OP_SYSEXIT:
717	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysExit);
718	break;
719	case OP_SYSCALL:
720	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysCall);
721	break;
722	case OP_SYSRET:
723	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysRet);
724	break;
725	}
726	#endif
727	}
728	else
729	AssertRC(rc);
730
731	/* go to the REM to emulate a single instruction */
732	return emR3RawExecuteInstruction(pVM, pVCpu, "RSWITCH: ");
733	}
734
735
736	/**
737	* Handle a trap (\#PF or \#GP) in patch code
738	*
739	* @returns VBox status code suitable for EM.
740	* @param pVM Pointer to the VM.
741	* @param pVCpu Pointer to the VMCPU.
742	* @param pCtx Pointer to the guest CPU context.
743	* @param gcret GC return code.
744	*/
745	static int emR3RawPatchTrap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int gcret)
746	{
747	uint8_t u8TrapNo;
748	int rc;
749	TRPMEVENT enmType;
750	RTGCUINT uErrorCode;
751	RTGCUINTPTR uCR2;
752
753	Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
754
755	if (gcret == VINF_PATM_PATCH_INT3)
756	{
757	u8TrapNo = 3;
758	uCR2 = 0;
759	uErrorCode = 0;
760	}
761	else if (gcret == VINF_PATM_PATCH_TRAP_GP)
762	{
763	/* No active trap in this case. Kind of ugly. */
764	u8TrapNo = X86_XCPT_GP;
765	uCR2 = 0;
766	uErrorCode = 0;
767	}
768	else
769	{
770	rc = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrorCode, &uCR2, NULL /* pu8InstrLen */);
771	if (RT_FAILURE(rc))
772	{
773	AssertReleaseMsgFailed(("emR3RawPatchTrap: no trap! (rc=%Rrc) gcret=%Rrc\n", rc, gcret));
774	return rc;
775	}
776	/* Reset the trap as we'll execute the original instruction again. */
777	TRPMResetTrap(pVCpu);
778	}
779
780	/*
781	* Deal with traps inside patch code.
782	* (This code won't run outside GC.)
783	*/
784	if (u8TrapNo != 1)
785	{
786	#ifdef LOG_ENABLED
787	DBGFR3_INFO_LOG(pVM, "cpumguest", "Trap in patch code");
788	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Patch code");
789
790	DISCPUSTATE Cpu;
791	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->eip, &Cpu, "Patch code: ");
792	if ( RT_SUCCESS(rc)
793	&& Cpu.pCurInstr->uOpcode == OP_IRET)
794	{
795	uint32_t eip, selCS, uEFlags;
796
797	/* Iret crashes are bad as we have already changed the flags on the stack */
798	rc = PGMPhysSimpleReadGCPtr(pVCpu, &eip, pCtx->esp, 4);
799	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selCS, pCtx->esp+4, 4);
800	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &uEFlags, pCtx->esp+8, 4);
801	if (rc == VINF_SUCCESS)
802	{
803	if ( (uEFlags & X86_EFL_VM)
804	\|\| (selCS & X86_SEL_RPL) == 3)
805	{
806	uint32_t selSS, esp;
807
808	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &esp, pCtx->esp + 12, 4);
809	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selSS, pCtx->esp + 16, 4);
810
811	if (uEFlags & X86_EFL_VM)
812	{
813	uint32_t selDS, selES, selFS, selGS;
814	rc = PGMPhysSimpleReadGCPtr(pVCpu, &selES, pCtx->esp + 20, 4);
815	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selDS, pCtx->esp + 24, 4);
816	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selFS, pCtx->esp + 28, 4);
817	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selGS, pCtx->esp + 32, 4);
818	if (rc == VINF_SUCCESS)
819	{
820	Log(("Patch code: IRET->VM stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
821	Log(("Patch code: IRET->VM stack frame: DS=%04X ES=%04X FS=%04X GS=%04X\n", selDS, selES, selFS, selGS));
822	}
823	}
824	else
825	Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
826	}
827	else
828	Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x\n", selCS, eip, uEFlags));
829	}
830	}
831	#endif /* LOG_ENABLED */
832	Log(("emR3RawPatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
833	pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0));
834
835	RTGCPTR pNewEip;
836	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
837	switch (rc)
838	{
839	/*
840	* Execute the faulting instruction.
841	*/
842	case VINF_SUCCESS:
843	{
844	/** @todo execute a whole block */
845	Log(("emR3RawPatchTrap: Executing faulting instruction at new address %RGv\n", pNewEip));
846	if (!(pVCpu->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
847	Log(("emR3RawPatchTrap: Virtual IF flag disabled!!\n"));
848
849	pCtx->eip = pNewEip;
850	AssertRelease(pCtx->eip);
851
852	if (pCtx->eflags.Bits.u1IF)
853	{
854	/* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
855	* int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
856	*/
857	if ( u8TrapNo == X86_XCPT_GP
858	&& PATMIsInt3Patch(pVM, pCtx->eip, NULL, NULL))
859	{
860	/** @todo move to PATMR3HandleTrap */
861	Log(("Possible Windows XP iret fault at %08RX32\n", pCtx->eip));
862	PATMR3RemovePatch(pVM, pCtx->eip);
863	}
864
865	/** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
866	/* Note: possibly because a reschedule is required (e.g. iret to V86 code) */
867
868	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
869	/* Interrupts are enabled; just go back to the original instruction.
870	return VINF_SUCCESS; */
871	}
872	return VINF_EM_RESCHEDULE_REM;
873	}
874
875	/*
876	* One instruction.
877	*/
878	case VINF_PATCH_EMULATE_INSTR:
879	Log(("emR3RawPatchTrap: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
880	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
881	pCtx->eip = pNewEip;
882	AssertRelease(pCtx->eip);
883	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHEMUL: ");
884
885	/*
886	* The patch was disabled, hand it to the REM.
887	*/
888	case VERR_PATCH_DISABLED:
889	if (!(pVCpu->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
890	Log(("emR3RawPatchTrap: Virtual IF flag disabled!!\n"));
891	pCtx->eip = pNewEip;
892	AssertRelease(pCtx->eip);
893
894	if (pCtx->eflags.Bits.u1IF)
895	{
896	/*
897	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
898	*/
899	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
900	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
901	}
902	return VINF_EM_RESCHEDULE_REM;
903
904	/* Force continued patch exection; usually due to write monitored stack. */
905	case VINF_PATCH_CONTINUE:
906	return VINF_SUCCESS;
907
908	/*
909	* Anything else is fatal.
910	*/
911	default:
912	AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap!\n", rc));
913	return VERR_IPE_UNEXPECTED_STATUS;
914	}
915	}
916	return VINF_SUCCESS;
917	}
918
919
920	/**
921	* Handle a privileged instruction.
922	*
923	* @returns VBox status code suitable for EM.
924	* @param pVM Pointer to the VM.
925	* @param pVCpu Pointer to the VMCPU.
926	*/
927	static int emR3RawPrivileged(PVM pVM, PVMCPU pVCpu)
928	{
929	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
930
931	Assert(!pCtx->eflags.Bits.u1VM);
932
933	if (PATMIsEnabled(pVM))
934	{
935	/*
936	* Check if in patch code.
937	*/
938	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
939	{
940	#ifdef LOG_ENABLED
941	DBGFR3_INFO_LOG(pVM, "cpumguest", "PRIV");
942	#endif
943	AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08x\n", pCtx->eip));
944	return VERR_EM_RAW_PATCH_CONFLICT;
945	}
946	if ( (pCtx->ss.Sel & X86_SEL_RPL) == 0
947	&& !pCtx->eflags.Bits.u1VM
948	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
949	{
950	int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
951	CPUMGetGuestCodeBits(pVCpu) == 32 ? PATMFL_CODE32 : 0);
952	if (RT_SUCCESS(rc))
953	{
954	#ifdef LOG_ENABLED
955	DBGFR3_INFO_LOG(pVM, "cpumguest", "PRIV");
956	#endif
957	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Patched privileged instruction");
958	return VINF_SUCCESS;
959	}
960	}
961	}
962
963	#ifdef LOG_ENABLED
964	if (!PATMIsPatchGCAddr(pVM, pCtx->eip))
965	{
966	DBGFR3_INFO_LOG(pVM, "cpumguest", "PRIV");
967	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Privileged instr");
968	}
969	#endif
970
971	/*
972	* Instruction statistics and logging.
973	*/
974	DISCPUSTATE Cpu;
975	int rc;
976
977	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "PRIV: ");
978	if (RT_SUCCESS(rc))
979	{
980	#ifdef VBOX_WITH_STATISTICS
981	PEMSTATS pStats = pVCpu->em.s.CTX_SUFF(pStats);
982	switch (Cpu.pCurInstr->uOpcode)
983	{
984	case OP_INVLPG:
985	STAM_COUNTER_INC(&pStats->StatInvlpg);
986	break;
987	case OP_IRET:
988	STAM_COUNTER_INC(&pStats->StatIret);
989	break;
990	case OP_CLI:
991	STAM_COUNTER_INC(&pStats->StatCli);
992	emR3RecordCli(pVM, pVCpu, pCtx->rip);
993	break;
994	case OP_STI:
995	STAM_COUNTER_INC(&pStats->StatSti);
996	break;
997	case OP_INSB:
998	case OP_INSWD:
999	case OP_IN:
1000	case OP_OUTSB:
1001	case OP_OUTSWD:
1002	case OP_OUT:
1003	AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
1004	break;
1005
1006	case OP_MOV_CR:
1007	if (Cpu.Param1.fUse & DISUSE_REG_GEN32)
1008	{
1009	//read
1010	Assert(Cpu.Param2.fUse & DISUSE_REG_CR);
1011	Assert(Cpu.Param2.Base.idxCtrlReg <= DISCREG_CR4);
1012	STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.Param2.Base.idxCtrlReg]);
1013	}
1014	else
1015	{
1016	//write
1017	Assert(Cpu.Param1.fUse & DISUSE_REG_CR);
1018	Assert(Cpu.Param1.Base.idxCtrlReg <= DISCREG_CR4);
1019	STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.Param1.Base.idxCtrlReg]);
1020	}
1021	break;
1022
1023	case OP_MOV_DR:
1024	STAM_COUNTER_INC(&pStats->StatMovDRx);
1025	break;
1026	case OP_LLDT:
1027	STAM_COUNTER_INC(&pStats->StatMovLldt);
1028	break;
1029	case OP_LIDT:
1030	STAM_COUNTER_INC(&pStats->StatMovLidt);
1031	break;
1032	case OP_LGDT:
1033	STAM_COUNTER_INC(&pStats->StatMovLgdt);
1034	break;
1035	case OP_SYSENTER:
1036	STAM_COUNTER_INC(&pStats->StatSysEnter);
1037	break;
1038	case OP_SYSEXIT:
1039	STAM_COUNTER_INC(&pStats->StatSysExit);
1040	break;
1041	case OP_SYSCALL:
1042	STAM_COUNTER_INC(&pStats->StatSysCall);
1043	break;
1044	case OP_SYSRET:
1045	STAM_COUNTER_INC(&pStats->StatSysRet);
1046	break;
1047	case OP_HLT:
1048	STAM_COUNTER_INC(&pStats->StatHlt);
1049	break;
1050	default:
1051	STAM_COUNTER_INC(&pStats->StatMisc);
1052	Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->uOpcode));
1053	break;
1054	}
1055	#endif /* VBOX_WITH_STATISTICS */
1056	if ( (pCtx->ss.Sel & X86_SEL_RPL) == 0
1057	&& !pCtx->eflags.Bits.u1VM
1058	&& CPUMGetGuestCodeBits(pVCpu) == 32)
1059	{
1060	STAM_PROFILE_START(&pVCpu->em.s.StatPrivEmu, a);
1061	switch (Cpu.pCurInstr->uOpcode)
1062	{
1063	case OP_CLI:
1064	pCtx->eflags.u32 &= ~X86_EFL_IF;
1065	Assert(Cpu.cbInstr == 1);
1066	pCtx->rip += Cpu.cbInstr;
1067	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1068	return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
1069
1070	case OP_STI:
1071	pCtx->eflags.u32 \|= X86_EFL_IF;
1072	EMSetInhibitInterruptsPC(pVCpu, pCtx->rip + Cpu.cbInstr);
1073	Assert(Cpu.cbInstr == 1);
1074	pCtx->rip += Cpu.cbInstr;
1075	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1076	return VINF_SUCCESS;
1077
1078	case OP_HLT:
1079	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1080	{
1081	PATMTRANSSTATE enmState;
1082	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->eip, &enmState);
1083
1084	if (enmState == PATMTRANS_OVERWRITTEN)
1085	{
1086	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1087	Assert(rc == VERR_PATCH_DISABLED);
1088	/* Conflict detected, patch disabled */
1089	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %08RX32\n", pCtx->eip));
1090
1091	enmState = PATMTRANS_SAFE;
1092	}
1093
1094	/* The translation had better be successful. Otherwise we can't recover. */
1095	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %08RX32\n", pCtx->eip));
1096	if (enmState != PATMTRANS_OVERWRITTEN)
1097	pCtx->eip = pOrgInstrGC;
1098	}
1099	/* no break; we could just return VINF_EM_HALT here */
1100
1101	case OP_MOV_CR:
1102	case OP_MOV_DR:
1103	#ifdef LOG_ENABLED
1104	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1105	{
1106	DBGFR3_INFO_LOG(pVM, "cpumguest", "PRIV");
1107	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Privileged instr");
1108	}
1109	#endif
1110
1111	rc = VBOXSTRICTRC_TODO(EMInterpretInstructionDisasState(pVCpu, &Cpu, CPUMCTX2CORE(pCtx), 0, EMCODETYPE_SUPERVISOR));
1112	if (RT_SUCCESS(rc))
1113	{
1114	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1115
1116	if ( Cpu.pCurInstr->uOpcode == OP_MOV_CR
1117	&& Cpu.Param1.fUse == DISUSE_REG_CR /* write */
1118	)
1119	{
1120	/* Deal with CR0 updates inside patch code that force
1121	* us to go to the recompiler.
1122	*/
1123	if ( PATMIsPatchGCAddr(pVM, pCtx->rip)
1124	&& (pCtx->cr0 & (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE)) != (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE))
1125	{
1126	PATMTRANSSTATE enmState;
1127	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->rip, &enmState);
1128
1129	Log(("Force recompiler switch due to cr0 (%RGp) update rip=%RGv -> %RGv (enmState=%d)\n", pCtx->cr0, pCtx->rip, pOrgInstrGC, enmState));
1130	if (enmState == PATMTRANS_OVERWRITTEN)
1131	{
1132	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1133	Assert(rc == VERR_PATCH_DISABLED);
1134	/* Conflict detected, patch disabled */
1135	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %RGv\n", (RTGCPTR)pCtx->rip));
1136	enmState = PATMTRANS_SAFE;
1137	}
1138	/* The translation had better be successful. Otherwise we can't recover. */
1139	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %RGv\n", (RTGCPTR)pCtx->rip));
1140	if (enmState != PATMTRANS_OVERWRITTEN)
1141	pCtx->rip = pOrgInstrGC;
1142	}
1143
1144	/* Reschedule is necessary as the execution/paging mode might have changed. */
1145	return VINF_EM_RESCHEDULE;
1146	}
1147	return rc; /* can return VINF_EM_HALT as well. */
1148	}
1149	AssertMsgReturn(rc == VERR_EM_INTERPRETER, ("%Rrc\n", rc), rc);
1150	break; /* fall back to the recompiler */
1151	}
1152	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1153	}
1154	}
1155
1156	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1157	return emR3RawPatchTrap(pVM, pVCpu, pCtx, VINF_PATM_PATCH_TRAP_GP);
1158
1159	return emR3RawExecuteInstruction(pVM, pVCpu, "PRIV");
1160	}
1161
1162
1163	/**
1164	* Update the forced rawmode execution modifier.
1165	*
1166	* This function is called when we're returning from the raw-mode loop(s). If we're
1167	* in patch code, it will set a flag forcing execution to be resumed in raw-mode,
1168	* if not in patch code, the flag will be cleared.
1169	*
1170	* We should never interrupt patch code while it's being executed. Cli patches can
1171	* contain big code blocks, but they are always executed with IF=0. Other patches
1172	* replace single instructions and should be atomic.
1173	*
1174	* @returns Updated rc.
1175	*
1176	* @param pVM Pointer to the VM.
1177	* @param pVCpu Pointer to the VMCPU.
1178	* @param pCtx Pointer to the guest CPU context.
1179	* @param rc The result code.
1180	*/
1181	int emR3RawUpdateForceFlag(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc)
1182	{
1183	if (PATMIsPatchGCAddr(pVM, pCtx->eip)) /** @todo check cs selector base/type */
1184	{
1185	/* ignore reschedule attempts. */
1186	switch (rc)
1187	{
1188	case VINF_EM_RESCHEDULE:
1189	case VINF_EM_RESCHEDULE_REM:
1190	LogFlow(("emR3RawUpdateForceFlag: patch address -> force raw reschedule\n"));
1191	rc = VINF_SUCCESS;
1192	break;
1193	}
1194	pVCpu->em.s.fForceRAW = true;
1195	}
1196	else
1197	pVCpu->em.s.fForceRAW = false;
1198	return rc;
1199	}
1200
1201
1202	/**
1203	* Check for pending raw actions
1204	*
1205	* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
1206	* EM statuses.
1207	* @param pVM Pointer to the VM.
1208	* @param pVCpu Pointer to the VMCPU.
1209	*/
1210	VMMR3_INT_DECL(int) EMR3CheckRawForcedActions(PVM pVM, PVMCPU pVCpu)
1211	{
1212	int rc = emR3RawForcedActions(pVM, pVCpu, pVCpu->em.s.pCtx);
1213	VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
1214	return rc;
1215	}
1216
1217
1218	/**
1219	* Process raw-mode specific forced actions.
1220	*
1221	* This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
1222	*
1223	* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
1224	* EM statuses.
1225	* @param pVM Pointer to the VM.
1226	* @param pVCpu Pointer to the VMCPU.
1227	* @param pCtx Pointer to the guest CPU context.
1228	*/
1229	static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1230	{
1231	/*
1232	* Note that the order is vitally important!
1233	* Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
1234	*/
1235	VBOXVMM_EM_FF_RAW(pVCpu, pVM->fGlobalForcedActions, pVCpu->fLocalForcedActions);
1236
1237	/*
1238	* Sync selector tables.
1239	*/
1240	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT))
1241	{
1242	VBOXSTRICTRC rcStrict = SELMR3UpdateFromCPUM(pVM, pVCpu);
1243	if (rcStrict != VINF_SUCCESS)
1244	return VBOXSTRICTRC_TODO(rcStrict);
1245	}
1246
1247	/*
1248	* Sync IDT.
1249	*
1250	* The CSAMR3CheckGates call in TRPMR3SyncIDT may call PGMPrefetchPage
1251	* and PGMShwModifyPage, so we're in for trouble if for instance a
1252	* PGMSyncCR3+pgmR3PoolClearAll is pending.
1253	*/
1254	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TRPM_SYNC_IDT))
1255	{
1256	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1257	&& EMIsRawRing0Enabled(pVM)
1258	&& CSAMIsEnabled(pVM))
1259	{
1260	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1261	if (RT_FAILURE(rc))
1262	return rc;
1263	}
1264
1265	int rc = TRPMR3SyncIDT(pVM, pVCpu);
1266	if (RT_FAILURE(rc))
1267	return rc;
1268	}
1269
1270	/*
1271	* Sync TSS.
1272	*/
1273	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
1274	{
1275	int rc = SELMR3SyncTSS(pVM, pVCpu);
1276	if (RT_FAILURE(rc))
1277	return rc;
1278	}
1279
1280	/*
1281	* Sync page directory.
1282	*/
1283	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
1284	{
1285	Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI);
1286	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1287	if (RT_FAILURE(rc))
1288	return rc;
1289
1290	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT));
1291
1292	/* Prefetch pages for EIP and ESP. */
1293	/** @todo This is rather expensive. Should investigate if it really helps at all. */
1294	rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), pCtx->rip));
1295	if (rc == VINF_SUCCESS)
1296	rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DISSELREG_SS, CPUMCTX2CORE(pCtx), pCtx->rsp));
1297	if (rc != VINF_SUCCESS)
1298	{
1299	if (rc != VINF_PGM_SYNC_CR3)
1300	{
1301	AssertLogRelMsgReturn(RT_FAILURE(rc), ("%Rrc\n", rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
1302	return rc;
1303	}
1304	rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1305	if (RT_FAILURE(rc))
1306	return rc;
1307	}
1308	/** @todo maybe prefetch the supervisor stack page as well */
1309	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT));
1310	}
1311
1312	/*
1313	* Allocate handy pages (just in case the above actions have consumed some pages).
1314	*/
1315	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
1316	{
1317	int rc = PGMR3PhysAllocateHandyPages(pVM);
1318	if (RT_FAILURE(rc))
1319	return rc;
1320	}
1321
1322	/*
1323	* Check whether we're out of memory now.
1324	*
1325	* This may stem from some of the above actions or operations that has been executed
1326	* since we ran FFs. The allocate handy pages must for instance always be followed by
1327	* this check.
1328	*/
1329	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
1330	return VINF_EM_NO_MEMORY;
1331
1332	return VINF_SUCCESS;
1333	}
1334
1335
1336	/**
1337	* Executes raw code.
1338	*
1339	* This function contains the raw-mode version of the inner
1340	* execution loop (the outer loop being in EMR3ExecuteVM()).
1341	*
1342	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
1343	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
1344	*
1345	* @param pVM Pointer to the VM.
1346	* @param pVCpu Pointer to the VMCPU.
1347	* @param pfFFDone Where to store an indicator telling whether or not
1348	* FFs were done before returning.
1349	*/
1350	int emR3RawExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
1351	{
1352	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatRAWTotal, a);
1353
1354	int rc = VERR_IPE_UNINITIALIZED_STATUS;
1355	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1356	LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pCtx->cs.Sel, pCtx->eip));
1357	pVCpu->em.s.fForceRAW = false;
1358	*pfFFDone = false;
1359
1360
1361	/*
1362	*
1363	* Spin till we get a forced action or raw mode status code resulting in
1364	* in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
1365	*
1366	*/
1367	for (;;)
1368	{
1369	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatRAWEntry, b);
1370
1371	/*
1372	* Check various preconditions.
1373	*/
1374	#ifdef VBOX_STRICT
1375	# ifdef VBOX_WITH_REM
1376	Assert(REMR3QueryPendingInterrupt(pVM, pVCpu) == REM_NO_PENDING_IRQ);
1377	# endif
1378	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss.Sel & X86_SEL_RPL) == 3 \|\| (pCtx->ss.Sel & X86_SEL_RPL) == 0
1379	\|\| (EMIsRawRing1Enabled(pVM) && (pCtx->ss.Sel & X86_SEL_RPL) == 1));
1380	AssertMsg( (pCtx->eflags.u32 & X86_EFL_IF)
1381	\|\| PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip),
1382	("Tried to execute code with IF at EIP=%08x!\n", pCtx->eip));
1383	if ( !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1384	&& PGMMapHasConflicts(pVM))
1385	{
1386	PGMMapCheck(pVM);
1387	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
1388	return VERR_EM_UNEXPECTED_MAPPING_CONFLICT;
1389	}
1390	#endif /* VBOX_STRICT */
1391
1392	/*
1393	* Process high priority pre-execution raw-mode FFs.
1394	*/
1395	if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
1396	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1397	{
1398	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
1399	VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
1400	if (rc != VINF_SUCCESS)
1401	break;
1402	}
1403
1404	/*
1405	* If we're going to execute ring-0 code, the guest state needs to
1406	* be modified a bit and some of the state components (IF, SS/CS RPL,
1407	* and perhaps EIP) needs to be stored with PATM.
1408	*/
1409	rc = CPUMRawEnter(pVCpu, NULL);
1410	if (rc != VINF_SUCCESS)
1411	{
1412	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWEntry, b);
1413	break;
1414	}
1415
1416	/*
1417	* Scan code before executing it. Don't bother with user mode or V86 code
1418	*/
1419	if ( (pCtx->ss.Sel & X86_SEL_RPL) <= 1
1420	&& !pCtx->eflags.Bits.u1VM
1421	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
1422	{
1423	STAM_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatRAWEntry, b);
1424	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
1425	STAM_PROFILE_ADV_RESUME(&pVCpu->em.s.StatRAWEntry, b);
1426	if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
1427	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1428	{
1429	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
1430	VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
1431	if (rc != VINF_SUCCESS)
1432	{
1433	rc = CPUMRawLeave(pVCpu, NULL, rc);
1434	break;
1435	}
1436	}
1437	}
1438
1439	#ifdef LOG_ENABLED
1440	/*
1441	* Log important stuff before entering GC.
1442	*/
1443	PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
1444	if (pCtx->eflags.Bits.u1VM)
1445	Log(("RV86: %04x:%08x IF=%d VMFlags=%x\n", pCtx->cs.Sel, pCtx->eip, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
1446	else if ((pCtx->ss.Sel & X86_SEL_RPL) == 1)
1447	Log(("RR0: %x:%08x ESP=%x:%08x EFL=%x IF=%d/%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n",
1448	pCtx->cs.Sel, pCtx->eip, pCtx->ss.Sel, pCtx->esp, CPUMRawGetEFlags(pVCpu), !!(pGCState->uVMFlags & X86_EFL_IF), pCtx->eflags.Bits.u1IF,
1449	pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss.Sel & X86_SEL_RPL), CSAMIsPageScanned(pVM, (RTGCPTR)pCtx->eip)));
1450	# ifdef VBOX_WITH_RAW_RING1
1451	else if ((pCtx->ss.Sel & X86_SEL_RPL) == 2)
1452	Log(("RR1: %x:%08x ESP=%x:%08x IF=%d VMFlags=%x CPL=%x\n", pCtx->cs.Sel, pCtx->eip, pCtx->ss.Sel, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, (pCtx->ss.Sel & X86_SEL_RPL)));
1453	# endif
1454	else if ((pCtx->ss.Sel & X86_SEL_RPL) == 3)
1455	Log(("RR3: %x:%08x ESP=%x:%08x IF=%d VMFlags=%x\n", pCtx->cs.Sel, pCtx->eip, pCtx->ss.Sel, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
1456	#endif /* LOG_ENABLED */
1457
1458
1459
1460	/*
1461	* Execute the code.
1462	*/
1463	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWEntry, b);
1464	if (RT_LIKELY(emR3IsExecutionAllowed(pVM, pVCpu)))
1465	{
1466	STAM_PROFILE_START(&pVCpu->em.s.StatRAWExec, c);
1467	VBOXVMM_EM_RAW_RUN_PRE(pVCpu, pCtx);
1468	rc = VMMR3RawRunGC(pVM, pVCpu);
1469	VBOXVMM_EM_RAW_RUN_RET(pVCpu, pCtx, rc);
1470	STAM_PROFILE_STOP(&pVCpu->em.s.StatRAWExec, c);
1471	}
1472	else
1473	{
1474	/* Give up this time slice; virtual time continues */
1475	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatCapped, u);
1476	RTThreadSleep(5);
1477	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatCapped, u);
1478	rc = VINF_SUCCESS;
1479	}
1480	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatRAWTail, d);
1481
1482	LogFlow(("RR%u-E: %08x ESP=%08x EFL=%x IF=%d/%d VMFlags=%x PIF=%d\n",
1483	(pCtx->ss.Sel & X86_SEL_RPL), pCtx->eip, pCtx->esp, CPUMRawGetEFlags(pVCpu),
1484	!!(pGCState->uVMFlags & X86_EFL_IF), pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF));
1485	LogFlow(("VMMR3RawRunGC returned %Rrc\n", rc));
1486
1487
1488
1489	/*
1490	* Restore the real CPU state and deal with high priority post
1491	* execution FFs before doing anything else.
1492	*/
1493	rc = CPUMRawLeave(pVCpu, NULL, rc);
1494	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
1495	if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
1496	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
1497	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
1498
1499	#ifdef VBOX_STRICT
1500	/*
1501	* Assert TSS consistency & rc vs patch code.
1502	*/
1503	if ( !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
1504	&& EMIsRawRing0Enabled(pVM))
1505	SELMR3CheckTSS(pVM);
1506	switch (rc)
1507	{
1508	case VINF_SUCCESS:
1509	case VINF_EM_RAW_INTERRUPT:
1510	case VINF_PATM_PATCH_TRAP_PF:
1511	case VINF_PATM_PATCH_TRAP_GP:
1512	case VINF_PATM_PATCH_INT3:
1513	case VINF_PATM_CHECK_PATCH_PAGE:
1514	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
1515	case VINF_EM_RAW_GUEST_TRAP:
1516	case VINF_EM_RESCHEDULE_RAW:
1517	break;
1518
1519	default:
1520	if (PATMIsPatchGCAddr(pVM, pCtx->eip) && !(pCtx->eflags.u32 & X86_EFL_TF))
1521	LogIt(NULL, 0, LOG_GROUP_PATM, ("Patch code interrupted at %RRv for reason %Rrc\n", (RTRCPTR)CPUMGetGuestEIP(pVCpu), rc));
1522	break;
1523	}
1524	/*
1525	* Let's go paranoid!
1526	*/
1527	if ( !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1528	&& PGMMapHasConflicts(pVM))
1529	{
1530	PGMMapCheck(pVM);
1531	AssertMsgFailed(("We should not get conflicts any longer!!! rc=%Rrc\n", rc));
1532	return VERR_EM_UNEXPECTED_MAPPING_CONFLICT;
1533	}
1534	#endif /* VBOX_STRICT */
1535
1536	/*
1537	* Process the returned status code.
1538	*/
1539	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
1540	{
1541	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1542	break;
1543	}
1544	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
1545	if (rc != VINF_SUCCESS)
1546	{
1547	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
1548	if (rc != VINF_SUCCESS)
1549	{
1550	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1551	break;
1552	}
1553	}
1554
1555	/*
1556	* Check and execute forced actions.
1557	*/
1558	#ifdef VBOX_HIGH_RES_TIMERS_HACK
1559	TMTimerPollVoid(pVM, pVCpu);
1560	#endif
1561	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1562	if ( VM_FF_IS_PENDING(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VM_FF_PGM_NO_MEMORY)
1563	\|\| VMCPU_FF_IS_PENDING(pVCpu, ~VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1564	{
1565	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss.Sel & X86_SEL_RPL) != (EMIsRawRing1Enabled(pVM) ? 2 : 1));
1566
1567	STAM_REL_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatRAWTotal, a);
1568	rc = emR3ForcedActions(pVM, pVCpu, rc);
1569	VBOXVMM_EM_FF_ALL_RET(pVCpu, rc);
1570	STAM_REL_PROFILE_ADV_RESUME(&pVCpu->em.s.StatRAWTotal, a);
1571	if ( rc != VINF_SUCCESS
1572	&& rc != VINF_EM_RESCHEDULE_RAW)
1573	{
1574	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
1575	if (rc != VINF_SUCCESS)
1576	{
1577	*pfFFDone = true;
1578	break;
1579	}
1580	}
1581	}
1582	}
1583
1584	/*
1585	* Return to outer loop.
1586	*/
1587	#if defined(LOG_ENABLED) && defined(DEBUG)
1588	RTLogFlush(NULL);
1589	#endif
1590	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTotal, a);
1591	return rc;
1592	}
1593

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source: vbox/trunk/src/VBox/VMM/VMMR3/EMRaw.cpp@ 47815

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