DBGFDisas.cpp@ 45752

最後變更在這個檔案從45752是 45752,由 vboxsync 提交於 12 年前
Don't call MMHyperIsInsideArea if we're using HM to execute code, it will return bogus results!
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1	/* $Id: DBGFDisas.cpp 45752 2013-04-26 01:32:02Z vboxsync $ */
2	/** @file
3	* DBGF - Debugger Facility, Disassembler.
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.alldomusa.eu.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_DBGF
22	#include <VBox/vmm/dbgf.h>
23	#include <VBox/vmm/selm.h>
24	#include <VBox/vmm/mm.h>
25	#include <VBox/vmm/pgm.h>
26	#include <VBox/vmm/cpum.h>
27	#include "DBGFInternal.h"
28	#include <VBox/dis.h>
29	#include <VBox/err.h>
30	#include <VBox/param.h>
31	#include <VBox/vmm/vm.h>
32	#include <VBox/vmm/uvm.h>
33	#include "internal/pgm.h"
34
35	#include <VBox/log.h>
36	#include <iprt/assert.h>
37	#include <iprt/string.h>
38	#include <iprt/alloca.h>
39	#include <iprt/ctype.h>
40
41
42	/*******************************************************************************
43	* Structures and Typedefs *
44	*******************************************************************************/
45	/**
46	* Structure used when disassembling and instructions in DBGF.
47	* This is used so the reader function can get the stuff it needs.
48	*/
49	typedef struct
50	{
51	/** The core structure. */
52	DISCPUSTATE Cpu;
53	/** Pointer to the VM. */
54	PVM pVM;
55	/** Pointer to the VMCPU. */
56	PVMCPU pVCpu;
57	/** The address space for resolving symbol. */
58	RTDBGAS hAs;
59	/** Pointer to the first byte in the segment. */
60	RTGCUINTPTR GCPtrSegBase;
61	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
62	RTGCUINTPTR GCPtrSegEnd;
63	/** The size of the segment minus 1. */
64	RTGCUINTPTR cbSegLimit;
65	/** The guest paging mode. */
66	PGMMODE enmMode;
67	/** Pointer to the current page - R3 Ptr. */
68	void const *pvPageR3;
69	/** Pointer to the current page - GC Ptr. */
70	RTGCPTR GCPtrPage;
71	/** Pointer to the next instruction (relative to GCPtrSegBase). */
72	RTGCUINTPTR GCPtrNext;
73	/** The lock information that PGMPhysReleasePageMappingLock needs. */
74	PGMPAGEMAPLOCK PageMapLock;
75	/** Whether the PageMapLock is valid or not. */
76	bool fLocked;
77	/** 64 bits mode or not. */
78	bool f64Bits;
79	} DBGFDISASSTATE, *PDBGFDISASSTATE;
80
81
82	/*******************************************************************************
83	* Internal Functions *
84	*******************************************************************************/
85	static FNDISREADBYTES dbgfR3DisasInstrRead;
86
87
88
89	/**
90	* Calls the disassembler with the proper reader functions and such for disa
91	*
92	* @returns VBox status code.
93	* @param pVM Pointer to the VM.
94	* @param pVCpu Pointer to the VMCPU.
95	* @param pSelInfo The selector info.
96	* @param enmMode The guest paging mode.
97	* @param fFlags DBGF_DISAS_FLAGS_XXX.
98	* @param GCPtr The GC pointer (selector offset).
99	* @param pState The disas CPU state.
100	*/
101	static int dbgfR3DisasInstrFirst(PVM pVM, PVMCPU pVCpu, PDBGFSELINFO pSelInfo, PGMMODE enmMode,
102	RTGCPTR GCPtr, uint32_t fFlags, PDBGFDISASSTATE pState)
103	{
104	pState->GCPtrSegBase = pSelInfo->GCPtrBase;
105	pState->GCPtrSegEnd = pSelInfo->cbLimit + 1 + (RTGCUINTPTR)pSelInfo->GCPtrBase;
106	pState->cbSegLimit = pSelInfo->cbLimit;
107	pState->enmMode = enmMode;
108	pState->GCPtrPage = 0;
109	pState->pvPageR3 = NULL;
110	pState->hAs = pSelInfo->fFlags & DBGFSELINFO_FLAGS_HYPER /** @todo Deal more explicitly with RC in DBGFR3Disas. /
111	? DBGF_AS_RC_AND_GC_GLOBAL
112	: DBGF_AS_GLOBAL;
113	pState->pVM = pVM;
114	pState->pVCpu = pVCpu;
115	pState->fLocked = false;
116	pState->f64Bits = enmMode >= PGMMODE_AMD64 && pSelInfo->u.Raw.Gen.u1Long;
117
118	DISCPUMODE enmCpuMode;
119	switch (fFlags & DBGF_DISAS_FLAGS_MODE_MASK)
120	{
121	default:
122	AssertFailed();
123	case DBGF_DISAS_FLAGS_DEFAULT_MODE:
124	enmCpuMode = pState->f64Bits
125	? DISCPUMODE_64BIT
126	: pSelInfo->u.Raw.Gen.u1DefBig
127	? DISCPUMODE_32BIT
128	: DISCPUMODE_16BIT;
129	break;
130	case DBGF_DISAS_FLAGS_16BIT_MODE:
131	case DBGF_DISAS_FLAGS_16BIT_REAL_MODE:
132	enmCpuMode = DISCPUMODE_16BIT;
133	break;
134	case DBGF_DISAS_FLAGS_32BIT_MODE:
135	enmCpuMode = DISCPUMODE_32BIT;
136	break;
137	case DBGF_DISAS_FLAGS_64BIT_MODE:
138	enmCpuMode = DISCPUMODE_64BIT;
139	break;
140	}
141
142	uint32_t cbInstr;
143	int rc = DISInstrWithReader(GCPtr,
144	enmCpuMode,
145	dbgfR3DisasInstrRead,
146	&pState->Cpu,
147	&pState->Cpu,
148	&cbInstr);
149	if (RT_SUCCESS(rc))
150	{
151	pState->GCPtrNext = GCPtr + cbInstr;
152	return VINF_SUCCESS;
153	}
154
155	/* cleanup */
156	if (pState->fLocked)
157	{
158	PGMPhysReleasePageMappingLock(pVM, &pState->PageMapLock);
159	pState->fLocked = false;
160	}
161	return rc;
162	}
163
164
165	#if 0
166	/**
167	* Calls the disassembler for disassembling the next instruction.
168	*
169	* @returns VBox status code.
170	* @param pState The disas CPU state.
171	*/
172	static int dbgfR3DisasInstrNext(PDBGFDISASSTATE pState)
173	{
174	uint32_t cbInstr;
175	int rc = DISInstr(&pState->Cpu, (void *)pState->GCPtrNext, 0, &cbInstr, NULL);
176	if (RT_SUCCESS(rc))
177	{
178	pState->GCPtrNext = GCPtr + cbInstr;
179	return VINF_SUCCESS;
180	}
181	return rc;
182	}
183	#endif
184
185
186	/**
187	* Done with the disassembler state, free associated resources.
188	*
189	* @param pState The disas CPU state ++.
190	*/
191	static void dbgfR3DisasInstrDone(PDBGFDISASSTATE pState)
192	{
193	if (pState->fLocked)
194	{
195	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
196	pState->fLocked = false;
197	}
198	}
199
200
201	/**
202	* @callback_method_impl{FNDISREADBYTES}
203	*
204	* @remarks The source is relative to the base address indicated by
205	* DBGFDISASSTATE::GCPtrSegBase.
206	*/
207	static DECLCALLBACK(int) dbgfR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
208	{
209	PDBGFDISASSTATE pState = (PDBGFDISASSTATE)pDis;
210	for (;;)
211	{
212	RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
213
214	/*
215	* Need to update the page translation?
216	*/
217	if ( !pState->pvPageR3
218	\|\| (GCPtr >> PAGE_SHIFT) != (pState->GCPtrPage >> PAGE_SHIFT))
219	{
220	int rc = VINF_SUCCESS;
221
222	/* translate the address */
223	pState->GCPtrPage = GCPtr & PAGE_BASE_GC_MASK;
224	if ( !HMIsEnabled(pState->pVM)
225	&& MMHyperIsInsideArea(pState->pVM, pState->GCPtrPage))
226	{
227	pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->GCPtrPage);
228	if (!pState->pvPageR3)
229	rc = VERR_INVALID_POINTER;
230	}
231	else
232	{
233	if (pState->fLocked)
234	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
235
236	if (pState->enmMode <= PGMMODE_PROTECTED)
237	rc = PGMPhysGCPhys2CCPtrReadOnly(pState->pVM, pState->GCPtrPage, &pState->pvPageR3, &pState->PageMapLock);
238	else
239	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->GCPtrPage, &pState->pvPageR3, &pState->PageMapLock);
240	pState->fLocked = RT_SUCCESS_NP(rc);
241	}
242	if (RT_FAILURE(rc))
243	{
244	pState->pvPageR3 = NULL;
245	return rc;
246	}
247	}
248
249	/*
250	* Check the segment limit.
251	*/
252	if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
253	return VERR_OUT_OF_SELECTOR_BOUNDS;
254
255	/*
256	* Calc how much we can read, maxing out the read.
257	*/
258	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
259	if (!pState->f64Bits)
260	{
261	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
262	if (cb > cbSeg && cbSeg)
263	cb = cbSeg;
264	}
265	if (cb > cbMaxRead)
266	cb = cbMaxRead;
267
268	/*
269	* Read and advance,
270	*/
271	memcpy(&pDis->abInstr[offInstr], (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
272	offInstr += (uint8_t)cb;
273	if (cb >= cbMinRead)
274	{
275	pDis->cbCachedInstr = offInstr;
276	return VINF_SUCCESS;
277	}
278	cbMaxRead -= (uint8_t)cb;
279	cbMinRead -= (uint8_t)cb;
280	}
281	}
282
283
284	/**
285	* @copydoc FNDISGETSYMBOL
286	*/
287	static DECLCALLBACK(int) dbgfR3DisasGetSymbol(PCDISCPUSTATE pCpu, uint32_t u32Sel, RTUINTPTR uAddress, char pszBuf, size_t cchBuf, RTINTPTR poff, void *pvUser)
288	{
289	PDBGFDISASSTATE pState = (PDBGFDISASSTATE)pCpu;
290	PCDBGFSELINFO pSelInfo = (PCDBGFSELINFO)pvUser;
291	DBGFADDRESS Addr;
292	RTDBGSYMBOL Sym;
293	RTGCINTPTR off;
294	int rc;
295
296	if ( DIS_FMT_SEL_IS_REG(u32Sel)
297	? DIS_FMT_SEL_GET_REG(u32Sel) == DISSELREG_CS
298	: pSelInfo->Sel == DIS_FMT_SEL_GET_VALUE(u32Sel))
299	{
300	rc = DBGFR3AddrFromSelInfoOff(pState->pVM->pUVM, &Addr, pSelInfo, uAddress);
301	if (RT_SUCCESS(rc))
302	rc = DBGFR3AsSymbolByAddr(pState->pVM->pUVM, pState->hAs, &Addr, &off, &Sym, NULL /phMod/);
303	}
304	else
305	rc = VERR_SYMBOL_NOT_FOUND; /** @todo implement this */
306	if (RT_SUCCESS(rc))
307	{
308	size_t cchName = strlen(Sym.szName);
309	if (cchName >= cchBuf)
310	cchName = cchBuf - 1;
311	memcpy(pszBuf, Sym.szName, cchName);
312	pszBuf[cchName] = '\0';
313
314	*poff = off;
315	}
316
317	return rc;
318	}
319
320
321	/**
322	* Disassembles the one instruction according to the specified flags and
323	* address, internal worker executing on the EMT of the specified virtual CPU.
324	*
325	* @returns VBox status code.
326	* @param pVM Pointer to the VM.
327	* @param pVCpu Pointer to the VMCPU.
328	* @param Sel The code selector. This used to determine the 32/16 bit ness and
329	* calculation of the actual instruction address.
330	* @param pGCPtr Pointer to the variable holding the code address
331	* relative to the base of Sel.
332	* @param fFlags Flags controlling where to start and how to format.
333	* A combination of the DBGF_DISAS_FLAGS_* \#defines.
334	* @param pszOutput Output buffer.
335	* @param cbOutput Size of the output buffer.
336	* @param pcbInstr Where to return the size of the instruction.
337	*/
338	static DECLCALLBACK(int)
339	dbgfR3DisasInstrExOnVCpu(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PRTGCPTR pGCPtr, uint32_t fFlags,
340	char pszOutput, uint32_t cbOutput, uint32_t pcbInstr)
341	{
342	VMCPU_ASSERT_EMT(pVCpu);
343	RTGCPTR GCPtr = *pGCPtr;
344	int rc;
345
346	/*
347	* Get the Sel and GCPtr if fFlags requests that.
348	*/
349	PCCPUMCTXCORE pCtxCore = NULL;
350	PCCPUMSELREG pSRegCS = NULL;
351	if (fFlags & DBGF_DISAS_FLAGS_CURRENT_GUEST)
352	{
353	pCtxCore = CPUMGetGuestCtxCore(pVCpu);
354	Sel = pCtxCore->cs.Sel;
355	pSRegCS = &pCtxCore->cs;
356	GCPtr = pCtxCore->rip;
357	}
358	else if (fFlags & DBGF_DISAS_FLAGS_CURRENT_HYPER)
359	{
360	pCtxCore = CPUMGetHyperCtxCore(pVCpu);
361	Sel = pCtxCore->cs.Sel;
362	GCPtr = pCtxCore->rip;
363	}
364	/*
365	* Check if the selector matches the guest CS, use the hidden
366	* registers from that if they are valid. Saves time and effort.
367	*/
368	else
369	{
370	pCtxCore = CPUMGetGuestCtxCore(pVCpu);
371	if (pCtxCore->cs.Sel == Sel && Sel != DBGF_SEL_FLAT)
372	pSRegCS = &pCtxCore->cs;
373	else
374	pCtxCore = NULL;
375	}
376
377	/*
378	* Read the selector info - assume no stale selectors and nasty stuff like that.
379	*
380	* Note! We CANNOT load invalid hidden selector registers since that would
381	* mean that log/debug statements or the debug will influence the
382	* guest state and make things behave differently.
383	*/
384	DBGFSELINFO SelInfo;
385	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
386	bool fRealModeAddress = false;
387
388	if ( pSRegCS
389	&& CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSRegCS))
390	{
391	SelInfo.Sel = Sel;
392	SelInfo.SelGate = 0;
393	SelInfo.GCPtrBase = pSRegCS->u64Base;
394	SelInfo.cbLimit = pSRegCS->u32Limit;
395	SelInfo.fFlags = PGMMODE_IS_LONG_MODE(enmMode)
396	? DBGFSELINFO_FLAGS_LONG_MODE
397	: enmMode != PGMMODE_REAL && !pCtxCore->eflags.Bits.u1VM
398	? DBGFSELINFO_FLAGS_PROT_MODE
399	: DBGFSELINFO_FLAGS_REAL_MODE;
400
401	SelInfo.u.Raw.au32[0] = 0;
402	SelInfo.u.Raw.au32[1] = 0;
403	SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
404	SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
405	SelInfo.u.Raw.Gen.u1Present = pSRegCS->Attr.n.u1Present;
406	SelInfo.u.Raw.Gen.u1Granularity = pSRegCS->Attr.n.u1Granularity;;
407	SelInfo.u.Raw.Gen.u1DefBig = pSRegCS->Attr.n.u1DefBig;
408	SelInfo.u.Raw.Gen.u1Long = pSRegCS->Attr.n.u1Long;
409	SelInfo.u.Raw.Gen.u1DescType = pSRegCS->Attr.n.u1DescType;
410	SelInfo.u.Raw.Gen.u4Type = pSRegCS->Attr.n.u4Type;
411	fRealModeAddress = !!(SelInfo.fFlags & DBGFSELINFO_FLAGS_REAL_MODE);
412	}
413	else if (Sel == DBGF_SEL_FLAT)
414	{
415	SelInfo.Sel = Sel;
416	SelInfo.SelGate = 0;
417	SelInfo.GCPtrBase = 0;
418	SelInfo.cbLimit = ~0;
419	SelInfo.fFlags = PGMMODE_IS_LONG_MODE(enmMode)
420	? DBGFSELINFO_FLAGS_LONG_MODE
421	: enmMode != PGMMODE_REAL
422	? DBGFSELINFO_FLAGS_PROT_MODE
423	: DBGFSELINFO_FLAGS_REAL_MODE;
424	SelInfo.u.Raw.au32[0] = 0;
425	SelInfo.u.Raw.au32[1] = 0;
426	SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
427	SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
428
429	pSRegCS = &CPUMGetGuestCtxCore(pVCpu)->cs;
430	if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSRegCS))
431	{
432	/* Assume the current CS defines the execution mode. */
433	SelInfo.u.Raw.Gen.u1Present = pSRegCS->Attr.n.u1Present;
434	SelInfo.u.Raw.Gen.u1Granularity = pSRegCS->Attr.n.u1Granularity;;
435	SelInfo.u.Raw.Gen.u1DefBig = pSRegCS->Attr.n.u1DefBig;
436	SelInfo.u.Raw.Gen.u1Long = pSRegCS->Attr.n.u1Long;
437	SelInfo.u.Raw.Gen.u1DescType = pSRegCS->Attr.n.u1DescType;
438	SelInfo.u.Raw.Gen.u4Type = pSRegCS->Attr.n.u4Type;
439	}
440	else
441	{
442	pSRegCS = NULL;
443	SelInfo.u.Raw.Gen.u1Present = 1;
444	SelInfo.u.Raw.Gen.u1Granularity = 1;
445	SelInfo.u.Raw.Gen.u1DefBig = 1;
446	SelInfo.u.Raw.Gen.u1DescType = 1;
447	SelInfo.u.Raw.Gen.u4Type = X86_SEL_TYPE_EO;
448	}
449	}
450	else if ( !(fFlags & DBGF_DISAS_FLAGS_CURRENT_HYPER)
451	&& ( (pCtxCore && pCtxCore->eflags.Bits.u1VM)
452	\|\| enmMode == PGMMODE_REAL
453	\|\| (fFlags & DBGF_DISAS_FLAGS_MODE_MASK) == DBGF_DISAS_FLAGS_16BIT_REAL_MODE
454	)
455	)
456	{ /* V86 mode or real mode - real mode addressing */
457	SelInfo.Sel = Sel;
458	SelInfo.SelGate = 0;
459	SelInfo.GCPtrBase = Sel * 16;
460	SelInfo.cbLimit = ~0;
461	SelInfo.fFlags = DBGFSELINFO_FLAGS_REAL_MODE;
462	SelInfo.u.Raw.au32[0] = 0;
463	SelInfo.u.Raw.au32[1] = 0;
464	SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
465	SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
466	SelInfo.u.Raw.Gen.u1Present = 1;
467	SelInfo.u.Raw.Gen.u1Granularity = 1;
468	SelInfo.u.Raw.Gen.u1DefBig = 0; /* 16 bits */
469	SelInfo.u.Raw.Gen.u1DescType = 1;
470	SelInfo.u.Raw.Gen.u4Type = X86_SEL_TYPE_EO;
471	fRealModeAddress = true;
472	}
473	else
474	{
475	rc = SELMR3GetSelectorInfo(pVM, pVCpu, Sel, &SelInfo);
476	if (RT_FAILURE(rc))
477	{
478	RTStrPrintf(pszOutput, cbOutput, "Sel=%04x -> %Rrc\n", Sel, rc);
479	return rc;
480	}
481	}
482
483	/*
484	* Disassemble it.
485	*/
486	DBGFDISASSTATE State;
487	rc = dbgfR3DisasInstrFirst(pVM, pVCpu, &SelInfo, enmMode, GCPtr, fFlags, &State);
488	if (RT_FAILURE(rc))
489	{
490	RTStrPrintf(pszOutput, cbOutput, "Disas -> %Rrc\n", rc);
491	return rc;
492	}
493
494	/*
495	* Format it.
496	*/
497	char szBuf[512];
498	DISFormatYasmEx(&State.Cpu, szBuf, sizeof(szBuf),
499	DIS_FMT_FLAGS_RELATIVE_BRANCH,
500	fFlags & DBGF_DISAS_FLAGS_NO_SYMBOLS ? NULL : dbgfR3DisasGetSymbol,
501	&SelInfo);
502
503	/*
504	* Print it to the user specified buffer.
505	*/
506	if (fFlags & DBGF_DISAS_FLAGS_NO_BYTES)
507	{
508	if (fFlags & DBGF_DISAS_FLAGS_NO_ADDRESS)
509	RTStrPrintf(pszOutput, cbOutput, "%s", szBuf);
510	else if (fRealModeAddress)
511	RTStrPrintf(pszOutput, cbOutput, "%04x:%04x %s", Sel, (unsigned)GCPtr, szBuf);
512	else if (Sel == DBGF_SEL_FLAT)
513	{
514	if (enmMode >= PGMMODE_AMD64)
515	RTStrPrintf(pszOutput, cbOutput, "%RGv %s", GCPtr, szBuf);
516	else
517	RTStrPrintf(pszOutput, cbOutput, "%08RX32 %s", (uint32_t)GCPtr, szBuf);
518	}
519	else
520	{
521	if (enmMode >= PGMMODE_AMD64)
522	RTStrPrintf(pszOutput, cbOutput, "%04x:%RGv %s", Sel, GCPtr, szBuf);
523	else
524	RTStrPrintf(pszOutput, cbOutput, "%04x:%08RX32 %s", Sel, (uint32_t)GCPtr, szBuf);
525	}
526	}
527	else
528	{
529	uint32_t cbInstr = State.Cpu.cbInstr;
530	uint8_t const *pabInstr = State.Cpu.abInstr;
531	if (fFlags & DBGF_DISAS_FLAGS_NO_ADDRESS)
532	RTStrPrintf(pszOutput, cbOutput, "%.Rhxs%s %s",
533	cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
534	szBuf);
535	else if (fRealModeAddress)
536	RTStrPrintf(pszOutput, cbOutput, "%04x:%04x %.Rhxs%s %s",
537	Sel, (unsigned)GCPtr,
538	cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
539	szBuf);
540	else if (Sel == DBGF_SEL_FLAT)
541	{
542	if (enmMode >= PGMMODE_AMD64)
543	RTStrPrintf(pszOutput, cbOutput, "%RGv %.Rhxs%s %s",
544	GCPtr,
545	cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
546	szBuf);
547	else
548	RTStrPrintf(pszOutput, cbOutput, "%08RX32 %.Rhxs%s %s",
549	(uint32_t)GCPtr,
550	cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
551	szBuf);
552	}
553	else
554	{
555	if (enmMode >= PGMMODE_AMD64)
556	RTStrPrintf(pszOutput, cbOutput, "%04x:%RGv %.Rhxs%s %s",
557	Sel, GCPtr,
558	cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
559	szBuf);
560	else
561	RTStrPrintf(pszOutput, cbOutput, "%04x:%08RX32 %.Rhxs%s %s",
562	Sel, (uint32_t)GCPtr,
563	cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
564	szBuf);
565	}
566	}
567
568	if (pcbInstr)
569	*pcbInstr = State.Cpu.cbInstr;
570
571	dbgfR3DisasInstrDone(&State);
572	return VINF_SUCCESS;
573	}
574
575
576	/**
577	* Disassembles the one instruction according to the specified flags and address.
578	*
579	* @returns VBox status code.
580	* @param pUVM The user mode VM handle.
581	* @param idCpu The ID of virtual CPU.
582	* @param Sel The code selector. This used to determine the 32/16 bit ness and
583	* calculation of the actual instruction address.
584	* @param GCPtr The code address relative to the base of Sel.
585	* @param fFlags Flags controlling where to start and how to format.
586	* A combination of the DBGF_DISAS_FLAGS_* \#defines.
587	* @param pszOutput Output buffer. This will always be properly
588	* terminated if @a cbOutput is greater than zero.
589	* @param cbOutput Size of the output buffer.
590	* @param pcbInstr Where to return the size of the instruction.
591	*
592	* @remarks May have to switch to the EMT of the virtual CPU in order to do
593	* address conversion.
594	*/
595	VMMR3DECL(int) DBGFR3DisasInstrEx(PUVM pUVM, VMCPUID idCpu, RTSEL Sel, RTGCPTR GCPtr, uint32_t fFlags,
596	char pszOutput, uint32_t cbOutput, uint32_t pcbInstr)
597	{
598	AssertReturn(cbOutput > 0, VERR_INVALID_PARAMETER);
599	*pszOutput = '\0';
600	UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
601	PVM pVM = pUVM->pVM;
602	VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
603	AssertReturn(idCpu < pUVM->cCpus, VERR_INVALID_CPU_ID);
604	AssertReturn(!(fFlags & ~DBGF_DISAS_FLAGS_VALID_MASK), VERR_INVALID_PARAMETER);
605	AssertReturn((fFlags & DBGF_DISAS_FLAGS_MODE_MASK) <= DBGF_DISAS_FLAGS_64BIT_MODE, VERR_INVALID_PARAMETER);
606
607	/*
608	* Optimize the common case where we're called on the EMT of idCpu since
609	* we're using this all the time when logging.
610	*/
611	int rc;
612	PVMCPU pVCpu = VMMGetCpu(pVM);
613	if ( pVCpu
614	&& pVCpu->idCpu == idCpu)
615	rc = dbgfR3DisasInstrExOnVCpu(pVM, pVCpu, Sel, &GCPtr, fFlags, pszOutput, cbOutput, pcbInstr);
616	else
617	rc = VMR3ReqPriorityCallWait(pVM, idCpu, (PFNRT)dbgfR3DisasInstrExOnVCpu, 8,
618	pVM, VMMGetCpuById(pVM, idCpu), Sel, &GCPtr, fFlags, pszOutput, cbOutput, pcbInstr);
619	return rc;
620	}
621
622
623	/**
624	* Disassembles the current guest context instruction.
625	* All registers and data will be displayed. Addresses will be attempted resolved to symbols.
626	*
627	* @returns VBox status code.
628	* @param pVCpu Pointer to the VMCPU.
629	* @param pszOutput Output buffer. This will always be properly
630	* terminated if @a cbOutput is greater than zero.
631	* @param cbOutput Size of the output buffer.
632	* @thread EMT(pVCpu)
633	*/
634	VMMR3_INT_DECL(int) DBGFR3DisasInstrCurrent(PVMCPU pVCpu, char *pszOutput, uint32_t cbOutput)
635	{
636	AssertReturn(cbOutput > 0, VERR_INVALID_PARAMETER);
637	*pszOutput = '\0';
638	Assert(VMCPU_IS_EMT(pVCpu));
639
640	RTGCPTR GCPtr = 0;
641	return dbgfR3DisasInstrExOnVCpu(pVCpu->pVMR3, pVCpu, 0, &GCPtr,
642	DBGF_DISAS_FLAGS_CURRENT_GUEST \| DBGF_DISAS_FLAGS_DEFAULT_MODE,
643	pszOutput, cbOutput, NULL);
644	}
645
646
647	/**
648	* Disassembles the current guest context instruction and writes it to the log.
649	* All registers and data will be displayed. Addresses will be attempted resolved to symbols.
650	*
651	* @returns VBox status code.
652	* @param pVCpu Pointer to the VMCPU.
653	* @param pszPrefix Short prefix string to the disassembly string. (optional)
654	* @thread EMT(pVCpu)
655	*/
656	VMMR3DECL(int) DBGFR3DisasInstrCurrentLogInternal(PVMCPU pVCpu, const char *pszPrefix)
657	{
658	char szBuf[256];
659	szBuf[0] = '\0';
660	int rc = DBGFR3DisasInstrCurrent(pVCpu, &szBuf[0], sizeof(szBuf));
661	if (RT_FAILURE(rc))
662	RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrCurrentLog failed with rc=%Rrc\n", rc);
663	if (pszPrefix && *pszPrefix)
664	{
665	if (pVCpu->CTX_SUFF(pVM)->cCpus > 1)
666	RTLogPrintf("%s-CPU%u: %s\n", pszPrefix, pVCpu->idCpu, szBuf);
667	else
668	RTLogPrintf("%s: %s\n", pszPrefix, szBuf);
669	}
670	else
671	RTLogPrintf("%s\n", szBuf);
672	return rc;
673	}
674
675
676
677	/**
678	* Disassembles the specified guest context instruction and writes it to the log.
679	* Addresses will be attempted resolved to symbols.
680	*
681	* @returns VBox status code.
682	* @param pVCpu Pointer to the VMCPU, defaults to CPU 0 if NULL.
683	* @param Sel The code selector. This used to determine the 32/16 bit-ness and
684	* calculation of the actual instruction address.
685	* @param GCPtr The code address relative to the base of Sel.
686	* @param pszPrefix Short prefix string to the disassembly string. (optional)
687	* @thread EMT(pVCpu)
688	*/
689	VMMR3DECL(int) DBGFR3DisasInstrLogInternal(PVMCPU pVCpu, RTSEL Sel, RTGCPTR GCPtr, const char *pszPrefix)
690	{
691	Assert(VMCPU_IS_EMT(pVCpu));
692
693	char szBuf[256];
694	RTGCPTR GCPtrTmp = GCPtr;
695	int rc = dbgfR3DisasInstrExOnVCpu(pVCpu->pVMR3, pVCpu, Sel, &GCPtrTmp, DBGF_DISAS_FLAGS_DEFAULT_MODE,
696	&szBuf[0], sizeof(szBuf), NULL);
697	if (RT_FAILURE(rc))
698	RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrLog(, %RTsel, %RGv) failed with rc=%Rrc\n", Sel, GCPtr, rc);
699	if (pszPrefix && *pszPrefix)
700	{
701	if (pVCpu->CTX_SUFF(pVM)->cCpus > 1)
702	RTLogPrintf("%s-CPU%u: %s\n", pszPrefix, pVCpu->idCpu, szBuf);
703	else
704	RTLogPrintf("%s: %s\n", pszPrefix, szBuf);
705	}
706	else
707	RTLogPrintf("%s\n", szBuf);
708	return rc;
709	}
710

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source: vbox/trunk/src/VBox/VMM/VMMR3/DBGFDisas.cpp@ 45752

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