VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3Db.cpp@ 50617

最後變更 在這個檔案從50617是 50590,由 vboxsync 提交於 11 年 前

CPUM,VMM: More work related to bus, cpu and tsc frequency info. Should cover older core and p6 as well as p4 now.

  • 屬性 svn:eol-style 設為 native
  • 屬性 svn:keywords 設為 Author Date Id Revision
檔案大小: 31.9 KB
 
1/* $Id: CPUMR3Db.cpp 50590 2014-02-25 18:51:23Z vboxsync $ */
2/** @file
3 * CPUM - CPU database part.
4 */
5
6/*
7 * Copyright (C) 2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.alldomusa.eu.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_CPUM
22#include <VBox/vmm/cpum.h>
23#include "CPUMInternal.h"
24#include <VBox/vmm/vm.h>
25
26#include <VBox/err.h>
27#include <iprt/asm-amd64-x86.h>
28#include <iprt/mem.h>
29#include <iprt/string.h>
30
31
32/*******************************************************************************
33* Structures and Typedefs *
34*******************************************************************************/
35typedef struct CPUMDBENTRY
36{
37 /** The CPU name. */
38 const char *pszName;
39 /** The full CPU name. */
40 const char *pszFullName;
41 /** The CPU vendor (CPUMCPUVENDOR). */
42 uint8_t enmVendor;
43 /** The CPU family. */
44 uint8_t uFamily;
45 /** The CPU model. */
46 uint8_t uModel;
47 /** The CPU stepping. */
48 uint8_t uStepping;
49 /** The microarchitecture. */
50 CPUMMICROARCH enmMicroarch;
51 /** Scalable bus frequency used for reporting other frequencies. */
52 uint64_t uScalableBusFreq;
53 /** Flags (TBD). */
54 uint32_t fFlags;
55 /** The maximum physical address with of the CPU. This should correspond to
56 * the value in CPUID leaf 0x80000008 when present. */
57 uint8_t cMaxPhysAddrWidth;
58 /** Pointer to an array of CPUID leaves. */
59 PCCPUMCPUIDLEAF paCpuIdLeaves;
60 /** The number of CPUID leaves in the array paCpuIdLeaves points to. */
61 uint32_t cCpuIdLeaves;
62 /** The method used to deal with unknown CPUID leaves. */
63 CPUMUKNOWNCPUID enmUnknownCpuId;
64 /** The default unknown CPUID value. */
65 CPUMCPUID DefUnknownCpuId;
66
67 /** MSR mask. Several microarchitectures ignore higher bits of the */
68 uint32_t fMsrMask;
69
70 /** The number of ranges in the table pointed to b paMsrRanges. */
71 uint32_t cMsrRanges;
72 /** MSR ranges for this CPU. */
73 PCCPUMMSRRANGE paMsrRanges;
74} CPUMDBENTRY;
75
76
77/*******************************************************************************
78* Defined Constants And Macros *
79*******************************************************************************/
80
81/** @def NULL_ALONE
82 * For eliminating an unnecessary data dependency in standalone builds (for
83 * VBoxSVC). */
84/** @def ZERO_ALONE
85 * For eliminating an unnecessary data size dependency in standalone builds (for
86 * VBoxSVC). */
87#ifndef CPUM_DB_STANDALONE
88# define NULL_ALONE(a_aTable) a_aTable
89# define ZERO_ALONE(a_cTable) a_cTable
90#else
91# define NULL_ALONE(a_aTable) NULL
92# define ZERO_ALONE(a_cTable) 0
93#endif
94
95
96/** @name Short macros for the MSR range entries.
97 *
98 * These are rather cryptic, but this is to reduce the attack on the right
99 * margin.
100 *
101 * @{ */
102/** Alias one MSR onto another (a_uTarget). */
103#define MAL(a_uMsr, a_szName, a_uTarget) \
104 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_MsrAlias, kCpumMsrWrFn_MsrAlias, 0, a_uTarget, 0, 0, a_szName)
105/** Functions handles everything. */
106#define MFN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
107 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
108/** Functions handles everything, with GP mask. */
109#define MFG(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrGpMask) \
110 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, a_fWrGpMask, a_szName)
111/** Function handlers, read-only. */
112#define MFO(a_uMsr, a_szName, a_enmRdFnSuff) \
113 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_ReadOnly, 0, 0, 0, UINT64_MAX, a_szName)
114/** Function handlers, ignore all writes. */
115#define MFI(a_uMsr, a_szName, a_enmRdFnSuff) \
116 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_IgnoreWrite, 0, 0, UINT64_MAX, 0, a_szName)
117/** Function handlers, with value. */
118#define MFV(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue) \
119 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, 0, 0, a_szName)
120/** Function handlers, with write ignore mask. */
121#define MFW(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrIgnMask) \
122 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, a_fWrIgnMask, 0, a_szName)
123/** Function handlers, extended version. */
124#define MFX(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
125 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
126/** Function handlers, with CPUMCPU storage variable. */
127#define MFS(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember) \
128 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
129 RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, 0, 0, a_szName)
130/** Function handlers, with CPUMCPU storage variable, ignore mask and GP mask. */
131#define MFZ(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember, a_fWrIgnMask, a_fWrGpMask) \
132 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
133 RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, a_fWrIgnMask, a_fWrGpMask, a_szName)
134/** Read-only fixed value. */
135#define MVO(a_uMsr, a_szName, a_uValue) \
136 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
137/** Read-only fixed value, ignores all writes. */
138#define MVI(a_uMsr, a_szName, a_uValue) \
139 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
140/** Read fixed value, ignore writes outside GP mask. */
141#define MVG(a_uMsr, a_szName, a_uValue, a_fWrGpMask) \
142 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, 0, a_fWrGpMask, a_szName)
143/** Read fixed value, extended version with both GP and ignore masks. */
144#define MVX(a_uMsr, a_szName, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
145 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
146/** The short form, no CPUM backing. */
147#define MSN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
148 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
149 a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
150
151/** Range: Functions handles everything. */
152#define RFN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
153 RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
154/** Range: Read fixed value, read-only. */
155#define RVO(a_uFirst, a_uLast, a_szName, a_uValue) \
156 RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
157/** Range: Read fixed value, ignore writes. */
158#define RVI(a_uFirst, a_uLast, a_szName, a_uValue) \
159 RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
160/** Range: The short form, no CPUM backing. */
161#define RSN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
162 RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
163 a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
164
165/** Internal form used by the macros. */
166#ifdef VBOX_WITH_STATISTICS
167# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
168 { a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName, \
169 { 0 }, { 0 }, { 0 }, { 0 } }
170#else
171# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
172 { a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName }
173#endif
174/** @} */
175
176
177#include "cpus/Intel_Core_i7_3960X.h"
178#include "cpus/Intel_Core_i5_3570.h"
179#include "cpus/Intel_Xeon_X5482_3_20GHz.h"
180#include "cpus/Intel_Pentium_M_processor_2_00GHz.h"
181#include "cpus/Intel_Pentium_4_3_00GHz.h"
182
183#include "cpus/AMD_FX_8150_Eight_Core.h"
184#include "cpus/AMD_Phenom_II_X6_1100T.h"
185#include "cpus/Quad_Core_AMD_Opteron_2384.h"
186#include "cpus/AMD_Athlon_64_3200.h"
187
188#include "cpus/VIA_QuadCore_L4700_1_2_GHz.h"
189
190
191
192/**
193 * The database entries.
194 *
195 * 1. The first entry is special. It is the fallback for unknown
196 * processors. Thus, it better be pretty representative.
197 *
198 * 2. The first entry for a CPU vendor is likewise important as it is
199 * the default entry for that vendor.
200 *
201 * Generally we put the most recent CPUs first, since these tend to have the
202 * most complicated and backwards compatible list of MSRs.
203 */
204static CPUMDBENTRY const * const g_apCpumDbEntries[] =
205{
206#ifdef VBOX_CPUDB_Intel_Core_i5_3570
207 &g_Entry_Intel_Core_i5_3570,
208#endif
209#ifdef VBOX_CPUDB_Intel_Core_i7_3960X
210 &g_Entry_Intel_Core_i7_3960X,
211#endif
212#ifdef Intel_Pentium_M_processor_2_00GHz
213 &g_Entry_Intel_Pentium_M_processor_2_00GHz,
214#endif
215#ifdef VBOX_CPUDB_Intel_Xeon_X5482_3_20GHz
216 &g_Entry_Intel_Xeon_X5482_3_20GHz,
217#endif
218#ifdef VBOX_CPUDB_Intel_Pentium_4_3_00GHz
219 &g_Entry_Intel_Pentium_4_3_00GHz,
220#endif
221
222#ifdef VBOX_CPUDB_AMD_FX_8150_Eight_Core
223 &g_Entry_AMD_FX_8150_Eight_Core,
224#endif
225#ifdef VBOX_CPUDB_AMD_Phenom_II_X6_1100T
226 &g_Entry_AMD_Phenom_II_X6_1100T,
227#endif
228#ifdef VBOX_CPUDB_Quad_Core_AMD_Opteron_2384
229 &g_Entry_Quad_Core_AMD_Opteron_2384,
230#endif
231#ifdef VBOX_CPUDB_AMD_Athlon_64_3200
232 &g_Entry_AMD_Athlon_64_3200,
233#endif
234
235#ifdef VBOX_CPUDB_VIA_QuadCore_L4700_1_2_GHz
236 &g_Entry_VIA_QuadCore_L4700_1_2_GHz,
237#endif
238};
239
240
241#ifndef CPUM_DB_STANDALONE
242
243/**
244 * Binary search used by cpumR3MsrRangesInsert and has some special properties
245 * wrt to mismatches.
246 *
247 * @returns Insert location.
248 * @param paMsrRanges The MSR ranges to search.
249 * @param cMsrRanges The number of MSR ranges.
250 * @param uMsr What to search for.
251 */
252static uint32_t cpumR3MsrRangesBinSearch(PCCPUMMSRRANGE paMsrRanges, uint32_t cMsrRanges, uint32_t uMsr)
253{
254 if (!cMsrRanges)
255 return 0;
256
257 uint32_t iStart = 0;
258 uint32_t iLast = cMsrRanges - 1;
259 for (;;)
260 {
261 uint32_t i = iStart + (iLast - iStart + 1) / 2;
262 if ( uMsr >= paMsrRanges[i].uFirst
263 && uMsr <= paMsrRanges[i].uLast)
264 return i;
265 if (uMsr < paMsrRanges[i].uFirst)
266 {
267 if (i <= iStart)
268 return i;
269 iLast = i - 1;
270 }
271 else
272 {
273 if (i >= iLast)
274 {
275 if (i < cMsrRanges)
276 i++;
277 return i;
278 }
279 iStart = i + 1;
280 }
281 }
282}
283
284
285/**
286 * Ensures that there is space for at least @a cNewRanges in the table,
287 * reallocating the table if necessary.
288 *
289 * @returns Pointer to the MSR ranges on success, NULL on failure. On failure
290 * @a *ppaMsrRanges is freed and set to NULL.
291 * @param ppaMsrRanges The variable pointing to the ranges (input/output).
292 * @param cMsrRanges The current number of ranges.
293 * @param cNewRanges The number of ranges to be added.
294 */
295static PCPUMMSRRANGE cpumR3MsrRangesEnsureSpace(PCPUMMSRRANGE *ppaMsrRanges, uint32_t cMsrRanges, uint32_t cNewRanges)
296{
297 uint32_t cMsrRangesAllocated = RT_ALIGN_32(cMsrRanges, 16);
298 if (cMsrRangesAllocated < cMsrRanges + cNewRanges)
299 {
300 uint32_t cNew = RT_ALIGN_32(cMsrRanges + cNewRanges, 16);
301 void *pvNew = RTMemRealloc(*ppaMsrRanges, cNew * sizeof(**ppaMsrRanges));
302 if (!pvNew)
303 {
304 RTMemFree(*ppaMsrRanges);
305 *ppaMsrRanges = NULL;
306 return NULL;
307 }
308 *ppaMsrRanges = (PCPUMMSRRANGE)pvNew;
309 }
310 return *ppaMsrRanges;
311}
312
313
314/**
315 * Inserts a new MSR range in into an sorted MSR range array.
316 *
317 * If the new MSR range overlaps existing ranges, the existing ones will be
318 * adjusted/removed to fit in the new one.
319 *
320 * @returns VBox status code.
321 * @retval VINF_SUCCESS
322 * @retval VERR_NO_MEMORY
323 *
324 * @param ppaMsrRanges The variable pointing to the ranges (input/output).
325 * @param pcMsrRanges The variable holding number of ranges.
326 * @param pNewRange The new range.
327 */
328int cpumR3MsrRangesInsert(PCPUMMSRRANGE *ppaMsrRanges, uint32_t *pcMsrRanges, PCCPUMMSRRANGE pNewRange)
329{
330 uint32_t cMsrRanges = *pcMsrRanges;
331 PCPUMMSRRANGE paMsrRanges = *ppaMsrRanges;
332
333 Assert(pNewRange->uLast >= pNewRange->uFirst);
334 Assert(pNewRange->enmRdFn > kCpumMsrRdFn_Invalid && pNewRange->enmRdFn < kCpumMsrRdFn_End);
335 Assert(pNewRange->enmWrFn > kCpumMsrWrFn_Invalid && pNewRange->enmWrFn < kCpumMsrWrFn_End);
336
337 /*
338 * Optimize the linear insertion case where we add new entries at the end.
339 */
340 if ( cMsrRanges > 0
341 && paMsrRanges[cMsrRanges - 1].uLast < pNewRange->uFirst)
342 {
343 paMsrRanges = cpumR3MsrRangesEnsureSpace(ppaMsrRanges, cMsrRanges, 1);
344 if (!paMsrRanges)
345 return VERR_NO_MEMORY;
346 paMsrRanges[cMsrRanges] = *pNewRange;
347 *pcMsrRanges += 1;
348 }
349 else
350 {
351 uint32_t i = cpumR3MsrRangesBinSearch(paMsrRanges, cMsrRanges, pNewRange->uFirst);
352 Assert(i == cMsrRanges || pNewRange->uFirst <= paMsrRanges[i].uLast);
353 Assert(i == 0 || pNewRange->uFirst > paMsrRanges[i - 1].uLast);
354
355 /*
356 * Adding an entirely new entry?
357 */
358 if ( i >= cMsrRanges
359 || pNewRange->uLast < paMsrRanges[i].uFirst)
360 {
361 paMsrRanges = cpumR3MsrRangesEnsureSpace(ppaMsrRanges, cMsrRanges, 1);
362 if (!paMsrRanges)
363 return VERR_NO_MEMORY;
364 if (i < cMsrRanges)
365 memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
366 paMsrRanges[i] = *pNewRange;
367 *pcMsrRanges += 1;
368 }
369 /*
370 * Replace existing entry?
371 */
372 else if ( pNewRange->uFirst == paMsrRanges[i].uFirst
373 && pNewRange->uLast == paMsrRanges[i].uLast)
374 paMsrRanges[i] = *pNewRange;
375 /*
376 * Splitting an existing entry?
377 */
378 else if ( pNewRange->uFirst > paMsrRanges[i].uFirst
379 && pNewRange->uLast < paMsrRanges[i].uLast)
380 {
381 paMsrRanges = cpumR3MsrRangesEnsureSpace(ppaMsrRanges, cMsrRanges, 2);
382 if (!paMsrRanges)
383 return VERR_NO_MEMORY;
384 if (i < cMsrRanges)
385 memmove(&paMsrRanges[i + 2], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
386 paMsrRanges[i + 1] = *pNewRange;
387 paMsrRanges[i + 2] = paMsrRanges[i];
388 paMsrRanges[i ].uLast = pNewRange->uFirst - 1;
389 paMsrRanges[i + 2].uFirst = pNewRange->uLast + 1;
390 *pcMsrRanges += 2;
391 }
392 /*
393 * Complicated scenarios that can affect more than one range.
394 *
395 * The current code does not optimize memmove calls when replacing
396 * one or more existing ranges, because it's tedious to deal with and
397 * not expected to be a frequent usage scenario.
398 */
399 else
400 {
401 /* Adjust start of first match? */
402 if ( pNewRange->uFirst <= paMsrRanges[i].uFirst
403 && pNewRange->uLast < paMsrRanges[i].uLast)
404 paMsrRanges[i].uFirst = pNewRange->uLast + 1;
405 else
406 {
407 /* Adjust end of first match? */
408 if (pNewRange->uFirst > paMsrRanges[i].uFirst)
409 {
410 Assert(paMsrRanges[i].uLast >= pNewRange->uFirst);
411 paMsrRanges[i].uLast = pNewRange->uFirst - 1;
412 i++;
413 }
414 /* Replace the whole first match (lazy bird). */
415 else
416 {
417 if (i + 1 < cMsrRanges)
418 memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
419 cMsrRanges = *pcMsrRanges -= 1;
420 }
421
422 /* Do the new range affect more ranges? */
423 while ( i < cMsrRanges
424 && pNewRange->uLast >= paMsrRanges[i].uFirst)
425 {
426 if (pNewRange->uLast < paMsrRanges[i].uLast)
427 {
428 /* Adjust the start of it, then we're done. */
429 paMsrRanges[i].uFirst = pNewRange->uLast + 1;
430 break;
431 }
432
433 /* Remove it entirely. */
434 if (i + 1 < cMsrRanges)
435 memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
436 cMsrRanges = *pcMsrRanges -= 1;
437 }
438 }
439
440 /* Now, perform a normal insertion. */
441 paMsrRanges = cpumR3MsrRangesEnsureSpace(ppaMsrRanges, cMsrRanges, 1);
442 if (!paMsrRanges)
443 return VERR_NO_MEMORY;
444 if (i < cMsrRanges)
445 memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
446 paMsrRanges[i] = *pNewRange;
447 *pcMsrRanges += 1;
448 }
449 }
450
451 return VINF_SUCCESS;
452}
453
454
455/**
456 * Worker for cpumR3MsrApplyFudge that applies one table.
457 *
458 * @returns VBox status code.
459 * @param pVM Pointer to the cross context VM structure.
460 * @param paRanges Array of MSRs to fudge.
461 * @param cRanges Number of MSRs in the array.
462 */
463static int cpumR3MsrApplyFudgeTable(PVM pVM, PCCPUMMSRRANGE paRanges, size_t cRanges)
464{
465 for (uint32_t i = 0; i < cRanges; i++)
466 if (!cpumLookupMsrRange(pVM, paRanges[i].uFirst))
467 {
468 LogRel(("CPUM: MSR fudge: %#010x %s\n", paRanges[i].uFirst, paRanges[i].szName));
469 int rc = cpumR3MsrRangesInsert(&pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
470 &paRanges[i]);
471 if (RT_FAILURE(rc))
472 return rc;
473 }
474 return VINF_SUCCESS;
475}
476
477
478/**
479 * Fudges the MSRs that guest are known to access in some odd cases.
480 *
481 * A typical example is a VM that has been moved between different hosts where
482 * for instance the cpu vendor differs.
483 *
484 * @returns VBox status code.
485 * @param pVM Pointer to the cross context VM structure.
486 */
487int cpumR3MsrApplyFudge(PVM pVM)
488{
489 /*
490 * Basic.
491 */
492 static CPUMMSRRANGE const s_aFudgeMsrs[] =
493 {
494 MFO(0x00000000, "IA32_P5_MC_ADDR", Ia32P5McAddr),
495 MFX(0x00000001, "IA32_P5_MC_TYPE", Ia32P5McType, Ia32P5McType, 0, 0, UINT64_MAX),
496 MVO(0x00000017, "IA32_PLATFORM_ID", 0),
497 MFN(0x0000001b, "IA32_APIC_BASE", Ia32ApicBase, Ia32ApicBase),
498 MVI(0x0000008b, "BIOS_SIGN", 0),
499 MFX(0x000000fe, "IA32_MTRRCAP", Ia32MtrrCap, ReadOnly, 0x508, 0, 0),
500 MFX(0x00000179, "IA32_MCG_CAP", Ia32McgCap, ReadOnly, 0x005, 0, 0),
501 MFX(0x0000017a, "IA32_MCG_STATUS", Ia32McgStatus, Ia32McgStatus, 0, ~(uint64_t)UINT32_MAX, 0),
502 MFN(0x000001a0, "IA32_MISC_ENABLE", Ia32MiscEnable, Ia32MiscEnable),
503 MFN(0x000001d9, "IA32_DEBUGCTL", Ia32DebugCtl, Ia32DebugCtl),
504 MFO(0x000001db, "P6_LAST_BRANCH_FROM_IP", P6LastBranchFromIp),
505 MFO(0x000001dc, "P6_LAST_BRANCH_TO_IP", P6LastBranchToIp),
506 MFO(0x000001dd, "P6_LAST_INT_FROM_IP", P6LastIntFromIp),
507 MFO(0x000001de, "P6_LAST_INT_TO_IP", P6LastIntToIp),
508 MFS(0x00000277, "IA32_PAT", Ia32Pat, Ia32Pat, Guest.msrPAT),
509 MFZ(0x000002ff, "IA32_MTRR_DEF_TYPE", Ia32MtrrDefType, Ia32MtrrDefType, GuestMsrs.msr.MtrrDefType, 0, ~(uint64_t)0xc07),
510 MFN(0x00000400, "IA32_MCi_CTL_STATUS_ADDR_MISC", Ia32McCtlStatusAddrMiscN, Ia32McCtlStatusAddrMiscN),
511 };
512 int rc = cpumR3MsrApplyFudgeTable(pVM, &s_aFudgeMsrs[0], RT_ELEMENTS(s_aFudgeMsrs));
513 AssertLogRelRCReturn(rc, rc);
514
515 /*
516 * XP might mistake opterons and other newer CPUs for P4s.
517 */
518 if (pVM->cpum.s.GuestFeatures.uFamily >= 0xf)
519 {
520 static CPUMMSRRANGE const s_aP4FudgeMsrs[] =
521 {
522 MFX(0x0000002c, "P4_EBC_FREQUENCY_ID", IntelP4EbcFrequencyId, IntelP4EbcFrequencyId, 0xf12010f, UINT64_MAX, 0),
523 };
524 rc = cpumR3MsrApplyFudgeTable(pVM, &s_aP4FudgeMsrs[0], RT_ELEMENTS(s_aP4FudgeMsrs));
525 AssertLogRelRCReturn(rc, rc);
526 }
527
528 return rc;
529}
530
531
532int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo)
533{
534 CPUMDBENTRY const *pEntry = NULL;
535 int rc;
536
537 if (!strcmp(pszName, "host"))
538 {
539 /*
540 * Create a CPU database entry for the host CPU. This means getting
541 * the CPUID bits from the real CPU and grabbing the closest matching
542 * database entry for MSRs.
543 */
544 rc = CPUMR3CpuIdDetectUnknownLeafMethod(&pInfo->enmUnknownCpuIdMethod, &pInfo->DefCpuId);
545 if (RT_FAILURE(rc))
546 return rc;
547 rc = CPUMR3CpuIdCollectLeaves(&pInfo->paCpuIdLeavesR3, &pInfo->cCpuIdLeaves);
548 if (RT_FAILURE(rc))
549 return rc;
550
551 /* Lookup database entry for MSRs. */
552 CPUMCPUVENDOR const enmVendor = CPUMR3CpuIdDetectVendorEx(pInfo->paCpuIdLeavesR3[0].uEax,
553 pInfo->paCpuIdLeavesR3[0].uEbx,
554 pInfo->paCpuIdLeavesR3[0].uEcx,
555 pInfo->paCpuIdLeavesR3[0].uEdx);
556 uint32_t const uStd1Eax = pInfo->paCpuIdLeavesR3[1].uEax;
557 uint8_t const uFamily = ASMGetCpuFamily(uStd1Eax);
558 uint8_t const uModel = ASMGetCpuModel(uStd1Eax, enmVendor == CPUMCPUVENDOR_INTEL);
559 uint8_t const uStepping = ASMGetCpuStepping(uStd1Eax);
560 CPUMMICROARCH const enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx(enmVendor, uFamily, uModel, uStepping);
561
562 for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
563 {
564 CPUMDBENTRY const *pCur = g_apCpumDbEntries[i];
565 if ((CPUMCPUVENDOR)pCur->enmVendor == enmVendor)
566 {
567 /* Match against Family, Microarch, model and stepping. Except
568 for family, always match the closer with preference given to
569 the later/older ones. */
570 if (pCur->uFamily == uFamily)
571 {
572 if (pCur->enmMicroarch == enmMicroarch)
573 {
574 if (pCur->uModel == uModel)
575 {
576 if (pCur->uStepping == uStepping)
577 {
578 /* Perfect match. */
579 pEntry = pCur;
580 break;
581 }
582
583 if ( !pEntry
584 || pEntry->uModel != uModel
585 || pEntry->enmMicroarch != enmMicroarch
586 || pEntry->uFamily != uFamily)
587 pEntry = pCur;
588 else if ( pCur->uStepping >= uStepping
589 ? pCur->uStepping < pEntry->uStepping || pEntry->uStepping < uStepping
590 : pCur->uStepping > pEntry->uStepping)
591 pEntry = pCur;
592 }
593 else if ( !pEntry
594 || pEntry->enmMicroarch != enmMicroarch
595 || pEntry->uFamily != uFamily)
596 pEntry = pCur;
597 else if ( pCur->uModel >= uModel
598 ? pCur->uModel < pEntry->uModel || pEntry->uModel < uModel
599 : pCur->uModel > pEntry->uModel)
600 pEntry = pCur;
601 }
602 else if ( !pEntry
603 || pEntry->uFamily != uFamily)
604 pEntry = pCur;
605 else if ( pCur->enmMicroarch >= enmMicroarch
606 ? pCur->enmMicroarch < pEntry->enmMicroarch || pEntry->enmMicroarch < enmMicroarch
607 : pCur->enmMicroarch > pEntry->enmMicroarch)
608 pEntry = pCur;
609 }
610 /* We don't do closeness matching on family, we use the first
611 entry for the CPU vendor instead. (P4 workaround.) */
612 else if (!pEntry)
613 pEntry = pCur;
614 }
615 }
616
617 if (pEntry)
618 LogRel(("CPUM: Matched host CPU %s %#x/%#x/%#x %s with CPU DB entry '%s' (%s %#x/%#x/%#x %s).\n",
619 CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
620 pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor), pEntry->uFamily, pEntry->uModel,
621 pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
622 else
623 {
624 pEntry = g_apCpumDbEntries[0];
625 LogRel(("CPUM: No matching processor database entry %s %#x/%#x/%#x %s, falling back on '%s'.\n",
626 CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
627 pEntry->pszName));
628 }
629 }
630 else
631 {
632 /*
633 * We're supposed to be emulating a specific CPU that is included in
634 * our CPU database. The CPUID tables needs to be copied onto the
635 * heap so the caller can modify them and so they can be freed like
636 * in the host case above.
637 */
638 for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
639 if (!strcmp(pszName, g_apCpumDbEntries[i]->pszName))
640 {
641 pEntry = g_apCpumDbEntries[i];
642 break;
643 }
644 if (!pEntry)
645 {
646 LogRel(("CPUM: Cannot locate any CPU by the name '%s'\n", pszName));
647 return VERR_CPUM_DB_CPU_NOT_FOUND;
648 }
649
650 pInfo->cCpuIdLeaves = pEntry->cCpuIdLeaves;
651 if (pEntry->cCpuIdLeaves)
652 {
653 pInfo->paCpuIdLeavesR3 = (PCPUMCPUIDLEAF)RTMemDup(pEntry->paCpuIdLeaves,
654 sizeof(pEntry->paCpuIdLeaves[0]) * pEntry->cCpuIdLeaves);
655 if (!pInfo->paCpuIdLeavesR3)
656 return VERR_NO_MEMORY;
657 }
658 else
659 pInfo->paCpuIdLeavesR3 = NULL;
660
661 pInfo->enmUnknownCpuIdMethod = pEntry->enmUnknownCpuId;
662 pInfo->DefCpuId = pEntry->DefUnknownCpuId;
663
664 LogRel(("CPUM: Using CPU DB entry '%s' (%s %#x/%#x/%#x %s).\n",
665 pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor),
666 pEntry->uFamily, pEntry->uModel, pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
667 }
668
669 pInfo->fMsrMask = pEntry->fMsrMask;
670 pInfo->iFirstExtCpuIdLeaf = 0; /* Set by caller. */
671 pInfo->uPadding = 0;
672 pInfo->uScalableBusFreq = pEntry->uScalableBusFreq;
673 pInfo->paCpuIdLeavesR0 = NIL_RTR0PTR;
674 pInfo->paMsrRangesR0 = NIL_RTR0PTR;
675 pInfo->paCpuIdLeavesRC = NIL_RTRCPTR;
676 pInfo->paMsrRangesRC = NIL_RTRCPTR;
677
678 /*
679 * Copy the MSR range.
680 */
681 uint32_t cMsrs = 0;
682 PCPUMMSRRANGE paMsrs = NULL;
683
684 PCCPUMMSRRANGE pCurMsr = pEntry->paMsrRanges;
685 uint32_t cLeft = pEntry->cMsrRanges;
686 while (cLeft-- > 0)
687 {
688 rc = cpumR3MsrRangesInsert(&paMsrs, &cMsrs, pCurMsr);
689 if (RT_FAILURE(rc))
690 {
691 Assert(!paMsrs); /* The above function frees this. */
692 RTMemFree(pInfo->paCpuIdLeavesR3);
693 pInfo->paCpuIdLeavesR3 = NULL;
694 return rc;
695 }
696 pCurMsr++;
697 }
698
699 pInfo->paMsrRangesR3 = paMsrs;
700 pInfo->cMsrRanges = cMsrs;
701 return VINF_SUCCESS;
702}
703
704
705/**
706 * Register statistics for the MSRs.
707 *
708 * This must not be called before the MSRs have been finalized and moved to the
709 * hyper heap.
710 *
711 * @returns VBox status code.
712 * @param pVM Pointer to the cross context VM structure.
713 */
714int cpumR3MsrRegStats(PVM pVM)
715{
716 /*
717 * Global statistics.
718 */
719 PCPUM pCpum = &pVM->cpum.s;
720 STAM_REL_REG(pVM, &pCpum->cMsrReads, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Reads",
721 STAMUNIT_OCCURENCES, "All RDMSRs making it to CPUM.");
722 STAM_REL_REG(pVM, &pCpum->cMsrReadsRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsRaisingGP",
723 STAMUNIT_OCCURENCES, "RDMSR raising #GPs, except unknown MSRs.");
724 STAM_REL_REG(pVM, &pCpum->cMsrReadsUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsUnknown",
725 STAMUNIT_OCCURENCES, "RDMSR on unknown MSRs (raises #GP).");
726 STAM_REL_REG(pVM, &pCpum->cMsrWrites, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Writes",
727 STAMUNIT_OCCURENCES, "All RDMSRs making it to CPUM.");
728 STAM_REL_REG(pVM, &pCpum->cMsrWritesRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesRaisingGP",
729 STAMUNIT_OCCURENCES, "WRMSR raising #GPs, except unknown MSRs.");
730 STAM_REL_REG(pVM, &pCpum->cMsrWritesToIgnoredBits, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesToIgnoredBits",
731 STAMUNIT_OCCURENCES, "Writing of ignored bits.");
732 STAM_REL_REG(pVM, &pCpum->cMsrWritesUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesUnknown",
733 STAMUNIT_OCCURENCES, "WRMSR on unknown MSRs (raises #GP).");
734
735
736# ifdef VBOX_WITH_STATISTICS
737 /*
738 * Per range.
739 */
740 PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.paMsrRangesR3;
741 uint32_t cRanges = pVM->cpum.s.GuestInfo.cMsrRanges;
742 for (uint32_t i = 0; i < cRanges; i++)
743 {
744 char szName[160];
745 ssize_t cchName;
746
747 if (paRanges[i].uFirst == paRanges[i].uLast)
748 cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%s",
749 paRanges[i].uFirst, paRanges[i].szName);
750 else
751 cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%#010x-%s",
752 paRanges[i].uFirst, paRanges[i].uLast, paRanges[i].szName);
753
754 RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-reads");
755 STAMR3Register(pVM, &paRanges[i].cReads, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, szName, STAMUNIT_OCCURENCES, "RDMSR");
756
757 RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-writes");
758 STAMR3Register(pVM, &paRanges[i].cWrites, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR");
759
760 RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-GPs");
761 STAMR3Register(pVM, &paRanges[i].cGps, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "#GPs");
762
763 RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-ign-bits-writes");
764 STAMR3Register(pVM, &paRanges[i].cIgnoredBits, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR w/ ignored bits");
765 }
766# endif /* VBOX_WITH_STATISTICS */
767
768 return VINF_SUCCESS;
769}
770
771#endif /* !CPUM_DB_STANDALONE */
772
注意: 瀏覽 TracBrowser 來幫助您使用儲存庫瀏覽器

© 2025 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette