CPUMR3Db.cpp@ 50157

最後變更在這個檔案從50157是 50157,由 vboxsync 提交於 11 年前
CPUMR3Db.cpp: Redid the cpu database matching (cpumR3DbGetCpuInfo) to not end up with P4 for unknown intel CPUs.
屬性 svn:eol-style 設為 `native` 屬性 svn:keywords 設為 `Author Date Id Revision`
檔案大小: 31.7 KB

行
1	/* $Id: CPUMR3Db.cpp 50157 2014-01-22 02:07:16Z vboxsync $ */
2	/** @file
3	* CPUM - CPU database part.
4	*/
5
6	/*
7	* Copyright (C) 2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.alldomusa.eu.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_CPUM
22	#include <VBox/vmm/cpum.h>
23	#include "CPUMInternal.h"
24	#include <VBox/vmm/vm.h>
25
26	#include <VBox/err.h>
27	#include <iprt/asm-amd64-x86.h>
28	#include <iprt/mem.h>
29	#include <iprt/string.h>
30
31
32	/*******************************************************************************
33	* Structures and Typedefs *
34	*******************************************************************************/
35	typedef struct CPUMDBENTRY
36	{
37	/** The CPU name. */
38	const char *pszName;
39	/** The full CPU name. */
40	const char *pszFullName;
41	/** The CPU vendor (CPUMCPUVENDOR). */
42	uint8_t enmVendor;
43	/** The CPU family. */
44	uint8_t uFamily;
45	/** The CPU model. */
46	uint8_t uModel;
47	/** The CPU stepping. */
48	uint8_t uStepping;
49	/** The microarchitecture. */
50	CPUMMICROARCH enmMicroarch;
51	/** Flags (TBD). */
52	uint32_t fFlags;
53	/** The maximum physical address with of the CPU. This should correspond to
54	* the value in CPUID leaf 0x80000008 when present. */
55	uint8_t cMaxPhysAddrWidth;
56	/** Pointer to an array of CPUID leaves. */
57	PCCPUMCPUIDLEAF paCpuIdLeaves;
58	/** The number of CPUID leaves in the array paCpuIdLeaves points to. */
59	uint32_t cCpuIdLeaves;
60	/** The method used to deal with unknown CPUID leaves. */
61	CPUMUKNOWNCPUID enmUnknownCpuId;
62	/** The default unknown CPUID value. */
63	CPUMCPUID DefUnknownCpuId;
64
65	/** MSR mask. Several microarchitectures ignore higher bits of the */
66	uint32_t fMsrMask;
67
68	/** The number of ranges in the table pointed to b paMsrRanges. */
69	uint32_t cMsrRanges;
70	/** MSR ranges for this CPU. */
71	PCCPUMMSRRANGE paMsrRanges;
72	} CPUMDBENTRY;
73
74
75	/*******************************************************************************
76	* Defined Constants And Macros *
77	*******************************************************************************/
78
79	/** @def NULL_ALONE
80	* For eliminating an unnecessary data dependency in standalone builds (for
81	* VBoxSVC). */
82	/** @def ZERO_ALONE
83	* For eliminating an unnecessary data size dependency in standalone builds (for
84	* VBoxSVC). */
85	#ifndef CPUM_DB_STANDALONE
86	# define NULL_ALONE(a_aTable) a_aTable
87	# define ZERO_ALONE(a_cTable) a_cTable
88	#else
89	# define NULL_ALONE(a_aTable) NULL
90	# define ZERO_ALONE(a_cTable) 0
91	#endif
92
93
94	/** @name Short macros for the MSR range entries.
95	*
96	* These are rather cryptic, but this is to reduce the attack on the right
97	* margin.
98	*
99	* @{ */
100	/** Alias one MSR onto another (a_uTarget). */
101	#define MAL(a_uMsr, a_szName, a_uTarget) \
102	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_MsrAlias, kCpumMsrWrFn_MsrAlias, 0, a_uTarget, 0, 0, a_szName)
103	/** Functions handles everything. */
104	#define MFN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
105	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
106	/** Functions handles everything, with GP mask. */
107	#define MFG(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrGpMask) \
108	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, a_fWrGpMask, a_szName)
109	/** Function handlers, read-only. */
110	#define MFO(a_uMsr, a_szName, a_enmRdFnSuff) \
111	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_ReadOnly, 0, 0, 0, UINT64_MAX, a_szName)
112	/** Function handlers, ignore all writes. */
113	#define MFI(a_uMsr, a_szName, a_enmRdFnSuff) \
114	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_IgnoreWrite, 0, 0, UINT64_MAX, 0, a_szName)
115	/** Function handlers, with value. */
116	#define MFV(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue) \
117	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, 0, 0, a_szName)
118	/** Function handlers, with write ignore mask. */
119	#define MFW(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrIgnMask) \
120	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, a_fWrIgnMask, 0, a_szName)
121	/** Function handlers, extended version. */
122	#define MFX(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
123	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
124	/** Function handlers, with CPUMCPU storage variable. */
125	#define MFS(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember) \
126	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
127	RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, 0, 0, a_szName)
128	/** Function handlers, with CPUMCPU storage variable, ignore mask and GP mask. */
129	#define MFZ(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember, a_fWrIgnMask, a_fWrGpMask) \
130	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
131	RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, a_fWrIgnMask, a_fWrGpMask, a_szName)
132	/** Read-only fixed value. */
133	#define MVO(a_uMsr, a_szName, a_uValue) \
134	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
135	/** Read-only fixed value, ignores all writes. */
136	#define MVI(a_uMsr, a_szName, a_uValue) \
137	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
138	/** Read fixed value, ignore writes outside GP mask. */
139	#define MVG(a_uMsr, a_szName, a_uValue, a_fWrGpMask) \
140	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, 0, a_fWrGpMask, a_szName)
141	/** Read fixed value, extended version with both GP and ignore masks. */
142	#define MVX(a_uMsr, a_szName, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
143	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
144	/** The short form, no CPUM backing. */
145	#define MSN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
146	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
147	a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
148
149	/** Range: Functions handles everything. */
150	#define RFN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
151	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
152	/** Range: Read fixed value, read-only. */
153	#define RVO(a_uFirst, a_uLast, a_szName, a_uValue) \
154	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
155	/** Range: Read fixed value, ignore writes. */
156	#define RVI(a_uFirst, a_uLast, a_szName, a_uValue) \
157	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
158	/** Range: The short form, no CPUM backing. */
159	#define RSN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
160	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
161	a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
162
163	/** Internal form used by the macros. */
164	#ifdef VBOX_WITH_STATISTICS
165	# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
166	{ a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName, \
167	{ 0 }, { 0 }, { 0 }, { 0 } }
168	#else
169	# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
170	{ a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName }
171	#endif
172	/** @} */
173
174
175	#include "cpus/Intel_Core_i7_3960X.h"
176	#include "cpus/Intel_Core_i5_3570.h"
177	#include "cpus/Intel_Xeon_X5482_3_20GHz.h"
178	#include "cpus/Intel_Pentium_M_processor_2_00GHz.h"
179	#include "cpus/Intel_Pentium_4_3_00GHz.h"
180
181	#include "cpus/AMD_FX_8150_Eight_Core.h"
182	#include "cpus/AMD_Phenom_II_X6_1100T.h"
183	#include "cpus/Quad_Core_AMD_Opteron_2384.h"
184	#include "cpus/AMD_Athlon_64_3200.h"
185
186	#include "cpus/VIA_QuadCore_L4700_1_2_GHz.h"
187
188
189
190	/**
191	* The database entries.
192	*
193	* 1. The first entry is special. It is the fallback for unknown
194	* processors. Thus, it better be pretty representative.
195	*
196	* 2. The first entry for a CPU vendor is likewise important as it is
197	* the default entry for that vendor.
198	*
199	* Generally we put the most recent CPUs first, since these tend to have the
200	* most complicated and backwards compatible list of MSRs.
201	*/
202	static CPUMDBENTRY const * const g_apCpumDbEntries[] =
203	{
204	#ifdef VBOX_CPUDB_Intel_Core_i5_3570
205	&g_Entry_Intel_Core_i5_3570,
206	#endif
207	#ifdef VBOX_CPUDB_Intel_Core_i7_3960X
208	&g_Entry_Intel_Core_i7_3960X,
209	#endif
210	#ifdef Intel_Pentium_M_processor_2_00GHz
211	&g_Entry_Intel_Pentium_M_processor_2_00GHz,
212	#endif
213	#ifdef VBOX_CPUDB_Intel_Xeon_X5482_3_20GHz
214	&g_Entry_Intel_Xeon_X5482_3_20GHz,
215	#endif
216	#ifdef VBOX_CPUDB_Intel_Pentium_4_3_00GHz
217	&g_Entry_Intel_Pentium_4_3_00GHz,
218	#endif
219
220	#ifdef VBOX_CPUDB_AMD_FX_8150_Eight_Core
221	&g_Entry_AMD_FX_8150_Eight_Core,
222	#endif
223	#ifdef VBOX_CPUDB_AMD_Phenom_II_X6_1100T
224	&g_Entry_AMD_Phenom_II_X6_1100T,
225	#endif
226	#ifdef VBOX_CPUDB_Quad_Core_AMD_Opteron_2384
227	&g_Entry_Quad_Core_AMD_Opteron_2384,
228	#endif
229	#ifdef VBOX_CPUDB_AMD_Athlon_64_3200
230	&g_Entry_AMD_Athlon_64_3200,
231	#endif
232
233	#ifdef VBOX_CPUDB_VIA_QuadCore_L4700_1_2_GHz
234	&g_Entry_VIA_QuadCore_L4700_1_2_GHz,
235	#endif
236	};
237
238
239	#ifndef CPUM_DB_STANDALONE
240
241	/**
242	* Binary search used by cpumR3MsrRangesInsert and has some special properties
243	* wrt to mismatches.
244	*
245	* @returns Insert location.
246	* @param paMsrRanges The MSR ranges to search.
247	* @param cMsrRanges The number of MSR ranges.
248	* @param uMsr What to search for.
249	*/
250	static uint32_t cpumR3MsrRangesBinSearch(PCCPUMMSRRANGE paMsrRanges, uint32_t cMsrRanges, uint32_t uMsr)
251	{
252	if (!cMsrRanges)
253	return 0;
254
255	uint32_t iStart = 0;
256	uint32_t iLast = cMsrRanges - 1;
257	for (;;)
258	{
259	uint32_t i = iStart + (iLast - iStart + 1) / 2;
260	if ( uMsr >= paMsrRanges[i].uFirst
261	&& uMsr <= paMsrRanges[i].uLast)
262	return i;
263	if (uMsr < paMsrRanges[i].uFirst)
264	{
265	if (i <= iStart)
266	return i;
267	iLast = i - 1;
268	}
269	else
270	{
271	if (i >= iLast)
272	{
273	if (i < cMsrRanges)
274	i++;
275	return i;
276	}
277	iStart = i + 1;
278	}
279	}
280	}
281
282
283	/**
284	* Ensures that there is space for at least @a cNewRanges in the table,
285	* reallocating the table if necessary.
286	*
287	* @returns Pointer to the MSR ranges on success, NULL on failure. On failure
288	* @a *ppaMsrRanges is freed and set to NULL.
289	* @param ppaMsrRanges The variable pointing to the ranges (input/output).
290	* @param cMsrRanges The current number of ranges.
291	* @param cNewRanges The number of ranges to be added.
292	*/
293	static PCPUMMSRRANGE cpumR3MsrRangesEnsureSpace(PCPUMMSRRANGE *ppaMsrRanges, uint32_t cMsrRanges, uint32_t cNewRanges)
294	{
295	uint32_t cMsrRangesAllocated = RT_ALIGN_32(cMsrRanges, 16);
296	if (cMsrRangesAllocated < cMsrRanges + cNewRanges)
297	{
298	uint32_t cNew = RT_ALIGN_32(cMsrRanges + cNewRanges, 16);
299	void pvNew = RTMemRealloc(ppaMsrRanges, cNew * sizeof(**ppaMsrRanges));
300	if (!pvNew)
301	{
302	RTMemFree(*ppaMsrRanges);
303	*ppaMsrRanges = NULL;
304	return NULL;
305	}
306	*ppaMsrRanges = (PCPUMMSRRANGE)pvNew;
307	}
308	return *ppaMsrRanges;
309	}
310
311
312	/**
313	* Inserts a new MSR range in into an sorted MSR range array.
314	*
315	* If the new MSR range overlaps existing ranges, the existing ones will be
316	* adjusted/removed to fit in the new one.
317	*
318	* @returns VBox status code.
319	* @retval VINF_SUCCESS
320	* @retval VERR_NO_MEMORY
321	*
322	* @param ppaMsrRanges The variable pointing to the ranges (input/output).
323	* @param pcMsrRanges The variable holding number of ranges.
324	* @param pNewRange The new range.
325	*/
326	int cpumR3MsrRangesInsert(PCPUMMSRRANGE ppaMsrRanges, uint32_t pcMsrRanges, PCCPUMMSRRANGE pNewRange)
327	{
328	uint32_t cMsrRanges = *pcMsrRanges;
329	PCPUMMSRRANGE paMsrRanges = *ppaMsrRanges;
330
331	Assert(pNewRange->uLast >= pNewRange->uFirst);
332	Assert(pNewRange->enmRdFn > kCpumMsrRdFn_Invalid && pNewRange->enmRdFn < kCpumMsrRdFn_End);
333	Assert(pNewRange->enmWrFn > kCpumMsrWrFn_Invalid && pNewRange->enmWrFn < kCpumMsrWrFn_End);
334
335	/*
336	* Optimize the linear insertion case where we add new entries at the end.
337	*/
338	if ( cMsrRanges > 0
339	&& paMsrRanges[cMsrRanges - 1].uLast < pNewRange->uFirst)
340	{
341	paMsrRanges = cpumR3MsrRangesEnsureSpace(ppaMsrRanges, cMsrRanges, 1);
342	if (!paMsrRanges)
343	return VERR_NO_MEMORY;
344	paMsrRanges[cMsrRanges] = *pNewRange;
345	*pcMsrRanges += 1;
346	}
347	else
348	{
349	uint32_t i = cpumR3MsrRangesBinSearch(paMsrRanges, cMsrRanges, pNewRange->uFirst);
350	Assert(i == cMsrRanges \|\| pNewRange->uFirst <= paMsrRanges[i].uLast);
351	Assert(i == 0 \|\| pNewRange->uFirst > paMsrRanges[i - 1].uLast);
352
353	/*
354	* Adding an entirely new entry?
355	*/
356	if ( i >= cMsrRanges
357	\|\| pNewRange->uLast < paMsrRanges[i].uFirst)
358	{
359	paMsrRanges = cpumR3MsrRangesEnsureSpace(ppaMsrRanges, cMsrRanges, 1);
360	if (!paMsrRanges)
361	return VERR_NO_MEMORY;
362	if (i < cMsrRanges)
363	memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
364	paMsrRanges[i] = *pNewRange;
365	*pcMsrRanges += 1;
366	}
367	/*
368	* Replace existing entry?
369	*/
370	else if ( pNewRange->uFirst == paMsrRanges[i].uFirst
371	&& pNewRange->uLast == paMsrRanges[i].uLast)
372	paMsrRanges[i] = *pNewRange;
373	/*
374	* Splitting an existing entry?
375	*/
376	else if ( pNewRange->uFirst > paMsrRanges[i].uFirst
377	&& pNewRange->uLast < paMsrRanges[i].uLast)
378	{
379	paMsrRanges = cpumR3MsrRangesEnsureSpace(ppaMsrRanges, cMsrRanges, 2);
380	if (!paMsrRanges)
381	return VERR_NO_MEMORY;
382	if (i < cMsrRanges)
383	memmove(&paMsrRanges[i + 2], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
384	paMsrRanges[i + 1] = *pNewRange;
385	paMsrRanges[i + 2] = paMsrRanges[i];
386	paMsrRanges[i ].uLast = pNewRange->uFirst - 1;
387	paMsrRanges[i + 2].uFirst = pNewRange->uLast + 1;
388	*pcMsrRanges += 2;
389	}
390	/*
391	* Complicated scenarios that can affect more than one range.
392	*
393	* The current code does not optimize memmove calls when replacing
394	* one or more existing ranges, because it's tedious to deal with and
395	* not expected to be a frequent usage scenario.
396	*/
397	else
398	{
399	/* Adjust start of first match? */
400	if ( pNewRange->uFirst <= paMsrRanges[i].uFirst
401	&& pNewRange->uLast < paMsrRanges[i].uLast)
402	paMsrRanges[i].uFirst = pNewRange->uLast + 1;
403	else
404	{
405	/* Adjust end of first match? */
406	if (pNewRange->uFirst > paMsrRanges[i].uFirst)
407	{
408	Assert(paMsrRanges[i].uLast >= pNewRange->uFirst);
409	paMsrRanges[i].uLast = pNewRange->uFirst - 1;
410	i++;
411	}
412	/* Replace the whole first match (lazy bird). */
413	else
414	{
415	if (i + 1 < cMsrRanges)
416	memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
417	cMsrRanges = *pcMsrRanges -= 1;
418	}
419
420	/* Do the new range affect more ranges? */
421	while ( i < cMsrRanges
422	&& pNewRange->uLast >= paMsrRanges[i].uFirst)
423	{
424	if (pNewRange->uLast < paMsrRanges[i].uLast)
425	{
426	/* Adjust the start of it, then we're done. */
427	paMsrRanges[i].uFirst = pNewRange->uLast + 1;
428	break;
429	}
430
431	/* Remove it entirely. */
432	if (i + 1 < cMsrRanges)
433	memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
434	cMsrRanges = *pcMsrRanges -= 1;
435	}
436	}
437
438	/* Now, perform a normal insertion. */
439	paMsrRanges = cpumR3MsrRangesEnsureSpace(ppaMsrRanges, cMsrRanges, 1);
440	if (!paMsrRanges)
441	return VERR_NO_MEMORY;
442	if (i < cMsrRanges)
443	memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
444	paMsrRanges[i] = *pNewRange;
445	*pcMsrRanges += 1;
446	}
447	}
448
449	return VINF_SUCCESS;
450	}
451
452
453	/**
454	* Worker for cpumR3MsrApplyFudge that applies one table.
455	*
456	* @returns VBox status code.
457	* @param pVM Pointer to the cross context VM structure.
458	* @param paRanges Array of MSRs to fudge.
459	* @param cRanges Number of MSRs in the array.
460	*/
461	static int cpumR3MsrApplyFudgeTable(PVM pVM, PCCPUMMSRRANGE paRanges, size_t cRanges)
462	{
463	for (uint32_t i = 0; i < cRanges; i++)
464	if (!cpumLookupMsrRange(pVM, paRanges[i].uFirst))
465	{
466	LogRel(("CPUM: MSR fudge: %#010x %s\n", paRanges[i].uFirst, paRanges[i].szName));
467	int rc = cpumR3MsrRangesInsert(&pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
468	&paRanges[i]);
469	if (RT_FAILURE(rc))
470	return rc;
471	}
472	return VINF_SUCCESS;
473	}
474
475
476	/**
477	* Fudges the MSRs that guest are known to access in some odd cases.
478	*
479	* A typical example is a VM that has been moved between different hosts where
480	* for instance the cpu vendor differs.
481	*
482	* @returns VBox status code.
483	* @param pVM Pointer to the cross context VM structure.
484	*/
485	int cpumR3MsrApplyFudge(PVM pVM)
486	{
487	/*
488	* Basic.
489	*/
490	static CPUMMSRRANGE const s_aFudgeMsrs[] =
491	{
492	MFO(0x00000000, "IA32_P5_MC_ADDR", Ia32P5McAddr),
493	MFX(0x00000001, "IA32_P5_MC_TYPE", Ia32P5McType, Ia32P5McType, 0, 0, UINT64_MAX),
494	MVO(0x00000017, "IA32_PLATFORM_ID", 0),
495	MFN(0x0000001b, "IA32_APIC_BASE", Ia32ApicBase, Ia32ApicBase),
496	MVI(0x0000008b, "BIOS_SIGN", 0),
497	MFX(0x000000fe, "IA32_MTRRCAP", Ia32MtrrCap, ReadOnly, 0x508, 0, 0),
498	MFX(0x00000179, "IA32_MCG_CAP", Ia32McgCap, ReadOnly, 0x005, 0, 0),
499	MFX(0x0000017a, "IA32_MCG_STATUS", Ia32McgStatus, Ia32McgStatus, 0, ~(uint64_t)UINT32_MAX, 0),
500	MFN(0x000001a0, "IA32_MISC_ENABLE", Ia32MiscEnable, Ia32MiscEnable),
501	MFN(0x000001d9, "IA32_DEBUGCTL", Ia32DebugCtl, Ia32DebugCtl),
502	MFO(0x000001db, "P6_LAST_BRANCH_FROM_IP", P6LastBranchFromIp),
503	MFO(0x000001dc, "P6_LAST_BRANCH_TO_IP", P6LastBranchToIp),
504	MFO(0x000001dd, "P6_LAST_INT_FROM_IP", P6LastIntFromIp),
505	MFO(0x000001de, "P6_LAST_INT_TO_IP", P6LastIntToIp),
506	MFS(0x00000277, "IA32_PAT", Ia32Pat, Ia32Pat, Guest.msrPAT),
507	MFZ(0x000002ff, "IA32_MTRR_DEF_TYPE", Ia32MtrrDefType, Ia32MtrrDefType, GuestMsrs.msr.MtrrDefType, 0, ~(uint64_t)0xc07),
508	MFN(0x00000400, "IA32_MCi_CTL_STATUS_ADDR_MISC", Ia32McCtlStatusAddrMiscN, Ia32McCtlStatusAddrMiscN),
509	};
510	int rc = cpumR3MsrApplyFudgeTable(pVM, &s_aFudgeMsrs[0], RT_ELEMENTS(s_aFudgeMsrs));
511	AssertLogRelRCReturn(rc, rc);
512
513	/*
514	* XP might mistake opterons and other newer CPUs for P4s.
515	*/
516	if (pVM->cpum.s.GuestFeatures.uFamily >= 0xf)
517	{
518	static CPUMMSRRANGE const s_aP4FudgeMsrs[] =
519	{
520	MFX(0x0000002c, "P4_EBC_FREQUENCY_ID", IntelP4EbcFrequencyId, IntelP4EbcFrequencyId, 0xf12010f, UINT64_MAX, 0),
521	};
522	rc = cpumR3MsrApplyFudgeTable(pVM, &s_aP4FudgeMsrs[0], RT_ELEMENTS(s_aP4FudgeMsrs));
523	AssertLogRelRCReturn(rc, rc);
524	}
525
526	return rc;
527	}
528
529
530	int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo)
531	{
532	CPUMDBENTRY const *pEntry = NULL;
533	int rc;
534
535	if (!strcmp(pszName, "host"))
536	{
537	/*
538	* Create a CPU database entry for the host CPU. This means getting
539	* the CPUID bits from the real CPU and grabbing the closest matching
540	* database entry for MSRs.
541	*/
542	rc = CPUMR3CpuIdDetectUnknownLeafMethod(&pInfo->enmUnknownCpuIdMethod, &pInfo->DefCpuId);
543	if (RT_FAILURE(rc))
544	return rc;
545	rc = CPUMR3CpuIdCollectLeaves(&pInfo->paCpuIdLeavesR3, &pInfo->cCpuIdLeaves);
546	if (RT_FAILURE(rc))
547	return rc;
548
549	/* Lookup database entry for MSRs. */
550	CPUMCPUVENDOR const enmVendor = CPUMR3CpuIdDetectVendorEx(pInfo->paCpuIdLeavesR3[0].uEax,
551	pInfo->paCpuIdLeavesR3[0].uEbx,
552	pInfo->paCpuIdLeavesR3[0].uEcx,
553	pInfo->paCpuIdLeavesR3[0].uEdx);
554	uint32_t const uStd1Eax = pInfo->paCpuIdLeavesR3[1].uEax;
555	uint8_t const uFamily = ASMGetCpuFamily(uStd1Eax);
556	uint8_t const uModel = ASMGetCpuModel(uStd1Eax, enmVendor == CPUMCPUVENDOR_INTEL);
557	uint8_t const uStepping = ASMGetCpuStepping(uStd1Eax);
558	CPUMMICROARCH const enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx(enmVendor, uFamily, uModel, uStepping);
559
560	for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
561	{
562	CPUMDBENTRY const *pCur = g_apCpumDbEntries[i];
563	if ((CPUMCPUVENDOR)pCur->enmVendor == enmVendor)
564	{
565	/* Match against Family, Microarch, model and stepping. Except
566	for family, always match the closer with preference given to
567	the later/older ones. */
568	if (pCur->uFamily == uFamily)
569	{
570	if (pCur->enmMicroarch == enmMicroarch)
571	{
572	if (pCur->uModel == uModel)
573	{
574	if (pCur->uStepping == uStepping)
575	{
576	/* Perfect match. */
577	pEntry = pCur;
578	break;
579	}
580
581	if ( !pEntry
582	\|\| pEntry->uModel != uModel
583	\|\| pEntry->enmMicroarch != enmMicroarch
584	\|\| pEntry->uFamily != uFamily)
585	pEntry = pCur;
586	else if ( pCur->uStepping >= uStepping
587	? pCur->uStepping < pEntry->uStepping \|\| pEntry->uStepping < uStepping
588	: pCur->uStepping > pEntry->uStepping)
589	pEntry = pCur;
590	}
591	else if ( !pEntry
592	\|\| pEntry->enmMicroarch != enmMicroarch
593	\|\| pEntry->uFamily != uFamily)
594	pEntry = pCur;
595	else if ( pCur->uModel >= uModel
596	? pCur->uModel < pEntry->uModel \|\| pEntry->uModel < uModel
597	: pCur->uModel > pEntry->uModel)
598	pEntry = pCur;
599	}
600	else if ( !pEntry
601	\|\| pEntry->uFamily != uFamily)
602	pEntry = pCur;
603	else if ( pCur->enmMicroarch >= enmMicroarch
604	? pCur->enmMicroarch < pEntry->enmMicroarch \|\| pEntry->enmMicroarch < enmMicroarch
605	: pCur->enmMicroarch > pEntry->enmMicroarch)
606	pEntry = pCur;
607	}
608	/* We don't do closeness matching on family, we use the first
609	entry for the CPU vendor instead. (P4 workaround.) */
610	else if (!pEntry)
611	pEntry = pCur;
612	}
613	}
614
615	if (pEntry)
616	LogRel(("CPUM: Matched host CPU %s %#x/%#x/%#x %s with CPU DB entry '%s' (%s %#x/%#x/%#x %s).\n",
617	CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
618	pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor), pEntry->uFamily, pEntry->uModel,
619	pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
620	else
621	{
622	pEntry = g_apCpumDbEntries[0];
623	LogRel(("CPUM: No matching processor database entry %s %#x/%#x/%#x %s, falling back on '%s'.\n",
624	CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
625	pEntry->pszName));
626	}
627	}
628	else
629	{
630	/*
631	* We're supposed to be emulating a specific CPU that is included in
632	* our CPU database. The CPUID tables needs to be copied onto the
633	* heap so the caller can modify them and so they can be freed like
634	* in the host case above.
635	*/
636	for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
637	if (!strcmp(pszName, g_apCpumDbEntries[i]->pszName))
638	{
639	pEntry = g_apCpumDbEntries[i];
640	break;
641	}
642	if (!pEntry)
643	{
644	LogRel(("CPUM: Cannot locate any CPU by the name '%s'\n", pszName));
645	return VERR_CPUM_DB_CPU_NOT_FOUND;
646	}
647
648	pInfo->cCpuIdLeaves = pEntry->cCpuIdLeaves;
649	if (pEntry->cCpuIdLeaves)
650	{
651	pInfo->paCpuIdLeavesR3 = (PCPUMCPUIDLEAF)RTMemDup(pEntry->paCpuIdLeaves,
652	sizeof(pEntry->paCpuIdLeaves[0]) * pEntry->cCpuIdLeaves);
653	if (!pInfo->paCpuIdLeavesR3)
654	return VERR_NO_MEMORY;
655	}
656	else
657	pInfo->paCpuIdLeavesR3 = NULL;
658
659	pInfo->enmUnknownCpuIdMethod = pEntry->enmUnknownCpuId;
660	pInfo->DefCpuId = pEntry->DefUnknownCpuId;
661
662	LogRel(("CPUM: Using CPU DB entry '%s' (%s %#x/%#x/%#x %s).\n",
663	pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor),
664	pEntry->uFamily, pEntry->uModel, pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
665	}
666
667	pInfo->fMsrMask = pEntry->fMsrMask;
668	pInfo->iFirstExtCpuIdLeaf = 0; /* Set by caller. */
669	pInfo->uPadding = 0;
670	pInfo->paCpuIdLeavesR0 = NIL_RTR0PTR;
671	pInfo->paMsrRangesR0 = NIL_RTR0PTR;
672	pInfo->paCpuIdLeavesRC = NIL_RTRCPTR;
673	pInfo->paMsrRangesRC = NIL_RTRCPTR;
674
675	/*
676	* Copy the MSR range.
677	*/
678	uint32_t cMsrs = 0;
679	PCPUMMSRRANGE paMsrs = NULL;
680
681	PCCPUMMSRRANGE pCurMsr = pEntry->paMsrRanges;
682	uint32_t cLeft = pEntry->cMsrRanges;
683	while (cLeft-- > 0)
684	{
685	rc = cpumR3MsrRangesInsert(&paMsrs, &cMsrs, pCurMsr);
686	if (RT_FAILURE(rc))
687	{
688	Assert(!paMsrs); /* The above function frees this. */
689	RTMemFree(pInfo->paCpuIdLeavesR3);
690	pInfo->paCpuIdLeavesR3 = NULL;
691	return rc;
692	}
693	pCurMsr++;
694	}
695
696	pInfo->paMsrRangesR3 = paMsrs;
697	pInfo->cMsrRanges = cMsrs;
698	return VINF_SUCCESS;
699	}
700
701
702	/**
703	* Register statistics for the MSRs.
704	*
705	* This must not be called before the MSRs have been finalized and moved to the
706	* hyper heap.
707	*
708	* @returns VBox status code.
709	* @param pVM Pointer to the cross context VM structure.
710	*/
711	int cpumR3MsrRegStats(PVM pVM)
712	{
713	/*
714	* Global statistics.
715	*/
716	PCPUM pCpum = &pVM->cpum.s;
717	STAM_REL_REG(pVM, &pCpum->cMsrReads, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Reads",
718	STAMUNIT_OCCURENCES, "All RDMSRs making it to CPUM.");
719	STAM_REL_REG(pVM, &pCpum->cMsrReadsRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsRaisingGP",
720	STAMUNIT_OCCURENCES, "RDMSR raising #GPs, except unknown MSRs.");
721	STAM_REL_REG(pVM, &pCpum->cMsrReadsUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsUnknown",
722	STAMUNIT_OCCURENCES, "RDMSR on unknown MSRs (raises #GP).");
723	STAM_REL_REG(pVM, &pCpum->cMsrWrites, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Writes",
724	STAMUNIT_OCCURENCES, "All RDMSRs making it to CPUM.");
725	STAM_REL_REG(pVM, &pCpum->cMsrWritesRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesRaisingGP",
726	STAMUNIT_OCCURENCES, "WRMSR raising #GPs, except unknown MSRs.");
727	STAM_REL_REG(pVM, &pCpum->cMsrWritesToIgnoredBits, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesToIgnoredBits",
728	STAMUNIT_OCCURENCES, "Writing of ignored bits.");
729	STAM_REL_REG(pVM, &pCpum->cMsrWritesUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesUnknown",
730	STAMUNIT_OCCURENCES, "WRMSR on unknown MSRs (raises #GP).");
731
732
733	# ifdef VBOX_WITH_STATISTICS
734	/*
735	* Per range.
736	*/
737	PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.paMsrRangesR3;
738	uint32_t cRanges = pVM->cpum.s.GuestInfo.cMsrRanges;
739	for (uint32_t i = 0; i < cRanges; i++)
740	{
741	char szName[160];
742	ssize_t cchName;
743
744	if (paRanges[i].uFirst == paRanges[i].uLast)
745	cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%s",
746	paRanges[i].uFirst, paRanges[i].szName);
747	else
748	cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%#010x-%s",
749	paRanges[i].uFirst, paRanges[i].uLast, paRanges[i].szName);
750
751	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-reads");
752	STAMR3Register(pVM, &paRanges[i].cReads, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, szName, STAMUNIT_OCCURENCES, "RDMSR");
753
754	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-writes");
755	STAMR3Register(pVM, &paRanges[i].cWrites, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR");
756
757	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-GPs");
758	STAMR3Register(pVM, &paRanges[i].cGps, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "#GPs");
759
760	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-ign-bits-writes");
761	STAMR3Register(pVM, &paRanges[i].cIgnoredBits, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR w/ ignored bits");
762	}
763	# endif /* VBOX_WITH_STATISTICS */
764
765	return VINF_SUCCESS;
766	}
767
768	#endif /* !CPUM_DB_STANDALONE */
769

注意: 瀏覽 TracBrowser 來幫助您使用儲存庫瀏覽器

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3Db.cpp@ 50157

以其他格式下載: