CPUMR3Db.cpp@ 49993

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CPUM: VIA MSR mappings (rough cut).
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1	/* $Id: CPUMR3Db.cpp 49993 2013-12-20 15:29:24Z vboxsync $ */
2	/** @file
3	* CPUM - CPU database part.
4	*/
5
6	/*
7	* Copyright (C) 2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.alldomusa.eu.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_CPUM
22	#include <VBox/vmm/cpum.h>
23	#include "CPUMInternal.h"
24	#include <VBox/vmm/vm.h>
25
26	#include <VBox/err.h>
27	#include <iprt/asm-amd64-x86.h>
28	#include <iprt/mem.h>
29	#include <iprt/string.h>
30
31
32	/*******************************************************************************
33	* Structures and Typedefs *
34	*******************************************************************************/
35	typedef struct CPUMDBENTRY
36	{
37	/** The CPU name. */
38	const char *pszName;
39	/** The full CPU name. */
40	const char *pszFullName;
41	/** The CPU vendor (CPUMCPUVENDOR). */
42	uint8_t enmVendor;
43	/** The CPU family. */
44	uint8_t uFamily;
45	/** The CPU model. */
46	uint8_t uModel;
47	/** The CPU stepping. */
48	uint8_t uStepping;
49	/** The microarchitecture. */
50	CPUMMICROARCH enmMicroarch;
51	/** Flags (TBD). */
52	uint32_t fFlags;
53	/** The maximum physical address with of the CPU. This should correspond to
54	* the value in CPUID leaf 0x80000008 when present. */
55	uint8_t cMaxPhysAddrWidth;
56	/** Pointer to an array of CPUID leaves. */
57	PCCPUMCPUIDLEAF paCpuIdLeaves;
58	/** The number of CPUID leaves in the array paCpuIdLeaves points to. */
59	uint32_t cCpuIdLeaves;
60	/** The method used to deal with unknown CPUID leaves. */
61	CPUMUKNOWNCPUID enmUnknownCpuId;
62	/** The default unknown CPUID value. */
63	CPUMCPUID DefUnknownCpuId;
64
65	/** MSR mask. Several microarchitectures ignore higher bits of the */
66	uint32_t fMsrMask;
67
68	/** The number of ranges in the table pointed to b paMsrRanges. */
69	uint32_t cMsrRanges;
70	/** MSR ranges for this CPU. */
71	PCCPUMMSRRANGE paMsrRanges;
72	} CPUMDBENTRY;
73
74
75	/*******************************************************************************
76	* Defined Constants And Macros *
77	*******************************************************************************/
78
79	/** @def NULL_ALONE
80	* For eliminating an unnecessary data dependency in standalone builds (for
81	* VBoxSVC). */
82	/** @def ZERO_ALONE
83	* For eliminating an unnecessary data size dependency in standalone builds (for
84	* VBoxSVC). */
85	#ifndef CPUM_DB_STANDALONE
86	# define NULL_ALONE(a_aTable) a_aTable
87	# define ZERO_ALONE(a_cTable) a_cTable
88	#else
89	# define NULL_ALONE(a_aTable) NULL
90	# define ZERO_ALONE(a_cTable) 0
91	#endif
92
93
94	/** @name Short macros for the MSR range entries.
95	*
96	* These are rather cryptic, but this is to reduce the attack on the right
97	* margin.
98	*
99	* @{ */
100	/** Alias one MSR onto another (a_uTarget). */
101	#define MAL(a_uMsr, a_szName, a_uTarget) \
102	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_MsrAlias, kCpumMsrWrFn_MsrAlias, 0, a_uTarget, 0, 0, a_szName)
103	/** Functions handles everything. */
104	#define MFN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
105	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
106	/** Functions handles everything, with GP mask. */
107	#define MFG(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrGpMask) \
108	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, a_fWrGpMask, a_szName)
109	/** Function handlers, read-only. */
110	#define MFO(a_uMsr, a_szName, a_enmRdFnSuff) \
111	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_ReadOnly, 0, 0, 0, UINT64_MAX, a_szName)
112	/** Function handlers, ignore all writes. */
113	#define MFI(a_uMsr, a_szName, a_enmRdFnSuff) \
114	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_IgnoreWrite, 0, 0, UINT64_MAX, 0, a_szName)
115	/** Function handlers, with value. */
116	#define MFV(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue) \
117	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, 0, 0, a_szName)
118	/** Function handlers, with write ignore mask. */
119	#define MFW(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrIgnMask) \
120	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, a_fWrIgnMask, 0, a_szName)
121	/** Function handlers, extended version. */
122	#define MFX(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
123	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
124	/** Function handlers, with CPUMCPU storage variable. */
125	#define MFS(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember) \
126	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
127	RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, 0, 0, a_szName)
128	/** Function handlers, with CPUMCPU storage variable, ignore mask and GP mask. */
129	#define MFZ(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember, a_fWrIgnMask, a_fWrGpMask) \
130	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
131	RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, a_fWrIgnMask, a_fWrGpMask, a_szName)
132	/** Read-only fixed value. */
133	#define MVO(a_uMsr, a_szName, a_uValue) \
134	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
135	/** Read-only fixed value, ignores all writes. */
136	#define MVI(a_uMsr, a_szName, a_uValue) \
137	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
138	/** Read fixed value, ignore writes outside GP mask. */
139	#define MVG(a_uMsr, a_szName, a_uValue, a_fWrGpMask) \
140	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, 0, a_fWrGpMask, a_szName)
141	/** Read fixed value, extended version with both GP and ignore masks. */
142	#define MVX(a_uMsr, a_szName, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
143	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
144	/** The short form, no CPUM backing. */
145	#define MSN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
146	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
147	a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
148
149	/** Range: Functions handles everything. */
150	#define RFN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
151	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
152	/** Range: Read fixed value, read-only. */
153	#define RVO(a_uFirst, a_uLast, a_szName, a_uValue) \
154	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
155	/** Range: Read fixed value, ignore writes. */
156	#define RVI(a_uFirst, a_uLast, a_szName, a_uValue) \
157	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
158	/** Range: The short form, no CPUM backing. */
159	#define RSN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
160	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
161	a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
162
163	/** Internal form used by the macros. */
164	#ifdef VBOX_WITH_STATISTICS
165	# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
166	{ a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName, \
167	{ 0 }, { 0 }, { 0 }, { 0 } }
168	#else
169	# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
170	{ a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName }
171	#endif
172	/** @} */
173
174
175	#include "cpus/Intel_Core_i7_3960X.h"
176	#include "cpus/Intel_Core_i5_3570.h"
177	#include "cpus/Intel_Xeon_X5482_3_20GHz.h"
178	#include "cpus/Intel_Pentium_M_processor_2_00GHz.h"
179	#include "cpus/Intel_Pentium_4_3_00GHz.h"
180
181	#include "cpus/AMD_FX_8150_Eight_Core.h"
182	#include "cpus/AMD_Phenom_II_X6_1100T.h"
183	#include "cpus/Quad_Core_AMD_Opteron_2384.h"
184	#include "cpus/AMD_Athlon_64_3200.h"
185
186	#include "cpus/VIA_QuadCore_L4700_1_2_GHz.h"
187
188
189
190	/**
191	* The database entries.
192	*
193	* Warning! The first entry is special. It is the fallback for unknown
194	* processors. Thus, it better be pretty representative.
195	*/
196	static CPUMDBENTRY const * const g_apCpumDbEntries[] =
197	{
198	#ifdef VBOX_CPUDB_Intel_Core_i5_3570
199	&g_Entry_Intel_Core_i5_3570,
200	#endif
201	#ifdef VBOX_CPUDB_Intel_Core_i7_3960X
202	&g_Entry_Intel_Core_i7_3960X,
203	#endif
204	#ifdef Intel_Pentium_M_processor_2_00GHz
205	&g_Entry_Intel_Pentium_M_processor_2_00GHz,
206	#endif
207	#ifdef VBOX_CPUDB_Intel_Xeon_X5482_3_20GHz
208	&g_Entry_Intel_Xeon_X5482_3_20GHz,
209	#endif
210	#ifdef VBOX_CPUDB_Intel_Pentium_4_3_00GHz
211	&g_Entry_Intel_Pentium_4_3_00GHz,
212	#endif
213
214	#ifdef VBOX_CPUDB_AMD_FX_8150_Eight_Core
215	&g_Entry_AMD_FX_8150_Eight_Core,
216	#endif
217	#ifdef VBOX_CPUDB_AMD_Phenom_II_X6_1100T
218	&g_Entry_AMD_Phenom_II_X6_1100T,
219	#endif
220	#ifdef VBOX_CPUDB_Quad_Core_AMD_Opteron_2384
221	&g_Entry_Quad_Core_AMD_Opteron_2384,
222	#endif
223	#ifdef VBOX_CPUDB_AMD_Athlon_64_3200
224	&g_Entry_AMD_Athlon_64_3200,
225	#endif
226
227	#ifdef VBOX_CPUDB_VIA_QuadCore_L4700_1_2_GHz
228	&g_Entry_VIA_QuadCore_L4700_1_2_GHz,
229	#endif
230	};
231
232
233	#ifndef CPUM_DB_STANDALONE
234
235	/**
236	* Binary search used by cpumR3MsrRangesInsert and has some special properties
237	* wrt to mismatches.
238	*
239	* @returns Insert location.
240	* @param paMsrRanges The MSR ranges to search.
241	* @param cMsrRanges The number of MSR ranges.
242	* @param uMsr What to search for.
243	*/
244	static uint32_t cpumR3MsrRangesBinSearch(PCCPUMMSRRANGE paMsrRanges, uint32_t cMsrRanges, uint32_t uMsr)
245	{
246	if (!cMsrRanges)
247	return 0;
248
249	uint32_t iStart = 0;
250	uint32_t iLast = cMsrRanges - 1;
251	for (;;)
252	{
253	uint32_t i = iStart + (iLast - iStart + 1) / 2;
254	if ( uMsr >= paMsrRanges[i].uFirst
255	&& uMsr <= paMsrRanges[i].uLast)
256	return i;
257	if (uMsr < paMsrRanges[i].uFirst)
258	{
259	if (i <= iStart)
260	return i;
261	iLast = i - 1;
262	}
263	else
264	{
265	if (i >= iLast)
266	{
267	if (i < cMsrRanges)
268	i++;
269	return i;
270	}
271	iStart = i + 1;
272	}
273	}
274	}
275
276
277	/**
278	* Ensures that there is space for at least @a cNewRanges in the table,
279	* reallocating the table if necessary.
280	*
281	* @returns Pointer to the MSR ranges on success, NULL on failure. On failure
282	* @a *ppaMsrRanges is freed and set to NULL.
283	* @param ppaMsrRanges The variable pointing to the ranges (input/output).
284	* @param cMsrRanges The current number of ranges.
285	* @param cNewRanges The number of ranges to be added.
286	*/
287	static PCPUMMSRRANGE cpumR3MsrRangesEnsureSpace(PCPUMMSRRANGE *ppaMsrRanges, uint32_t cMsrRanges, uint32_t cNewRanges)
288	{
289	uint32_t cMsrRangesAllocated = RT_ALIGN_32(cMsrRanges, 16);
290	if (cMsrRangesAllocated < cMsrRanges + cNewRanges)
291	{
292	uint32_t cNew = RT_ALIGN_32(cMsrRanges + cNewRanges, 16);
293	void pvNew = RTMemRealloc(ppaMsrRanges, cNew * sizeof(**ppaMsrRanges));
294	if (!pvNew)
295	{
296	RTMemFree(*ppaMsrRanges);
297	*ppaMsrRanges = NULL;
298	return NULL;
299	}
300	*ppaMsrRanges = (PCPUMMSRRANGE)pvNew;
301	}
302	return *ppaMsrRanges;
303	}
304
305
306	/**
307	* Inserts a new MSR range in into an sorted MSR range array.
308	*
309	* If the new MSR range overlaps existing ranges, the existing ones will be
310	* adjusted/removed to fit in the new one.
311	*
312	* @returns VBox status code.
313	* @retval VINF_SUCCESS
314	* @retval VERR_NO_MEMORY
315	*
316	* @param ppaMsrRanges The variable pointing to the ranges (input/output).
317	* @param pcMsrRanges The variable holding number of ranges.
318	* @param pNewRange The new range.
319	*/
320	int cpumR3MsrRangesInsert(PCPUMMSRRANGE ppaMsrRanges, uint32_t pcMsrRanges, PCCPUMMSRRANGE pNewRange)
321	{
322	uint32_t cMsrRanges = *pcMsrRanges;
323	PCPUMMSRRANGE paMsrRanges = *ppaMsrRanges;
324
325	Assert(pNewRange->uLast >= pNewRange->uFirst);
326	Assert(pNewRange->enmRdFn > kCpumMsrRdFn_Invalid && pNewRange->enmRdFn < kCpumMsrRdFn_End);
327	Assert(pNewRange->enmWrFn > kCpumMsrWrFn_Invalid && pNewRange->enmWrFn < kCpumMsrWrFn_End);
328
329	/*
330	* Optimize the linear insertion case where we add new entries at the end.
331	*/
332	if ( cMsrRanges > 0
333	&& paMsrRanges[cMsrRanges - 1].uLast < pNewRange->uFirst)
334	{
335	paMsrRanges = cpumR3MsrRangesEnsureSpace(ppaMsrRanges, cMsrRanges, 1);
336	if (!paMsrRanges)
337	return VERR_NO_MEMORY;
338	paMsrRanges[cMsrRanges] = *pNewRange;
339	*pcMsrRanges += 1;
340	}
341	else
342	{
343	uint32_t i = cpumR3MsrRangesBinSearch(paMsrRanges, cMsrRanges, pNewRange->uFirst);
344	Assert(i == cMsrRanges \|\| pNewRange->uFirst <= paMsrRanges[i].uLast);
345	Assert(i == 0 \|\| pNewRange->uFirst > paMsrRanges[i - 1].uLast);
346
347	/*
348	* Adding an entirely new entry?
349	*/
350	if ( i >= cMsrRanges
351	\|\| pNewRange->uLast < paMsrRanges[i].uFirst)
352	{
353	paMsrRanges = cpumR3MsrRangesEnsureSpace(ppaMsrRanges, cMsrRanges, 1);
354	if (!paMsrRanges)
355	return VERR_NO_MEMORY;
356	if (i < cMsrRanges)
357	memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
358	paMsrRanges[i] = *pNewRange;
359	*pcMsrRanges += 1;
360	}
361	/*
362	* Replace existing entry?
363	*/
364	else if ( pNewRange->uFirst == paMsrRanges[i].uFirst
365	&& pNewRange->uLast == paMsrRanges[i].uLast)
366	paMsrRanges[i] = *pNewRange;
367	/*
368	* Splitting an existing entry?
369	*/
370	else if ( pNewRange->uFirst > paMsrRanges[i].uFirst
371	&& pNewRange->uLast < paMsrRanges[i].uLast)
372	{
373	paMsrRanges = cpumR3MsrRangesEnsureSpace(ppaMsrRanges, cMsrRanges, 2);
374	if (!paMsrRanges)
375	return VERR_NO_MEMORY;
376	if (i < cMsrRanges)
377	memmove(&paMsrRanges[i + 2], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
378	paMsrRanges[i + 1] = *pNewRange;
379	paMsrRanges[i + 2] = paMsrRanges[i];
380	paMsrRanges[i ].uLast = pNewRange->uFirst - 1;
381	paMsrRanges[i + 2].uFirst = pNewRange->uLast + 1;
382	*pcMsrRanges += 2;
383	}
384	/*
385	* Complicated scenarios that can affect more than one range.
386	*
387	* The current code does not optimize memmove calls when replacing
388	* one or more existing ranges, because it's tedious to deal with and
389	* not expected to be a frequent usage scenario.
390	*/
391	else
392	{
393	/* Adjust start of first match? */
394	if ( pNewRange->uFirst <= paMsrRanges[i].uFirst
395	&& pNewRange->uLast < paMsrRanges[i].uLast)
396	paMsrRanges[i].uFirst = pNewRange->uLast + 1;
397	else
398	{
399	/* Adjust end of first match? */
400	if (pNewRange->uFirst > paMsrRanges[i].uFirst)
401	{
402	Assert(paMsrRanges[i].uLast >= pNewRange->uFirst);
403	paMsrRanges[i].uLast = pNewRange->uFirst - 1;
404	i++;
405	}
406	/* Replace the whole first match (lazy bird). */
407	else
408	{
409	if (i + 1 < cMsrRanges)
410	memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
411	cMsrRanges = *pcMsrRanges -= 1;
412	}
413
414	/* Do the new range affect more ranges? */
415	while ( i < cMsrRanges
416	&& pNewRange->uLast >= paMsrRanges[i].uFirst)
417	{
418	if (pNewRange->uLast < paMsrRanges[i].uLast)
419	{
420	/* Adjust the start of it, then we're done. */
421	paMsrRanges[i].uFirst = pNewRange->uLast + 1;
422	break;
423	}
424
425	/* Remove it entirely. */
426	if (i + 1 < cMsrRanges)
427	memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
428	cMsrRanges = *pcMsrRanges -= 1;
429	}
430	}
431
432	/* Now, perform a normal insertion. */
433	paMsrRanges = cpumR3MsrRangesEnsureSpace(ppaMsrRanges, cMsrRanges, 1);
434	if (!paMsrRanges)
435	return VERR_NO_MEMORY;
436	if (i < cMsrRanges)
437	memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
438	paMsrRanges[i] = *pNewRange;
439	*pcMsrRanges += 1;
440	}
441	}
442
443	return VINF_SUCCESS;
444	}
445
446
447	/**
448	* Worker for cpumR3MsrApplyFudge that applies one table.
449	*
450	* @returns VBox status code.
451	* @param pVM Pointer to the cross context VM structure.
452	* @param paRanges Array of MSRs to fudge.
453	* @param cRanges Number of MSRs in the array.
454	*/
455	static int cpumR3MsrApplyFudgeTable(PVM pVM, PCCPUMMSRRANGE paRanges, size_t cRanges)
456	{
457	for (uint32_t i = 0; i < cRanges; i++)
458	if (!cpumLookupMsrRange(pVM, paRanges[i].uFirst))
459	{
460	LogRel(("CPUM: MSR fudge: %#010x %s\n", paRanges[i].uFirst, paRanges[i].szName));
461	int rc = cpumR3MsrRangesInsert(&pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
462	&paRanges[i]);
463	if (RT_FAILURE(rc))
464	return rc;
465	}
466	return VINF_SUCCESS;
467	}
468
469
470	/**
471	* Fudges the MSRs that guest are known to access in some odd cases.
472	*
473	* A typical example is a VM that has been moved between different hosts where
474	* for instance the cpu vendor differs.
475	*
476	* @returns VBox status code.
477	* @param pVM Pointer to the cross context VM structure.
478	*/
479	int cpumR3MsrApplyFudge(PVM pVM)
480	{
481	/*
482	* Basic.
483	*/
484	static CPUMMSRRANGE const s_aFudgeMsrs[] =
485	{
486	MFO(0x00000000, "IA32_P5_MC_ADDR", Ia32P5McAddr),
487	MFX(0x00000001, "IA32_P5_MC_TYPE", Ia32P5McType, Ia32P5McType, 0, 0, UINT64_MAX),
488	MVO(0x00000017, "IA32_PLATFORM_ID", 0),
489	MFN(0x0000001b, "IA32_APIC_BASE", Ia32ApicBase, Ia32ApicBase),
490	MVI(0x0000008b, "BIOS_SIGN", 0),
491	MFX(0x000000fe, "IA32_MTRRCAP", Ia32MtrrCap, ReadOnly, 0x508, 0, 0),
492	MFX(0x00000179, "IA32_MCG_CAP", Ia32McgCap, ReadOnly, 0x005, 0, 0),
493	MFX(0x0000017a, "IA32_MCG_STATUS", Ia32McgStatus, Ia32McgStatus, 0, ~(uint64_t)UINT32_MAX, 0),
494	MFN(0x000001a0, "IA32_MISC_ENABLE", Ia32MiscEnable, Ia32MiscEnable),
495	MFN(0x000001d9, "IA32_DEBUGCTL", Ia32DebugCtl, Ia32DebugCtl),
496	MFO(0x000001db, "P6_LAST_BRANCH_FROM_IP", P6LastBranchFromIp),
497	MFO(0x000001dc, "P6_LAST_BRANCH_TO_IP", P6LastBranchToIp),
498	MFO(0x000001dd, "P6_LAST_INT_FROM_IP", P6LastIntFromIp),
499	MFO(0x000001de, "P6_LAST_INT_TO_IP", P6LastIntToIp),
500	MFS(0x00000277, "IA32_PAT", Ia32Pat, Ia32Pat, Guest.msrPAT),
501	MFZ(0x000002ff, "IA32_MTRR_DEF_TYPE", Ia32MtrrDefType, Ia32MtrrDefType, GuestMsrs.msr.MtrrDefType, 0, ~(uint64_t)0xc07),
502	MFN(0x00000400, "IA32_MCi_CTL_STATUS_ADDR_MISC", Ia32McCtlStatusAddrMiscN, Ia32McCtlStatusAddrMiscN),
503	};
504	int rc = cpumR3MsrApplyFudgeTable(pVM, &s_aFudgeMsrs[0], RT_ELEMENTS(s_aFudgeMsrs));
505	AssertLogRelRCReturn(rc, rc);
506
507	/*
508	* XP might mistake opterons and other newer CPUs for P4s.
509	*/
510	if (pVM->cpum.s.GuestFeatures.uFamily >= 0xf)
511	{
512	static CPUMMSRRANGE const s_aP4FudgeMsrs[] =
513	{
514	MFX(0x0000002c, "P4_EBC_FREQUENCY_ID", IntelP4EbcFrequencyId, IntelP4EbcFrequencyId, 0xf12010f, UINT64_MAX, 0),
515	};
516	rc = cpumR3MsrApplyFudgeTable(pVM, &s_aP4FudgeMsrs[0], RT_ELEMENTS(s_aP4FudgeMsrs));
517	AssertLogRelRCReturn(rc, rc);
518	}
519
520	return rc;
521	}
522
523
524	int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo)
525	{
526	CPUMDBENTRY const *pEntry = NULL;
527	int rc;
528
529	if (!strcmp(pszName, "host"))
530	{
531	/*
532	* Create a CPU database entry for the host CPU. This means getting
533	* the CPUID bits from the real CPU and grabbing the closest matching
534	* database entry for MSRs.
535	*/
536	rc = CPUMR3CpuIdDetectUnknownLeafMethod(&pInfo->enmUnknownCpuIdMethod, &pInfo->DefCpuId);
537	if (RT_FAILURE(rc))
538	return rc;
539	rc = CPUMR3CpuIdCollectLeaves(&pInfo->paCpuIdLeavesR3, &pInfo->cCpuIdLeaves);
540	if (RT_FAILURE(rc))
541	return rc;
542
543	/* Lookup database entry for MSRs. */
544	CPUMCPUVENDOR const enmVendor = CPUMR3CpuIdDetectVendorEx(pInfo->paCpuIdLeavesR3[0].uEax,
545	pInfo->paCpuIdLeavesR3[0].uEbx,
546	pInfo->paCpuIdLeavesR3[0].uEcx,
547	pInfo->paCpuIdLeavesR3[0].uEdx);
548	uint32_t const uStd1Eax = pInfo->paCpuIdLeavesR3[1].uEax;
549	uint8_t const uFamily = ASMGetCpuFamily(uStd1Eax);
550	uint8_t const uModel = ASMGetCpuModel(uStd1Eax, enmVendor == CPUMCPUVENDOR_INTEL);
551	uint8_t const uStepping = ASMGetCpuStepping(uStd1Eax);
552	CPUMMICROARCH const enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx(enmVendor, uFamily, uModel, uStepping);
553
554	for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
555	{
556	CPUMDBENTRY const *pCur = g_apCpumDbEntries[i];
557	if ((CPUMCPUVENDOR)pCur->enmVendor == enmVendor)
558	{
559	/* Anything from the same vendor is better than nothing: */
560	if (!pEntry)
561	pEntry = pCur;
562	/* Newer micro arch is better than an older one: */
563	else if ( pEntry->enmMicroarch < enmMicroarch
564	&& pCur->enmMicroarch >= enmMicroarch)
565	pEntry = pCur;
566	/* Prefer a micro arch match: */
567	else if ( pEntry->enmMicroarch != enmMicroarch
568	&& pCur->enmMicroarch == enmMicroarch)
569	pEntry = pCur;
570	/* If the micro arch matches, check model and stepping. Stop
571	looping if we get an exact match. */
572	else if ( pEntry->enmMicroarch == enmMicroarch
573	&& pCur->enmMicroarch == enmMicroarch)
574	{
575	if (pCur->uModel == uModel)
576	{
577	/* Perfect match? */
578	if (pCur->uStepping == uStepping)
579	{
580	pEntry = pCur;
581	break;
582	}
583
584	/* Better model match? */
585	if (pEntry->uModel != uModel)
586	pEntry = pCur;
587	/* The one with the closest stepping, prefering ones over earlier ones. */
588	else if ( pCur->uStepping > uStepping
589	? pCur->uStepping < pEntry->uStepping \|\| pEntry->uStepping < uStepping
590	: pCur->uStepping > pEntry->uStepping)
591	pEntry = pCur;
592	}
593	/* The one with the closest model, prefering later ones over earlier ones. */
594	else if ( pCur->uModel > uModel
595	? pCur->uModel < pEntry->uModel \|\| pEntry->uModel < uModel
596	: pCur->uModel > pEntry->uModel)
597	pEntry = pCur;
598	}
599	}
600	}
601
602	if (pEntry)
603	LogRel(("CPUM: Matched host CPU %s %#x/%#x/%#x %s with CPU DB entry '%s' (%s %#x/%#x/%#x %s).\n",
604	CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
605	pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor), pEntry->uFamily, pEntry->uModel,
606	pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
607	else
608	{
609	pEntry = g_apCpumDbEntries[0];
610	LogRel(("CPUM: No matching processor database entry %s %#x/%#x/%#x %s, falling back on '%s'.\n",
611	CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
612	pEntry->pszName));
613	}
614	}
615	else
616	{
617	/*
618	* We're supposed to be emulating a specific CPU that is included in
619	* our CPU database. The CPUID tables needs to be copied onto the
620	* heap so the caller can modify them and so they can be freed like
621	* in the host case above.
622	*/
623	for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
624	if (!strcmp(pszName, g_apCpumDbEntries[i]->pszName))
625	{
626	pEntry = g_apCpumDbEntries[i];
627	break;
628	}
629	if (!pEntry)
630	{
631	LogRel(("CPUM: Cannot locate any CPU by the name '%s'\n", pszName));
632	return VERR_CPUM_DB_CPU_NOT_FOUND;
633	}
634
635	pInfo->cCpuIdLeaves = pEntry->cCpuIdLeaves;
636	if (pEntry->cCpuIdLeaves)
637	{
638	pInfo->paCpuIdLeavesR3 = (PCPUMCPUIDLEAF)RTMemDup(pEntry->paCpuIdLeaves,
639	sizeof(pEntry->paCpuIdLeaves[0]) * pEntry->cCpuIdLeaves);
640	if (!pInfo->paCpuIdLeavesR3)
641	return VERR_NO_MEMORY;
642	}
643	else
644	pInfo->paCpuIdLeavesR3 = NULL;
645
646	pInfo->enmUnknownCpuIdMethod = pEntry->enmUnknownCpuId;
647	pInfo->DefCpuId = pEntry->DefUnknownCpuId;
648
649	LogRel(("CPUM: Using CPU DB entry '%s' (%s %#x/%#x/%#x %s).\n",
650	pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor),
651	pEntry->uFamily, pEntry->uModel, pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
652	}
653
654	pInfo->fMsrMask = pEntry->fMsrMask;
655	pInfo->iFirstExtCpuIdLeaf = 0; /* Set by caller. */
656	pInfo->uPadding = 0;
657	pInfo->paCpuIdLeavesR0 = NIL_RTR0PTR;
658	pInfo->paMsrRangesR0 = NIL_RTR0PTR;
659	pInfo->paCpuIdLeavesRC = NIL_RTRCPTR;
660	pInfo->paMsrRangesRC = NIL_RTRCPTR;
661
662	/*
663	* Copy the MSR range.
664	*/
665	uint32_t cMsrs = 0;
666	PCPUMMSRRANGE paMsrs = NULL;
667
668	PCCPUMMSRRANGE pCurMsr = pEntry->paMsrRanges;
669	uint32_t cLeft = pEntry->cMsrRanges;
670	while (cLeft-- > 0)
671	{
672	rc = cpumR3MsrRangesInsert(&paMsrs, &cMsrs, pCurMsr);
673	if (RT_FAILURE(rc))
674	{
675	Assert(!paMsrs); /* The above function frees this. */
676	RTMemFree(pInfo->paCpuIdLeavesR3);
677	pInfo->paCpuIdLeavesR3 = NULL;
678	return rc;
679	}
680	pCurMsr++;
681	}
682
683	pInfo->paMsrRangesR3 = paMsrs;
684	pInfo->cMsrRanges = cMsrs;
685	return VINF_SUCCESS;
686	}
687
688
689	/**
690	* Register statistics for the MSRs.
691	*
692	* This must not be called before the MSRs have been finalized and moved to the
693	* hyper heap.
694	*
695	* @returns VBox status code.
696	* @param pVM Pointer to the cross context VM structure.
697	*/
698	int cpumR3MsrRegStats(PVM pVM)
699	{
700	/*
701	* Global statistics.
702	*/
703	PCPUM pCpum = &pVM->cpum.s;
704	STAM_REL_REG(pVM, &pCpum->cMsrReads, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Reads",
705	STAMUNIT_OCCURENCES, "All RDMSRs making it to CPUM.");
706	STAM_REL_REG(pVM, &pCpum->cMsrReadsRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsRaisingGP",
707	STAMUNIT_OCCURENCES, "RDMSR raising #GPs, except unknown MSRs.");
708	STAM_REL_REG(pVM, &pCpum->cMsrReadsUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsUnknown",
709	STAMUNIT_OCCURENCES, "RDMSR on unknown MSRs (raises #GP).");
710	STAM_REL_REG(pVM, &pCpum->cMsrWrites, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Writes",
711	STAMUNIT_OCCURENCES, "All RDMSRs making it to CPUM.");
712	STAM_REL_REG(pVM, &pCpum->cMsrWritesRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesRaisingGP",
713	STAMUNIT_OCCURENCES, "WRMSR raising #GPs, except unknown MSRs.");
714	STAM_REL_REG(pVM, &pCpum->cMsrWritesToIgnoredBits, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesToIgnoredBits",
715	STAMUNIT_OCCURENCES, "Writing of ignored bits.");
716	STAM_REL_REG(pVM, &pCpum->cMsrWritesUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesUnknown",
717	STAMUNIT_OCCURENCES, "WRMSR on unknown MSRs (raises #GP).");
718
719
720	# ifdef VBOX_WITH_STATISTICS
721	/*
722	* Per range.
723	*/
724	PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.paMsrRangesR3;
725	uint32_t cRanges = pVM->cpum.s.GuestInfo.cMsrRanges;
726	for (uint32_t i = 0; i < cRanges; i++)
727	{
728	char szName[160];
729	ssize_t cchName;
730
731	if (paRanges[i].uFirst == paRanges[i].uLast)
732	cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%s",
733	paRanges[i].uFirst, paRanges[i].szName);
734	else
735	cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%#010x-%s",
736	paRanges[i].uFirst, paRanges[i].uLast, paRanges[i].szName);
737
738	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-reads");
739	STAMR3Register(pVM, &paRanges[i].cReads, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, szName, STAMUNIT_OCCURENCES, "RDMSR");
740
741	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-writes");
742	STAMR3Register(pVM, &paRanges[i].cWrites, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR");
743
744	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-GPs");
745	STAMR3Register(pVM, &paRanges[i].cGps, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "#GPs");
746
747	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-ign-bits-writes");
748	STAMR3Register(pVM, &paRanges[i].cIgnoredBits, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR w/ ignored bits");
749	}
750	# endif /* VBOX_WITH_STATISTICS */
751
752	return VINF_SUCCESS;
753	}
754
755	#endif /* !CPUM_DB_STANDALONE */
756

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3Db.cpp@ 49993

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