CPUM.cpp@ 94931

最後變更在這個檔案從94931是 94931,由 vboxsync 提交於 3 年前
VMM/CPUM: Introduced a global variable g_CpumHostFeatures for keeping the host CPU features. This is safer than keeping this info in the shared part of the VM structure. bugref:10093
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1	/* $Id: CPUM.cpp 94931 2022-05-09 08:24:47Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2022 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.alldomusa.eu.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_cpum CPUM - CPU Monitor / Manager
19	*
20	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
21	* also responsible for lazy FPU handling and some of the context loading
22	* in raw mode.
23	*
24	* There are three CPU contexts, the most important one is the guest one (GC).
25	* When running in raw-mode (RC) there is a special hyper context for the VMM
26	* part that floats around inside the guest address space. When running in
27	* raw-mode, CPUM also maintains a host context for saving and restoring
28	* registers across world switches. This latter is done in cooperation with the
29	* world switcher (@see pg_vmm).
30	*
31	* @see grp_cpum
32	*
33	* @section sec_cpum_fpu FPU / SSE / AVX / ++ state.
34	*
35	* TODO: proper write up, currently just some notes.
36	*
37	* The ring-0 FPU handling per OS:
38	*
39	* - 64-bit Windows uses XMM registers in the kernel as part of the calling
40	* convention (Visual C++ doesn't seem to have a way to disable
41	* generating such code either), so CR0.TS/EM are always zero from what I
42	* can tell. We are also forced to always load/save the guest XMM0-XMM15
43	* registers when entering/leaving guest context. Interrupt handlers
44	* using FPU/SSE will offically have call save and restore functions
45	* exported by the kernel, if the really really have to use the state.
46	*
47	* - 32-bit windows does lazy FPU handling, I think, probably including
48	* lazying saving. The Windows Internals book states that it's a bad
49	* idea to use the FPU in kernel space. However, it looks like it will
50	* restore the FPU state of the current thread in case of a kernel \#NM.
51	* Interrupt handlers should be same as for 64-bit.
52	*
53	* - Darwin allows taking \#NM in kernel space, restoring current thread's
54	* state if I read the code correctly. It saves the FPU state of the
55	* outgoing thread, and uses CR0.TS to lazily load the state of the
56	* incoming one. No idea yet how the FPU is treated by interrupt
57	* handlers, i.e. whether they are allowed to disable the state or
58	* something.
59	*
60	* - Linux also allows \#NM in kernel space (don't know since when), and
61	* uses CR0.TS for lazy loading. Saves outgoing thread's state, lazy
62	* loads the incoming unless configured to agressivly load it. Interrupt
63	* handlers can ask whether they're allowed to use the FPU, and may
64	* freely trash the state if Linux thinks it has saved the thread's state
65	* already. This is a problem.
66	*
67	* - Solaris will, from what I can tell, panic if it gets an \#NM in kernel
68	* context. When switching threads, the kernel will save the state of
69	* the outgoing thread and lazy load the incoming one using CR0.TS.
70	* There are a few routines in seeblk.s which uses the SSE unit in ring-0
71	* to do stuff, HAT are among the users. The routines there will
72	* manually clear CR0.TS and save the XMM registers they use only if
73	* CR0.TS was zero upon entry. They will skip it when not, because as
74	* mentioned above, the FPU state is saved when switching away from a
75	* thread and CR0.TS set to 1, so when CR0.TS is 1 there is nothing to
76	* preserve. This is a problem if we restore CR0.TS to 1 after loading
77	* the guest state.
78	*
79	* - FreeBSD - no idea yet.
80	*
81	* - OS/2 does not allow \#NMs in kernel space IIRC. Does lazy loading,
82	* possibly also lazy saving. Interrupts must preserve the CR0.TS+EM &
83	* FPU states.
84	*
85	* Up to r107425 (2016-05-24) we would only temporarily modify CR0.TS/EM while
86	* saving and restoring the host and guest states. The motivation for this
87	* change is that we want to be able to emulate SSE instruction in ring-0 (IEM).
88	*
89	* Starting with that change, we will leave CR0.TS=EM=0 after saving the host
90	* state and only restore it once we've restore the host FPU state. This has the
91	* accidental side effect of triggering Solaris to preserve XMM registers in
92	* sseblk.s. When CR0 was changed by saving the FPU state, CPUM must now inform
93	* the VT-x (HMVMX) code about it as it caches the CR0 value in the VMCS.
94	*
95	*
96	* @section sec_cpum_logging Logging Level Assignments.
97	*
98	* Following log level assignments:
99	* - Log6 is used for FPU state management.
100	* - Log7 is used for FPU state actualization.
101	*
102	*/
103
104
105	/*********************************************************************************************************************************
106	* Header Files *
107	*********************************************************************************************************************************/
108	#define LOG_GROUP LOG_GROUP_CPUM
109	#define CPUM_WITH_NONCONST_HOST_FEATURES
110	#include <VBox/vmm/cpum.h>
111	#include <VBox/vmm/cpumdis.h>
112	#include <VBox/vmm/cpumctx-v1_6.h>
113	#include <VBox/vmm/pgm.h>
114	#include <VBox/vmm/apic.h>
115	#include <VBox/vmm/mm.h>
116	#include <VBox/vmm/em.h>
117	#include <VBox/vmm/iem.h>
118	#include <VBox/vmm/selm.h>
119	#include <VBox/vmm/dbgf.h>
120	#include <VBox/vmm/hm.h>
121	#include <VBox/vmm/hmvmxinline.h>
122	#include <VBox/vmm/ssm.h>
123	#include "CPUMInternal.h"
124	#include <VBox/vmm/vm.h>
125
126	#include <VBox/param.h>
127	#include <VBox/dis.h>
128	#include <VBox/err.h>
129	#include <VBox/log.h>
130	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
131	# include <iprt/asm-amd64-x86.h>
132	#endif
133	#include <iprt/assert.h>
134	#include <iprt/cpuset.h>
135	#include <iprt/mem.h>
136	#include <iprt/mp.h>
137	#include <iprt/string.h>
138
139
140	/*********************************************************************************************************************************
141	* Defined Constants And Macros *
142	*********************************************************************************************************************************/
143	/**
144	* This was used in the saved state up to the early life of version 14.
145	*
146	* It indicates that we may have some out-of-sync hidden segement registers.
147	* It is only relevant for raw-mode.
148	*/
149	#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
150
151
152	/*********************************************************************************************************************************
153	* Structures and Typedefs *
154	*********************************************************************************************************************************/
155
156	/**
157	* What kind of cpu info dump to perform.
158	*/
159	typedef enum CPUMDUMPTYPE
160	{
161	CPUMDUMPTYPE_TERSE,
162	CPUMDUMPTYPE_DEFAULT,
163	CPUMDUMPTYPE_VERBOSE
164	} CPUMDUMPTYPE;
165	/** Pointer to a cpu info dump type. */
166	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
167
168
169	/*********************************************************************************************************************************
170	* Internal Functions *
171	*********************************************************************************************************************************/
172	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
173	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
174	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
175	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
176	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
177	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
178	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
179	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
180	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
181	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
182	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
183
184
185	/*********************************************************************************************************************************
186	* Global Variables *
187	*********************************************************************************************************************************/
188	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
189	/** Host CPU features. */
190	DECL_HIDDEN_DATA(CPUHOSTFEATURES) g_CpumHostFeatures;
191	#endif
192
193	/** Saved state field descriptors for CPUMCTX. */
194	static const SSMFIELD g_aCpumCtxFields[] =
195	{
196	SSMFIELD_ENTRY( CPUMCTX, rdi),
197	SSMFIELD_ENTRY( CPUMCTX, rsi),
198	SSMFIELD_ENTRY( CPUMCTX, rbp),
199	SSMFIELD_ENTRY( CPUMCTX, rax),
200	SSMFIELD_ENTRY( CPUMCTX, rbx),
201	SSMFIELD_ENTRY( CPUMCTX, rdx),
202	SSMFIELD_ENTRY( CPUMCTX, rcx),
203	SSMFIELD_ENTRY( CPUMCTX, rsp),
204	SSMFIELD_ENTRY( CPUMCTX, rflags),
205	SSMFIELD_ENTRY( CPUMCTX, rip),
206	SSMFIELD_ENTRY( CPUMCTX, r8),
207	SSMFIELD_ENTRY( CPUMCTX, r9),
208	SSMFIELD_ENTRY( CPUMCTX, r10),
209	SSMFIELD_ENTRY( CPUMCTX, r11),
210	SSMFIELD_ENTRY( CPUMCTX, r12),
211	SSMFIELD_ENTRY( CPUMCTX, r13),
212	SSMFIELD_ENTRY( CPUMCTX, r14),
213	SSMFIELD_ENTRY( CPUMCTX, r15),
214	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
215	SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
216	SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
217	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
218	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
219	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
220	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
221	SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
222	SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
223	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
224	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
225	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
226	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
227	SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
228	SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
229	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
230	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
231	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
232	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
233	SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
234	SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
235	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
236	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
237	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
238	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
239	SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
240	SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
241	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
242	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
243	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
244	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
245	SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
246	SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
247	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
248	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
249	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
250	SSMFIELD_ENTRY( CPUMCTX, cr0),
251	SSMFIELD_ENTRY( CPUMCTX, cr2),
252	SSMFIELD_ENTRY( CPUMCTX, cr3),
253	SSMFIELD_ENTRY( CPUMCTX, cr4),
254	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
255	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
256	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
257	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
258	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
259	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
260	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
261	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
262	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
263	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
264	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
265	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
266	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
267	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
268	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
269	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
270	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
271	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
272	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
273	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
274	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
275	SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
276	SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
277	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
278	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
279	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
280	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
281	SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
282	SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
283	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
284	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
285	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
286	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[0], CPUM_SAVED_STATE_VERSION_XSAVE),
287	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[1], CPUM_SAVED_STATE_VERSION_XSAVE),
288	SSMFIELD_ENTRY_VER( CPUMCTX, fXStateMask, CPUM_SAVED_STATE_VERSION_XSAVE),
289	SSMFIELD_ENTRY_TERM()
290	};
291
292	/** Saved state field descriptors for SVM nested hardware-virtualization
293	* Host State. */
294	static const SSMFIELD g_aSvmHwvirtHostState[] =
295	{
296	SSMFIELD_ENTRY( SVMHOSTSTATE, uEferMsr),
297	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr0),
298	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr4),
299	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr3),
300	SSMFIELD_ENTRY( SVMHOSTSTATE, uRip),
301	SSMFIELD_ENTRY( SVMHOSTSTATE, uRsp),
302	SSMFIELD_ENTRY( SVMHOSTSTATE, uRax),
303	SSMFIELD_ENTRY( SVMHOSTSTATE, rflags),
304	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Sel),
305	SSMFIELD_ENTRY( SVMHOSTSTATE, es.ValidSel),
306	SSMFIELD_ENTRY( SVMHOSTSTATE, es.fFlags),
307	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u64Base),
308	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u32Limit),
309	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Attr),
310	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Sel),
311	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.ValidSel),
312	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.fFlags),
313	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u64Base),
314	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u32Limit),
315	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Attr),
316	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Sel),
317	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.ValidSel),
318	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.fFlags),
319	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u64Base),
320	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u32Limit),
321	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Attr),
322	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Sel),
323	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.ValidSel),
324	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.fFlags),
325	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u64Base),
326	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u32Limit),
327	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Attr),
328	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.cbGdt),
329	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.pGdt),
330	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.cbIdt),
331	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.pIdt),
332	SSMFIELD_ENTRY_IGNORE(SVMHOSTSTATE, abPadding),
333	SSMFIELD_ENTRY_TERM()
334	};
335
336	/** Saved state field descriptors for VMX nested hardware-virtualization
337	* VMCS. */
338	static const SSMFIELD g_aVmxHwvirtVmcs[] =
339	{
340	SSMFIELD_ENTRY( VMXVVMCS, u32VmcsRevId),
341	SSMFIELD_ENTRY( VMXVVMCS, enmVmxAbort),
342	SSMFIELD_ENTRY( VMXVVMCS, fVmcsState),
343	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au8Padding0),
344	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved0),
345
346	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, u16Reserved0),
347
348	SSMFIELD_ENTRY( VMXVVMCS, u32RoVmInstrError),
349	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitReason),
350	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitIntInfo),
351	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitIntErrCode),
352	SSMFIELD_ENTRY( VMXVVMCS, u32RoIdtVectoringInfo),
353	SSMFIELD_ENTRY( VMXVVMCS, u32RoIdtVectoringErrCode),
354	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitInstrLen),
355	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitInstrInfo),
356	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32RoReserved2),
357
358	SSMFIELD_ENTRY( VMXVVMCS, u64RoGuestPhysAddr),
359	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved1),
360
361	SSMFIELD_ENTRY( VMXVVMCS, u64RoExitQual),
362	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRcx),
363	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRsi),
364	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRdi),
365	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRip),
366	SSMFIELD_ENTRY( VMXVVMCS, u64RoGuestLinearAddr),
367	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved5),
368
369	SSMFIELD_ENTRY( VMXVVMCS, u16Vpid),
370	SSMFIELD_ENTRY( VMXVVMCS, u16PostIntNotifyVector),
371	SSMFIELD_ENTRY( VMXVVMCS, u16EptpIndex),
372	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved0),
373
374	SSMFIELD_ENTRY( VMXVVMCS, u32PinCtls),
375	SSMFIELD_ENTRY( VMXVVMCS, u32ProcCtls),
376	SSMFIELD_ENTRY( VMXVVMCS, u32XcptBitmap),
377	SSMFIELD_ENTRY( VMXVVMCS, u32XcptPFMask),
378	SSMFIELD_ENTRY( VMXVVMCS, u32XcptPFMatch),
379	SSMFIELD_ENTRY( VMXVVMCS, u32Cr3TargetCount),
380	SSMFIELD_ENTRY( VMXVVMCS, u32ExitCtls),
381	SSMFIELD_ENTRY( VMXVVMCS, u32ExitMsrStoreCount),
382	SSMFIELD_ENTRY( VMXVVMCS, u32ExitMsrLoadCount),
383	SSMFIELD_ENTRY( VMXVVMCS, u32EntryCtls),
384	SSMFIELD_ENTRY( VMXVVMCS, u32EntryMsrLoadCount),
385	SSMFIELD_ENTRY( VMXVVMCS, u32EntryIntInfo),
386	SSMFIELD_ENTRY( VMXVVMCS, u32EntryXcptErrCode),
387	SSMFIELD_ENTRY( VMXVVMCS, u32EntryInstrLen),
388	SSMFIELD_ENTRY( VMXVVMCS, u32TprThreshold),
389	SSMFIELD_ENTRY( VMXVVMCS, u32ProcCtls2),
390	SSMFIELD_ENTRY( VMXVVMCS, u32PleGap),
391	SSMFIELD_ENTRY( VMXVVMCS, u32PleWindow),
392	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved1),
393
394	SSMFIELD_ENTRY( VMXVVMCS, u64AddrIoBitmapA),
395	SSMFIELD_ENTRY( VMXVVMCS, u64AddrIoBitmapB),
396	SSMFIELD_ENTRY( VMXVVMCS, u64AddrMsrBitmap),
397	SSMFIELD_ENTRY( VMXVVMCS, u64AddrExitMsrStore),
398	SSMFIELD_ENTRY( VMXVVMCS, u64AddrExitMsrLoad),
399	SSMFIELD_ENTRY( VMXVVMCS, u64AddrEntryMsrLoad),
400	SSMFIELD_ENTRY( VMXVVMCS, u64ExecVmcsPtr),
401	SSMFIELD_ENTRY( VMXVVMCS, u64AddrPml),
402	SSMFIELD_ENTRY( VMXVVMCS, u64TscOffset),
403	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVirtApic),
404	SSMFIELD_ENTRY( VMXVVMCS, u64AddrApicAccess),
405	SSMFIELD_ENTRY( VMXVVMCS, u64AddrPostedIntDesc),
406	SSMFIELD_ENTRY( VMXVVMCS, u64VmFuncCtls),
407	SSMFIELD_ENTRY( VMXVVMCS, u64EptPtr),
408	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap0),
409	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap1),
410	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap2),
411	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap3),
412	SSMFIELD_ENTRY( VMXVVMCS, u64AddrEptpList),
413	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVmreadBitmap),
414	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVmwriteBitmap),
415	SSMFIELD_ENTRY( VMXVVMCS, u64AddrXcptVeInfo),
416	SSMFIELD_ENTRY( VMXVVMCS, u64XssExitBitmap),
417	SSMFIELD_ENTRY( VMXVVMCS, u64EnclsExitBitmap),
418	SSMFIELD_ENTRY( VMXVVMCS, u64SppTablePtr),
419	SSMFIELD_ENTRY( VMXVVMCS, u64TscMultiplier),
420	SSMFIELD_ENTRY_VER( VMXVVMCS, u64ProcCtls3, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
421	SSMFIELD_ENTRY_VER( VMXVVMCS, u64EnclvExitBitmap, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
422	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved0),
423
424	SSMFIELD_ENTRY( VMXVVMCS, u64Cr0Mask),
425	SSMFIELD_ENTRY( VMXVVMCS, u64Cr4Mask),
426	SSMFIELD_ENTRY( VMXVVMCS, u64Cr0ReadShadow),
427	SSMFIELD_ENTRY( VMXVVMCS, u64Cr4ReadShadow),
428	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target0),
429	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target1),
430	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target2),
431	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target3),
432	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved4),
433
434	SSMFIELD_ENTRY( VMXVVMCS, HostEs),
435	SSMFIELD_ENTRY( VMXVVMCS, HostCs),
436	SSMFIELD_ENTRY( VMXVVMCS, HostSs),
437	SSMFIELD_ENTRY( VMXVVMCS, HostDs),
438	SSMFIELD_ENTRY( VMXVVMCS, HostFs),
439	SSMFIELD_ENTRY( VMXVVMCS, HostGs),
440	SSMFIELD_ENTRY( VMXVVMCS, HostTr),
441	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved2),
442
443	SSMFIELD_ENTRY( VMXVVMCS, u32HostSysenterCs),
444	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved4),
445
446	SSMFIELD_ENTRY( VMXVVMCS, u64HostPatMsr),
447	SSMFIELD_ENTRY( VMXVVMCS, u64HostEferMsr),
448	SSMFIELD_ENTRY( VMXVVMCS, u64HostPerfGlobalCtlMsr),
449	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostPkrsMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
450	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved3),
451
452	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr0),
453	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr3),
454	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr4),
455	SSMFIELD_ENTRY( VMXVVMCS, u64HostFsBase),
456	SSMFIELD_ENTRY( VMXVVMCS, u64HostGsBase),
457	SSMFIELD_ENTRY( VMXVVMCS, u64HostTrBase),
458	SSMFIELD_ENTRY( VMXVVMCS, u64HostGdtrBase),
459	SSMFIELD_ENTRY( VMXVVMCS, u64HostIdtrBase),
460	SSMFIELD_ENTRY( VMXVVMCS, u64HostSysenterEsp),
461	SSMFIELD_ENTRY( VMXVVMCS, u64HostSysenterEip),
462	SSMFIELD_ENTRY( VMXVVMCS, u64HostRsp),
463	SSMFIELD_ENTRY( VMXVVMCS, u64HostRip),
464	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostSCetMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
465	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostSsp, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
466	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostIntrSspTableAddrMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
467	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved7),
468
469	SSMFIELD_ENTRY( VMXVVMCS, GuestEs),
470	SSMFIELD_ENTRY( VMXVVMCS, GuestCs),
471	SSMFIELD_ENTRY( VMXVVMCS, GuestSs),
472	SSMFIELD_ENTRY( VMXVVMCS, GuestDs),
473	SSMFIELD_ENTRY( VMXVVMCS, GuestFs),
474	SSMFIELD_ENTRY( VMXVVMCS, GuestGs),
475	SSMFIELD_ENTRY( VMXVVMCS, GuestLdtr),
476	SSMFIELD_ENTRY( VMXVVMCS, GuestTr),
477	SSMFIELD_ENTRY( VMXVVMCS, u16GuestIntStatus),
478	SSMFIELD_ENTRY( VMXVVMCS, u16PmlIndex),
479	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved1),
480
481	SSMFIELD_ENTRY( VMXVVMCS, u32GuestEsLimit),
482	SSMFIELD_ENTRY( VMXVVMCS, u32GuestCsLimit),
483	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSsLimit),
484	SSMFIELD_ENTRY( VMXVVMCS, u32GuestDsLimit),
485	SSMFIELD_ENTRY( VMXVVMCS, u32GuestFsLimit),
486	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGsLimit),
487	SSMFIELD_ENTRY( VMXVVMCS, u32GuestLdtrLimit),
488	SSMFIELD_ENTRY( VMXVVMCS, u32GuestTrLimit),
489	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGdtrLimit),
490	SSMFIELD_ENTRY( VMXVVMCS, u32GuestIdtrLimit),
491	SSMFIELD_ENTRY( VMXVVMCS, u32GuestEsAttr),
492	SSMFIELD_ENTRY( VMXVVMCS, u32GuestCsAttr),
493	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSsAttr),
494	SSMFIELD_ENTRY( VMXVVMCS, u32GuestDsAttr),
495	SSMFIELD_ENTRY( VMXVVMCS, u32GuestFsAttr),
496	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGsAttr),
497	SSMFIELD_ENTRY( VMXVVMCS, u32GuestLdtrAttr),
498	SSMFIELD_ENTRY( VMXVVMCS, u32GuestTrAttr),
499	SSMFIELD_ENTRY( VMXVVMCS, u32GuestIntrState),
500	SSMFIELD_ENTRY( VMXVVMCS, u32GuestActivityState),
501	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSmBase),
502	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSysenterCS),
503	SSMFIELD_ENTRY( VMXVVMCS, u32PreemptTimer),
504	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved3),
505
506	SSMFIELD_ENTRY( VMXVVMCS, u64VmcsLinkPtr),
507	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDebugCtlMsr),
508	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPatMsr),
509	SSMFIELD_ENTRY( VMXVVMCS, u64GuestEferMsr),
510	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPerfGlobalCtlMsr),
511	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte0),
512	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte1),
513	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte2),
514	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte3),
515	SSMFIELD_ENTRY( VMXVVMCS, u64GuestBndcfgsMsr),
516	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRtitCtlMsr),
517	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestPkrsMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
518	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved2),
519
520	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr0),
521	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr3),
522	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr4),
523	SSMFIELD_ENTRY( VMXVVMCS, u64GuestEsBase),
524	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCsBase),
525	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSsBase),
526	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDsBase),
527	SSMFIELD_ENTRY( VMXVVMCS, u64GuestFsBase),
528	SSMFIELD_ENTRY( VMXVVMCS, u64GuestGsBase),
529	SSMFIELD_ENTRY( VMXVVMCS, u64GuestLdtrBase),
530	SSMFIELD_ENTRY( VMXVVMCS, u64GuestTrBase),
531	SSMFIELD_ENTRY( VMXVVMCS, u64GuestGdtrBase),
532	SSMFIELD_ENTRY( VMXVVMCS, u64GuestIdtrBase),
533	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDr7),
534	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRsp),
535	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRip),
536	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRFlags),
537	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPendingDbgXcpts),
538	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSysenterEsp),
539	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSysenterEip),
540	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestSCetMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
541	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestSsp, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
542	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestIntrSspTableAddrMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
543	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved6),
544
545	SSMFIELD_ENTRY_TERM()
546	};
547
548	/** Saved state field descriptors for CPUMCTX. */
549	static const SSMFIELD g_aCpumX87Fields[] =
550	{
551	SSMFIELD_ENTRY( X86FXSTATE, FCW),
552	SSMFIELD_ENTRY( X86FXSTATE, FSW),
553	SSMFIELD_ENTRY( X86FXSTATE, FTW),
554	SSMFIELD_ENTRY( X86FXSTATE, FOP),
555	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
556	SSMFIELD_ENTRY( X86FXSTATE, CS),
557	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
558	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
559	SSMFIELD_ENTRY( X86FXSTATE, DS),
560	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
561	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
562	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
563	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
564	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
565	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
566	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
567	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
568	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
569	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
570	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
571	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
572	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
573	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
574	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
575	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
576	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
577	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
578	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
579	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
580	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
581	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
582	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
583	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
584	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
585	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
586	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
587	SSMFIELD_ENTRY_VER( X86FXSTATE, au32RsrvdForSoftware[0], CPUM_SAVED_STATE_VERSION_XSAVE), /* 32-bit/64-bit hack */
588	SSMFIELD_ENTRY_TERM()
589	};
590
591	/** Saved state field descriptors for X86XSAVEHDR. */
592	static const SSMFIELD g_aCpumXSaveHdrFields[] =
593	{
594	SSMFIELD_ENTRY( X86XSAVEHDR, bmXState),
595	SSMFIELD_ENTRY_TERM()
596	};
597
598	/** Saved state field descriptors for X86XSAVEYMMHI. */
599	static const SSMFIELD g_aCpumYmmHiFields[] =
600	{
601	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[0]),
602	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[1]),
603	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[2]),
604	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[3]),
605	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[4]),
606	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[5]),
607	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[6]),
608	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[7]),
609	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[8]),
610	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[9]),
611	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[10]),
612	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[11]),
613	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[12]),
614	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[13]),
615	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[14]),
616	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[15]),
617	SSMFIELD_ENTRY_TERM()
618	};
619
620	/** Saved state field descriptors for X86XSAVEBNDREGS. */
621	static const SSMFIELD g_aCpumBndRegsFields[] =
622	{
623	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[0]),
624	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[1]),
625	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[2]),
626	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[3]),
627	SSMFIELD_ENTRY_TERM()
628	};
629
630	/** Saved state field descriptors for X86XSAVEBNDCFG. */
631	static const SSMFIELD g_aCpumBndCfgFields[] =
632	{
633	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fConfig),
634	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fStatus),
635	SSMFIELD_ENTRY_TERM()
636	};
637
638	#if 0 /** @todo */
639	/** Saved state field descriptors for X86XSAVEOPMASK. */
640	static const SSMFIELD g_aCpumOpmaskFields[] =
641	{
642	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[0]),
643	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[1]),
644	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[2]),
645	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[3]),
646	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[4]),
647	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[5]),
648	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[6]),
649	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[7]),
650	SSMFIELD_ENTRY_TERM()
651	};
652	#endif
653
654	/** Saved state field descriptors for X86XSAVEZMMHI256. */
655	static const SSMFIELD g_aCpumZmmHi256Fields[] =
656	{
657	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[0]),
658	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[1]),
659	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[2]),
660	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[3]),
661	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[4]),
662	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[5]),
663	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[6]),
664	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[7]),
665	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[8]),
666	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[9]),
667	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[10]),
668	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[11]),
669	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[12]),
670	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[13]),
671	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[14]),
672	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[15]),
673	SSMFIELD_ENTRY_TERM()
674	};
675
676	/** Saved state field descriptors for X86XSAVEZMM16HI. */
677	static const SSMFIELD g_aCpumZmm16HiFields[] =
678	{
679	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[0]),
680	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[1]),
681	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[2]),
682	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[3]),
683	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[4]),
684	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[5]),
685	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[6]),
686	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[7]),
687	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[8]),
688	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[9]),
689	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[10]),
690	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[11]),
691	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[12]),
692	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[13]),
693	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[14]),
694	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[15]),
695	SSMFIELD_ENTRY_TERM()
696	};
697
698
699
700	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
701	* registeres changed. */
702	static const SSMFIELD g_aCpumX87FieldsMem[] =
703	{
704	SSMFIELD_ENTRY( X86FXSTATE, FCW),
705	SSMFIELD_ENTRY( X86FXSTATE, FSW),
706	SSMFIELD_ENTRY( X86FXSTATE, FTW),
707	SSMFIELD_ENTRY( X86FXSTATE, FOP),
708	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
709	SSMFIELD_ENTRY( X86FXSTATE, CS),
710	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
711	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
712	SSMFIELD_ENTRY( X86FXSTATE, DS),
713	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
714	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
715	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
716	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
717	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
718	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
719	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
720	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
721	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
722	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
723	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
724	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
725	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
726	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
727	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
728	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
729	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
730	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
731	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
732	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
733	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
734	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
735	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
736	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
737	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
738	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
739	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
740	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
741	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
742	};
743
744	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
745	* registeres changed. */
746	static const SSMFIELD g_aCpumCtxFieldsMem[] =
747	{
748	SSMFIELD_ENTRY( CPUMCTX, rdi),
749	SSMFIELD_ENTRY( CPUMCTX, rsi),
750	SSMFIELD_ENTRY( CPUMCTX, rbp),
751	SSMFIELD_ENTRY( CPUMCTX, rax),
752	SSMFIELD_ENTRY( CPUMCTX, rbx),
753	SSMFIELD_ENTRY( CPUMCTX, rdx),
754	SSMFIELD_ENTRY( CPUMCTX, rcx),
755	SSMFIELD_ENTRY( CPUMCTX, rsp),
756	SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
757	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
758	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
759	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
760	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
761	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
762	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
763	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
764	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
765	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
766	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
767	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
768	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
769	SSMFIELD_ENTRY( CPUMCTX, rflags),
770	SSMFIELD_ENTRY( CPUMCTX, rip),
771	SSMFIELD_ENTRY( CPUMCTX, r8),
772	SSMFIELD_ENTRY( CPUMCTX, r9),
773	SSMFIELD_ENTRY( CPUMCTX, r10),
774	SSMFIELD_ENTRY( CPUMCTX, r11),
775	SSMFIELD_ENTRY( CPUMCTX, r12),
776	SSMFIELD_ENTRY( CPUMCTX, r13),
777	SSMFIELD_ENTRY( CPUMCTX, r14),
778	SSMFIELD_ENTRY( CPUMCTX, r15),
779	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
780	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
781	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
782	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
783	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
784	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
785	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
786	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
787	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
788	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
789	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
790	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
791	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
792	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
793	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
794	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
795	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
796	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
797	SSMFIELD_ENTRY( CPUMCTX, cr0),
798	SSMFIELD_ENTRY( CPUMCTX, cr2),
799	SSMFIELD_ENTRY( CPUMCTX, cr3),
800	SSMFIELD_ENTRY( CPUMCTX, cr4),
801	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
802	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
803	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
804	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
805	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
806	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
807	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
808	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
809	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
810	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
811	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
812	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
813	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
814	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
815	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
816	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
817	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
818	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
819	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
820	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
821	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
822	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
823	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
824	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
825	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
826	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
827	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
828	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
829	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
830	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
831	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
832	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
833	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
834	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
835	SSMFIELD_ENTRY_TERM()
836	};
837
838	/** Saved state field descriptors for CPUMCTX_VER1_6. */
839	static const SSMFIELD g_aCpumX87FieldsV16[] =
840	{
841	SSMFIELD_ENTRY( X86FXSTATE, FCW),
842	SSMFIELD_ENTRY( X86FXSTATE, FSW),
843	SSMFIELD_ENTRY( X86FXSTATE, FTW),
844	SSMFIELD_ENTRY( X86FXSTATE, FOP),
845	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
846	SSMFIELD_ENTRY( X86FXSTATE, CS),
847	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
848	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
849	SSMFIELD_ENTRY( X86FXSTATE, DS),
850	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
851	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
852	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
853	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
854	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
855	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
856	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
857	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
858	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
859	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
860	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
861	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
862	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
863	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
864	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
865	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
866	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
867	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
868	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
869	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
870	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
871	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
872	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
873	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
874	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
875	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
876	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
877	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
878	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
879	SSMFIELD_ENTRY_TERM()
880	};
881
882	/** Saved state field descriptors for CPUMCTX_VER1_6. */
883	static const SSMFIELD g_aCpumCtxFieldsV16[] =
884	{
885	SSMFIELD_ENTRY( CPUMCTX, rdi),
886	SSMFIELD_ENTRY( CPUMCTX, rsi),
887	SSMFIELD_ENTRY( CPUMCTX, rbp),
888	SSMFIELD_ENTRY( CPUMCTX, rax),
889	SSMFIELD_ENTRY( CPUMCTX, rbx),
890	SSMFIELD_ENTRY( CPUMCTX, rdx),
891	SSMFIELD_ENTRY( CPUMCTX, rcx),
892	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
893	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
894	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
895	SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /rsp_notused/),
896	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
897	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
898	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
899	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
900	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
901	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
902	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
903	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
904	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
905	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
906	SSMFIELD_ENTRY( CPUMCTX, rflags),
907	SSMFIELD_ENTRY( CPUMCTX, rip),
908	SSMFIELD_ENTRY( CPUMCTX, r8),
909	SSMFIELD_ENTRY( CPUMCTX, r9),
910	SSMFIELD_ENTRY( CPUMCTX, r10),
911	SSMFIELD_ENTRY( CPUMCTX, r11),
912	SSMFIELD_ENTRY( CPUMCTX, r12),
913	SSMFIELD_ENTRY( CPUMCTX, r13),
914	SSMFIELD_ENTRY( CPUMCTX, r14),
915	SSMFIELD_ENTRY( CPUMCTX, r15),
916	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
917	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
918	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
919	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
920	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
921	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
922	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
923	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
924	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
925	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
926	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
927	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
928	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
929	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
930	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
931	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
932	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
933	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
934	SSMFIELD_ENTRY( CPUMCTX, cr0),
935	SSMFIELD_ENTRY( CPUMCTX, cr2),
936	SSMFIELD_ENTRY( CPUMCTX, cr3),
937	SSMFIELD_ENTRY( CPUMCTX, cr4),
938	SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
939	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
940	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
941	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
942	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
943	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
944	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
945	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
946	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
947	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
948	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
949	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
950	SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
951	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
952	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
953	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
954	SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
955	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
956	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
957	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
958	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
959	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
960	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
961	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
962	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
963	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
964	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
965	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
966	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
967	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
968	SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
969	SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
970	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
971	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
972	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
973	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
974	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
975	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
976	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
977	SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
978	SSMFIELD_ENTRY_TERM()
979	};
980
981
982	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
983	/**
984	* Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs.
985	*
986	* AMD K7, K8 and newer AMD CPUs do not save/restore the x87 error pointers
987	* (last instruction pointer, last data pointer, last opcode) except when the ES
988	* bit (Exception Summary) in x87 FSW (FPU Status Word) is set. Thus if we don't
989	* clear these registers there is potential, local FPU leakage from a process
990	* using the FPU to another.
991	*
992	* See AMD Instruction Reference for FXSAVE, FXRSTOR.
993	*
994	* @param pVM The cross context VM structure.
995	*/
996	static void cpumR3CheckLeakyFpu(PVM pVM)
997	{
998	uint32_t u32CpuVersion = ASMCpuId_EAX(1);
999	uint32_t const u32Family = u32CpuVersion >> 8;
1000	if ( u32Family >= 6 /* K7 and higher */
1001	&& (ASMIsAmdCpu() \|\| ASMIsHygonCpu()) )
1002	{
1003	uint32_t cExt = ASMCpuId_EAX(0x80000000);
1004	if (RTX86IsValidExtRange(cExt))
1005	{
1006	uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
1007	if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1008	{
1009	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1010	{
1011	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1012	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_FFXSR_LEAKY;
1013	}
1014	Log(("CPUM: Host CPU has leaky fxsave/fxrstor behaviour\n"));
1015	}
1016	}
1017	}
1018	}
1019	#endif
1020
1021
1022	/**
1023	* Initialize SVM hardware virtualization state (used to allocate it).
1024	*
1025	* @param pVM The cross context VM structure.
1026	*/
1027	static void cpumR3InitSvmHwVirtState(PVM pVM)
1028	{
1029	Assert(pVM->cpum.s.GuestFeatures.fSvm);
1030
1031	LogRel(("CPUM: AMD-V nested-guest init\n"));
1032	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1033	{
1034	PVMCPU pVCpu = pVM->apCpusR3[i];
1035	pVCpu->cpum.s.Guest.hwvirt.enmHwvirt = CPUMHWVIRT_SVM;
1036
1037	AssertCompile(SVM_VMCB_PAGES * X86_PAGE_SIZE == sizeof(pVCpu->cpum.s.Guest.hwvirt.svm.Vmcb));
1038	AssertCompile(SVM_MSRPM_PAGES * X86_PAGE_SIZE == sizeof(pVCpu->cpum.s.Guest.hwvirt.svm.abMsrBitmap));
1039	AssertCompile(SVM_IOPM_PAGES * X86_PAGE_SIZE == sizeof(pVCpu->cpum.s.Guest.hwvirt.svm.abIoBitmap));
1040	}
1041	}
1042
1043
1044	/**
1045	* Resets per-VCPU SVM hardware virtualization state.
1046	*
1047	* @param pVCpu The cross context virtual CPU structure.
1048	*/
1049	DECLINLINE(void) cpumR3ResetSvmHwVirtState(PVMCPU pVCpu)
1050	{
1051	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1052	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_SVM);
1053
1054	RT_ZERO(pCtx->hwvirt.svm.Vmcb);
1055	pCtx->hwvirt.svm.uMsrHSavePa = 0;
1056	pCtx->hwvirt.svm.uPrevPauseTick = 0;
1057	}
1058
1059
1060	/**
1061	* Allocates memory for the VMX hardware virtualization state.
1062	*
1063	* @param pVM The cross context VM structure.
1064	*/
1065	static void cpumR3InitVmxHwVirtState(PVM pVM)
1066	{
1067	LogRel(("CPUM: VT-x nested-guest init\n"));
1068	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1069	{
1070	PVMCPU pVCpu = pVM->apCpusR3[i];
1071	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1072
1073	pCtx->hwvirt.enmHwvirt = CPUMHWVIRT_VMX;
1074
1075	AssertCompile(sizeof(pCtx->hwvirt.vmx.Vmcs) == VMX_V_VMCS_PAGES * X86_PAGE_SIZE);
1076	AssertCompile(sizeof(pCtx->hwvirt.vmx.Vmcs) == VMX_V_VMCS_SIZE);
1077	AssertCompile(sizeof(pCtx->hwvirt.vmx.ShadowVmcs) == VMX_V_SHADOW_VMCS_PAGES * X86_PAGE_SIZE);
1078	AssertCompile(sizeof(pCtx->hwvirt.vmx.ShadowVmcs) == VMX_V_SHADOW_VMCS_SIZE);
1079	AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmreadBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_PAGES * X86_PAGE_SIZE);
1080	AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmreadBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
1081	AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmwriteBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_PAGES * X86_PAGE_SIZE);
1082	AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmwriteBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
1083	AssertCompile(sizeof(pCtx->hwvirt.vmx.aEntryMsrLoadArea) == VMX_V_AUTOMSR_AREA_PAGES * X86_PAGE_SIZE);
1084	AssertCompile(sizeof(pCtx->hwvirt.vmx.aEntryMsrLoadArea) == VMX_V_AUTOMSR_AREA_SIZE);
1085	AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrStoreArea) == VMX_V_AUTOMSR_AREA_PAGES * X86_PAGE_SIZE);
1086	AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrStoreArea) == VMX_V_AUTOMSR_AREA_SIZE);
1087	AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrLoadArea) == VMX_V_AUTOMSR_AREA_PAGES * X86_PAGE_SIZE);
1088	AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrLoadArea) == VMX_V_AUTOMSR_AREA_SIZE);
1089	AssertCompile(sizeof(pCtx->hwvirt.vmx.abMsrBitmap) == VMX_V_MSR_BITMAP_PAGES * X86_PAGE_SIZE);
1090	AssertCompile(sizeof(pCtx->hwvirt.vmx.abMsrBitmap) == VMX_V_MSR_BITMAP_SIZE);
1091	AssertCompile(sizeof(pCtx->hwvirt.vmx.abIoBitmap) == (VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES) * X86_PAGE_SIZE);
1092	AssertCompile(sizeof(pCtx->hwvirt.vmx.abIoBitmap) == VMX_V_IO_BITMAP_A_SIZE + VMX_V_IO_BITMAP_B_SIZE);
1093	AssertCompile(sizeof(pCtx->hwvirt.vmx.abVirtApicPage) == VMX_V_VIRT_APIC_PAGES * X86_PAGE_SIZE);
1094	AssertCompile(sizeof(pCtx->hwvirt.vmx.abVirtApicPage) == VMX_V_VIRT_APIC_SIZE);
1095
1096	/*
1097	* Zero out all allocated pages (should compress well for saved-state).
1098	*/
1099	/** @todo r=bird: this is and always was unnecessary - they are already zeroed. */
1100	RT_ZERO(pCtx->hwvirt.vmx.Vmcs);
1101	RT_ZERO(pCtx->hwvirt.vmx.ShadowVmcs);
1102	RT_ZERO(pCtx->hwvirt.vmx.abVmreadBitmap);
1103	RT_ZERO(pCtx->hwvirt.vmx.abVmwriteBitmap);
1104	RT_ZERO(pCtx->hwvirt.vmx.aEntryMsrLoadArea);
1105	RT_ZERO(pCtx->hwvirt.vmx.aExitMsrStoreArea);
1106	RT_ZERO(pCtx->hwvirt.vmx.aExitMsrLoadArea);
1107	RT_ZERO(pCtx->hwvirt.vmx.abMsrBitmap);
1108	RT_ZERO(pCtx->hwvirt.vmx.abIoBitmap);
1109	RT_ZERO(pCtx->hwvirt.vmx.abVirtApicPage);
1110	}
1111	}
1112
1113
1114	/**
1115	* Resets per-VCPU VMX hardware virtualization state.
1116	*
1117	* @param pVCpu The cross context virtual CPU structure.
1118	*/
1119	DECLINLINE(void) cpumR3ResetVmxHwVirtState(PVMCPU pVCpu)
1120	{
1121	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1122	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_VMX);
1123
1124	RT_ZERO(pCtx->hwvirt.vmx.Vmcs);
1125	RT_ZERO(pCtx->hwvirt.vmx.ShadowVmcs);
1126	pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1127	pCtx->hwvirt.vmx.GCPhysShadowVmcs = NIL_RTGCPHYS;
1128	pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1129	pCtx->hwvirt.vmx.fInVmxRootMode = false;
1130	pCtx->hwvirt.vmx.fInVmxNonRootMode = false;
1131	/* Don't reset diagnostics here. */
1132
1133	/* Stop any VMX-preemption timer. */
1134	CPUMStopGuestVmxPremptTimer(pVCpu);
1135
1136	/* Clear all nested-guest FFs. */
1137	VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_ALL_MASK);
1138	}
1139
1140
1141	/**
1142	* Displays the host and guest VMX features.
1143	*
1144	* @param pVM The cross context VM structure.
1145	* @param pHlp The info helper functions.
1146	* @param pszArgs "terse", "default" or "verbose".
1147	*/
1148	DECLCALLBACK(void) cpumR3InfoVmxFeatures(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1149	{
1150	RT_NOREF(pszArgs);
1151	PCCPUMFEATURES pHostFeatures = &pVM->cpum.s.HostFeatures;
1152	PCCPUMFEATURES pGuestFeatures = &pVM->cpum.s.GuestFeatures;
1153	if ( pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL
1154	\|\| pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_VIA
1155	\|\| pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_SHANGHAI)
1156	{
1157	#define VMXFEATDUMP(a_szDesc, a_Var) \
1158	pHlp->pfnPrintf(pHlp, " %s = %u (%u)\n", a_szDesc, pGuestFeatures->a_Var, pHostFeatures->a_Var)
1159
1160	pHlp->pfnPrintf(pHlp, "Nested hardware virtualization - VMX features\n");
1161	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
1162	VMXFEATDUMP("VMX - Virtual-Machine Extensions ", fVmx);
1163	/* Basic. */
1164	VMXFEATDUMP("InsOutInfo - INS/OUTS instruction info. ", fVmxInsOutInfo);
1165
1166	/* Pin-based controls. */
1167	VMXFEATDUMP("ExtIntExit - External interrupt exiting ", fVmxExtIntExit);
1168	VMXFEATDUMP("NmiExit - NMI exiting ", fVmxNmiExit);
1169	VMXFEATDUMP("VirtNmi - Virtual NMIs ", fVmxVirtNmi);
1170	VMXFEATDUMP("PreemptTimer - VMX preemption timer ", fVmxPreemptTimer);
1171	VMXFEATDUMP("PostedInt - Posted interrupts ", fVmxPostedInt);
1172
1173	/* Processor-based controls. */
1174	VMXFEATDUMP("IntWindowExit - Interrupt-window exiting ", fVmxIntWindowExit);
1175	VMXFEATDUMP("TscOffsetting - TSC offsetting ", fVmxTscOffsetting);
1176	VMXFEATDUMP("HltExit - HLT exiting ", fVmxHltExit);
1177	VMXFEATDUMP("InvlpgExit - INVLPG exiting ", fVmxInvlpgExit);
1178	VMXFEATDUMP("MwaitExit - MWAIT exiting ", fVmxMwaitExit);
1179	VMXFEATDUMP("RdpmcExit - RDPMC exiting ", fVmxRdpmcExit);
1180	VMXFEATDUMP("RdtscExit - RDTSC exiting ", fVmxRdtscExit);
1181	VMXFEATDUMP("Cr3LoadExit - CR3-load exiting ", fVmxCr3LoadExit);
1182	VMXFEATDUMP("Cr3StoreExit - CR3-store exiting ", fVmxCr3StoreExit);
1183	VMXFEATDUMP("TertiaryExecCtls - Activate tertiary controls ", fVmxTertiaryExecCtls);
1184	VMXFEATDUMP("Cr8LoadExit - CR8-load exiting ", fVmxCr8LoadExit);
1185	VMXFEATDUMP("Cr8StoreExit - CR8-store exiting ", fVmxCr8StoreExit);
1186	VMXFEATDUMP("UseTprShadow - Use TPR shadow ", fVmxUseTprShadow);
1187	VMXFEATDUMP("NmiWindowExit - NMI-window exiting ", fVmxNmiWindowExit);
1188	VMXFEATDUMP("MovDRxExit - Mov-DR exiting ", fVmxMovDRxExit);
1189	VMXFEATDUMP("UncondIoExit - Unconditional I/O exiting ", fVmxUncondIoExit);
1190	VMXFEATDUMP("UseIoBitmaps - Use I/O bitmaps ", fVmxUseIoBitmaps);
1191	VMXFEATDUMP("MonitorTrapFlag - Monitor Trap Flag ", fVmxMonitorTrapFlag);
1192	VMXFEATDUMP("UseMsrBitmaps - MSR bitmaps ", fVmxUseMsrBitmaps);
1193	VMXFEATDUMP("MonitorExit - MONITOR exiting ", fVmxMonitorExit);
1194	VMXFEATDUMP("PauseExit - PAUSE exiting ", fVmxPauseExit);
1195	VMXFEATDUMP("SecondaryExecCtl - Activate secondary controls ", fVmxSecondaryExecCtls);
1196
1197	/* Secondary processor-based controls. */
1198	VMXFEATDUMP("VirtApic - Virtualize-APIC accesses ", fVmxVirtApicAccess);
1199	VMXFEATDUMP("Ept - Extended Page Tables ", fVmxEpt);
1200	VMXFEATDUMP("DescTableExit - Descriptor-table exiting ", fVmxDescTableExit);
1201	VMXFEATDUMP("Rdtscp - Enable RDTSCP ", fVmxRdtscp);
1202	VMXFEATDUMP("VirtX2ApicMode - Virtualize-x2APIC mode ", fVmxVirtX2ApicMode);
1203	VMXFEATDUMP("Vpid - Enable VPID ", fVmxVpid);
1204	VMXFEATDUMP("WbinvdExit - WBINVD exiting ", fVmxWbinvdExit);
1205	VMXFEATDUMP("UnrestrictedGuest - Unrestricted guest ", fVmxUnrestrictedGuest);
1206	VMXFEATDUMP("ApicRegVirt - APIC-register virtualization ", fVmxApicRegVirt);
1207	VMXFEATDUMP("VirtIntDelivery - Virtual-interrupt delivery ", fVmxVirtIntDelivery);
1208	VMXFEATDUMP("PauseLoopExit - PAUSE-loop exiting ", fVmxPauseLoopExit);
1209	VMXFEATDUMP("RdrandExit - RDRAND exiting ", fVmxRdrandExit);
1210	VMXFEATDUMP("Invpcid - Enable INVPCID ", fVmxInvpcid);
1211	VMXFEATDUMP("VmFuncs - Enable VM Functions ", fVmxVmFunc);
1212	VMXFEATDUMP("VmcsShadowing - VMCS shadowing ", fVmxVmcsShadowing);
1213	VMXFEATDUMP("RdseedExiting - RDSEED exiting ", fVmxRdseedExit);
1214	VMXFEATDUMP("PML - Page-Modification Log (PML) ", fVmxPml);
1215	VMXFEATDUMP("EptVe - EPT violations can cause #VE ", fVmxEptXcptVe);
1216	VMXFEATDUMP("ConcealVmxFromPt - Conceal VMX from Processor Trace ", fVmxConcealVmxFromPt);
1217	VMXFEATDUMP("XsavesXRstors - Enable XSAVES/XRSTORS ", fVmxXsavesXrstors);
1218	VMXFEATDUMP("ModeBasedExecuteEpt - Mode-based execute permissions ", fVmxModeBasedExecuteEpt);
1219	VMXFEATDUMP("SppEpt - Sub-page page write permissions for EPT ", fVmxSppEpt);
1220	VMXFEATDUMP("PtEpt - Processor Trace address' translatable by EPT ", fVmxPtEpt);
1221	VMXFEATDUMP("UseTscScaling - Use TSC scaling ", fVmxUseTscScaling);
1222	VMXFEATDUMP("UserWaitPause - Enable TPAUSE, UMONITOR and UMWAIT ", fVmxUserWaitPause);
1223	VMXFEATDUMP("EnclvExit - ENCLV exiting ", fVmxEnclvExit);
1224
1225	/* Tertiary processor-based controls. */
1226	VMXFEATDUMP("LoadIwKeyExit - LOADIWKEY exiting ", fVmxLoadIwKeyExit);
1227
1228	/* VM-entry controls. */
1229	VMXFEATDUMP("EntryLoadDebugCtls - Load debug controls on VM-entry ", fVmxEntryLoadDebugCtls);
1230	VMXFEATDUMP("Ia32eModeGuest - IA-32e mode guest ", fVmxIa32eModeGuest);
1231	VMXFEATDUMP("EntryLoadEferMsr - Load IA32_EFER MSR on VM-entry ", fVmxEntryLoadEferMsr);
1232	VMXFEATDUMP("EntryLoadPatMsr - Load IA32_PAT MSR on VM-entry ", fVmxEntryLoadPatMsr);
1233
1234	/* VM-exit controls. */
1235	VMXFEATDUMP("ExitSaveDebugCtls - Save debug controls on VM-exit ", fVmxExitSaveDebugCtls);
1236	VMXFEATDUMP("HostAddrSpaceSize - Host address-space size ", fVmxHostAddrSpaceSize);
1237	VMXFEATDUMP("ExitAckExtInt - Acknowledge interrupt on VM-exit ", fVmxExitAckExtInt);
1238	VMXFEATDUMP("ExitSavePatMsr - Save IA32_PAT MSR on VM-exit ", fVmxExitSavePatMsr);
1239	VMXFEATDUMP("ExitLoadPatMsr - Load IA32_PAT MSR on VM-exit ", fVmxExitLoadPatMsr);
1240	VMXFEATDUMP("ExitSaveEferMsr - Save IA32_EFER MSR on VM-exit ", fVmxExitSaveEferMsr);
1241	VMXFEATDUMP("ExitLoadEferMsr - Load IA32_EFER MSR on VM-exit ", fVmxExitLoadEferMsr);
1242	VMXFEATDUMP("SavePreemptTimer - Save VMX-preemption timer ", fVmxSavePreemptTimer);
1243
1244	/* Miscellaneous data. */
1245	VMXFEATDUMP("ExitSaveEferLma - Save IA32_EFER.LMA on VM-exit ", fVmxExitSaveEferLma);
1246	VMXFEATDUMP("IntelPt - Intel PT (Processor Trace) in VMX operation ", fVmxPt);
1247	VMXFEATDUMP("VmwriteAll - VMWRITE to any supported VMCS field ", fVmxVmwriteAll);
1248	VMXFEATDUMP("EntryInjectSoftInt - Inject softint. with 0-len instr. ", fVmxEntryInjectSoftInt);
1249	#undef VMXFEATDUMP
1250	}
1251	else
1252	pHlp->pfnPrintf(pHlp, "No VMX features present - requires an Intel or compatible CPU.\n");
1253	}
1254
1255
1256	/**
1257	* Checks whether nested-guest execution using hardware-assisted VMX (e.g, using HM
1258	* or NEM) is allowed.
1259	*
1260	* @returns @c true if hardware-assisted nested-guest execution is allowed, @c false
1261	* otherwise.
1262	* @param pVM The cross context VM structure.
1263	*/
1264	static bool cpumR3IsHwAssistNstGstExecAllowed(PVM pVM)
1265	{
1266	AssertMsg(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET, ("Calling this function too early!\n"));
1267	#ifndef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
1268	if ( pVM->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT
1269	\|\| pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1270	return true;
1271	#else
1272	NOREF(pVM);
1273	#endif
1274	return false;
1275	}
1276
1277
1278	/**
1279	* Initializes the VMX guest MSRs from guest CPU features based on the host MSRs.
1280	*
1281	* @param pVM The cross context VM structure.
1282	* @param pHostVmxMsrs The host VMX MSRs. Pass NULL when fully emulating VMX
1283	* and no hardware-assisted nested-guest execution is
1284	* possible for this VM.
1285	* @param pGuestFeatures The guest features to use (only VMX features are
1286	* accessed).
1287	* @param pGuestVmxMsrs Where to store the initialized guest VMX MSRs.
1288	*
1289	* @remarks This function ASSUMES the VMX guest-features are already exploded!
1290	*/
1291	static void cpumR3InitVmxGuestMsrs(PVM pVM, PCVMXMSRS pHostVmxMsrs, PCCPUMFEATURES pGuestFeatures, PVMXMSRS pGuestVmxMsrs)
1292	{
1293	bool const fIsNstGstHwExecAllowed = cpumR3IsHwAssistNstGstExecAllowed(pVM);
1294
1295	Assert(!fIsNstGstHwExecAllowed \|\| pHostVmxMsrs);
1296	Assert(pGuestFeatures->fVmx);
1297
1298	/*
1299	* We don't support the following MSRs yet:
1300	* - True Pin-based VM-execution controls.
1301	* - True Processor-based VM-execution controls.
1302	* - True VM-entry VM-execution controls.
1303	* - True VM-exit VM-execution controls.
1304	*/
1305
1306	/* Basic information. */
1307	uint8_t const fTrueVmxMsrs = 1;
1308	{
1309	uint64_t const u64Basic = RT_BF_MAKE(VMX_BF_BASIC_VMCS_ID, VMX_V_VMCS_REVISION_ID )
1310	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_SIZE, VMX_V_VMCS_SIZE )
1311	\| RT_BF_MAKE(VMX_BF_BASIC_PHYSADDR_WIDTH, !pGuestFeatures->fLongMode )
1312	\| RT_BF_MAKE(VMX_BF_BASIC_DUAL_MON, 0 )
1313	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_MEM_TYPE, VMX_BASIC_MEM_TYPE_WB )
1314	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_INS_OUTS, pGuestFeatures->fVmxInsOutInfo)
1315	\| RT_BF_MAKE(VMX_BF_BASIC_TRUE_CTLS, fTrueVmxMsrs );
1316	pGuestVmxMsrs->u64Basic = u64Basic;
1317	}
1318
1319	/* Pin-based VM-execution controls. */
1320	{
1321	uint32_t const fFeatures = (pGuestFeatures->fVmxExtIntExit << VMX_BF_PIN_CTLS_EXT_INT_EXIT_SHIFT )
1322	\| (pGuestFeatures->fVmxNmiExit << VMX_BF_PIN_CTLS_NMI_EXIT_SHIFT )
1323	\| (pGuestFeatures->fVmxVirtNmi << VMX_BF_PIN_CTLS_VIRT_NMI_SHIFT )
1324	\| (pGuestFeatures->fVmxPreemptTimer << VMX_BF_PIN_CTLS_PREEMPT_TIMER_SHIFT)
1325	\| (pGuestFeatures->fVmxPostedInt << VMX_BF_PIN_CTLS_POSTED_INT_SHIFT );
1326	uint32_t const fAllowed0 = VMX_PIN_CTLS_DEFAULT1;
1327	uint32_t const fAllowed1 = fFeatures \| VMX_PIN_CTLS_DEFAULT1;
1328	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n",
1329	fAllowed0, fAllowed1, fFeatures));
1330	pGuestVmxMsrs->PinCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1331
1332	/* True pin-based VM-execution controls. */
1333	if (fTrueVmxMsrs)
1334	{
1335	/* VMX_PIN_CTLS_DEFAULT1 contains MB1 reserved bits and must be reserved MB1 in true pin-based controls as well. */
1336	pGuestVmxMsrs->TruePinCtls.u = pGuestVmxMsrs->PinCtls.u;
1337	}
1338	}
1339
1340	/* Processor-based VM-execution controls. */
1341	{
1342	uint32_t const fFeatures = (pGuestFeatures->fVmxIntWindowExit << VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_SHIFT )
1343	\| (pGuestFeatures->fVmxTscOffsetting << VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_SHIFT)
1344	\| (pGuestFeatures->fVmxHltExit << VMX_BF_PROC_CTLS_HLT_EXIT_SHIFT )
1345	\| (pGuestFeatures->fVmxInvlpgExit << VMX_BF_PROC_CTLS_INVLPG_EXIT_SHIFT )
1346	\| (pGuestFeatures->fVmxMwaitExit << VMX_BF_PROC_CTLS_MWAIT_EXIT_SHIFT )
1347	\| (pGuestFeatures->fVmxRdpmcExit << VMX_BF_PROC_CTLS_RDPMC_EXIT_SHIFT )
1348	\| (pGuestFeatures->fVmxRdtscExit << VMX_BF_PROC_CTLS_RDTSC_EXIT_SHIFT )
1349	\| (pGuestFeatures->fVmxCr3LoadExit << VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_SHIFT )
1350	\| (pGuestFeatures->fVmxCr3StoreExit << VMX_BF_PROC_CTLS_CR3_STORE_EXIT_SHIFT )
1351	\| (pGuestFeatures->fVmxTertiaryExecCtls << VMX_BF_PROC_CTLS_USE_TERTIARY_CTLS_SHIFT )
1352	\| (pGuestFeatures->fVmxCr8LoadExit << VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_SHIFT )
1353	\| (pGuestFeatures->fVmxCr8StoreExit << VMX_BF_PROC_CTLS_CR8_STORE_EXIT_SHIFT )
1354	\| (pGuestFeatures->fVmxUseTprShadow << VMX_BF_PROC_CTLS_USE_TPR_SHADOW_SHIFT )
1355	\| (pGuestFeatures->fVmxNmiWindowExit << VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_SHIFT )
1356	\| (pGuestFeatures->fVmxMovDRxExit << VMX_BF_PROC_CTLS_MOV_DR_EXIT_SHIFT )
1357	\| (pGuestFeatures->fVmxUncondIoExit << VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_SHIFT )
1358	\| (pGuestFeatures->fVmxUseIoBitmaps << VMX_BF_PROC_CTLS_USE_IO_BITMAPS_SHIFT )
1359	\| (pGuestFeatures->fVmxMonitorTrapFlag << VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_SHIFT )
1360	\| (pGuestFeatures->fVmxUseMsrBitmaps << VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_SHIFT )
1361	\| (pGuestFeatures->fVmxMonitorExit << VMX_BF_PROC_CTLS_MONITOR_EXIT_SHIFT )
1362	\| (pGuestFeatures->fVmxPauseExit << VMX_BF_PROC_CTLS_PAUSE_EXIT_SHIFT )
1363	\| (pGuestFeatures->fVmxSecondaryExecCtls << VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_SHIFT);
1364	uint32_t const fAllowed0 = VMX_PROC_CTLS_DEFAULT1;
1365	uint32_t const fAllowed1 = fFeatures \| VMX_PROC_CTLS_DEFAULT1;
1366	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1367	fAllowed1, fFeatures));
1368	pGuestVmxMsrs->ProcCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1369
1370	/* True processor-based VM-execution controls. */
1371	if (fTrueVmxMsrs)
1372	{
1373	/* VMX_PROC_CTLS_DEFAULT1 contains MB1 reserved bits but the following are not really reserved. */
1374	uint32_t const fTrueAllowed0 = VMX_PROC_CTLS_DEFAULT1 & ~( VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_MASK
1375	\| VMX_BF_PROC_CTLS_CR3_STORE_EXIT_MASK);
1376	uint32_t const fTrueAllowed1 = fFeatures \| fTrueAllowed0;
1377	pGuestVmxMsrs->TrueProcCtls.u = RT_MAKE_U64(fTrueAllowed0, fTrueAllowed1);
1378	}
1379	}
1380
1381	/* Secondary processor-based VM-execution controls. */
1382	if (pGuestFeatures->fVmxSecondaryExecCtls)
1383	{
1384	uint32_t const fFeatures = (pGuestFeatures->fVmxVirtApicAccess << VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_SHIFT )
1385	\| (pGuestFeatures->fVmxEpt << VMX_BF_PROC_CTLS2_EPT_SHIFT )
1386	\| (pGuestFeatures->fVmxDescTableExit << VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_SHIFT )
1387	\| (pGuestFeatures->fVmxRdtscp << VMX_BF_PROC_CTLS2_RDTSCP_SHIFT )
1388	\| (pGuestFeatures->fVmxVirtX2ApicMode << VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_SHIFT )
1389	\| (pGuestFeatures->fVmxVpid << VMX_BF_PROC_CTLS2_VPID_SHIFT )
1390	\| (pGuestFeatures->fVmxWbinvdExit << VMX_BF_PROC_CTLS2_WBINVD_EXIT_SHIFT )
1391	\| (pGuestFeatures->fVmxUnrestrictedGuest << VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_SHIFT )
1392	\| (pGuestFeatures->fVmxApicRegVirt << VMX_BF_PROC_CTLS2_APIC_REG_VIRT_SHIFT )
1393	\| (pGuestFeatures->fVmxVirtIntDelivery << VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_SHIFT )
1394	\| (pGuestFeatures->fVmxPauseLoopExit << VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_SHIFT )
1395	\| (pGuestFeatures->fVmxRdrandExit << VMX_BF_PROC_CTLS2_RDRAND_EXIT_SHIFT )
1396	\| (pGuestFeatures->fVmxInvpcid << VMX_BF_PROC_CTLS2_INVPCID_SHIFT )
1397	\| (pGuestFeatures->fVmxVmFunc << VMX_BF_PROC_CTLS2_VMFUNC_SHIFT )
1398	\| (pGuestFeatures->fVmxVmcsShadowing << VMX_BF_PROC_CTLS2_VMCS_SHADOWING_SHIFT )
1399	\| (pGuestFeatures->fVmxRdseedExit << VMX_BF_PROC_CTLS2_RDSEED_EXIT_SHIFT )
1400	\| (pGuestFeatures->fVmxPml << VMX_BF_PROC_CTLS2_PML_SHIFT )
1401	\| (pGuestFeatures->fVmxEptXcptVe << VMX_BF_PROC_CTLS2_EPT_VE_SHIFT )
1402	\| (pGuestFeatures->fVmxConcealVmxFromPt << VMX_BF_PROC_CTLS2_CONCEAL_VMX_FROM_PT_SHIFT)
1403	\| (pGuestFeatures->fVmxXsavesXrstors << VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_SHIFT )
1404	\| (pGuestFeatures->fVmxModeBasedExecuteEpt << VMX_BF_PROC_CTLS2_MODE_BASED_EPT_PERM_SHIFT)
1405	\| (pGuestFeatures->fVmxSppEpt << VMX_BF_PROC_CTLS2_SPP_EPT_SHIFT )
1406	\| (pGuestFeatures->fVmxPtEpt << VMX_BF_PROC_CTLS2_PT_EPT_SHIFT )
1407	\| (pGuestFeatures->fVmxUseTscScaling << VMX_BF_PROC_CTLS2_TSC_SCALING_SHIFT )
1408	\| (pGuestFeatures->fVmxUserWaitPause << VMX_BF_PROC_CTLS2_USER_WAIT_PAUSE_SHIFT )
1409	\| (pGuestFeatures->fVmxEnclvExit << VMX_BF_PROC_CTLS2_ENCLV_EXIT_SHIFT );
1410	uint32_t const fAllowed0 = 0;
1411	uint32_t const fAllowed1 = fFeatures;
1412	pGuestVmxMsrs->ProcCtls2.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1413	}
1414
1415	/* Tertiary processor-based VM-execution controls. */
1416	if (pGuestFeatures->fVmxTertiaryExecCtls)
1417	{
1418	pGuestVmxMsrs->u64ProcCtls3 = (pGuestFeatures->fVmxLoadIwKeyExit << VMX_BF_PROC_CTLS3_LOADIWKEY_EXIT_SHIFT);
1419	}
1420
1421	/* VM-exit controls. */
1422	{
1423	uint32_t const fFeatures = (pGuestFeatures->fVmxExitSaveDebugCtls << VMX_BF_EXIT_CTLS_SAVE_DEBUG_SHIFT )
1424	\| (pGuestFeatures->fVmxHostAddrSpaceSize << VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_SHIFT)
1425	\| (pGuestFeatures->fVmxExitAckExtInt << VMX_BF_EXIT_CTLS_ACK_EXT_INT_SHIFT )
1426	\| (pGuestFeatures->fVmxExitSavePatMsr << VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_SHIFT )
1427	\| (pGuestFeatures->fVmxExitLoadPatMsr << VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_SHIFT )
1428	\| (pGuestFeatures->fVmxExitSaveEferMsr << VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_SHIFT )
1429	\| (pGuestFeatures->fVmxExitLoadEferMsr << VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_SHIFT )
1430	\| (pGuestFeatures->fVmxSavePreemptTimer << VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_SHIFT );
1431	/* Set the default1 class bits. See Intel spec. A.4 "VM-exit Controls". */
1432	uint32_t const fAllowed0 = VMX_EXIT_CTLS_DEFAULT1;
1433	uint32_t const fAllowed1 = fFeatures \| VMX_EXIT_CTLS_DEFAULT1;
1434	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1435	fAllowed1, fFeatures));
1436	pGuestVmxMsrs->ExitCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1437
1438	/* True VM-exit controls. */
1439	if (fTrueVmxMsrs)
1440	{
1441	/* VMX_EXIT_CTLS_DEFAULT1 contains MB1 reserved bits but the following are not really reserved */
1442	uint32_t const fTrueAllowed0 = VMX_EXIT_CTLS_DEFAULT1 & ~VMX_BF_EXIT_CTLS_SAVE_DEBUG_MASK;
1443	uint32_t const fTrueAllowed1 = fFeatures \| fTrueAllowed0;
1444	pGuestVmxMsrs->TrueExitCtls.u = RT_MAKE_U64(fTrueAllowed0, fTrueAllowed1);
1445	}
1446	}
1447
1448	/* VM-entry controls. */
1449	{
1450	uint32_t const fFeatures = (pGuestFeatures->fVmxEntryLoadDebugCtls << VMX_BF_ENTRY_CTLS_LOAD_DEBUG_SHIFT )
1451	\| (pGuestFeatures->fVmxIa32eModeGuest << VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_SHIFT)
1452	\| (pGuestFeatures->fVmxEntryLoadEferMsr << VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_SHIFT )
1453	\| (pGuestFeatures->fVmxEntryLoadPatMsr << VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_SHIFT );
1454	uint32_t const fAllowed0 = VMX_ENTRY_CTLS_DEFAULT1;
1455	uint32_t const fAllowed1 = fFeatures \| VMX_ENTRY_CTLS_DEFAULT1;
1456	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed0=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1457	fAllowed1, fFeatures));
1458	pGuestVmxMsrs->EntryCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1459
1460	/* True VM-entry controls. */
1461	if (fTrueVmxMsrs)
1462	{
1463	/* VMX_ENTRY_CTLS_DEFAULT1 contains MB1 reserved bits but the following are not really reserved */
1464	uint32_t const fTrueAllowed0 = VMX_ENTRY_CTLS_DEFAULT1 & ~( VMX_BF_ENTRY_CTLS_LOAD_DEBUG_MASK
1465	\| VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_MASK
1466	\| VMX_BF_ENTRY_CTLS_ENTRY_SMM_MASK
1467	\| VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_MASK);
1468	uint32_t const fTrueAllowed1 = fFeatures \| fTrueAllowed0;
1469	pGuestVmxMsrs->TrueEntryCtls.u = RT_MAKE_U64(fTrueAllowed0, fTrueAllowed1);
1470	}
1471	}
1472
1473	/* Miscellaneous data. */
1474	{
1475	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Misc : 0;
1476
1477	uint8_t const cMaxMsrs = RT_MIN(RT_BF_GET(uHostMsr, VMX_BF_MISC_MAX_MSRS), VMX_V_AUTOMSR_COUNT_MAX);
1478	uint8_t const fActivityState = RT_BF_GET(uHostMsr, VMX_BF_MISC_ACTIVITY_STATES) & VMX_V_GUEST_ACTIVITY_STATE_MASK;
1479	pGuestVmxMsrs->u64Misc = RT_BF_MAKE(VMX_BF_MISC_PREEMPT_TIMER_TSC, VMX_V_PREEMPT_TIMER_SHIFT )
1480	\| RT_BF_MAKE(VMX_BF_MISC_EXIT_SAVE_EFER_LMA, pGuestFeatures->fVmxExitSaveEferLma )
1481	\| RT_BF_MAKE(VMX_BF_MISC_ACTIVITY_STATES, fActivityState )
1482	\| RT_BF_MAKE(VMX_BF_MISC_INTEL_PT, pGuestFeatures->fVmxPt )
1483	\| RT_BF_MAKE(VMX_BF_MISC_SMM_READ_SMBASE_MSR, 0 )
1484	\| RT_BF_MAKE(VMX_BF_MISC_CR3_TARGET, VMX_V_CR3_TARGET_COUNT )
1485	\| RT_BF_MAKE(VMX_BF_MISC_MAX_MSRS, cMaxMsrs )
1486	\| RT_BF_MAKE(VMX_BF_MISC_VMXOFF_BLOCK_SMI, 0 )
1487	\| RT_BF_MAKE(VMX_BF_MISC_VMWRITE_ALL, pGuestFeatures->fVmxVmwriteAll )
1488	\| RT_BF_MAKE(VMX_BF_MISC_ENTRY_INJECT_SOFT_INT, pGuestFeatures->fVmxEntryInjectSoftInt)
1489	\| RT_BF_MAKE(VMX_BF_MISC_MSEG_ID, VMX_V_MSEG_REV_ID );
1490	}
1491
1492	/* CR0 Fixed-0 (we report this fixed value regardless of whether UX is supported as it does on real hardware). */
1493	pGuestVmxMsrs->u64Cr0Fixed0 = VMX_V_CR0_FIXED0;
1494
1495	/* CR0 Fixed-1. */
1496	{
1497	/*
1498	* All CPUs I've looked at so far report CR0 fixed-1 bits as 0xffffffff.
1499	* This is different from CR4 fixed-1 bits which are reported as per the
1500	* CPU features and/or micro-architecture/generation. Why? Ask Intel.
1501	*/
1502	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Cr0Fixed1 : VMX_V_CR0_FIXED1;
1503	pGuestVmxMsrs->u64Cr0Fixed1 = uHostMsr \| pGuestVmxMsrs->u64Cr0Fixed0; /* Make sure the CR0 MB1 bits are not clear. */
1504	}
1505
1506	/* CR4 Fixed-0. */
1507	pGuestVmxMsrs->u64Cr4Fixed0 = VMX_V_CR4_FIXED0;
1508
1509	/* CR4 Fixed-1. */
1510	{
1511	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Cr4Fixed1 : CPUMGetGuestCR4ValidMask(pVM);
1512	pGuestVmxMsrs->u64Cr4Fixed1 = uHostMsr \| pGuestVmxMsrs->u64Cr4Fixed0; /* Make sure the CR4 MB1 bits are not clear. */
1513	}
1514
1515	/* VMCS Enumeration. */
1516	pGuestVmxMsrs->u64VmcsEnum = VMX_V_VMCS_MAX_INDEX << VMX_BF_VMCS_ENUM_HIGHEST_IDX_SHIFT;
1517
1518	/* VPID and EPT Capabilities. */
1519	if (pGuestFeatures->fVmxEpt)
1520	{
1521	/*
1522	* INVVPID instruction always causes a VM-exit unconditionally, so we are free to fake
1523	* and emulate any INVVPID flush type. However, it only makes sense to expose the types
1524	* when INVVPID instruction is supported just to be more compatible with guest
1525	* hypervisors that may make assumptions by only looking at this MSR even though they
1526	* are technically supposed to refer to VMX_PROC_CTLS2_VPID first.
1527	*
1528	* See Intel spec. 25.1.2 "Instructions That Cause VM Exits Unconditionally".
1529	* See Intel spec. 30.3 "VMX Instructions".
1530	*/
1531	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64EptVpidCaps : UINT64_MAX;
1532	uint8_t const fVpid = pGuestFeatures->fVmxVpid;
1533
1534	uint8_t const fExecOnly = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_EXEC_ONLY);
1535	uint8_t const fPml4 = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1536	uint8_t const fMemTypeUc = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_MEMTYPE_UC);
1537	uint8_t const fMemTypeWb = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_MEMTYPE_WB);
1538	uint8_t const f2MPage = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_PDE_2M);
1539	uint8_t const f1GPage = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_PDPTE_1G);
1540	uint8_t const fInvept = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT);
1541	/** @todo Nested VMX: Support accessed/dirty bits, see @bugref{10092#c25}. */
1542	/* uint8_t const fAccessDirty = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY); */
1543	uint8_t const fEptSingle = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX);
1544	uint8_t const fEptAll = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX);
1545	uint8_t const fVpidIndiv = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1546	uint8_t const fVpidSingle = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
1547	uint8_t const fVpidAll = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
1548	uint8_t const fVpidSingleGlobal = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
1549	pGuestVmxMsrs->u64EptVpidCaps = RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_EXEC_ONLY, fExecOnly)
1550	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4, fPml4)
1551	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_MEMTYPE_UC, fMemTypeUc)
1552	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_MEMTYPE_WB, fMemTypeWb)
1553	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PDE_2M, f2MPage)
1554	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PDPTE_1G, f1GPage)
1555	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT, fInvept)
1556	//\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY, 0)
1557	//\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION, 0)
1558	//\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_SUPER_SHW_STACK, 0)
1559	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX, fEptSingle)
1560	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX, fEptAll)
1561	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID, fVpid)
1562	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR, fVpid & fVpidIndiv)
1563	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX, fVpid & fVpidSingle)
1564	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX, fVpid & fVpidAll)
1565	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS, fVpid & fVpidSingleGlobal);
1566	}
1567
1568	/* VM Functions. */
1569	if (pGuestFeatures->fVmxVmFunc)
1570	pGuestVmxMsrs->u64VmFunc = RT_BF_MAKE(VMX_BF_VMFUNC_EPTP_SWITCHING, 1);
1571	}
1572
1573
1574	/**
1575	* Checks whether the given guest CPU VMX features are compatible with the provided
1576	* base features.
1577	*
1578	* @returns @c true if compatible, @c false otherwise.
1579	* @param pVM The cross context VM structure.
1580	* @param pBase The base VMX CPU features.
1581	* @param pGst The guest VMX CPU features.
1582	*
1583	* @remarks Only VMX feature bits are examined.
1584	*/
1585	static bool cpumR3AreVmxCpuFeaturesCompatible(PVM pVM, PCCPUMFEATURES pBase, PCCPUMFEATURES pGst)
1586	{
1587	if (!cpumR3IsHwAssistNstGstExecAllowed(pVM))
1588	return false;
1589
1590	#define CPUM_VMX_FEAT_SHIFT(a_pFeat, a_FeatName, a_cShift) ((uint64_t)(a_pFeat->a_FeatName) << (a_cShift))
1591	#define CPUM_VMX_MAKE_FEATURES_1(a_pFeat) ( CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxInsOutInfo , 0) \
1592	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExtIntExit , 1) \
1593	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxNmiExit , 2) \
1594	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtNmi , 3) \
1595	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPreemptTimer , 4) \
1596	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPostedInt , 5) \
1597	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxIntWindowExit , 6) \
1598	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxTscOffsetting , 7) \
1599	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxHltExit , 8) \
1600	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxInvlpgExit , 9) \
1601	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMwaitExit , 10) \
1602	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdpmcExit , 12) \
1603	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdtscExit , 13) \
1604	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr3LoadExit , 14) \
1605	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr3StoreExit , 15) \
1606	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxTertiaryExecCtls , 16) \
1607	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr8LoadExit , 17) \
1608	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr8StoreExit , 18) \
1609	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseTprShadow , 19) \
1610	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxNmiWindowExit , 20) \
1611	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMovDRxExit , 21) \
1612	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUncondIoExit , 22) \
1613	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseIoBitmaps , 23) \
1614	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMonitorTrapFlag , 24) \
1615	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseMsrBitmaps , 25) \
1616	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMonitorExit , 26) \
1617	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPauseExit , 27) \
1618	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxSecondaryExecCtls , 28) \
1619	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtApicAccess , 29) \
1620	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEpt , 30) \
1621	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxDescTableExit , 31) \
1622	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdtscp , 32) \
1623	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtX2ApicMode , 33) \
1624	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVpid , 34) \
1625	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxWbinvdExit , 35) \
1626	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUnrestrictedGuest , 36) \
1627	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxApicRegVirt , 37) \
1628	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtIntDelivery , 38) \
1629	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPauseLoopExit , 39) \
1630	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdrandExit , 40) \
1631	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxInvpcid , 41) \
1632	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVmFunc , 42) \
1633	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVmcsShadowing , 43) \
1634	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdseedExit , 44) \
1635	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPml , 45) \
1636	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEptXcptVe , 46) \
1637	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxConcealVmxFromPt , 47) \
1638	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxXsavesXrstors , 48) \
1639	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxModeBasedExecuteEpt, 49) \
1640	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxSppEpt , 50) \
1641	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPtEpt , 51) \
1642	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseTscScaling , 52) \
1643	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUserWaitPause , 53) \
1644	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEnclvExit , 54) \
1645	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxLoadIwKeyExit , 55) \
1646	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryLoadDebugCtls , 56) \
1647	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxIa32eModeGuest , 57) \
1648	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryLoadEferMsr , 58) \
1649	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryLoadPatMsr , 59) \
1650	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSaveDebugCtls , 60) \
1651	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxHostAddrSpaceSize , 61) \
1652	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitAckExtInt , 62) \
1653	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSavePatMsr , 63))
1654
1655	#define CPUM_VMX_MAKE_FEATURES_2(a_pFeat) ( CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitLoadPatMsr , 0) \
1656	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSaveEferMsr , 1) \
1657	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitLoadEferMsr , 2) \
1658	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxSavePreemptTimer , 3) \
1659	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSaveEferLma , 4) \
1660	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPt , 5) \
1661	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVmwriteAll , 6) \
1662	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryInjectSoftInt , 7))
1663
1664	/* Check first set of feature bits. */
1665	{
1666	uint64_t const fBase = CPUM_VMX_MAKE_FEATURES_1(pBase);
1667	uint64_t const fGst = CPUM_VMX_MAKE_FEATURES_1(pGst);
1668	if ((fBase \| fGst) != fBase)
1669	{
1670	uint64_t const fDiff = fBase ^ fGst;
1671	LogRel(("CPUM: VMX features (1) now exposed to the guest are incompatible with those from the saved state. fBase=%#RX64 fGst=%#RX64 fDiff=%#RX64\n",
1672	fBase, fGst, fDiff));
1673	return false;
1674	}
1675	}
1676
1677	/* Check second set of feature bits. */
1678	{
1679	uint64_t const fBase = CPUM_VMX_MAKE_FEATURES_2(pBase);
1680	uint64_t const fGst = CPUM_VMX_MAKE_FEATURES_2(pGst);
1681	if ((fBase \| fGst) != fBase)
1682	{
1683	uint64_t const fDiff = fBase ^ fGst;
1684	LogRel(("CPUM: VMX features (2) now exposed to the guest are incompatible with those from the saved state. fBase=%#RX64 fGst=%#RX64 fDiff=%#RX64\n",
1685	fBase, fGst, fDiff));
1686	return false;
1687	}
1688	}
1689	#undef CPUM_VMX_FEAT_SHIFT
1690	#undef CPUM_VMX_MAKE_FEATURES_1
1691	#undef CPUM_VMX_MAKE_FEATURES_2
1692
1693	return true;
1694	}
1695
1696
1697	/**
1698	* Initializes VMX guest features and MSRs.
1699	*
1700	* @param pVM The cross context VM structure.
1701	* @param pHostVmxMsrs The host VMX MSRs. Pass NULL when fully emulating VMX
1702	* and no hardware-assisted nested-guest execution is
1703	* possible for this VM.
1704	* @param pGuestVmxMsrs Where to store the initialized guest VMX MSRs.
1705	*/
1706	void cpumR3InitVmxGuestFeaturesAndMsrs(PVM pVM, PCVMXMSRS pHostVmxMsrs, PVMXMSRS pGuestVmxMsrs)
1707	{
1708	Assert(pVM);
1709	Assert(pGuestVmxMsrs);
1710
1711	/*
1712	* While it would be nice to check this earlier while initializing fNestedVmxEpt
1713	* but we would not have enumearted host features then, so do it at least now.
1714	*/
1715	if ( !pVM->cpum.s.HostFeatures.fNoExecute
1716	&& pVM->cpum.s.fNestedVmxEpt)
1717	{
1718	LogRel(("CPUM: Warning! EPT not exposed to the guest since NX isn't available on the host.\n"));
1719	pVM->cpum.s.fNestedVmxEpt = false;
1720	pVM->cpum.s.fNestedVmxUnrestrictedGuest = false;
1721	}
1722
1723	/*
1724	* Initialize the set of VMX features we emulate.
1725	*
1726	* Note! Some bits might be reported as 1 always if they fall under the
1727	* default1 class bits (e.g. fVmxEntryLoadDebugCtls), see @bugref{9180#c5}.
1728	*/
1729	CPUMFEATURES EmuFeat;
1730	RT_ZERO(EmuFeat);
1731	EmuFeat.fVmx = 1;
1732	EmuFeat.fVmxInsOutInfo = 1;
1733	EmuFeat.fVmxExtIntExit = 1;
1734	EmuFeat.fVmxNmiExit = 1;
1735	EmuFeat.fVmxVirtNmi = 1;
1736	EmuFeat.fVmxPreemptTimer = pVM->cpum.s.fNestedVmxPreemptTimer;
1737	EmuFeat.fVmxPostedInt = 0;
1738	EmuFeat.fVmxIntWindowExit = 1;
1739	EmuFeat.fVmxTscOffsetting = 1;
1740	EmuFeat.fVmxHltExit = 1;
1741	EmuFeat.fVmxInvlpgExit = 1;
1742	EmuFeat.fVmxMwaitExit = 1;
1743	EmuFeat.fVmxRdpmcExit = 1;
1744	EmuFeat.fVmxRdtscExit = 1;
1745	EmuFeat.fVmxCr3LoadExit = 1;
1746	EmuFeat.fVmxCr3StoreExit = 1;
1747	EmuFeat.fVmxTertiaryExecCtls = 0;
1748	EmuFeat.fVmxCr8LoadExit = 1;
1749	EmuFeat.fVmxCr8StoreExit = 1;
1750	EmuFeat.fVmxUseTprShadow = 1;
1751	EmuFeat.fVmxNmiWindowExit = 0;
1752	EmuFeat.fVmxMovDRxExit = 1;
1753	EmuFeat.fVmxUncondIoExit = 1;
1754	EmuFeat.fVmxUseIoBitmaps = 1;
1755	EmuFeat.fVmxMonitorTrapFlag = 0;
1756	EmuFeat.fVmxUseMsrBitmaps = 1;
1757	EmuFeat.fVmxMonitorExit = 1;
1758	EmuFeat.fVmxPauseExit = 1;
1759	EmuFeat.fVmxSecondaryExecCtls = 1;
1760	EmuFeat.fVmxVirtApicAccess = 1;
1761	EmuFeat.fVmxEpt = pVM->cpum.s.fNestedVmxEpt;
1762	EmuFeat.fVmxDescTableExit = 1;
1763	EmuFeat.fVmxRdtscp = 1;
1764	EmuFeat.fVmxVirtX2ApicMode = 0;
1765	EmuFeat.fVmxVpid = 0; /** @todo Consider enabling this when EPT works. */
1766	EmuFeat.fVmxWbinvdExit = 1;
1767	EmuFeat.fVmxUnrestrictedGuest = pVM->cpum.s.fNestedVmxUnrestrictedGuest;
1768	EmuFeat.fVmxApicRegVirt = 0;
1769	EmuFeat.fVmxVirtIntDelivery = 0;
1770	EmuFeat.fVmxPauseLoopExit = 0;
1771	EmuFeat.fVmxRdrandExit = 0;
1772	EmuFeat.fVmxInvpcid = 1;
1773	EmuFeat.fVmxVmFunc = 0;
1774	EmuFeat.fVmxVmcsShadowing = 0;
1775	EmuFeat.fVmxRdseedExit = 0;
1776	EmuFeat.fVmxPml = 0;
1777	EmuFeat.fVmxEptXcptVe = 0;
1778	EmuFeat.fVmxConcealVmxFromPt = 0;
1779	EmuFeat.fVmxXsavesXrstors = 0;
1780	EmuFeat.fVmxModeBasedExecuteEpt = 0;
1781	EmuFeat.fVmxSppEpt = 0;
1782	EmuFeat.fVmxPtEpt = 0;
1783	EmuFeat.fVmxUseTscScaling = 0;
1784	EmuFeat.fVmxUserWaitPause = 0;
1785	EmuFeat.fVmxEnclvExit = 0;
1786	EmuFeat.fVmxLoadIwKeyExit = 0;
1787	EmuFeat.fVmxEntryLoadDebugCtls = 1;
1788	EmuFeat.fVmxIa32eModeGuest = 1;
1789	EmuFeat.fVmxEntryLoadEferMsr = 1;
1790	EmuFeat.fVmxEntryLoadPatMsr = 0;
1791	EmuFeat.fVmxExitSaveDebugCtls = 1;
1792	EmuFeat.fVmxHostAddrSpaceSize = 1;
1793	EmuFeat.fVmxExitAckExtInt = 1;
1794	EmuFeat.fVmxExitSavePatMsr = 0;
1795	EmuFeat.fVmxExitLoadPatMsr = 0;
1796	EmuFeat.fVmxExitSaveEferMsr = 1;
1797	EmuFeat.fVmxExitLoadEferMsr = 1;
1798	EmuFeat.fVmxSavePreemptTimer = 0; /* Cannot be enabled if VMX-preemption timer is disabled. */
1799	EmuFeat.fVmxExitSaveEferLma = 1; /* Cannot be disabled if unrestricted guest is enabled. */
1800	EmuFeat.fVmxPt = 0;
1801	EmuFeat.fVmxVmwriteAll = 0; /** @todo NSTVMX: enable this when nested VMCS shadowing is enabled. */
1802	EmuFeat.fVmxEntryInjectSoftInt = 1;
1803
1804	/*
1805	* Merge guest features.
1806	*
1807	* When hardware-assisted VMX may be used, any feature we emulate must also be supported
1808	* by the hardware, hence we merge our emulated features with the host features below.
1809	*/
1810	PCCPUMFEATURES pBaseFeat = cpumR3IsHwAssistNstGstExecAllowed(pVM) ? &pVM->cpum.s.HostFeatures : &EmuFeat;
1811	PCPUMFEATURES pGuestFeat = &pVM->cpum.s.GuestFeatures;
1812	Assert(pBaseFeat->fVmx);
1813	pGuestFeat->fVmxInsOutInfo = (pBaseFeat->fVmxInsOutInfo & EmuFeat.fVmxInsOutInfo );
1814	pGuestFeat->fVmxExtIntExit = (pBaseFeat->fVmxExtIntExit & EmuFeat.fVmxExtIntExit );
1815	pGuestFeat->fVmxNmiExit = (pBaseFeat->fVmxNmiExit & EmuFeat.fVmxNmiExit );
1816	pGuestFeat->fVmxVirtNmi = (pBaseFeat->fVmxVirtNmi & EmuFeat.fVmxVirtNmi );
1817	pGuestFeat->fVmxPreemptTimer = (pBaseFeat->fVmxPreemptTimer & EmuFeat.fVmxPreemptTimer );
1818	pGuestFeat->fVmxPostedInt = (pBaseFeat->fVmxPostedInt & EmuFeat.fVmxPostedInt );
1819	pGuestFeat->fVmxIntWindowExit = (pBaseFeat->fVmxIntWindowExit & EmuFeat.fVmxIntWindowExit );
1820	pGuestFeat->fVmxTscOffsetting = (pBaseFeat->fVmxTscOffsetting & EmuFeat.fVmxTscOffsetting );
1821	pGuestFeat->fVmxHltExit = (pBaseFeat->fVmxHltExit & EmuFeat.fVmxHltExit );
1822	pGuestFeat->fVmxInvlpgExit = (pBaseFeat->fVmxInvlpgExit & EmuFeat.fVmxInvlpgExit );
1823	pGuestFeat->fVmxMwaitExit = (pBaseFeat->fVmxMwaitExit & EmuFeat.fVmxMwaitExit );
1824	pGuestFeat->fVmxRdpmcExit = (pBaseFeat->fVmxRdpmcExit & EmuFeat.fVmxRdpmcExit );
1825	pGuestFeat->fVmxRdtscExit = (pBaseFeat->fVmxRdtscExit & EmuFeat.fVmxRdtscExit );
1826	pGuestFeat->fVmxCr3LoadExit = (pBaseFeat->fVmxCr3LoadExit & EmuFeat.fVmxCr3LoadExit );
1827	pGuestFeat->fVmxCr3StoreExit = (pBaseFeat->fVmxCr3StoreExit & EmuFeat.fVmxCr3StoreExit );
1828	pGuestFeat->fVmxTertiaryExecCtls = (pBaseFeat->fVmxTertiaryExecCtls & EmuFeat.fVmxTertiaryExecCtls );
1829	pGuestFeat->fVmxCr8LoadExit = (pBaseFeat->fVmxCr8LoadExit & EmuFeat.fVmxCr8LoadExit );
1830	pGuestFeat->fVmxCr8StoreExit = (pBaseFeat->fVmxCr8StoreExit & EmuFeat.fVmxCr8StoreExit );
1831	pGuestFeat->fVmxUseTprShadow = (pBaseFeat->fVmxUseTprShadow & EmuFeat.fVmxUseTprShadow );
1832	pGuestFeat->fVmxNmiWindowExit = (pBaseFeat->fVmxNmiWindowExit & EmuFeat.fVmxNmiWindowExit );
1833	pGuestFeat->fVmxMovDRxExit = (pBaseFeat->fVmxMovDRxExit & EmuFeat.fVmxMovDRxExit );
1834	pGuestFeat->fVmxUncondIoExit = (pBaseFeat->fVmxUncondIoExit & EmuFeat.fVmxUncondIoExit );
1835	pGuestFeat->fVmxUseIoBitmaps = (pBaseFeat->fVmxUseIoBitmaps & EmuFeat.fVmxUseIoBitmaps );
1836	pGuestFeat->fVmxMonitorTrapFlag = (pBaseFeat->fVmxMonitorTrapFlag & EmuFeat.fVmxMonitorTrapFlag );
1837	pGuestFeat->fVmxUseMsrBitmaps = (pBaseFeat->fVmxUseMsrBitmaps & EmuFeat.fVmxUseMsrBitmaps );
1838	pGuestFeat->fVmxMonitorExit = (pBaseFeat->fVmxMonitorExit & EmuFeat.fVmxMonitorExit );
1839	pGuestFeat->fVmxPauseExit = (pBaseFeat->fVmxPauseExit & EmuFeat.fVmxPauseExit );
1840	pGuestFeat->fVmxSecondaryExecCtls = (pBaseFeat->fVmxSecondaryExecCtls & EmuFeat.fVmxSecondaryExecCtls );
1841	pGuestFeat->fVmxVirtApicAccess = (pBaseFeat->fVmxVirtApicAccess & EmuFeat.fVmxVirtApicAccess );
1842	pGuestFeat->fVmxEpt = (pBaseFeat->fVmxEpt & EmuFeat.fVmxEpt );
1843	pGuestFeat->fVmxDescTableExit = (pBaseFeat->fVmxDescTableExit & EmuFeat.fVmxDescTableExit );
1844	pGuestFeat->fVmxRdtscp = (pBaseFeat->fVmxRdtscp & EmuFeat.fVmxRdtscp );
1845	pGuestFeat->fVmxVirtX2ApicMode = (pBaseFeat->fVmxVirtX2ApicMode & EmuFeat.fVmxVirtX2ApicMode );
1846	pGuestFeat->fVmxVpid = (pBaseFeat->fVmxVpid & EmuFeat.fVmxVpid );
1847	pGuestFeat->fVmxWbinvdExit = (pBaseFeat->fVmxWbinvdExit & EmuFeat.fVmxWbinvdExit );
1848	pGuestFeat->fVmxUnrestrictedGuest = (pBaseFeat->fVmxUnrestrictedGuest & EmuFeat.fVmxUnrestrictedGuest );
1849	pGuestFeat->fVmxApicRegVirt = (pBaseFeat->fVmxApicRegVirt & EmuFeat.fVmxApicRegVirt );
1850	pGuestFeat->fVmxVirtIntDelivery = (pBaseFeat->fVmxVirtIntDelivery & EmuFeat.fVmxVirtIntDelivery );
1851	pGuestFeat->fVmxPauseLoopExit = (pBaseFeat->fVmxPauseLoopExit & EmuFeat.fVmxPauseLoopExit );
1852	pGuestFeat->fVmxRdrandExit = (pBaseFeat->fVmxRdrandExit & EmuFeat.fVmxRdrandExit );
1853	pGuestFeat->fVmxInvpcid = (pBaseFeat->fVmxInvpcid & EmuFeat.fVmxInvpcid );
1854	pGuestFeat->fVmxVmFunc = (pBaseFeat->fVmxVmFunc & EmuFeat.fVmxVmFunc );
1855	pGuestFeat->fVmxVmcsShadowing = (pBaseFeat->fVmxVmcsShadowing & EmuFeat.fVmxVmcsShadowing );
1856	pGuestFeat->fVmxRdseedExit = (pBaseFeat->fVmxRdseedExit & EmuFeat.fVmxRdseedExit );
1857	pGuestFeat->fVmxPml = (pBaseFeat->fVmxPml & EmuFeat.fVmxPml );
1858	pGuestFeat->fVmxEptXcptVe = (pBaseFeat->fVmxEptXcptVe & EmuFeat.fVmxEptXcptVe );
1859	pGuestFeat->fVmxConcealVmxFromPt = (pBaseFeat->fVmxConcealVmxFromPt & EmuFeat.fVmxConcealVmxFromPt );
1860	pGuestFeat->fVmxXsavesXrstors = (pBaseFeat->fVmxXsavesXrstors & EmuFeat.fVmxXsavesXrstors );
1861	pGuestFeat->fVmxModeBasedExecuteEpt = (pBaseFeat->fVmxModeBasedExecuteEpt & EmuFeat.fVmxModeBasedExecuteEpt );
1862	pGuestFeat->fVmxSppEpt = (pBaseFeat->fVmxSppEpt & EmuFeat.fVmxSppEpt );
1863	pGuestFeat->fVmxPtEpt = (pBaseFeat->fVmxPtEpt & EmuFeat.fVmxPtEpt );
1864	pGuestFeat->fVmxUseTscScaling = (pBaseFeat->fVmxUseTscScaling & EmuFeat.fVmxUseTscScaling );
1865	pGuestFeat->fVmxUserWaitPause = (pBaseFeat->fVmxUserWaitPause & EmuFeat.fVmxUserWaitPause );
1866	pGuestFeat->fVmxEnclvExit = (pBaseFeat->fVmxEnclvExit & EmuFeat.fVmxEnclvExit );
1867	pGuestFeat->fVmxLoadIwKeyExit = (pBaseFeat->fVmxLoadIwKeyExit & EmuFeat.fVmxLoadIwKeyExit );
1868	pGuestFeat->fVmxEntryLoadDebugCtls = (pBaseFeat->fVmxEntryLoadDebugCtls & EmuFeat.fVmxEntryLoadDebugCtls );
1869	pGuestFeat->fVmxIa32eModeGuest = (pBaseFeat->fVmxIa32eModeGuest & EmuFeat.fVmxIa32eModeGuest );
1870	pGuestFeat->fVmxEntryLoadEferMsr = (pBaseFeat->fVmxEntryLoadEferMsr & EmuFeat.fVmxEntryLoadEferMsr );
1871	pGuestFeat->fVmxEntryLoadPatMsr = (pBaseFeat->fVmxEntryLoadPatMsr & EmuFeat.fVmxEntryLoadPatMsr );
1872	pGuestFeat->fVmxExitSaveDebugCtls = (pBaseFeat->fVmxExitSaveDebugCtls & EmuFeat.fVmxExitSaveDebugCtls );
1873	pGuestFeat->fVmxHostAddrSpaceSize = (pBaseFeat->fVmxHostAddrSpaceSize & EmuFeat.fVmxHostAddrSpaceSize );
1874	pGuestFeat->fVmxExitAckExtInt = (pBaseFeat->fVmxExitAckExtInt & EmuFeat.fVmxExitAckExtInt );
1875	pGuestFeat->fVmxExitSavePatMsr = (pBaseFeat->fVmxExitSavePatMsr & EmuFeat.fVmxExitSavePatMsr );
1876	pGuestFeat->fVmxExitLoadPatMsr = (pBaseFeat->fVmxExitLoadPatMsr & EmuFeat.fVmxExitLoadPatMsr );
1877	pGuestFeat->fVmxExitSaveEferMsr = (pBaseFeat->fVmxExitSaveEferMsr & EmuFeat.fVmxExitSaveEferMsr );
1878	pGuestFeat->fVmxExitLoadEferMsr = (pBaseFeat->fVmxExitLoadEferMsr & EmuFeat.fVmxExitLoadEferMsr );
1879	pGuestFeat->fVmxSavePreemptTimer = (pBaseFeat->fVmxSavePreemptTimer & EmuFeat.fVmxSavePreemptTimer );
1880	pGuestFeat->fVmxExitSaveEferLma = (pBaseFeat->fVmxExitSaveEferLma & EmuFeat.fVmxExitSaveEferLma );
1881	pGuestFeat->fVmxPt = (pBaseFeat->fVmxPt & EmuFeat.fVmxPt );
1882	pGuestFeat->fVmxVmwriteAll = (pBaseFeat->fVmxVmwriteAll & EmuFeat.fVmxVmwriteAll );
1883	pGuestFeat->fVmxEntryInjectSoftInt = (pBaseFeat->fVmxEntryInjectSoftInt & EmuFeat.fVmxEntryInjectSoftInt );
1884
1885	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
1886	/* Don't expose VMX preemption timer if host is subject to VMX-preemption timer erratum. */
1887	if ( pGuestFeat->fVmxPreemptTimer
1888	&& HMIsSubjectToVmxPreemptTimerErratum())
1889	{
1890	LogRel(("CPUM: Warning! VMX-preemption timer not exposed to guest due to host CPU erratum.\n"));
1891	pGuestFeat->fVmxPreemptTimer = 0;
1892	pGuestFeat->fVmxSavePreemptTimer = 0;
1893	}
1894	#endif
1895
1896	/* Sanity checking. */
1897	if (!pGuestFeat->fVmxSecondaryExecCtls)
1898	{
1899	Assert(!pGuestFeat->fVmxVirtApicAccess);
1900	Assert(!pGuestFeat->fVmxEpt);
1901	Assert(!pGuestFeat->fVmxDescTableExit);
1902	Assert(!pGuestFeat->fVmxRdtscp);
1903	Assert(!pGuestFeat->fVmxVirtX2ApicMode);
1904	Assert(!pGuestFeat->fVmxVpid);
1905	Assert(!pGuestFeat->fVmxWbinvdExit);
1906	Assert(!pGuestFeat->fVmxUnrestrictedGuest);
1907	Assert(!pGuestFeat->fVmxApicRegVirt);
1908	Assert(!pGuestFeat->fVmxVirtIntDelivery);
1909	Assert(!pGuestFeat->fVmxPauseLoopExit);
1910	Assert(!pGuestFeat->fVmxRdrandExit);
1911	Assert(!pGuestFeat->fVmxInvpcid);
1912	Assert(!pGuestFeat->fVmxVmFunc);
1913	Assert(!pGuestFeat->fVmxVmcsShadowing);
1914	Assert(!pGuestFeat->fVmxRdseedExit);
1915	Assert(!pGuestFeat->fVmxPml);
1916	Assert(!pGuestFeat->fVmxEptXcptVe);
1917	Assert(!pGuestFeat->fVmxConcealVmxFromPt);
1918	Assert(!pGuestFeat->fVmxXsavesXrstors);
1919	Assert(!pGuestFeat->fVmxModeBasedExecuteEpt);
1920	Assert(!pGuestFeat->fVmxSppEpt);
1921	Assert(!pGuestFeat->fVmxPtEpt);
1922	Assert(!pGuestFeat->fVmxUseTscScaling);
1923	Assert(!pGuestFeat->fVmxUserWaitPause);
1924	Assert(!pGuestFeat->fVmxEnclvExit);
1925	}
1926	else if (pGuestFeat->fVmxUnrestrictedGuest)
1927	{
1928	/* See footnote in Intel spec. 27.2 "Recording VM-Exit Information And Updating VM-entry Control Fields". */
1929	Assert(pGuestFeat->fVmxExitSaveEferLma);
1930	/* Unrestricted guest execution requires EPT. See Intel spec. 25.2.1.1 "VM-Execution Control Fields". */
1931	Assert(pGuestFeat->fVmxEpt);
1932	}
1933
1934	if (!pGuestFeat->fVmxTertiaryExecCtls)
1935	Assert(!pGuestFeat->fVmxLoadIwKeyExit);
1936
1937	/*
1938	* Finally initialize the VMX guest MSRs.
1939	*/
1940	cpumR3InitVmxGuestMsrs(pVM, pHostVmxMsrs, pGuestFeat, pGuestVmxMsrs);
1941	}
1942
1943
1944	/**
1945	* Gets the host hardware-virtualization MSRs.
1946	*
1947	* @returns VBox status code.
1948	* @param pMsrs Where to store the MSRs.
1949	*/
1950	static int cpumR3GetHostHwvirtMsrs(PCPUMMSRS pMsrs)
1951	{
1952	Assert(pMsrs);
1953
1954	uint32_t fCaps = 0;
1955	int rc = SUPR3QueryVTCaps(&fCaps);
1956	if (RT_SUCCESS(rc))
1957	{
1958	if (fCaps & (SUPVTCAPS_VT_X \| SUPVTCAPS_AMD_V))
1959	{
1960	SUPHWVIRTMSRS HwvirtMsrs;
1961	rc = SUPR3GetHwvirtMsrs(&HwvirtMsrs, false /* fForceRequery */);
1962	if (RT_SUCCESS(rc))
1963	{
1964	if (fCaps & SUPVTCAPS_VT_X)
1965	HMGetVmxMsrsFromHwvirtMsrs(&HwvirtMsrs, &pMsrs->hwvirt.vmx);
1966	else
1967	HMGetSvmMsrsFromHwvirtMsrs(&HwvirtMsrs, &pMsrs->hwvirt.svm);
1968	return VINF_SUCCESS;
1969	}
1970
1971	LogRel(("CPUM: Querying hardware-virtualization MSRs failed. rc=%Rrc\n", rc));
1972	return rc;
1973	}
1974
1975	LogRel(("CPUM: Querying hardware-virtualization capability succeeded but did not find VT-x or AMD-V\n"));
1976	return VERR_INTERNAL_ERROR_5;
1977	}
1978	LogRel(("CPUM: No hardware-virtualization capability detected\n"));
1979	return VINF_SUCCESS;
1980	}
1981
1982
1983	/**
1984	* @callback_method_impl{FNTMTIMERINT,
1985	* Callback that fires when the nested VMX-preemption timer expired.}
1986	*/
1987	static DECLCALLBACK(void) cpumR3VmxPreemptTimerCallback(PVM pVM, TMTIMERHANDLE hTimer, void *pvUser)
1988	{
1989	RT_NOREF(pVM, hTimer);
1990	PVMCPU pVCpu = (PVMCPUR3)pvUser;
1991	AssertPtr(pVCpu);
1992	VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
1993	}
1994
1995
1996	/**
1997	* Initializes the CPUM.
1998	*
1999	* @returns VBox status code.
2000	* @param pVM The cross context VM structure.
2001	*/
2002	VMMR3DECL(int) CPUMR3Init(PVM pVM)
2003	{
2004	LogFlow(("CPUMR3Init\n"));
2005
2006	/*
2007	* Assert alignment, sizes and tables.
2008	*/
2009	AssertCompileMemberAlignment(VM, cpum.s, 32);
2010	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
2011	AssertCompileSizeAlignment(CPUMCTX, 64);
2012	AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
2013	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
2014	AssertCompileMemberAlignment(VM, cpum, 64);
2015	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
2016	#ifdef VBOX_STRICT
2017	int rc2 = cpumR3MsrStrictInitChecks();
2018	AssertRCReturn(rc2, rc2);
2019	#endif
2020
2021	/*
2022	* Gather info about the host CPU.
2023	*/
2024	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
2025	if (!ASMHasCpuId())
2026	{
2027	LogRel(("The CPU doesn't support CPUID!\n"));
2028	return VERR_UNSUPPORTED_CPU;
2029	}
2030
2031	pVM->cpum.s.fHostMxCsrMask = CPUMR3DeterminHostMxCsrMask();
2032	#endif
2033
2034	CPUMMSRS HostMsrs;
2035	RT_ZERO(HostMsrs);
2036	int rc = cpumR3GetHostHwvirtMsrs(&HostMsrs);
2037	AssertLogRelRCReturn(rc, rc);
2038
2039	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
2040	PCPUMCPUIDLEAF paLeaves;
2041	uint32_t cLeaves;
2042	rc = CPUMCpuIdCollectLeavesX86(&paLeaves, &cLeaves);
2043	AssertLogRelRCReturn(rc, rc);
2044
2045	rc = cpumCpuIdExplodeFeaturesX86(paLeaves, cLeaves, &HostMsrs, &g_CpumHostFeatures.s);
2046	RTMemFree(paLeaves);
2047	AssertLogRelRCReturn(rc, rc);
2048	pVM->cpum.s.HostFeatures = g_CpumHostFeatures.s;
2049	pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.enmCpuVendor;
2050	#endif
2051
2052	/*
2053	* Check that the CPU supports the minimum features we require.
2054	*/
2055	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
2056	if (!pVM->cpum.s.HostFeatures.fFxSaveRstor)
2057	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support the FXSAVE/FXRSTOR instruction.");
2058	if (!pVM->cpum.s.HostFeatures.fMmx)
2059	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support MMX.");
2060	if (!pVM->cpum.s.HostFeatures.fTsc)
2061	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support RDTSC.");
2062	#endif
2063
2064	/*
2065	* Setup the CR4 AND and OR masks used in the raw-mode switcher.
2066	*/
2067	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
2068	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFXSR;
2069
2070	/*
2071	* Figure out which XSAVE/XRSTOR features are available on the host.
2072	*/
2073	uint64_t fXcr0Host = 0;
2074	uint64_t fXStateHostMask = 0;
2075	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
2076	if ( pVM->cpum.s.HostFeatures.fXSaveRstor
2077	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor)
2078	{
2079	fXStateHostMask = fXcr0Host = ASMGetXcr0();
2080	fXStateHostMask &= XSAVE_C_X87 \| XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI;
2081	AssertLogRelMsgStmt((fXStateHostMask & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
2082	("%#llx\n", fXStateHostMask), fXStateHostMask = 0);
2083	}
2084	#endif
2085	pVM->cpum.s.fXStateHostMask = fXStateHostMask;
2086	LogRel(("CPUM: fXStateHostMask=%#llx; initial: %#llx; host XCR0=%#llx\n",
2087	pVM->cpum.s.fXStateHostMask, fXStateHostMask, fXcr0Host));
2088
2089	/*
2090	* Initialize the host XSAVE/XRSTOR mask.
2091	*/
2092	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
2093	uint32_t cbMaxXState = pVM->cpum.s.HostFeatures.cbMaxExtendedState;
2094	cbMaxXState = RT_ALIGN(cbMaxXState, 128);
2095	AssertLogRelReturn( pVM->cpum.s.HostFeatures.cbMaxExtendedState >= sizeof(X86FXSTATE)
2096	&& pVM->cpum.s.HostFeatures.cbMaxExtendedState <= sizeof(pVM->apCpusR3[0]->cpum.s.Host.XState)
2097	&& pVM->cpum.s.HostFeatures.cbMaxExtendedState <= sizeof(pVM->apCpusR3[0]->cpum.s.Guest.XState)
2098	, VERR_CPUM_IPE_2);
2099	#endif
2100
2101	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2102	{
2103	PVMCPU pVCpu = pVM->apCpusR3[i];
2104
2105	pVCpu->cpum.s.Host.fXStateMask = fXStateHostMask;
2106	pVCpu->cpum.s.hNestedVmxPreemptTimer = NIL_TMTIMERHANDLE;
2107	}
2108
2109	/*
2110	* Register saved state data item.
2111	*/
2112	rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
2113	NULL, cpumR3LiveExec, NULL,
2114	NULL, cpumR3SaveExec, NULL,
2115	cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
2116	if (RT_FAILURE(rc))
2117	return rc;
2118
2119	/*
2120	* Register info handlers and registers with the debugger facility.
2121	*/
2122	DBGFR3InfoRegisterInternalEx(pVM, "cpum", "Displays the all the cpu states.",
2123	&cpumR3InfoAll, DBGFINFO_FLAGS_ALL_EMTS);
2124	DBGFR3InfoRegisterInternalEx(pVM, "cpumguest", "Displays the guest cpu state.",
2125	&cpumR3InfoGuest, DBGFINFO_FLAGS_ALL_EMTS);
2126	DBGFR3InfoRegisterInternalEx(pVM, "cpumguesthwvirt", "Displays the guest hwvirt. cpu state.",
2127	&cpumR3InfoGuestHwvirt, DBGFINFO_FLAGS_ALL_EMTS);
2128	DBGFR3InfoRegisterInternalEx(pVM, "cpumhyper", "Displays the hypervisor cpu state.",
2129	&cpumR3InfoHyper, DBGFINFO_FLAGS_ALL_EMTS);
2130	DBGFR3InfoRegisterInternalEx(pVM, "cpumhost", "Displays the host cpu state.",
2131	&cpumR3InfoHost, DBGFINFO_FLAGS_ALL_EMTS);
2132	DBGFR3InfoRegisterInternalEx(pVM, "cpumguestinstr", "Displays the current guest instruction.",
2133	&cpumR3InfoGuestInstr, DBGFINFO_FLAGS_ALL_EMTS);
2134	DBGFR3InfoRegisterInternal( pVM, "cpuid", "Displays the guest cpuid leaves.",
2135	&cpumR3CpuIdInfo);
2136	DBGFR3InfoRegisterInternal( pVM, "cpumvmxfeat", "Displays the host and guest VMX hwvirt. features.",
2137	&cpumR3InfoVmxFeatures);
2138
2139	rc = cpumR3DbgInit(pVM);
2140	if (RT_FAILURE(rc))
2141	return rc;
2142
2143	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
2144	/*
2145	* Check if we need to workaround partial/leaky FPU handling.
2146	*/
2147	cpumR3CheckLeakyFpu(pVM);
2148	#endif
2149
2150	/*
2151	* Initialize the Guest CPUID and MSR states.
2152	*/
2153	rc = cpumR3InitCpuIdAndMsrs(pVM, &HostMsrs);
2154	if (RT_FAILURE(rc))
2155	return rc;
2156
2157	/*
2158	* Init the VMX/SVM state.
2159	*
2160	* This must be done after initializing CPUID/MSR features as we access the
2161	* the VMX/SVM guest features below.
2162	*
2163	* In the case of nested VT-x, we also need to create the per-VCPU
2164	* VMX preemption timers.
2165	*/
2166	if (pVM->cpum.s.GuestFeatures.fVmx)
2167	cpumR3InitVmxHwVirtState(pVM);
2168	else if (pVM->cpum.s.GuestFeatures.fSvm)
2169	cpumR3InitSvmHwVirtState(pVM);
2170	else
2171	Assert(pVM->apCpusR3[0]->cpum.s.Guest.hwvirt.enmHwvirt == CPUMHWVIRT_NONE);
2172
2173	CPUMR3Reset(pVM);
2174	return VINF_SUCCESS;
2175	}
2176
2177
2178	/**
2179	* Applies relocations to data and code managed by this
2180	* component. This function will be called at init and
2181	* whenever the VMM need to relocate it self inside the GC.
2182	*
2183	* The CPUM will update the addresses used by the switcher.
2184	*
2185	* @param pVM The cross context VM structure.
2186	*/
2187	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
2188	{
2189	RT_NOREF(pVM);
2190	}
2191
2192
2193	/**
2194	* Terminates the CPUM.
2195	*
2196	* Termination means cleaning up and freeing all resources,
2197	* the VM it self is at this point powered off or suspended.
2198	*
2199	* @returns VBox status code.
2200	* @param pVM The cross context VM structure.
2201	*/
2202	VMMR3DECL(int) CPUMR3Term(PVM pVM)
2203	{
2204	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2205	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2206	{
2207	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2208	memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
2209	pVCpu->cpum.s.uMagic = 0;
2210	pvCpu->cpum.s.Guest.dr[5] = 0;
2211	}
2212	#endif
2213
2214	if (pVM->cpum.s.GuestFeatures.fVmx)
2215	{
2216	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2217	{
2218	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2219	if (pVCpu->cpum.s.hNestedVmxPreemptTimer != NIL_TMTIMERHANDLE)
2220	{
2221	int rc = TMR3TimerDestroy(pVM, pVCpu->cpum.s.hNestedVmxPreemptTimer); AssertRC(rc);
2222	pVCpu->cpum.s.hNestedVmxPreemptTimer = NIL_TMTIMERHANDLE;
2223	}
2224	}
2225	}
2226	return VINF_SUCCESS;
2227	}
2228
2229
2230	/**
2231	* Resets a virtual CPU.
2232	*
2233	* Used by CPUMR3Reset and CPU hot plugging.
2234	*
2235	* @param pVM The cross context VM structure.
2236	* @param pVCpu The cross context virtual CPU structure of the CPU that is
2237	* being reset. This may differ from the current EMT.
2238	*/
2239	VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
2240	{
2241	/** @todo anything different for VCPU > 0? */
2242	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2243
2244	/*
2245	* Initialize everything to ZERO first.
2246	*/
2247	uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
2248
2249	RT_BZERO(pCtx, RT_UOFFSETOF(CPUMCTX, aoffXState));
2250
2251	pVCpu->cpum.s.fUseFlags = fUseFlags;
2252
2253	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
2254	pCtx->eip = 0x0000fff0;
2255	pCtx->edx = 0x00000600; /* P6 processor */
2256	pCtx->eflags.Bits.u1Reserved0 = 1;
2257
2258	pCtx->cs.Sel = 0xf000;
2259	pCtx->cs.ValidSel = 0xf000;
2260	pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
2261	pCtx->cs.u64Base = UINT64_C(0xffff0000);
2262	pCtx->cs.u32Limit = 0x0000ffff;
2263	pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
2264	pCtx->cs.Attr.n.u1Present = 1;
2265	pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
2266
2267	pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
2268	pCtx->ds.u32Limit = 0x0000ffff;
2269	pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
2270	pCtx->ds.Attr.n.u1Present = 1;
2271	pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2272
2273	pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
2274	pCtx->es.u32Limit = 0x0000ffff;
2275	pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
2276	pCtx->es.Attr.n.u1Present = 1;
2277	pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2278
2279	pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
2280	pCtx->fs.u32Limit = 0x0000ffff;
2281	pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
2282	pCtx->fs.Attr.n.u1Present = 1;
2283	pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2284
2285	pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
2286	pCtx->gs.u32Limit = 0x0000ffff;
2287	pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
2288	pCtx->gs.Attr.n.u1Present = 1;
2289	pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2290
2291	pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
2292	pCtx->ss.u32Limit = 0x0000ffff;
2293	pCtx->ss.Attr.n.u1Present = 1;
2294	pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
2295	pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2296
2297	pCtx->idtr.cbIdt = 0xffff;
2298	pCtx->gdtr.cbGdt = 0xffff;
2299
2300	pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2301	pCtx->ldtr.u32Limit = 0xffff;
2302	pCtx->ldtr.Attr.n.u1Present = 1;
2303	pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
2304
2305	pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
2306	pCtx->tr.u32Limit = 0xffff;
2307	pCtx->tr.Attr.n.u1Present = 1;
2308	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
2309
2310	pCtx->dr[6] = X86_DR6_INIT_VAL;
2311	pCtx->dr[7] = X86_DR7_INIT_VAL;
2312
2313	PX86FXSTATE pFpuCtx = &pCtx->XState.x87;
2314	pFpuCtx->FTW = 0x00; /* All empty (abbridged tag reg edition). */
2315	pFpuCtx->FCW = 0x37f;
2316
2317	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
2318	IA-32 Processor States Following Power-up, Reset, or INIT */
2319	pFpuCtx->MXCSR = 0x1F80;
2320	pFpuCtx->MXCSR_MASK = pVM->cpum.s.GuestInfo.fMxCsrMask; /** @todo check if REM messes this up... */
2321
2322	pCtx->aXcr[0] = XSAVE_C_X87;
2323	if (pVM->cpum.s.HostFeatures.cbMaxExtendedState >= RT_UOFFSETOF(X86XSAVEAREA, Hdr))
2324	{
2325	/* The entire FXSAVE state needs loading when we switch to XSAVE/XRSTOR
2326	as we don't know what happened before. (Bother optimize later?) */
2327	pCtx->XState.Hdr.bmXState = XSAVE_C_X87 \| XSAVE_C_SSE;
2328	}
2329
2330	/*
2331	* MSRs.
2332	*/
2333	/* Init PAT MSR */
2334	pCtx->msrPAT = MSR_IA32_CR_PAT_INIT_VAL;
2335
2336	/* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
2337	* The Intel docs don't mention it. */
2338	Assert(!pCtx->msrEFER);
2339
2340	/* IA32_MISC_ENABLE - not entirely sure what the init/reset state really
2341	is supposed to be here, just trying provide useful/sensible values. */
2342	PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
2343	if (pRange)
2344	{
2345	pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
2346	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
2347	\| (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
2348	\| MSR_IA32_MISC_ENABLE_FAST_STRINGS;
2349	pRange->fWrIgnMask \|= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
2350	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
2351	pRange->fWrGpMask &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
2352	}
2353
2354	/** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
2355
2356	/** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
2357	* called from each EMT while we're getting called by CPUMR3Reset()
2358	* iteratively on the same thread. Fix later. */
2359	#if 0 /** @todo r=bird: This we will do in TM, not here. */
2360	/* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
2361	CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
2362	#endif
2363
2364
2365	/* C-state control. Guesses. */
2366	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /C1/ \| RT_BIT_32(25) \| RT_BIT_32(26) \| RT_BIT_32(27) \| RT_BIT_32(28);
2367	/* For Nehalem+ and Atoms, the 0xE2 MSR (MSR_PKG_CST_CONFIG_CONTROL) is documented. For Core 2,
2368	* it's undocumented but exists as MSR_PMG_CST_CONFIG_CONTROL and has similar but not identical
2369	* functionality. The default value must be different due to incompatible write mask.
2370	*/
2371	if (CPUMMICROARCH_IS_INTEL_CORE2(pVM->cpum.s.GuestFeatures.enmMicroarch))
2372	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x202a01; /* From Mac Pro Harpertown, unlocked. */
2373	else if (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Intel_Core_Yonah)
2374	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x26740c; /* From MacBookPro1,1. */
2375
2376	/*
2377	* Hardware virtualization state.
2378	*/
2379	CPUMSetGuestGif(pCtx, true);
2380	Assert(!pVM->cpum.s.GuestFeatures.fVmx \|\| !pVM->cpum.s.GuestFeatures.fSvm); /* Paranoia. */
2381	if (pVM->cpum.s.GuestFeatures.fVmx)
2382	cpumR3ResetVmxHwVirtState(pVCpu);
2383	else if (pVM->cpum.s.GuestFeatures.fSvm)
2384	cpumR3ResetSvmHwVirtState(pVCpu);
2385	}
2386
2387
2388	/**
2389	* Resets the CPU.
2390	*
2391	* @returns VINF_SUCCESS.
2392	* @param pVM The cross context VM structure.
2393	*/
2394	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
2395	{
2396	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2397	{
2398	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2399	CPUMR3ResetCpu(pVM, pVCpu);
2400
2401	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2402
2403	/* Magic marker for searching in crash dumps. */
2404	strcpy((char *)pVCpu->.cpum.s.aMagic, "CPUMCPU Magic");
2405	pVCpu->cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
2406	pVCpu->cpum.s.Guest->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
2407	#endif
2408	}
2409	}
2410
2411
2412
2413
2414	/**
2415	* Pass 0 live exec callback.
2416	*
2417	* @returns VINF_SSM_DONT_CALL_AGAIN.
2418	* @param pVM The cross context VM structure.
2419	* @param pSSM The saved state handle.
2420	* @param uPass The pass (0).
2421	*/
2422	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2423	{
2424	AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
2425	cpumR3SaveCpuId(pVM, pSSM);
2426	return VINF_SSM_DONT_CALL_AGAIN;
2427	}
2428
2429
2430	/**
2431	* Execute state save operation.
2432	*
2433	* @returns VBox status code.
2434	* @param pVM The cross context VM structure.
2435	* @param pSSM SSM operation handle.
2436	*/
2437	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
2438	{
2439	/*
2440	* Save.
2441	*/
2442	SSMR3PutU32(pSSM, pVM->cCpus);
2443	SSMR3PutU32(pSSM, sizeof(pVM->apCpusR3[0]->cpum.s.GuestMsrs.msr));
2444	CPUMCTX DummyHyperCtx;
2445	RT_ZERO(DummyHyperCtx);
2446	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2447	{
2448	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2449
2450	SSMR3PutStructEx(pSSM, &DummyHyperCtx, sizeof(DummyHyperCtx), 0, g_aCpumCtxFields, NULL);
2451
2452	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
2453	SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2454	SSMR3PutStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87), 0, g_aCpumX87Fields, NULL);
2455	if (pGstCtx->fXStateMask != 0)
2456	SSMR3PutStructEx(pSSM, &pGstCtx->XState.Hdr, sizeof(pGstCtx->XState.Hdr), 0, g_aCpumXSaveHdrFields, NULL);
2457	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
2458	{
2459	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
2460	SSMR3PutStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2461	}
2462	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2463	{
2464	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
2465	SSMR3PutStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2466	}
2467	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2468	{
2469	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
2470	SSMR3PutStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2471	}
2472	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2473	{
2474	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
2475	SSMR3PutStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2476	}
2477	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2478	{
2479	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
2480	SSMR3PutStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2481	}
2482	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[0].u);
2483	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[1].u);
2484	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[2].u);
2485	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[3].u);
2486	if (pVM->cpum.s.GuestFeatures.fSvm)
2487	{
2488	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uMsrHSavePa);
2489	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.svm.GCPhysVmcb);
2490	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uPrevPauseTick);
2491	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilter);
2492	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2493	SSMR3PutBool(pSSM, pGstCtx->hwvirt.svm.fInterceptEvents);
2494	SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState), 0 /* fFlags */,
2495	g_aSvmHwvirtHostState, NULL /* pvUser */);
2496	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.svm.Vmcb, sizeof(pGstCtx->hwvirt.svm.Vmcb));
2497	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.svm.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.svm.abMsrBitmap));
2498	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.svm.abIoBitmap[0], sizeof(pGstCtx->hwvirt.svm.abIoBitmap));
2499	SSMR3PutU32(pSSM, pGstCtx->hwvirt.fLocalForcedActions);
2500	SSMR3PutBool(pSSM, pGstCtx->hwvirt.fGif);
2501	}
2502	if (pVM->cpum.s.GuestFeatures.fVmx)
2503	{
2504	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysVmxon);
2505	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysVmcs);
2506	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysShadowVmcs);
2507	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInVmxRootMode);
2508	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInVmxNonRootMode);
2509	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInterceptEvents);
2510	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fNmiUnblockingIret);
2511	SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.vmx.Vmcs, sizeof(pGstCtx->hwvirt.vmx.Vmcs), 0, g_aVmxHwvirtVmcs, NULL);
2512	SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.vmx.ShadowVmcs, sizeof(pGstCtx->hwvirt.vmx.ShadowVmcs),
2513	0, g_aVmxHwvirtVmcs, NULL);
2514	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abVmreadBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmreadBitmap));
2515	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abVmwriteBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmwriteBitmap));
2516	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.aEntryMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aEntryMsrLoadArea));
2517	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrStoreArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrStoreArea));
2518	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrLoadArea));
2519	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abMsrBitmap));
2520	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abIoBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abIoBitmap));
2521	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uFirstPauseLoopTick);
2522	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uPrevPauseTick);
2523	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uEntryTick);
2524	SSMR3PutU16(pSSM, pGstCtx->hwvirt.vmx.offVirtApicWrite);
2525	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fVirtNmiBlocking);
2526	SSMR3PutU64(pSSM, MSR_IA32_FEATURE_CONTROL_LOCK \| MSR_IA32_FEATURE_CONTROL_VMXON); /* Deprecated since 2021/09/22. Value kept backwards compatibile with 6.1.26. */
2527	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Basic);
2528	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.PinCtls.u);
2529	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ProcCtls.u);
2530	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ProcCtls2.u);
2531	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ExitCtls.u);
2532	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.EntryCtls.u);
2533	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TruePinCtls.u);
2534	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueProcCtls.u);
2535	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueEntryCtls.u);
2536	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueExitCtls.u);
2537	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Misc);
2538	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed0);
2539	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed1);
2540	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed0);
2541	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed1);
2542	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64VmcsEnum);
2543	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64VmFunc);
2544	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64EptVpidCaps);
2545	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64ProcCtls3);
2546	}
2547	SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
2548	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
2549	AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
2550	SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
2551	}
2552
2553	cpumR3SaveCpuId(pVM, pSSM);
2554	return VINF_SUCCESS;
2555	}
2556
2557
2558	/**
2559	* @callback_method_impl{FNSSMINTLOADPREP}
2560	*/
2561	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2562	{
2563	NOREF(pSSM);
2564	pVM->cpum.s.fPendingRestore = true;
2565	return VINF_SUCCESS;
2566	}
2567
2568
2569	/**
2570	* @callback_method_impl{FNSSMINTLOADEXEC}
2571	*/
2572	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2573	{
2574	int rc; /* Only for AssertRCReturn use. */
2575
2576	/*
2577	* Validate version.
2578	*/
2579	if ( uVersion != CPUM_SAVED_STATE_VERSION_PAE_PDPES
2580	&& uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2
2581	&& uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX
2582	&& uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_SVM
2583	&& uVersion != CPUM_SAVED_STATE_VERSION_XSAVE
2584	&& uVersion != CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT
2585	&& uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
2586	&& uVersion != CPUM_SAVED_STATE_VERSION_PUT_STRUCT
2587	&& uVersion != CPUM_SAVED_STATE_VERSION_MEM
2588	&& uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
2589	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
2590	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
2591	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
2592	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2593	&& uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
2594	{
2595	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
2596	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2597	}
2598
2599	if (uPass == SSM_PASS_FINAL)
2600	{
2601	/*
2602	* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
2603	* really old SSM file versions.)
2604	*/
2605	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2606	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
2607	else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
2608	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR));
2609
2610	/*
2611	* Figure x86 and ctx field definitions to use for older states.
2612	*/
2613	uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
2614	PCSSMFIELD paCpumCtx1Fields = g_aCpumX87Fields;
2615	PCSSMFIELD paCpumCtx2Fields = g_aCpumCtxFields;
2616	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2617	{
2618	paCpumCtx1Fields = g_aCpumX87FieldsV16;
2619	paCpumCtx2Fields = g_aCpumCtxFieldsV16;
2620	}
2621	else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2622	{
2623	paCpumCtx1Fields = g_aCpumX87FieldsMem;
2624	paCpumCtx2Fields = g_aCpumCtxFieldsMem;
2625	}
2626
2627	/*
2628	* The hyper state used to preceed the CPU count. Starting with
2629	* XSAVE it was moved down till after we've got the count.
2630	*/
2631	CPUMCTX HyperCtxIgnored;
2632	if (uVersion < CPUM_SAVED_STATE_VERSION_XSAVE)
2633	{
2634	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2635	{
2636	X86FXSTATE Ign;
2637	SSMR3GetStructEx(pSSM, &Ign, sizeof(Ign), fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
2638	SSMR3GetStructEx(pSSM, &HyperCtxIgnored, sizeof(HyperCtxIgnored),
2639	fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
2640	}
2641	}
2642
2643	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
2644	{
2645	uint32_t cCpus;
2646	rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2647	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
2648	VERR_SSM_UNEXPECTED_DATA);
2649	}
2650	AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
2651	\|\| pVM->cCpus == 1,
2652	("cCpus=%u\n", pVM->cCpus),
2653	VERR_SSM_UNEXPECTED_DATA);
2654
2655	uint32_t cbMsrs = 0;
2656	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2657	{
2658	rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
2659	AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
2660	VERR_SSM_UNEXPECTED_DATA);
2661	AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
2662	VERR_SSM_UNEXPECTED_DATA);
2663	}
2664
2665	/*
2666	* Do the per-CPU restoring.
2667	*/
2668	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2669	{
2670	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2671	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
2672
2673	if (uVersion >= CPUM_SAVED_STATE_VERSION_XSAVE)
2674	{
2675	/*
2676	* The XSAVE saved state layout moved the hyper state down here.
2677	*/
2678	rc = SSMR3GetStructEx(pSSM, &HyperCtxIgnored, sizeof(HyperCtxIgnored), 0, g_aCpumCtxFields, NULL);
2679	AssertRCReturn(rc, rc);
2680
2681	/*
2682	* Start by restoring the CPUMCTX structure and the X86FXSAVE bits of the extended state.
2683	*/
2684	rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2685	rc = SSMR3GetStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87), 0, g_aCpumX87Fields, NULL);
2686	AssertRCReturn(rc, rc);
2687
2688	/* Check that the xsave/xrstor mask is valid (invalid results in #GP). */
2689	if (pGstCtx->fXStateMask != 0)
2690	{
2691	AssertLogRelMsgReturn(!(pGstCtx->fXStateMask & ~pVM->cpum.s.fXStateGuestMask),
2692	("fXStateMask=%#RX64 fXStateGuestMask=%#RX64\n",
2693	pGstCtx->fXStateMask, pVM->cpum.s.fXStateGuestMask),
2694	VERR_CPUM_INCOMPATIBLE_XSAVE_COMP_MASK);
2695	AssertLogRelMsgReturn(pGstCtx->fXStateMask & XSAVE_C_X87,
2696	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2697	AssertLogRelMsgReturn((pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
2698	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2699	AssertLogRelMsgReturn( (pGstCtx->fXStateMask & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
2700	\|\| (pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
2701	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
2702	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2703	}
2704
2705	/* Check that the XCR0 mask is valid (invalid results in #GP). */
2706	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87, ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XCR0);
2707	if (pGstCtx->aXcr[0] != XSAVE_C_X87)
2708	{
2709	AssertLogRelMsgReturn(!(pGstCtx->aXcr[0] & ~(pGstCtx->fXStateMask \| XSAVE_C_X87)),
2710	("xcr0=%#RX64 fXStateMask=%#RX64\n", pGstCtx->aXcr[0], pGstCtx->fXStateMask),
2711	VERR_CPUM_INVALID_XCR0);
2712	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87,
2713	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2714	AssertLogRelMsgReturn((pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
2715	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2716	AssertLogRelMsgReturn( (pGstCtx->aXcr[0] & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
2717	\|\| (pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
2718	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
2719	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2720	}
2721
2722	/* Check that the XCR1 is zero, as we don't implement it yet. */
2723	AssertLogRelMsgReturn(!pGstCtx->aXcr[1], ("xcr1=%#RX64\n", pGstCtx->aXcr[1]), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2724
2725	/*
2726	* Restore the individual extended state components we support.
2727	*/
2728	if (pGstCtx->fXStateMask != 0)
2729	{
2730	rc = SSMR3GetStructEx(pSSM, &pGstCtx->XState.Hdr, sizeof(pGstCtx->XState.Hdr),
2731	0, g_aCpumXSaveHdrFields, NULL);
2732	AssertRCReturn(rc, rc);
2733	AssertLogRelMsgReturn(!(pGstCtx->XState.Hdr.bmXState & ~pGstCtx->fXStateMask),
2734	("bmXState=%#RX64 fXStateMask=%#RX64\n",
2735	pGstCtx->XState.Hdr.bmXState, pGstCtx->fXStateMask),
2736	VERR_CPUM_INVALID_XSAVE_HDR);
2737	}
2738	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
2739	{
2740	PX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PX86XSAVEYMMHI);
2741	SSMR3GetStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2742	}
2743	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2744	{
2745	PX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PX86XSAVEBNDREGS);
2746	SSMR3GetStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2747	}
2748	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2749	{
2750	PX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PX86XSAVEBNDCFG);
2751	SSMR3GetStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2752	}
2753	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2754	{
2755	PX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PX86XSAVEZMMHI256);
2756	SSMR3GetStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2757	}
2758	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2759	{
2760	PX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PX86XSAVEZMM16HI);
2761	SSMR3GetStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2762	}
2763	if (uVersion >= CPUM_SAVED_STATE_VERSION_PAE_PDPES)
2764	{
2765	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[0].u);
2766	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[1].u);
2767	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[2].u);
2768	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[3].u);
2769	}
2770	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_SVM)
2771	{
2772	if (pVM->cpum.s.GuestFeatures.fSvm)
2773	{
2774	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uMsrHSavePa);
2775	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.svm.GCPhysVmcb);
2776	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uPrevPauseTick);
2777	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilter);
2778	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2779	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.svm.fInterceptEvents);
2780	SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState),
2781	0 /* fFlags /, g_aSvmHwvirtHostState, NULL / pvUser */);
2782	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.svm.Vmcb, sizeof(pGstCtx->hwvirt.svm.Vmcb));
2783	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.svm.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.svm.abMsrBitmap));
2784	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.svm.abIoBitmap[0], sizeof(pGstCtx->hwvirt.svm.abIoBitmap));
2785	SSMR3GetU32(pSSM, &pGstCtx->hwvirt.fLocalForcedActions);
2786	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.fGif);
2787	}
2788	}
2789	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_VMX)
2790	{
2791	if (pVM->cpum.s.GuestFeatures.fVmx)
2792	{
2793	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysVmxon);
2794	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysVmcs);
2795	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysShadowVmcs);
2796	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInVmxRootMode);
2797	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInVmxNonRootMode);
2798	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInterceptEvents);
2799	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fNmiUnblockingIret);
2800	SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.vmx.Vmcs, sizeof(pGstCtx->hwvirt.vmx.Vmcs),
2801	0, g_aVmxHwvirtVmcs, NULL);
2802	SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.vmx.ShadowVmcs, sizeof(pGstCtx->hwvirt.vmx.ShadowVmcs),
2803	0, g_aVmxHwvirtVmcs, NULL);
2804	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abVmreadBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmreadBitmap));
2805	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abVmwriteBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmwriteBitmap));
2806	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.aEntryMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aEntryMsrLoadArea));
2807	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrStoreArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrStoreArea));
2808	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrLoadArea));
2809	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abMsrBitmap));
2810	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abIoBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abIoBitmap));
2811	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uFirstPauseLoopTick);
2812	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uPrevPauseTick);
2813	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uEntryTick);
2814	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.vmx.offVirtApicWrite);
2815	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fVirtNmiBlocking);
2816	SSMR3Skip(pSSM, sizeof(uint64_t)); /* Unused - used to be IA32_FEATURE_CONTROL, see @bugref{10106}. */
2817	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Basic);
2818	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.PinCtls.u);
2819	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ProcCtls.u);
2820	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ProcCtls2.u);
2821	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ExitCtls.u);
2822	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.EntryCtls.u);
2823	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TruePinCtls.u);
2824	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueProcCtls.u);
2825	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueEntryCtls.u);
2826	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueExitCtls.u);
2827	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Misc);
2828	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed0);
2829	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed1);
2830	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed0);
2831	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed1);
2832	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64VmcsEnum);
2833	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64VmFunc);
2834	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64EptVpidCaps);
2835	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2)
2836	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64ProcCtls3);
2837	}
2838	}
2839	}
2840	else
2841	{
2842	/*
2843	* Pre XSAVE saved state.
2844	*/
2845	SSMR3GetStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87),
2846	fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
2847	SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
2848	}
2849
2850	/*
2851	* Restore a couple of flags and the MSRs.
2852	*/
2853	uint32_t fIgnoredUsedFlags = 0;
2854	rc = SSMR3GetU32(pSSM, &fIgnoredUsedFlags); /* we're recalc the two relevant flags after loading state. */
2855	AssertRCReturn(rc, rc);
2856	SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
2857
2858	rc = VINF_SUCCESS;
2859	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2860	rc = SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
2861	else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
2862	{
2863	SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
2864	rc = SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
2865	}
2866	AssertRCReturn(rc, rc);
2867
2868	/* REM and other may have cleared must-be-one fields in DR6 and
2869	DR7, fix these. */
2870	pGstCtx->dr[6] &= ~(X86_DR6_RAZ_MASK \| X86_DR6_MBZ_MASK);
2871	pGstCtx->dr[6] \|= X86_DR6_RA1_MASK;
2872	pGstCtx->dr[7] &= ~(X86_DR7_RAZ_MASK \| X86_DR7_MBZ_MASK);
2873	pGstCtx->dr[7] \|= X86_DR7_RA1_MASK;
2874	}
2875
2876	/* Older states does not have the internal selector register flags
2877	and valid selector value. Supply those. */
2878	if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2879	{
2880	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2881	{
2882	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2883	bool const fValid = true /!VM_IS_RAW_MODE_ENABLED(pVM)/
2884	\|\| ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2885	&& !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
2886	PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
2887	if (fValid)
2888	{
2889	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2890	{
2891	paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
2892	paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
2893	}
2894
2895	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2896	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2897	}
2898	else
2899	{
2900	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2901	{
2902	paSelReg[iSelReg].fFlags = 0;
2903	paSelReg[iSelReg].ValidSel = 0;
2904	}
2905
2906	/* This might not be 104% correct, but I think it's close
2907	enough for all practical purposes... (REM always loaded
2908	LDTR registers.) */
2909	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2910	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2911	}
2912	pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2913	pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
2914	}
2915	}
2916
2917	/* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
2918	if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2919	&& uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2920	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2921	{
2922	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2923	pVCpu->cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
2924	}
2925
2926	/*
2927	* A quick sanity check.
2928	*/
2929	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2930	{
2931	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2932	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2933	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2934	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2935	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2936	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2937	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2938	}
2939	}
2940
2941	pVM->cpum.s.fPendingRestore = false;
2942
2943	/*
2944	* Guest CPUIDs (and VMX MSR features).
2945	*/
2946	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2)
2947	{
2948	CPUMMSRS GuestMsrs;
2949	RT_ZERO(GuestMsrs);
2950
2951	CPUMFEATURES BaseFeatures;
2952	bool const fVmxGstFeat = pVM->cpum.s.GuestFeatures.fVmx;
2953	if (fVmxGstFeat)
2954	{
2955	/*
2956	* At this point the MSRs in the guest CPU-context are loaded with the guest VMX MSRs from the saved state.
2957	* However the VMX sub-features have not been exploded yet. So cache the base (host derived) VMX features
2958	* here so we can compare them for compatibility after exploding guest features.
2959	*/
2960	BaseFeatures = pVM->cpum.s.GuestFeatures;
2961
2962	/* Use the VMX MSR features from the saved state while exploding guest features. */
2963	GuestMsrs.hwvirt.vmx = pVM->apCpusR3[0]->cpum.s.Guest.hwvirt.vmx.Msrs;
2964	}
2965
2966	/* Load CPUID and explode guest features. */
2967	rc = cpumR3LoadCpuId(pVM, pSSM, uVersion, &GuestMsrs);
2968	if (fVmxGstFeat)
2969	{
2970	/*
2971	* Check if the exploded VMX features from the saved state are compatible with the host-derived features
2972	* we cached earlier (above). The is required if we use hardware-assisted nested-guest execution with
2973	* VMX features presented to the guest.
2974	*/
2975	bool const fIsCompat = cpumR3AreVmxCpuFeaturesCompatible(pVM, &BaseFeatures, &pVM->cpum.s.GuestFeatures);
2976	if (!fIsCompat)
2977	return VERR_CPUM_INVALID_HWVIRT_FEAT_COMBO;
2978	}
2979	return rc;
2980	}
2981	return cpumR3LoadCpuIdPre32(pVM, pSSM, uVersion);
2982	}
2983
2984
2985	/**
2986	* @callback_method_impl{FNSSMINTLOADDONE}
2987	*/
2988	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
2989	{
2990	if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
2991	return VINF_SUCCESS;
2992
2993	/* just check this since we can. / /* @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
2994	if (pVM->cpum.s.fPendingRestore)
2995	{
2996	LogRel(("CPUM: Missing state!\n"));
2997	return VERR_INTERNAL_ERROR_2;
2998	}
2999
3000	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
3001	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3002	{
3003	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3004
3005	/* Notify PGM of the NXE states in case they've changed. */
3006	PGMNotifyNxeChanged(pVCpu, RT_BOOL(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
3007
3008	/* During init. this is done in CPUMR3InitCompleted(). */
3009	if (fSupportsLongMode)
3010	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
3011
3012	/* Recalc the CPUM_USE_DEBUG_REGS_HYPER value. */
3013	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX);
3014	}
3015	return VINF_SUCCESS;
3016	}
3017
3018
3019	/**
3020	* Checks if the CPUM state restore is still pending.
3021	*
3022	* @returns true / false.
3023	* @param pVM The cross context VM structure.
3024	*/
3025	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
3026	{
3027	return pVM->cpum.s.fPendingRestore;
3028	}
3029
3030
3031	/**
3032	* Formats the EFLAGS value into mnemonics.
3033	*
3034	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
3035	* @param efl The EFLAGS value.
3036	*/
3037	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
3038	{
3039	/*
3040	* Format the flags.
3041	*/
3042	static const struct
3043	{
3044	const char pszSet; const char pszClear; uint32_t fFlag;
3045	} s_aFlags[] =
3046	{
3047	{ "vip",NULL, X86_EFL_VIP },
3048	{ "vif",NULL, X86_EFL_VIF },
3049	{ "ac", NULL, X86_EFL_AC },
3050	{ "vm", NULL, X86_EFL_VM },
3051	{ "rf", NULL, X86_EFL_RF },
3052	{ "nt", NULL, X86_EFL_NT },
3053	{ "ov", "nv", X86_EFL_OF },
3054	{ "dn", "up", X86_EFL_DF },
3055	{ "ei", "di", X86_EFL_IF },
3056	{ "tf", NULL, X86_EFL_TF },
3057	{ "nt", "pl", X86_EFL_SF },
3058	{ "nz", "zr", X86_EFL_ZF },
3059	{ "ac", "na", X86_EFL_AF },
3060	{ "po", "pe", X86_EFL_PF },
3061	{ "cy", "nc", X86_EFL_CF },
3062	};
3063	char *psz = pszEFlags;
3064	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
3065	{
3066	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
3067	if (pszAdd)
3068	{
3069	strcpy(psz, pszAdd);
3070	psz += strlen(pszAdd);
3071	*psz++ = ' ';
3072	}
3073	}
3074	psz[-1] = '\0';
3075	}
3076
3077
3078	/**
3079	* Formats a full register dump.
3080	*
3081	* @param pVM The cross context VM structure.
3082	* @param pCtx The context to format.
3083	* @param pCtxCore The context core to format.
3084	* @param pHlp Output functions.
3085	* @param enmType The dump type.
3086	* @param pszPrefix Register name prefix.
3087	*/
3088	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
3089	const char *pszPrefix)
3090	{
3091	NOREF(pVM);
3092
3093	/*
3094	* Format the EFLAGS.
3095	*/
3096	uint32_t efl = pCtxCore->eflags.u32;
3097	char szEFlags[80];
3098	cpumR3InfoFormatFlags(&szEFlags[0], efl);
3099
3100	/*
3101	* Format the registers.
3102	*/
3103	switch (enmType)
3104	{
3105	case CPUMDUMPTYPE_TERSE:
3106	if (CPUMIsGuestIn64BitCodeEx(pCtx))
3107	pHlp->pfnPrintf(pHlp,
3108	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3109	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3110	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3111	"%sr14=%016RX64 %sr15=%016RX64\n"
3112	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3113	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
3114	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3115	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3116	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3117	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3118	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3119	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
3120	else
3121	pHlp->pfnPrintf(pHlp,
3122	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3123	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3124	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
3125	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3126	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3127	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3128	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
3129	break;
3130
3131	case CPUMDUMPTYPE_DEFAULT:
3132	if (CPUMIsGuestIn64BitCodeEx(pCtx))
3133	pHlp->pfnPrintf(pHlp,
3134	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3135	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3136	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3137	"%sr14=%016RX64 %sr15=%016RX64\n"
3138	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3139	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
3140	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
3141	,
3142	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3143	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3144	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3145	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3146	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3147	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
3148	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3149	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
3150	else
3151	pHlp->pfnPrintf(pHlp,
3152	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3153	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3154	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
3155	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
3156	,
3157	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3158	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3159	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3160	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
3161	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3162	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
3163	break;
3164
3165	case CPUMDUMPTYPE_VERBOSE:
3166	if (CPUMIsGuestIn64BitCodeEx(pCtx))
3167	pHlp->pfnPrintf(pHlp,
3168	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3169	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3170	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3171	"%sr14=%016RX64 %sr15=%016RX64\n"
3172	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3173	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3174	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3175	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3176	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3177	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3178	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3179	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
3180	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
3181	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
3182	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
3183	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3184	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3185	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
3186	,
3187	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3188	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3189	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3190	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3191	pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
3192	pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
3193	pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
3194	pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
3195	pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
3196	pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
3197	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3198	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
3199	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
3200	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
3201	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
3202	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
3203	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3204	else
3205	pHlp->pfnPrintf(pHlp,
3206	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3207	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3208	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
3209	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
3210	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
3211	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
3212	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
3213	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
3214	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
3215	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3216	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3217	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
3218	,
3219	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3220	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3221	pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
3222	pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
3223	pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
3224	pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
3225	pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
3226	pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3227	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
3228	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
3229	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
3230	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3231
3232	pHlp->pfnPrintf(pHlp, "%sxcr=%016RX64 %sxcr1=%016RX64 %sxss=%016RX64 (fXStateMask=%016RX64)\n",
3233	pszPrefix, pCtx->aXcr[0], pszPrefix, pCtx->aXcr[1],
3234	pszPrefix, UINT64_C(0) /** @todo XSS */, pCtx->fXStateMask);
3235	{
3236	PX86FXSTATE pFpuCtx = &pCtx->XState.x87;
3237	pHlp->pfnPrintf(pHlp,
3238	"%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
3239	"%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
3240	,
3241	pszPrefix, pFpuCtx->FCW, pszPrefix, pFpuCtx->FSW, pszPrefix, pFpuCtx->FTW, pszPrefix, pFpuCtx->FOP,
3242	pszPrefix, pFpuCtx->MXCSR, pszPrefix, pFpuCtx->MXCSR_MASK,
3243	pszPrefix, pFpuCtx->FPUIP, pszPrefix, pFpuCtx->CS, pszPrefix, pFpuCtx->Rsrvd1,
3244	pszPrefix, pFpuCtx->FPUDP, pszPrefix, pFpuCtx->DS, pszPrefix, pFpuCtx->Rsrvd2
3245	);
3246	/*
3247	* The FSAVE style memory image contains ST(0)-ST(7) at increasing addresses,
3248	* not (FP)R0-7 as Intel SDM suggests.
3249	*/
3250	unsigned iShift = (pFpuCtx->FSW >> 11) & 7;
3251	for (unsigned iST = 0; iST < RT_ELEMENTS(pFpuCtx->aRegs); iST++)
3252	{
3253	unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pFpuCtx->aRegs);
3254	unsigned uTag = (pFpuCtx->FTW >> (2 * iFPR)) & 3;
3255	char chSign = pFpuCtx->aRegs[iST].au16[4] & 0x8000 ? '-' : '+';
3256	unsigned iInteger = (unsigned)(pFpuCtx->aRegs[iST].au64[0] >> 63);
3257	uint64_t u64Fraction = pFpuCtx->aRegs[iST].au64[0] & UINT64_C(0x7fffffffffffffff);
3258	int iExponent = pFpuCtx->aRegs[iST].au16[4] & 0x7fff;
3259	iExponent -= 16383; /* subtract bias */
3260	/** @todo This isn't entirenly correct and needs more work! */
3261	pHlp->pfnPrintf(pHlp,
3262	"%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu * 2 ^ %d (*)",
3263	pszPrefix, iST, pszPrefix, iFPR,
3264	pFpuCtx->aRegs[iST].au16[4], pFpuCtx->aRegs[iST].au32[1], pFpuCtx->aRegs[iST].au32[0],
3265	uTag, chSign, iInteger, u64Fraction, iExponent);
3266	if (pFpuCtx->aRegs[iST].au16[5] \|\| pFpuCtx->aRegs[iST].au16[6] \|\| pFpuCtx->aRegs[iST].au16[7])
3267	pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
3268	pFpuCtx->aRegs[iST].au16[5], pFpuCtx->aRegs[iST].au16[6], pFpuCtx->aRegs[iST].au16[7]);
3269	else
3270	pHlp->pfnPrintf(pHlp, "\n");
3271	}
3272
3273	/* XMM/YMM/ZMM registers. */
3274	if (pCtx->fXStateMask & XSAVE_C_YMM)
3275	{
3276	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
3277	if (!(pCtx->fXStateMask & XSAVE_C_ZMM_HI256))
3278	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3279	pHlp->pfnPrintf(pHlp, "%sYMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3280	pszPrefix, i, i < 10 ? " " : "",
3281	pYmmHiCtx->aYmmHi[i].au32[3],
3282	pYmmHiCtx->aYmmHi[i].au32[2],
3283	pYmmHiCtx->aYmmHi[i].au32[1],
3284	pYmmHiCtx->aYmmHi[i].au32[0],
3285	pFpuCtx->aXMM[i].au32[3],
3286	pFpuCtx->aXMM[i].au32[2],
3287	pFpuCtx->aXMM[i].au32[1],
3288	pFpuCtx->aXMM[i].au32[0]);
3289	else
3290	{
3291	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
3292	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3293	pHlp->pfnPrintf(pHlp,
3294	"%sZMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3295	pszPrefix, i, i < 10 ? " " : "",
3296	pZmmHi256->aHi256Regs[i].au32[7],
3297	pZmmHi256->aHi256Regs[i].au32[6],
3298	pZmmHi256->aHi256Regs[i].au32[5],
3299	pZmmHi256->aHi256Regs[i].au32[4],
3300	pZmmHi256->aHi256Regs[i].au32[3],
3301	pZmmHi256->aHi256Regs[i].au32[2],
3302	pZmmHi256->aHi256Regs[i].au32[1],
3303	pZmmHi256->aHi256Regs[i].au32[0],
3304	pYmmHiCtx->aYmmHi[i].au32[3],
3305	pYmmHiCtx->aYmmHi[i].au32[2],
3306	pYmmHiCtx->aYmmHi[i].au32[1],
3307	pYmmHiCtx->aYmmHi[i].au32[0],
3308	pFpuCtx->aXMM[i].au32[3],
3309	pFpuCtx->aXMM[i].au32[2],
3310	pFpuCtx->aXMM[i].au32[1],
3311	pFpuCtx->aXMM[i].au32[0]);
3312
3313	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
3314	for (unsigned i = 0; i < RT_ELEMENTS(pZmm16Hi->aRegs); i++)
3315	pHlp->pfnPrintf(pHlp,
3316	"%sZMM%u=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3317	pszPrefix, i + 16,
3318	pZmm16Hi->aRegs[i].au32[15],
3319	pZmm16Hi->aRegs[i].au32[14],
3320	pZmm16Hi->aRegs[i].au32[13],
3321	pZmm16Hi->aRegs[i].au32[12],
3322	pZmm16Hi->aRegs[i].au32[11],
3323	pZmm16Hi->aRegs[i].au32[10],
3324	pZmm16Hi->aRegs[i].au32[9],
3325	pZmm16Hi->aRegs[i].au32[8],
3326	pZmm16Hi->aRegs[i].au32[7],
3327	pZmm16Hi->aRegs[i].au32[6],
3328	pZmm16Hi->aRegs[i].au32[5],
3329	pZmm16Hi->aRegs[i].au32[4],
3330	pZmm16Hi->aRegs[i].au32[3],
3331	pZmm16Hi->aRegs[i].au32[2],
3332	pZmm16Hi->aRegs[i].au32[1],
3333	pZmm16Hi->aRegs[i].au32[0]);
3334	}
3335	}
3336	else
3337	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3338	pHlp->pfnPrintf(pHlp,
3339	i & 1
3340	? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
3341	: "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
3342	pszPrefix, i, i < 10 ? " " : "",
3343	pFpuCtx->aXMM[i].au32[3],
3344	pFpuCtx->aXMM[i].au32[2],
3345	pFpuCtx->aXMM[i].au32[1],
3346	pFpuCtx->aXMM[i].au32[0]);
3347
3348	if (pCtx->fXStateMask & XSAVE_C_OPMASK)
3349	{
3350	PCX86XSAVEOPMASK pOpMask = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_OPMASK_BIT, PCX86XSAVEOPMASK);
3351	for (unsigned i = 0; i < RT_ELEMENTS(pOpMask->aKRegs); i += 4)
3352	pHlp->pfnPrintf(pHlp, "%sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64\n",
3353	pszPrefix, i + 0, pOpMask->aKRegs[i + 0],
3354	pszPrefix, i + 1, pOpMask->aKRegs[i + 1],
3355	pszPrefix, i + 2, pOpMask->aKRegs[i + 2],
3356	pszPrefix, i + 3, pOpMask->aKRegs[i + 3]);
3357	}
3358
3359	if (pCtx->fXStateMask & XSAVE_C_BNDREGS)
3360	{
3361	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
3362	for (unsigned i = 0; i < RT_ELEMENTS(pBndRegs->aRegs); i += 2)
3363	pHlp->pfnPrintf(pHlp, "%sBNDREG%u=%016RX64/%016RX64 %sBNDREG%u=%016RX64/%016RX64\n",
3364	pszPrefix, i, pBndRegs->aRegs[i].uLowerBound, pBndRegs->aRegs[i].uUpperBound,
3365	pszPrefix, i + 1, pBndRegs->aRegs[i + 1].uLowerBound, pBndRegs->aRegs[i + 1].uUpperBound);
3366	}
3367
3368	if (pCtx->fXStateMask & XSAVE_C_BNDCSR)
3369	{
3370	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
3371	pHlp->pfnPrintf(pHlp, "%sBNDCFG.CONFIG=%016RX64 %sBNDCFG.STATUS=%016RX64\n",
3372	pszPrefix, pBndCfg->fConfig, pszPrefix, pBndCfg->fStatus);
3373	}
3374
3375	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->au32RsrvdRest); i++)
3376	if (pFpuCtx->au32RsrvdRest[i])
3377	pHlp->pfnPrintf(pHlp, "%sRsrvdRest[%u]=%RX32 (offset=%#x)\n",
3378	pszPrefix, i, pFpuCtx->au32RsrvdRest[i], RT_UOFFSETOF_DYN(X86FXSTATE, au32RsrvdRest[i]) );
3379	}
3380
3381	pHlp->pfnPrintf(pHlp,
3382	"%sEFER =%016RX64\n"
3383	"%sPAT =%016RX64\n"
3384	"%sSTAR =%016RX64\n"
3385	"%sCSTAR =%016RX64\n"
3386	"%sLSTAR =%016RX64\n"
3387	"%sSFMASK =%016RX64\n"
3388	"%sKERNELGSBASE =%016RX64\n",
3389	pszPrefix, pCtx->msrEFER,
3390	pszPrefix, pCtx->msrPAT,
3391	pszPrefix, pCtx->msrSTAR,
3392	pszPrefix, pCtx->msrCSTAR,
3393	pszPrefix, pCtx->msrLSTAR,
3394	pszPrefix, pCtx->msrSFMASK,
3395	pszPrefix, pCtx->msrKERNELGSBASE);
3396
3397	if (CPUMIsGuestInPAEModeEx(pCtx))
3398	for (unsigned i = 0; i < RT_ELEMENTS(pCtx->aPaePdpes); i++)
3399	pHlp->pfnPrintf(pHlp, "%sPAE PDPTE %u =%016RX64\n", pszPrefix, i, pCtx->aPaePdpes[i]);
3400	break;
3401	}
3402	}
3403
3404
3405	/**
3406	* Display all cpu states and any other cpum info.
3407	*
3408	* @param pVM The cross context VM structure.
3409	* @param pHlp The info helper functions.
3410	* @param pszArgs Arguments, ignored.
3411	*/
3412	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3413	{
3414	cpumR3InfoGuest(pVM, pHlp, pszArgs);
3415	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
3416	cpumR3InfoGuestHwvirt(pVM, pHlp, pszArgs);
3417	cpumR3InfoHyper(pVM, pHlp, pszArgs);
3418	cpumR3InfoHost(pVM, pHlp, pszArgs);
3419	}
3420
3421
3422	/**
3423	* Parses the info argument.
3424	*
3425	* The argument starts with 'verbose', 'terse' or 'default' and then
3426	* continues with the comment string.
3427	*
3428	* @param pszArgs The pointer to the argument string.
3429	* @param penmType Where to store the dump type request.
3430	* @param ppszComment Where to store the pointer to the comment string.
3431	*/
3432	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
3433	{
3434	if (!pszArgs)
3435	{
3436	*penmType = CPUMDUMPTYPE_DEFAULT;
3437	*ppszComment = "";
3438	}
3439	else
3440	{
3441	if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
3442	{
3443	pszArgs += 7;
3444	*penmType = CPUMDUMPTYPE_VERBOSE;
3445	}
3446	else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
3447	{
3448	pszArgs += 5;
3449	*penmType = CPUMDUMPTYPE_TERSE;
3450	}
3451	else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
3452	{
3453	pszArgs += 7;
3454	*penmType = CPUMDUMPTYPE_DEFAULT;
3455	}
3456	else
3457	*penmType = CPUMDUMPTYPE_DEFAULT;
3458	*ppszComment = RTStrStripL(pszArgs);
3459	}
3460	}
3461
3462
3463	/**
3464	* Display the guest cpu state.
3465	*
3466	* @param pVM The cross context VM structure.
3467	* @param pHlp The info helper functions.
3468	* @param pszArgs Arguments.
3469	*/
3470	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3471	{
3472	CPUMDUMPTYPE enmType;
3473	const char *pszComment;
3474	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3475
3476	PVMCPU pVCpu = VMMGetCpu(pVM);
3477	if (!pVCpu)
3478	pVCpu = pVM->apCpusR3[0];
3479
3480	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
3481
3482	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3483	cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
3484	}
3485
3486
3487	/**
3488	* Displays an SVM VMCB control area.
3489	*
3490	* @param pHlp The info helper functions.
3491	* @param pVmcbCtrl Pointer to a SVM VMCB controls area.
3492	* @param pszPrefix Caller specified string prefix.
3493	*/
3494	static void cpumR3InfoSvmVmcbCtrl(PCDBGFINFOHLP pHlp, PCSVMVMCBCTRL pVmcbCtrl, const char *pszPrefix)
3495	{
3496	AssertReturnVoid(pHlp);
3497	AssertReturnVoid(pVmcbCtrl);
3498
3499	pHlp->pfnPrintf(pHlp, "%sCRX-read intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdCRx);
3500	pHlp->pfnPrintf(pHlp, "%sCRX-write intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrCRx);
3501	pHlp->pfnPrintf(pHlp, "%sDRX-read intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdDRx);
3502	pHlp->pfnPrintf(pHlp, "%sDRX-write intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrDRx);
3503	pHlp->pfnPrintf(pHlp, "%sException intercepts = %#RX32\n", pszPrefix, pVmcbCtrl->u32InterceptXcpt);
3504	pHlp->pfnPrintf(pHlp, "%sControl intercepts = %#RX64\n", pszPrefix, pVmcbCtrl->u64InterceptCtrl);
3505	pHlp->pfnPrintf(pHlp, "%sPause-filter threshold = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterThreshold);
3506	pHlp->pfnPrintf(pHlp, "%sPause-filter count = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterCount);
3507	pHlp->pfnPrintf(pHlp, "%sIOPM bitmap physaddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64IOPMPhysAddr);
3508	pHlp->pfnPrintf(pHlp, "%sMSRPM bitmap physaddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64MSRPMPhysAddr);
3509	pHlp->pfnPrintf(pHlp, "%sTSC offset = %#RX64\n", pszPrefix, pVmcbCtrl->u64TSCOffset);
3510	pHlp->pfnPrintf(pHlp, "%sTLB Control\n", pszPrefix);
3511	pHlp->pfnPrintf(pHlp, " %sASID = %#RX32\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u32ASID);
3512	pHlp->pfnPrintf(pHlp, " %sTLB-flush type = %u\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u8TLBFlush);
3513	pHlp->pfnPrintf(pHlp, "%sInterrupt Control\n", pszPrefix);
3514	pHlp->pfnPrintf(pHlp, " %sVTPR = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VTPR, pVmcbCtrl->IntCtrl.n.u8VTPR);
3515	pHlp->pfnPrintf(pHlp, " %sVIRQ (Pending) = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIrqPending);
3516	pHlp->pfnPrintf(pHlp, " %sVINTR vector = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VIntrVector);
3517	pHlp->pfnPrintf(pHlp, " %sVGIF = %u\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGif);
3518	pHlp->pfnPrintf(pHlp, " %sVINTR priority = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u4VIntrPrio);
3519	pHlp->pfnPrintf(pHlp, " %sIgnore TPR = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1IgnoreTPR);
3520	pHlp->pfnPrintf(pHlp, " %sVINTR masking = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIntrMasking);
3521	pHlp->pfnPrintf(pHlp, " %sVGIF enable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGifEnable);
3522	pHlp->pfnPrintf(pHlp, " %sAVIC enable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1AvicEnable);
3523	pHlp->pfnPrintf(pHlp, "%sInterrupt Shadow\n", pszPrefix);
3524	pHlp->pfnPrintf(pHlp, " %sInterrupt shadow = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1IntShadow);
3525	pHlp->pfnPrintf(pHlp, " %sGuest-interrupt Mask = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1GuestIntMask);
3526	pHlp->pfnPrintf(pHlp, "%sExit Code = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitCode);
3527	pHlp->pfnPrintf(pHlp, "%sEXITINFO1 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo1);
3528	pHlp->pfnPrintf(pHlp, "%sEXITINFO2 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo2);
3529	pHlp->pfnPrintf(pHlp, "%sExit Interrupt Info\n", pszPrefix);
3530	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1Valid);
3531	pHlp->pfnPrintf(pHlp, " %sVector = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u8Vector, pVmcbCtrl->ExitIntInfo.n.u8Vector);
3532	pHlp->pfnPrintf(pHlp, " %sType = %u\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u3Type);
3533	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1ErrorCodeValid);
3534	pHlp->pfnPrintf(pHlp, " %sError-code = %#RX32\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u32ErrorCode);
3535	pHlp->pfnPrintf(pHlp, "%sNested paging and SEV\n", pszPrefix);
3536	pHlp->pfnPrintf(pHlp, " %sNested paging = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging);
3537	pHlp->pfnPrintf(pHlp, " %sSEV (Secure Encrypted VM) = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1Sev);
3538	pHlp->pfnPrintf(pHlp, " %sSEV-ES (Encrypted State) = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1SevEs);
3539	pHlp->pfnPrintf(pHlp, "%sEvent Inject\n", pszPrefix);
3540	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1Valid);
3541	pHlp->pfnPrintf(pHlp, " %sVector = %#RX32 (%u)\n", pszPrefix, pVmcbCtrl->EventInject.n.u8Vector, pVmcbCtrl->EventInject.n.u8Vector);
3542	pHlp->pfnPrintf(pHlp, " %sType = %u\n", pszPrefix, pVmcbCtrl->EventInject.n.u3Type);
3543	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1ErrorCodeValid);
3544	pHlp->pfnPrintf(pHlp, " %sError-code = %#RX32\n", pszPrefix, pVmcbCtrl->EventInject.n.u32ErrorCode);
3545	pHlp->pfnPrintf(pHlp, "%sNested-paging CR3 = %#RX64\n", pszPrefix, pVmcbCtrl->u64NestedPagingCR3);
3546	pHlp->pfnPrintf(pHlp, "%sLBR Virtualization\n", pszPrefix);
3547	pHlp->pfnPrintf(pHlp, " %sLBR virt = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1LbrVirt);
3548	pHlp->pfnPrintf(pHlp, " %sVirt. VMSAVE/VMLOAD = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1VirtVmsaveVmload);
3549	pHlp->pfnPrintf(pHlp, "%sVMCB Clean Bits = %#RX32\n", pszPrefix, pVmcbCtrl->u32VmcbCleanBits);
3550	pHlp->pfnPrintf(pHlp, "%sNext-RIP = %#RX64\n", pszPrefix, pVmcbCtrl->u64NextRIP);
3551	pHlp->pfnPrintf(pHlp, "%sInstruction bytes fetched = %u\n", pszPrefix, pVmcbCtrl->cbInstrFetched);
3552	pHlp->pfnPrintf(pHlp, "%sInstruction bytes = %.*Rhxs\n", pszPrefix, sizeof(pVmcbCtrl->abInstr), pVmcbCtrl->abInstr);
3553	pHlp->pfnPrintf(pHlp, "%sAVIC\n", pszPrefix);
3554	pHlp->pfnPrintf(pHlp, " %sBar addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBar.n.u40Addr);
3555	pHlp->pfnPrintf(pHlp, " %sBacking page addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBackingPagePtr.n.u40Addr);
3556	pHlp->pfnPrintf(pHlp, " %sLogical table addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicLogicalTablePtr.n.u40Addr);
3557	pHlp->pfnPrintf(pHlp, " %sPhysical table addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u40Addr);
3558	pHlp->pfnPrintf(pHlp, " %sLast guest core Id = %u\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u8LastGuestCoreId);
3559	}
3560
3561
3562	/**
3563	* Helper for dumping the SVM VMCB selector registers.
3564	*
3565	* @param pHlp The info helper functions.
3566	* @param pSel Pointer to the SVM selector register.
3567	* @param pszName Name of the selector.
3568	* @param pszPrefix Caller specified string prefix.
3569	*/
3570	DECLINLINE(void) cpumR3InfoSvmVmcbSelReg(PCDBGFINFOHLP pHlp, PCSVMSELREG pSel, const char pszName, const char pszPrefix)
3571	{
3572	/* The string width of 4 used below is to handle 'LDTR'. Change later if longer register names are used. */
3573	pHlp->pfnPrintf(pHlp, "%s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", pszPrefix,
3574	pszName, pSel->u16Sel, pSel->u64Base, pSel->u32Limit, pSel->u16Attr);
3575	}
3576
3577
3578	/**
3579	* Helper for dumping the SVM VMCB GDTR/IDTR registers.
3580	*
3581	* @param pHlp The info helper functions.
3582	* @param pXdtr Pointer to the descriptor table register.
3583	* @param pszName Name of the descriptor table register.
3584	* @param pszPrefix Caller specified string prefix.
3585	*/
3586	DECLINLINE(void) cpumR3InfoSvmVmcbXdtr(PCDBGFINFOHLP pHlp, PCSVMXDTR pXdtr, const char pszName, const char pszPrefix)
3587	{
3588	/* The string width of 4 used below is to cover 'GDTR', 'IDTR'. Change later if longer register names are used. */
3589	pHlp->pfnPrintf(pHlp, "%s%-4s = %016RX64:%04x\n", pszPrefix, pszName, pXdtr->u64Base, pXdtr->u32Limit);
3590	}
3591
3592
3593	/**
3594	* Displays an SVM VMCB state-save area.
3595	*
3596	* @param pHlp The info helper functions.
3597	* @param pVmcbStateSave Pointer to a SVM VMCB controls area.
3598	* @param pszPrefix Caller specified string prefix.
3599	*/
3600	static void cpumR3InfoSvmVmcbStateSave(PCDBGFINFOHLP pHlp, PCSVMVMCBSTATESAVE pVmcbStateSave, const char *pszPrefix)
3601	{
3602	AssertReturnVoid(pHlp);
3603	AssertReturnVoid(pVmcbStateSave);
3604
3605	char szEFlags[80];
3606	cpumR3InfoFormatFlags(&szEFlags[0], pVmcbStateSave->u64RFlags);
3607
3608	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->CS, "CS", pszPrefix);
3609	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->SS, "SS", pszPrefix);
3610	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->ES, "ES", pszPrefix);
3611	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->DS, "DS", pszPrefix);
3612	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->FS, "FS", pszPrefix);
3613	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->GS, "GS", pszPrefix);
3614	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->LDTR, "LDTR", pszPrefix);
3615	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->TR, "TR", pszPrefix);
3616	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->GDTR, "GDTR", pszPrefix);
3617	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->IDTR, "IDTR", pszPrefix);
3618	pHlp->pfnPrintf(pHlp, "%sCPL = %u\n", pszPrefix, pVmcbStateSave->u8CPL);
3619	pHlp->pfnPrintf(pHlp, "%sEFER = %#RX64\n", pszPrefix, pVmcbStateSave->u64EFER);
3620	pHlp->pfnPrintf(pHlp, "%sCR4 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR4);
3621	pHlp->pfnPrintf(pHlp, "%sCR3 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR3);
3622	pHlp->pfnPrintf(pHlp, "%sCR0 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR0);
3623	pHlp->pfnPrintf(pHlp, "%sDR7 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR7);
3624	pHlp->pfnPrintf(pHlp, "%sDR6 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR6);
3625	pHlp->pfnPrintf(pHlp, "%sRFLAGS = %#RX64 %31s\n", pszPrefix, pVmcbStateSave->u64RFlags, szEFlags);
3626	pHlp->pfnPrintf(pHlp, "%sRIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RIP);
3627	pHlp->pfnPrintf(pHlp, "%sRSP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RSP);
3628	pHlp->pfnPrintf(pHlp, "%sRAX = %#RX64\n", pszPrefix, pVmcbStateSave->u64RAX);
3629	pHlp->pfnPrintf(pHlp, "%sSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64STAR);
3630	pHlp->pfnPrintf(pHlp, "%sLSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64LSTAR);
3631	pHlp->pfnPrintf(pHlp, "%sCSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64CSTAR);
3632	pHlp->pfnPrintf(pHlp, "%sSFMASK = %#RX64\n", pszPrefix, pVmcbStateSave->u64SFMASK);
3633	pHlp->pfnPrintf(pHlp, "%sKERNELGSBASE = %#RX64\n", pszPrefix, pVmcbStateSave->u64KernelGSBase);
3634	pHlp->pfnPrintf(pHlp, "%sSysEnter CS = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterCS);
3635	pHlp->pfnPrintf(pHlp, "%sSysEnter EIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterEIP);
3636	pHlp->pfnPrintf(pHlp, "%sSysEnter ESP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterESP);
3637	pHlp->pfnPrintf(pHlp, "%sCR2 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR2);
3638	pHlp->pfnPrintf(pHlp, "%sPAT = %#RX64\n", pszPrefix, pVmcbStateSave->u64PAT);
3639	pHlp->pfnPrintf(pHlp, "%sDBGCTL = %#RX64\n", pszPrefix, pVmcbStateSave->u64DBGCTL);
3640	pHlp->pfnPrintf(pHlp, "%sBR_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_FROM);
3641	pHlp->pfnPrintf(pHlp, "%sBR_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_TO);
3642	pHlp->pfnPrintf(pHlp, "%sLASTXCPT_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPFROM);
3643	pHlp->pfnPrintf(pHlp, "%sLASTXCPT_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPTO);
3644	}
3645
3646
3647	/**
3648	* Displays a virtual-VMCS.
3649	*
3650	* @param pVCpu The cross context virtual CPU structure.
3651	* @param pHlp The info helper functions.
3652	* @param pVmcs Pointer to a virtual VMCS.
3653	* @param pszPrefix Caller specified string prefix.
3654	*/
3655	static void cpumR3InfoVmxVmcs(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, PCVMXVVMCS pVmcs, const char *pszPrefix)
3656	{
3657	AssertReturnVoid(pHlp);
3658	AssertReturnVoid(pVmcs);
3659
3660	/* The string width of -4 used in the macros below to cover 'LDTR', 'GDTR', 'IDTR. */
3661	#define CPUMVMX_DUMP_HOST_XDTR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3662	do { \
3663	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {base=%016RX64}\n", \
3664	(a_pszPrefix), (a_SegName), (a_pVmcs)->u64Host##a_Seg##Base.u); \
3665	} while (0)
3666
3667	#define CPUMVMX_DUMP_HOST_FS_GS_TR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3668	do { \
3669	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {%04x base=%016RX64}\n", \
3670	(a_pszPrefix), (a_SegName), (a_pVmcs)->Host##a_Seg, (a_pVmcs)->u64Host##a_Seg##Base.u); \
3671	} while (0)
3672
3673	#define CPUMVMX_DUMP_GUEST_SEGREG(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3674	do { \
3675	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", \
3676	(a_pszPrefix), (a_SegName), (a_pVmcs)->Guest##a_Seg, (a_pVmcs)->u64Guest##a_Seg##Base.u, \
3677	(a_pVmcs)->u32Guest##a_Seg##Limit, (a_pVmcs)->u32Guest##a_Seg##Attr); \
3678	} while (0)
3679
3680	#define CPUMVMX_DUMP_GUEST_XDTR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3681	do { \
3682	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {base=%016RX64 limit=%08x}\n", \
3683	(a_pszPrefix), (a_SegName), (a_pVmcs)->u64Guest##a_Seg##Base.u, (a_pVmcs)->u32Guest##a_Seg##Limit); \
3684	} while (0)
3685
3686	/* Header. */
3687	{
3688	pHlp->pfnPrintf(pHlp, "%sHeader:\n", pszPrefix);
3689	pHlp->pfnPrintf(pHlp, " %sVMCS revision id = %#RX32\n", pszPrefix, pVmcs->u32VmcsRevId);
3690	pHlp->pfnPrintf(pHlp, " %sVMX-abort id = %#RX32 (%s)\n", pszPrefix, pVmcs->enmVmxAbort, VMXGetAbortDesc(pVmcs->enmVmxAbort));
3691	pHlp->pfnPrintf(pHlp, " %sVMCS state = %#x (%s)\n", pszPrefix, pVmcs->fVmcsState, VMXGetVmcsStateDesc(pVmcs->fVmcsState));
3692	}
3693
3694	/* Control fields. */
3695	{
3696	/* 16-bit. */
3697	pHlp->pfnPrintf(pHlp, "%sControl:\n", pszPrefix);
3698	pHlp->pfnPrintf(pHlp, " %sVPID = %#RX16\n", pszPrefix, pVmcs->u16Vpid);
3699	pHlp->pfnPrintf(pHlp, " %sPosted intr notify vector = %#RX16\n", pszPrefix, pVmcs->u16PostIntNotifyVector);
3700	pHlp->pfnPrintf(pHlp, " %sEPTP index = %#RX16\n", pszPrefix, pVmcs->u16EptpIndex);
3701
3702	/* 32-bit. */
3703	pHlp->pfnPrintf(pHlp, " %sPin ctls = %#RX32\n", pszPrefix, pVmcs->u32PinCtls);
3704	pHlp->pfnPrintf(pHlp, " %sProcessor ctls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls);
3705	pHlp->pfnPrintf(pHlp, " %sSecondary processor ctls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls2);
3706	pHlp->pfnPrintf(pHlp, " %sVM-exit ctls = %#RX32\n", pszPrefix, pVmcs->u32ExitCtls);
3707	pHlp->pfnPrintf(pHlp, " %sVM-entry ctls = %#RX32\n", pszPrefix, pVmcs->u32EntryCtls);
3708	pHlp->pfnPrintf(pHlp, " %sException bitmap = %#RX32\n", pszPrefix, pVmcs->u32XcptBitmap);
3709	pHlp->pfnPrintf(pHlp, " %sPage-fault mask = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMask);
3710	pHlp->pfnPrintf(pHlp, " %sPage-fault match = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMatch);
3711	pHlp->pfnPrintf(pHlp, " %sCR3-target count = %RU32\n", pszPrefix, pVmcs->u32Cr3TargetCount);
3712	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR store count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrStoreCount);
3713	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR load count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrLoadCount);
3714	pHlp->pfnPrintf(pHlp, " %sVM-entry MSR load count = %RU32\n", pszPrefix, pVmcs->u32EntryMsrLoadCount);
3715	pHlp->pfnPrintf(pHlp, " %sVM-entry interruption info = %#RX32\n", pszPrefix, pVmcs->u32EntryIntInfo);
3716	{
3717	uint32_t const fInfo = pVmcs->u32EntryIntInfo;
3718	uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(fInfo);
3719	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_VALID(fInfo));
3720	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetEntryIntInfoTypeDesc(uType));
3721	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_ENTRY_INT_INFO_VECTOR(fInfo));
3722	pHlp->pfnPrintf(pHlp, " %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo));
3723	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(fInfo));
3724	}
3725	pHlp->pfnPrintf(pHlp, " %sVM-entry xcpt error-code = %#RX32\n", pszPrefix, pVmcs->u32EntryXcptErrCode);
3726	pHlp->pfnPrintf(pHlp, " %sVM-entry instr length = %u byte(s)\n", pszPrefix, pVmcs->u32EntryInstrLen);
3727	pHlp->pfnPrintf(pHlp, " %sTPR threshold = %#RX32\n", pszPrefix, pVmcs->u32TprThreshold);
3728	pHlp->pfnPrintf(pHlp, " %sPLE gap = %#RX32\n", pszPrefix, pVmcs->u32PleGap);
3729	pHlp->pfnPrintf(pHlp, " %sPLE window = %#RX32\n", pszPrefix, pVmcs->u32PleWindow);
3730
3731	/* 64-bit. */
3732	pHlp->pfnPrintf(pHlp, " %sIO-bitmap A addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapA.u);
3733	pHlp->pfnPrintf(pHlp, " %sIO-bitmap B addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapB.u);
3734	pHlp->pfnPrintf(pHlp, " %sMSR-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrMsrBitmap.u);
3735	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR store addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrStore.u);
3736	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrLoad.u);
3737	pHlp->pfnPrintf(pHlp, " %sVM-entry MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEntryMsrLoad.u);
3738	pHlp->pfnPrintf(pHlp, " %sExecutive VMCS ptr = %#RX64\n", pszPrefix, pVmcs->u64ExecVmcsPtr.u);
3739	pHlp->pfnPrintf(pHlp, " %sPML addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPml.u);
3740	pHlp->pfnPrintf(pHlp, " %sTSC offset = %#RX64\n", pszPrefix, pVmcs->u64TscOffset.u);
3741	pHlp->pfnPrintf(pHlp, " %sVirtual-APIC addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVirtApic.u);
3742	pHlp->pfnPrintf(pHlp, " %sAPIC-access addr = %#RX64\n", pszPrefix, pVmcs->u64AddrApicAccess.u);
3743	pHlp->pfnPrintf(pHlp, " %sPosted-intr desc addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPostedIntDesc.u);
3744	pHlp->pfnPrintf(pHlp, " %sVM-functions control = %#RX64\n", pszPrefix, pVmcs->u64VmFuncCtls.u);
3745	pHlp->pfnPrintf(pHlp, " %sEPTP ptr = %#RX64\n", pszPrefix, pVmcs->u64EptPtr.u);
3746	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 0 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap0.u);
3747	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 1 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap1.u);
3748	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 2 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap2.u);
3749	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 3 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap3.u);
3750	pHlp->pfnPrintf(pHlp, " %sEPTP-list addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEptpList.u);
3751	pHlp->pfnPrintf(pHlp, " %sVMREAD-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmreadBitmap.u);
3752	pHlp->pfnPrintf(pHlp, " %sVMWRITE-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmwriteBitmap.u);
3753	pHlp->pfnPrintf(pHlp, " %sVirt-Xcpt info addr = %#RX64\n", pszPrefix, pVmcs->u64AddrXcptVeInfo.u);
3754	pHlp->pfnPrintf(pHlp, " %sXSS-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64XssExitBitmap.u);
3755	pHlp->pfnPrintf(pHlp, " %sENCLS-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64EnclsExitBitmap.u);
3756	pHlp->pfnPrintf(pHlp, " %sSPP-table ptr = %#RX64\n", pszPrefix, pVmcs->u64SppTablePtr.u);
3757	pHlp->pfnPrintf(pHlp, " %sTSC multiplier = %#RX64\n", pszPrefix, pVmcs->u64TscMultiplier.u);
3758	pHlp->pfnPrintf(pHlp, " %sTertiary processor ctls = %#RX64\n", pszPrefix, pVmcs->u64ProcCtls3.u);
3759	pHlp->pfnPrintf(pHlp, " %sENCLV-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64EnclvExitBitmap.u);
3760
3761	/* Natural width. */
3762	pHlp->pfnPrintf(pHlp, " %sCR0 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr0Mask.u);
3763	pHlp->pfnPrintf(pHlp, " %sCR4 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr4Mask.u);
3764	pHlp->pfnPrintf(pHlp, " %sCR0 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr0ReadShadow.u);
3765	pHlp->pfnPrintf(pHlp, " %sCR4 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr4ReadShadow.u);
3766	pHlp->pfnPrintf(pHlp, " %sCR3-target 0 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target0.u);
3767	pHlp->pfnPrintf(pHlp, " %sCR3-target 1 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target1.u);
3768	pHlp->pfnPrintf(pHlp, " %sCR3-target 2 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target2.u);
3769	pHlp->pfnPrintf(pHlp, " %sCR3-target 3 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target3.u);
3770	}
3771
3772	/* Guest state. */
3773	{
3774	char szEFlags[80];
3775	cpumR3InfoFormatFlags(&szEFlags[0], pVmcs->u64GuestRFlags.u);
3776	pHlp->pfnPrintf(pHlp, "%sGuest state:\n", pszPrefix);
3777
3778	/* 16-bit. */
3779	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Cs, "CS", pszPrefix);
3780	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ss, "SS", pszPrefix);
3781	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Es, "ES", pszPrefix);
3782	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ds, "DS", pszPrefix);
3783	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Fs, "FS", pszPrefix);
3784	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Gs, "GS", pszPrefix);
3785	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ldtr, "LDTR", pszPrefix);
3786	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Tr, "TR", pszPrefix);
3787	CPUMVMX_DUMP_GUEST_XDTR(pHlp, pVmcs, Gdtr, "GDTR", pszPrefix);
3788	CPUMVMX_DUMP_GUEST_XDTR(pHlp, pVmcs, Idtr, "IDTR", pszPrefix);
3789	pHlp->pfnPrintf(pHlp, " %sInterrupt status = %#RX16\n", pszPrefix, pVmcs->u16GuestIntStatus);
3790	pHlp->pfnPrintf(pHlp, " %sPML index = %#RX16\n", pszPrefix, pVmcs->u16PmlIndex);
3791
3792	/* 32-bit. */
3793	pHlp->pfnPrintf(pHlp, " %sInterruptibility state = %#RX32\n", pszPrefix, pVmcs->u32GuestIntrState);
3794	pHlp->pfnPrintf(pHlp, " %sActivity state = %#RX32\n", pszPrefix, pVmcs->u32GuestActivityState);
3795	pHlp->pfnPrintf(pHlp, " %sSMBASE = %#RX32\n", pszPrefix, pVmcs->u32GuestSmBase);
3796	pHlp->pfnPrintf(pHlp, " %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32GuestSysenterCS);
3797	pHlp->pfnPrintf(pHlp, " %sVMX-preemption timer value = %#RX32\n", pszPrefix, pVmcs->u32PreemptTimer);
3798
3799	/* 64-bit. */
3800	pHlp->pfnPrintf(pHlp, " %sVMCS link ptr = %#RX64\n", pszPrefix, pVmcs->u64VmcsLinkPtr.u);
3801	pHlp->pfnPrintf(pHlp, " %sDBGCTL = %#RX64\n", pszPrefix, pVmcs->u64GuestDebugCtlMsr.u);
3802	pHlp->pfnPrintf(pHlp, " %sPAT = %#RX64\n", pszPrefix, pVmcs->u64GuestPatMsr.u);
3803	pHlp->pfnPrintf(pHlp, " %sEFER = %#RX64\n", pszPrefix, pVmcs->u64GuestEferMsr.u);
3804	pHlp->pfnPrintf(pHlp, " %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64GuestPerfGlobalCtlMsr.u);
3805	pHlp->pfnPrintf(pHlp, " %sPDPTE 0 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte0.u);
3806	pHlp->pfnPrintf(pHlp, " %sPDPTE 1 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte1.u);
3807	pHlp->pfnPrintf(pHlp, " %sPDPTE 2 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte2.u);
3808	pHlp->pfnPrintf(pHlp, " %sPDPTE 3 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte3.u);
3809	pHlp->pfnPrintf(pHlp, " %sBNDCFGS = %#RX64\n", pszPrefix, pVmcs->u64GuestBndcfgsMsr.u);
3810	pHlp->pfnPrintf(pHlp, " %sRTIT_CTL = %#RX64\n", pszPrefix, pVmcs->u64GuestRtitCtlMsr.u);
3811	pHlp->pfnPrintf(pHlp, " %sPKRS = %#RX64\n", pszPrefix, pVmcs->u64GuestPkrsMsr.u);
3812
3813	/* Natural width. */
3814	pHlp->pfnPrintf(pHlp, " %sCR0 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr0.u);
3815	pHlp->pfnPrintf(pHlp, " %sCR3 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr3.u);
3816	pHlp->pfnPrintf(pHlp, " %sCR4 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr4.u);
3817	pHlp->pfnPrintf(pHlp, " %sDR7 = %#RX64\n", pszPrefix, pVmcs->u64GuestDr7.u);
3818	pHlp->pfnPrintf(pHlp, " %sRSP = %#RX64\n", pszPrefix, pVmcs->u64GuestRsp.u);
3819	pHlp->pfnPrintf(pHlp, " %sRIP = %#RX64\n", pszPrefix, pVmcs->u64GuestRip.u);
3820	pHlp->pfnPrintf(pHlp, " %sRFLAGS = %#RX64 %31s\n",pszPrefix, pVmcs->u64GuestRFlags.u, szEFlags);
3821	pHlp->pfnPrintf(pHlp, " %sPending debug xcpts = %#RX64\n", pszPrefix, pVmcs->u64GuestPendingDbgXcpts.u);
3822	pHlp->pfnPrintf(pHlp, " %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEsp.u);
3823	pHlp->pfnPrintf(pHlp, " %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEip.u);
3824	pHlp->pfnPrintf(pHlp, " %sS_CET = %#RX64\n", pszPrefix, pVmcs->u64GuestSCetMsr.u);
3825	pHlp->pfnPrintf(pHlp, " %sSSP = %#RX64\n", pszPrefix, pVmcs->u64GuestSsp.u);
3826	pHlp->pfnPrintf(pHlp, " %sINTERRUPT_SSP_TABLE_ADDR = %#RX64\n", pszPrefix, pVmcs->u64GuestIntrSspTableAddrMsr.u);
3827	}
3828
3829	/* Host state. */
3830	{
3831	pHlp->pfnPrintf(pHlp, "%sHost state:\n", pszPrefix);
3832
3833	/* 16-bit. */
3834	pHlp->pfnPrintf(pHlp, " %sCS = %#RX16\n", pszPrefix, pVmcs->HostCs);
3835	pHlp->pfnPrintf(pHlp, " %sSS = %#RX16\n", pszPrefix, pVmcs->HostSs);
3836	pHlp->pfnPrintf(pHlp, " %sDS = %#RX16\n", pszPrefix, pVmcs->HostDs);
3837	pHlp->pfnPrintf(pHlp, " %sES = %#RX16\n", pszPrefix, pVmcs->HostEs);
3838	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Fs, "FS", pszPrefix);
3839	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Gs, "GS", pszPrefix);
3840	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Tr, "TR", pszPrefix);
3841	CPUMVMX_DUMP_HOST_XDTR(pHlp, pVmcs, Gdtr, "GDTR", pszPrefix);
3842	CPUMVMX_DUMP_HOST_XDTR(pHlp, pVmcs, Idtr, "IDTR", pszPrefix);
3843
3844	/* 32-bit. */
3845	pHlp->pfnPrintf(pHlp, " %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32HostSysenterCs);
3846
3847	/* 64-bit. */
3848	pHlp->pfnPrintf(pHlp, " %sEFER = %#RX64\n", pszPrefix, pVmcs->u64HostEferMsr.u);
3849	pHlp->pfnPrintf(pHlp, " %sPAT = %#RX64\n", pszPrefix, pVmcs->u64HostPatMsr.u);
3850	pHlp->pfnPrintf(pHlp, " %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64HostPerfGlobalCtlMsr.u);
3851	pHlp->pfnPrintf(pHlp, " %sPKRS = %#RX64\n", pszPrefix, pVmcs->u64HostPkrsMsr.u);
3852
3853	/* Natural width. */
3854	pHlp->pfnPrintf(pHlp, " %sCR0 = %#RX64\n", pszPrefix, pVmcs->u64HostCr0.u);
3855	pHlp->pfnPrintf(pHlp, " %sCR3 = %#RX64\n", pszPrefix, pVmcs->u64HostCr3.u);
3856	pHlp->pfnPrintf(pHlp, " %sCR4 = %#RX64\n", pszPrefix, pVmcs->u64HostCr4.u);
3857	pHlp->pfnPrintf(pHlp, " %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEsp.u);
3858	pHlp->pfnPrintf(pHlp, " %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEip.u);
3859	pHlp->pfnPrintf(pHlp, " %sRSP = %#RX64\n", pszPrefix, pVmcs->u64HostRsp.u);
3860	pHlp->pfnPrintf(pHlp, " %sRIP = %#RX64\n", pszPrefix, pVmcs->u64HostRip.u);
3861	pHlp->pfnPrintf(pHlp, " %sS_CET = %#RX64\n", pszPrefix, pVmcs->u64HostSCetMsr.u);
3862	pHlp->pfnPrintf(pHlp, " %sSSP = %#RX64\n", pszPrefix, pVmcs->u64HostSsp.u);
3863	pHlp->pfnPrintf(pHlp, " %sINTERRUPT_SSP_TABLE_ADDR = %#RX64\n", pszPrefix, pVmcs->u64HostIntrSspTableAddrMsr.u);
3864
3865	}
3866
3867	/* Read-only fields. */
3868	{
3869	pHlp->pfnPrintf(pHlp, "%sRead-only data fields:\n", pszPrefix);
3870
3871	/* 16-bit (none currently). */
3872
3873	/* 32-bit. */
3874	pHlp->pfnPrintf(pHlp, " %sExit reason = %u (%s)\n", pszPrefix, pVmcs->u32RoExitReason, HMGetVmxExitName(pVmcs->u32RoExitReason));
3875	pHlp->pfnPrintf(pHlp, " %sExit qualification = %#RX64\n", pszPrefix, pVmcs->u64RoExitQual.u);
3876	pHlp->pfnPrintf(pHlp, " %sVM-instruction error = %#RX32\n", pszPrefix, pVmcs->u32RoVmInstrError);
3877	pHlp->pfnPrintf(pHlp, " %sVM-exit intr info = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntInfo);
3878	{
3879	uint32_t const fInfo = pVmcs->u32RoExitIntInfo;
3880	uint8_t const uType = VMX_EXIT_INT_INFO_TYPE(fInfo);
3881	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_VALID(fInfo));
3882	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetExitIntInfoTypeDesc(uType));
3883	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_EXIT_INT_INFO_VECTOR(fInfo));
3884	pHlp->pfnPrintf(pHlp, " %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo));
3885	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(fInfo));
3886	}
3887	pHlp->pfnPrintf(pHlp, " %sVM-exit intr error-code = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntErrCode);
3888	pHlp->pfnPrintf(pHlp, " %sIDT-vectoring info = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringInfo);
3889	{
3890	uint32_t const fInfo = pVmcs->u32RoIdtVectoringInfo;
3891	uint8_t const uType = VMX_IDT_VECTORING_INFO_TYPE(fInfo);
3892	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_VALID(fInfo));
3893	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetIdtVectoringInfoTypeDesc(uType));
3894	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_IDT_VECTORING_INFO_VECTOR(fInfo));
3895	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(fInfo));
3896	}
3897	pHlp->pfnPrintf(pHlp, " %sIDT-vectoring error-code = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringErrCode);
3898	pHlp->pfnPrintf(pHlp, " %sVM-exit instruction length = %u byte(s)\n", pszPrefix, pVmcs->u32RoExitInstrLen);
3899	pHlp->pfnPrintf(pHlp, " %sVM-exit instruction info = %#RX64\n", pszPrefix, pVmcs->u32RoExitInstrInfo);
3900
3901	/* 64-bit. */
3902	pHlp->pfnPrintf(pHlp, " %sGuest-physical addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestPhysAddr.u);
3903
3904	/* Natural width. */
3905	pHlp->pfnPrintf(pHlp, " %sI/O RCX = %#RX64\n", pszPrefix, pVmcs->u64RoIoRcx.u);
3906	pHlp->pfnPrintf(pHlp, " %sI/O RSI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRsi.u);
3907	pHlp->pfnPrintf(pHlp, " %sI/O RDI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRdi.u);
3908	pHlp->pfnPrintf(pHlp, " %sI/O RIP = %#RX64\n", pszPrefix, pVmcs->u64RoIoRip.u);
3909	pHlp->pfnPrintf(pHlp, " %sGuest-linear addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestLinearAddr.u);
3910	}
3911
3912	#ifdef DEBUG_ramshankar
3913	if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
3914	{
3915	void *pvPage = RTMemTmpAllocZ(VMX_V_VIRT_APIC_SIZE);
3916	Assert(pvPage);
3917	RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3918	int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pvPage, GCPhysVirtApic, VMX_V_VIRT_APIC_SIZE);
3919	if (RT_SUCCESS(rc))
3920	{
3921	pHlp->pfnPrintf(pHlp, " %sVirtual-APIC page\n", pszPrefix);
3922	pHlp->pfnPrintf(pHlp, "%.*Rhxs\n", VMX_V_VIRT_APIC_SIZE, pvPage);
3923	pHlp->pfnPrintf(pHlp, "\n");
3924	}
3925	RTMemTmpFree(pvPage);
3926	}
3927	#else
3928	NOREF(pVCpu);
3929	#endif
3930
3931	#undef CPUMVMX_DUMP_HOST_XDTR
3932	#undef CPUMVMX_DUMP_HOST_FS_GS_TR
3933	#undef CPUMVMX_DUMP_GUEST_SEGREG
3934	#undef CPUMVMX_DUMP_GUEST_XDTR
3935	}
3936
3937
3938	/**
3939	* Display the guest's hardware-virtualization cpu state.
3940	*
3941	* @param pVM The cross context VM structure.
3942	* @param pHlp The info helper functions.
3943	* @param pszArgs Arguments, ignored.
3944	*/
3945	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3946	{
3947	RT_NOREF(pszArgs);
3948
3949	PVMCPU pVCpu = VMMGetCpu(pVM);
3950	if (!pVCpu)
3951	pVCpu = pVM->apCpusR3[0];
3952
3953	PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3954	bool const fSvm = pVM->cpum.s.GuestFeatures.fSvm;
3955	bool const fVmx = pVM->cpum.s.GuestFeatures.fVmx;
3956
3957	pHlp->pfnPrintf(pHlp, "VCPU[%u] hardware virtualization state:\n", pVCpu->idCpu);
3958	pHlp->pfnPrintf(pHlp, "fLocalForcedActions = %#RX32\n", pCtx->hwvirt.fLocalForcedActions);
3959	pHlp->pfnPrintf(pHlp, "In nested-guest hwvirt mode = %RTbool\n", CPUMIsGuestInNestedHwvirtMode(pCtx));
3960
3961	if (fSvm)
3962	{
3963	pHlp->pfnPrintf(pHlp, "SVM hwvirt state:\n");
3964	pHlp->pfnPrintf(pHlp, " fGif = %RTbool\n", pCtx->hwvirt.fGif);
3965
3966	char szEFlags[80];
3967	cpumR3InfoFormatFlags(&szEFlags[0], pCtx->hwvirt.svm.HostState.rflags.u);
3968	pHlp->pfnPrintf(pHlp, " uMsrHSavePa = %#RX64\n", pCtx->hwvirt.svm.uMsrHSavePa);
3969	pHlp->pfnPrintf(pHlp, " GCPhysVmcb = %#RGp\n", pCtx->hwvirt.svm.GCPhysVmcb);
3970	pHlp->pfnPrintf(pHlp, " VmcbCtrl:\n");
3971	cpumR3InfoSvmVmcbCtrl(pHlp, &pCtx->hwvirt.svm.Vmcb.ctrl, " " /* pszPrefix */);
3972	pHlp->pfnPrintf(pHlp, " VmcbStateSave:\n");
3973	cpumR3InfoSvmVmcbStateSave(pHlp, &pCtx->hwvirt.svm.Vmcb.guest, " " /* pszPrefix */);
3974	pHlp->pfnPrintf(pHlp, " HostState:\n");
3975	pHlp->pfnPrintf(pHlp, " uEferMsr = %#RX64\n", pCtx->hwvirt.svm.HostState.uEferMsr);
3976	pHlp->pfnPrintf(pHlp, " uCr0 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr0);
3977	pHlp->pfnPrintf(pHlp, " uCr4 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr4);
3978	pHlp->pfnPrintf(pHlp, " uCr3 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr3);
3979	pHlp->pfnPrintf(pHlp, " uRip = %#RX64\n", pCtx->hwvirt.svm.HostState.uRip);
3980	pHlp->pfnPrintf(pHlp, " uRsp = %#RX64\n", pCtx->hwvirt.svm.HostState.uRsp);
3981	pHlp->pfnPrintf(pHlp, " uRax = %#RX64\n", pCtx->hwvirt.svm.HostState.uRax);
3982	pHlp->pfnPrintf(pHlp, " rflags = %#RX64 %31s\n", pCtx->hwvirt.svm.HostState.rflags.u64, szEFlags);
3983	PCCPUMSELREG pSelEs = &pCtx->hwvirt.svm.HostState.es;
3984	pHlp->pfnPrintf(pHlp, " es = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
3985	pSelEs->Sel, pSelEs->u64Base, pSelEs->u32Limit, pSelEs->Attr.u);
3986	PCCPUMSELREG pSelCs = &pCtx->hwvirt.svm.HostState.cs;
3987	pHlp->pfnPrintf(pHlp, " cs = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
3988	pSelCs->Sel, pSelCs->u64Base, pSelCs->u32Limit, pSelCs->Attr.u);
3989	PCCPUMSELREG pSelSs = &pCtx->hwvirt.svm.HostState.ss;
3990	pHlp->pfnPrintf(pHlp, " ss = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
3991	pSelSs->Sel, pSelSs->u64Base, pSelSs->u32Limit, pSelSs->Attr.u);
3992	PCCPUMSELREG pSelDs = &pCtx->hwvirt.svm.HostState.ds;
3993	pHlp->pfnPrintf(pHlp, " ds = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
3994	pSelDs->Sel, pSelDs->u64Base, pSelDs->u32Limit, pSelDs->Attr.u);
3995	pHlp->pfnPrintf(pHlp, " gdtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.gdtr.pGdt,
3996	pCtx->hwvirt.svm.HostState.gdtr.cbGdt);
3997	pHlp->pfnPrintf(pHlp, " idtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.idtr.pIdt,
3998	pCtx->hwvirt.svm.HostState.idtr.cbIdt);
3999	pHlp->pfnPrintf(pHlp, " cPauseFilter = %RU16\n", pCtx->hwvirt.svm.cPauseFilter);
4000	pHlp->pfnPrintf(pHlp, " cPauseFilterThreshold = %RU32\n", pCtx->hwvirt.svm.cPauseFilterThreshold);
4001	pHlp->pfnPrintf(pHlp, " fInterceptEvents = %u\n", pCtx->hwvirt.svm.fInterceptEvents);
4002	}
4003	else if (fVmx)
4004	{
4005	pHlp->pfnPrintf(pHlp, "VMX hwvirt state:\n");
4006	pHlp->pfnPrintf(pHlp, " GCPhysVmxon = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmxon);
4007	pHlp->pfnPrintf(pHlp, " GCPhysVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmcs);
4008	pHlp->pfnPrintf(pHlp, " GCPhysShadowVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysShadowVmcs);
4009	pHlp->pfnPrintf(pHlp, " enmDiag = %u (%s)\n", pCtx->hwvirt.vmx.enmDiag, HMGetVmxDiagDesc(pCtx->hwvirt.vmx.enmDiag));
4010	pHlp->pfnPrintf(pHlp, " uDiagAux = %#RX64\n", pCtx->hwvirt.vmx.uDiagAux);
4011	pHlp->pfnPrintf(pHlp, " enmAbort = %u (%s)\n", pCtx->hwvirt.vmx.enmAbort, VMXGetAbortDesc(pCtx->hwvirt.vmx.enmAbort));
4012	pHlp->pfnPrintf(pHlp, " uAbortAux = %u (%#x)\n", pCtx->hwvirt.vmx.uAbortAux, pCtx->hwvirt.vmx.uAbortAux);
4013	pHlp->pfnPrintf(pHlp, " fInVmxRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxRootMode);
4014	pHlp->pfnPrintf(pHlp, " fInVmxNonRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxNonRootMode);
4015	pHlp->pfnPrintf(pHlp, " fInterceptEvents = %RTbool\n", pCtx->hwvirt.vmx.fInterceptEvents);
4016	pHlp->pfnPrintf(pHlp, " fNmiUnblockingIret = %RTbool\n", pCtx->hwvirt.vmx.fNmiUnblockingIret);
4017	pHlp->pfnPrintf(pHlp, " uFirstPauseLoopTick = %RX64\n", pCtx->hwvirt.vmx.uFirstPauseLoopTick);
4018	pHlp->pfnPrintf(pHlp, " uPrevPauseTick = %RX64\n", pCtx->hwvirt.vmx.uPrevPauseTick);
4019	pHlp->pfnPrintf(pHlp, " uEntryTick = %RX64\n", pCtx->hwvirt.vmx.uEntryTick);
4020	pHlp->pfnPrintf(pHlp, " offVirtApicWrite = %#RX16\n", pCtx->hwvirt.vmx.offVirtApicWrite);
4021	pHlp->pfnPrintf(pHlp, " fVirtNmiBlocking = %RTbool\n", pCtx->hwvirt.vmx.fVirtNmiBlocking);
4022	pHlp->pfnPrintf(pHlp, " VMCS cache:\n");
4023	cpumR3InfoVmxVmcs(pVCpu, pHlp, &pCtx->hwvirt.vmx.Vmcs, " " /* pszPrefix */);
4024	}
4025	else
4026	pHlp->pfnPrintf(pHlp, "Hwvirt state disabled.\n");
4027
4028	#undef CPUMHWVIRTDUMP_NONE
4029	#undef CPUMHWVIRTDUMP_COMMON
4030	#undef CPUMHWVIRTDUMP_SVM
4031	#undef CPUMHWVIRTDUMP_VMX
4032	#undef CPUMHWVIRTDUMP_LAST
4033	#undef CPUMHWVIRTDUMP_ALL
4034	}
4035
4036	/**
4037	* Display the current guest instruction
4038	*
4039	* @param pVM The cross context VM structure.
4040	* @param pHlp The info helper functions.
4041	* @param pszArgs Arguments, ignored.
4042	*/
4043	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4044	{
4045	NOREF(pszArgs);
4046
4047	PVMCPU pVCpu = VMMGetCpu(pVM);
4048	if (!pVCpu)
4049	pVCpu = pVM->apCpusR3[0];
4050
4051	char szInstruction[256];
4052	szInstruction[0] = '\0';
4053	DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
4054	pHlp->pfnPrintf(pHlp, "\nCPUM%u: %s\n\n", pVCpu->idCpu, szInstruction);
4055	}
4056
4057
4058	/**
4059	* Display the hypervisor cpu state.
4060	*
4061	* @param pVM The cross context VM structure.
4062	* @param pHlp The info helper functions.
4063	* @param pszArgs Arguments, ignored.
4064	*/
4065	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4066	{
4067	PVMCPU pVCpu = VMMGetCpu(pVM);
4068	if (!pVCpu)
4069	pVCpu = pVM->apCpusR3[0];
4070
4071	CPUMDUMPTYPE enmType;
4072	const char *pszComment;
4073	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
4074	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
4075
4076	pHlp->pfnPrintf(pHlp,
4077	".dr0=%016RX64 .dr1=%016RX64 .dr2=%016RX64 .dr3=%016RX64\n"
4078	".dr4=%016RX64 .dr5=%016RX64 .dr6=%016RX64 .dr7=%016RX64\n",
4079	pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1], pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3],
4080	pVCpu->cpum.s.Hyper.dr[4], pVCpu->cpum.s.Hyper.dr[5], pVCpu->cpum.s.Hyper.dr[6], pVCpu->cpum.s.Hyper.dr[7]);
4081	pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
4082	}
4083
4084
4085	/**
4086	* Display the host cpu state.
4087	*
4088	* @param pVM The cross context VM structure.
4089	* @param pHlp The info helper functions.
4090	* @param pszArgs Arguments, ignored.
4091	*/
4092	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4093	{
4094	CPUMDUMPTYPE enmType;
4095	const char *pszComment;
4096	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
4097	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
4098
4099	PVMCPU pVCpu = VMMGetCpu(pVM);
4100	if (!pVCpu)
4101	pVCpu = pVM->apCpusR3[0];
4102	PCPUMHOSTCTX pCtx = &pVCpu->cpum.s.Host;
4103
4104	/*
4105	* Format the EFLAGS.
4106	*/
4107	uint64_t efl = pCtx->rflags;
4108	char szEFlags[80];
4109	cpumR3InfoFormatFlags(&szEFlags[0], efl);
4110
4111	/*
4112	* Format the registers.
4113	*/
4114	pHlp->pfnPrintf(pHlp,
4115	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
4116	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
4117	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
4118	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
4119	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
4120	"r14=%016RX64 r15=%016RX64\n"
4121	"iopl=%d %31s\n"
4122	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
4123	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
4124	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
4125	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
4126	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
4127	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
4128	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
4129	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
4130	,
4131	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
4132	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
4133	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
4134	/pCtx->r8, pCtx->r9,/ pCtx->r10,
4135	pCtx->r11, pCtx->r12, pCtx->r13,
4136	pCtx->r14, pCtx->r15,
4137	X86_EFL_GET_IOPL(efl), szEFlags,
4138	pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
4139	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
4140	pCtx->cr4, pCtx->ldtr, pCtx->tr,
4141	pCtx->dr0, pCtx->dr1, pCtx->dr2,
4142	pCtx->dr3, pCtx->dr6, pCtx->dr7,
4143	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
4144	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
4145	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
4146	}
4147
4148	/**
4149	* Structure used when disassembling and instructions in DBGF.
4150	* This is used so the reader function can get the stuff it needs.
4151	*/
4152	typedef struct CPUMDISASSTATE
4153	{
4154	/** Pointer to the CPU structure. */
4155	PDISCPUSTATE pCpu;
4156	/** Pointer to the VM. */
4157	PVM pVM;
4158	/** Pointer to the VMCPU. */
4159	PVMCPU pVCpu;
4160	/** Pointer to the first byte in the segment. */
4161	RTGCUINTPTR GCPtrSegBase;
4162	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
4163	RTGCUINTPTR GCPtrSegEnd;
4164	/** The size of the segment minus 1. */
4165	RTGCUINTPTR cbSegLimit;
4166	/** Pointer to the current page - R3 Ptr. */
4167	void const *pvPageR3;
4168	/** Pointer to the current page - GC Ptr. */
4169	RTGCPTR pvPageGC;
4170	/** The lock information that PGMPhysReleasePageMappingLock needs. */
4171	PGMPAGEMAPLOCK PageMapLock;
4172	/** Whether the PageMapLock is valid or not. */
4173	bool fLocked;
4174	/** 64 bits mode or not. */
4175	bool f64Bits;
4176	} CPUMDISASSTATE, *PCPUMDISASSTATE;
4177
4178
4179	/**
4180	* @callback_method_impl{FNDISREADBYTES}
4181	*/
4182	static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
4183	{
4184	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
4185	for (;;)
4186	{
4187	RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
4188
4189	/*
4190	* Need to update the page translation?
4191	*/
4192	if ( !pState->pvPageR3
4193	\|\| (GCPtr >> GUEST_PAGE_SHIFT) != (pState->pvPageGC >> GUEST_PAGE_SHIFT))
4194	{
4195	/* translate the address */
4196	pState->pvPageGC = GCPtr & ~(RTGCPTR)GUEST_PAGE_OFFSET_MASK;
4197
4198	/* Release mapping lock previously acquired. */
4199	if (pState->fLocked)
4200	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
4201	int rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
4202	if (RT_SUCCESS(rc))
4203	pState->fLocked = true;
4204	else
4205	{
4206	pState->fLocked = false;
4207	pState->pvPageR3 = NULL;
4208	return rc;
4209	}
4210	}
4211
4212	/*
4213	* Check the segment limit.
4214	*/
4215	if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
4216	return VERR_OUT_OF_SELECTOR_BOUNDS;
4217
4218	/*
4219	* Calc how much we can read.
4220	*/
4221	uint32_t cb = GUEST_PAGE_SIZE - (GCPtr & GUEST_PAGE_OFFSET_MASK);
4222	if (!pState->f64Bits)
4223	{
4224	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
4225	if (cb > cbSeg && cbSeg)
4226	cb = cbSeg;
4227	}
4228	if (cb > cbMaxRead)
4229	cb = cbMaxRead;
4230
4231	/*
4232	* Read and advance or exit.
4233	*/
4234	memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & GUEST_PAGE_OFFSET_MASK), cb);
4235	offInstr += (uint8_t)cb;
4236	if (cb >= cbMinRead)
4237	{
4238	pDis->cbCachedInstr = offInstr;
4239	return VINF_SUCCESS;
4240	}
4241	cbMinRead -= (uint8_t)cb;
4242	cbMaxRead -= (uint8_t)cb;
4243	}
4244	}
4245
4246
4247	/**
4248	* Disassemble an instruction and return the information in the provided structure.
4249	*
4250	* @returns VBox status code.
4251	* @param pVM The cross context VM structure.
4252	* @param pVCpu The cross context virtual CPU structure.
4253	* @param pCtx Pointer to the guest CPU context.
4254	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
4255	* @param pCpu Disassembly state.
4256	* @param pszPrefix String prefix for logging (debug only).
4257	*
4258	*/
4259	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu,
4260	const char *pszPrefix)
4261	{
4262	CPUMDISASSTATE State;
4263	int rc;
4264
4265	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
4266	State.pCpu = pCpu;
4267	State.pvPageGC = 0;
4268	State.pvPageR3 = NULL;
4269	State.pVM = pVM;
4270	State.pVCpu = pVCpu;
4271	State.fLocked = false;
4272	State.f64Bits = false;
4273
4274	/*
4275	* Get selector information.
4276	*/
4277	DISCPUMODE enmDisCpuMode;
4278	if ( (pCtx->cr0 & X86_CR0_PE)
4279	&& pCtx->eflags.Bits.u1VM == 0)
4280	{
4281	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4282	return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
4283	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
4284	State.GCPtrSegBase = pCtx->cs.u64Base;
4285	State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
4286	State.cbSegLimit = pCtx->cs.u32Limit;
4287	enmDisCpuMode = (State.f64Bits)
4288	? DISCPUMODE_64BIT
4289	: pCtx->cs.Attr.n.u1DefBig
4290	? DISCPUMODE_32BIT
4291	: DISCPUMODE_16BIT;
4292	}
4293	else
4294	{
4295	/* real or V86 mode */
4296	enmDisCpuMode = DISCPUMODE_16BIT;
4297	State.GCPtrSegBase = pCtx->cs.Sel * 16;
4298	State.GCPtrSegEnd = 0xFFFFFFFF;
4299	State.cbSegLimit = 0xFFFFFFFF;
4300	}
4301
4302	/*
4303	* Disassemble the instruction.
4304	*/
4305	uint32_t cbInstr;
4306	#ifndef LOG_ENABLED
4307	RT_NOREF_PV(pszPrefix);
4308	rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
4309	if (RT_SUCCESS(rc))
4310	{
4311	#else
4312	char szOutput[160];
4313	rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
4314	pCpu, &cbInstr, szOutput, sizeof(szOutput));
4315	if (RT_SUCCESS(rc))
4316	{
4317	/* log it */
4318	if (pszPrefix)
4319	Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
4320	else
4321	Log(("%s", szOutput));
4322	#endif
4323	rc = VINF_SUCCESS;
4324	}
4325	else
4326	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
4327
4328	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
4329	if (State.fLocked)
4330	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
4331
4332	return rc;
4333	}
4334
4335
4336
4337	/**
4338	* API for controlling a few of the CPU features found in CR4.
4339	*
4340	* Currently only X86_CR4_TSD is accepted as input.
4341	*
4342	* @returns VBox status code.
4343	*
4344	* @param pVM The cross context VM structure.
4345	* @param fOr The CR4 OR mask.
4346	* @param fAnd The CR4 AND mask.
4347	*/
4348	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
4349	{
4350	AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
4351	AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
4352
4353	pVM->cpum.s.CR4.OrMask &= fAnd;
4354	pVM->cpum.s.CR4.OrMask \|= fOr;
4355
4356	return VINF_SUCCESS;
4357	}
4358
4359
4360	/**
4361	* Called when the ring-3 init phase completes.
4362	*
4363	* @returns VBox status code.
4364	* @param pVM The cross context VM structure.
4365	* @param enmWhat Which init phase.
4366	*/
4367	VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
4368	{
4369	switch (enmWhat)
4370	{
4371	case VMINITCOMPLETED_RING3:
4372	{
4373	/*
4374	* Figure out if the guest uses 32-bit or 64-bit FPU state at runtime for 64-bit capable VMs.
4375	* Only applicable/used on 64-bit hosts, refer CPUMR0A.asm. See @bugref{7138}.
4376	*/
4377	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
4378	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4379	{
4380	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4381
4382	/* While loading a saved-state we fix it up in, cpumR3LoadDone(). */
4383	if (fSupportsLongMode)
4384	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
4385	}
4386
4387	/* Register statistic counters for MSRs. */
4388	cpumR3MsrRegStats(pVM);
4389
4390	/* Create VMX-preemption timer for nested guests if required. Must be
4391	done here as CPUM is initialized before TM. */
4392	if (pVM->cpum.s.GuestFeatures.fVmx)
4393	{
4394	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4395	{
4396	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4397	char szName[32];
4398	RTStrPrintf(szName, sizeof(szName), "Nested VMX-preemption %u", idCpu);
4399	int rc = TMR3TimerCreate(pVM, TMCLOCK_VIRTUAL_SYNC, cpumR3VmxPreemptTimerCallback, pVCpu,
4400	TMTIMER_FLAGS_RING0, szName, &pVCpu->cpum.s.hNestedVmxPreemptTimer);
4401	AssertLogRelRCReturn(rc, rc);
4402	}
4403	}
4404	break;
4405	}
4406
4407	default:
4408	break;
4409	}
4410	return VINF_SUCCESS;
4411	}
4412
4413
4414	/**
4415	* Called when the ring-0 init phases completed.
4416	*
4417	* @param pVM The cross context VM structure.
4418	*/
4419	VMMR3DECL(void) CPUMR3LogCpuIdAndMsrFeatures(PVM pVM)
4420	{
4421	/*
4422	* Enable log buffering as we're going to log a lot of lines.
4423	*/
4424	bool const fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
4425
4426	/*
4427	* Log the cpuid.
4428	*/
4429	RTCPUSET OnlineSet;
4430	LogRel(("CPUM: Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
4431	(unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
4432	RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
4433	RTCPUID cCores = RTMpGetCoreCount();
4434	if (cCores)
4435	LogRel(("CPUM: Physical host cores: %u\n", (unsigned)cCores));
4436	LogRel(("*********************** CPUID dump **********************\n"));
4437	DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
4438	LogRel(("\n"));
4439	DBGFR3_INFO_LOG_SAFE(pVM, "cpuid", "verbose"); /* macro */
4440	LogRel(("****************** End of CPUID dump ********************\n"));
4441
4442	/*
4443	* Log VT-x extended features.
4444	*
4445	* SVM features are currently all covered under CPUID so there is nothing
4446	* to do here for SVM.
4447	*/
4448	if (pVM->cpum.s.HostFeatures.fVmx)
4449	{
4450	LogRel(("********************* VT-x features *********************\n"));
4451	DBGFR3Info(pVM->pUVM, "cpumvmxfeat", "default", DBGFR3InfoLogRelHlp());
4452	LogRel(("\n"));
4453	LogRel(("***************** End of VT-x features ******************\n"));
4454	}
4455
4456	/*
4457	* Restore the log buffering state to what it was previously.
4458	*/
4459	RTLogRelSetBuffering(fOldBuffered);
4460	}
4461
4462
4463	/**
4464	* Marks the guest debug state as active.
4465	*
4466	* @returns nothing.
4467	* @param pVCpu The cross context virtual CPU structure.
4468	*
4469	* @note This is used solely by NEM (hence the name) to set the correct flags here
4470	* without loading the host's DRx registers, which is not possible from ring-3 anyway.
4471	* The specific NEM backends have to make sure to load the correct values.
4472	*/
4473	VMMR3_INT_DECL(void) CPUMR3NemActivateGuestDebugState(PVMCPUCC pVCpu)
4474	{
4475	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_HYPER);
4476	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_GUEST);
4477	}
4478
4479
4480	/**
4481	* Marks the hyper debug state as active.
4482	*
4483	* @returns nothing.
4484	* @param pVCpu The cross context virtual CPU structure.
4485	*
4486	* @note This is used solely by NEM (hence the name) to set the correct flags here
4487	* without loading the host's DRx registers, which is not possible from ring-3 anyway.
4488	* The specific NEM backends have to make sure to load the correct values.
4489	*/
4490	VMMR3_INT_DECL(void) CPUMR3NemActivateHyperDebugState(PVMCPUCC pVCpu)
4491	{
4492	/*
4493	* Make sure the hypervisor values are up to date.
4494	*/
4495	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX /* no loading, please */);
4496
4497	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_GUEST);
4498	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HYPER);
4499	}

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 94931

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