CPUM.cpp@ 81733

最後變更在這個檔案從81733是 81733,由 vboxsync 提交於 5 年前
VMM: Nested VMX: bugref:9180 Detect VMX-preemption timer erratum and don't passthrough the feature to guests if the erratum is detected.
屬性 svn:eol-style 設為 `native` 屬性 svn:keywords 設為 `Id Revision`
檔案大小: 237.9 KB

行
1	/* $Id: CPUM.cpp 81733 2019-11-07 04:43:30Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.alldomusa.eu.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_cpum CPUM - CPU Monitor / Manager
19	*
20	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
21	* also responsible for lazy FPU handling and some of the context loading
22	* in raw mode.
23	*
24	* There are three CPU contexts, the most important one is the guest one (GC).
25	* When running in raw-mode (RC) there is a special hyper context for the VMM
26	* part that floats around inside the guest address space. When running in
27	* raw-mode, CPUM also maintains a host context for saving and restoring
28	* registers across world switches. This latter is done in cooperation with the
29	* world switcher (@see pg_vmm).
30	*
31	* @see grp_cpum
32	*
33	* @section sec_cpum_fpu FPU / SSE / AVX / ++ state.
34	*
35	* TODO: proper write up, currently just some notes.
36	*
37	* The ring-0 FPU handling per OS:
38	*
39	* - 64-bit Windows uses XMM registers in the kernel as part of the calling
40	* convention (Visual C++ doesn't seem to have a way to disable
41	* generating such code either), so CR0.TS/EM are always zero from what I
42	* can tell. We are also forced to always load/save the guest XMM0-XMM15
43	* registers when entering/leaving guest context. Interrupt handlers
44	* using FPU/SSE will offically have call save and restore functions
45	* exported by the kernel, if the really really have to use the state.
46	*
47	* - 32-bit windows does lazy FPU handling, I think, probably including
48	* lazying saving. The Windows Internals book states that it's a bad
49	* idea to use the FPU in kernel space. However, it looks like it will
50	* restore the FPU state of the current thread in case of a kernel \#NM.
51	* Interrupt handlers should be same as for 64-bit.
52	*
53	* - Darwin allows taking \#NM in kernel space, restoring current thread's
54	* state if I read the code correctly. It saves the FPU state of the
55	* outgoing thread, and uses CR0.TS to lazily load the state of the
56	* incoming one. No idea yet how the FPU is treated by interrupt
57	* handlers, i.e. whether they are allowed to disable the state or
58	* something.
59	*
60	* - Linux also allows \#NM in kernel space (don't know since when), and
61	* uses CR0.TS for lazy loading. Saves outgoing thread's state, lazy
62	* loads the incoming unless configured to agressivly load it. Interrupt
63	* handlers can ask whether they're allowed to use the FPU, and may
64	* freely trash the state if Linux thinks it has saved the thread's state
65	* already. This is a problem.
66	*
67	* - Solaris will, from what I can tell, panic if it gets an \#NM in kernel
68	* context. When switching threads, the kernel will save the state of
69	* the outgoing thread and lazy load the incoming one using CR0.TS.
70	* There are a few routines in seeblk.s which uses the SSE unit in ring-0
71	* to do stuff, HAT are among the users. The routines there will
72	* manually clear CR0.TS and save the XMM registers they use only if
73	* CR0.TS was zero upon entry. They will skip it when not, because as
74	* mentioned above, the FPU state is saved when switching away from a
75	* thread and CR0.TS set to 1, so when CR0.TS is 1 there is nothing to
76	* preserve. This is a problem if we restore CR0.TS to 1 after loading
77	* the guest state.
78	*
79	* - FreeBSD - no idea yet.
80	*
81	* - OS/2 does not allow \#NMs in kernel space IIRC. Does lazy loading,
82	* possibly also lazy saving. Interrupts must preserve the CR0.TS+EM &
83	* FPU states.
84	*
85	* Up to r107425 (2016-05-24) we would only temporarily modify CR0.TS/EM while
86	* saving and restoring the host and guest states. The motivation for this
87	* change is that we want to be able to emulate SSE instruction in ring-0 (IEM).
88	*
89	* Starting with that change, we will leave CR0.TS=EM=0 after saving the host
90	* state and only restore it once we've restore the host FPU state. This has the
91	* accidental side effect of triggering Solaris to preserve XMM registers in
92	* sseblk.s. When CR0 was changed by saving the FPU state, CPUM must now inform
93	* the VT-x (HMVMX) code about it as it caches the CR0 value in the VMCS.
94	*
95	*
96	* @section sec_cpum_logging Logging Level Assignments.
97	*
98	* Following log level assignments:
99	* - Log6 is used for FPU state management.
100	* - Log7 is used for FPU state actualization.
101	*
102	*/
103
104
105	/*********************************************************************************************************************************
106	* Header Files *
107	*********************************************************************************************************************************/
108	#define LOG_GROUP LOG_GROUP_CPUM
109	#include <VBox/vmm/cpum.h>
110	#include <VBox/vmm/cpumdis.h>
111	#include <VBox/vmm/cpumctx-v1_6.h>
112	#include <VBox/vmm/pgm.h>
113	#include <VBox/vmm/apic.h>
114	#include <VBox/vmm/mm.h>
115	#include <VBox/vmm/em.h>
116	#include <VBox/vmm/iem.h>
117	#include <VBox/vmm/selm.h>
118	#include <VBox/vmm/dbgf.h>
119	#include <VBox/vmm/hm.h>
120	#include <VBox/vmm/hmvmxinline.h>
121	#include <VBox/vmm/ssm.h>
122	#include "CPUMInternal.h"
123	#include <VBox/vmm/vm.h>
124
125	#include <VBox/param.h>
126	#include <VBox/dis.h>
127	#include <VBox/err.h>
128	#include <VBox/log.h>
129	#include <iprt/asm-amd64-x86.h>
130	#include <iprt/assert.h>
131	#include <iprt/cpuset.h>
132	#include <iprt/mem.h>
133	#include <iprt/mp.h>
134	#include <iprt/string.h>
135
136
137	/*********************************************************************************************************************************
138	* Defined Constants And Macros *
139	*********************************************************************************************************************************/
140	/**
141	* This was used in the saved state up to the early life of version 14.
142	*
143	* It indicates that we may have some out-of-sync hidden segement registers.
144	* It is only relevant for raw-mode.
145	*/
146	#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
147
148
149	/*********************************************************************************************************************************
150	* Structures and Typedefs *
151	*********************************************************************************************************************************/
152
153	/**
154	* What kind of cpu info dump to perform.
155	*/
156	typedef enum CPUMDUMPTYPE
157	{
158	CPUMDUMPTYPE_TERSE,
159	CPUMDUMPTYPE_DEFAULT,
160	CPUMDUMPTYPE_VERBOSE
161	} CPUMDUMPTYPE;
162	/** Pointer to a cpu info dump type. */
163	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
164
165
166	/*********************************************************************************************************************************
167	* Internal Functions *
168	*********************************************************************************************************************************/
169	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
170	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
171	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
172	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
173	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
174	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
175	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
176	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
177	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
178	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
179	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
180
181
182	/*********************************************************************************************************************************
183	* Global Variables *
184	*********************************************************************************************************************************/
185	/** Saved state field descriptors for CPUMCTX. */
186	static const SSMFIELD g_aCpumCtxFields[] =
187	{
188	SSMFIELD_ENTRY( CPUMCTX, rdi),
189	SSMFIELD_ENTRY( CPUMCTX, rsi),
190	SSMFIELD_ENTRY( CPUMCTX, rbp),
191	SSMFIELD_ENTRY( CPUMCTX, rax),
192	SSMFIELD_ENTRY( CPUMCTX, rbx),
193	SSMFIELD_ENTRY( CPUMCTX, rdx),
194	SSMFIELD_ENTRY( CPUMCTX, rcx),
195	SSMFIELD_ENTRY( CPUMCTX, rsp),
196	SSMFIELD_ENTRY( CPUMCTX, rflags),
197	SSMFIELD_ENTRY( CPUMCTX, rip),
198	SSMFIELD_ENTRY( CPUMCTX, r8),
199	SSMFIELD_ENTRY( CPUMCTX, r9),
200	SSMFIELD_ENTRY( CPUMCTX, r10),
201	SSMFIELD_ENTRY( CPUMCTX, r11),
202	SSMFIELD_ENTRY( CPUMCTX, r12),
203	SSMFIELD_ENTRY( CPUMCTX, r13),
204	SSMFIELD_ENTRY( CPUMCTX, r14),
205	SSMFIELD_ENTRY( CPUMCTX, r15),
206	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
207	SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
208	SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
209	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
210	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
211	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
212	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
213	SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
214	SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
215	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
216	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
217	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
218	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
219	SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
220	SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
221	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
222	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
223	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
224	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
225	SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
226	SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
227	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
228	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
229	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
230	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
231	SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
232	SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
233	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
234	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
235	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
236	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
237	SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
238	SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
239	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
240	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
241	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
242	SSMFIELD_ENTRY( CPUMCTX, cr0),
243	SSMFIELD_ENTRY( CPUMCTX, cr2),
244	SSMFIELD_ENTRY( CPUMCTX, cr3),
245	SSMFIELD_ENTRY( CPUMCTX, cr4),
246	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
247	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
248	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
249	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
250	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
251	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
252	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
253	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
254	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
255	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
256	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
257	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
258	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
259	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
260	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
261	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
262	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
263	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
264	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
265	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
266	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
267	SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
268	SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
269	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
270	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
271	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
272	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
273	SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
274	SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
275	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
276	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
277	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
278	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[0], CPUM_SAVED_STATE_VERSION_XSAVE),
279	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[1], CPUM_SAVED_STATE_VERSION_XSAVE),
280	SSMFIELD_ENTRY_VER( CPUMCTX, fXStateMask, CPUM_SAVED_STATE_VERSION_XSAVE),
281	SSMFIELD_ENTRY_TERM()
282	};
283
284	/** Saved state field descriptors for SVM nested hardware-virtualization
285	* Host State. */
286	static const SSMFIELD g_aSvmHwvirtHostState[] =
287	{
288	SSMFIELD_ENTRY( SVMHOSTSTATE, uEferMsr),
289	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr0),
290	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr4),
291	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr3),
292	SSMFIELD_ENTRY( SVMHOSTSTATE, uRip),
293	SSMFIELD_ENTRY( SVMHOSTSTATE, uRsp),
294	SSMFIELD_ENTRY( SVMHOSTSTATE, uRax),
295	SSMFIELD_ENTRY( SVMHOSTSTATE, rflags),
296	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Sel),
297	SSMFIELD_ENTRY( SVMHOSTSTATE, es.ValidSel),
298	SSMFIELD_ENTRY( SVMHOSTSTATE, es.fFlags),
299	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u64Base),
300	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u32Limit),
301	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Attr),
302	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Sel),
303	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.ValidSel),
304	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.fFlags),
305	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u64Base),
306	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u32Limit),
307	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Attr),
308	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Sel),
309	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.ValidSel),
310	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.fFlags),
311	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u64Base),
312	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u32Limit),
313	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Attr),
314	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Sel),
315	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.ValidSel),
316	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.fFlags),
317	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u64Base),
318	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u32Limit),
319	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Attr),
320	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.cbGdt),
321	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.pGdt),
322	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.cbIdt),
323	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.pIdt),
324	SSMFIELD_ENTRY_IGNORE(SVMHOSTSTATE, abPadding),
325	SSMFIELD_ENTRY_TERM()
326	};
327
328	/** Saved state field descriptors for VMX nested hardware-virtualization
329	* VMCS. */
330	static const SSMFIELD g_aVmxHwvirtVmcs[] =
331	{
332	SSMFIELD_ENTRY( VMXVVMCS, u32VmcsRevId),
333	SSMFIELD_ENTRY( VMXVVMCS, enmVmxAbort),
334	SSMFIELD_ENTRY( VMXVVMCS, fVmcsState),
335	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au8Padding0),
336	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved0),
337
338	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, u16Reserved0),
339
340	SSMFIELD_ENTRY( VMXVVMCS, u32RoVmInstrError),
341	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitReason),
342	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitIntInfo),
343	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitIntErrCode),
344	SSMFIELD_ENTRY( VMXVVMCS, u32RoIdtVectoringInfo),
345	SSMFIELD_ENTRY( VMXVVMCS, u32RoIdtVectoringErrCode),
346	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitInstrLen),
347	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitInstrInfo),
348	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32RoReserved2),
349
350	SSMFIELD_ENTRY( VMXVVMCS, u64RoGuestPhysAddr),
351	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved1),
352
353	SSMFIELD_ENTRY( VMXVVMCS, u64RoExitQual),
354	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRcx),
355	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRsi),
356	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRdi),
357	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRip),
358	SSMFIELD_ENTRY( VMXVVMCS, u64RoGuestLinearAddr),
359	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved5),
360
361	SSMFIELD_ENTRY( VMXVVMCS, u16Vpid),
362	SSMFIELD_ENTRY( VMXVVMCS, u16PostIntNotifyVector),
363	SSMFIELD_ENTRY( VMXVVMCS, u16EptpIndex),
364	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved0),
365
366	SSMFIELD_ENTRY( VMXVVMCS, u32PinCtls),
367	SSMFIELD_ENTRY( VMXVVMCS, u32ProcCtls),
368	SSMFIELD_ENTRY( VMXVVMCS, u32XcptBitmap),
369	SSMFIELD_ENTRY( VMXVVMCS, u32XcptPFMask),
370	SSMFIELD_ENTRY( VMXVVMCS, u32XcptPFMatch),
371	SSMFIELD_ENTRY( VMXVVMCS, u32Cr3TargetCount),
372	SSMFIELD_ENTRY( VMXVVMCS, u32ExitCtls),
373	SSMFIELD_ENTRY( VMXVVMCS, u32ExitMsrStoreCount),
374	SSMFIELD_ENTRY( VMXVVMCS, u32ExitMsrLoadCount),
375	SSMFIELD_ENTRY( VMXVVMCS, u32EntryCtls),
376	SSMFIELD_ENTRY( VMXVVMCS, u32EntryMsrLoadCount),
377	SSMFIELD_ENTRY( VMXVVMCS, u32EntryIntInfo),
378	SSMFIELD_ENTRY( VMXVVMCS, u32EntryXcptErrCode),
379	SSMFIELD_ENTRY( VMXVVMCS, u32EntryInstrLen),
380	SSMFIELD_ENTRY( VMXVVMCS, u32TprThreshold),
381	SSMFIELD_ENTRY( VMXVVMCS, u32ProcCtls2),
382	SSMFIELD_ENTRY( VMXVVMCS, u32PleGap),
383	SSMFIELD_ENTRY( VMXVVMCS, u32PleWindow),
384	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved1),
385
386	SSMFIELD_ENTRY( VMXVVMCS, u64AddrIoBitmapA),
387	SSMFIELD_ENTRY( VMXVVMCS, u64AddrIoBitmapB),
388	SSMFIELD_ENTRY( VMXVVMCS, u64AddrMsrBitmap),
389	SSMFIELD_ENTRY( VMXVVMCS, u64AddrExitMsrStore),
390	SSMFIELD_ENTRY( VMXVVMCS, u64AddrExitMsrLoad),
391	SSMFIELD_ENTRY( VMXVVMCS, u64AddrEntryMsrLoad),
392	SSMFIELD_ENTRY( VMXVVMCS, u64ExecVmcsPtr),
393	SSMFIELD_ENTRY( VMXVVMCS, u64AddrPml),
394	SSMFIELD_ENTRY( VMXVVMCS, u64TscOffset),
395	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVirtApic),
396	SSMFIELD_ENTRY( VMXVVMCS, u64AddrApicAccess),
397	SSMFIELD_ENTRY( VMXVVMCS, u64AddrPostedIntDesc),
398	SSMFIELD_ENTRY( VMXVVMCS, u64VmFuncCtls),
399	SSMFIELD_ENTRY( VMXVVMCS, u64EptpPtr),
400	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap0),
401	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap1),
402	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap2),
403	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap3),
404	SSMFIELD_ENTRY( VMXVVMCS, u64AddrEptpList),
405	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVmreadBitmap),
406	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVmwriteBitmap),
407	SSMFIELD_ENTRY( VMXVVMCS, u64AddrXcptVeInfo),
408	SSMFIELD_ENTRY( VMXVVMCS, u64XssBitmap),
409	SSMFIELD_ENTRY( VMXVVMCS, u64EnclsBitmap),
410	SSMFIELD_ENTRY( VMXVVMCS, u64SpptPtr),
411	SSMFIELD_ENTRY( VMXVVMCS, u64TscMultiplier),
412	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved0),
413
414	SSMFIELD_ENTRY( VMXVVMCS, u64Cr0Mask),
415	SSMFIELD_ENTRY( VMXVVMCS, u64Cr4Mask),
416	SSMFIELD_ENTRY( VMXVVMCS, u64Cr0ReadShadow),
417	SSMFIELD_ENTRY( VMXVVMCS, u64Cr4ReadShadow),
418	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target0),
419	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target1),
420	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target2),
421	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target3),
422	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved4),
423
424	SSMFIELD_ENTRY( VMXVVMCS, HostEs),
425	SSMFIELD_ENTRY( VMXVVMCS, HostCs),
426	SSMFIELD_ENTRY( VMXVVMCS, HostSs),
427	SSMFIELD_ENTRY( VMXVVMCS, HostDs),
428	SSMFIELD_ENTRY( VMXVVMCS, HostFs),
429	SSMFIELD_ENTRY( VMXVVMCS, HostGs),
430	SSMFIELD_ENTRY( VMXVVMCS, HostTr),
431	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved2),
432
433	SSMFIELD_ENTRY( VMXVVMCS, u32HostSysenterCs),
434	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved4),
435
436	SSMFIELD_ENTRY( VMXVVMCS, u64HostPatMsr),
437	SSMFIELD_ENTRY( VMXVVMCS, u64HostEferMsr),
438	SSMFIELD_ENTRY( VMXVVMCS, u64HostPerfGlobalCtlMsr),
439	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved3),
440
441	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr0),
442	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr3),
443	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr4),
444	SSMFIELD_ENTRY( VMXVVMCS, u64HostFsBase),
445	SSMFIELD_ENTRY( VMXVVMCS, u64HostGsBase),
446	SSMFIELD_ENTRY( VMXVVMCS, u64HostTrBase),
447	SSMFIELD_ENTRY( VMXVVMCS, u64HostGdtrBase),
448	SSMFIELD_ENTRY( VMXVVMCS, u64HostIdtrBase),
449	SSMFIELD_ENTRY( VMXVVMCS, u64HostSysenterEsp),
450	SSMFIELD_ENTRY( VMXVVMCS, u64HostSysenterEip),
451	SSMFIELD_ENTRY( VMXVVMCS, u64HostRsp),
452	SSMFIELD_ENTRY( VMXVVMCS, u64HostRip),
453	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved7),
454
455	SSMFIELD_ENTRY( VMXVVMCS, GuestEs),
456	SSMFIELD_ENTRY( VMXVVMCS, GuestCs),
457	SSMFIELD_ENTRY( VMXVVMCS, GuestSs),
458	SSMFIELD_ENTRY( VMXVVMCS, GuestDs),
459	SSMFIELD_ENTRY( VMXVVMCS, GuestFs),
460	SSMFIELD_ENTRY( VMXVVMCS, GuestGs),
461	SSMFIELD_ENTRY( VMXVVMCS, GuestLdtr),
462	SSMFIELD_ENTRY( VMXVVMCS, GuestTr),
463	SSMFIELD_ENTRY( VMXVVMCS, u16GuestIntStatus),
464	SSMFIELD_ENTRY( VMXVVMCS, u16PmlIndex),
465	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved1),
466
467	SSMFIELD_ENTRY( VMXVVMCS, u32GuestEsLimit),
468	SSMFIELD_ENTRY( VMXVVMCS, u32GuestCsLimit),
469	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSsLimit),
470	SSMFIELD_ENTRY( VMXVVMCS, u32GuestDsLimit),
471	SSMFIELD_ENTRY( VMXVVMCS, u32GuestFsLimit),
472	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGsLimit),
473	SSMFIELD_ENTRY( VMXVVMCS, u32GuestLdtrLimit),
474	SSMFIELD_ENTRY( VMXVVMCS, u32GuestTrLimit),
475	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGdtrLimit),
476	SSMFIELD_ENTRY( VMXVVMCS, u32GuestIdtrLimit),
477	SSMFIELD_ENTRY( VMXVVMCS, u32GuestEsAttr),
478	SSMFIELD_ENTRY( VMXVVMCS, u32GuestCsAttr),
479	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSsAttr),
480	SSMFIELD_ENTRY( VMXVVMCS, u32GuestDsAttr),
481	SSMFIELD_ENTRY( VMXVVMCS, u32GuestFsAttr),
482	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGsAttr),
483	SSMFIELD_ENTRY( VMXVVMCS, u32GuestLdtrAttr),
484	SSMFIELD_ENTRY( VMXVVMCS, u32GuestTrAttr),
485	SSMFIELD_ENTRY( VMXVVMCS, u32GuestIntrState),
486	SSMFIELD_ENTRY( VMXVVMCS, u32GuestActivityState),
487	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSmBase),
488	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSysenterCS),
489	SSMFIELD_ENTRY( VMXVVMCS, u32PreemptTimer),
490	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved3),
491
492	SSMFIELD_ENTRY( VMXVVMCS, u64VmcsLinkPtr),
493	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDebugCtlMsr),
494	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPatMsr),
495	SSMFIELD_ENTRY( VMXVVMCS, u64GuestEferMsr),
496	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPerfGlobalCtlMsr),
497	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte0),
498	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte1),
499	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte2),
500	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte3),
501	SSMFIELD_ENTRY( VMXVVMCS, u64GuestBndcfgsMsr),
502	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRtitCtlMsr),
503	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved2),
504
505	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr0),
506	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr3),
507	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr4),
508	SSMFIELD_ENTRY( VMXVVMCS, u64GuestEsBase),
509	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCsBase),
510	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSsBase),
511	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDsBase),
512	SSMFIELD_ENTRY( VMXVVMCS, u64GuestFsBase),
513	SSMFIELD_ENTRY( VMXVVMCS, u64GuestGsBase),
514	SSMFIELD_ENTRY( VMXVVMCS, u64GuestLdtrBase),
515	SSMFIELD_ENTRY( VMXVVMCS, u64GuestTrBase),
516	SSMFIELD_ENTRY( VMXVVMCS, u64GuestGdtrBase),
517	SSMFIELD_ENTRY( VMXVVMCS, u64GuestIdtrBase),
518	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDr7),
519	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRsp),
520	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRip),
521	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRFlags),
522	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPendingDbgXcpts),
523	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSysenterEsp),
524	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSysenterEip),
525	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved6),
526
527	SSMFIELD_ENTRY_TERM()
528	};
529
530	/** Saved state field descriptors for CPUMCTX. */
531	static const SSMFIELD g_aCpumX87Fields[] =
532	{
533	SSMFIELD_ENTRY( X86FXSTATE, FCW),
534	SSMFIELD_ENTRY( X86FXSTATE, FSW),
535	SSMFIELD_ENTRY( X86FXSTATE, FTW),
536	SSMFIELD_ENTRY( X86FXSTATE, FOP),
537	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
538	SSMFIELD_ENTRY( X86FXSTATE, CS),
539	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
540	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
541	SSMFIELD_ENTRY( X86FXSTATE, DS),
542	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
543	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
544	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
545	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
546	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
547	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
548	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
549	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
550	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
551	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
552	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
553	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
554	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
555	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
556	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
557	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
558	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
559	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
560	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
561	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
562	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
563	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
564	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
565	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
566	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
567	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
568	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
569	SSMFIELD_ENTRY_VER( X86FXSTATE, au32RsrvdForSoftware[0], CPUM_SAVED_STATE_VERSION_XSAVE), /* 32-bit/64-bit hack */
570	SSMFIELD_ENTRY_TERM()
571	};
572
573	/** Saved state field descriptors for X86XSAVEHDR. */
574	static const SSMFIELD g_aCpumXSaveHdrFields[] =
575	{
576	SSMFIELD_ENTRY( X86XSAVEHDR, bmXState),
577	SSMFIELD_ENTRY_TERM()
578	};
579
580	/** Saved state field descriptors for X86XSAVEYMMHI. */
581	static const SSMFIELD g_aCpumYmmHiFields[] =
582	{
583	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[0]),
584	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[1]),
585	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[2]),
586	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[3]),
587	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[4]),
588	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[5]),
589	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[6]),
590	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[7]),
591	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[8]),
592	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[9]),
593	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[10]),
594	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[11]),
595	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[12]),
596	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[13]),
597	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[14]),
598	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[15]),
599	SSMFIELD_ENTRY_TERM()
600	};
601
602	/** Saved state field descriptors for X86XSAVEBNDREGS. */
603	static const SSMFIELD g_aCpumBndRegsFields[] =
604	{
605	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[0]),
606	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[1]),
607	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[2]),
608	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[3]),
609	SSMFIELD_ENTRY_TERM()
610	};
611
612	/** Saved state field descriptors for X86XSAVEBNDCFG. */
613	static const SSMFIELD g_aCpumBndCfgFields[] =
614	{
615	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fConfig),
616	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fStatus),
617	SSMFIELD_ENTRY_TERM()
618	};
619
620	#if 0 /** @todo */
621	/** Saved state field descriptors for X86XSAVEOPMASK. */
622	static const SSMFIELD g_aCpumOpmaskFields[] =
623	{
624	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[0]),
625	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[1]),
626	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[2]),
627	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[3]),
628	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[4]),
629	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[5]),
630	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[6]),
631	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[7]),
632	SSMFIELD_ENTRY_TERM()
633	};
634	#endif
635
636	/** Saved state field descriptors for X86XSAVEZMMHI256. */
637	static const SSMFIELD g_aCpumZmmHi256Fields[] =
638	{
639	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[0]),
640	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[1]),
641	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[2]),
642	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[3]),
643	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[4]),
644	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[5]),
645	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[6]),
646	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[7]),
647	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[8]),
648	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[9]),
649	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[10]),
650	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[11]),
651	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[12]),
652	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[13]),
653	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[14]),
654	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[15]),
655	SSMFIELD_ENTRY_TERM()
656	};
657
658	/** Saved state field descriptors for X86XSAVEZMM16HI. */
659	static const SSMFIELD g_aCpumZmm16HiFields[] =
660	{
661	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[0]),
662	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[1]),
663	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[2]),
664	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[3]),
665	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[4]),
666	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[5]),
667	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[6]),
668	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[7]),
669	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[8]),
670	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[9]),
671	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[10]),
672	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[11]),
673	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[12]),
674	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[13]),
675	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[14]),
676	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[15]),
677	SSMFIELD_ENTRY_TERM()
678	};
679
680
681
682	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
683	* registeres changed. */
684	static const SSMFIELD g_aCpumX87FieldsMem[] =
685	{
686	SSMFIELD_ENTRY( X86FXSTATE, FCW),
687	SSMFIELD_ENTRY( X86FXSTATE, FSW),
688	SSMFIELD_ENTRY( X86FXSTATE, FTW),
689	SSMFIELD_ENTRY( X86FXSTATE, FOP),
690	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
691	SSMFIELD_ENTRY( X86FXSTATE, CS),
692	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
693	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
694	SSMFIELD_ENTRY( X86FXSTATE, DS),
695	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
696	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
697	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
698	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
699	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
700	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
701	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
702	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
703	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
704	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
705	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
706	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
707	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
708	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
709	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
710	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
711	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
712	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
713	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
714	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
715	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
716	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
717	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
718	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
719	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
720	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
721	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
722	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
723	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
724	};
725
726	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
727	* registeres changed. */
728	static const SSMFIELD g_aCpumCtxFieldsMem[] =
729	{
730	SSMFIELD_ENTRY( CPUMCTX, rdi),
731	SSMFIELD_ENTRY( CPUMCTX, rsi),
732	SSMFIELD_ENTRY( CPUMCTX, rbp),
733	SSMFIELD_ENTRY( CPUMCTX, rax),
734	SSMFIELD_ENTRY( CPUMCTX, rbx),
735	SSMFIELD_ENTRY( CPUMCTX, rdx),
736	SSMFIELD_ENTRY( CPUMCTX, rcx),
737	SSMFIELD_ENTRY( CPUMCTX, rsp),
738	SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
739	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
740	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
741	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
742	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
743	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
744	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
745	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
746	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
747	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
748	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
749	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
750	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
751	SSMFIELD_ENTRY( CPUMCTX, rflags),
752	SSMFIELD_ENTRY( CPUMCTX, rip),
753	SSMFIELD_ENTRY( CPUMCTX, r8),
754	SSMFIELD_ENTRY( CPUMCTX, r9),
755	SSMFIELD_ENTRY( CPUMCTX, r10),
756	SSMFIELD_ENTRY( CPUMCTX, r11),
757	SSMFIELD_ENTRY( CPUMCTX, r12),
758	SSMFIELD_ENTRY( CPUMCTX, r13),
759	SSMFIELD_ENTRY( CPUMCTX, r14),
760	SSMFIELD_ENTRY( CPUMCTX, r15),
761	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
762	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
763	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
764	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
765	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
766	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
767	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
768	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
769	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
770	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
771	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
772	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
773	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
774	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
775	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
776	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
777	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
778	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
779	SSMFIELD_ENTRY( CPUMCTX, cr0),
780	SSMFIELD_ENTRY( CPUMCTX, cr2),
781	SSMFIELD_ENTRY( CPUMCTX, cr3),
782	SSMFIELD_ENTRY( CPUMCTX, cr4),
783	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
784	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
785	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
786	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
787	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
788	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
789	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
790	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
791	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
792	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
793	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
794	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
795	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
796	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
797	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
798	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
799	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
800	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
801	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
802	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
803	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
804	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
805	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
806	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
807	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
808	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
809	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
810	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
811	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
812	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
813	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
814	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
815	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
816	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
817	SSMFIELD_ENTRY_TERM()
818	};
819
820	/** Saved state field descriptors for CPUMCTX_VER1_6. */
821	static const SSMFIELD g_aCpumX87FieldsV16[] =
822	{
823	SSMFIELD_ENTRY( X86FXSTATE, FCW),
824	SSMFIELD_ENTRY( X86FXSTATE, FSW),
825	SSMFIELD_ENTRY( X86FXSTATE, FTW),
826	SSMFIELD_ENTRY( X86FXSTATE, FOP),
827	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
828	SSMFIELD_ENTRY( X86FXSTATE, CS),
829	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
830	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
831	SSMFIELD_ENTRY( X86FXSTATE, DS),
832	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
833	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
834	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
835	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
836	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
837	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
838	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
839	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
840	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
841	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
842	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
843	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
844	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
845	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
846	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
847	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
848	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
849	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
850	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
851	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
852	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
853	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
854	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
855	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
856	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
857	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
858	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
859	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
860	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
861	SSMFIELD_ENTRY_TERM()
862	};
863
864	/** Saved state field descriptors for CPUMCTX_VER1_6. */
865	static const SSMFIELD g_aCpumCtxFieldsV16[] =
866	{
867	SSMFIELD_ENTRY( CPUMCTX, rdi),
868	SSMFIELD_ENTRY( CPUMCTX, rsi),
869	SSMFIELD_ENTRY( CPUMCTX, rbp),
870	SSMFIELD_ENTRY( CPUMCTX, rax),
871	SSMFIELD_ENTRY( CPUMCTX, rbx),
872	SSMFIELD_ENTRY( CPUMCTX, rdx),
873	SSMFIELD_ENTRY( CPUMCTX, rcx),
874	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
875	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
876	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
877	SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /rsp_notused/),
878	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
879	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
880	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
881	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
882	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
883	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
884	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
885	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
886	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
887	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
888	SSMFIELD_ENTRY( CPUMCTX, rflags),
889	SSMFIELD_ENTRY( CPUMCTX, rip),
890	SSMFIELD_ENTRY( CPUMCTX, r8),
891	SSMFIELD_ENTRY( CPUMCTX, r9),
892	SSMFIELD_ENTRY( CPUMCTX, r10),
893	SSMFIELD_ENTRY( CPUMCTX, r11),
894	SSMFIELD_ENTRY( CPUMCTX, r12),
895	SSMFIELD_ENTRY( CPUMCTX, r13),
896	SSMFIELD_ENTRY( CPUMCTX, r14),
897	SSMFIELD_ENTRY( CPUMCTX, r15),
898	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
899	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
900	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
901	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
902	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
903	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
904	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
905	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
906	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
907	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
908	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
909	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
910	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
911	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
912	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
913	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
914	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
915	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
916	SSMFIELD_ENTRY( CPUMCTX, cr0),
917	SSMFIELD_ENTRY( CPUMCTX, cr2),
918	SSMFIELD_ENTRY( CPUMCTX, cr3),
919	SSMFIELD_ENTRY( CPUMCTX, cr4),
920	SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
921	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
922	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
923	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
924	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
925	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
926	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
927	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
928	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
929	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
930	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
931	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
932	SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
933	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
934	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
935	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
936	SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
937	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
938	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
939	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
940	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
941	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
942	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
943	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
944	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
945	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
946	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
947	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
948	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
949	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
950	SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
951	SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
952	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
953	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
954	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
955	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
956	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
957	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
958	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
959	SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
960	SSMFIELD_ENTRY_TERM()
961	};
962
963
964	/**
965	* Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs.
966	*
967	* AMD K7, K8 and newer AMD CPUs do not save/restore the x87 error pointers
968	* (last instruction pointer, last data pointer, last opcode) except when the ES
969	* bit (Exception Summary) in x87 FSW (FPU Status Word) is set. Thus if we don't
970	* clear these registers there is potential, local FPU leakage from a process
971	* using the FPU to another.
972	*
973	* See AMD Instruction Reference for FXSAVE, FXRSTOR.
974	*
975	* @param pVM The cross context VM structure.
976	*/
977	static void cpumR3CheckLeakyFpu(PVM pVM)
978	{
979	uint32_t u32CpuVersion = ASMCpuId_EAX(1);
980	uint32_t const u32Family = u32CpuVersion >> 8;
981	if ( u32Family >= 6 /* K7 and higher */
982	&& (ASMIsAmdCpu() \|\| ASMIsHygonCpu()) )
983	{
984	uint32_t cExt = ASMCpuId_EAX(0x80000000);
985	if (ASMIsValidExtRange(cExt))
986	{
987	uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
988	if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
989	{
990	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
991	{
992	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
993	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_FFXSR_LEAKY;
994	}
995	Log(("CPUM: Host CPU has leaky fxsave/fxrstor behaviour\n"));
996	}
997	}
998	}
999	}
1000
1001
1002	/**
1003	* Frees memory allocated for the SVM hardware virtualization state.
1004	*
1005	* @param pVM The cross context VM structure.
1006	*/
1007	static void cpumR3FreeSvmHwVirtState(PVM pVM)
1008	{
1009	Assert(pVM->cpum.s.GuestFeatures.fSvm);
1010	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1011	{
1012	PVMCPU pVCpu = pVM->apCpusR3[i];
1013	if (pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3)
1014	{
1015	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3, SVM_VMCB_PAGES);
1016	pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3 = NULL;
1017	}
1018	pVCpu->cpum.s.Guest.hwvirt.svm.HCPhysVmcb = NIL_RTHCPHYS;
1019
1020	if (pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3)
1021	{
1022	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3, SVM_MSRPM_PAGES);
1023	pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3 = NULL;
1024	}
1025
1026	if (pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3)
1027	{
1028	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3, SVM_IOPM_PAGES);
1029	pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3 = NULL;
1030	}
1031	}
1032	}
1033
1034
1035	/**
1036	* Allocates memory for the SVM hardware virtualization state.
1037	*
1038	* @returns VBox status code.
1039	* @param pVM The cross context VM structure.
1040	*/
1041	static int cpumR3AllocSvmHwVirtState(PVM pVM)
1042	{
1043	Assert(pVM->cpum.s.GuestFeatures.fSvm);
1044
1045	int rc = VINF_SUCCESS;
1046	LogRel(("CPUM: Allocating %u pages for the nested-guest SVM MSR and IO permission bitmaps\n",
1047	pVM->cCpus * (SVM_MSRPM_PAGES + SVM_IOPM_PAGES)));
1048	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1049	{
1050	PVMCPU pVCpu = pVM->apCpusR3[i];
1051	pVCpu->cpum.s.Guest.hwvirt.enmHwvirt = CPUMHWVIRT_SVM;
1052
1053	/*
1054	* Allocate the nested-guest VMCB.
1055	*/
1056	SUPPAGE SupNstGstVmcbPage;
1057	RT_ZERO(SupNstGstVmcbPage);
1058	SupNstGstVmcbPage.Phys = NIL_RTHCPHYS;
1059	Assert(SVM_VMCB_PAGES == 1);
1060	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3);
1061	rc = SUPR3PageAllocEx(SVM_VMCB_PAGES, 0 /* fFlags /, (void *)&pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3,
1062	&pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR0, &SupNstGstVmcbPage);
1063	if (RT_FAILURE(rc))
1064	{
1065	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3);
1066	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMCB\n", pVCpu->idCpu, SVM_VMCB_PAGES));
1067	break;
1068	}
1069	pVCpu->cpum.s.Guest.hwvirt.svm.HCPhysVmcb = SupNstGstVmcbPage.Phys;
1070
1071	/*
1072	* Allocate the MSRPM (MSR Permission bitmap).
1073	*/
1074	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3);
1075	rc = SUPR3PageAllocEx(SVM_MSRPM_PAGES, 0 /* fFlags */, &pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3,
1076	&pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR0, NULL /* paPages */);
1077	if (RT_FAILURE(rc))
1078	{
1079	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3);
1080	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's MSR permission bitmap\n", pVCpu->idCpu,
1081	SVM_MSRPM_PAGES));
1082	break;
1083	}
1084
1085	/*
1086	* Allocate the IOPM (IO Permission bitmap).
1087	*/
1088	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3);
1089	rc = SUPR3PageAllocEx(SVM_IOPM_PAGES, 0 /* fFlags */, &pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3,
1090	&pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR0, NULL /* paPages */);
1091	if (RT_FAILURE(rc))
1092	{
1093	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3);
1094	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's IO permission bitmap\n", pVCpu->idCpu,
1095	SVM_IOPM_PAGES));
1096	break;
1097	}
1098	}
1099
1100	/* On any failure, cleanup. */
1101	if (RT_FAILURE(rc))
1102	cpumR3FreeSvmHwVirtState(pVM);
1103
1104	return rc;
1105	}
1106
1107
1108	/**
1109	* Resets per-VCPU SVM hardware virtualization state.
1110	*
1111	* @param pVCpu The cross context virtual CPU structure.
1112	*/
1113	DECLINLINE(void) cpumR3ResetSvmHwVirtState(PVMCPU pVCpu)
1114	{
1115	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1116	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_SVM);
1117	Assert(pCtx->hwvirt.svm.CTX_SUFF(pVmcb));
1118
1119	memset(pCtx->hwvirt.svm.CTX_SUFF(pVmcb), 0, SVM_VMCB_PAGES << PAGE_SHIFT);
1120	pCtx->hwvirt.svm.uMsrHSavePa = 0;
1121	pCtx->hwvirt.svm.uPrevPauseTick = 0;
1122	}
1123
1124
1125	/**
1126	* Frees memory allocated for the VMX hardware virtualization state.
1127	*
1128	* @param pVM The cross context VM structure.
1129	*/
1130	static void cpumR3FreeVmxHwVirtState(PVM pVM)
1131	{
1132	Assert(pVM->cpum.s.GuestFeatures.fVmx);
1133	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1134	{
1135	PVMCPU pVCpu = pVM->apCpusR3[i];
1136	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1137
1138	if (pCtx->hwvirt.vmx.pVmcsR3)
1139	{
1140	SUPR3ContFree(pCtx->hwvirt.vmx.pVmcsR3, VMX_V_VMCS_PAGES);
1141	pCtx->hwvirt.vmx.pVmcsR3 = NULL;
1142	}
1143	if (pCtx->hwvirt.vmx.pShadowVmcsR3)
1144	{
1145	SUPR3ContFree(pCtx->hwvirt.vmx.pShadowVmcsR3, VMX_V_VMCS_PAGES);
1146	pCtx->hwvirt.vmx.pShadowVmcsR3 = NULL;
1147	}
1148	if (pCtx->hwvirt.vmx.pvVirtApicPageR3)
1149	{
1150	SUPR3ContFree(pCtx->hwvirt.vmx.pvVirtApicPageR3, VMX_V_VIRT_APIC_PAGES);
1151	pCtx->hwvirt.vmx.pvVirtApicPageR3 = NULL;
1152	}
1153	if (pCtx->hwvirt.vmx.pvVmreadBitmapR3)
1154	{
1155	SUPR3ContFree(pCtx->hwvirt.vmx.pvVmreadBitmapR3, VMX_V_VMREAD_VMWRITE_BITMAP_PAGES);
1156	pCtx->hwvirt.vmx.pvVmreadBitmapR3 = NULL;
1157	}
1158	if (pCtx->hwvirt.vmx.pvVmwriteBitmapR3)
1159	{
1160	SUPR3ContFree(pCtx->hwvirt.vmx.pvVmwriteBitmapR3, VMX_V_VMREAD_VMWRITE_BITMAP_PAGES);
1161	pCtx->hwvirt.vmx.pvVmwriteBitmapR3 = NULL;
1162	}
1163	if (pCtx->hwvirt.vmx.pEntryMsrLoadAreaR3)
1164	{
1165	SUPR3ContFree(pCtx->hwvirt.vmx.pEntryMsrLoadAreaR3, VMX_V_AUTOMSR_AREA_PAGES);
1166	pCtx->hwvirt.vmx.pEntryMsrLoadAreaR3 = NULL;
1167	}
1168	if (pCtx->hwvirt.vmx.pExitMsrStoreAreaR3)
1169	{
1170	SUPR3ContFree(pCtx->hwvirt.vmx.pExitMsrStoreAreaR3, VMX_V_AUTOMSR_AREA_PAGES);
1171	pCtx->hwvirt.vmx.pExitMsrStoreAreaR3 = NULL;
1172	}
1173	if (pCtx->hwvirt.vmx.pExitMsrLoadAreaR3)
1174	{
1175	SUPR3ContFree(pCtx->hwvirt.vmx.pExitMsrLoadAreaR3, VMX_V_AUTOMSR_AREA_PAGES);
1176	pCtx->hwvirt.vmx.pExitMsrLoadAreaR3 = NULL;
1177	}
1178	if (pCtx->hwvirt.vmx.pvMsrBitmapR3)
1179	{
1180	SUPR3ContFree(pCtx->hwvirt.vmx.pvMsrBitmapR3, VMX_V_MSR_BITMAP_PAGES);
1181	pCtx->hwvirt.vmx.pvMsrBitmapR3 = NULL;
1182	}
1183	if (pCtx->hwvirt.vmx.pvIoBitmapR3)
1184	{
1185	SUPR3ContFree(pCtx->hwvirt.vmx.pvIoBitmapR3, VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES);
1186	pCtx->hwvirt.vmx.pvIoBitmapR3 = NULL;
1187	}
1188	}
1189	}
1190
1191
1192	/**
1193	* Allocates memory for the VMX hardware virtualization state.
1194	*
1195	* @returns VBox status code.
1196	* @param pVM The cross context VM structure.
1197	*/
1198	static int cpumR3AllocVmxHwVirtState(PVM pVM)
1199	{
1200	int rc = VINF_SUCCESS;
1201	uint32_t const cPages = VMX_V_VMCS_PAGES
1202	+ VMX_V_SHADOW_VMCS_PAGES
1203	+ VMX_V_VIRT_APIC_PAGES
1204	+ (2 * VMX_V_VMREAD_VMWRITE_BITMAP_PAGES)
1205	+ (3 * VMX_V_AUTOMSR_AREA_PAGES)
1206	+ VMX_V_MSR_BITMAP_PAGES
1207	+ (VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES);
1208	LogRel(("CPUM: Allocating %u pages for the nested-guest VMCS and related structures\n", pVM->cCpus * cPages));
1209	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1210	{
1211	PVMCPU pVCpu = pVM->apCpusR3[i];
1212	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1213	pCtx->hwvirt.enmHwvirt = CPUMHWVIRT_VMX;
1214
1215	/*
1216	* Allocate the nested-guest current VMCS.
1217	*/
1218	pCtx->hwvirt.vmx.pVmcsR3 = (PVMXVVMCS)SUPR3ContAlloc(VMX_V_VMCS_PAGES,
1219	&pCtx->hwvirt.vmx.pVmcsR0,
1220	&pCtx->hwvirt.vmx.HCPhysVmcs);
1221	if (pCtx->hwvirt.vmx.pVmcsR3)
1222	{ /* likely */ }
1223	else
1224	{
1225	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMCS\n", pVCpu->idCpu, VMX_V_VMCS_PAGES));
1226	break;
1227	}
1228
1229	/*
1230	* Allocate the nested-guest shadow VMCS.
1231	*/
1232	pCtx->hwvirt.vmx.pShadowVmcsR3 = (PVMXVVMCS)SUPR3ContAlloc(VMX_V_VMCS_PAGES,
1233	&pCtx->hwvirt.vmx.pShadowVmcsR0,
1234	&pCtx->hwvirt.vmx.HCPhysShadowVmcs);
1235	if (pCtx->hwvirt.vmx.pShadowVmcsR3)
1236	{ /* likely */ }
1237	else
1238	{
1239	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's shadow VMCS\n", pVCpu->idCpu, VMX_V_VMCS_PAGES));
1240	break;
1241	}
1242
1243	/*
1244	* Allocate the virtual-APIC page.
1245	*/
1246	pCtx->hwvirt.vmx.pvVirtApicPageR3 = SUPR3ContAlloc(VMX_V_VIRT_APIC_PAGES,
1247	&pCtx->hwvirt.vmx.pvVirtApicPageR0,
1248	&pCtx->hwvirt.vmx.HCPhysVirtApicPage);
1249	if (pCtx->hwvirt.vmx.pvVirtApicPageR3)
1250	{ /* likely */ }
1251	else
1252	{
1253	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's virtual-APIC page\n", pVCpu->idCpu,
1254	VMX_V_VIRT_APIC_PAGES));
1255	break;
1256	}
1257
1258	/*
1259	* Allocate the VMREAD-bitmap.
1260	*/
1261	pCtx->hwvirt.vmx.pvVmreadBitmapR3 = SUPR3ContAlloc(VMX_V_VMREAD_VMWRITE_BITMAP_PAGES,
1262	&pCtx->hwvirt.vmx.pvVmreadBitmapR0,
1263	&pCtx->hwvirt.vmx.HCPhysVmreadBitmap);
1264	if (pCtx->hwvirt.vmx.pvVmreadBitmapR3)
1265	{ /* likely */ }
1266	else
1267	{
1268	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMREAD-bitmap\n", pVCpu->idCpu,
1269	VMX_V_VMREAD_VMWRITE_BITMAP_PAGES));
1270	break;
1271	}
1272
1273	/*
1274	* Allocatge the VMWRITE-bitmap.
1275	*/
1276	pCtx->hwvirt.vmx.pvVmwriteBitmapR3 = SUPR3ContAlloc(VMX_V_VMREAD_VMWRITE_BITMAP_PAGES,
1277	&pCtx->hwvirt.vmx.pvVmwriteBitmapR0,
1278	&pCtx->hwvirt.vmx.HCPhysVmwriteBitmap);
1279	if (pCtx->hwvirt.vmx.pvVmwriteBitmapR3)
1280	{ /* likely */ }
1281	else
1282	{
1283	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMWRITE-bitmap\n", pVCpu->idCpu,
1284	VMX_V_VMREAD_VMWRITE_BITMAP_PAGES));
1285	break;
1286	}
1287
1288	/*
1289	* Allocate the VM-entry MSR-load area.
1290	*/
1291	pCtx->hwvirt.vmx.pEntryMsrLoadAreaR3 = (PVMXAUTOMSR)SUPR3ContAlloc(VMX_V_AUTOMSR_AREA_PAGES,
1292	&pCtx->hwvirt.vmx.pEntryMsrLoadAreaR0,
1293	&pCtx->hwvirt.vmx.HCPhysEntryMsrLoadArea);
1294	if (pCtx->hwvirt.vmx.pEntryMsrLoadAreaR3)
1295	{ /* likely */ }
1296	else
1297	{
1298	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VM-entry MSR-load area\n", pVCpu->idCpu,
1299	VMX_V_AUTOMSR_AREA_PAGES));
1300	break;
1301	}
1302
1303	/*
1304	* Allocate the VM-exit MSR-store area.
1305	*/
1306	pCtx->hwvirt.vmx.pExitMsrStoreAreaR3 = (PVMXAUTOMSR)SUPR3ContAlloc(VMX_V_AUTOMSR_AREA_PAGES,
1307	&pCtx->hwvirt.vmx.pExitMsrStoreAreaR0,
1308	&pCtx->hwvirt.vmx.HCPhysExitMsrStoreArea);
1309	if (pCtx->hwvirt.vmx.pExitMsrStoreAreaR3)
1310	{ /* likely */ }
1311	else
1312	{
1313	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VM-exit MSR-store area\n", pVCpu->idCpu,
1314	VMX_V_AUTOMSR_AREA_PAGES));
1315	break;
1316	}
1317
1318	/*
1319	* Allocate the VM-exit MSR-load area.
1320	*/
1321	pCtx->hwvirt.vmx.pExitMsrLoadAreaR3 = (PVMXAUTOMSR)SUPR3ContAlloc(VMX_V_AUTOMSR_AREA_PAGES,
1322	&pCtx->hwvirt.vmx.pExitMsrLoadAreaR0,
1323	&pCtx->hwvirt.vmx.HCPhysExitMsrLoadArea);
1324	if (pCtx->hwvirt.vmx.pExitMsrLoadAreaR3)
1325	{ /* likely */ }
1326	else
1327	{
1328	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VM-exit MSR-load area\n", pVCpu->idCpu,
1329	VMX_V_AUTOMSR_AREA_PAGES));
1330	break;
1331	}
1332
1333	/*
1334	* Allocate the MSR bitmap.
1335	*/
1336	pCtx->hwvirt.vmx.pvMsrBitmapR3 = SUPR3ContAlloc(VMX_V_MSR_BITMAP_PAGES,
1337	&pCtx->hwvirt.vmx.pvMsrBitmapR0,
1338	&pCtx->hwvirt.vmx.HCPhysMsrBitmap);
1339	if (pCtx->hwvirt.vmx.pvMsrBitmapR3)
1340	{ /* likely */ }
1341	else
1342	{
1343	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's MSR bitmap\n", pVCpu->idCpu,
1344	VMX_V_MSR_BITMAP_PAGES));
1345	break;
1346	}
1347
1348	/*
1349	* Allocate the I/O bitmaps (A and B).
1350	*/
1351	pCtx->hwvirt.vmx.pvIoBitmapR3 = SUPR3ContAlloc(VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES,
1352	&pCtx->hwvirt.vmx.pvIoBitmapR0,
1353	&pCtx->hwvirt.vmx.HCPhysIoBitmap);
1354	if (pCtx->hwvirt.vmx.pvIoBitmapR3)
1355	{ /* likely */ }
1356	else
1357	{
1358	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's I/O bitmaps\n", pVCpu->idCpu,
1359	VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES));
1360	break;
1361	}
1362
1363	/*
1364	* Zero out all allocated pages (should compress well for saved-state).
1365	*/
1366	memset(pCtx->hwvirt.vmx.CTX_SUFF(pVmcs), 0, VMX_V_VMCS_SIZE);
1367	memset(pCtx->hwvirt.vmx.CTX_SUFF(pShadowVmcs), 0, VMX_V_SHADOW_VMCS_SIZE);
1368	memset(pCtx->hwvirt.vmx.CTX_SUFF(pvVirtApicPage), 0, VMX_V_VIRT_APIC_SIZE);
1369	memset(pCtx->hwvirt.vmx.CTX_SUFF(pvVmreadBitmap), 0, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
1370	memset(pCtx->hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap), 0, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
1371	memset(pCtx->hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea), 0, VMX_V_AUTOMSR_AREA_SIZE);
1372	memset(pCtx->hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea), 0, VMX_V_AUTOMSR_AREA_SIZE);
1373	memset(pCtx->hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea), 0, VMX_V_AUTOMSR_AREA_SIZE);
1374	memset(pCtx->hwvirt.vmx.CTX_SUFF(pvMsrBitmap), 0, VMX_V_MSR_BITMAP_SIZE);
1375	memset(pCtx->hwvirt.vmx.CTX_SUFF(pvIoBitmap), 0, VMX_V_IO_BITMAP_A_SIZE + VMX_V_IO_BITMAP_B_SIZE);
1376	}
1377
1378	/* On any failure, cleanup. */
1379	if (RT_FAILURE(rc))
1380	cpumR3FreeVmxHwVirtState(pVM);
1381
1382	return rc;
1383	}
1384
1385
1386	/**
1387	* Resets per-VCPU VMX hardware virtualization state.
1388	*
1389	* @param pVCpu The cross context virtual CPU structure.
1390	*/
1391	DECLINLINE(void) cpumR3ResetVmxHwVirtState(PVMCPU pVCpu)
1392	{
1393	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1394	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_VMX);
1395	Assert(pCtx->hwvirt.vmx.CTX_SUFF(pVmcs));
1396	Assert(pCtx->hwvirt.vmx.CTX_SUFF(pShadowVmcs));
1397
1398	memset(pCtx->hwvirt.vmx.CTX_SUFF(pVmcs), 0, VMX_V_VMCS_SIZE);
1399	memset(pCtx->hwvirt.vmx.CTX_SUFF(pShadowVmcs), 0, VMX_V_SHADOW_VMCS_SIZE);
1400	pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1401	pCtx->hwvirt.vmx.GCPhysShadowVmcs = NIL_RTGCPHYS;
1402	pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1403	pCtx->hwvirt.vmx.fInVmxRootMode = false;
1404	pCtx->hwvirt.vmx.fInVmxNonRootMode = false;
1405	/* Don't reset diagnostics here. */
1406	}
1407
1408
1409	/**
1410	* Displays the host and guest VMX features.
1411	*
1412	* @param pVM The cross context VM structure.
1413	* @param pHlp The info helper functions.
1414	* @param pszArgs "terse", "default" or "verbose".
1415	*/
1416	DECLCALLBACK(void) cpumR3InfoVmxFeatures(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1417	{
1418	RT_NOREF(pszArgs);
1419	PCCPUMFEATURES pHostFeatures = &pVM->cpum.s.HostFeatures;
1420	PCCPUMFEATURES pGuestFeatures = &pVM->cpum.s.GuestFeatures;
1421	if ( pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL
1422	\|\| pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_VIA
1423	\|\| pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_SHANGHAI)
1424	{
1425	#define VMXFEATDUMP(a_szDesc, a_Var) \
1426	pHlp->pfnPrintf(pHlp, " %s = %u (%u)\n", a_szDesc, pGuestFeatures->a_Var, pHostFeatures->a_Var)
1427
1428	pHlp->pfnPrintf(pHlp, "Nested hardware virtualization - VMX features\n");
1429	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
1430	VMXFEATDUMP("VMX - Virtual-Machine Extensions ", fVmx);
1431	/* Basic. */
1432	VMXFEATDUMP("InsOutInfo - INS/OUTS instruction info. ", fVmxInsOutInfo);
1433	/* Pin-based controls. */
1434	VMXFEATDUMP("ExtIntExit - External interrupt exiting ", fVmxExtIntExit);
1435	VMXFEATDUMP("NmiExit - NMI exiting ", fVmxNmiExit);
1436	VMXFEATDUMP("VirtNmi - Virtual NMIs ", fVmxVirtNmi);
1437	VMXFEATDUMP("PreemptTimer - VMX preemption timer ", fVmxPreemptTimer);
1438	VMXFEATDUMP("PostedInt - Posted interrupts ", fVmxPostedInt);
1439	/* Processor-based controls. */
1440	VMXFEATDUMP("IntWindowExit - Interrupt-window exiting ", fVmxIntWindowExit);
1441	VMXFEATDUMP("TscOffsetting - TSC offsetting ", fVmxTscOffsetting);
1442	VMXFEATDUMP("HltExit - HLT exiting ", fVmxHltExit);
1443	VMXFEATDUMP("InvlpgExit - INVLPG exiting ", fVmxInvlpgExit);
1444	VMXFEATDUMP("MwaitExit - MWAIT exiting ", fVmxMwaitExit);
1445	VMXFEATDUMP("RdpmcExit - RDPMC exiting ", fVmxRdpmcExit);
1446	VMXFEATDUMP("RdtscExit - RDTSC exiting ", fVmxRdtscExit);
1447	VMXFEATDUMP("Cr3LoadExit - CR3-load exiting ", fVmxCr3LoadExit);
1448	VMXFEATDUMP("Cr3StoreExit - CR3-store exiting ", fVmxCr3StoreExit);
1449	VMXFEATDUMP("Cr8LoadExit - CR8-load exiting ", fVmxCr8LoadExit);
1450	VMXFEATDUMP("Cr8StoreExit - CR8-store exiting ", fVmxCr8StoreExit);
1451	VMXFEATDUMP("UseTprShadow - Use TPR shadow ", fVmxUseTprShadow);
1452	VMXFEATDUMP("NmiWindowExit - NMI-window exiting ", fVmxNmiWindowExit);
1453	VMXFEATDUMP("MovDRxExit - Mov-DR exiting ", fVmxMovDRxExit);
1454	VMXFEATDUMP("UncondIoExit - Unconditional I/O exiting ", fVmxUncondIoExit);
1455	VMXFEATDUMP("UseIoBitmaps - Use I/O bitmaps ", fVmxUseIoBitmaps);
1456	VMXFEATDUMP("MonitorTrapFlag - Monitor Trap Flag ", fVmxMonitorTrapFlag);
1457	VMXFEATDUMP("UseMsrBitmaps - MSR bitmaps ", fVmxUseMsrBitmaps);
1458	VMXFEATDUMP("MonitorExit - MONITOR exiting ", fVmxMonitorExit);
1459	VMXFEATDUMP("PauseExit - PAUSE exiting ", fVmxPauseExit);
1460	VMXFEATDUMP("SecondaryExecCtl - Activate secondary controls ", fVmxSecondaryExecCtls);
1461	/* Secondary processor-based controls. */
1462	VMXFEATDUMP("VirtApic - Virtualize-APIC accesses ", fVmxVirtApicAccess);
1463	VMXFEATDUMP("Ept - Extended Page Tables ", fVmxEpt);
1464	VMXFEATDUMP("DescTableExit - Descriptor-table exiting ", fVmxDescTableExit);
1465	VMXFEATDUMP("Rdtscp - Enable RDTSCP ", fVmxRdtscp);
1466	VMXFEATDUMP("VirtX2ApicMode - Virtualize-x2APIC mode ", fVmxVirtX2ApicMode);
1467	VMXFEATDUMP("Vpid - Enable VPID ", fVmxVpid);
1468	VMXFEATDUMP("WbinvdExit - WBINVD exiting ", fVmxWbinvdExit);
1469	VMXFEATDUMP("UnrestrictedGuest - Unrestricted guest ", fVmxUnrestrictedGuest);
1470	VMXFEATDUMP("ApicRegVirt - APIC-register virtualization ", fVmxApicRegVirt);
1471	VMXFEATDUMP("VirtIntDelivery - Virtual-interrupt delivery ", fVmxVirtIntDelivery);
1472	VMXFEATDUMP("PauseLoopExit - PAUSE-loop exiting ", fVmxPauseLoopExit);
1473	VMXFEATDUMP("RdrandExit - RDRAND exiting ", fVmxRdrandExit);
1474	VMXFEATDUMP("Invpcid - Enable INVPCID ", fVmxInvpcid);
1475	VMXFEATDUMP("VmFuncs - Enable VM Functions ", fVmxVmFunc);
1476	VMXFEATDUMP("VmcsShadowing - VMCS shadowing ", fVmxVmcsShadowing);
1477	VMXFEATDUMP("RdseedExiting - RDSEED exiting ", fVmxRdseedExit);
1478	VMXFEATDUMP("PML - Page-Modification Log (PML) ", fVmxPml);
1479	VMXFEATDUMP("EptVe - EPT violations can cause #VE ", fVmxEptXcptVe);
1480	VMXFEATDUMP("XsavesXRstors - Enable XSAVES/XRSTORS ", fVmxXsavesXrstors);
1481	/* VM-entry controls. */
1482	VMXFEATDUMP("EntryLoadDebugCtls - Load debug controls on VM-entry ", fVmxEntryLoadDebugCtls);
1483	VMXFEATDUMP("Ia32eModeGuest - IA-32e mode guest ", fVmxIa32eModeGuest);
1484	VMXFEATDUMP("EntryLoadEferMsr - Load IA32_EFER MSR on VM-entry ", fVmxEntryLoadEferMsr);
1485	VMXFEATDUMP("EntryLoadPatMsr - Load IA32_PAT MSR on VM-entry ", fVmxEntryLoadPatMsr);
1486	/* VM-exit controls. */
1487	VMXFEATDUMP("ExitSaveDebugCtls - Save debug controls on VM-exit ", fVmxExitSaveDebugCtls);
1488	VMXFEATDUMP("HostAddrSpaceSize - Host address-space size ", fVmxHostAddrSpaceSize);
1489	VMXFEATDUMP("ExitAckExtInt - Acknowledge interrupt on VM-exit ", fVmxExitAckExtInt);
1490	VMXFEATDUMP("ExitSavePatMsr - Save IA32_PAT MSR on VM-exit ", fVmxExitSavePatMsr);
1491	VMXFEATDUMP("ExitLoadPatMsr - Load IA32_PAT MSR on VM-exit ", fVmxExitLoadPatMsr);
1492	VMXFEATDUMP("ExitSaveEferMsr - Save IA32_EFER MSR on VM-exit ", fVmxExitSaveEferMsr);
1493	VMXFEATDUMP("ExitLoadEferMsr - Load IA32_EFER MSR on VM-exit ", fVmxExitLoadEferMsr);
1494	VMXFEATDUMP("SavePreemptTimer - Save VMX-preemption timer ", fVmxSavePreemptTimer);
1495	/* Miscellaneous data. */
1496	VMXFEATDUMP("ExitSaveEferLma - Save IA32_EFER.LMA on VM-exit ", fVmxExitSaveEferLma);
1497	VMXFEATDUMP("IntelPt - Intel PT (Processor Trace) in VMX operation ", fVmxIntelPt);
1498	VMXFEATDUMP("VmwriteAll - VMWRITE to any supported VMCS field ", fVmxVmwriteAll);
1499	VMXFEATDUMP("EntryInjectSoftInt - Inject softint. with 0-len instr. ", fVmxEntryInjectSoftInt);
1500	#undef VMXFEATDUMP
1501	}
1502	else
1503	pHlp->pfnPrintf(pHlp, "No VMX features present - requires an Intel or compatible CPU.\n");
1504	}
1505
1506
1507	/**
1508	* Checks whether nested-guest execution using hardware-assisted VMX (e.g, using HM
1509	* or NEM) is allowed.
1510	*
1511	* @returns @c true if hardware-assisted nested-guest execution is allowed, @c false
1512	* otherwise.
1513	* @param pVM The cross context VM structure.
1514	*/
1515	static bool cpumR3IsHwAssistNstGstExecAllowed(PVM pVM)
1516	{
1517	AssertMsg(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET, ("Calling this function too early!\n"));
1518	#ifndef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
1519	if ( pVM->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT
1520	\|\| pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1521	return true;
1522	#else
1523	NOREF(pVM);
1524	#endif
1525	return false;
1526	}
1527
1528
1529	/**
1530	* Initializes the VMX guest MSRs from guest CPU features based on the host MSRs.
1531	*
1532	* @param pVM The cross context VM structure.
1533	* @param pHostVmxMsrs The host VMX MSRs. Pass NULL when fully emulating VMX
1534	* and no hardware-assisted nested-guest execution is
1535	* possible for this VM.
1536	* @param pGuestFeatures The guest features to use (only VMX features are
1537	* accessed).
1538	* @param pGuestVmxMsrs Where to store the initialized guest VMX MSRs.
1539	*
1540	* @remarks This function ASSUMES the VMX guest-features are already exploded!
1541	*/
1542	static void cpumR3InitVmxGuestMsrs(PVM pVM, PCVMXMSRS pHostVmxMsrs, PCCPUMFEATURES pGuestFeatures, PVMXMSRS pGuestVmxMsrs)
1543	{
1544	bool const fIsNstGstHwExecAllowed = cpumR3IsHwAssistNstGstExecAllowed(pVM);
1545
1546	Assert(!fIsNstGstHwExecAllowed \|\| pHostVmxMsrs);
1547	Assert(pGuestFeatures->fVmx);
1548
1549	/*
1550	* We don't support the following MSRs yet:
1551	* - True Pin-based VM-execution controls.
1552	* - True Processor-based VM-execution controls.
1553	* - True VM-entry VM-execution controls.
1554	* - True VM-exit VM-execution controls.
1555	*/
1556
1557	/* Feature control. */
1558	pGuestVmxMsrs->u64FeatCtrl = MSR_IA32_FEATURE_CONTROL_LOCK \| MSR_IA32_FEATURE_CONTROL_VMXON;
1559
1560	/* Basic information. */
1561	{
1562	uint64_t const u64Basic = RT_BF_MAKE(VMX_BF_BASIC_VMCS_ID, VMX_V_VMCS_REVISION_ID )
1563	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_SIZE, VMX_V_VMCS_SIZE )
1564	\| RT_BF_MAKE(VMX_BF_BASIC_PHYSADDR_WIDTH, !pGuestFeatures->fLongMode )
1565	\| RT_BF_MAKE(VMX_BF_BASIC_DUAL_MON, 0 )
1566	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_MEM_TYPE, VMX_BASIC_MEM_TYPE_WB )
1567	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_INS_OUTS, pGuestFeatures->fVmxInsOutInfo)
1568	\| RT_BF_MAKE(VMX_BF_BASIC_TRUE_CTLS, 0 );
1569	pGuestVmxMsrs->u64Basic = u64Basic;
1570	}
1571
1572	/* Pin-based VM-execution controls. */
1573	{
1574	uint32_t const fFeatures = (pGuestFeatures->fVmxExtIntExit << VMX_BF_PIN_CTLS_EXT_INT_EXIT_SHIFT )
1575	\| (pGuestFeatures->fVmxNmiExit << VMX_BF_PIN_CTLS_NMI_EXIT_SHIFT )
1576	\| (pGuestFeatures->fVmxVirtNmi << VMX_BF_PIN_CTLS_VIRT_NMI_SHIFT )
1577	\| (pGuestFeatures->fVmxPreemptTimer << VMX_BF_PIN_CTLS_PREEMPT_TIMER_SHIFT)
1578	\| (pGuestFeatures->fVmxPostedInt << VMX_BF_PIN_CTLS_POSTED_INT_SHIFT );
1579	uint32_t const fAllowed0 = VMX_PIN_CTLS_DEFAULT1;
1580	uint32_t const fAllowed1 = fFeatures \| VMX_PIN_CTLS_DEFAULT1;
1581	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n",
1582	fAllowed0, fAllowed1, fFeatures));
1583	pGuestVmxMsrs->PinCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1584	}
1585
1586	/* Processor-based VM-execution controls. */
1587	{
1588	uint32_t const fFeatures = (pGuestFeatures->fVmxIntWindowExit << VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_SHIFT )
1589	\| (pGuestFeatures->fVmxTscOffsetting << VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_SHIFT)
1590	\| (pGuestFeatures->fVmxHltExit << VMX_BF_PROC_CTLS_HLT_EXIT_SHIFT )
1591	\| (pGuestFeatures->fVmxInvlpgExit << VMX_BF_PROC_CTLS_INVLPG_EXIT_SHIFT )
1592	\| (pGuestFeatures->fVmxMwaitExit << VMX_BF_PROC_CTLS_MWAIT_EXIT_SHIFT )
1593	\| (pGuestFeatures->fVmxRdpmcExit << VMX_BF_PROC_CTLS_RDPMC_EXIT_SHIFT )
1594	\| (pGuestFeatures->fVmxRdtscExit << VMX_BF_PROC_CTLS_RDTSC_EXIT_SHIFT )
1595	\| (pGuestFeatures->fVmxCr3LoadExit << VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_SHIFT )
1596	\| (pGuestFeatures->fVmxCr3StoreExit << VMX_BF_PROC_CTLS_CR3_STORE_EXIT_SHIFT )
1597	\| (pGuestFeatures->fVmxCr8LoadExit << VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_SHIFT )
1598	\| (pGuestFeatures->fVmxCr8StoreExit << VMX_BF_PROC_CTLS_CR8_STORE_EXIT_SHIFT )
1599	\| (pGuestFeatures->fVmxUseTprShadow << VMX_BF_PROC_CTLS_USE_TPR_SHADOW_SHIFT )
1600	\| (pGuestFeatures->fVmxNmiWindowExit << VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_SHIFT )
1601	\| (pGuestFeatures->fVmxMovDRxExit << VMX_BF_PROC_CTLS_MOV_DR_EXIT_SHIFT )
1602	\| (pGuestFeatures->fVmxUncondIoExit << VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_SHIFT )
1603	\| (pGuestFeatures->fVmxUseIoBitmaps << VMX_BF_PROC_CTLS_USE_IO_BITMAPS_SHIFT )
1604	\| (pGuestFeatures->fVmxMonitorTrapFlag << VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_SHIFT )
1605	\| (pGuestFeatures->fVmxUseMsrBitmaps << VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_SHIFT )
1606	\| (pGuestFeatures->fVmxMonitorExit << VMX_BF_PROC_CTLS_MONITOR_EXIT_SHIFT )
1607	\| (pGuestFeatures->fVmxPauseExit << VMX_BF_PROC_CTLS_PAUSE_EXIT_SHIFT )
1608	\| (pGuestFeatures->fVmxSecondaryExecCtls << VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_SHIFT);
1609	uint32_t const fAllowed0 = VMX_PROC_CTLS_DEFAULT1;
1610	uint32_t const fAllowed1 = fFeatures \| VMX_PROC_CTLS_DEFAULT1;
1611	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1612	fAllowed1, fFeatures));
1613	pGuestVmxMsrs->ProcCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1614	}
1615
1616	/* Secondary processor-based VM-execution controls. */
1617	if (pGuestFeatures->fVmxSecondaryExecCtls)
1618	{
1619	uint32_t const fFeatures = (pGuestFeatures->fVmxVirtApicAccess << VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_SHIFT )
1620	\| (pGuestFeatures->fVmxEpt << VMX_BF_PROC_CTLS2_EPT_SHIFT )
1621	\| (pGuestFeatures->fVmxDescTableExit << VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_SHIFT )
1622	\| (pGuestFeatures->fVmxRdtscp << VMX_BF_PROC_CTLS2_RDTSCP_SHIFT )
1623	\| (pGuestFeatures->fVmxVirtX2ApicMode << VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_SHIFT )
1624	\| (pGuestFeatures->fVmxVpid << VMX_BF_PROC_CTLS2_VPID_SHIFT )
1625	\| (pGuestFeatures->fVmxWbinvdExit << VMX_BF_PROC_CTLS2_WBINVD_EXIT_SHIFT )
1626	\| (pGuestFeatures->fVmxUnrestrictedGuest << VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_SHIFT)
1627	\| (pGuestFeatures->fVmxApicRegVirt << VMX_BF_PROC_CTLS2_APIC_REG_VIRT_SHIFT )
1628	\| (pGuestFeatures->fVmxVirtIntDelivery << VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_SHIFT )
1629	\| (pGuestFeatures->fVmxPauseLoopExit << VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_SHIFT )
1630	\| (pGuestFeatures->fVmxRdrandExit << VMX_BF_PROC_CTLS2_RDRAND_EXIT_SHIFT )
1631	\| (pGuestFeatures->fVmxInvpcid << VMX_BF_PROC_CTLS2_INVPCID_SHIFT )
1632	\| (pGuestFeatures->fVmxVmFunc << VMX_BF_PROC_CTLS2_VMFUNC_SHIFT )
1633	\| (pGuestFeatures->fVmxVmcsShadowing << VMX_BF_PROC_CTLS2_VMCS_SHADOWING_SHIFT )
1634	\| (pGuestFeatures->fVmxRdseedExit << VMX_BF_PROC_CTLS2_RDSEED_EXIT_SHIFT )
1635	\| (pGuestFeatures->fVmxPml << VMX_BF_PROC_CTLS2_PML_SHIFT )
1636	\| (pGuestFeatures->fVmxEptXcptVe << VMX_BF_PROC_CTLS2_EPT_VE_SHIFT )
1637	\| (pGuestFeatures->fVmxXsavesXrstors << VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_SHIFT )
1638	\| (pGuestFeatures->fVmxUseTscScaling << VMX_BF_PROC_CTLS2_TSC_SCALING_SHIFT );
1639	uint32_t const fAllowed0 = 0;
1640	uint32_t const fAllowed1 = fFeatures;
1641	pGuestVmxMsrs->ProcCtls2.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1642	}
1643
1644	/* VM-exit controls. */
1645	{
1646	uint32_t const fFeatures = (pGuestFeatures->fVmxExitSaveDebugCtls << VMX_BF_EXIT_CTLS_SAVE_DEBUG_SHIFT )
1647	\| (pGuestFeatures->fVmxHostAddrSpaceSize << VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_SHIFT)
1648	\| (pGuestFeatures->fVmxExitAckExtInt << VMX_BF_EXIT_CTLS_ACK_EXT_INT_SHIFT )
1649	\| (pGuestFeatures->fVmxExitSavePatMsr << VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_SHIFT )
1650	\| (pGuestFeatures->fVmxExitLoadPatMsr << VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_SHIFT )
1651	\| (pGuestFeatures->fVmxExitSaveEferMsr << VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_SHIFT )
1652	\| (pGuestFeatures->fVmxExitLoadEferMsr << VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_SHIFT )
1653	\| (pGuestFeatures->fVmxSavePreemptTimer << VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_SHIFT );
1654	/* Set the default1 class bits. See Intel spec. A.4 "VM-exit Controls". */
1655	uint32_t const fAllowed0 = VMX_EXIT_CTLS_DEFAULT1;
1656	uint32_t const fAllowed1 = fFeatures \| VMX_EXIT_CTLS_DEFAULT1;
1657	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1658	fAllowed1, fFeatures));
1659	pGuestVmxMsrs->ExitCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1660	}
1661
1662	/* VM-entry controls. */
1663	{
1664	uint32_t const fFeatures = (pGuestFeatures->fVmxEntryLoadDebugCtls << VMX_BF_ENTRY_CTLS_LOAD_DEBUG_SHIFT )
1665	\| (pGuestFeatures->fVmxIa32eModeGuest << VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_SHIFT)
1666	\| (pGuestFeatures->fVmxEntryLoadEferMsr << VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_SHIFT )
1667	\| (pGuestFeatures->fVmxEntryLoadPatMsr << VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_SHIFT );
1668	uint32_t const fAllowed0 = VMX_ENTRY_CTLS_DEFAULT1;
1669	uint32_t const fAllowed1 = fFeatures \| VMX_ENTRY_CTLS_DEFAULT1;
1670	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed0=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1671	fAllowed1, fFeatures));
1672	pGuestVmxMsrs->EntryCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1673	}
1674
1675	/* Miscellaneous data. */
1676	{
1677	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Misc : 0;
1678
1679	uint8_t const cMaxMsrs = RT_MIN(RT_BF_GET(uHostMsr, VMX_BF_MISC_MAX_MSRS), VMX_V_AUTOMSR_COUNT_MAX);
1680	uint8_t const fActivityState = RT_BF_GET(uHostMsr, VMX_BF_MISC_ACTIVITY_STATES) & VMX_V_GUEST_ACTIVITY_STATE_MASK;
1681	pGuestVmxMsrs->u64Misc = RT_BF_MAKE(VMX_BF_MISC_PREEMPT_TIMER_TSC, VMX_V_PREEMPT_TIMER_SHIFT )
1682	\| RT_BF_MAKE(VMX_BF_MISC_EXIT_SAVE_EFER_LMA, pGuestFeatures->fVmxExitSaveEferLma )
1683	\| RT_BF_MAKE(VMX_BF_MISC_ACTIVITY_STATES, fActivityState )
1684	\| RT_BF_MAKE(VMX_BF_MISC_INTEL_PT, pGuestFeatures->fVmxIntelPt )
1685	\| RT_BF_MAKE(VMX_BF_MISC_SMM_READ_SMBASE_MSR, 0 )
1686	\| RT_BF_MAKE(VMX_BF_MISC_CR3_TARGET, VMX_V_CR3_TARGET_COUNT )
1687	\| RT_BF_MAKE(VMX_BF_MISC_MAX_MSRS, cMaxMsrs )
1688	\| RT_BF_MAKE(VMX_BF_MISC_VMXOFF_BLOCK_SMI, 0 )
1689	\| RT_BF_MAKE(VMX_BF_MISC_VMWRITE_ALL, pGuestFeatures->fVmxVmwriteAll )
1690	\| RT_BF_MAKE(VMX_BF_MISC_ENTRY_INJECT_SOFT_INT, pGuestFeatures->fVmxEntryInjectSoftInt)
1691	\| RT_BF_MAKE(VMX_BF_MISC_MSEG_ID, VMX_V_MSEG_REV_ID );
1692	}
1693
1694	/* CR0 Fixed-0. */
1695	pGuestVmxMsrs->u64Cr0Fixed0 = pGuestFeatures->fVmxUnrestrictedGuest ? VMX_V_CR0_FIXED0_UX : VMX_V_CR0_FIXED0;
1696
1697	/* CR0 Fixed-1. */
1698	{
1699	/*
1700	* All CPUs I've looked at so far report CR0 fixed-1 bits as 0xffffffff.
1701	* This is different from CR4 fixed-1 bits which are reported as per the
1702	* CPU features and/or micro-architecture/generation. Why? Ask Intel.
1703	*/
1704	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Cr0Fixed1 : 0xffffffff;
1705	pGuestVmxMsrs->u64Cr0Fixed1 = uHostMsr \| pGuestVmxMsrs->u64Cr0Fixed0; /* Make sure the CR0 MB1 bits are not clear. */
1706	}
1707
1708	/* CR4 Fixed-0. */
1709	pGuestVmxMsrs->u64Cr4Fixed0 = VMX_V_CR4_FIXED0;
1710
1711	/* CR4 Fixed-1. */
1712	{
1713	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Cr4Fixed1 : CPUMGetGuestCR4ValidMask(pVM);
1714	pGuestVmxMsrs->u64Cr4Fixed1 = uHostMsr \| pGuestVmxMsrs->u64Cr4Fixed0; /* Make sure the CR4 MB1 bits are not clear. */
1715	}
1716
1717	/* VMCS Enumeration. */
1718	pGuestVmxMsrs->u64VmcsEnum = VMX_V_VMCS_MAX_INDEX << VMX_BF_VMCS_ENUM_HIGHEST_IDX_SHIFT;
1719
1720	/* VPID and EPT Capabilities. */
1721	{
1722	/*
1723	* INVVPID instruction always causes a VM-exit unconditionally, so we are free to fake
1724	* and emulate any INVVPID flush type. However, it only makes sense to expose the types
1725	* when INVVPID instruction is supported just to be more compatible with guest
1726	* hypervisors that may make assumptions by only looking at this MSR even though they
1727	* are technically supposed to refer to bit 37 of MSR_IA32_VMX_PROC_CTLS2 first.
1728	*
1729	* See Intel spec. 25.1.2 "Instructions That Cause VM Exits Unconditionally".
1730	* See Intel spec. 30.3 "VMX Instructions".
1731	*/
1732	uint8_t const fVpid = pGuestFeatures->fVmxVpid;
1733	pGuestVmxMsrs->u64EptVpidCaps = RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID, fVpid)
1734	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX, fVpid & 1)
1735	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX, fVpid & 1)
1736	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS, fVpid & 1);
1737	}
1738
1739	/* VM Functions. */
1740	if (pGuestFeatures->fVmxVmFunc)
1741	pGuestVmxMsrs->u64VmFunc = RT_BF_MAKE(VMX_BF_VMFUNC_EPTP_SWITCHING, 1);
1742	}
1743
1744
1745	/**
1746	* Checks whether the given guest CPU VMX features are compatible with the provided
1747	* base features.
1748	*
1749	* @returns @c true if compatible, @c false otherwise.
1750	* @param pVM The cross context VM structure.
1751	* @param pBase The base VMX CPU features.
1752	* @param pGst The guest VMX CPU features.
1753	*
1754	* @remarks Only VMX feature bits are examined.
1755	*/
1756	static bool cpumR3AreVmxCpuFeaturesCompatible(PVM pVM, PCCPUMFEATURES pBase, PCCPUMFEATURES pGst)
1757	{
1758	if (cpumR3IsHwAssistNstGstExecAllowed(pVM))
1759	{
1760	uint64_t const fBase = ((uint64_t)pBase->fVmxInsOutInfo << 0) \| ((uint64_t)pBase->fVmxExtIntExit << 1)
1761	\| ((uint64_t)pBase->fVmxNmiExit << 2) \| ((uint64_t)pBase->fVmxVirtNmi << 3)
1762	\| ((uint64_t)pBase->fVmxPreemptTimer << 4) \| ((uint64_t)pBase->fVmxPostedInt << 5)
1763	\| ((uint64_t)pBase->fVmxIntWindowExit << 6) \| ((uint64_t)pBase->fVmxTscOffsetting << 7)
1764	\| ((uint64_t)pBase->fVmxHltExit << 8) \| ((uint64_t)pBase->fVmxInvlpgExit << 9)
1765	\| ((uint64_t)pBase->fVmxMwaitExit << 10) \| ((uint64_t)pBase->fVmxRdpmcExit << 11)
1766	\| ((uint64_t)pBase->fVmxRdtscExit << 12) \| ((uint64_t)pBase->fVmxCr3LoadExit << 13)
1767	\| ((uint64_t)pBase->fVmxCr3StoreExit << 14) \| ((uint64_t)pBase->fVmxCr8LoadExit << 15)
1768	\| ((uint64_t)pBase->fVmxCr8StoreExit << 16) \| ((uint64_t)pBase->fVmxUseTprShadow << 17)
1769	\| ((uint64_t)pBase->fVmxNmiWindowExit << 18) \| ((uint64_t)pBase->fVmxMovDRxExit << 19)
1770	\| ((uint64_t)pBase->fVmxUncondIoExit << 20) \| ((uint64_t)pBase->fVmxUseIoBitmaps << 21)
1771	\| ((uint64_t)pBase->fVmxMonitorTrapFlag << 22) \| ((uint64_t)pBase->fVmxUseMsrBitmaps << 23)
1772	\| ((uint64_t)pBase->fVmxMonitorExit << 24) \| ((uint64_t)pBase->fVmxPauseExit << 25)
1773	\| ((uint64_t)pBase->fVmxSecondaryExecCtls << 26) \| ((uint64_t)pBase->fVmxVirtApicAccess << 27)
1774	\| ((uint64_t)pBase->fVmxEpt << 28) \| ((uint64_t)pBase->fVmxDescTableExit << 29)
1775	\| ((uint64_t)pBase->fVmxRdtscp << 30) \| ((uint64_t)pBase->fVmxVirtX2ApicMode << 31)
1776	\| ((uint64_t)pBase->fVmxVpid << 32) \| ((uint64_t)pBase->fVmxWbinvdExit << 33)
1777	\| ((uint64_t)pBase->fVmxUnrestrictedGuest << 34) \| ((uint64_t)pBase->fVmxApicRegVirt << 35)
1778	\| ((uint64_t)pBase->fVmxVirtIntDelivery << 36) \| ((uint64_t)pBase->fVmxPauseLoopExit << 37)
1779	\| ((uint64_t)pBase->fVmxRdrandExit << 38) \| ((uint64_t)pBase->fVmxInvpcid << 39)
1780	\| ((uint64_t)pBase->fVmxVmFunc << 40) \| ((uint64_t)pBase->fVmxVmcsShadowing << 41)
1781	\| ((uint64_t)pBase->fVmxRdseedExit << 42) \| ((uint64_t)pBase->fVmxPml << 43)
1782	\| ((uint64_t)pBase->fVmxEptXcptVe << 44) \| ((uint64_t)pBase->fVmxXsavesXrstors << 45)
1783	\| ((uint64_t)pBase->fVmxUseTscScaling << 46) \| ((uint64_t)pBase->fVmxEntryLoadDebugCtls << 47)
1784	\| ((uint64_t)pBase->fVmxIa32eModeGuest << 48) \| ((uint64_t)pBase->fVmxEntryLoadEferMsr << 49)
1785	\| ((uint64_t)pBase->fVmxEntryLoadPatMsr << 50) \| ((uint64_t)pBase->fVmxExitSaveDebugCtls << 51)
1786	\| ((uint64_t)pBase->fVmxHostAddrSpaceSize << 52) \| ((uint64_t)pBase->fVmxExitAckExtInt << 53)
1787	\| ((uint64_t)pBase->fVmxExitSavePatMsr << 54) \| ((uint64_t)pBase->fVmxExitLoadPatMsr << 55)
1788	\| ((uint64_t)pBase->fVmxExitSaveEferMsr << 56) \| ((uint64_t)pBase->fVmxExitLoadEferMsr << 57)
1789	\| ((uint64_t)pBase->fVmxSavePreemptTimer << 58) \| ((uint64_t)pBase->fVmxExitSaveEferLma << 59)
1790	\| ((uint64_t)pBase->fVmxIntelPt << 60) \| ((uint64_t)pBase->fVmxVmwriteAll << 61)
1791	\| ((uint64_t)pBase->fVmxEntryInjectSoftInt << 62);
1792
1793	uint64_t const fGst = ((uint64_t)pGst->fVmxInsOutInfo << 0) \| ((uint64_t)pGst->fVmxExtIntExit << 1)
1794	\| ((uint64_t)pGst->fVmxNmiExit << 2) \| ((uint64_t)pGst->fVmxVirtNmi << 3)
1795	\| ((uint64_t)pGst->fVmxPreemptTimer << 4) \| ((uint64_t)pGst->fVmxPostedInt << 5)
1796	\| ((uint64_t)pGst->fVmxIntWindowExit << 6) \| ((uint64_t)pGst->fVmxTscOffsetting << 7)
1797	\| ((uint64_t)pGst->fVmxHltExit << 8) \| ((uint64_t)pGst->fVmxInvlpgExit << 9)
1798	\| ((uint64_t)pGst->fVmxMwaitExit << 10) \| ((uint64_t)pGst->fVmxRdpmcExit << 11)
1799	\| ((uint64_t)pGst->fVmxRdtscExit << 12) \| ((uint64_t)pGst->fVmxCr3LoadExit << 13)
1800	\| ((uint64_t)pGst->fVmxCr3StoreExit << 14) \| ((uint64_t)pGst->fVmxCr8LoadExit << 15)
1801	\| ((uint64_t)pGst->fVmxCr8StoreExit << 16) \| ((uint64_t)pGst->fVmxUseTprShadow << 17)
1802	\| ((uint64_t)pGst->fVmxNmiWindowExit << 18) \| ((uint64_t)pGst->fVmxMovDRxExit << 19)
1803	\| ((uint64_t)pGst->fVmxUncondIoExit << 20) \| ((uint64_t)pGst->fVmxUseIoBitmaps << 21)
1804	\| ((uint64_t)pGst->fVmxMonitorTrapFlag << 22) \| ((uint64_t)pGst->fVmxUseMsrBitmaps << 23)
1805	\| ((uint64_t)pGst->fVmxMonitorExit << 24) \| ((uint64_t)pGst->fVmxPauseExit << 25)
1806	\| ((uint64_t)pGst->fVmxSecondaryExecCtls << 26) \| ((uint64_t)pGst->fVmxVirtApicAccess << 27)
1807	\| ((uint64_t)pGst->fVmxEpt << 28) \| ((uint64_t)pGst->fVmxDescTableExit << 29)
1808	\| ((uint64_t)pGst->fVmxRdtscp << 30) \| ((uint64_t)pGst->fVmxVirtX2ApicMode << 31)
1809	\| ((uint64_t)pGst->fVmxVpid << 32) \| ((uint64_t)pGst->fVmxWbinvdExit << 33)
1810	\| ((uint64_t)pGst->fVmxUnrestrictedGuest << 34) \| ((uint64_t)pGst->fVmxApicRegVirt << 35)
1811	\| ((uint64_t)pGst->fVmxVirtIntDelivery << 36) \| ((uint64_t)pGst->fVmxPauseLoopExit << 37)
1812	\| ((uint64_t)pGst->fVmxRdrandExit << 38) \| ((uint64_t)pGst->fVmxInvpcid << 39)
1813	\| ((uint64_t)pGst->fVmxVmFunc << 40) \| ((uint64_t)pGst->fVmxVmcsShadowing << 41)
1814	\| ((uint64_t)pGst->fVmxRdseedExit << 42) \| ((uint64_t)pGst->fVmxPml << 43)
1815	\| ((uint64_t)pGst->fVmxEptXcptVe << 44) \| ((uint64_t)pGst->fVmxXsavesXrstors << 45)
1816	\| ((uint64_t)pGst->fVmxUseTscScaling << 46) \| ((uint64_t)pGst->fVmxEntryLoadDebugCtls << 47)
1817	\| ((uint64_t)pGst->fVmxIa32eModeGuest << 48) \| ((uint64_t)pGst->fVmxEntryLoadEferMsr << 49)
1818	\| ((uint64_t)pGst->fVmxEntryLoadPatMsr << 50) \| ((uint64_t)pGst->fVmxExitSaveDebugCtls << 51)
1819	\| ((uint64_t)pGst->fVmxHostAddrSpaceSize << 52) \| ((uint64_t)pGst->fVmxExitAckExtInt << 53)
1820	\| ((uint64_t)pGst->fVmxExitSavePatMsr << 54) \| ((uint64_t)pGst->fVmxExitLoadPatMsr << 55)
1821	\| ((uint64_t)pGst->fVmxExitSaveEferMsr << 56) \| ((uint64_t)pGst->fVmxExitLoadEferMsr << 57)
1822	\| ((uint64_t)pGst->fVmxSavePreemptTimer << 58) \| ((uint64_t)pGst->fVmxExitSaveEferLma << 59)
1823	\| ((uint64_t)pGst->fVmxIntelPt << 60) \| ((uint64_t)pGst->fVmxVmwriteAll << 61)
1824	\| ((uint64_t)pGst->fVmxEntryInjectSoftInt << 62);
1825
1826	if ((fBase \| fGst) != fBase)
1827	{
1828	uint64_t const fDiff = fBase ^ fGst;
1829	LogRel(("CPUM: VMX features now exposed to the guest are incompatible with those from the saved state. fBase=%#RX64 fGst=%#RX64 fDiff=%#RX64\n",
1830	fBase, fGst, fDiff));
1831	return false;
1832	}
1833	return true;
1834	}
1835	return true;
1836	}
1837
1838
1839	/**
1840	* Initializes VMX guest features and MSRs.
1841	*
1842	* @param pVM The cross context VM structure.
1843	* @param pHostVmxMsrs The host VMX MSRs. Pass NULL when fully emulating VMX
1844	* and no hardware-assisted nested-guest execution is
1845	* possible for this VM.
1846	* @param pGuestVmxMsrs Where to store the initialized guest VMX MSRs.
1847	*/
1848	void cpumR3InitVmxGuestFeaturesAndMsrs(PVM pVM, PCVMXMSRS pHostVmxMsrs, PVMXMSRS pGuestVmxMsrs)
1849	{
1850	Assert(pVM);
1851	Assert(pGuestVmxMsrs);
1852
1853	/*
1854	* Initialize the set of VMX features we emulate.
1855	*
1856	* Note! Some bits might be reported as 1 always if they fall under the
1857	* default1 class bits (e.g. fVmxEntryLoadDebugCtls), see @bugref{9180#c5}.
1858	*/
1859	CPUMFEATURES EmuFeat;
1860	RT_ZERO(EmuFeat);
1861	EmuFeat.fVmx = 1;
1862	EmuFeat.fVmxInsOutInfo = 1;
1863	EmuFeat.fVmxExtIntExit = 1;
1864	EmuFeat.fVmxNmiExit = 1;
1865	EmuFeat.fVmxVirtNmi = 0;
1866	EmuFeat.fVmxPreemptTimer = 0; /** @todo NSTVMX: enable this. */
1867	EmuFeat.fVmxPostedInt = 0;
1868	EmuFeat.fVmxIntWindowExit = 1;
1869	EmuFeat.fVmxTscOffsetting = 1;
1870	EmuFeat.fVmxHltExit = 1;
1871	EmuFeat.fVmxInvlpgExit = 1;
1872	EmuFeat.fVmxMwaitExit = 1;
1873	EmuFeat.fVmxRdpmcExit = 1;
1874	EmuFeat.fVmxRdtscExit = 1;
1875	EmuFeat.fVmxCr3LoadExit = 1;
1876	EmuFeat.fVmxCr3StoreExit = 1;
1877	EmuFeat.fVmxCr8LoadExit = 1;
1878	EmuFeat.fVmxCr8StoreExit = 1;
1879	EmuFeat.fVmxUseTprShadow = 1;
1880	EmuFeat.fVmxNmiWindowExit = 0;
1881	EmuFeat.fVmxMovDRxExit = 1;
1882	EmuFeat.fVmxUncondIoExit = 1;
1883	EmuFeat.fVmxUseIoBitmaps = 1;
1884	EmuFeat.fVmxMonitorTrapFlag = 0;
1885	EmuFeat.fVmxUseMsrBitmaps = 1;
1886	EmuFeat.fVmxMonitorExit = 1;
1887	EmuFeat.fVmxPauseExit = 1;
1888	EmuFeat.fVmxSecondaryExecCtls = 1;
1889	EmuFeat.fVmxVirtApicAccess = 1;
1890	EmuFeat.fVmxEpt = 0; /* Cannot be disabled if unrestricted guest is enabled. */
1891	EmuFeat.fVmxDescTableExit = 1;
1892	EmuFeat.fVmxRdtscp = 1;
1893	EmuFeat.fVmxVirtX2ApicMode = 0;
1894	EmuFeat.fVmxVpid = 0; /** @todo NSTVMX: enable this. */
1895	EmuFeat.fVmxWbinvdExit = 1;
1896	EmuFeat.fVmxUnrestrictedGuest = 0;
1897	EmuFeat.fVmxApicRegVirt = 0;
1898	EmuFeat.fVmxVirtIntDelivery = 0;
1899	EmuFeat.fVmxPauseLoopExit = 0;
1900	EmuFeat.fVmxRdrandExit = 0;
1901	EmuFeat.fVmxInvpcid = 1;
1902	EmuFeat.fVmxVmFunc = 0;
1903	EmuFeat.fVmxVmcsShadowing = 0;
1904	EmuFeat.fVmxRdseedExit = 0;
1905	EmuFeat.fVmxPml = 0;
1906	EmuFeat.fVmxEptXcptVe = 0;
1907	EmuFeat.fVmxXsavesXrstors = 0;
1908	EmuFeat.fVmxUseTscScaling = 0;
1909	EmuFeat.fVmxEntryLoadDebugCtls = 1;
1910	EmuFeat.fVmxIa32eModeGuest = 1;
1911	EmuFeat.fVmxEntryLoadEferMsr = 1;
1912	EmuFeat.fVmxEntryLoadPatMsr = 0;
1913	EmuFeat.fVmxExitSaveDebugCtls = 1;
1914	EmuFeat.fVmxHostAddrSpaceSize = 1;
1915	EmuFeat.fVmxExitAckExtInt = 1;
1916	EmuFeat.fVmxExitSavePatMsr = 0;
1917	EmuFeat.fVmxExitLoadPatMsr = 0;
1918	EmuFeat.fVmxExitSaveEferMsr = 1;
1919	EmuFeat.fVmxExitLoadEferMsr = 1;
1920	EmuFeat.fVmxSavePreemptTimer = 0;
1921	EmuFeat.fVmxExitSaveEferLma = 1; /* Cannot be disabled if unrestricted guest is enabled. */
1922	EmuFeat.fVmxIntelPt = 0;
1923	EmuFeat.fVmxVmwriteAll = 0; /** @todo NSTVMX: enable this when nested VMCS shadowing is enabled. */
1924	EmuFeat.fVmxEntryInjectSoftInt = 1;
1925
1926	/*
1927	* Merge guest features.
1928	*
1929	* When hardware-assisted VMX may be used, any feature we emulate must also be supported
1930	* by the hardware, hence we merge our emulated features with the host features below.
1931	*/
1932	PCCPUMFEATURES pBaseFeat = cpumR3IsHwAssistNstGstExecAllowed(pVM) ? &pVM->cpum.s.HostFeatures : &EmuFeat;
1933	PCPUMFEATURES pGuestFeat = &pVM->cpum.s.GuestFeatures;
1934	Assert(pBaseFeat->fVmx);
1935	pGuestFeat->fVmxInsOutInfo = (pBaseFeat->fVmxInsOutInfo & EmuFeat.fVmxInsOutInfo );
1936	pGuestFeat->fVmxExtIntExit = (pBaseFeat->fVmxExtIntExit & EmuFeat.fVmxExtIntExit );
1937	pGuestFeat->fVmxNmiExit = (pBaseFeat->fVmxNmiExit & EmuFeat.fVmxNmiExit );
1938	pGuestFeat->fVmxVirtNmi = (pBaseFeat->fVmxVirtNmi & EmuFeat.fVmxVirtNmi );
1939	pGuestFeat->fVmxPreemptTimer = (pBaseFeat->fVmxPreemptTimer & EmuFeat.fVmxPreemptTimer );
1940	pGuestFeat->fVmxPostedInt = (pBaseFeat->fVmxPostedInt & EmuFeat.fVmxPostedInt );
1941	pGuestFeat->fVmxIntWindowExit = (pBaseFeat->fVmxIntWindowExit & EmuFeat.fVmxIntWindowExit );
1942	pGuestFeat->fVmxTscOffsetting = (pBaseFeat->fVmxTscOffsetting & EmuFeat.fVmxTscOffsetting );
1943	pGuestFeat->fVmxHltExit = (pBaseFeat->fVmxHltExit & EmuFeat.fVmxHltExit );
1944	pGuestFeat->fVmxInvlpgExit = (pBaseFeat->fVmxInvlpgExit & EmuFeat.fVmxInvlpgExit );
1945	pGuestFeat->fVmxMwaitExit = (pBaseFeat->fVmxMwaitExit & EmuFeat.fVmxMwaitExit );
1946	pGuestFeat->fVmxRdpmcExit = (pBaseFeat->fVmxRdpmcExit & EmuFeat.fVmxRdpmcExit );
1947	pGuestFeat->fVmxRdtscExit = (pBaseFeat->fVmxRdtscExit & EmuFeat.fVmxRdtscExit );
1948	pGuestFeat->fVmxCr3LoadExit = (pBaseFeat->fVmxCr3LoadExit & EmuFeat.fVmxCr3LoadExit );
1949	pGuestFeat->fVmxCr3StoreExit = (pBaseFeat->fVmxCr3StoreExit & EmuFeat.fVmxCr3StoreExit );
1950	pGuestFeat->fVmxCr8LoadExit = (pBaseFeat->fVmxCr8LoadExit & EmuFeat.fVmxCr8LoadExit );
1951	pGuestFeat->fVmxCr8StoreExit = (pBaseFeat->fVmxCr8StoreExit & EmuFeat.fVmxCr8StoreExit );
1952	pGuestFeat->fVmxUseTprShadow = (pBaseFeat->fVmxUseTprShadow & EmuFeat.fVmxUseTprShadow );
1953	pGuestFeat->fVmxNmiWindowExit = (pBaseFeat->fVmxNmiWindowExit & EmuFeat.fVmxNmiWindowExit );
1954	pGuestFeat->fVmxMovDRxExit = (pBaseFeat->fVmxMovDRxExit & EmuFeat.fVmxMovDRxExit );
1955	pGuestFeat->fVmxUncondIoExit = (pBaseFeat->fVmxUncondIoExit & EmuFeat.fVmxUncondIoExit );
1956	pGuestFeat->fVmxUseIoBitmaps = (pBaseFeat->fVmxUseIoBitmaps & EmuFeat.fVmxUseIoBitmaps );
1957	pGuestFeat->fVmxMonitorTrapFlag = (pBaseFeat->fVmxMonitorTrapFlag & EmuFeat.fVmxMonitorTrapFlag );
1958	pGuestFeat->fVmxUseMsrBitmaps = (pBaseFeat->fVmxUseMsrBitmaps & EmuFeat.fVmxUseMsrBitmaps );
1959	pGuestFeat->fVmxMonitorExit = (pBaseFeat->fVmxMonitorExit & EmuFeat.fVmxMonitorExit );
1960	pGuestFeat->fVmxPauseExit = (pBaseFeat->fVmxPauseExit & EmuFeat.fVmxPauseExit );
1961	pGuestFeat->fVmxSecondaryExecCtls = (pBaseFeat->fVmxSecondaryExecCtls & EmuFeat.fVmxSecondaryExecCtls );
1962	pGuestFeat->fVmxVirtApicAccess = (pBaseFeat->fVmxVirtApicAccess & EmuFeat.fVmxVirtApicAccess );
1963	pGuestFeat->fVmxEpt = (pBaseFeat->fVmxEpt & EmuFeat.fVmxEpt );
1964	pGuestFeat->fVmxDescTableExit = (pBaseFeat->fVmxDescTableExit & EmuFeat.fVmxDescTableExit );
1965	pGuestFeat->fVmxRdtscp = (pBaseFeat->fVmxRdtscp & EmuFeat.fVmxRdtscp );
1966	pGuestFeat->fVmxVirtX2ApicMode = (pBaseFeat->fVmxVirtX2ApicMode & EmuFeat.fVmxVirtX2ApicMode );
1967	pGuestFeat->fVmxVpid = (pBaseFeat->fVmxVpid & EmuFeat.fVmxVpid );
1968	pGuestFeat->fVmxWbinvdExit = (pBaseFeat->fVmxWbinvdExit & EmuFeat.fVmxWbinvdExit );
1969	pGuestFeat->fVmxUnrestrictedGuest = (pBaseFeat->fVmxUnrestrictedGuest & EmuFeat.fVmxUnrestrictedGuest );
1970	pGuestFeat->fVmxApicRegVirt = (pBaseFeat->fVmxApicRegVirt & EmuFeat.fVmxApicRegVirt );
1971	pGuestFeat->fVmxVirtIntDelivery = (pBaseFeat->fVmxVirtIntDelivery & EmuFeat.fVmxVirtIntDelivery );
1972	pGuestFeat->fVmxPauseLoopExit = (pBaseFeat->fVmxPauseLoopExit & EmuFeat.fVmxPauseLoopExit );
1973	pGuestFeat->fVmxRdrandExit = (pBaseFeat->fVmxRdrandExit & EmuFeat.fVmxRdrandExit );
1974	pGuestFeat->fVmxInvpcid = (pBaseFeat->fVmxInvpcid & EmuFeat.fVmxInvpcid );
1975	pGuestFeat->fVmxVmFunc = (pBaseFeat->fVmxVmFunc & EmuFeat.fVmxVmFunc );
1976	pGuestFeat->fVmxVmcsShadowing = (pBaseFeat->fVmxVmcsShadowing & EmuFeat.fVmxVmcsShadowing );
1977	pGuestFeat->fVmxRdseedExit = (pBaseFeat->fVmxRdseedExit & EmuFeat.fVmxRdseedExit );
1978	pGuestFeat->fVmxPml = (pBaseFeat->fVmxPml & EmuFeat.fVmxPml );
1979	pGuestFeat->fVmxEptXcptVe = (pBaseFeat->fVmxEptXcptVe & EmuFeat.fVmxEptXcptVe );
1980	pGuestFeat->fVmxXsavesXrstors = (pBaseFeat->fVmxXsavesXrstors & EmuFeat.fVmxXsavesXrstors );
1981	pGuestFeat->fVmxUseTscScaling = (pBaseFeat->fVmxUseTscScaling & EmuFeat.fVmxUseTscScaling );
1982	pGuestFeat->fVmxEntryLoadDebugCtls = (pBaseFeat->fVmxEntryLoadDebugCtls & EmuFeat.fVmxEntryLoadDebugCtls );
1983	pGuestFeat->fVmxIa32eModeGuest = (pBaseFeat->fVmxIa32eModeGuest & EmuFeat.fVmxIa32eModeGuest );
1984	pGuestFeat->fVmxEntryLoadEferMsr = (pBaseFeat->fVmxEntryLoadEferMsr & EmuFeat.fVmxEntryLoadEferMsr );
1985	pGuestFeat->fVmxEntryLoadPatMsr = (pBaseFeat->fVmxEntryLoadPatMsr & EmuFeat.fVmxEntryLoadPatMsr );
1986	pGuestFeat->fVmxExitSaveDebugCtls = (pBaseFeat->fVmxExitSaveDebugCtls & EmuFeat.fVmxExitSaveDebugCtls );
1987	pGuestFeat->fVmxHostAddrSpaceSize = (pBaseFeat->fVmxHostAddrSpaceSize & EmuFeat.fVmxHostAddrSpaceSize );
1988	pGuestFeat->fVmxExitAckExtInt = (pBaseFeat->fVmxExitAckExtInt & EmuFeat.fVmxExitAckExtInt );
1989	pGuestFeat->fVmxExitSavePatMsr = (pBaseFeat->fVmxExitSavePatMsr & EmuFeat.fVmxExitSavePatMsr );
1990	pGuestFeat->fVmxExitLoadPatMsr = (pBaseFeat->fVmxExitLoadPatMsr & EmuFeat.fVmxExitLoadPatMsr );
1991	pGuestFeat->fVmxExitSaveEferMsr = (pBaseFeat->fVmxExitSaveEferMsr & EmuFeat.fVmxExitSaveEferMsr );
1992	pGuestFeat->fVmxExitLoadEferMsr = (pBaseFeat->fVmxExitLoadEferMsr & EmuFeat.fVmxExitLoadEferMsr );
1993	pGuestFeat->fVmxSavePreemptTimer = (pBaseFeat->fVmxSavePreemptTimer & EmuFeat.fVmxSavePreemptTimer );
1994	pGuestFeat->fVmxExitSaveEferLma = (pBaseFeat->fVmxExitSaveEferLma & EmuFeat.fVmxExitSaveEferLma );
1995	pGuestFeat->fVmxIntelPt = (pBaseFeat->fVmxIntelPt & EmuFeat.fVmxIntelPt );
1996	pGuestFeat->fVmxVmwriteAll = (pBaseFeat->fVmxVmwriteAll & EmuFeat.fVmxVmwriteAll );
1997	pGuestFeat->fVmxEntryInjectSoftInt = (pBaseFeat->fVmxEntryInjectSoftInt & EmuFeat.fVmxEntryInjectSoftInt );
1998
1999	if (HMIsSubjectToVmxPreemptTimerErratum())
2000	{
2001	Log(("CPUM: VMX-preemption timer erratum detected. Cannot expose VMX-preemption timer feature to guests."));
2002	pGuestFeat->fVmxPreemptTimer = 0;
2003	}
2004
2005	/* Paranoia. */
2006	if (!pGuestFeat->fVmxSecondaryExecCtls)
2007	{
2008	Assert(!pGuestFeat->fVmxVirtApicAccess);
2009	Assert(!pGuestFeat->fVmxEpt);
2010	Assert(!pGuestFeat->fVmxDescTableExit);
2011	Assert(!pGuestFeat->fVmxRdtscp);
2012	Assert(!pGuestFeat->fVmxVirtX2ApicMode);
2013	Assert(!pGuestFeat->fVmxVpid);
2014	Assert(!pGuestFeat->fVmxWbinvdExit);
2015	Assert(!pGuestFeat->fVmxUnrestrictedGuest);
2016	Assert(!pGuestFeat->fVmxApicRegVirt);
2017	Assert(!pGuestFeat->fVmxVirtIntDelivery);
2018	Assert(!pGuestFeat->fVmxPauseLoopExit);
2019	Assert(!pGuestFeat->fVmxRdrandExit);
2020	Assert(!pGuestFeat->fVmxInvpcid);
2021	Assert(!pGuestFeat->fVmxVmFunc);
2022	Assert(!pGuestFeat->fVmxVmcsShadowing);
2023	Assert(!pGuestFeat->fVmxRdseedExit);
2024	Assert(!pGuestFeat->fVmxPml);
2025	Assert(!pGuestFeat->fVmxEptXcptVe);
2026	Assert(!pGuestFeat->fVmxXsavesXrstors);
2027	Assert(!pGuestFeat->fVmxUseTscScaling);
2028	}
2029	if (pGuestFeat->fVmxUnrestrictedGuest)
2030	{
2031	/* See footnote in Intel spec. 27.2 "Recording VM-Exit Information And Updating VM-entry Control Fields". */
2032	Assert(pGuestFeat->fVmxExitSaveEferLma);
2033	}
2034
2035	/*
2036	* Finally initialize the VMX guest MSRs.
2037	*/
2038	cpumR3InitVmxGuestMsrs(pVM, pHostVmxMsrs, pGuestFeat, pGuestVmxMsrs);
2039	}
2040
2041
2042	/**
2043	* Gets the host hardware-virtualization MSRs.
2044	*
2045	* @returns VBox status code.
2046	* @param pMsrs Where to store the MSRs.
2047	*/
2048	static int cpumR3GetHostHwvirtMsrs(PCPUMMSRS pMsrs)
2049	{
2050	Assert(pMsrs);
2051
2052	uint32_t fCaps = 0;
2053	int rc = SUPR3QueryVTCaps(&fCaps);
2054	if (RT_SUCCESS(rc))
2055	{
2056	if (fCaps & (SUPVTCAPS_VT_X \| SUPVTCAPS_AMD_V))
2057	{
2058	SUPHWVIRTMSRS HwvirtMsrs;
2059	rc = SUPR3GetHwvirtMsrs(&HwvirtMsrs, false /* fForceRequery */);
2060	if (RT_SUCCESS(rc))
2061	{
2062	if (fCaps & SUPVTCAPS_VT_X)
2063	HMGetVmxMsrsFromHwvirtMsrs(&HwvirtMsrs, &pMsrs->hwvirt.vmx);
2064	else
2065	HMGetSvmMsrsFromHwvirtMsrs(&HwvirtMsrs, &pMsrs->hwvirt.svm);
2066	return VINF_SUCCESS;
2067	}
2068
2069	LogRel(("CPUM: Querying hardware-virtualization MSRs failed. rc=%Rrc\n", rc));
2070	return rc;
2071	}
2072	else
2073	{
2074	LogRel(("CPUM: Querying hardware-virtualization capability succeeded but did not find VT-x or AMD-V\n"));
2075	return VERR_INTERNAL_ERROR_5;
2076	}
2077	}
2078	else
2079	LogRel(("CPUM: No hardware-virtualization capability detected\n"));
2080
2081	return VINF_SUCCESS;
2082	}
2083
2084
2085	/**
2086	* Initializes the CPUM.
2087	*
2088	* @returns VBox status code.
2089	* @param pVM The cross context VM structure.
2090	*/
2091	VMMR3DECL(int) CPUMR3Init(PVM pVM)
2092	{
2093	LogFlow(("CPUMR3Init\n"));
2094
2095	/*
2096	* Assert alignment, sizes and tables.
2097	*/
2098	AssertCompileMemberAlignment(VM, cpum.s, 32);
2099	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
2100	AssertCompileSizeAlignment(CPUMCTX, 64);
2101	AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
2102	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
2103	AssertCompileMemberAlignment(VM, cpum, 64);
2104	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
2105	#ifdef VBOX_STRICT
2106	int rc2 = cpumR3MsrStrictInitChecks();
2107	AssertRCReturn(rc2, rc2);
2108	#endif
2109
2110	/*
2111	* Gather info about the host CPU.
2112	*/
2113	if (!ASMHasCpuId())
2114	{
2115	LogRel(("The CPU doesn't support CPUID!\n"));
2116	return VERR_UNSUPPORTED_CPU;
2117	}
2118
2119	pVM->cpum.s.fHostMxCsrMask = CPUMR3DeterminHostMxCsrMask();
2120
2121	CPUMMSRS HostMsrs;
2122	RT_ZERO(HostMsrs);
2123	int rc = cpumR3GetHostHwvirtMsrs(&HostMsrs);
2124	AssertLogRelRCReturn(rc, rc);
2125
2126	PCPUMCPUIDLEAF paLeaves;
2127	uint32_t cLeaves;
2128	rc = CPUMR3CpuIdCollectLeaves(&paLeaves, &cLeaves);
2129	AssertLogRelRCReturn(rc, rc);
2130
2131	rc = cpumR3CpuIdExplodeFeatures(paLeaves, cLeaves, &HostMsrs, &pVM->cpum.s.HostFeatures);
2132	RTMemFree(paLeaves);
2133	AssertLogRelRCReturn(rc, rc);
2134	pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.enmCpuVendor;
2135
2136	/*
2137	* Check that the CPU supports the minimum features we require.
2138	*/
2139	if (!pVM->cpum.s.HostFeatures.fFxSaveRstor)
2140	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support the FXSAVE/FXRSTOR instruction.");
2141	if (!pVM->cpum.s.HostFeatures.fMmx)
2142	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support MMX.");
2143	if (!pVM->cpum.s.HostFeatures.fTsc)
2144	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support RDTSC.");
2145
2146	/*
2147	* Setup the CR4 AND and OR masks used in the raw-mode switcher.
2148	*/
2149	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
2150	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFXSR;
2151
2152	/*
2153	* Figure out which XSAVE/XRSTOR features are available on the host.
2154	*/
2155	uint64_t fXcr0Host = 0;
2156	uint64_t fXStateHostMask = 0;
2157	if ( pVM->cpum.s.HostFeatures.fXSaveRstor
2158	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor)
2159	{
2160	fXStateHostMask = fXcr0Host = ASMGetXcr0();
2161	fXStateHostMask &= XSAVE_C_X87 \| XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI;
2162	AssertLogRelMsgStmt((fXStateHostMask & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
2163	("%#llx\n", fXStateHostMask), fXStateHostMask = 0);
2164	}
2165	pVM->cpum.s.fXStateHostMask = fXStateHostMask;
2166	LogRel(("CPUM: fXStateHostMask=%#llx; initial: %#llx; host XCR0=%#llx\n",
2167	pVM->cpum.s.fXStateHostMask, fXStateHostMask, fXcr0Host));
2168
2169	/*
2170	* Allocate memory for the extended CPU state and initialize the host XSAVE/XRSTOR mask.
2171	*/
2172	uint32_t cbMaxXState = pVM->cpum.s.HostFeatures.cbMaxExtendedState;
2173	cbMaxXState = RT_ALIGN(cbMaxXState, 128);
2174	AssertLogRelReturn(cbMaxXState >= sizeof(X86FXSTATE) && cbMaxXState <= _8K, VERR_CPUM_IPE_2);
2175
2176	uint8_t *pbXStates;
2177	rc = MMR3HyperAllocOnceNoRelEx(pVM, cbMaxXState * 2 * pVM->cCpus, PAGE_SIZE, MM_TAG_CPUM_CTX,
2178	MMHYPER_AONR_FLAGS_KERNEL_MAPPING, (void **)&pbXStates);
2179	AssertLogRelRCReturn(rc, rc);
2180
2181	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2182	{
2183	PVMCPU pVCpu = pVM->apCpusR3[i];
2184
2185	pVCpu->cpum.s.Guest.pXStateR3 = (PX86XSAVEAREA)pbXStates;
2186	pVCpu->cpum.s.Guest.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
2187	pbXStates += cbMaxXState;
2188
2189	pVCpu->cpum.s.Host.pXStateR3 = (PX86XSAVEAREA)pbXStates;
2190	pVCpu->cpum.s.Host.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
2191	pbXStates += cbMaxXState;
2192
2193	pVCpu->cpum.s.Host.fXStateMask = fXStateHostMask;
2194	}
2195
2196	/*
2197	* Register saved state data item.
2198	*/
2199	rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
2200	NULL, cpumR3LiveExec, NULL,
2201	NULL, cpumR3SaveExec, NULL,
2202	cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
2203	if (RT_FAILURE(rc))
2204	return rc;
2205
2206	/*
2207	* Register info handlers and registers with the debugger facility.
2208	*/
2209	DBGFR3InfoRegisterInternalEx(pVM, "cpum", "Displays the all the cpu states.",
2210	&cpumR3InfoAll, DBGFINFO_FLAGS_ALL_EMTS);
2211	DBGFR3InfoRegisterInternalEx(pVM, "cpumguest", "Displays the guest cpu state.",
2212	&cpumR3InfoGuest, DBGFINFO_FLAGS_ALL_EMTS);
2213	DBGFR3InfoRegisterInternalEx(pVM, "cpumguesthwvirt", "Displays the guest hwvirt. cpu state.",
2214	&cpumR3InfoGuestHwvirt, DBGFINFO_FLAGS_ALL_EMTS);
2215	DBGFR3InfoRegisterInternalEx(pVM, "cpumhyper", "Displays the hypervisor cpu state.",
2216	&cpumR3InfoHyper, DBGFINFO_FLAGS_ALL_EMTS);
2217	DBGFR3InfoRegisterInternalEx(pVM, "cpumhost", "Displays the host cpu state.",
2218	&cpumR3InfoHost, DBGFINFO_FLAGS_ALL_EMTS);
2219	DBGFR3InfoRegisterInternalEx(pVM, "cpumguestinstr", "Displays the current guest instruction.",
2220	&cpumR3InfoGuestInstr, DBGFINFO_FLAGS_ALL_EMTS);
2221	DBGFR3InfoRegisterInternal( pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
2222	DBGFR3InfoRegisterInternal( pVM, "cpumvmxfeat", "Displays the host and guest VMX hwvirt. features.",
2223	&cpumR3InfoVmxFeatures);
2224
2225	rc = cpumR3DbgInit(pVM);
2226	if (RT_FAILURE(rc))
2227	return rc;
2228
2229	/*
2230	* Check if we need to workaround partial/leaky FPU handling.
2231	*/
2232	cpumR3CheckLeakyFpu(pVM);
2233
2234	/*
2235	* Initialize the Guest CPUID and MSR states.
2236	*/
2237	rc = cpumR3InitCpuIdAndMsrs(pVM, &HostMsrs);
2238	if (RT_FAILURE(rc))
2239	return rc;
2240
2241	/*
2242	* Allocate memory required by the guest hardware-virtualization structures.
2243	* This must be done after initializing CPUID/MSR features as we access the
2244	* the VMX/SVM guest features below.
2245	*/
2246	if (pVM->cpum.s.GuestFeatures.fVmx)
2247	rc = cpumR3AllocVmxHwVirtState(pVM);
2248	else if (pVM->cpum.s.GuestFeatures.fSvm)
2249	rc = cpumR3AllocSvmHwVirtState(pVM);
2250	else
2251	Assert(pVM->apCpusR3[0]->cpum.s.Guest.hwvirt.enmHwvirt == CPUMHWVIRT_NONE);
2252	if (RT_FAILURE(rc))
2253	return rc;
2254
2255	CPUMR3Reset(pVM);
2256	return VINF_SUCCESS;
2257	}
2258
2259
2260	/**
2261	* Applies relocations to data and code managed by this
2262	* component. This function will be called at init and
2263	* whenever the VMM need to relocate it self inside the GC.
2264	*
2265	* The CPUM will update the addresses used by the switcher.
2266	*
2267	* @param pVM The cross context VM structure.
2268	*/
2269	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
2270	{
2271	RT_NOREF(pVM);
2272	}
2273
2274
2275	/**
2276	* Terminates the CPUM.
2277	*
2278	* Termination means cleaning up and freeing all resources,
2279	* the VM it self is at this point powered off or suspended.
2280	*
2281	* @returns VBox status code.
2282	* @param pVM The cross context VM structure.
2283	*/
2284	VMMR3DECL(int) CPUMR3Term(PVM pVM)
2285	{
2286	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2287	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2288	{
2289	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2290	memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
2291	pVCpu->cpum.s.uMagic = 0;
2292	pvCpu->cpum.s.Guest.dr[5] = 0;
2293	}
2294	#endif
2295
2296	if (pVM->cpum.s.GuestFeatures.fVmx)
2297	cpumR3FreeVmxHwVirtState(pVM);
2298	else if (pVM->cpum.s.GuestFeatures.fSvm)
2299	cpumR3FreeSvmHwVirtState(pVM);
2300	return VINF_SUCCESS;
2301	}
2302
2303
2304	/**
2305	* Resets a virtual CPU.
2306	*
2307	* Used by CPUMR3Reset and CPU hot plugging.
2308	*
2309	* @param pVM The cross context VM structure.
2310	* @param pVCpu The cross context virtual CPU structure of the CPU that is
2311	* being reset. This may differ from the current EMT.
2312	*/
2313	VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
2314	{
2315	/** @todo anything different for VCPU > 0? */
2316	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2317
2318	/*
2319	* Initialize everything to ZERO first.
2320	*/
2321	uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
2322
2323	AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateR3));
2324	memset(pCtx, 0, RT_UOFFSETOF(CPUMCTX, pXStateR0));
2325
2326	pVCpu->cpum.s.fUseFlags = fUseFlags;
2327
2328	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
2329	pCtx->eip = 0x0000fff0;
2330	pCtx->edx = 0x00000600; /* P6 processor */
2331	pCtx->eflags.Bits.u1Reserved0 = 1;
2332
2333	pCtx->cs.Sel = 0xf000;
2334	pCtx->cs.ValidSel = 0xf000;
2335	pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
2336	pCtx->cs.u64Base = UINT64_C(0xffff0000);
2337	pCtx->cs.u32Limit = 0x0000ffff;
2338	pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
2339	pCtx->cs.Attr.n.u1Present = 1;
2340	pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
2341
2342	pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
2343	pCtx->ds.u32Limit = 0x0000ffff;
2344	pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
2345	pCtx->ds.Attr.n.u1Present = 1;
2346	pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2347
2348	pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
2349	pCtx->es.u32Limit = 0x0000ffff;
2350	pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
2351	pCtx->es.Attr.n.u1Present = 1;
2352	pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2353
2354	pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
2355	pCtx->fs.u32Limit = 0x0000ffff;
2356	pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
2357	pCtx->fs.Attr.n.u1Present = 1;
2358	pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2359
2360	pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
2361	pCtx->gs.u32Limit = 0x0000ffff;
2362	pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
2363	pCtx->gs.Attr.n.u1Present = 1;
2364	pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2365
2366	pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
2367	pCtx->ss.u32Limit = 0x0000ffff;
2368	pCtx->ss.Attr.n.u1Present = 1;
2369	pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
2370	pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2371
2372	pCtx->idtr.cbIdt = 0xffff;
2373	pCtx->gdtr.cbGdt = 0xffff;
2374
2375	pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2376	pCtx->ldtr.u32Limit = 0xffff;
2377	pCtx->ldtr.Attr.n.u1Present = 1;
2378	pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
2379
2380	pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
2381	pCtx->tr.u32Limit = 0xffff;
2382	pCtx->tr.Attr.n.u1Present = 1;
2383	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
2384
2385	pCtx->dr[6] = X86_DR6_INIT_VAL;
2386	pCtx->dr[7] = X86_DR7_INIT_VAL;
2387
2388	PX86FXSTATE pFpuCtx = &pCtx->pXStateR3->x87; AssertReleaseMsg(RT_VALID_PTR(pFpuCtx), ("%p\n", pFpuCtx));
2389	pFpuCtx->FTW = 0x00; /* All empty (abbridged tag reg edition). */
2390	pFpuCtx->FCW = 0x37f;
2391
2392	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
2393	IA-32 Processor States Following Power-up, Reset, or INIT */
2394	pFpuCtx->MXCSR = 0x1F80;
2395	pFpuCtx->MXCSR_MASK = pVM->cpum.s.GuestInfo.fMxCsrMask; /** @todo check if REM messes this up... */
2396
2397	pCtx->aXcr[0] = XSAVE_C_X87;
2398	if (pVM->cpum.s.HostFeatures.cbMaxExtendedState >= RT_UOFFSETOF(X86XSAVEAREA, Hdr))
2399	{
2400	/* The entire FXSAVE state needs loading when we switch to XSAVE/XRSTOR
2401	as we don't know what happened before. (Bother optimize later?) */
2402	pCtx->pXStateR3->Hdr.bmXState = XSAVE_C_X87 \| XSAVE_C_SSE;
2403	}
2404
2405	/*
2406	* MSRs.
2407	*/
2408	/* Init PAT MSR */
2409	pCtx->msrPAT = MSR_IA32_CR_PAT_INIT_VAL;
2410
2411	/* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
2412	* The Intel docs don't mention it. */
2413	Assert(!pCtx->msrEFER);
2414
2415	/* IA32_MISC_ENABLE - not entirely sure what the init/reset state really
2416	is supposed to be here, just trying provide useful/sensible values. */
2417	PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
2418	if (pRange)
2419	{
2420	pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
2421	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
2422	\| (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
2423	\| MSR_IA32_MISC_ENABLE_FAST_STRINGS;
2424	pRange->fWrIgnMask \|= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
2425	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
2426	pRange->fWrGpMask &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
2427	}
2428
2429	/** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
2430
2431	/** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
2432	* called from each EMT while we're getting called by CPUMR3Reset()
2433	* iteratively on the same thread. Fix later. */
2434	#if 0 /** @todo r=bird: This we will do in TM, not here. */
2435	/* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
2436	CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
2437	#endif
2438
2439
2440	/* C-state control. Guesses. */
2441	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /C1/ \| RT_BIT_32(25) \| RT_BIT_32(26) \| RT_BIT_32(27) \| RT_BIT_32(28);
2442	/* For Nehalem+ and Atoms, the 0xE2 MSR (MSR_PKG_CST_CONFIG_CONTROL) is documented. For Core 2,
2443	* it's undocumented but exists as MSR_PMG_CST_CONFIG_CONTROL and has similar but not identical
2444	* functionality. The default value must be different due to incompatible write mask.
2445	*/
2446	if (CPUMMICROARCH_IS_INTEL_CORE2(pVM->cpum.s.GuestFeatures.enmMicroarch))
2447	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x202a01; /* From Mac Pro Harpertown, unlocked. */
2448	else if (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Intel_Core_Yonah)
2449	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x26740c; /* From MacBookPro1,1. */
2450
2451	/*
2452	* Hardware virtualization state.
2453	*/
2454	CPUMSetGuestGif(pCtx, true);
2455	Assert(!pVM->cpum.s.GuestFeatures.fVmx \|\| !pVM->cpum.s.GuestFeatures.fSvm); /* Paranoia. */
2456	if (pVM->cpum.s.GuestFeatures.fVmx)
2457	cpumR3ResetVmxHwVirtState(pVCpu);
2458	else if (pVM->cpum.s.GuestFeatures.fSvm)
2459	cpumR3ResetSvmHwVirtState(pVCpu);
2460	}
2461
2462
2463	/**
2464	* Resets the CPU.
2465	*
2466	* @returns VINF_SUCCESS.
2467	* @param pVM The cross context VM structure.
2468	*/
2469	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
2470	{
2471	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2472	{
2473	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2474	CPUMR3ResetCpu(pVM, pVCpu);
2475
2476	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2477
2478	/* Magic marker for searching in crash dumps. */
2479	strcpy((char *)pVCpu->.cpum.s.aMagic, "CPUMCPU Magic");
2480	pVCpu->cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
2481	pVCpu->cpum.s.Guest->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
2482	#endif
2483	}
2484	}
2485
2486
2487
2488
2489	/**
2490	* Pass 0 live exec callback.
2491	*
2492	* @returns VINF_SSM_DONT_CALL_AGAIN.
2493	* @param pVM The cross context VM structure.
2494	* @param pSSM The saved state handle.
2495	* @param uPass The pass (0).
2496	*/
2497	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2498	{
2499	AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
2500	cpumR3SaveCpuId(pVM, pSSM);
2501	return VINF_SSM_DONT_CALL_AGAIN;
2502	}
2503
2504
2505	/**
2506	* Execute state save operation.
2507	*
2508	* @returns VBox status code.
2509	* @param pVM The cross context VM structure.
2510	* @param pSSM SSM operation handle.
2511	*/
2512	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
2513	{
2514	/*
2515	* Save.
2516	*/
2517	SSMR3PutU32(pSSM, pVM->cCpus);
2518	SSMR3PutU32(pSSM, sizeof(pVM->apCpusR3[0]->cpum.s.GuestMsrs.msr));
2519	CPUMCTX DummyHyperCtx;
2520	RT_ZERO(DummyHyperCtx);
2521	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2522	{
2523	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2524
2525	SSMR3PutStructEx(pSSM, &DummyHyperCtx, sizeof(DummyHyperCtx), 0, g_aCpumCtxFields, NULL);
2526
2527	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
2528	SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2529	SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
2530	if (pGstCtx->fXStateMask != 0)
2531	SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr), 0, g_aCpumXSaveHdrFields, NULL);
2532	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
2533	{
2534	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
2535	SSMR3PutStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2536	}
2537	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2538	{
2539	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
2540	SSMR3PutStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2541	}
2542	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2543	{
2544	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
2545	SSMR3PutStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2546	}
2547	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2548	{
2549	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
2550	SSMR3PutStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2551	}
2552	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2553	{
2554	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
2555	SSMR3PutStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2556	}
2557	if (pVM->cpum.s.GuestFeatures.fSvm)
2558	{
2559	Assert(pGstCtx->hwvirt.svm.CTX_SUFF(pVmcb));
2560	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uMsrHSavePa);
2561	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.svm.GCPhysVmcb);
2562	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uPrevPauseTick);
2563	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilter);
2564	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2565	SSMR3PutBool(pSSM, pGstCtx->hwvirt.svm.fInterceptEvents);
2566	SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState), 0 /* fFlags */,
2567	g_aSvmHwvirtHostState, NULL /* pvUser */);
2568	SSMR3PutMem(pSSM, pGstCtx->hwvirt.svm.pVmcbR3, SVM_VMCB_PAGES << X86_PAGE_4K_SHIFT);
2569	SSMR3PutMem(pSSM, pGstCtx->hwvirt.svm.pvMsrBitmapR3, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
2570	SSMR3PutMem(pSSM, pGstCtx->hwvirt.svm.pvIoBitmapR3, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT);
2571	SSMR3PutU32(pSSM, pGstCtx->hwvirt.fLocalForcedActions);
2572	SSMR3PutBool(pSSM, pGstCtx->hwvirt.fGif);
2573	}
2574	if (pVM->cpum.s.GuestFeatures.fVmx)
2575	{
2576	Assert(pGstCtx->hwvirt.vmx.CTX_SUFF(pVmcs));
2577	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysVmxon);
2578	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysVmcs);
2579	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysShadowVmcs);
2580	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInVmxRootMode);
2581	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInVmxNonRootMode);
2582	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInterceptEvents);
2583	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fNmiUnblockingIret);
2584	SSMR3PutStructEx(pSSM, pGstCtx->hwvirt.vmx.pVmcsR3, sizeof(VMXVVMCS), 0, g_aVmxHwvirtVmcs, NULL);
2585	SSMR3PutStructEx(pSSM, pGstCtx->hwvirt.vmx.pShadowVmcsR3, sizeof(VMXVVMCS), 0, g_aVmxHwvirtVmcs, NULL);
2586	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pvVmreadBitmapR3, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
2587	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pvVmwriteBitmapR3, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
2588	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pEntryMsrLoadAreaR3, VMX_V_AUTOMSR_AREA_SIZE);
2589	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pExitMsrStoreAreaR3, VMX_V_AUTOMSR_AREA_SIZE);
2590	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pExitMsrLoadAreaR3, VMX_V_AUTOMSR_AREA_SIZE);
2591	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pvMsrBitmapR3, VMX_V_MSR_BITMAP_SIZE);
2592	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pvIoBitmapR3, VMX_V_IO_BITMAP_A_SIZE + VMX_V_IO_BITMAP_B_SIZE);
2593	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uFirstPauseLoopTick);
2594	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uPrevPauseTick);
2595	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uEntryTick);
2596	SSMR3PutU16(pSSM, pGstCtx->hwvirt.vmx.offVirtApicWrite);
2597	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fVirtNmiBlocking);
2598	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64FeatCtrl);
2599	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Basic);
2600	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.PinCtls.u);
2601	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ProcCtls.u);
2602	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ProcCtls2.u);
2603	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ExitCtls.u);
2604	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.EntryCtls.u);
2605	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TruePinCtls.u);
2606	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueProcCtls.u);
2607	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueEntryCtls.u);
2608	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueExitCtls.u);
2609	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Misc);
2610	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed0);
2611	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed1);
2612	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed0);
2613	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed1);
2614	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64VmcsEnum);
2615	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64VmFunc);
2616	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64EptVpidCaps);
2617	}
2618	SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
2619	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
2620	AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
2621	SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
2622	}
2623
2624	cpumR3SaveCpuId(pVM, pSSM);
2625	return VINF_SUCCESS;
2626	}
2627
2628
2629	/**
2630	* @callback_method_impl{FNSSMINTLOADPREP}
2631	*/
2632	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2633	{
2634	NOREF(pSSM);
2635	pVM->cpum.s.fPendingRestore = true;
2636	return VINF_SUCCESS;
2637	}
2638
2639
2640	/**
2641	* @callback_method_impl{FNSSMINTLOADEXEC}
2642	*/
2643	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2644	{
2645	int rc; /* Only for AssertRCReturn use. */
2646
2647	/*
2648	* Validate version.
2649	*/
2650	if ( uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_IEM
2651	&& uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_SVM
2652	&& uVersion != CPUM_SAVED_STATE_VERSION_XSAVE
2653	&& uVersion != CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT
2654	&& uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
2655	&& uVersion != CPUM_SAVED_STATE_VERSION_PUT_STRUCT
2656	&& uVersion != CPUM_SAVED_STATE_VERSION_MEM
2657	&& uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
2658	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
2659	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
2660	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
2661	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2662	&& uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
2663	{
2664	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
2665	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2666	}
2667
2668	if (uPass == SSM_PASS_FINAL)
2669	{
2670	/*
2671	* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
2672	* really old SSM file versions.)
2673	*/
2674	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2675	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
2676	else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
2677	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR));
2678
2679	/*
2680	* Figure x86 and ctx field definitions to use for older states.
2681	*/
2682	uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
2683	PCSSMFIELD paCpumCtx1Fields = g_aCpumX87Fields;
2684	PCSSMFIELD paCpumCtx2Fields = g_aCpumCtxFields;
2685	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2686	{
2687	paCpumCtx1Fields = g_aCpumX87FieldsV16;
2688	paCpumCtx2Fields = g_aCpumCtxFieldsV16;
2689	}
2690	else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2691	{
2692	paCpumCtx1Fields = g_aCpumX87FieldsMem;
2693	paCpumCtx2Fields = g_aCpumCtxFieldsMem;
2694	}
2695
2696	/*
2697	* The hyper state used to preceed the CPU count. Starting with
2698	* XSAVE it was moved down till after we've got the count.
2699	*/
2700	CPUMCTX HyperCtxIgnored;
2701	if (uVersion < CPUM_SAVED_STATE_VERSION_XSAVE)
2702	{
2703	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2704	{
2705	X86FXSTATE Ign;
2706	SSMR3GetStructEx(pSSM, &Ign, sizeof(Ign), fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
2707	SSMR3GetStructEx(pSSM, &HyperCtxIgnored, sizeof(HyperCtxIgnored),
2708	fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
2709	}
2710	}
2711
2712	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
2713	{
2714	uint32_t cCpus;
2715	rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2716	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
2717	VERR_SSM_UNEXPECTED_DATA);
2718	}
2719	AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
2720	\|\| pVM->cCpus == 1,
2721	("cCpus=%u\n", pVM->cCpus),
2722	VERR_SSM_UNEXPECTED_DATA);
2723
2724	uint32_t cbMsrs = 0;
2725	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2726	{
2727	rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
2728	AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
2729	VERR_SSM_UNEXPECTED_DATA);
2730	AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
2731	VERR_SSM_UNEXPECTED_DATA);
2732	}
2733
2734	/*
2735	* Do the per-CPU restoring.
2736	*/
2737	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2738	{
2739	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2740	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
2741
2742	if (uVersion >= CPUM_SAVED_STATE_VERSION_XSAVE)
2743	{
2744	/*
2745	* The XSAVE saved state layout moved the hyper state down here.
2746	*/
2747	rc = SSMR3GetStructEx(pSSM, &HyperCtxIgnored, sizeof(HyperCtxIgnored), 0, g_aCpumCtxFields, NULL);
2748	AssertRCReturn(rc, rc);
2749
2750	/*
2751	* Start by restoring the CPUMCTX structure and the X86FXSAVE bits of the extended state.
2752	*/
2753	rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2754	rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
2755	AssertRCReturn(rc, rc);
2756
2757	/* Check that the xsave/xrstor mask is valid (invalid results in #GP). */
2758	if (pGstCtx->fXStateMask != 0)
2759	{
2760	AssertLogRelMsgReturn(!(pGstCtx->fXStateMask & ~pVM->cpum.s.fXStateGuestMask),
2761	("fXStateMask=%#RX64 fXStateGuestMask=%#RX64\n",
2762	pGstCtx->fXStateMask, pVM->cpum.s.fXStateGuestMask),
2763	VERR_CPUM_INCOMPATIBLE_XSAVE_COMP_MASK);
2764	AssertLogRelMsgReturn(pGstCtx->fXStateMask & XSAVE_C_X87,
2765	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2766	AssertLogRelMsgReturn((pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
2767	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2768	AssertLogRelMsgReturn( (pGstCtx->fXStateMask & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
2769	\|\| (pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
2770	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
2771	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2772	}
2773
2774	/* Check that the XCR0 mask is valid (invalid results in #GP). */
2775	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87, ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XCR0);
2776	if (pGstCtx->aXcr[0] != XSAVE_C_X87)
2777	{
2778	AssertLogRelMsgReturn(!(pGstCtx->aXcr[0] & ~(pGstCtx->fXStateMask \| XSAVE_C_X87)),
2779	("xcr0=%#RX64 fXStateMask=%#RX64\n", pGstCtx->aXcr[0], pGstCtx->fXStateMask),
2780	VERR_CPUM_INVALID_XCR0);
2781	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87,
2782	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2783	AssertLogRelMsgReturn((pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
2784	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2785	AssertLogRelMsgReturn( (pGstCtx->aXcr[0] & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
2786	\|\| (pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
2787	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
2788	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2789	}
2790
2791	/* Check that the XCR1 is zero, as we don't implement it yet. */
2792	AssertLogRelMsgReturn(!pGstCtx->aXcr[1], ("xcr1=%#RX64\n", pGstCtx->aXcr[1]), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2793
2794	/*
2795	* Restore the individual extended state components we support.
2796	*/
2797	if (pGstCtx->fXStateMask != 0)
2798	{
2799	rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr),
2800	0, g_aCpumXSaveHdrFields, NULL);
2801	AssertRCReturn(rc, rc);
2802	AssertLogRelMsgReturn(!(pGstCtx->pXStateR3->Hdr.bmXState & ~pGstCtx->fXStateMask),
2803	("bmXState=%#RX64 fXStateMask=%#RX64\n",
2804	pGstCtx->pXStateR3->Hdr.bmXState, pGstCtx->fXStateMask),
2805	VERR_CPUM_INVALID_XSAVE_HDR);
2806	}
2807	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
2808	{
2809	PX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PX86XSAVEYMMHI);
2810	SSMR3GetStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2811	}
2812	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2813	{
2814	PX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PX86XSAVEBNDREGS);
2815	SSMR3GetStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2816	}
2817	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2818	{
2819	PX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PX86XSAVEBNDCFG);
2820	SSMR3GetStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2821	}
2822	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2823	{
2824	PX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PX86XSAVEZMMHI256);
2825	SSMR3GetStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2826	}
2827	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2828	{
2829	PX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PX86XSAVEZMM16HI);
2830	SSMR3GetStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2831	}
2832	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_SVM)
2833	{
2834	if (pVM->cpum.s.GuestFeatures.fSvm)
2835	{
2836	Assert(pGstCtx->hwvirt.svm.CTX_SUFF(pVmcb));
2837	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uMsrHSavePa);
2838	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.svm.GCPhysVmcb);
2839	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uPrevPauseTick);
2840	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilter);
2841	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2842	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.svm.fInterceptEvents);
2843	SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState),
2844	0 /* fFlags /, g_aSvmHwvirtHostState, NULL / pvUser */);
2845	SSMR3GetMem(pSSM, pGstCtx->hwvirt.svm.pVmcbR3, SVM_VMCB_PAGES << X86_PAGE_4K_SHIFT);
2846	SSMR3GetMem(pSSM, pGstCtx->hwvirt.svm.pvMsrBitmapR3, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
2847	SSMR3GetMem(pSSM, pGstCtx->hwvirt.svm.pvIoBitmapR3, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT);
2848	SSMR3GetU32(pSSM, &pGstCtx->hwvirt.fLocalForcedActions);
2849	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.fGif);
2850	}
2851	}
2852	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_IEM)
2853	{
2854	if (pVM->cpum.s.GuestFeatures.fVmx)
2855	{
2856	Assert(pGstCtx->hwvirt.vmx.CTX_SUFF(pVmcs));
2857	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysVmxon);
2858	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysVmcs);
2859	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysShadowVmcs);
2860	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInVmxRootMode);
2861	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInVmxNonRootMode);
2862	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInterceptEvents);
2863	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fNmiUnblockingIret);
2864	SSMR3GetStructEx(pSSM, pGstCtx->hwvirt.vmx.pVmcsR3, sizeof(VMXVVMCS), 0, g_aVmxHwvirtVmcs, NULL);
2865	SSMR3GetStructEx(pSSM, pGstCtx->hwvirt.vmx.pShadowVmcsR3, sizeof(VMXVVMCS), 0, g_aVmxHwvirtVmcs, NULL);
2866	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pvVmreadBitmapR3, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
2867	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pvVmwriteBitmapR3, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
2868	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pEntryMsrLoadAreaR3, VMX_V_AUTOMSR_AREA_SIZE);
2869	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pExitMsrStoreAreaR3, VMX_V_AUTOMSR_AREA_SIZE);
2870	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pExitMsrLoadAreaR3, VMX_V_AUTOMSR_AREA_SIZE);
2871	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pvMsrBitmapR3, VMX_V_MSR_BITMAP_SIZE);
2872	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pvIoBitmapR3, VMX_V_IO_BITMAP_A_SIZE + VMX_V_IO_BITMAP_B_SIZE);
2873	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uFirstPauseLoopTick);
2874	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uPrevPauseTick);
2875	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uEntryTick);
2876	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.vmx.offVirtApicWrite);
2877	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fVirtNmiBlocking);
2878	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64FeatCtrl);
2879	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Basic);
2880	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.PinCtls.u);
2881	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ProcCtls.u);
2882	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ProcCtls2.u);
2883	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ExitCtls.u);
2884	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.EntryCtls.u);
2885	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TruePinCtls.u);
2886	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueProcCtls.u);
2887	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueEntryCtls.u);
2888	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueExitCtls.u);
2889	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Misc);
2890	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed0);
2891	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed1);
2892	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed0);
2893	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed1);
2894	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64VmcsEnum);
2895	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64VmFunc);
2896	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64EptVpidCaps);
2897	}
2898	}
2899	}
2900	else
2901	{
2902	/*
2903	* Pre XSAVE saved state.
2904	*/
2905	SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87),
2906	fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
2907	SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
2908	}
2909
2910	/*
2911	* Restore a couple of flags and the MSRs.
2912	*/
2913	SSMR3GetU32(pSSM, &pVCpu->cpum.s.fUseFlags);
2914	SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
2915
2916	rc = VINF_SUCCESS;
2917	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2918	rc = SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
2919	else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
2920	{
2921	SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
2922	rc = SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
2923	}
2924	AssertRCReturn(rc, rc);
2925
2926	/* REM and other may have cleared must-be-one fields in DR6 and
2927	DR7, fix these. */
2928	pGstCtx->dr[6] &= ~(X86_DR6_RAZ_MASK \| X86_DR6_MBZ_MASK);
2929	pGstCtx->dr[6] \|= X86_DR6_RA1_MASK;
2930	pGstCtx->dr[7] &= ~(X86_DR7_RAZ_MASK \| X86_DR7_MBZ_MASK);
2931	pGstCtx->dr[7] \|= X86_DR7_RA1_MASK;
2932	}
2933
2934	/* Older states does not have the internal selector register flags
2935	and valid selector value. Supply those. */
2936	if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2937	{
2938	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2939	{
2940	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2941	bool const fValid = true /!VM_IS_RAW_MODE_ENABLED(pVM)/
2942	\|\| ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2943	&& !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
2944	PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
2945	if (fValid)
2946	{
2947	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2948	{
2949	paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
2950	paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
2951	}
2952
2953	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2954	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2955	}
2956	else
2957	{
2958	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2959	{
2960	paSelReg[iSelReg].fFlags = 0;
2961	paSelReg[iSelReg].ValidSel = 0;
2962	}
2963
2964	/* This might not be 104% correct, but I think it's close
2965	enough for all practical purposes... (REM always loaded
2966	LDTR registers.) */
2967	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2968	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2969	}
2970	pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2971	pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
2972	}
2973	}
2974
2975	/* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
2976	if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2977	&& uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2978	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2979	{
2980	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2981	pVCpu->cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
2982	}
2983
2984	/*
2985	* A quick sanity check.
2986	*/
2987	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2988	{
2989	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2990	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2991	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2992	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2993	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2994	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2995	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2996	}
2997	}
2998
2999	pVM->cpum.s.fPendingRestore = false;
3000
3001	/*
3002	* Guest CPUIDs (and VMX MSR features).
3003	*/
3004	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2)
3005	{
3006	CPUMMSRS GuestMsrs;
3007	RT_ZERO(GuestMsrs);
3008
3009	CPUMFEATURES BaseFeatures;
3010	bool const fVmxGstFeat = pVM->cpum.s.GuestFeatures.fVmx;
3011	if (fVmxGstFeat)
3012	{
3013	/*
3014	* At this point the MSRs in the guest CPU-context are loaded with the guest VMX MSRs from the saved state.
3015	* However the VMX sub-features have not been exploded yet. So cache the base (host derived) VMX features
3016	* here so we can compare them for compatibility after exploding guest features.
3017	*/
3018	BaseFeatures = pVM->cpum.s.GuestFeatures;
3019
3020	/* Use the VMX MSR features from the saved state while exploding guest features. */
3021	GuestMsrs.hwvirt.vmx = pVM->apCpusR3[0]->cpum.s.Guest.hwvirt.vmx.Msrs;
3022	}
3023
3024	/* Load CPUID and explode guest features. */
3025	rc = cpumR3LoadCpuId(pVM, pSSM, uVersion, &GuestMsrs);
3026	if (fVmxGstFeat)
3027	{
3028	/*
3029	* Check if the exploded VMX features from the saved state are compatible with the host-derived features
3030	* we cached earlier (above). The is required if we use hardware-assisted nested-guest execution with
3031	* VMX features presented to the guest.
3032	*/
3033	bool const fIsCompat = cpumR3AreVmxCpuFeaturesCompatible(pVM, &BaseFeatures, &pVM->cpum.s.GuestFeatures);
3034	if (!fIsCompat)
3035	return VERR_CPUM_INVALID_HWVIRT_FEAT_COMBO;
3036	}
3037	return rc;
3038	}
3039	return cpumR3LoadCpuIdPre32(pVM, pSSM, uVersion);
3040	}
3041
3042
3043	/**
3044	* @callback_method_impl{FNSSMINTLOADDONE}
3045	*/
3046	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
3047	{
3048	if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
3049	return VINF_SUCCESS;
3050
3051	/* just check this since we can. / /* @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
3052	if (pVM->cpum.s.fPendingRestore)
3053	{
3054	LogRel(("CPUM: Missing state!\n"));
3055	return VERR_INTERNAL_ERROR_2;
3056	}
3057
3058	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
3059	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3060	{
3061	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3062
3063	/* Notify PGM of the NXE states in case they've changed. */
3064	PGMNotifyNxeChanged(pVCpu, RT_BOOL(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
3065
3066	/* During init. this is done in CPUMR3InitCompleted(). */
3067	if (fSupportsLongMode)
3068	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
3069	}
3070	return VINF_SUCCESS;
3071	}
3072
3073
3074	/**
3075	* Checks if the CPUM state restore is still pending.
3076	*
3077	* @returns true / false.
3078	* @param pVM The cross context VM structure.
3079	*/
3080	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
3081	{
3082	return pVM->cpum.s.fPendingRestore;
3083	}
3084
3085
3086	/**
3087	* Formats the EFLAGS value into mnemonics.
3088	*
3089	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
3090	* @param efl The EFLAGS value.
3091	*/
3092	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
3093	{
3094	/*
3095	* Format the flags.
3096	*/
3097	static const struct
3098	{
3099	const char pszSet; const char pszClear; uint32_t fFlag;
3100	} s_aFlags[] =
3101	{
3102	{ "vip",NULL, X86_EFL_VIP },
3103	{ "vif",NULL, X86_EFL_VIF },
3104	{ "ac", NULL, X86_EFL_AC },
3105	{ "vm", NULL, X86_EFL_VM },
3106	{ "rf", NULL, X86_EFL_RF },
3107	{ "nt", NULL, X86_EFL_NT },
3108	{ "ov", "nv", X86_EFL_OF },
3109	{ "dn", "up", X86_EFL_DF },
3110	{ "ei", "di", X86_EFL_IF },
3111	{ "tf", NULL, X86_EFL_TF },
3112	{ "nt", "pl", X86_EFL_SF },
3113	{ "nz", "zr", X86_EFL_ZF },
3114	{ "ac", "na", X86_EFL_AF },
3115	{ "po", "pe", X86_EFL_PF },
3116	{ "cy", "nc", X86_EFL_CF },
3117	};
3118	char *psz = pszEFlags;
3119	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
3120	{
3121	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
3122	if (pszAdd)
3123	{
3124	strcpy(psz, pszAdd);
3125	psz += strlen(pszAdd);
3126	*psz++ = ' ';
3127	}
3128	}
3129	psz[-1] = '\0';
3130	}
3131
3132
3133	/**
3134	* Formats a full register dump.
3135	*
3136	* @param pVM The cross context VM structure.
3137	* @param pCtx The context to format.
3138	* @param pCtxCore The context core to format.
3139	* @param pHlp Output functions.
3140	* @param enmType The dump type.
3141	* @param pszPrefix Register name prefix.
3142	*/
3143	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
3144	const char *pszPrefix)
3145	{
3146	NOREF(pVM);
3147
3148	/*
3149	* Format the EFLAGS.
3150	*/
3151	uint32_t efl = pCtxCore->eflags.u32;
3152	char szEFlags[80];
3153	cpumR3InfoFormatFlags(&szEFlags[0], efl);
3154
3155	/*
3156	* Format the registers.
3157	*/
3158	switch (enmType)
3159	{
3160	case CPUMDUMPTYPE_TERSE:
3161	if (CPUMIsGuestIn64BitCodeEx(pCtx))
3162	pHlp->pfnPrintf(pHlp,
3163	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3164	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3165	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3166	"%sr14=%016RX64 %sr15=%016RX64\n"
3167	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3168	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
3169	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3170	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3171	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3172	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3173	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3174	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
3175	else
3176	pHlp->pfnPrintf(pHlp,
3177	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3178	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3179	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
3180	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3181	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3182	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3183	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
3184	break;
3185
3186	case CPUMDUMPTYPE_DEFAULT:
3187	if (CPUMIsGuestIn64BitCodeEx(pCtx))
3188	pHlp->pfnPrintf(pHlp,
3189	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3190	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3191	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3192	"%sr14=%016RX64 %sr15=%016RX64\n"
3193	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3194	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
3195	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
3196	,
3197	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3198	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3199	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3200	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3201	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3202	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
3203	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3204	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
3205	else
3206	pHlp->pfnPrintf(pHlp,
3207	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3208	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3209	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
3210	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
3211	,
3212	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3213	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3214	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3215	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
3216	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3217	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
3218	break;
3219
3220	case CPUMDUMPTYPE_VERBOSE:
3221	if (CPUMIsGuestIn64BitCodeEx(pCtx))
3222	pHlp->pfnPrintf(pHlp,
3223	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3224	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3225	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3226	"%sr14=%016RX64 %sr15=%016RX64\n"
3227	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3228	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3229	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3230	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3231	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3232	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3233	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3234	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
3235	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
3236	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
3237	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
3238	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3239	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3240	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
3241	,
3242	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3243	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3244	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3245	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3246	pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
3247	pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
3248	pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
3249	pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
3250	pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
3251	pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
3252	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3253	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
3254	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
3255	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
3256	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
3257	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
3258	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3259	else
3260	pHlp->pfnPrintf(pHlp,
3261	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3262	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3263	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
3264	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
3265	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
3266	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
3267	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
3268	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
3269	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
3270	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3271	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3272	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
3273	,
3274	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3275	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3276	pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
3277	pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
3278	pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
3279	pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
3280	pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
3281	pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3282	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
3283	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
3284	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
3285	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3286
3287	pHlp->pfnPrintf(pHlp, "%sxcr=%016RX64 %sxcr1=%016RX64 %sxss=%016RX64 (fXStateMask=%016RX64)\n",
3288	pszPrefix, pCtx->aXcr[0], pszPrefix, pCtx->aXcr[1],
3289	pszPrefix, UINT64_C(0) /** @todo XSS */, pCtx->fXStateMask);
3290	if (pCtx->CTX_SUFF(pXState))
3291	{
3292	PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
3293	pHlp->pfnPrintf(pHlp,
3294	"%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
3295	"%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
3296	,
3297	pszPrefix, pFpuCtx->FCW, pszPrefix, pFpuCtx->FSW, pszPrefix, pFpuCtx->FTW, pszPrefix, pFpuCtx->FOP,
3298	pszPrefix, pFpuCtx->MXCSR, pszPrefix, pFpuCtx->MXCSR_MASK,
3299	pszPrefix, pFpuCtx->FPUIP, pszPrefix, pFpuCtx->CS, pszPrefix, pFpuCtx->Rsrvd1,
3300	pszPrefix, pFpuCtx->FPUDP, pszPrefix, pFpuCtx->DS, pszPrefix, pFpuCtx->Rsrvd2
3301	);
3302	/*
3303	* The FSAVE style memory image contains ST(0)-ST(7) at increasing addresses,
3304	* not (FP)R0-7 as Intel SDM suggests.
3305	*/
3306	unsigned iShift = (pFpuCtx->FSW >> 11) & 7;
3307	for (unsigned iST = 0; iST < RT_ELEMENTS(pFpuCtx->aRegs); iST++)
3308	{
3309	unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pFpuCtx->aRegs);
3310	unsigned uTag = (pFpuCtx->FTW >> (2 * iFPR)) & 3;
3311	char chSign = pFpuCtx->aRegs[iST].au16[4] & 0x8000 ? '-' : '+';
3312	unsigned iInteger = (unsigned)(pFpuCtx->aRegs[iST].au64[0] >> 63);
3313	uint64_t u64Fraction = pFpuCtx->aRegs[iST].au64[0] & UINT64_C(0x7fffffffffffffff);
3314	int iExponent = pFpuCtx->aRegs[iST].au16[4] & 0x7fff;
3315	iExponent -= 16383; /* subtract bias */
3316	/** @todo This isn't entirenly correct and needs more work! */
3317	pHlp->pfnPrintf(pHlp,
3318	"%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu * 2 ^ %d (*)",
3319	pszPrefix, iST, pszPrefix, iFPR,
3320	pFpuCtx->aRegs[iST].au16[4], pFpuCtx->aRegs[iST].au32[1], pFpuCtx->aRegs[iST].au32[0],
3321	uTag, chSign, iInteger, u64Fraction, iExponent);
3322	if (pFpuCtx->aRegs[iST].au16[5] \|\| pFpuCtx->aRegs[iST].au16[6] \|\| pFpuCtx->aRegs[iST].au16[7])
3323	pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
3324	pFpuCtx->aRegs[iST].au16[5], pFpuCtx->aRegs[iST].au16[6], pFpuCtx->aRegs[iST].au16[7]);
3325	else
3326	pHlp->pfnPrintf(pHlp, "\n");
3327	}
3328
3329	/* XMM/YMM/ZMM registers. */
3330	if (pCtx->fXStateMask & XSAVE_C_YMM)
3331	{
3332	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
3333	if (!(pCtx->fXStateMask & XSAVE_C_ZMM_HI256))
3334	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3335	pHlp->pfnPrintf(pHlp, "%sYMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3336	pszPrefix, i, i < 10 ? " " : "",
3337	pYmmHiCtx->aYmmHi[i].au32[3],
3338	pYmmHiCtx->aYmmHi[i].au32[2],
3339	pYmmHiCtx->aYmmHi[i].au32[1],
3340	pYmmHiCtx->aYmmHi[i].au32[0],
3341	pFpuCtx->aXMM[i].au32[3],
3342	pFpuCtx->aXMM[i].au32[2],
3343	pFpuCtx->aXMM[i].au32[1],
3344	pFpuCtx->aXMM[i].au32[0]);
3345	else
3346	{
3347	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
3348	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3349	pHlp->pfnPrintf(pHlp,
3350	"%sZMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3351	pszPrefix, i, i < 10 ? " " : "",
3352	pZmmHi256->aHi256Regs[i].au32[7],
3353	pZmmHi256->aHi256Regs[i].au32[6],
3354	pZmmHi256->aHi256Regs[i].au32[5],
3355	pZmmHi256->aHi256Regs[i].au32[4],
3356	pZmmHi256->aHi256Regs[i].au32[3],
3357	pZmmHi256->aHi256Regs[i].au32[2],
3358	pZmmHi256->aHi256Regs[i].au32[1],
3359	pZmmHi256->aHi256Regs[i].au32[0],
3360	pYmmHiCtx->aYmmHi[i].au32[3],
3361	pYmmHiCtx->aYmmHi[i].au32[2],
3362	pYmmHiCtx->aYmmHi[i].au32[1],
3363	pYmmHiCtx->aYmmHi[i].au32[0],
3364	pFpuCtx->aXMM[i].au32[3],
3365	pFpuCtx->aXMM[i].au32[2],
3366	pFpuCtx->aXMM[i].au32[1],
3367	pFpuCtx->aXMM[i].au32[0]);
3368
3369	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
3370	for (unsigned i = 0; i < RT_ELEMENTS(pZmm16Hi->aRegs); i++)
3371	pHlp->pfnPrintf(pHlp,
3372	"%sZMM%u=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3373	pszPrefix, i + 16,
3374	pZmm16Hi->aRegs[i].au32[15],
3375	pZmm16Hi->aRegs[i].au32[14],
3376	pZmm16Hi->aRegs[i].au32[13],
3377	pZmm16Hi->aRegs[i].au32[12],
3378	pZmm16Hi->aRegs[i].au32[11],
3379	pZmm16Hi->aRegs[i].au32[10],
3380	pZmm16Hi->aRegs[i].au32[9],
3381	pZmm16Hi->aRegs[i].au32[8],
3382	pZmm16Hi->aRegs[i].au32[7],
3383	pZmm16Hi->aRegs[i].au32[6],
3384	pZmm16Hi->aRegs[i].au32[5],
3385	pZmm16Hi->aRegs[i].au32[4],
3386	pZmm16Hi->aRegs[i].au32[3],
3387	pZmm16Hi->aRegs[i].au32[2],
3388	pZmm16Hi->aRegs[i].au32[1],
3389	pZmm16Hi->aRegs[i].au32[0]);
3390	}
3391	}
3392	else
3393	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3394	pHlp->pfnPrintf(pHlp,
3395	i & 1
3396	? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
3397	: "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
3398	pszPrefix, i, i < 10 ? " " : "",
3399	pFpuCtx->aXMM[i].au32[3],
3400	pFpuCtx->aXMM[i].au32[2],
3401	pFpuCtx->aXMM[i].au32[1],
3402	pFpuCtx->aXMM[i].au32[0]);
3403
3404	if (pCtx->fXStateMask & XSAVE_C_OPMASK)
3405	{
3406	PCX86XSAVEOPMASK pOpMask = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_OPMASK_BIT, PCX86XSAVEOPMASK);
3407	for (unsigned i = 0; i < RT_ELEMENTS(pOpMask->aKRegs); i += 4)
3408	pHlp->pfnPrintf(pHlp, "%sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64\n",
3409	pszPrefix, i + 0, pOpMask->aKRegs[i + 0],
3410	pszPrefix, i + 1, pOpMask->aKRegs[i + 1],
3411	pszPrefix, i + 2, pOpMask->aKRegs[i + 2],
3412	pszPrefix, i + 3, pOpMask->aKRegs[i + 3]);
3413	}
3414
3415	if (pCtx->fXStateMask & XSAVE_C_BNDREGS)
3416	{
3417	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
3418	for (unsigned i = 0; i < RT_ELEMENTS(pBndRegs->aRegs); i += 2)
3419	pHlp->pfnPrintf(pHlp, "%sBNDREG%u=%016RX64/%016RX64 %sBNDREG%u=%016RX64/%016RX64\n",
3420	pszPrefix, i, pBndRegs->aRegs[i].uLowerBound, pBndRegs->aRegs[i].uUpperBound,
3421	pszPrefix, i + 1, pBndRegs->aRegs[i + 1].uLowerBound, pBndRegs->aRegs[i + 1].uUpperBound);
3422	}
3423
3424	if (pCtx->fXStateMask & XSAVE_C_BNDCSR)
3425	{
3426	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
3427	pHlp->pfnPrintf(pHlp, "%sBNDCFG.CONFIG=%016RX64 %sBNDCFG.STATUS=%016RX64\n",
3428	pszPrefix, pBndCfg->fConfig, pszPrefix, pBndCfg->fStatus);
3429	}
3430
3431	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->au32RsrvdRest); i++)
3432	if (pFpuCtx->au32RsrvdRest[i])
3433	pHlp->pfnPrintf(pHlp, "%sRsrvdRest[%u]=%RX32 (offset=%#x)\n",
3434	pszPrefix, i, pFpuCtx->au32RsrvdRest[i], RT_UOFFSETOF_DYN(X86FXSTATE, au32RsrvdRest[i]) );
3435	}
3436
3437	pHlp->pfnPrintf(pHlp,
3438	"%sEFER =%016RX64\n"
3439	"%sPAT =%016RX64\n"
3440	"%sSTAR =%016RX64\n"
3441	"%sCSTAR =%016RX64\n"
3442	"%sLSTAR =%016RX64\n"
3443	"%sSFMASK =%016RX64\n"
3444	"%sKERNELGSBASE =%016RX64\n",
3445	pszPrefix, pCtx->msrEFER,
3446	pszPrefix, pCtx->msrPAT,
3447	pszPrefix, pCtx->msrSTAR,
3448	pszPrefix, pCtx->msrCSTAR,
3449	pszPrefix, pCtx->msrLSTAR,
3450	pszPrefix, pCtx->msrSFMASK,
3451	pszPrefix, pCtx->msrKERNELGSBASE);
3452	break;
3453	}
3454	}
3455
3456
3457	/**
3458	* Display all cpu states and any other cpum info.
3459	*
3460	* @param pVM The cross context VM structure.
3461	* @param pHlp The info helper functions.
3462	* @param pszArgs Arguments, ignored.
3463	*/
3464	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3465	{
3466	cpumR3InfoGuest(pVM, pHlp, pszArgs);
3467	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
3468	cpumR3InfoGuestHwvirt(pVM, pHlp, pszArgs);
3469	cpumR3InfoHyper(pVM, pHlp, pszArgs);
3470	cpumR3InfoHost(pVM, pHlp, pszArgs);
3471	}
3472
3473
3474	/**
3475	* Parses the info argument.
3476	*
3477	* The argument starts with 'verbose', 'terse' or 'default' and then
3478	* continues with the comment string.
3479	*
3480	* @param pszArgs The pointer to the argument string.
3481	* @param penmType Where to store the dump type request.
3482	* @param ppszComment Where to store the pointer to the comment string.
3483	*/
3484	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
3485	{
3486	if (!pszArgs)
3487	{
3488	*penmType = CPUMDUMPTYPE_DEFAULT;
3489	*ppszComment = "";
3490	}
3491	else
3492	{
3493	if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
3494	{
3495	pszArgs += 7;
3496	*penmType = CPUMDUMPTYPE_VERBOSE;
3497	}
3498	else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
3499	{
3500	pszArgs += 5;
3501	*penmType = CPUMDUMPTYPE_TERSE;
3502	}
3503	else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
3504	{
3505	pszArgs += 7;
3506	*penmType = CPUMDUMPTYPE_DEFAULT;
3507	}
3508	else
3509	*penmType = CPUMDUMPTYPE_DEFAULT;
3510	*ppszComment = RTStrStripL(pszArgs);
3511	}
3512	}
3513
3514
3515	/**
3516	* Display the guest cpu state.
3517	*
3518	* @param pVM The cross context VM structure.
3519	* @param pHlp The info helper functions.
3520	* @param pszArgs Arguments.
3521	*/
3522	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3523	{
3524	CPUMDUMPTYPE enmType;
3525	const char *pszComment;
3526	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3527
3528	PVMCPU pVCpu = VMMGetCpu(pVM);
3529	if (!pVCpu)
3530	pVCpu = pVM->apCpusR3[0];
3531
3532	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
3533
3534	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3535	cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
3536	}
3537
3538
3539	/**
3540	* Displays an SVM VMCB control area.
3541	*
3542	* @param pHlp The info helper functions.
3543	* @param pVmcbCtrl Pointer to a SVM VMCB controls area.
3544	* @param pszPrefix Caller specified string prefix.
3545	*/
3546	static void cpumR3InfoSvmVmcbCtrl(PCDBGFINFOHLP pHlp, PCSVMVMCBCTRL pVmcbCtrl, const char *pszPrefix)
3547	{
3548	AssertReturnVoid(pHlp);
3549	AssertReturnVoid(pVmcbCtrl);
3550
3551	pHlp->pfnPrintf(pHlp, "%sCRX-read intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdCRx);
3552	pHlp->pfnPrintf(pHlp, "%sCRX-write intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrCRx);
3553	pHlp->pfnPrintf(pHlp, "%sDRX-read intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdDRx);
3554	pHlp->pfnPrintf(pHlp, "%sDRX-write intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrDRx);
3555	pHlp->pfnPrintf(pHlp, "%sException intercepts = %#RX32\n", pszPrefix, pVmcbCtrl->u32InterceptXcpt);
3556	pHlp->pfnPrintf(pHlp, "%sControl intercepts = %#RX64\n", pszPrefix, pVmcbCtrl->u64InterceptCtrl);
3557	pHlp->pfnPrintf(pHlp, "%sPause-filter threshold = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterThreshold);
3558	pHlp->pfnPrintf(pHlp, "%sPause-filter count = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterCount);
3559	pHlp->pfnPrintf(pHlp, "%sIOPM bitmap physaddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64IOPMPhysAddr);
3560	pHlp->pfnPrintf(pHlp, "%sMSRPM bitmap physaddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64MSRPMPhysAddr);
3561	pHlp->pfnPrintf(pHlp, "%sTSC offset = %#RX64\n", pszPrefix, pVmcbCtrl->u64TSCOffset);
3562	pHlp->pfnPrintf(pHlp, "%sTLB Control\n", pszPrefix);
3563	pHlp->pfnPrintf(pHlp, " %sASID = %#RX32\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u32ASID);
3564	pHlp->pfnPrintf(pHlp, " %sTLB-flush type = %u\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u8TLBFlush);
3565	pHlp->pfnPrintf(pHlp, "%sInterrupt Control\n", pszPrefix);
3566	pHlp->pfnPrintf(pHlp, " %sVTPR = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VTPR, pVmcbCtrl->IntCtrl.n.u8VTPR);
3567	pHlp->pfnPrintf(pHlp, " %sVIRQ (Pending) = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIrqPending);
3568	pHlp->pfnPrintf(pHlp, " %sVINTR vector = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VIntrVector);
3569	pHlp->pfnPrintf(pHlp, " %sVGIF = %u\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGif);
3570	pHlp->pfnPrintf(pHlp, " %sVINTR priority = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u4VIntrPrio);
3571	pHlp->pfnPrintf(pHlp, " %sIgnore TPR = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1IgnoreTPR);
3572	pHlp->pfnPrintf(pHlp, " %sVINTR masking = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIntrMasking);
3573	pHlp->pfnPrintf(pHlp, " %sVGIF enable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGifEnable);
3574	pHlp->pfnPrintf(pHlp, " %sAVIC enable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1AvicEnable);
3575	pHlp->pfnPrintf(pHlp, "%sInterrupt Shadow\n", pszPrefix);
3576	pHlp->pfnPrintf(pHlp, " %sInterrupt shadow = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1IntShadow);
3577	pHlp->pfnPrintf(pHlp, " %sGuest-interrupt Mask = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1GuestIntMask);
3578	pHlp->pfnPrintf(pHlp, "%sExit Code = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitCode);
3579	pHlp->pfnPrintf(pHlp, "%sEXITINFO1 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo1);
3580	pHlp->pfnPrintf(pHlp, "%sEXITINFO2 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo2);
3581	pHlp->pfnPrintf(pHlp, "%sExit Interrupt Info\n", pszPrefix);
3582	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1Valid);
3583	pHlp->pfnPrintf(pHlp, " %sVector = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u8Vector, pVmcbCtrl->ExitIntInfo.n.u8Vector);
3584	pHlp->pfnPrintf(pHlp, " %sType = %u\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u3Type);
3585	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1ErrorCodeValid);
3586	pHlp->pfnPrintf(pHlp, " %sError-code = %#RX32\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u32ErrorCode);
3587	pHlp->pfnPrintf(pHlp, "%sNested paging and SEV\n", pszPrefix);
3588	pHlp->pfnPrintf(pHlp, " %sNested paging = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging);
3589	pHlp->pfnPrintf(pHlp, " %sSEV (Secure Encrypted VM) = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1Sev);
3590	pHlp->pfnPrintf(pHlp, " %sSEV-ES (Encrypted State) = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1SevEs);
3591	pHlp->pfnPrintf(pHlp, "%sEvent Inject\n", pszPrefix);
3592	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1Valid);
3593	pHlp->pfnPrintf(pHlp, " %sVector = %#RX32 (%u)\n", pszPrefix, pVmcbCtrl->EventInject.n.u8Vector, pVmcbCtrl->EventInject.n.u8Vector);
3594	pHlp->pfnPrintf(pHlp, " %sType = %u\n", pszPrefix, pVmcbCtrl->EventInject.n.u3Type);
3595	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1ErrorCodeValid);
3596	pHlp->pfnPrintf(pHlp, " %sError-code = %#RX32\n", pszPrefix, pVmcbCtrl->EventInject.n.u32ErrorCode);
3597	pHlp->pfnPrintf(pHlp, "%sNested-paging CR3 = %#RX64\n", pszPrefix, pVmcbCtrl->u64NestedPagingCR3);
3598	pHlp->pfnPrintf(pHlp, "%sLBR Virtualization\n", pszPrefix);
3599	pHlp->pfnPrintf(pHlp, " %sLBR virt = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1LbrVirt);
3600	pHlp->pfnPrintf(pHlp, " %sVirt. VMSAVE/VMLOAD = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1VirtVmsaveVmload);
3601	pHlp->pfnPrintf(pHlp, "%sVMCB Clean Bits = %#RX32\n", pszPrefix, pVmcbCtrl->u32VmcbCleanBits);
3602	pHlp->pfnPrintf(pHlp, "%sNext-RIP = %#RX64\n", pszPrefix, pVmcbCtrl->u64NextRIP);
3603	pHlp->pfnPrintf(pHlp, "%sInstruction bytes fetched = %u\n", pszPrefix, pVmcbCtrl->cbInstrFetched);
3604	pHlp->pfnPrintf(pHlp, "%sInstruction bytes = %.*Rhxs\n", pszPrefix, sizeof(pVmcbCtrl->abInstr), pVmcbCtrl->abInstr);
3605	pHlp->pfnPrintf(pHlp, "%sAVIC\n", pszPrefix);
3606	pHlp->pfnPrintf(pHlp, " %sBar addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBar.n.u40Addr);
3607	pHlp->pfnPrintf(pHlp, " %sBacking page addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBackingPagePtr.n.u40Addr);
3608	pHlp->pfnPrintf(pHlp, " %sLogical table addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicLogicalTablePtr.n.u40Addr);
3609	pHlp->pfnPrintf(pHlp, " %sPhysical table addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u40Addr);
3610	pHlp->pfnPrintf(pHlp, " %sLast guest core Id = %u\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u8LastGuestCoreId);
3611	}
3612
3613
3614	/**
3615	* Helper for dumping the SVM VMCB selector registers.
3616	*
3617	* @param pHlp The info helper functions.
3618	* @param pSel Pointer to the SVM selector register.
3619	* @param pszName Name of the selector.
3620	* @param pszPrefix Caller specified string prefix.
3621	*/
3622	DECLINLINE(void) cpumR3InfoSvmVmcbSelReg(PCDBGFINFOHLP pHlp, PCSVMSELREG pSel, const char pszName, const char pszPrefix)
3623	{
3624	/* The string width of 4 used below is to handle 'LDTR'. Change later if longer register names are used. */
3625	pHlp->pfnPrintf(pHlp, "%s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", pszPrefix,
3626	pszName, pSel->u16Sel, pSel->u64Base, pSel->u32Limit, pSel->u16Attr);
3627	}
3628
3629
3630	/**
3631	* Helper for dumping the SVM VMCB GDTR/IDTR registers.
3632	*
3633	* @param pHlp The info helper functions.
3634	* @param pXdtr Pointer to the descriptor table register.
3635	* @param pszName Name of the descriptor table register.
3636	* @param pszPrefix Caller specified string prefix.
3637	*/
3638	DECLINLINE(void) cpumR3InfoSvmVmcbXdtr(PCDBGFINFOHLP pHlp, PCSVMXDTR pXdtr, const char pszName, const char pszPrefix)
3639	{
3640	/* The string width of 4 used below is to cover 'GDTR', 'IDTR'. Change later if longer register names are used. */
3641	pHlp->pfnPrintf(pHlp, "%s%-4s = %016RX64:%04x\n", pszPrefix, pszName, pXdtr->u64Base, pXdtr->u32Limit);
3642	}
3643
3644
3645	/**
3646	* Displays an SVM VMCB state-save area.
3647	*
3648	* @param pHlp The info helper functions.
3649	* @param pVmcbStateSave Pointer to a SVM VMCB controls area.
3650	* @param pszPrefix Caller specified string prefix.
3651	*/
3652	static void cpumR3InfoSvmVmcbStateSave(PCDBGFINFOHLP pHlp, PCSVMVMCBSTATESAVE pVmcbStateSave, const char *pszPrefix)
3653	{
3654	AssertReturnVoid(pHlp);
3655	AssertReturnVoid(pVmcbStateSave);
3656
3657	char szEFlags[80];
3658	cpumR3InfoFormatFlags(&szEFlags[0], pVmcbStateSave->u64RFlags);
3659
3660	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->CS, "CS", pszPrefix);
3661	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->SS, "SS", pszPrefix);
3662	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->ES, "ES", pszPrefix);
3663	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->DS, "DS", pszPrefix);
3664	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->FS, "FS", pszPrefix);
3665	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->GS, "GS", pszPrefix);
3666	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->LDTR, "LDTR", pszPrefix);
3667	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->TR, "TR", pszPrefix);
3668	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->GDTR, "GDTR", pszPrefix);
3669	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->IDTR, "IDTR", pszPrefix);
3670	pHlp->pfnPrintf(pHlp, "%sCPL = %u\n", pszPrefix, pVmcbStateSave->u8CPL);
3671	pHlp->pfnPrintf(pHlp, "%sEFER = %#RX64\n", pszPrefix, pVmcbStateSave->u64EFER);
3672	pHlp->pfnPrintf(pHlp, "%sCR4 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR4);
3673	pHlp->pfnPrintf(pHlp, "%sCR3 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR3);
3674	pHlp->pfnPrintf(pHlp, "%sCR0 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR0);
3675	pHlp->pfnPrintf(pHlp, "%sDR7 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR7);
3676	pHlp->pfnPrintf(pHlp, "%sDR6 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR6);
3677	pHlp->pfnPrintf(pHlp, "%sRFLAGS = %#RX64 %31s\n", pszPrefix, pVmcbStateSave->u64RFlags, szEFlags);
3678	pHlp->pfnPrintf(pHlp, "%sRIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RIP);
3679	pHlp->pfnPrintf(pHlp, "%sRSP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RSP);
3680	pHlp->pfnPrintf(pHlp, "%sRAX = %#RX64\n", pszPrefix, pVmcbStateSave->u64RAX);
3681	pHlp->pfnPrintf(pHlp, "%sSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64STAR);
3682	pHlp->pfnPrintf(pHlp, "%sLSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64LSTAR);
3683	pHlp->pfnPrintf(pHlp, "%sCSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64CSTAR);
3684	pHlp->pfnPrintf(pHlp, "%sSFMASK = %#RX64\n", pszPrefix, pVmcbStateSave->u64SFMASK);
3685	pHlp->pfnPrintf(pHlp, "%sKERNELGSBASE = %#RX64\n", pszPrefix, pVmcbStateSave->u64KernelGSBase);
3686	pHlp->pfnPrintf(pHlp, "%sSysEnter CS = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterCS);
3687	pHlp->pfnPrintf(pHlp, "%sSysEnter EIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterEIP);
3688	pHlp->pfnPrintf(pHlp, "%sSysEnter ESP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterESP);
3689	pHlp->pfnPrintf(pHlp, "%sCR2 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR2);
3690	pHlp->pfnPrintf(pHlp, "%sPAT = %#RX64\n", pszPrefix, pVmcbStateSave->u64PAT);
3691	pHlp->pfnPrintf(pHlp, "%sDBGCTL = %#RX64\n", pszPrefix, pVmcbStateSave->u64DBGCTL);
3692	pHlp->pfnPrintf(pHlp, "%sBR_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_FROM);
3693	pHlp->pfnPrintf(pHlp, "%sBR_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_TO);
3694	pHlp->pfnPrintf(pHlp, "%sLASTXCPT_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPFROM);
3695	pHlp->pfnPrintf(pHlp, "%sLASTXCPT_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPTO);
3696	}
3697
3698
3699	/**
3700	* Displays a virtual-VMCS.
3701	*
3702	* @param pVCpu The cross context virtual CPU structure.
3703	* @param pHlp The info helper functions.
3704	* @param pVmcs Pointer to a virtual VMCS.
3705	* @param pszPrefix Caller specified string prefix.
3706	*/
3707	static void cpumR3InfoVmxVmcs(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, PCVMXVVMCS pVmcs, const char *pszPrefix)
3708	{
3709	AssertReturnVoid(pHlp);
3710	AssertReturnVoid(pVmcs);
3711
3712	/* The string width of -4 used in the macros below to cover 'LDTR', 'GDTR', 'IDTR. */
3713	#define CPUMVMX_DUMP_HOST_XDTR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3714	do { \
3715	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {base=%016RX64}\n", \
3716	(a_pszPrefix), (a_SegName), (a_pVmcs)->u64Host##a_Seg##Base.u); \
3717	} while (0)
3718
3719	#define CPUMVMX_DUMP_HOST_FS_GS_TR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3720	do { \
3721	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {%04x base=%016RX64}\n", \
3722	(a_pszPrefix), (a_SegName), (a_pVmcs)->Host##a_Seg, (a_pVmcs)->u64Host##a_Seg##Base.u); \
3723	} while (0)
3724
3725	#define CPUMVMX_DUMP_GUEST_SEGREG(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3726	do { \
3727	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", \
3728	(a_pszPrefix), (a_SegName), (a_pVmcs)->Guest##a_Seg, (a_pVmcs)->u64Guest##a_Seg##Base.u, \
3729	(a_pVmcs)->u32Guest##a_Seg##Limit, (a_pVmcs)->u32Guest##a_Seg##Attr); \
3730	} while (0)
3731
3732	#define CPUMVMX_DUMP_GUEST_XDTR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3733	do { \
3734	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {base=%016RX64 limit=%08x}\n", \
3735	(a_pszPrefix), (a_SegName), (a_pVmcs)->u64Guest##a_Seg##Base.u, (a_pVmcs)->u32Guest##a_Seg##Limit); \
3736	} while (0)
3737
3738	/* Header. */
3739	{
3740	pHlp->pfnPrintf(pHlp, "%sHeader:\n", pszPrefix);
3741	pHlp->pfnPrintf(pHlp, " %sVMCS revision id = %#RX32\n", pszPrefix, pVmcs->u32VmcsRevId);
3742	pHlp->pfnPrintf(pHlp, " %sVMX-abort id = %#RX32 (%s)\n", pszPrefix, pVmcs->enmVmxAbort, VMXGetAbortDesc(pVmcs->enmVmxAbort));
3743	pHlp->pfnPrintf(pHlp, " %sVMCS state = %#x (%s)\n", pszPrefix, pVmcs->fVmcsState, VMXGetVmcsStateDesc(pVmcs->fVmcsState));
3744	}
3745
3746	/* Control fields. */
3747	{
3748	/* 16-bit. */
3749	pHlp->pfnPrintf(pHlp, "%sControl:\n", pszPrefix);
3750	pHlp->pfnPrintf(pHlp, " %sVPID = %#RX16\n", pszPrefix, pVmcs->u16Vpid);
3751	pHlp->pfnPrintf(pHlp, " %sPosted intr notify vector = %#RX16\n", pszPrefix, pVmcs->u16PostIntNotifyVector);
3752	pHlp->pfnPrintf(pHlp, " %sEPTP index = %#RX16\n", pszPrefix, pVmcs->u16EptpIndex);
3753
3754	/* 32-bit. */
3755	pHlp->pfnPrintf(pHlp, " %sPin ctls = %#RX32\n", pszPrefix, pVmcs->u32PinCtls);
3756	pHlp->pfnPrintf(pHlp, " %sProcessor ctls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls);
3757	pHlp->pfnPrintf(pHlp, " %sSecondary processor ctls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls2);
3758	pHlp->pfnPrintf(pHlp, " %sVM-exit ctls = %#RX32\n", pszPrefix, pVmcs->u32ExitCtls);
3759	pHlp->pfnPrintf(pHlp, " %sVM-entry ctls = %#RX32\n", pszPrefix, pVmcs->u32EntryCtls);
3760	pHlp->pfnPrintf(pHlp, " %sException bitmap = %#RX32\n", pszPrefix, pVmcs->u32XcptBitmap);
3761	pHlp->pfnPrintf(pHlp, " %sPage-fault mask = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMask);
3762	pHlp->pfnPrintf(pHlp, " %sPage-fault match = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMatch);
3763	pHlp->pfnPrintf(pHlp, " %sCR3-target count = %RU32\n", pszPrefix, pVmcs->u32Cr3TargetCount);
3764	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR store count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrStoreCount);
3765	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR load count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrLoadCount);
3766	pHlp->pfnPrintf(pHlp, " %sVM-entry MSR load count = %RU32\n", pszPrefix, pVmcs->u32EntryMsrLoadCount);
3767	pHlp->pfnPrintf(pHlp, " %sVM-entry interruption info = %#RX32\n", pszPrefix, pVmcs->u32EntryIntInfo);
3768	{
3769	uint32_t const fInfo = pVmcs->u32EntryIntInfo;
3770	uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(fInfo);
3771	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_VALID(fInfo));
3772	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetEntryIntInfoTypeDesc(uType));
3773	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_ENTRY_INT_INFO_VECTOR(fInfo));
3774	pHlp->pfnPrintf(pHlp, " %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo));
3775	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(fInfo));
3776	}
3777	pHlp->pfnPrintf(pHlp, " %sVM-entry xcpt error-code = %#RX32\n", pszPrefix, pVmcs->u32EntryXcptErrCode);
3778	pHlp->pfnPrintf(pHlp, " %sVM-entry instr length = %u byte(s)\n", pszPrefix, pVmcs->u32EntryInstrLen);
3779	pHlp->pfnPrintf(pHlp, " %sTPR threshold = %#RX32\n", pszPrefix, pVmcs->u32TprThreshold);
3780	pHlp->pfnPrintf(pHlp, " %sPLE gap = %#RX32\n", pszPrefix, pVmcs->u32PleGap);
3781	pHlp->pfnPrintf(pHlp, " %sPLE window = %#RX32\n", pszPrefix, pVmcs->u32PleWindow);
3782
3783	/* 64-bit. */
3784	pHlp->pfnPrintf(pHlp, " %sIO-bitmap A addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapA.u);
3785	pHlp->pfnPrintf(pHlp, " %sIO-bitmap B addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapB.u);
3786	pHlp->pfnPrintf(pHlp, " %sMSR-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrMsrBitmap.u);
3787	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR store addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrStore.u);
3788	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrLoad.u);
3789	pHlp->pfnPrintf(pHlp, " %sVM-entry MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEntryMsrLoad.u);
3790	pHlp->pfnPrintf(pHlp, " %sExecutive VMCS ptr = %#RX64\n", pszPrefix, pVmcs->u64ExecVmcsPtr.u);
3791	pHlp->pfnPrintf(pHlp, " %sPML addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPml.u);
3792	pHlp->pfnPrintf(pHlp, " %sTSC offset = %#RX64\n", pszPrefix, pVmcs->u64TscOffset.u);
3793	pHlp->pfnPrintf(pHlp, " %sVirtual-APIC addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVirtApic.u);
3794	pHlp->pfnPrintf(pHlp, " %sAPIC-access addr = %#RX64\n", pszPrefix, pVmcs->u64AddrApicAccess.u);
3795	pHlp->pfnPrintf(pHlp, " %sPosted-intr desc addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPostedIntDesc.u);
3796	pHlp->pfnPrintf(pHlp, " %sVM-functions control = %#RX64\n", pszPrefix, pVmcs->u64VmFuncCtls.u);
3797	pHlp->pfnPrintf(pHlp, " %sEPTP ptr = %#RX64\n", pszPrefix, pVmcs->u64EptpPtr.u);
3798	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 0 addr = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap0.u);
3799	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 1 addr = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap1.u);
3800	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 2 addr = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap2.u);
3801	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 3 addr = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap3.u);
3802	pHlp->pfnPrintf(pHlp, " %sEPTP-list addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEptpList.u);
3803	pHlp->pfnPrintf(pHlp, " %sVMREAD-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmreadBitmap.u);
3804	pHlp->pfnPrintf(pHlp, " %sVMWRITE-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmwriteBitmap.u);
3805	pHlp->pfnPrintf(pHlp, " %sVirt-Xcpt info addr = %#RX64\n", pszPrefix, pVmcs->u64AddrXcptVeInfo.u);
3806	pHlp->pfnPrintf(pHlp, " %sXSS-bitmap = %#RX64\n", pszPrefix, pVmcs->u64XssBitmap.u);
3807	pHlp->pfnPrintf(pHlp, " %sENCLS-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64EnclsBitmap.u);
3808	pHlp->pfnPrintf(pHlp, " %sSPPT ptr = %#RX64\n", pszPrefix, pVmcs->u64SpptPtr.u);
3809	pHlp->pfnPrintf(pHlp, " %sTSC multiplier = %#RX64\n", pszPrefix, pVmcs->u64TscMultiplier.u);
3810
3811	/* Natural width. */
3812	pHlp->pfnPrintf(pHlp, " %sCR0 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr0Mask.u);
3813	pHlp->pfnPrintf(pHlp, " %sCR4 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr4Mask.u);
3814	pHlp->pfnPrintf(pHlp, " %sCR0 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr0ReadShadow.u);
3815	pHlp->pfnPrintf(pHlp, " %sCR4 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr4ReadShadow.u);
3816	pHlp->pfnPrintf(pHlp, " %sCR3-target 0 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target0.u);
3817	pHlp->pfnPrintf(pHlp, " %sCR3-target 1 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target1.u);
3818	pHlp->pfnPrintf(pHlp, " %sCR3-target 2 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target2.u);
3819	pHlp->pfnPrintf(pHlp, " %sCR3-target 3 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target3.u);
3820	}
3821
3822	/* Guest state. */
3823	{
3824	char szEFlags[80];
3825	cpumR3InfoFormatFlags(&szEFlags[0], pVmcs->u64GuestRFlags.u);
3826	pHlp->pfnPrintf(pHlp, "%sGuest state:\n", pszPrefix);
3827
3828	/* 16-bit. */
3829	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Cs, "cs", pszPrefix);
3830	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ss, "ss", pszPrefix);
3831	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Es, "es", pszPrefix);
3832	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ds, "ds", pszPrefix);
3833	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Fs, "fs", pszPrefix);
3834	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Gs, "gs", pszPrefix);
3835	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ldtr, "ldtr", pszPrefix);
3836	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Tr, "tr", pszPrefix);
3837	CPUMVMX_DUMP_GUEST_XDTR(pHlp, pVmcs, Gdtr, "gdtr", pszPrefix);
3838	CPUMVMX_DUMP_GUEST_XDTR(pHlp, pVmcs, Idtr, "idtr", pszPrefix);
3839	pHlp->pfnPrintf(pHlp, " %sInterrupt status = %#RX16\n", pszPrefix, pVmcs->u16GuestIntStatus);
3840	pHlp->pfnPrintf(pHlp, " %sPML index = %#RX16\n", pszPrefix, pVmcs->u16PmlIndex);
3841
3842	/* 32-bit. */
3843	pHlp->pfnPrintf(pHlp, " %sInterruptibility state = %#RX32\n", pszPrefix, pVmcs->u32GuestIntrState);
3844	pHlp->pfnPrintf(pHlp, " %sActivity state = %#RX32\n", pszPrefix, pVmcs->u32GuestActivityState);
3845	pHlp->pfnPrintf(pHlp, " %sSMBASE = %#RX32\n", pszPrefix, pVmcs->u32GuestSmBase);
3846	pHlp->pfnPrintf(pHlp, " %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32GuestSysenterCS);
3847	pHlp->pfnPrintf(pHlp, " %sVMX-preemption timer value = %#RX32\n", pszPrefix, pVmcs->u32PreemptTimer);
3848
3849	/* 64-bit. */
3850	pHlp->pfnPrintf(pHlp, " %sVMCS link ptr = %#RX64\n", pszPrefix, pVmcs->u64VmcsLinkPtr.u);
3851	pHlp->pfnPrintf(pHlp, " %sDBGCTL = %#RX64\n", pszPrefix, pVmcs->u64GuestDebugCtlMsr.u);
3852	pHlp->pfnPrintf(pHlp, " %sPAT = %#RX64\n", pszPrefix, pVmcs->u64GuestPatMsr.u);
3853	pHlp->pfnPrintf(pHlp, " %sEFER = %#RX64\n", pszPrefix, pVmcs->u64GuestEferMsr.u);
3854	pHlp->pfnPrintf(pHlp, " %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64GuestPerfGlobalCtlMsr.u);
3855	pHlp->pfnPrintf(pHlp, " %sPDPTE 0 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte0.u);
3856	pHlp->pfnPrintf(pHlp, " %sPDPTE 1 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte1.u);
3857	pHlp->pfnPrintf(pHlp, " %sPDPTE 2 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte2.u);
3858	pHlp->pfnPrintf(pHlp, " %sPDPTE 3 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte3.u);
3859	pHlp->pfnPrintf(pHlp, " %sBNDCFGS = %#RX64\n", pszPrefix, pVmcs->u64GuestBndcfgsMsr.u);
3860	pHlp->pfnPrintf(pHlp, " %sRTIT_CTL = %#RX64\n", pszPrefix, pVmcs->u64GuestRtitCtlMsr.u);
3861
3862	/* Natural width. */
3863	pHlp->pfnPrintf(pHlp, " %scr0 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr0.u);
3864	pHlp->pfnPrintf(pHlp, " %scr3 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr3.u);
3865	pHlp->pfnPrintf(pHlp, " %scr4 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr4.u);
3866	pHlp->pfnPrintf(pHlp, " %sdr7 = %#RX64\n", pszPrefix, pVmcs->u64GuestDr7.u);
3867	pHlp->pfnPrintf(pHlp, " %srsp = %#RX64\n", pszPrefix, pVmcs->u64GuestRsp.u);
3868	pHlp->pfnPrintf(pHlp, " %srip = %#RX64\n", pszPrefix, pVmcs->u64GuestRip.u);
3869	pHlp->pfnPrintf(pHlp, " %srflags = %#RX64 %31s\n",pszPrefix, pVmcs->u64GuestRFlags.u, szEFlags);
3870	pHlp->pfnPrintf(pHlp, " %sPending debug xcpts = %#RX64\n", pszPrefix, pVmcs->u64GuestPendingDbgXcpts.u);
3871	pHlp->pfnPrintf(pHlp, " %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEsp.u);
3872	pHlp->pfnPrintf(pHlp, " %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEip.u);
3873	}
3874
3875	/* Host state. */
3876	{
3877	pHlp->pfnPrintf(pHlp, "%sHost state:\n", pszPrefix);
3878
3879	/* 16-bit. */
3880	pHlp->pfnPrintf(pHlp, " %scs = %#RX16\n", pszPrefix, pVmcs->HostCs);
3881	pHlp->pfnPrintf(pHlp, " %sss = %#RX16\n", pszPrefix, pVmcs->HostSs);
3882	pHlp->pfnPrintf(pHlp, " %sds = %#RX16\n", pszPrefix, pVmcs->HostDs);
3883	pHlp->pfnPrintf(pHlp, " %ses = %#RX16\n", pszPrefix, pVmcs->HostEs);
3884	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Fs, "fs", pszPrefix);
3885	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Gs, "gs", pszPrefix);
3886	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Tr, "tr", pszPrefix);
3887	CPUMVMX_DUMP_HOST_XDTR(pHlp, pVmcs, Gdtr, "gdtr", pszPrefix);
3888	CPUMVMX_DUMP_HOST_XDTR(pHlp, pVmcs, Idtr, "idtr", pszPrefix);
3889
3890	/* 32-bit. */
3891	pHlp->pfnPrintf(pHlp, " %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32HostSysenterCs);
3892
3893	/* 64-bit. */
3894	pHlp->pfnPrintf(pHlp, " %sEFER = %#RX64\n", pszPrefix, pVmcs->u64HostEferMsr.u);
3895	pHlp->pfnPrintf(pHlp, " %sPAT = %#RX64\n", pszPrefix, pVmcs->u64HostPatMsr.u);
3896	pHlp->pfnPrintf(pHlp, " %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64HostPerfGlobalCtlMsr.u);
3897
3898	/* Natural width. */
3899	pHlp->pfnPrintf(pHlp, " %scr0 = %#RX64\n", pszPrefix, pVmcs->u64HostCr0.u);
3900	pHlp->pfnPrintf(pHlp, " %scr3 = %#RX64\n", pszPrefix, pVmcs->u64HostCr3.u);
3901	pHlp->pfnPrintf(pHlp, " %scr4 = %#RX64\n", pszPrefix, pVmcs->u64HostCr4.u);
3902	pHlp->pfnPrintf(pHlp, " %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEsp.u);
3903	pHlp->pfnPrintf(pHlp, " %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEip.u);
3904	pHlp->pfnPrintf(pHlp, " %srsp = %#RX64\n", pszPrefix, pVmcs->u64HostRsp.u);
3905	pHlp->pfnPrintf(pHlp, " %srip = %#RX64\n", pszPrefix, pVmcs->u64HostRip.u);
3906	}
3907
3908	/* Read-only fields. */
3909	{
3910	pHlp->pfnPrintf(pHlp, "%sRead-only data fields:\n", pszPrefix);
3911
3912	/* 16-bit (none currently). */
3913
3914	/* 32-bit. */
3915	pHlp->pfnPrintf(pHlp, " %sExit reason = %u (%s)\n", pszPrefix, pVmcs->u32RoExitReason, HMGetVmxExitName(pVmcs->u32RoExitReason));
3916	pHlp->pfnPrintf(pHlp, " %sExit qualification = %#RX64\n", pszPrefix, pVmcs->u64RoExitQual.u);
3917	pHlp->pfnPrintf(pHlp, " %sVM-instruction error = %#RX32\n", pszPrefix, pVmcs->u32RoVmInstrError);
3918	pHlp->pfnPrintf(pHlp, " %sVM-exit intr info = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntInfo);
3919	{
3920	uint32_t const fInfo = pVmcs->u32RoExitIntInfo;
3921	uint8_t const uType = VMX_EXIT_INT_INFO_TYPE(fInfo);
3922	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_VALID(fInfo));
3923	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetExitIntInfoTypeDesc(uType));
3924	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_EXIT_INT_INFO_VECTOR(fInfo));
3925	pHlp->pfnPrintf(pHlp, " %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo));
3926	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(fInfo));
3927	}
3928	pHlp->pfnPrintf(pHlp, " %sVM-exit intr error-code = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntErrCode);
3929	pHlp->pfnPrintf(pHlp, " %sIDT-vectoring info = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringInfo);
3930	{
3931	uint32_t const fInfo = pVmcs->u32RoIdtVectoringInfo;
3932	uint8_t const uType = VMX_IDT_VECTORING_INFO_TYPE(fInfo);
3933	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_VALID(fInfo));
3934	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetIdtVectoringInfoTypeDesc(uType));
3935	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_IDT_VECTORING_INFO_VECTOR(fInfo));
3936	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(fInfo));
3937	}
3938	pHlp->pfnPrintf(pHlp, " %sIDT-vectoring error-code = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringErrCode);
3939	pHlp->pfnPrintf(pHlp, " %sVM-exit instruction length = %u byte(s)\n", pszPrefix, pVmcs->u32RoExitInstrLen);
3940	pHlp->pfnPrintf(pHlp, " %sVM-exit instruction info = %#RX64\n", pszPrefix, pVmcs->u32RoExitInstrInfo);
3941
3942	/* 64-bit. */
3943	pHlp->pfnPrintf(pHlp, " %sGuest-physical addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestPhysAddr.u);
3944
3945	/* Natural width. */
3946	pHlp->pfnPrintf(pHlp, " %sI/O RCX = %#RX64\n", pszPrefix, pVmcs->u64RoIoRcx.u);
3947	pHlp->pfnPrintf(pHlp, " %sI/O RSI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRsi.u);
3948	pHlp->pfnPrintf(pHlp, " %sI/O RDI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRdi.u);
3949	pHlp->pfnPrintf(pHlp, " %sI/O RIP = %#RX64\n", pszPrefix, pVmcs->u64RoIoRip.u);
3950	pHlp->pfnPrintf(pHlp, " %sGuest-linear addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestLinearAddr.u);
3951	}
3952
3953	#ifdef DEBUG_ramshankar
3954	if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
3955	{
3956	void *pvPage = RTMemTmpAllocZ(VMX_V_VIRT_APIC_SIZE);
3957	Assert(pvPage);
3958	RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3959	int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pvPage, GCPhysVirtApic, VMX_V_VIRT_APIC_SIZE);
3960	if (RT_SUCCESS(rc))
3961	{
3962	pHlp->pfnPrintf(pHlp, " %sVirtual-APIC page\n", pszPrefix);
3963	pHlp->pfnPrintf(pHlp, "%.*Rhxs\n", VMX_V_VIRT_APIC_SIZE, pvPage);
3964	pHlp->pfnPrintf(pHlp, "\n");
3965	}
3966	RTMemTmpFree(pvPage);
3967	}
3968	#else
3969	NOREF(pVCpu);
3970	#endif
3971
3972	#undef CPUMVMX_DUMP_HOST_XDTR
3973	#undef CPUMVMX_DUMP_HOST_FS_GS_TR
3974	#undef CPUMVMX_DUMP_GUEST_SEGREG
3975	#undef CPUMVMX_DUMP_GUEST_XDTR
3976	}
3977
3978
3979	/**
3980	* Display the guest's hardware-virtualization cpu state.
3981	*
3982	* @param pVM The cross context VM structure.
3983	* @param pHlp The info helper functions.
3984	* @param pszArgs Arguments, ignored.
3985	*/
3986	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3987	{
3988	RT_NOREF(pszArgs);
3989
3990	PVMCPU pVCpu = VMMGetCpu(pVM);
3991	if (!pVCpu)
3992	pVCpu = pVM->apCpusR3[0];
3993
3994	/*
3995	* Figure out what to dump.
3996	*
3997	* In the future we may need to dump everything whether or not we're actively in nested-guest mode
3998	* or not, hence the reason why we use a mask to determine what needs dumping. Currently, we only
3999	* dump hwvirt. state when the guest CPU is executing a nested-guest.
4000	*/
4001	/** @todo perhaps make this configurable through pszArgs, depending on how much
4002	* noise we wish to accept when nested hwvirt. isn't used. */
4003	#define CPUMHWVIRTDUMP_NONE (0)
4004	#define CPUMHWVIRTDUMP_SVM RT_BIT(0)
4005	#define CPUMHWVIRTDUMP_VMX RT_BIT(1)
4006	#define CPUMHWVIRTDUMP_COMMON RT_BIT(2)
4007	#define CPUMHWVIRTDUMP_LAST CPUMHWVIRTDUMP_VMX
4008
4009	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
4010	static const char *const s_aHwvirtModes[] = { "No/inactive", "SVM", "VMX", "Common" };
4011	bool const fSvm = pVM->cpum.s.GuestFeatures.fSvm;
4012	bool const fVmx = pVM->cpum.s.GuestFeatures.fVmx;
4013	uint8_t const idxHwvirtState = fSvm ? CPUMHWVIRTDUMP_SVM : (fVmx ? CPUMHWVIRTDUMP_VMX : CPUMHWVIRTDUMP_NONE);
4014	AssertCompile(CPUMHWVIRTDUMP_LAST <= RT_ELEMENTS(s_aHwvirtModes));
4015	Assert(idxHwvirtState < RT_ELEMENTS(s_aHwvirtModes));
4016	const char *pcszHwvirtMode = s_aHwvirtModes[idxHwvirtState];
4017	uint32_t fDumpState = idxHwvirtState \| CPUMHWVIRTDUMP_COMMON;
4018
4019	/*
4020	* Dump it.
4021	*/
4022	pHlp->pfnPrintf(pHlp, "VCPU[%u] hardware virtualization state:\n", pVCpu->idCpu);
4023
4024	if (fDumpState & CPUMHWVIRTDUMP_COMMON)
4025	pHlp->pfnPrintf(pHlp, "fLocalForcedActions = %#RX32\n", pCtx->hwvirt.fLocalForcedActions);
4026
4027	pHlp->pfnPrintf(pHlp, "%s hwvirt state%s\n", pcszHwvirtMode, (fDumpState & (CPUMHWVIRTDUMP_SVM \| CPUMHWVIRTDUMP_VMX)) ?
4028	":" : "");
4029	if (fDumpState & CPUMHWVIRTDUMP_SVM)
4030	{
4031	pHlp->pfnPrintf(pHlp, " fGif = %RTbool\n", pCtx->hwvirt.fGif);
4032
4033	char szEFlags[80];
4034	cpumR3InfoFormatFlags(&szEFlags[0], pCtx->hwvirt.svm.HostState.rflags.u);
4035	pHlp->pfnPrintf(pHlp, " uMsrHSavePa = %#RX64\n", pCtx->hwvirt.svm.uMsrHSavePa);
4036	pHlp->pfnPrintf(pHlp, " GCPhysVmcb = %#RGp\n", pCtx->hwvirt.svm.GCPhysVmcb);
4037	pHlp->pfnPrintf(pHlp, " VmcbCtrl:\n");
4038	cpumR3InfoSvmVmcbCtrl(pHlp, &pCtx->hwvirt.svm.pVmcbR3->ctrl, " " /* pszPrefix */);
4039	pHlp->pfnPrintf(pHlp, " VmcbStateSave:\n");
4040	cpumR3InfoSvmVmcbStateSave(pHlp, &pCtx->hwvirt.svm.pVmcbR3->guest, " " /* pszPrefix */);
4041	pHlp->pfnPrintf(pHlp, " HostState:\n");
4042	pHlp->pfnPrintf(pHlp, " uEferMsr = %#RX64\n", pCtx->hwvirt.svm.HostState.uEferMsr);
4043	pHlp->pfnPrintf(pHlp, " uCr0 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr0);
4044	pHlp->pfnPrintf(pHlp, " uCr4 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr4);
4045	pHlp->pfnPrintf(pHlp, " uCr3 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr3);
4046	pHlp->pfnPrintf(pHlp, " uRip = %#RX64\n", pCtx->hwvirt.svm.HostState.uRip);
4047	pHlp->pfnPrintf(pHlp, " uRsp = %#RX64\n", pCtx->hwvirt.svm.HostState.uRsp);
4048	pHlp->pfnPrintf(pHlp, " uRax = %#RX64\n", pCtx->hwvirt.svm.HostState.uRax);
4049	pHlp->pfnPrintf(pHlp, " rflags = %#RX64 %31s\n", pCtx->hwvirt.svm.HostState.rflags.u64, szEFlags);
4050	PCPUMSELREG pSel = &pCtx->hwvirt.svm.HostState.es;
4051	pHlp->pfnPrintf(pHlp, " es = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4052	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
4053	pSel = &pCtx->hwvirt.svm.HostState.cs;
4054	pHlp->pfnPrintf(pHlp, " cs = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4055	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
4056	pSel = &pCtx->hwvirt.svm.HostState.ss;
4057	pHlp->pfnPrintf(pHlp, " ss = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4058	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
4059	pSel = &pCtx->hwvirt.svm.HostState.ds;
4060	pHlp->pfnPrintf(pHlp, " ds = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4061	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
4062	pHlp->pfnPrintf(pHlp, " gdtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.gdtr.pGdt,
4063	pCtx->hwvirt.svm.HostState.gdtr.cbGdt);
4064	pHlp->pfnPrintf(pHlp, " idtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.idtr.pIdt,
4065	pCtx->hwvirt.svm.HostState.idtr.cbIdt);
4066	pHlp->pfnPrintf(pHlp, " cPauseFilter = %RU16\n", pCtx->hwvirt.svm.cPauseFilter);
4067	pHlp->pfnPrintf(pHlp, " cPauseFilterThreshold = %RU32\n", pCtx->hwvirt.svm.cPauseFilterThreshold);
4068	pHlp->pfnPrintf(pHlp, " fInterceptEvents = %u\n", pCtx->hwvirt.svm.fInterceptEvents);
4069	pHlp->pfnPrintf(pHlp, " pvMsrBitmapR3 = %p\n", pCtx->hwvirt.svm.pvMsrBitmapR3);
4070	pHlp->pfnPrintf(pHlp, " pvMsrBitmapR0 = %RKv\n", pCtx->hwvirt.svm.pvMsrBitmapR0);
4071	pHlp->pfnPrintf(pHlp, " pvIoBitmapR3 = %p\n", pCtx->hwvirt.svm.pvIoBitmapR3);
4072	pHlp->pfnPrintf(pHlp, " pvIoBitmapR0 = %RKv\n", pCtx->hwvirt.svm.pvIoBitmapR0);
4073	}
4074
4075	if (fDumpState & CPUMHWVIRTDUMP_VMX)
4076	{
4077	pHlp->pfnPrintf(pHlp, " GCPhysVmxon = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmxon);
4078	pHlp->pfnPrintf(pHlp, " GCPhysVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmcs);
4079	pHlp->pfnPrintf(pHlp, " GCPhysShadowVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysShadowVmcs);
4080	pHlp->pfnPrintf(pHlp, " enmDiag = %u (%s)\n", pCtx->hwvirt.vmx.enmDiag, HMGetVmxDiagDesc(pCtx->hwvirt.vmx.enmDiag));
4081	pHlp->pfnPrintf(pHlp, " uDiagAux = %#RX64\n", pCtx->hwvirt.vmx.uDiagAux);
4082	pHlp->pfnPrintf(pHlp, " enmAbort = %u (%s)\n", pCtx->hwvirt.vmx.enmAbort, VMXGetAbortDesc(pCtx->hwvirt.vmx.enmAbort));
4083	pHlp->pfnPrintf(pHlp, " uAbortAux = %u (%#x)\n", pCtx->hwvirt.vmx.uAbortAux, pCtx->hwvirt.vmx.uAbortAux);
4084	pHlp->pfnPrintf(pHlp, " fInVmxRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxRootMode);
4085	pHlp->pfnPrintf(pHlp, " fInVmxNonRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxNonRootMode);
4086	pHlp->pfnPrintf(pHlp, " fInterceptEvents = %RTbool\n", pCtx->hwvirt.vmx.fInterceptEvents);
4087	pHlp->pfnPrintf(pHlp, " fNmiUnblockingIret = %RTbool\n", pCtx->hwvirt.vmx.fNmiUnblockingIret);
4088	pHlp->pfnPrintf(pHlp, " uFirstPauseLoopTick = %RX64\n", pCtx->hwvirt.vmx.uFirstPauseLoopTick);
4089	pHlp->pfnPrintf(pHlp, " uPrevPauseTick = %RX64\n", pCtx->hwvirt.vmx.uPrevPauseTick);
4090	pHlp->pfnPrintf(pHlp, " uEntryTick = %RX64\n", pCtx->hwvirt.vmx.uEntryTick);
4091	pHlp->pfnPrintf(pHlp, " offVirtApicWrite = %#RX16\n", pCtx->hwvirt.vmx.offVirtApicWrite);
4092	pHlp->pfnPrintf(pHlp, " fVirtNmiBlocking = %RTbool\n", pCtx->hwvirt.vmx.fVirtNmiBlocking);
4093	pHlp->pfnPrintf(pHlp, " VMCS cache:\n");
4094	cpumR3InfoVmxVmcs(pVCpu, pHlp, pCtx->hwvirt.vmx.pVmcsR3, " " /* pszPrefix */);
4095	}
4096
4097	#undef CPUMHWVIRTDUMP_NONE
4098	#undef CPUMHWVIRTDUMP_COMMON
4099	#undef CPUMHWVIRTDUMP_SVM
4100	#undef CPUMHWVIRTDUMP_VMX
4101	#undef CPUMHWVIRTDUMP_LAST
4102	#undef CPUMHWVIRTDUMP_ALL
4103	}
4104
4105	/**
4106	* Display the current guest instruction
4107	*
4108	* @param pVM The cross context VM structure.
4109	* @param pHlp The info helper functions.
4110	* @param pszArgs Arguments, ignored.
4111	*/
4112	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4113	{
4114	NOREF(pszArgs);
4115
4116	PVMCPU pVCpu = VMMGetCpu(pVM);
4117	if (!pVCpu)
4118	pVCpu = pVM->apCpusR3[0];
4119
4120	char szInstruction[256];
4121	szInstruction[0] = '\0';
4122	DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
4123	pHlp->pfnPrintf(pHlp, "\nCPUM%u: %s\n\n", pVCpu->idCpu, szInstruction);
4124	}
4125
4126
4127	/**
4128	* Display the hypervisor cpu state.
4129	*
4130	* @param pVM The cross context VM structure.
4131	* @param pHlp The info helper functions.
4132	* @param pszArgs Arguments, ignored.
4133	*/
4134	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4135	{
4136	PVMCPU pVCpu = VMMGetCpu(pVM);
4137	if (!pVCpu)
4138	pVCpu = pVM->apCpusR3[0];
4139
4140	CPUMDUMPTYPE enmType;
4141	const char *pszComment;
4142	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
4143	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
4144
4145	pHlp->pfnPrintf(pHlp,
4146	".dr0=%016RX64 .dr1=%016RX64 .dr2=%016RX64 .dr3=%016RX64\n"
4147	".dr4=%016RX64 .dr5=%016RX64 .dr6=%016RX64 .dr7=%016RX64\n",
4148	pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1], pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3],
4149	pVCpu->cpum.s.Hyper.dr[4], pVCpu->cpum.s.Hyper.dr[5], pVCpu->cpum.s.Hyper.dr[6], pVCpu->cpum.s.Hyper.dr[7]);
4150	pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
4151	}
4152
4153
4154	/**
4155	* Display the host cpu state.
4156	*
4157	* @param pVM The cross context VM structure.
4158	* @param pHlp The info helper functions.
4159	* @param pszArgs Arguments, ignored.
4160	*/
4161	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4162	{
4163	CPUMDUMPTYPE enmType;
4164	const char *pszComment;
4165	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
4166	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
4167
4168	PVMCPU pVCpu = VMMGetCpu(pVM);
4169	if (!pVCpu)
4170	pVCpu = pVM->apCpusR3[0];
4171	PCPUMHOSTCTX pCtx = &pVCpu->cpum.s.Host;
4172
4173	/*
4174	* Format the EFLAGS.
4175	*/
4176	uint64_t efl = pCtx->rflags;
4177	char szEFlags[80];
4178	cpumR3InfoFormatFlags(&szEFlags[0], efl);
4179
4180	/*
4181	* Format the registers.
4182	*/
4183	pHlp->pfnPrintf(pHlp,
4184	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
4185	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
4186	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
4187	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
4188	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
4189	"r14=%016RX64 r15=%016RX64\n"
4190	"iopl=%d %31s\n"
4191	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
4192	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
4193	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
4194	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
4195	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
4196	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
4197	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
4198	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
4199	,
4200	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
4201	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
4202	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
4203	/pCtx->r8, pCtx->r9,/ pCtx->r10,
4204	pCtx->r11, pCtx->r12, pCtx->r13,
4205	pCtx->r14, pCtx->r15,
4206	X86_EFL_GET_IOPL(efl), szEFlags,
4207	pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
4208	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
4209	pCtx->cr4, pCtx->ldtr, pCtx->tr,
4210	pCtx->dr0, pCtx->dr1, pCtx->dr2,
4211	pCtx->dr3, pCtx->dr6, pCtx->dr7,
4212	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
4213	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
4214	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
4215	}
4216
4217	/**
4218	* Structure used when disassembling and instructions in DBGF.
4219	* This is used so the reader function can get the stuff it needs.
4220	*/
4221	typedef struct CPUMDISASSTATE
4222	{
4223	/** Pointer to the CPU structure. */
4224	PDISCPUSTATE pCpu;
4225	/** Pointer to the VM. */
4226	PVM pVM;
4227	/** Pointer to the VMCPU. */
4228	PVMCPU pVCpu;
4229	/** Pointer to the first byte in the segment. */
4230	RTGCUINTPTR GCPtrSegBase;
4231	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
4232	RTGCUINTPTR GCPtrSegEnd;
4233	/** The size of the segment minus 1. */
4234	RTGCUINTPTR cbSegLimit;
4235	/** Pointer to the current page - R3 Ptr. */
4236	void const *pvPageR3;
4237	/** Pointer to the current page - GC Ptr. */
4238	RTGCPTR pvPageGC;
4239	/** The lock information that PGMPhysReleasePageMappingLock needs. */
4240	PGMPAGEMAPLOCK PageMapLock;
4241	/** Whether the PageMapLock is valid or not. */
4242	bool fLocked;
4243	/** 64 bits mode or not. */
4244	bool f64Bits;
4245	} CPUMDISASSTATE, *PCPUMDISASSTATE;
4246
4247
4248	/**
4249	* @callback_method_impl{FNDISREADBYTES}
4250	*/
4251	static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
4252	{
4253	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
4254	for (;;)
4255	{
4256	RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
4257
4258	/*
4259	* Need to update the page translation?
4260	*/
4261	if ( !pState->pvPageR3
4262	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
4263	{
4264	/* translate the address */
4265	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
4266
4267	/* Release mapping lock previously acquired. */
4268	if (pState->fLocked)
4269	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
4270	int rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
4271	if (RT_SUCCESS(rc))
4272	pState->fLocked = true;
4273	else
4274	{
4275	pState->fLocked = false;
4276	pState->pvPageR3 = NULL;
4277	return rc;
4278	}
4279	}
4280
4281	/*
4282	* Check the segment limit.
4283	*/
4284	if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
4285	return VERR_OUT_OF_SELECTOR_BOUNDS;
4286
4287	/*
4288	* Calc how much we can read.
4289	*/
4290	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
4291	if (!pState->f64Bits)
4292	{
4293	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
4294	if (cb > cbSeg && cbSeg)
4295	cb = cbSeg;
4296	}
4297	if (cb > cbMaxRead)
4298	cb = cbMaxRead;
4299
4300	/*
4301	* Read and advance or exit.
4302	*/
4303	memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
4304	offInstr += (uint8_t)cb;
4305	if (cb >= cbMinRead)
4306	{
4307	pDis->cbCachedInstr = offInstr;
4308	return VINF_SUCCESS;
4309	}
4310	cbMinRead -= (uint8_t)cb;
4311	cbMaxRead -= (uint8_t)cb;
4312	}
4313	}
4314
4315
4316	/**
4317	* Disassemble an instruction and return the information in the provided structure.
4318	*
4319	* @returns VBox status code.
4320	* @param pVM The cross context VM structure.
4321	* @param pVCpu The cross context virtual CPU structure.
4322	* @param pCtx Pointer to the guest CPU context.
4323	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
4324	* @param pCpu Disassembly state.
4325	* @param pszPrefix String prefix for logging (debug only).
4326	*
4327	*/
4328	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu,
4329	const char *pszPrefix)
4330	{
4331	CPUMDISASSTATE State;
4332	int rc;
4333
4334	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
4335	State.pCpu = pCpu;
4336	State.pvPageGC = 0;
4337	State.pvPageR3 = NULL;
4338	State.pVM = pVM;
4339	State.pVCpu = pVCpu;
4340	State.fLocked = false;
4341	State.f64Bits = false;
4342
4343	/*
4344	* Get selector information.
4345	*/
4346	DISCPUMODE enmDisCpuMode;
4347	if ( (pCtx->cr0 & X86_CR0_PE)
4348	&& pCtx->eflags.Bits.u1VM == 0)
4349	{
4350	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4351	return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
4352	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
4353	State.GCPtrSegBase = pCtx->cs.u64Base;
4354	State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
4355	State.cbSegLimit = pCtx->cs.u32Limit;
4356	enmDisCpuMode = (State.f64Bits)
4357	? DISCPUMODE_64BIT
4358	: pCtx->cs.Attr.n.u1DefBig
4359	? DISCPUMODE_32BIT
4360	: DISCPUMODE_16BIT;
4361	}
4362	else
4363	{
4364	/* real or V86 mode */
4365	enmDisCpuMode = DISCPUMODE_16BIT;
4366	State.GCPtrSegBase = pCtx->cs.Sel * 16;
4367	State.GCPtrSegEnd = 0xFFFFFFFF;
4368	State.cbSegLimit = 0xFFFFFFFF;
4369	}
4370
4371	/*
4372	* Disassemble the instruction.
4373	*/
4374	uint32_t cbInstr;
4375	#ifndef LOG_ENABLED
4376	RT_NOREF_PV(pszPrefix);
4377	rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
4378	if (RT_SUCCESS(rc))
4379	{
4380	#else
4381	char szOutput[160];
4382	rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
4383	pCpu, &cbInstr, szOutput, sizeof(szOutput));
4384	if (RT_SUCCESS(rc))
4385	{
4386	/* log it */
4387	if (pszPrefix)
4388	Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
4389	else
4390	Log(("%s", szOutput));
4391	#endif
4392	rc = VINF_SUCCESS;
4393	}
4394	else
4395	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
4396
4397	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
4398	if (State.fLocked)
4399	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
4400
4401	return rc;
4402	}
4403
4404
4405
4406	/**
4407	* API for controlling a few of the CPU features found in CR4.
4408	*
4409	* Currently only X86_CR4_TSD is accepted as input.
4410	*
4411	* @returns VBox status code.
4412	*
4413	* @param pVM The cross context VM structure.
4414	* @param fOr The CR4 OR mask.
4415	* @param fAnd The CR4 AND mask.
4416	*/
4417	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
4418	{
4419	AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
4420	AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
4421
4422	pVM->cpum.s.CR4.OrMask &= fAnd;
4423	pVM->cpum.s.CR4.OrMask \|= fOr;
4424
4425	return VINF_SUCCESS;
4426	}
4427
4428
4429	/**
4430	* Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
4431	*
4432	* Only REM should ever call this function!
4433	*
4434	* @returns The changed flags.
4435	* @param pVCpu The cross context virtual CPU structure.
4436	* @param puCpl Where to return the current privilege level (CPL).
4437	*/
4438	VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
4439	{
4440	Assert(!pVCpu->cpum.s.fRemEntered);
4441
4442	/*
4443	* Get the CPL first.
4444	*/
4445	*puCpl = CPUMGetGuestCPL(pVCpu);
4446
4447	/*
4448	* Get and reset the flags.
4449	*/
4450	uint32_t fFlags = pVCpu->cpum.s.fChanged;
4451	pVCpu->cpum.s.fChanged = 0;
4452
4453	/** @todo change the switcher to use the fChanged flags. */
4454	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
4455	{
4456	fFlags \|= CPUM_CHANGED_FPU_REM;
4457	pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
4458	}
4459
4460	pVCpu->cpum.s.fRemEntered = true;
4461	return fFlags;
4462	}
4463
4464
4465	/**
4466	* Leaves REM.
4467	*
4468	* @param pVCpu The cross context virtual CPU structure.
4469	* @param fNoOutOfSyncSels This is @c false if there are out of sync
4470	* registers.
4471	*/
4472	VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
4473	{
4474	Assert(pVCpu->cpum.s.fRemEntered);
4475
4476	RT_NOREF_PV(fNoOutOfSyncSels);
4477
4478	pVCpu->cpum.s.fRemEntered = false;
4479	}
4480
4481
4482	/**
4483	* Called when the ring-3 init phase completes.
4484	*
4485	* @returns VBox status code.
4486	* @param pVM The cross context VM structure.
4487	* @param enmWhat Which init phase.
4488	*/
4489	VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
4490	{
4491	switch (enmWhat)
4492	{
4493	case VMINITCOMPLETED_RING3:
4494	{
4495	/*
4496	* Figure out if the guest uses 32-bit or 64-bit FPU state at runtime for 64-bit capable VMs.
4497	* Only applicable/used on 64-bit hosts, refer CPUMR0A.asm. See @bugref{7138}.
4498	*/
4499	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
4500	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4501	{
4502	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4503
4504	/* While loading a saved-state we fix it up in, cpumR3LoadDone(). */
4505	if (fSupportsLongMode)
4506	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
4507	}
4508
4509	/* Register statistic counters for MSRs. */
4510	cpumR3MsrRegStats(pVM);
4511	break;
4512	}
4513
4514	default:
4515	break;
4516	}
4517	return VINF_SUCCESS;
4518	}
4519
4520
4521	/**
4522	* Called when the ring-0 init phases completed.
4523	*
4524	* @param pVM The cross context VM structure.
4525	*/
4526	VMMR3DECL(void) CPUMR3LogCpuIdAndMsrFeatures(PVM pVM)
4527	{
4528	/*
4529	* Enable log buffering as we're going to log a lot of lines.
4530	*/
4531	bool const fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
4532
4533	/*
4534	* Log the cpuid.
4535	*/
4536	RTCPUSET OnlineSet;
4537	LogRel(("CPUM: Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
4538	(unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
4539	RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
4540	RTCPUID cCores = RTMpGetCoreCount();
4541	if (cCores)
4542	LogRel(("CPUM: Physical host cores: %u\n", (unsigned)cCores));
4543	LogRel(("*********************** CPUID dump **********************\n"));
4544	DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
4545	LogRel(("\n"));
4546	DBGFR3_INFO_LOG_SAFE(pVM, "cpuid", "verbose"); /* macro */
4547	LogRel(("****************** End of CPUID dump ********************\n"));
4548
4549	/*
4550	* Log VT-x extended features.
4551	*
4552	* SVM features are currently all covered under CPUID so there is nothing
4553	* to do here for SVM.
4554	*/
4555	if (pVM->cpum.s.HostFeatures.fVmx)
4556	{
4557	LogRel(("********************* VT-x features *********************\n"));
4558	DBGFR3Info(pVM->pUVM, "cpumvmxfeat", "default", DBGFR3InfoLogRelHlp());
4559	LogRel(("\n"));
4560	LogRel(("***************** End of VT-x features ******************\n"));
4561	}
4562
4563	/*
4564	* Restore the log buffering state to what it was previously.
4565	*/
4566	RTLogRelSetBuffering(fOldBuffered);
4567	}
4568

注意: 瀏覽 TracBrowser 來幫助您使用儲存庫瀏覽器

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 81733

以其他格式下載: