VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 51934

最後變更 在這個檔案從51934是 51832,由 vboxsync 提交於 11 年 前

VMM/CPUM: todo.
  • 屬性 svn:eol-style 設為 native
  • 屬性 svn:keywords 設為 Id Revision
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1/* $Id: CPUM.cpp 51832 2014-07-03 05:12:28Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.alldomusa.eu.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_cpum CPUM - CPU Monitor / Manager
19 *
20 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
21 * also responsible for lazy FPU handling and some of the context loading
22 * in raw mode.
23 *
24 * There are three CPU contexts, the most important one is the guest one (GC).
25 * When running in raw-mode (RC) there is a special hyper context for the VMM
26 * part that floats around inside the guest address space. When running in
27 * raw-mode, CPUM also maintains a host context for saving and restoring
28 * registers across world switches. This latter is done in cooperation with the
29 * world switcher (@see pg_vmm).
30 *
31 * @see grp_cpum
32 */
33
34/*******************************************************************************
35* Header Files *
36*******************************************************************************/
37#define LOG_GROUP LOG_GROUP_CPUM
38#include <VBox/vmm/cpum.h>
39#include <VBox/vmm/cpumdis.h>
40#include <VBox/vmm/cpumctx-v1_6.h>
41#include <VBox/vmm/pgm.h>
42#include <VBox/vmm/pdmapi.h>
43#include <VBox/vmm/mm.h>
44#include <VBox/vmm/em.h>
45#include <VBox/vmm/selm.h>
46#include <VBox/vmm/dbgf.h>
47#include <VBox/vmm/patm.h>
48#include <VBox/vmm/hm.h>
49#include <VBox/vmm/ssm.h>
50#include "CPUMInternal.h"
51#include <VBox/vmm/vm.h>
52
53#include <VBox/param.h>
54#include <VBox/dis.h>
55#include <VBox/err.h>
56#include <VBox/log.h>
57#include <iprt/asm-amd64-x86.h>
58#include <iprt/assert.h>
59#include <iprt/cpuset.h>
60#include <iprt/mem.h>
61#include <iprt/mp.h>
62#include <iprt/string.h>
63#include "internal/pgm.h"
64
65
66/*******************************************************************************
67* Defined Constants And Macros *
68*******************************************************************************/
69/** The current saved state version. */
70#define CPUM_SAVED_STATE_VERSION 14
71/** The current saved state version before using SSMR3PutStruct. */
72#define CPUM_SAVED_STATE_VERSION_MEM 13
73/** The saved state version before introducing the MSR size field. */
74#define CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE 12
75/** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
76 * selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
77#define CPUM_SAVED_STATE_VERSION_VER3_2 11
78/** The saved state version of 3.0 and 3.1 trunk before the teleportation
79 * changes. */
80#define CPUM_SAVED_STATE_VERSION_VER3_0 10
81/** The saved state version for the 2.1 trunk before the MSR changes. */
82#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
83/** The saved state version of 2.0, used for backwards compatibility. */
84#define CPUM_SAVED_STATE_VERSION_VER2_0 8
85/** The saved state version of 1.6, used for backwards compatibility. */
86#define CPUM_SAVED_STATE_VERSION_VER1_6 6
87
88
89/**
90 * This was used in the saved state up to the early life of version 14.
91 *
92 * It indicates that we may have some out-of-sync hidden segement registers.
93 * It is only relevant for raw-mode.
94 */
95#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
96
97
98/*******************************************************************************
99* Structures and Typedefs *
100*******************************************************************************/
101
102/**
103 * What kind of cpu info dump to perform.
104 */
105typedef enum CPUMDUMPTYPE
106{
107 CPUMDUMPTYPE_TERSE,
108 CPUMDUMPTYPE_DEFAULT,
109 CPUMDUMPTYPE_VERBOSE
110} CPUMDUMPTYPE;
111/** Pointer to a cpu info dump type. */
112typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
113
114
115/*******************************************************************************
116* Internal Functions *
117*******************************************************************************/
118static int cpumR3CpuIdInit(PVM pVM);
119static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
120static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
121static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
122static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
123static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
124static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
125static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
126static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
127static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
128static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
129static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
130
131
132/*******************************************************************************
133* Global Variables *
134*******************************************************************************/
135/** Saved state field descriptors for CPUMCTX. */
136static const SSMFIELD g_aCpumCtxFields[] =
137{
138 SSMFIELD_ENTRY( CPUMCTX, fpu.FCW),
139 SSMFIELD_ENTRY( CPUMCTX, fpu.FSW),
140 SSMFIELD_ENTRY( CPUMCTX, fpu.FTW),
141 SSMFIELD_ENTRY( CPUMCTX, fpu.FOP),
142 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUIP),
143 SSMFIELD_ENTRY( CPUMCTX, fpu.CS),
144 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd1),
145 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUDP),
146 SSMFIELD_ENTRY( CPUMCTX, fpu.DS),
147 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd2),
148 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR),
149 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR_MASK),
150 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[0]),
151 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[1]),
152 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[2]),
153 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[3]),
154 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[4]),
155 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[5]),
156 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[6]),
157 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[7]),
158 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[0]),
159 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[1]),
160 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[2]),
161 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[3]),
162 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[4]),
163 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[5]),
164 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[6]),
165 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[7]),
166 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[8]),
167 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[9]),
168 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[10]),
169 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[11]),
170 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[12]),
171 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[13]),
172 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[14]),
173 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[15]),
174 SSMFIELD_ENTRY( CPUMCTX, rdi),
175 SSMFIELD_ENTRY( CPUMCTX, rsi),
176 SSMFIELD_ENTRY( CPUMCTX, rbp),
177 SSMFIELD_ENTRY( CPUMCTX, rax),
178 SSMFIELD_ENTRY( CPUMCTX, rbx),
179 SSMFIELD_ENTRY( CPUMCTX, rdx),
180 SSMFIELD_ENTRY( CPUMCTX, rcx),
181 SSMFIELD_ENTRY( CPUMCTX, rsp),
182 SSMFIELD_ENTRY( CPUMCTX, rflags),
183 SSMFIELD_ENTRY( CPUMCTX, rip),
184 SSMFIELD_ENTRY( CPUMCTX, r8),
185 SSMFIELD_ENTRY( CPUMCTX, r9),
186 SSMFIELD_ENTRY( CPUMCTX, r10),
187 SSMFIELD_ENTRY( CPUMCTX, r11),
188 SSMFIELD_ENTRY( CPUMCTX, r12),
189 SSMFIELD_ENTRY( CPUMCTX, r13),
190 SSMFIELD_ENTRY( CPUMCTX, r14),
191 SSMFIELD_ENTRY( CPUMCTX, r15),
192 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
193 SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
194 SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
195 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
196 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
197 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
198 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
199 SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
200 SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
201 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
202 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
203 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
204 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
205 SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
206 SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
207 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
208 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
209 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
210 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
211 SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
212 SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
213 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
214 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
215 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
216 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
217 SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
218 SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
219 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
220 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
221 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
222 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
223 SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
224 SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
225 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
226 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
227 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
228 SSMFIELD_ENTRY( CPUMCTX, cr0),
229 SSMFIELD_ENTRY( CPUMCTX, cr2),
230 SSMFIELD_ENTRY( CPUMCTX, cr3),
231 SSMFIELD_ENTRY( CPUMCTX, cr4),
232 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
233 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
234 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
235 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
236 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
237 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
238 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
239 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
240 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
241 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
242 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
243 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
244 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
245 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
246 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
247 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
248 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
249 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
250 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
251 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
252 /* msrApicBase is not included here, it resides in the APIC device state. */
253 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
254 SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
255 SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
256 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
257 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
258 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
259 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
260 SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
261 SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
262 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
263 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
264 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
265 SSMFIELD_ENTRY_TERM()
266};
267
268/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
269 * registeres changed. */
270static const SSMFIELD g_aCpumCtxFieldsMem[] =
271{
272 SSMFIELD_ENTRY( CPUMCTX, fpu.FCW),
273 SSMFIELD_ENTRY( CPUMCTX, fpu.FSW),
274 SSMFIELD_ENTRY( CPUMCTX, fpu.FTW),
275 SSMFIELD_ENTRY( CPUMCTX, fpu.FOP),
276 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUIP),
277 SSMFIELD_ENTRY( CPUMCTX, fpu.CS),
278 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd1),
279 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUDP),
280 SSMFIELD_ENTRY( CPUMCTX, fpu.DS),
281 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd2),
282 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR),
283 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR_MASK),
284 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[0]),
285 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[1]),
286 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[2]),
287 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[3]),
288 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[4]),
289 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[5]),
290 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[6]),
291 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[7]),
292 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[0]),
293 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[1]),
294 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[2]),
295 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[3]),
296 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[4]),
297 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[5]),
298 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[6]),
299 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[7]),
300 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[8]),
301 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[9]),
302 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[10]),
303 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[11]),
304 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[12]),
305 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[13]),
306 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[14]),
307 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[15]),
308 SSMFIELD_ENTRY_IGNORE( CPUMCTX, fpu.au32RsrvdRest),
309 SSMFIELD_ENTRY( CPUMCTX, rdi),
310 SSMFIELD_ENTRY( CPUMCTX, rsi),
311 SSMFIELD_ENTRY( CPUMCTX, rbp),
312 SSMFIELD_ENTRY( CPUMCTX, rax),
313 SSMFIELD_ENTRY( CPUMCTX, rbx),
314 SSMFIELD_ENTRY( CPUMCTX, rdx),
315 SSMFIELD_ENTRY( CPUMCTX, rcx),
316 SSMFIELD_ENTRY( CPUMCTX, rsp),
317 SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
318 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
319 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
320 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
321 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
322 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
323 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
324 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
325 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
326 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
327 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
328 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
329 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
330 SSMFIELD_ENTRY( CPUMCTX, rflags),
331 SSMFIELD_ENTRY( CPUMCTX, rip),
332 SSMFIELD_ENTRY( CPUMCTX, r8),
333 SSMFIELD_ENTRY( CPUMCTX, r9),
334 SSMFIELD_ENTRY( CPUMCTX, r10),
335 SSMFIELD_ENTRY( CPUMCTX, r11),
336 SSMFIELD_ENTRY( CPUMCTX, r12),
337 SSMFIELD_ENTRY( CPUMCTX, r13),
338 SSMFIELD_ENTRY( CPUMCTX, r14),
339 SSMFIELD_ENTRY( CPUMCTX, r15),
340 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
341 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
342 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
343 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
344 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
345 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
346 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
347 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
348 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
349 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
350 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
351 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
352 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
353 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
354 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
355 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
356 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
357 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
358 SSMFIELD_ENTRY( CPUMCTX, cr0),
359 SSMFIELD_ENTRY( CPUMCTX, cr2),
360 SSMFIELD_ENTRY( CPUMCTX, cr3),
361 SSMFIELD_ENTRY( CPUMCTX, cr4),
362 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
363 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
364 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
365 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
366 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
367 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
368 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
369 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
370 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
371 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
372 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
373 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
374 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
375 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
376 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
377 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
378 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
379 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
380 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
381 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
382 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
383 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
384 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
385 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
386 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
387 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
388 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
389 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
390 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
391 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
392 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
393 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
394 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
395 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
396 SSMFIELD_ENTRY_TERM()
397};
398
399/** Saved state field descriptors for CPUMCTX_VER1_6. */
400static const SSMFIELD g_aCpumCtxFieldsV16[] =
401{
402 SSMFIELD_ENTRY( CPUMCTX, fpu.FCW),
403 SSMFIELD_ENTRY( CPUMCTX, fpu.FSW),
404 SSMFIELD_ENTRY( CPUMCTX, fpu.FTW),
405 SSMFIELD_ENTRY( CPUMCTX, fpu.FOP),
406 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUIP),
407 SSMFIELD_ENTRY( CPUMCTX, fpu.CS),
408 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd1),
409 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUDP),
410 SSMFIELD_ENTRY( CPUMCTX, fpu.DS),
411 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd2),
412 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR),
413 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR_MASK),
414 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[0]),
415 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[1]),
416 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[2]),
417 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[3]),
418 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[4]),
419 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[5]),
420 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[6]),
421 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[7]),
422 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[0]),
423 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[1]),
424 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[2]),
425 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[3]),
426 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[4]),
427 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[5]),
428 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[6]),
429 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[7]),
430 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[8]),
431 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[9]),
432 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[10]),
433 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[11]),
434 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[12]),
435 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[13]),
436 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[14]),
437 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[15]),
438 SSMFIELD_ENTRY_IGNORE( CPUMCTX, fpu.au32RsrvdRest),
439 SSMFIELD_ENTRY( CPUMCTX, rdi),
440 SSMFIELD_ENTRY( CPUMCTX, rsi),
441 SSMFIELD_ENTRY( CPUMCTX, rbp),
442 SSMFIELD_ENTRY( CPUMCTX, rax),
443 SSMFIELD_ENTRY( CPUMCTX, rbx),
444 SSMFIELD_ENTRY( CPUMCTX, rdx),
445 SSMFIELD_ENTRY( CPUMCTX, rcx),
446 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
447 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
448 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
449 SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /*rsp_notused*/),
450 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
451 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
452 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
453 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
454 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
455 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
456 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
457 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
458 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
459 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
460 SSMFIELD_ENTRY( CPUMCTX, rflags),
461 SSMFIELD_ENTRY( CPUMCTX, rip),
462 SSMFIELD_ENTRY( CPUMCTX, r8),
463 SSMFIELD_ENTRY( CPUMCTX, r9),
464 SSMFIELD_ENTRY( CPUMCTX, r10),
465 SSMFIELD_ENTRY( CPUMCTX, r11),
466 SSMFIELD_ENTRY( CPUMCTX, r12),
467 SSMFIELD_ENTRY( CPUMCTX, r13),
468 SSMFIELD_ENTRY( CPUMCTX, r14),
469 SSMFIELD_ENTRY( CPUMCTX, r15),
470 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
471 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
472 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
473 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
474 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
475 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
476 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
477 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
478 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
479 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
480 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
481 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
482 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
483 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
484 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
485 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
486 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
487 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
488 SSMFIELD_ENTRY( CPUMCTX, cr0),
489 SSMFIELD_ENTRY( CPUMCTX, cr2),
490 SSMFIELD_ENTRY( CPUMCTX, cr3),
491 SSMFIELD_ENTRY( CPUMCTX, cr4),
492 SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
493 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
494 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
495 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
496 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
497 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
498 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
499 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
500 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
501 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
502 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
503 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
504 SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
505 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
506 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
507 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
508 SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
509 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
510 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
511 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
512 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
513 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
514 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
515 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
516 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
517 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
518 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
519 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
520 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
521 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
522 SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
523 SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
524 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
525 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
526 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
527 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
528 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
529 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
530 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
531 SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
532 SSMFIELD_ENTRY_TERM()
533};
534
535
536/**
537 * Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs.
538 *
539 * AMD K7, K8 and newer AMD CPUs do not save/restore the x87 error
540 * pointers (last instruction pointer, last data pointer, last opcode)
541 * except when the ES bit (Exception Summary) in x87 FSW (FPU Status
542 * Word) is set. Thus if we don't clear these registers there is
543 * potential, local FPU leakage from a process using the FPU to
544 * another.
545 *
546 * See AMD Instruction Reference for FXSAVE, FXRSTOR.
547 *
548 * @param pVM Pointer to the VM.
549 */
550static void cpumR3CheckLeakyFpu(PVM pVM)
551{
552 uint32_t u32CpuVersion = ASMCpuId_EAX(1);
553 uint32_t const u32Family = u32CpuVersion >> 8;
554 if ( u32Family >= 6 /* K7 and higher */
555 && ASMIsAmdCpu())
556 {
557 uint32_t cExt = ASMCpuId_EAX(0x80000000);
558 if (ASMIsValidExtRange(cExt))
559 {
560 uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
561 if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
562 {
563 for (VMCPUID i = 0; i < pVM->cCpus; i++)
564 pVM->aCpus[i].cpum.s.fUseFlags |= CPUM_USE_FFXSR_LEAKY;
565 Log(("CPUMR3Init: host CPU has leaky fxsave/fxrstor behaviour\n"));
566 }
567 }
568 }
569}
570
571
572/**
573 * Initializes the CPUM.
574 *
575 * @returns VBox status code.
576 * @param pVM Pointer to the VM.
577 */
578VMMR3DECL(int) CPUMR3Init(PVM pVM)
579{
580 LogFlow(("CPUMR3Init\n"));
581
582 /*
583 * Assert alignment, sizes and tables.
584 */
585 AssertCompileMemberAlignment(VM, cpum.s, 32);
586 AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
587 AssertCompileSizeAlignment(CPUMCTX, 64);
588 AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
589 AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
590 AssertCompileMemberAlignment(VM, cpum, 64);
591 AssertCompileMemberAlignment(VM, aCpus, 64);
592 AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
593 AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
594#ifdef VBOX_STRICT
595 int rc2 = cpumR3MsrStrictInitChecks();
596 AssertRCReturn(rc2, rc2);
597#endif
598
599 /* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
600 pVM->cpum.s.offCPUMCPU0 = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
601 Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
602
603
604 /* Calculate the offset from CPUMCPU to CPUM. */
605 for (VMCPUID i = 0; i < pVM->cCpus; i++)
606 {
607 PVMCPU pVCpu = &pVM->aCpus[i];
608
609 pVCpu->cpum.s.offCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
610 Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
611 }
612
613 /*
614 * Check that the CPU supports the minimum features we require.
615 */
616 if (!ASMHasCpuId())
617 {
618 Log(("The CPU doesn't support CPUID!\n"));
619 return VERR_UNSUPPORTED_CPU;
620 }
621 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
622 ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
623
624 /* Setup the CR4 AND and OR masks used in the switcher */
625 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
626 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
627 {
628 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
629 /* No FXSAVE implies no SSE */
630 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
631 pVM->cpum.s.CR4.OrMask = 0;
632 }
633 else
634 {
635 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
636 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
637 }
638
639 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
640 {
641 Log(("The CPU doesn't support MMX!\n"));
642 return VERR_UNSUPPORTED_CPU;
643 }
644 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
645 {
646 Log(("The CPU doesn't support TSC!\n"));
647 return VERR_UNSUPPORTED_CPU;
648 }
649 /* Bogus on AMD? */
650 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
651 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
652
653 /*
654 * Gather info about the host CPU.
655 */
656 PCPUMCPUIDLEAF paLeaves;
657 uint32_t cLeaves;
658 int rc = CPUMR3CpuIdCollectLeaves(&paLeaves, &cLeaves);
659 AssertLogRelRCReturn(rc, rc);
660
661 rc = cpumR3CpuIdExplodeFeatures(paLeaves, cLeaves, &pVM->cpum.s.HostFeatures);
662 RTMemFree(paLeaves);
663 AssertLogRelRCReturn(rc, rc);
664 pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.enmCpuVendor;
665
666 /*
667 * Setup hypervisor startup values.
668 */
669
670 /*
671 * Register saved state data item.
672 */
673 rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
674 NULL, cpumR3LiveExec, NULL,
675 NULL, cpumR3SaveExec, NULL,
676 cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
677 if (RT_FAILURE(rc))
678 return rc;
679
680 /*
681 * Register info handlers and registers with the debugger facility.
682 */
683 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
684 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
685 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
686 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
687 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
688 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
689
690 rc = cpumR3DbgInit(pVM);
691 if (RT_FAILURE(rc))
692 return rc;
693
694 /*
695 * Check if we need to workaround partial/leaky FPU handling.
696 */
697 cpumR3CheckLeakyFpu(pVM);
698
699 /*
700 * Initialize the Guest CPUID state.
701 */
702 rc = cpumR3CpuIdInit(pVM);
703 if (RT_FAILURE(rc))
704 return rc;
705 CPUMR3Reset(pVM);
706 return VINF_SUCCESS;
707}
708
709
710/**
711 * Loads MSR range overrides.
712 *
713 * This must be called before the MSR ranges are moved from the normal heap to
714 * the hyper heap!
715 *
716 * @returns VBox status code (VMSetError called).
717 * @param pVM Pointer to the cross context VM structure
718 * @param pMsrNode The CFGM node with the MSR overrides.
719 */
720static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
721{
722 for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
723 {
724 /*
725 * Assemble a valid MSR range.
726 */
727 CPUMMSRRANGE MsrRange;
728 MsrRange.offCpumCpu = 0;
729 MsrRange.fReserved = 0;
730
731 int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
732 if (RT_FAILURE(rc))
733 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
734
735 rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
736 if (RT_FAILURE(rc))
737 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
738 MsrRange.szName, rc);
739
740 rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
741 if (RT_FAILURE(rc))
742 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
743 MsrRange.szName, rc);
744
745 char szType[32];
746 rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
747 if (RT_FAILURE(rc))
748 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
749 MsrRange.szName, rc);
750 if (!RTStrICmp(szType, "FixedValue"))
751 {
752 MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
753 MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
754
755 rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
756 if (RT_FAILURE(rc))
757 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
758 MsrRange.szName, rc);
759
760 rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
761 if (RT_FAILURE(rc))
762 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
763 MsrRange.szName, rc);
764
765 rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
766 if (RT_FAILURE(rc))
767 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
768 MsrRange.szName, rc);
769 }
770 else
771 return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
772 "Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
773
774 /*
775 * Insert the range into the table (replaces/splits/shrinks existing
776 * MSR ranges).
777 */
778 rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
779 &MsrRange);
780 if (RT_FAILURE(rc))
781 return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
782 }
783
784 return VINF_SUCCESS;
785}
786
787
788/**
789 * Loads CPUID leaf overrides.
790 *
791 * This must be called before the CPUID leaves are moved from the normal
792 * heap to the hyper heap!
793 *
794 * @returns VBox status code (VMSetError called).
795 * @param pVM Pointer to the cross context VM structure
796 * @param pParentNode The CFGM node with the CPUID leaves.
797 * @param pszLabel How to label the overrides we're loading.
798 */
799static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
800{
801 for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
802 {
803 /*
804 * Get the leaf and subleaf numbers.
805 */
806 char szName[128];
807 int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
808 if (RT_FAILURE(rc))
809 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
810
811 /* The leaf number is either specified directly or thru the node name. */
812 uint32_t uLeaf;
813 rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
814 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
815 {
816 rc = RTStrToUInt32Full(szName, 16, &uLeaf);
817 if (rc != VINF_SUCCESS)
818 return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
819 "Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
820 }
821 else if (RT_FAILURE(rc))
822 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
823 pszLabel, szName, rc);
824
825 uint32_t uSubLeaf;
826 rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
827 if (RT_FAILURE(rc))
828 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
829 pszLabel, szName, rc);
830
831 uint32_t fSubLeafMask;
832 rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
833 if (RT_FAILURE(rc))
834 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
835 pszLabel, szName, rc);
836
837 /*
838 * Look up the specified leaf, since the output register values
839 * defaults to any existing values. This allows overriding a single
840 * register, without needing to know the other values.
841 */
842 PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
843 uLeaf, uSubLeaf);
844 CPUMCPUIDLEAF Leaf;
845 if (pLeaf)
846 Leaf = *pLeaf;
847 else
848 RT_ZERO(Leaf);
849 Leaf.uLeaf = uLeaf;
850 Leaf.uSubLeaf = uSubLeaf;
851 Leaf.fSubLeafMask = fSubLeafMask;
852
853 rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
854 if (RT_FAILURE(rc))
855 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
856 pszLabel, szName, rc);
857 rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
858 if (RT_FAILURE(rc))
859 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
860 pszLabel, szName, rc);
861 rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
862 if (RT_FAILURE(rc))
863 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
864 pszLabel, szName, rc);
865 rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
866 if (RT_FAILURE(rc))
867 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
868 pszLabel, szName, rc);
869
870 /*
871 * Insert the leaf into the table (replaces existing ones).
872 */
873 rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
874 &Leaf);
875 if (RT_FAILURE(rc))
876 return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
877 }
878
879 return VINF_SUCCESS;
880}
881
882
883
884/**
885 * Fetches overrides for a CPUID leaf.
886 *
887 * @returns VBox status code.
888 * @param pLeaf The leaf to load the overrides into.
889 * @param pCfgNode The CFGM node containing the overrides
890 * (/CPUM/HostCPUID/ or /CPUM/CPUID/).
891 * @param iLeaf The CPUID leaf number.
892 */
893static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
894{
895 PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
896 if (pLeafNode)
897 {
898 uint32_t u32;
899 int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
900 if (RT_SUCCESS(rc))
901 pLeaf->eax = u32;
902 else
903 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
904
905 rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
906 if (RT_SUCCESS(rc))
907 pLeaf->ebx = u32;
908 else
909 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
910
911 rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
912 if (RT_SUCCESS(rc))
913 pLeaf->ecx = u32;
914 else
915 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
916
917 rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
918 if (RT_SUCCESS(rc))
919 pLeaf->edx = u32;
920 else
921 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
922
923 }
924 return VINF_SUCCESS;
925}
926
927
928/**
929 * Load the overrides for a set of CPUID leaves.
930 *
931 * @returns VBox status code.
932 * @param paLeaves The leaf array.
933 * @param cLeaves The number of leaves.
934 * @param uStart The start leaf number.
935 * @param pCfgNode The CFGM node containing the overrides
936 * (/CPUM/HostCPUID/ or /CPUM/CPUID/).
937 */
938static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
939{
940 for (uint32_t i = 0; i < cLeaves; i++)
941 {
942 int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
943 if (RT_FAILURE(rc))
944 return rc;
945 }
946
947 return VINF_SUCCESS;
948}
949
950/**
951 * Init a set of host CPUID leaves.
952 *
953 * @returns VBox status code.
954 * @param paLeaves The leaf array.
955 * @param cLeaves The number of leaves.
956 * @param uStart The start leaf number.
957 * @param pCfgNode The /CPUM/HostCPUID/ node.
958 */
959static int cpumR3CpuIdInitHostSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
960{
961 /* Using the ECX variant for all of them can't hurt... */
962 for (uint32_t i = 0; i < cLeaves; i++)
963 ASMCpuIdExSlow(uStart + i, 0, 0, 0, &paLeaves[i].eax, &paLeaves[i].ebx, &paLeaves[i].ecx, &paLeaves[i].edx);
964
965 /* Load CPUID leaf override; we currently don't care if the user
966 specifies features the host CPU doesn't support. */
967 return cpumR3CpuIdInitLoadOverrideSet(uStart, paLeaves, cLeaves, pCfgNode);
968}
969
970
971static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCPUM, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
972{
973 /*
974 * Install the CPUID information.
975 */
976 int rc = MMHyperDupMem(pVM, paLeaves, sizeof(paLeaves[0]) * cLeaves, 32,
977 MM_TAG_CPUM_CPUID, (void **)&pCPUM->GuestInfo.paCpuIdLeavesR3);
978
979 AssertLogRelRCReturn(rc, rc);
980
981
982 pCPUM->GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, pCPUM->GuestInfo.paCpuIdLeavesR3);
983 pCPUM->GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pCPUM->GuestInfo.paCpuIdLeavesR3);
984 Assert(MMHyperR0ToR3(pVM, pCPUM->GuestInfo.paCpuIdLeavesR0) == (void *)pCPUM->GuestInfo.paCpuIdLeavesR3);
985 Assert(MMHyperRCToR3(pVM, pCPUM->GuestInfo.paCpuIdLeavesRC) == (void *)pCPUM->GuestInfo.paCpuIdLeavesR3);
986
987 /*
988 * Explode the guest CPU features.
989 */
990 rc = cpumR3CpuIdExplodeFeatures(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, &pCPUM->GuestFeatures);
991 AssertLogRelRCReturn(rc, rc);
992
993 /*
994 * Adjust the scalable bus frequency according to the CPUID information
995 * we're now using.
996 */
997 if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
998 pCPUM->GuestInfo.uScalableBusFreq = pCPUM->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
999 ? UINT64_C(100000000) /* 100MHz */
1000 : UINT64_C(133333333); /* 133MHz */
1001
1002 /*
1003 * Populate the legacy arrays. Currently used for everything, later only
1004 * for patch manager.
1005 */
1006 struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
1007 {
1008 { pCPUM->aGuestCpuIdStd, RT_ELEMENTS(pCPUM->aGuestCpuIdStd), 0x00000000 },
1009 { pCPUM->aGuestCpuIdExt, RT_ELEMENTS(pCPUM->aGuestCpuIdExt), 0x80000000 },
1010 { pCPUM->aGuestCpuIdCentaur, RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), 0xc0000000 },
1011 };
1012 for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
1013 {
1014 uint32_t cLeft = aOldRanges[i].cCpuIds;
1015 uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
1016 PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
1017 while (cLeft-- > 0)
1018 {
1019 uLeaf--;
1020 pLegacyLeaf--;
1021
1022 PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, uLeaf,
1023 0 /* uSubLeaf */);
1024 if (pLeaf)
1025 {
1026 pLegacyLeaf->eax = pLeaf->uEax;
1027 pLegacyLeaf->ebx = pLeaf->uEbx;
1028 pLegacyLeaf->ecx = pLeaf->uEcx;
1029 pLegacyLeaf->edx = pLeaf->uEdx;
1030 }
1031 else
1032 *pLegacyLeaf = pCPUM->GuestInfo.DefCpuId;
1033 }
1034 }
1035
1036 pCPUM->GuestCpuIdDef = pCPUM->GuestInfo.DefCpuId;
1037
1038 return VINF_SUCCESS;
1039}
1040
1041
1042/**
1043 * Initializes the emulated CPU's cpuid information.
1044 *
1045 * @returns VBox status code.
1046 * @param pVM Pointer to the VM.
1047 */
1048static int cpumR3CpuIdInit(PVM pVM)
1049{
1050 PCPUM pCPUM = &pVM->cpum.s;
1051 PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
1052 int rc;
1053
1054#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
1055 if ( pCPUM->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
1056 { \
1057 LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
1058 (a_pLeafReg) &= ~(uint32_t)(fMask); \
1059 }
1060#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
1061 if ( pCPUM->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
1062 { \
1063 LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
1064 (a_pLeafReg) &= ~(uint32_t)(fBitMask); \
1065 }
1066
1067 /*
1068 * Read the configuration.
1069 */
1070 /** @cfgm{CPUM/SyntheticCpu, boolean, false}
1071 * Enables the Synthetic CPU. The Vendor ID and Processor Name are
1072 * completely overridden by VirtualBox custom strings. Some
1073 * CPUID information is withheld, like the cache info.
1074 *
1075 * This is obsoleted by PortableCpuIdLevel. */
1076 bool fSyntheticCpu;
1077 rc = CFGMR3QueryBoolDef(pCpumCfg, "SyntheticCpu", &fSyntheticCpu, false);
1078 AssertRCReturn(rc, rc);
1079
1080 /** @cfgm{CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
1081 * When non-zero CPUID features that could cause portability issues will be
1082 * stripped. The higher the value the more features gets stripped. Higher
1083 * values should only be used when older CPUs are involved since it may
1084 * harm performance and maybe also cause problems with specific guests. */
1085 rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pCPUM->u8PortableCpuIdLevel, fSyntheticCpu ? 1 : 0);
1086 AssertLogRelRCReturn(rc, rc);
1087
1088 /** @cfgm{CPUM/GuestCpuName, string}
1089 * The name of the CPU we're to emulate. The default is the host CPU.
1090 * Note! CPUs other than "host" one is currently unsupported. */
1091 char szCpuName[128];
1092 rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", szCpuName, sizeof(szCpuName), "host");
1093 AssertLogRelRCReturn(rc, rc);
1094
1095 /** @cfgm{/CPUM/CMPXCHG16B, boolean, false}
1096 * Expose CMPXCHG16B to the guest if supported by the host.
1097 */
1098 bool fCmpXchg16b;
1099 rc = CFGMR3QueryBoolDef(pCpumCfg, "CMPXCHG16B", &fCmpXchg16b, false);
1100 AssertLogRelRCReturn(rc, rc);
1101
1102 /** @cfgm{/CPUM/MONITOR, boolean, true}
1103 * Expose MONITOR/MWAIT instructions to the guest.
1104 */
1105 bool fMonitor;
1106 rc = CFGMR3QueryBoolDef(pCpumCfg, "MONITOR", &fMonitor, true);
1107 AssertLogRelRCReturn(rc, rc);
1108
1109 /** @cfgm{/CPUM/MWaitExtensions, boolean, false}
1110 * Expose MWAIT extended features to the guest. For now we expose just MWAIT
1111 * break on interrupt feature (bit 1).
1112 */
1113 bool fMWaitExtensions;
1114 rc = CFGMR3QueryBoolDef(pCpumCfg, "MWaitExtensions", &fMWaitExtensions, false);
1115 AssertLogRelRCReturn(rc, rc);
1116
1117 /** @cfgm{/CPUM/SSE4.1, boolean, true}
1118 * Expose SSE4.1 to the guest if available.
1119 */
1120 bool fSse41;
1121 rc = CFGMR3QueryBoolDef(pCpumCfg, "SSE4.1", &fSse41, true);
1122 AssertLogRelRCReturn(rc, rc);
1123
1124 /** @cfgm{/CPUM/SSE4.2, boolean, true}
1125 * Expose SSE4.2 to the guest if available.
1126 */
1127 bool fSse42;
1128 rc = CFGMR3QueryBoolDef(pCpumCfg, "SSE4.2", &fSse42, true);
1129 AssertLogRelRCReturn(rc, rc);
1130
1131 /** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
1132 * Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
1133 * bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
1134 * This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
1135 */
1136 bool fNt4LeafLimit;
1137 rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &fNt4LeafLimit, false);
1138 AssertLogRelRCReturn(rc, rc);
1139
1140 /** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
1141 * Restrict the reported CPU family+model+stepping of intel CPUs. This is
1142 * probably going to be a temporary hack, so don't depend on this.
1143 * The 1st byte of the value is the stepping, the 2nd byte value is the model
1144 * number and the 3rd byte value is the family, and the 4th value must be zero.
1145 */
1146 uint32_t uMaxIntelFamilyModelStep;
1147 rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &uMaxIntelFamilyModelStep, UINT32_MAX);
1148 AssertLogRelRCReturn(rc, rc);
1149
1150 /*
1151 * Get the guest CPU data from the database and/or the host.
1152 */
1153 rc = cpumR3DbGetCpuInfo(szCpuName, &pCPUM->GuestInfo);
1154 if (RT_FAILURE(rc))
1155 return rc == VERR_CPUM_DB_CPU_NOT_FOUND
1156 ? VMSetError(pVM, rc, RT_SRC_POS,
1157 "Info on guest CPU '%s' could not be found. Please, select a different CPU.", szCpuName)
1158 : rc;
1159
1160 /** @cfgm{CPUM/MSRs/[Name]/[First|Last|Type|Value|...],}
1161 * Overrides the guest MSRs.
1162 */
1163 rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
1164
1165 /** @cfgm{CPUM/HostCPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
1166 * Overrides the CPUID leaf values (from the host CPU usually) used for
1167 * calculating the guest CPUID leaves. This can be used to preserve the CPUID
1168 * values when moving a VM to a different machine. Another use is restricting
1169 * (or extending) the feature set exposed to the guest. */
1170 if (RT_SUCCESS(rc))
1171 rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
1172
1173 if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
1174 rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
1175 "Found unsupported configuration node '/CPUM/CPUID/'. "
1176 "Please use IMachine::setCPUIDLeaf() instead.");
1177
1178 /*
1179 * Pre-exploded the CPUID info.
1180 */
1181 if (RT_SUCCESS(rc))
1182 rc = cpumR3CpuIdExplodeFeatures(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, &pCPUM->GuestFeatures);
1183 if (RT_FAILURE(rc))
1184 {
1185 RTMemFree(pCPUM->GuestInfo.paCpuIdLeavesR3);
1186 pCPUM->GuestInfo.paCpuIdLeavesR3 = NULL;
1187 RTMemFree(pCPUM->GuestInfo.paMsrRangesR3);
1188 pCPUM->GuestInfo.paMsrRangesR3 = NULL;
1189 return rc;
1190 }
1191
1192
1193 /* ... split this function about here ... */
1194
1195
1196 /* Cpuid 1:
1197 * Only report features we can support.
1198 *
1199 * Note! When enabling new features the Synthetic CPU and Portable CPUID
1200 * options may require adjusting (i.e. stripping what was enabled).
1201 */
1202 PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves,
1203 1, 0); /* Note! Must refetch when used later. */
1204 AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
1205 pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
1206 | X86_CPUID_FEATURE_EDX_VME
1207 | X86_CPUID_FEATURE_EDX_DE
1208 | X86_CPUID_FEATURE_EDX_PSE
1209 | X86_CPUID_FEATURE_EDX_TSC
1210 | X86_CPUID_FEATURE_EDX_MSR
1211 //| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
1212 | X86_CPUID_FEATURE_EDX_MCE
1213 | X86_CPUID_FEATURE_EDX_CX8
1214 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
1215 /* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
1216 //| X86_CPUID_FEATURE_EDX_SEP
1217 | X86_CPUID_FEATURE_EDX_MTRR
1218 | X86_CPUID_FEATURE_EDX_PGE
1219 | X86_CPUID_FEATURE_EDX_MCA
1220 | X86_CPUID_FEATURE_EDX_CMOV
1221 | X86_CPUID_FEATURE_EDX_PAT
1222 | X86_CPUID_FEATURE_EDX_PSE36
1223 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
1224 | X86_CPUID_FEATURE_EDX_CLFSH
1225 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
1226 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
1227 | X86_CPUID_FEATURE_EDX_MMX
1228 | X86_CPUID_FEATURE_EDX_FXSR
1229 | X86_CPUID_FEATURE_EDX_SSE
1230 | X86_CPUID_FEATURE_EDX_SSE2
1231 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
1232 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
1233 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
1234 //| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
1235 | 0;
1236 pStdFeatureLeaf->uEcx &= 0
1237 | X86_CPUID_FEATURE_ECX_SSE3
1238 /* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
1239 | ((fMonitor && pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
1240 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
1241 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
1242 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
1243 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
1244 | X86_CPUID_FEATURE_ECX_SSSE3
1245 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
1246 | (fCmpXchg16b ? X86_CPUID_FEATURE_ECX_CX16 : 0)
1247 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
1248 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
1249 | (fSse41 ? X86_CPUID_FEATURE_ECX_SSE4_1 : 0)
1250 | (fSse42 ? X86_CPUID_FEATURE_ECX_SSE4_2 : 0)
1251 /* ECX Bit 21 - x2APIC support - not yet. */
1252 // | X86_CPUID_FEATURE_ECX_X2APIC
1253 /* ECX Bit 23 - POPCNT instruction. */
1254 //| X86_CPUID_FEATURE_ECX_POPCNT
1255 | 0;
1256 if (pCPUM->u8PortableCpuIdLevel > 0)
1257 {
1258 PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
1259 PORTABLE_DISABLE_FEATURE_BIT(1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
1260 PORTABLE_DISABLE_FEATURE_BIT(1, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
1261 PORTABLE_DISABLE_FEATURE_BIT(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1);
1262 PORTABLE_DISABLE_FEATURE_BIT(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2);
1263 PORTABLE_DISABLE_FEATURE_BIT(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16);
1264 PORTABLE_DISABLE_FEATURE_BIT(2, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
1265 PORTABLE_DISABLE_FEATURE_BIT(3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
1266 PORTABLE_DISABLE_FEATURE_BIT(3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
1267 PORTABLE_DISABLE_FEATURE_BIT(3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
1268
1269 Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP
1270 | X86_CPUID_FEATURE_EDX_PSN
1271 | X86_CPUID_FEATURE_EDX_DS
1272 | X86_CPUID_FEATURE_EDX_ACPI
1273 | X86_CPUID_FEATURE_EDX_SS
1274 | X86_CPUID_FEATURE_EDX_TM
1275 | X86_CPUID_FEATURE_EDX_PBE
1276 )));
1277 Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_PCLMUL
1278 | X86_CPUID_FEATURE_ECX_DTES64
1279 | X86_CPUID_FEATURE_ECX_CPLDS
1280 | X86_CPUID_FEATURE_ECX_VMX
1281 | X86_CPUID_FEATURE_ECX_SMX
1282 | X86_CPUID_FEATURE_ECX_EST
1283 | X86_CPUID_FEATURE_ECX_TM2
1284 | X86_CPUID_FEATURE_ECX_CNTXID
1285 | X86_CPUID_FEATURE_ECX_FMA
1286 | X86_CPUID_FEATURE_ECX_CX16
1287 | X86_CPUID_FEATURE_ECX_TPRUPDATE
1288 | X86_CPUID_FEATURE_ECX_PDCM
1289 | X86_CPUID_FEATURE_ECX_DCA
1290 | X86_CPUID_FEATURE_ECX_MOVBE
1291 | X86_CPUID_FEATURE_ECX_AES
1292 | X86_CPUID_FEATURE_ECX_POPCNT
1293 | X86_CPUID_FEATURE_ECX_XSAVE
1294 | X86_CPUID_FEATURE_ECX_OSXSAVE
1295 | X86_CPUID_FEATURE_ECX_AVX
1296 )));
1297 }
1298
1299 /* Cpuid 0x80000001:
1300 * Only report features we can support.
1301 *
1302 * Note! When enabling new features the Synthetic CPU and Portable CPUID
1303 * options may require adjusting (i.e. stripping what was enabled).
1304 *
1305 * ASSUMES that this is ALWAYS the AMD defined feature set if present.
1306 */
1307 PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves,
1308 UINT32_C(0x80000001), 0); /* Note! Must refetch when used later. */
1309 if (pExtFeatureLeaf)
1310 {
1311 pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
1312 | X86_CPUID_AMD_FEATURE_EDX_VME
1313 | X86_CPUID_AMD_FEATURE_EDX_DE
1314 | X86_CPUID_AMD_FEATURE_EDX_PSE
1315 | X86_CPUID_AMD_FEATURE_EDX_TSC
1316 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
1317 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
1318 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
1319 | X86_CPUID_AMD_FEATURE_EDX_CX8
1320 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
1321 /* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
1322 //| X86_CPUID_EXT_FEATURE_EDX_SEP
1323 | X86_CPUID_AMD_FEATURE_EDX_MTRR
1324 | X86_CPUID_AMD_FEATURE_EDX_PGE
1325 | X86_CPUID_AMD_FEATURE_EDX_MCA
1326 | X86_CPUID_AMD_FEATURE_EDX_CMOV
1327 | X86_CPUID_AMD_FEATURE_EDX_PAT
1328 | X86_CPUID_AMD_FEATURE_EDX_PSE36
1329 //| X86_CPUID_EXT_FEATURE_EDX_NX - not virtualized, requires PAE.
1330 //| X86_CPUID_AMD_FEATURE_EDX_AXMMX
1331 | X86_CPUID_AMD_FEATURE_EDX_MMX
1332 | X86_CPUID_AMD_FEATURE_EDX_FXSR
1333 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
1334 //| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
1335 | X86_CPUID_EXT_FEATURE_EDX_RDTSCP
1336 //| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
1337 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
1338 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
1339 | 0;
1340 pExtFeatureLeaf->uEcx &= 0
1341 //| X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
1342 //| X86_CPUID_AMD_FEATURE_ECX_CMPL
1343 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
1344 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
1345 /* Note: This could prevent teleporting from AMD to Intel CPUs! */
1346 | X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
1347 //| X86_CPUID_AMD_FEATURE_ECX_ABM
1348 //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
1349 //| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
1350 //| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
1351 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
1352 //| X86_CPUID_AMD_FEATURE_ECX_IBS
1353 //| X86_CPUID_AMD_FEATURE_ECX_SSE5
1354 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
1355 //| X86_CPUID_AMD_FEATURE_ECX_WDT
1356 | 0;
1357 if (pCPUM->u8PortableCpuIdLevel > 0)
1358 {
1359 PORTABLE_DISABLE_FEATURE_BIT(1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
1360 PORTABLE_DISABLE_FEATURE_BIT(1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1361 PORTABLE_DISABLE_FEATURE_BIT(1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1362 PORTABLE_DISABLE_FEATURE_BIT(1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1363 PORTABLE_DISABLE_FEATURE_BIT(1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1364 PORTABLE_DISABLE_FEATURE_BIT(2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1365 PORTABLE_DISABLE_FEATURE_BIT(3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
1366
1367 Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_CMPL
1368 | X86_CPUID_AMD_FEATURE_ECX_SVM
1369 | X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
1370 | X86_CPUID_AMD_FEATURE_ECX_CR8L
1371 | X86_CPUID_AMD_FEATURE_ECX_ABM
1372 | X86_CPUID_AMD_FEATURE_ECX_SSE4A
1373 | X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
1374 | X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
1375 | X86_CPUID_AMD_FEATURE_ECX_OSVW
1376 | X86_CPUID_AMD_FEATURE_ECX_IBS
1377 | X86_CPUID_AMD_FEATURE_ECX_SSE5
1378 | X86_CPUID_AMD_FEATURE_ECX_SKINIT
1379 | X86_CPUID_AMD_FEATURE_ECX_WDT
1380 | UINT32_C(0xffffc000)
1381 )));
1382 Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
1383 | X86_CPUID_EXT_FEATURE_EDX_SYSCALL
1384 | RT_BIT(18)
1385 | RT_BIT(19)
1386 | RT_BIT(21)
1387 | X86_CPUID_AMD_FEATURE_EDX_AXMMX
1388 | X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
1389 | RT_BIT(28)
1390 )));
1391 }
1392 }
1393
1394 /*
1395 * Hide HTT, multicode, SMP, whatever.
1396 * (APIC-ID := 0 and #LogCpus := 0)
1397 */
1398 pStdFeatureLeaf->uEbx &= 0x0000ffff;
1399#ifdef VBOX_WITH_MULTI_CORE
1400 if (pVM->cCpus > 1)
1401 {
1402 /* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU core times the number of CPU cores per processor */
1403 pStdFeatureLeaf->uEbx |= (pVM->cCpus << 16);
1404 pStdFeatureLeaf->uEdx |= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading *or* multi-core CPUs */
1405 }
1406#endif
1407
1408 /* Cpuid 2:
1409 * Intel: Cache and TLB information
1410 * AMD: Reserved
1411 * VIA: Reserved
1412 * Safe to expose; restrict the number of calls to 1 for the portable case.
1413 */
1414 PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, 2, 0);
1415 if ( pCPUM->u8PortableCpuIdLevel > 0
1416 && pCurLeaf
1417 && (pCurLeaf->uEax & 0xff) > 1)
1418 {
1419 LogRel(("PortableCpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
1420 pCurLeaf->uEax &= UINT32_C(0xfffffffe);
1421 }
1422
1423 /* Cpuid 3:
1424 * Intel: EAX, EBX - reserved (transmeta uses these)
1425 * ECX, EDX - Processor Serial Number if available, otherwise reserved
1426 * AMD: Reserved
1427 * VIA: Reserved
1428 * Safe to expose
1429 */
1430 pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, 3, 0);
1431 pStdFeatureLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, 1, 0);
1432 if ( !(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN)
1433 && pCurLeaf)
1434 {
1435 pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
1436 if (pCPUM->u8PortableCpuIdLevel > 0)
1437 pCurLeaf->uEax = pCurLeaf->uEbx = 0;
1438 }
1439
1440 /* Cpuid 4:
1441 * Intel: Deterministic Cache Parameters Leaf
1442 * Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
1443 * AMD: Reserved
1444 * VIA: Reserved
1445 * Safe to expose, except for EAX:
1446 * Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
1447 * Bits 31-26: Maximum number of processor cores in this physical package**
1448 * Note: These SMP values are constant regardless of ECX
1449 */
1450 CPUMCPUIDLEAF NewLeaf;
1451 pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, 4, 0);
1452 if (pCurLeaf)
1453 {
1454 NewLeaf.uLeaf = 4;
1455 NewLeaf.uSubLeaf = 0;
1456 NewLeaf.fSubLeafMask = 0;
1457 NewLeaf.uEax = 0;
1458 NewLeaf.uEbx = 0;
1459 NewLeaf.uEcx = 0;
1460 NewLeaf.uEdx = 0;
1461 NewLeaf.fFlags = 0;
1462#ifdef VBOX_WITH_MULTI_CORE
1463 if ( pVM->cCpus > 1
1464 && pCPUM->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
1465 {
1466 AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
1467 /* One logical processor with possibly multiple cores. */
1468 /* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
1469 NewLeaf.uEax |= ((pVM->cCpus - 1) << 26); /* 6 bits only -> 64 cores! */
1470 }
1471#endif
1472 rc = cpumR3CpuIdInsert(NULL /* pVM */, &pCPUM->GuestInfo.paCpuIdLeavesR3, &pCPUM->GuestInfo.cCpuIdLeaves, &NewLeaf);
1473 AssertLogRelRCReturn(rc, rc);
1474 }
1475
1476 /* Cpuid 5: Monitor/mwait Leaf
1477 * Intel: ECX, EDX - reserved
1478 * EAX, EBX - Smallest and largest monitor line size
1479 * AMD: EDX - reserved
1480 * EAX, EBX - Smallest and largest monitor line size
1481 * ECX - extensions (ignored for now)
1482 * VIA: Reserved
1483 * Safe to expose
1484 */
1485 pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, 5, 0);
1486 if (pCurLeaf)
1487 {
1488 pStdFeatureLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, 1, 0);
1489 if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
1490 pCurLeaf->uEax = pCurLeaf->uEbx = 0;
1491
1492 pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
1493 if (fMWaitExtensions)
1494 {
1495 pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
1496 /** @todo: for now we just expose host's MWAIT C-states, although conceptually
1497 it shall be part of our power management virtualization model */
1498#if 0
1499 /* MWAIT sub C-states */
1500 pCurLeaf->uEdx =
1501 (0 << 0) /* 0 in C0 */ |
1502 (2 << 4) /* 2 in C1 */ |
1503 (2 << 8) /* 2 in C2 */ |
1504 (2 << 12) /* 2 in C3 */ |
1505 (0 << 16) /* 0 in C4 */
1506 ;
1507#endif
1508 }
1509 else
1510 pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
1511 }
1512
1513 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
1514 * Safe to pass on to the guest.
1515 *
1516 * Intel: 0x800000005 reserved
1517 * 0x800000006 L2 cache information
1518 * AMD: 0x800000005 L1 cache information
1519 * 0x800000006 L2/L3 cache information
1520 * VIA: 0x800000005 TLB and L1 cache information
1521 * 0x800000006 L2 cache information
1522 */
1523
1524 /* Cpuid 0x800000007:
1525 * Intel: Reserved
1526 * AMD: EAX, EBX, ECX - reserved
1527 * EDX: Advanced Power Management Information
1528 * VIA: Reserved
1529 */
1530 pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, UINT32_C(0x80000007), 0);
1531 if (pCurLeaf)
1532 {
1533 Assert(pCPUM->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
1534
1535 pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
1536
1537 if (pCPUM->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
1538 {
1539 /* Only expose the TSC invariant capability bit to the guest. */
1540 pCurLeaf->uEdx &= 0
1541 //| X86_CPUID_AMD_ADVPOWER_EDX_TS
1542 //| X86_CPUID_AMD_ADVPOWER_EDX_FID
1543 //| X86_CPUID_AMD_ADVPOWER_EDX_VID
1544 //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
1545 //| X86_CPUID_AMD_ADVPOWER_EDX_TM
1546 //| X86_CPUID_AMD_ADVPOWER_EDX_STC
1547 //| X86_CPUID_AMD_ADVPOWER_EDX_MC
1548 //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
1549#if 0
1550 /*
1551 * We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer
1552 * Linux kernels blindly assume that the AMD performance counters work
1553 * if this is set for 64 bits guests. (Can't really find a CPUID feature
1554 * bit for them though.)
1555 */
1556 | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
1557#endif
1558 | 0;
1559 }
1560 else
1561 pCurLeaf->uEdx = 0;
1562 }
1563
1564 /* Cpuid 0x800000008:
1565 * Intel: EAX: Virtual/Physical address Size
1566 * EBX, ECX, EDX - reserved
1567 * AMD: EBX, EDX - reserved
1568 * EAX: Virtual/Physical/Guest address Size
1569 * ECX: Number of cores + APICIdCoreIdSize
1570 * VIA: EAX: Virtual/Physical address Size
1571 * EBX, ECX, EDX - reserved
1572 */
1573 pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, UINT32_C(0x80000008), 0);
1574 if (pCurLeaf)
1575 {
1576 /* Only expose the virtual and physical address sizes to the guest. */
1577 pCurLeaf->uEax &= UINT32_C(0x0000ffff);
1578 pCurLeaf->uEbx = pCurLeaf->uEdx = 0; /* reserved */
1579 /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
1580 * NC (0-7) Number of cores; 0 equals 1 core */
1581 pCurLeaf->uEcx = 0;
1582#ifdef VBOX_WITH_MULTI_CORE
1583 if ( pVM->cCpus > 1
1584 && pCPUM->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
1585 {
1586 /* Legacy method to determine the number of cores. */
1587 pCurLeaf->uEcx |= (pVM->cCpus - 1); /* NC: Number of CPU cores - 1; 8 bits */
1588 pExtFeatureLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves,
1589 UINT32_C(0x80000001), 0);
1590 if (pExtFeatureLeaf)
1591 pExtFeatureLeaf->uEcx |= X86_CPUID_AMD_FEATURE_ECX_CMPL;
1592 }
1593#endif
1594 }
1595
1596
1597 /*
1598 * Limit it the number of entries, zapping the remainder.
1599 *
1600 * The limits are masking off stuff about power saving and similar, this
1601 * is perhaps a bit crudely done as there is probably some relatively harmless
1602 * info too in these leaves (like words about having a constant TSC).
1603 */
1604 pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, 0, 0);
1605 if (pCurLeaf)
1606 {
1607 if (pCurLeaf->uEax > 5)
1608 {
1609 pCurLeaf->uEax = 5;
1610 cpumR3CpuIdRemoveRange(pCPUM->GuestInfo.paCpuIdLeavesR3, &pCPUM->GuestInfo.cCpuIdLeaves,
1611 pCurLeaf->uEax + 1, UINT32_C(0x000fffff));
1612 }
1613
1614 /* NT4 hack, no zapping of extra leaves here. */
1615 if (fNt4LeafLimit && pCurLeaf->uEax > 3)
1616 pCurLeaf->uEax = 3;
1617 }
1618
1619 pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, UINT32_C(0x80000000), 0);
1620 if (pCurLeaf)
1621 {
1622 if (pCurLeaf->uEax > UINT32_C(0x80000008))
1623 {
1624 pCurLeaf->uEax = UINT32_C(0x80000008);
1625 cpumR3CpuIdRemoveRange(pCPUM->GuestInfo.paCpuIdLeavesR3, &pCPUM->GuestInfo.cCpuIdLeaves,
1626 pCurLeaf->uEax + 1, UINT32_C(0x800fffff));
1627 }
1628 }
1629
1630 /*
1631 * Centaur stuff (VIA).
1632 *
1633 * The important part here (we think) is to make sure the 0xc0000000
1634 * function returns 0xc0000001. As for the features, we don't currently
1635 * let on about any of those... 0xc0000002 seems to be some
1636 * temperature/hz/++ stuff, include it as well (static).
1637 */
1638 pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, UINT32_C(0xc0000000), 0);
1639 if (pCurLeaf)
1640 {
1641 if ( pCurLeaf->uEax >= UINT32_C(0xc0000000)
1642 && pCurLeaf->uEax <= UINT32_C(0xc0000004))
1643 {
1644 pCurLeaf->uEax = RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000002));
1645 cpumR3CpuIdRemoveRange(pCPUM->GuestInfo.paCpuIdLeavesR3, &pCPUM->GuestInfo.cCpuIdLeaves,
1646 UINT32_C(0xc0000002), UINT32_C(0xc00fffff));
1647
1648 pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves,
1649 UINT32_C(0xc0000001), 0);
1650 if (pCurLeaf)
1651 pCurLeaf->uEdx = 0; /* all features hidden */
1652 }
1653 else
1654 cpumR3CpuIdRemoveRange(pCPUM->GuestInfo.paCpuIdLeavesR3, &pCPUM->GuestInfo.cCpuIdLeaves,
1655 UINT32_C(0xc0000000), UINT32_C(0xc00fffff));
1656 }
1657
1658 /*
1659 * Hypervisor identification.
1660 *
1661 * We only return minimal information, primarily ensuring that the
1662 * 0x40000000 function returns 0x40000001 and identifying ourselves.
1663 * Currently we do not support any hypervisor-specific interface.
1664 */
1665 NewLeaf.uLeaf = UINT32_C(0x40000000);
1666 NewLeaf.uSubLeaf = 0;
1667 NewLeaf.fSubLeafMask = 0;
1668 NewLeaf.uEax = UINT32_C(0x40000001);
1669 NewLeaf.uEbx = 0x786f4256 /* 'VBox' */;
1670 NewLeaf.uEcx = 0x786f4256 /* 'VBox' */;
1671 NewLeaf.uEdx = 0x786f4256 /* 'VBox' */;
1672 NewLeaf.fFlags = 0;
1673 rc = cpumR3CpuIdInsert(NULL /* pVM */, &pCPUM->GuestInfo.paCpuIdLeavesR3, &pCPUM->GuestInfo.cCpuIdLeaves, &NewLeaf);
1674 AssertLogRelRCReturn(rc, rc);
1675
1676 NewLeaf.uLeaf = UINT32_C(0x40000001);
1677 NewLeaf.uEax = 0x656e6f6e; /* 'none' */
1678 NewLeaf.uEbx = 0;
1679 NewLeaf.uEcx = 0;
1680 NewLeaf.uEdx = 0;
1681 NewLeaf.fFlags = 0;
1682 rc = cpumR3CpuIdInsert(NULL /* pVM */, &pCPUM->GuestInfo.paCpuIdLeavesR3, &pCPUM->GuestInfo.cCpuIdLeaves, &NewLeaf);
1683 AssertLogRelRCReturn(rc, rc);
1684
1685 /*
1686 * Mini CPU selection support for making Mac OS X happy.
1687 */
1688 /** @todo This should probably be removed, as GIM Minimal provider does this
1689 * work. */
1690 if (pCPUM->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
1691 {
1692 pStdFeatureLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, 1, 0);
1693 uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pStdFeatureLeaf->uEax),
1694 ASMGetCpuModelIntel(pStdFeatureLeaf->uEax),
1695 ASMGetCpuFamily(pStdFeatureLeaf->uEax),
1696 0);
1697 if (uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
1698 {
1699 uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
1700 uNew |= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
1701 uNew |= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
1702 uNew |= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
1703 uNew |= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
1704 if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
1705 uNew |= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
1706 LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
1707 pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
1708 pStdFeatureLeaf->uEax = uNew;
1709 }
1710 }
1711
1712 /*
1713 * MSR fudging.
1714 */
1715 /** @cfgm{CPUM/FudgeMSRs, boolean, true}
1716 * Fudges some common MSRs if not present in the selected CPU database entry.
1717 * This is for trying to keep VMs running when moved between different hosts
1718 * and different CPU vendors. */
1719 bool fEnable;
1720 rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRCReturn(rc, rc);
1721 if (fEnable)
1722 {
1723 rc = cpumR3MsrApplyFudge(pVM);
1724 AssertLogRelRCReturn(rc, rc);
1725 }
1726
1727 /*
1728 * Move the MSR and CPUID arrays over on the hypervisor heap, and explode
1729 * guest CPU features again.
1730 */
1731 void *pvFree = pCPUM->GuestInfo.paCpuIdLeavesR3;
1732 int rc1 = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCPUM, pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves);
1733 RTMemFree(pvFree);
1734
1735 pvFree = pCPUM->GuestInfo.paMsrRangesR3;
1736 int rc2 = MMHyperDupMem(pVM, pvFree,
1737 sizeof(pCPUM->GuestInfo.paMsrRangesR3[0]) * pCPUM->GuestInfo.cMsrRanges, 32,
1738 MM_TAG_CPUM_MSRS, (void **)&pCPUM->GuestInfo.paMsrRangesR3);
1739 RTMemFree(pvFree);
1740 AssertLogRelRCReturn(rc1, rc1);
1741 AssertLogRelRCReturn(rc2, rc2);
1742
1743 pCPUM->GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, pCPUM->GuestInfo.paMsrRangesR3);
1744 pCPUM->GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pCPUM->GuestInfo.paMsrRangesR3);
1745 cpumR3MsrRegStats(pVM);
1746
1747 /*
1748 * Some more configuration that we're applying at the end of everything
1749 * via the CPUMSetGuestCpuIdFeature API.
1750 */
1751
1752 /* Check if PAE was explicitely enabled by the user. */
1753 rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false); AssertRCReturn(rc, rc);
1754 if (fEnable)
1755 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1756
1757 /* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
1758 rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false); AssertRCReturn(rc, rc);
1759 if (fEnable)
1760 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1761
1762 /* We don't enable the Hypervisor Present bit by default, but it may be needed by some guests. */
1763 rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableHVP", &fEnable, false); AssertRCReturn(rc, rc);
1764 if (fEnable)
1765 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_HVP);
1766
1767#undef PORTABLE_DISABLE_FEATURE_BIT
1768#undef PORTABLE_CLEAR_BITS_WHEN
1769
1770 return VINF_SUCCESS;
1771}
1772
1773
1774/**
1775 * Applies relocations to data and code managed by this
1776 * component. This function will be called at init and
1777 * whenever the VMM need to relocate it self inside the GC.
1778 *
1779 * The CPUM will update the addresses used by the switcher.
1780 *
1781 * @param pVM The VM.
1782 */
1783VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
1784{
1785 LogFlow(("CPUMR3Relocate\n"));
1786
1787 pVM->cpum.s.GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paMsrRangesR3);
1788 pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
1789
1790 /* Recheck the guest DRx values in raw-mode. */
1791 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1792 CPUMRecalcHyperDRx(&pVM->aCpus[iCpu], UINT8_MAX, false);
1793}
1794
1795
1796/**
1797 * Apply late CPUM property changes based on the fHWVirtEx setting
1798 *
1799 * @param pVM Pointer to the VM.
1800 * @param fHWVirtExEnabled HWVirtEx enabled/disabled
1801 */
1802VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled)
1803{
1804 /*
1805 * Workaround for missing cpuid(0) patches when leaf 4 returns GuestCpuIdDef:
1806 * If we miss to patch a cpuid(0).eax then Linux tries to determine the number
1807 * of processors from (cpuid(4).eax >> 26) + 1.
1808 *
1809 * Note: this code is obsolete, but let's keep it here for reference.
1810 * Purpose is valid when we artificially cap the max std id to less than 4.
1811 */
1812 if (!fHWVirtExEnabled)
1813 {
1814 Assert( pVM->cpum.s.aGuestCpuIdStd[4].eax == 0
1815 || pVM->cpum.s.aGuestCpuIdStd[0].eax < 0x4);
1816 pVM->cpum.s.aGuestCpuIdStd[4].eax = 0;
1817 }
1818}
1819
1820/**
1821 * Terminates the CPUM.
1822 *
1823 * Termination means cleaning up and freeing all resources,
1824 * the VM it self is at this point powered off or suspended.
1825 *
1826 * @returns VBox status code.
1827 * @param pVM Pointer to the VM.
1828 */
1829VMMR3DECL(int) CPUMR3Term(PVM pVM)
1830{
1831#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1832 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1833 {
1834 PVMCPU pVCpu = &pVM->aCpus[i];
1835 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1836
1837 memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
1838 pVCpu->cpum.s.uMagic = 0;
1839 pCtx->dr[5] = 0;
1840 }
1841#else
1842 NOREF(pVM);
1843#endif
1844 return VINF_SUCCESS;
1845}
1846
1847
1848/**
1849 * Resets a virtual CPU.
1850 *
1851 * Used by CPUMR3Reset and CPU hot plugging.
1852 *
1853 * @param pVM Pointer to the cross context VM structure.
1854 * @param pVCpu Pointer to the cross context virtual CPU structure of
1855 * the CPU that is being reset. This may differ from the
1856 * current EMT.
1857 */
1858VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
1859{
1860 /** @todo anything different for VCPU > 0? */
1861 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1862
1863 /*
1864 * Initialize everything to ZERO first.
1865 */
1866 uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
1867 memset(pCtx, 0, sizeof(*pCtx));
1868 pVCpu->cpum.s.fUseFlags = fUseFlags;
1869
1870 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
1871 pCtx->eip = 0x0000fff0;
1872 pCtx->edx = 0x00000600; /* P6 processor */
1873 pCtx->eflags.Bits.u1Reserved0 = 1;
1874
1875 pCtx->cs.Sel = 0xf000;
1876 pCtx->cs.ValidSel = 0xf000;
1877 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
1878 pCtx->cs.u64Base = UINT64_C(0xffff0000);
1879 pCtx->cs.u32Limit = 0x0000ffff;
1880 pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
1881 pCtx->cs.Attr.n.u1Present = 1;
1882 pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
1883
1884 pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
1885 pCtx->ds.u32Limit = 0x0000ffff;
1886 pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
1887 pCtx->ds.Attr.n.u1Present = 1;
1888 pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1889
1890 pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
1891 pCtx->es.u32Limit = 0x0000ffff;
1892 pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
1893 pCtx->es.Attr.n.u1Present = 1;
1894 pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1895
1896 pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
1897 pCtx->fs.u32Limit = 0x0000ffff;
1898 pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
1899 pCtx->fs.Attr.n.u1Present = 1;
1900 pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1901
1902 pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
1903 pCtx->gs.u32Limit = 0x0000ffff;
1904 pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
1905 pCtx->gs.Attr.n.u1Present = 1;
1906 pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1907
1908 pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
1909 pCtx->ss.u32Limit = 0x0000ffff;
1910 pCtx->ss.Attr.n.u1Present = 1;
1911 pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
1912 pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1913
1914 pCtx->idtr.cbIdt = 0xffff;
1915 pCtx->gdtr.cbGdt = 0xffff;
1916
1917 pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1918 pCtx->ldtr.u32Limit = 0xffff;
1919 pCtx->ldtr.Attr.n.u1Present = 1;
1920 pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
1921
1922 pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
1923 pCtx->tr.u32Limit = 0xffff;
1924 pCtx->tr.Attr.n.u1Present = 1;
1925 pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
1926
1927 pCtx->dr[6] = X86_DR6_INIT_VAL;
1928 pCtx->dr[7] = X86_DR7_INIT_VAL;
1929
1930 pCtx->fpu.FTW = 0x00; /* All empty (abbridged tag reg edition). */
1931 pCtx->fpu.FCW = 0x37f;
1932
1933 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
1934 IA-32 Processor States Following Power-up, Reset, or INIT */
1935 pCtx->fpu.MXCSR = 0x1F80;
1936 pCtx->fpu.MXCSR_MASK = 0xffff; /** @todo REM always changed this for us. Should probably check if the HW really
1937 supports all bits, since a zero value here should be read as 0xffbf. */
1938
1939 /*
1940 * MSRs.
1941 */
1942 /* Init PAT MSR */
1943 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
1944
1945 /* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
1946 * The Intel docs don't mention it. */
1947 Assert(!pCtx->msrEFER);
1948
1949 /* IA32_MISC_ENABLE - not entirely sure what the init/reset state really
1950 is supposed to be here, just trying provide useful/sensible values. */
1951 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
1952 if (pRange)
1953 {
1954 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
1955 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
1956 | (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
1957 | MSR_IA32_MISC_ENABLE_FAST_STRINGS;
1958 pRange->fWrIgnMask |= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
1959 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
1960 pRange->fWrGpMask &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
1961 }
1962
1963 /** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
1964
1965 /** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
1966 * called from each EMT while we're getting called by CPUMR3Reset()
1967 * iteratively on the same thread. Fix later. */
1968#if 0 /** @todo r=bird: This we will do in TM, not here. */
1969 /* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
1970 CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
1971#endif
1972
1973
1974 /* C-state control. Guesses. */
1975 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /*C1*/ | RT_BIT_32(25) | RT_BIT_32(26) | RT_BIT_32(27) | RT_BIT_32(28);
1976
1977
1978 /*
1979 * Get the APIC base MSR from the APIC device. For historical reasons (saved state), the APIC base
1980 * continues to reside in the APIC device and we cache it here in the VCPU for all further accesses.
1981 */
1982 PDMApicGetBase(pVCpu, &pCtx->msrApicBase);
1983}
1984
1985
1986/**
1987 * Resets the CPU.
1988 *
1989 * @returns VINF_SUCCESS.
1990 * @param pVM Pointer to the VM.
1991 */
1992VMMR3DECL(void) CPUMR3Reset(PVM pVM)
1993{
1994 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1995 {
1996 CPUMR3ResetCpu(pVM, &pVM->aCpus[i]);
1997
1998#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1999 PCPUMCTX pCtx = &pVM->aCpus[i].cpum.s.Guest;
2000
2001 /* Magic marker for searching in crash dumps. */
2002 strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
2003 pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
2004 pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
2005#endif
2006 }
2007}
2008
2009
2010/**
2011 * Called both in pass 0 and the final pass.
2012 *
2013 * @param pVM Pointer to the VM.
2014 * @param pSSM The saved state handle.
2015 */
2016static void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
2017{
2018 /*
2019 * Save all the CPU ID leaves here so we can check them for compatibility
2020 * upon loading.
2021 */
2022 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
2023 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
2024
2025 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
2026 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
2027
2028 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
2029 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
2030
2031 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
2032
2033 /*
2034 * Save a good portion of the raw CPU IDs as well as they may come in
2035 * handy when validating features for raw mode.
2036 */
2037 CPUMCPUID aRawStd[16];
2038 for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
2039 ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
2040 SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
2041 SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
2042
2043 CPUMCPUID aRawExt[32];
2044 for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
2045 ASMCpuIdExSlow(i | UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
2046 SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
2047 SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
2048}
2049
2050
2051static int cpumR3LoadCpuIdOneGuestArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves)
2052{
2053 uint32_t cCpuIds;
2054 int rc = SSMR3GetU32(pSSM, &cCpuIds);
2055 if (RT_SUCCESS(rc))
2056 {
2057 if (cCpuIds < 64)
2058 {
2059 for (uint32_t i = 0; i < cCpuIds; i++)
2060 {
2061 CPUMCPUID CpuId;
2062 rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
2063 if (RT_FAILURE(rc))
2064 break;
2065
2066 CPUMCPUIDLEAF NewLeaf;
2067 NewLeaf.uLeaf = uBase + i;
2068 NewLeaf.uSubLeaf = 0;
2069 NewLeaf.fSubLeafMask = 0;
2070 NewLeaf.uEax = CpuId.eax;
2071 NewLeaf.uEbx = CpuId.ebx;
2072 NewLeaf.uEcx = CpuId.ecx;
2073 NewLeaf.uEdx = CpuId.edx;
2074 NewLeaf.fFlags = 0;
2075 rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
2076 }
2077 }
2078 else
2079 rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2080 }
2081 if (RT_FAILURE(rc))
2082 {
2083 RTMemFree(*ppaLeaves);
2084 *ppaLeaves = NULL;
2085 *pcLeaves = 0;
2086 }
2087 return rc;
2088}
2089
2090
2091static int cpumR3LoadCpuIdGuestArrays(PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves)
2092{
2093 *ppaLeaves = NULL;
2094 *pcLeaves = 0;
2095
2096 int rc = cpumR3LoadCpuIdOneGuestArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
2097 if (RT_SUCCESS(rc))
2098 rc = cpumR3LoadCpuIdOneGuestArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
2099 if (RT_SUCCESS(rc))
2100 rc = cpumR3LoadCpuIdOneGuestArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
2101
2102 return rc;
2103}
2104
2105
2106/**
2107 * Loads the CPU ID leaves saved by pass 0.
2108 *
2109 * @returns VBox status code.
2110 * @param pVM Pointer to the VM.
2111 * @param pSSM The saved state handle.
2112 * @param uVersion The format version.
2113 */
2114static int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
2115{
2116 AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
2117
2118 /*
2119 * Define a bunch of macros for simplifying the code.
2120 */
2121 /* Generic expression + failure message. */
2122#define CPUID_CHECK_RET(expr, fmt) \
2123 do { \
2124 if (!(expr)) \
2125 { \
2126 char *pszMsg = RTStrAPrintf2 fmt; /* lack of variadic macros sucks */ \
2127 if (fStrictCpuIdChecks) \
2128 { \
2129 int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
2130 RTStrFree(pszMsg); \
2131 return rcCpuid; \
2132 } \
2133 LogRel(("CPUM: %s\n", pszMsg)); \
2134 RTStrFree(pszMsg); \
2135 } \
2136 } while (0)
2137#define CPUID_CHECK_WRN(expr, fmt) \
2138 do { \
2139 if (!(expr)) \
2140 LogRel(fmt); \
2141 } while (0)
2142
2143 /* For comparing two values and bitch if they differs. */
2144#define CPUID_CHECK2_RET(what, host, saved) \
2145 do { \
2146 if ((host) != (saved)) \
2147 { \
2148 if (fStrictCpuIdChecks) \
2149 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
2150 N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
2151 LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
2152 } \
2153 } while (0)
2154#define CPUID_CHECK2_WRN(what, host, saved) \
2155 do { \
2156 if ((host) != (saved)) \
2157 LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
2158 } while (0)
2159
2160 /* For checking raw cpu features (raw mode). */
2161#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
2162 do { \
2163 if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
2164 { \
2165 if (fStrictCpuIdChecks) \
2166 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
2167 N_(#bit " mismatch: host=%d saved=%d"), \
2168 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
2169 LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
2170 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
2171 } \
2172 } while (0)
2173#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
2174 do { \
2175 if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
2176 LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
2177 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
2178 } while (0)
2179#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
2180
2181 /* For checking guest features. */
2182#define CPUID_GST_FEATURE_RET(set, reg, bit) \
2183 do { \
2184 if ( (aGuestCpuId##set [1].reg & bit) \
2185 && !(aHostRaw##set [1].reg & bit) \
2186 && !(aHostOverride##set [1].reg & bit) \
2187 ) \
2188 { \
2189 if (fStrictCpuIdChecks) \
2190 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
2191 N_(#bit " is not supported by the host but has already exposed to the guest")); \
2192 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
2193 } \
2194 } while (0)
2195#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
2196 do { \
2197 if ( (aGuestCpuId##set [1].reg & bit) \
2198 && !(aHostRaw##set [1].reg & bit) \
2199 && !(aHostOverride##set [1].reg & bit) \
2200 ) \
2201 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
2202 } while (0)
2203#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
2204 do { \
2205 if ( (aGuestCpuId##set [1].reg & bit) \
2206 && !(aHostRaw##set [1].reg & bit) \
2207 && !(aHostOverride##set [1].reg & bit) \
2208 ) \
2209 LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
2210 } while (0)
2211#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
2212
2213 /* For checking guest features if AMD guest CPU. */
2214#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
2215 do { \
2216 if ( (aGuestCpuId##set [1].reg & bit) \
2217 && fGuestAmd \
2218 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
2219 && !(aHostOverride##set [1].reg & bit) \
2220 ) \
2221 { \
2222 if (fStrictCpuIdChecks) \
2223 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
2224 N_(#bit " is not supported by the host but has already exposed to the guest")); \
2225 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
2226 } \
2227 } while (0)
2228#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
2229 do { \
2230 if ( (aGuestCpuId##set [1].reg & bit) \
2231 && fGuestAmd \
2232 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
2233 && !(aHostOverride##set [1].reg & bit) \
2234 ) \
2235 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
2236 } while (0)
2237#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
2238 do { \
2239 if ( (aGuestCpuId##set [1].reg & bit) \
2240 && fGuestAmd \
2241 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
2242 && !(aHostOverride##set [1].reg & bit) \
2243 ) \
2244 LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
2245 } while (0)
2246#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
2247
2248 /* For checking AMD features which have a corresponding bit in the standard
2249 range. (Intel defines very few bits in the extended feature sets.) */
2250#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
2251 do { \
2252 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
2253 && !(fHostAmd \
2254 ? aHostRawExt[1].reg & (ExtBit) \
2255 : aHostRawStd[1].reg & (StdBit)) \
2256 && !(aHostOverrideExt[1].reg & (ExtBit)) \
2257 ) \
2258 { \
2259 if (fStrictCpuIdChecks) \
2260 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
2261 N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
2262 LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
2263 } \
2264 } while (0)
2265#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
2266 do { \
2267 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
2268 && !(fHostAmd \
2269 ? aHostRawExt[1].reg & (ExtBit) \
2270 : aHostRawStd[1].reg & (StdBit)) \
2271 && !(aHostOverrideExt[1].reg & (ExtBit)) \
2272 ) \
2273 LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
2274 } while (0)
2275#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
2276 do { \
2277 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
2278 && !(fHostAmd \
2279 ? aHostRawExt[1].reg & (ExtBit) \
2280 : aHostRawStd[1].reg & (StdBit)) \
2281 && !(aHostOverrideExt[1].reg & (ExtBit)) \
2282 ) \
2283 LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
2284 } while (0)
2285#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
2286
2287 /*
2288 * Load them into stack buffers first.
2289 */
2290 PCPUMCPUIDLEAF paLeaves;
2291 uint32_t cLeaves;
2292 int rc = cpumR3LoadCpuIdGuestArrays(pSSM, uVersion, &paLeaves, &cLeaves);
2293 AssertRCReturn(rc, rc);
2294
2295 /** @todo we'll be leaking paLeaves on error return... */
2296
2297 CPUMCPUID GuestCpuIdDef;
2298 rc = SSMR3GetMem(pSSM, &GuestCpuIdDef, sizeof(GuestCpuIdDef));
2299 AssertRCReturn(rc, rc);
2300
2301 CPUMCPUID aRawStd[16];
2302 uint32_t cRawStd;
2303 rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
2304 if (cRawStd > RT_ELEMENTS(aRawStd))
2305 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2306 rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
2307 AssertRCReturn(rc, rc);
2308 for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
2309 ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
2310
2311 CPUMCPUID aRawExt[32];
2312 uint32_t cRawExt;
2313 rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
2314 if (cRawExt > RT_ELEMENTS(aRawExt))
2315 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2316 rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
2317 AssertRCReturn(rc, rc);
2318 for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
2319 ASMCpuIdExSlow(i | UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
2320
2321 /*
2322 * Get the raw CPU IDs for the current host.
2323 */
2324 CPUMCPUID aHostRawStd[16];
2325 for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
2326 ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].eax, &aHostRawStd[i].ebx, &aHostRawStd[i].ecx, &aHostRawStd[i].edx);
2327
2328 CPUMCPUID aHostRawExt[32];
2329 for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
2330 ASMCpuIdExSlow(i | UINT32_C(0x80000000), 0, 0, 0,
2331 &aHostRawExt[i].eax, &aHostRawExt[i].ebx, &aHostRawExt[i].ecx, &aHostRawExt[i].edx);
2332
2333 /*
2334 * Get the host and guest overrides so we don't reject the state because
2335 * some feature was enabled thru these interfaces.
2336 * Note! We currently only need the feature leaves, so skip rest.
2337 */
2338 PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
2339 CPUMCPUID aHostOverrideStd[2];
2340 memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
2341 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
2342
2343 CPUMCPUID aHostOverrideExt[2];
2344 memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
2345 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
2346
2347 /*
2348 * This can be skipped.
2349 */
2350 bool fStrictCpuIdChecks;
2351 CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
2352
2353
2354
2355 /*
2356 * For raw-mode we'll require that the CPUs are very similar since we don't
2357 * intercept CPUID instructions for user mode applications.
2358 */
2359 if (!HMIsEnabled(pVM))
2360 {
2361 /* CPUID(0) */
2362 CPUID_CHECK_RET( aHostRawStd[0].ebx == aRawStd[0].ebx
2363 && aHostRawStd[0].ecx == aRawStd[0].ecx
2364 && aHostRawStd[0].edx == aRawStd[0].edx,
2365 (N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
2366 &aHostRawStd[0].ebx, &aHostRawStd[0].edx, &aHostRawStd[0].ecx,
2367 &aRawStd[0].ebx, &aRawStd[0].edx, &aRawStd[0].ecx));
2368 CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].eax, aRawStd[0].eax);
2369 CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3);
2370 CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
2371
2372 bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].ebx, aRawStd[0].ecx, aRawStd[0].edx);
2373
2374 /* CPUID(1).eax */
2375 CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].eax), ASMGetCpuFamily(aRawStd[1].eax));
2376 CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].eax, fIntel), ASMGetCpuModel(aRawStd[1].eax, fIntel));
2377 CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].eax >> 12) & 3, (aRawStd[1].eax >> 12) & 3 );
2378
2379 /* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
2380 CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].ebx & 0xff, aRawStd[1].ebx & 0xff);
2381 CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].ebx >> 8) & 0xff, (aRawStd[1].ebx >> 8) & 0xff);
2382
2383 /* CPUID(1).ecx */
2384 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3);
2385 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL);
2386 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64);
2387 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
2388 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS);
2389 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_VMX);
2390 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_SMX);
2391 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_EST);
2392 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TM2);
2393 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3);
2394 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID);
2395 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(11) /*reserved*/ );
2396 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA);
2397 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16);
2398 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
2399 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM);
2400 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(16) /*reserved*/);
2401 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(17) /*reserved*/);
2402 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DCA);
2403 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1);
2404 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2);
2405 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
2406 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE);
2407 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT);
2408 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(24) /*reserved*/);
2409 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES);
2410 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE);
2411 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE);
2412 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX);
2413 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(29) /*reserved*/);
2414 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(30) /*reserved*/);
2415 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_HVP);
2416
2417 /* CPUID(1).edx */
2418 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
2419 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
2420 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE);
2421 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
2422 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC);
2423 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR);
2424 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
2425 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
2426 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8);
2427 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
2428 CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(10) /*reserved*/);
2429 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
2430 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
2431 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
2432 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
2433 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV);
2434 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
2435 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
2436 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
2437 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH);
2438 CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(20) /*reserved*/);
2439 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_DS);
2440 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_ACPI);
2441 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX);
2442 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR);
2443 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE);
2444 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2);
2445 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SS);
2446 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_HTT);
2447 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_TM);
2448 CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(30) /*JMPE/IA64*/);
2449 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PBE);
2450
2451 /* CPUID(2) - config, mostly about caches. ignore. */
2452 /* CPUID(3) - processor serial number. ignore. */
2453 /* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
2454 /* CPUID(5) - mwait/monitor config. ignore. */
2455 /* CPUID(6) - power management. ignore. */
2456 /* CPUID(7) - ???. ignore. */
2457 /* CPUID(8) - ???. ignore. */
2458 /* CPUID(9) - DCA. ignore for now. */
2459 /* CPUID(a) - PeMo info. ignore for now. */
2460 /* CPUID(b) - topology info - takes ECX as input. ignore. */
2461
2462 /* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
2463 CPUID_CHECK_WRN( aRawStd[0].eax < UINT32_C(0x0000000d)
2464 || aHostRawStd[0].eax >= UINT32_C(0x0000000d),
2465 ("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
2466 if ( aRawStd[0].eax >= UINT32_C(0x0000000d)
2467 && aHostRawStd[0].eax >= UINT32_C(0x0000000d))
2468 {
2469 CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].eax, aRawStd[0xd].eax);
2470 CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].edx, aRawStd[0xd].edx);
2471 CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].ebx, aRawStd[0xd].ebx);
2472 CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].ecx, aRawStd[0xd].ecx);
2473 }
2474
2475 /* CPUID(0x80000000) - same as CPUID(0) except for eax.
2476 Note! Intel have/is marking many of the fields here as reserved. We
2477 will verify them as if it's an AMD CPU. */
2478 CPUID_CHECK_RET( (aHostRawExt[0].eax >= UINT32_C(0x80000001) && aHostRawExt[0].eax <= UINT32_C(0x8000007f))
2479 || !(aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f)),
2480 (N_("Extended leaves was present on saved state host, but is missing on the current\n")));
2481 if (aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f))
2482 {
2483 CPUID_CHECK_RET( aHostRawExt[0].ebx == aRawExt[0].ebx
2484 && aHostRawExt[0].ecx == aRawExt[0].ecx
2485 && aHostRawExt[0].edx == aRawExt[0].edx,
2486 (N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
2487 &aHostRawExt[0].ebx, &aHostRawExt[0].edx, &aHostRawExt[0].ecx,
2488 &aRawExt[0].ebx, &aRawExt[0].edx, &aRawExt[0].ecx));
2489 CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].eax, aRawExt[0].eax);
2490
2491 /* CPUID(0x80000001).eax - same as CPUID(0).eax. */
2492 CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].eax), ASMGetCpuFamily(aRawExt[1].eax));
2493 CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].eax, fIntel), ASMGetCpuModel(aRawExt[1].eax, fIntel));
2494 CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].eax >> 12) & 3, (aRawExt[1].eax >> 12) & 3 );
2495 CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3 );
2496 CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
2497
2498 /* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
2499 CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].ebx & 0xffff, aRawExt[1].ebx & 0xffff);
2500 CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].ebx >> 16) & 0xfff, (aRawExt[1].ebx >> 16) & 0xfff);
2501 CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].ebx >> 28) & 0xf, (aRawExt[1].ebx >> 28) & 0xf);
2502
2503 /* CPUID(0x80000001).ecx */
2504 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
2505 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
2506 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM);
2507 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
2508 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
2509 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM);
2510 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
2511 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
2512 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
2513 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
2514 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS);
2515 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5);
2516 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
2517 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT);
2518 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
2519 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
2520 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
2521 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
2522 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
2523 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
2524 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
2525 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
2526 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
2527 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
2528 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
2529 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
2530 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
2531 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
2532 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
2533 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
2534 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
2535 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
2536
2537 /* CPUID(0x80000001).edx */
2538 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FPU);
2539 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_VME);
2540 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_DE);
2541 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE);
2542 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_TSC);
2543 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MSR);
2544 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAE);
2545 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCE);
2546 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CX8);
2547 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_APIC);
2548 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(10) /*reserved*/);
2549 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_SEP);
2550 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
2551 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PGE);
2552 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCA);
2553 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
2554 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAT);
2555 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
2556 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(18) /*reserved*/);
2557 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(19) /*reserved*/);
2558 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_NX);
2559 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(21) /*reserved*/);
2560 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
2561 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MMX);
2562 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
2563 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2564 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
2565 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2566 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(28) /*reserved*/);
2567 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
2568 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2569 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2570
2571 /** @todo verify the rest as well. */
2572 }
2573 }
2574
2575
2576
2577 /*
2578 * Verify that we can support the features already exposed to the guest on
2579 * this host.
2580 *
2581 * Most of the features we're emulating requires intercepting instruction
2582 * and doing it the slow way, so there is no need to warn when they aren't
2583 * present in the host CPU. Thus we use IGN instead of EMU on these.
2584 *
2585 * Trailing comments:
2586 * "EMU" - Possible to emulate, could be lots of work and very slow.
2587 * "EMU?" - Can this be emulated?
2588 */
2589 CPUMCPUID aGuestCpuIdStd[2];
2590 RT_ZERO(aGuestCpuIdStd);
2591 cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
2592
2593 /* CPUID(1).ecx */
2594 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
2595 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
2596 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
2597 CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
2598 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
2599 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
2600 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
2601 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
2602 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
2603 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
2604 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
2605 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(11) /*reserved*/ );
2606 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
2607 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
2608 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
2609 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
2610 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(16) /*reserved*/);
2611 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(17) /*reserved*/);
2612 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
2613 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
2614 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
2615 CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
2616 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
2617 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
2618 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(24) /*reserved*/);
2619 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
2620 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
2621 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE); // -> EMU
2622 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
2623 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(29) /*reserved*/);
2624 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(30) /*reserved*/);
2625 CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
2626
2627 /* CPUID(1).edx */
2628 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
2629 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
2630 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
2631 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
2632 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
2633 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
2634 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
2635 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
2636 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
2637 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
2638 CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(10) /*reserved*/);
2639 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
2640 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
2641 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
2642 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
2643 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
2644 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
2645 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
2646 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
2647 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
2648 CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(20) /*reserved*/);
2649 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
2650 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
2651 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
2652 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
2653 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
2654 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
2655 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
2656 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
2657 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
2658 CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(30) /*JMPE/IA64*/); // -> EMU
2659 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
2660
2661 /* CPUID(0x80000000). */
2662 CPUMCPUID aGuestCpuIdExt[2];
2663 RT_ZERO(aGuestCpuIdExt);
2664 if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
2665 {
2666 /** @todo deal with no 0x80000001 on the host. */
2667 bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].ebx, aHostRawStd[0].ecx, aHostRawStd[0].edx);
2668 bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].ebx, aGuestCpuIdExt[0].ecx, aGuestCpuIdExt[0].edx);
2669
2670 /* CPUID(0x80000001).ecx */
2671 CPUID_GST_FEATURE_WRN(Ext, ecx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
2672 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
2673 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
2674 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
2675 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
2676 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
2677 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
2678 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
2679 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
2680 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
2681 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
2682 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5); // -> EMU
2683 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
2684 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
2685 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
2686 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
2687 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
2688 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
2689 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
2690 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
2691 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
2692 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
2693 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
2694 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
2695 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
2696 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
2697 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
2698 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
2699 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
2700 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
2701 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
2702 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
2703
2704 /* CPUID(0x80000001).edx */
2705 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
2706 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
2707 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
2708 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
2709 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
2710 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
2711 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
2712 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
2713 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
2714 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
2715 CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(10) /*reserved*/);
2716 CPUID_GST_FEATURE_IGN( Ext, edx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
2717 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
2718 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
2719 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
2720 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
2721 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
2722 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
2723 CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(18) /*reserved*/);
2724 CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(19) /*reserved*/);
2725 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_EXT_FEATURE_EDX_NX);
2726 CPUID_GST_FEATURE_WRN( Ext, edx, RT_BIT_32(21) /*reserved*/);
2727 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
2728 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
2729 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
2730 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2731 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
2732 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2733 CPUID_GST_FEATURE_IGN( Ext, edx, RT_BIT_32(28) /*reserved*/);
2734 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
2735 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2736 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2737 }
2738
2739 /*
2740 * We're good, commit the CPU ID leaves.
2741 */
2742 MMHyperFree(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
2743 pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
2744 pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
2745 pVM->cpum.s.GuestInfo.DefCpuId = GuestCpuIdDef;
2746 rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves);
2747 RTMemFree(paLeaves);
2748 AssertLogRelRCReturn(rc, rc);
2749
2750
2751#undef CPUID_CHECK_RET
2752#undef CPUID_CHECK_WRN
2753#undef CPUID_CHECK2_RET
2754#undef CPUID_CHECK2_WRN
2755#undef CPUID_RAW_FEATURE_RET
2756#undef CPUID_RAW_FEATURE_WRN
2757#undef CPUID_RAW_FEATURE_IGN
2758#undef CPUID_GST_FEATURE_RET
2759#undef CPUID_GST_FEATURE_WRN
2760#undef CPUID_GST_FEATURE_EMU
2761#undef CPUID_GST_FEATURE_IGN
2762#undef CPUID_GST_FEATURE2_RET
2763#undef CPUID_GST_FEATURE2_WRN
2764#undef CPUID_GST_FEATURE2_EMU
2765#undef CPUID_GST_FEATURE2_IGN
2766#undef CPUID_GST_AMD_FEATURE_RET
2767#undef CPUID_GST_AMD_FEATURE_WRN
2768#undef CPUID_GST_AMD_FEATURE_EMU
2769#undef CPUID_GST_AMD_FEATURE_IGN
2770
2771 return VINF_SUCCESS;
2772}
2773
2774
2775/**
2776 * Pass 0 live exec callback.
2777 *
2778 * @returns VINF_SSM_DONT_CALL_AGAIN.
2779 * @param pVM Pointer to the VM.
2780 * @param pSSM The saved state handle.
2781 * @param uPass The pass (0).
2782 */
2783static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2784{
2785 AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
2786 cpumR3SaveCpuId(pVM, pSSM);
2787 return VINF_SSM_DONT_CALL_AGAIN;
2788}
2789
2790
2791/**
2792 * Execute state save operation.
2793 *
2794 * @returns VBox status code.
2795 * @param pVM Pointer to the VM.
2796 * @param pSSM SSM operation handle.
2797 */
2798static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
2799{
2800 /*
2801 * Save.
2802 */
2803 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2804 {
2805 PVMCPU pVCpu = &pVM->aCpus[i];
2806 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
2807 }
2808
2809 SSMR3PutU32(pSSM, pVM->cCpus);
2810 SSMR3PutU32(pSSM, sizeof(pVM->aCpus[0].cpum.s.GuestMsrs.msr));
2811 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2812 {
2813 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2814
2815 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest), 0, g_aCpumCtxFields, NULL);
2816 SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
2817 SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
2818 AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
2819 SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
2820 }
2821
2822 cpumR3SaveCpuId(pVM, pSSM);
2823 return VINF_SUCCESS;
2824}
2825
2826
2827/**
2828 * @copydoc FNSSMINTLOADPREP
2829 */
2830static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2831{
2832 NOREF(pSSM);
2833 pVM->cpum.s.fPendingRestore = true;
2834 return VINF_SUCCESS;
2835}
2836
2837
2838/**
2839 * @copydoc FNSSMINTLOADEXEC
2840 */
2841static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2842{
2843 /*
2844 * Validate version.
2845 */
2846 if ( uVersion != CPUM_SAVED_STATE_VERSION
2847 && uVersion != CPUM_SAVED_STATE_VERSION_MEM
2848 && uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
2849 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
2850 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
2851 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
2852 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2853 && uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
2854 {
2855 AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
2856 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2857 }
2858
2859 if (uPass == SSM_PASS_FINAL)
2860 {
2861 /*
2862 * Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
2863 * really old SSM file versions.)
2864 */
2865 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2866 SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
2867 else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
2868 SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
2869
2870 uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
2871 PCSSMFIELD paCpumCtxFields = g_aCpumCtxFields;
2872 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2873 paCpumCtxFields = g_aCpumCtxFieldsV16;
2874 else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2875 paCpumCtxFields = g_aCpumCtxFieldsMem;
2876
2877 /*
2878 * Restore.
2879 */
2880 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2881 {
2882 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2883 uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
2884 uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
2885 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), fLoad, paCpumCtxFields, NULL);
2886 pVCpu->cpum.s.Hyper.cr3 = uCR3;
2887 pVCpu->cpum.s.Hyper.rsp = uRSP;
2888 }
2889
2890 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
2891 {
2892 uint32_t cCpus;
2893 int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2894 AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
2895 VERR_SSM_UNEXPECTED_DATA);
2896 }
2897 AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
2898 || pVM->cCpus == 1,
2899 ("cCpus=%u\n", pVM->cCpus),
2900 VERR_SSM_UNEXPECTED_DATA);
2901
2902 uint32_t cbMsrs = 0;
2903 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2904 {
2905 int rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
2906 AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
2907 VERR_SSM_UNEXPECTED_DATA);
2908 AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
2909 VERR_SSM_UNEXPECTED_DATA);
2910 }
2911
2912 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2913 {
2914 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2915 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest), fLoad,
2916 paCpumCtxFields, NULL);
2917 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fUseFlags);
2918 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
2919 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2920 SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
2921 else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
2922 {
2923 SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
2924 SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
2925 }
2926
2927 /* REM and other may have cleared must-be-one fields in DR6 and
2928 DR7, fix these. */
2929 pVCpu->cpum.s.Guest.dr[6] &= ~(X86_DR6_RAZ_MASK | X86_DR6_MBZ_MASK);
2930 pVCpu->cpum.s.Guest.dr[6] |= X86_DR6_RA1_MASK;
2931 pVCpu->cpum.s.Guest.dr[7] &= ~(X86_DR7_RAZ_MASK | X86_DR7_MBZ_MASK);
2932 pVCpu->cpum.s.Guest.dr[7] |= X86_DR7_RA1_MASK;
2933 }
2934
2935 /* Older states does not have the internal selector register flags
2936 and valid selector value. Supply those. */
2937 if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2938 {
2939 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2940 {
2941 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2942 bool const fValid = HMIsEnabled(pVM)
2943 || ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2944 && !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
2945 PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
2946 if (fValid)
2947 {
2948 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2949 {
2950 paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
2951 paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
2952 }
2953
2954 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2955 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2956 }
2957 else
2958 {
2959 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2960 {
2961 paSelReg[iSelReg].fFlags = 0;
2962 paSelReg[iSelReg].ValidSel = 0;
2963 }
2964
2965 /* This might not be 104% correct, but I think it's close
2966 enough for all practical purposes... (REM always loaded
2967 LDTR registers.) */
2968 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2969 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2970 }
2971 pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2972 pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
2973 }
2974 }
2975
2976 /* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
2977 if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2978 && uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2979 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2980 pVM->aCpus[iCpu].cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
2981
2982 /*
2983 * A quick sanity check.
2984 */
2985 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2986 {
2987 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2988 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2989 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2990 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2991 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2992 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2993 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2994 }
2995 }
2996
2997 pVM->cpum.s.fPendingRestore = false;
2998
2999 /*
3000 * Guest CPUIDs.
3001 */
3002 if (uVersion > CPUM_SAVED_STATE_VERSION_VER3_0)
3003 return cpumR3LoadCpuId(pVM, pSSM, uVersion);
3004
3005 /** @todo Merge the code below into cpumR3LoadCpuId when we've found out what is
3006 * actually required. */
3007
3008 /*
3009 * Restore the CPUID leaves.
3010 *
3011 * Note that we support restoring less than the current amount of standard
3012 * leaves because we've been allowed more is newer version of VBox.
3013 */
3014 uint32_t cElements;
3015 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
3016 if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
3017 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
3018 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
3019
3020 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
3021 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
3022 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
3023 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
3024
3025 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
3026 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
3027 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
3028 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
3029
3030 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
3031
3032 /*
3033 * Check that the basic cpuid id information is unchanged.
3034 */
3035 /** @todo we should check the 64 bits capabilities too! */
3036 uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
3037 ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
3038 ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
3039 uint32_t au32CpuIdSaved[8];
3040 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
3041 if (RT_SUCCESS(rc))
3042 {
3043 /* Ignore CPU stepping. */
3044 au32CpuId[4] &= 0xfffffff0;
3045 au32CpuIdSaved[4] &= 0xfffffff0;
3046
3047 /* Ignore APIC ID (AMD specs). */
3048 au32CpuId[5] &= ~0xff000000;
3049 au32CpuIdSaved[5] &= ~0xff000000;
3050
3051 /* Ignore the number of Logical CPUs (AMD specs). */
3052 au32CpuId[5] &= ~0x00ff0000;
3053 au32CpuIdSaved[5] &= ~0x00ff0000;
3054
3055 /* Ignore some advanced capability bits, that we don't expose to the guest. */
3056 au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
3057 | X86_CPUID_FEATURE_ECX_VMX
3058 | X86_CPUID_FEATURE_ECX_SMX
3059 | X86_CPUID_FEATURE_ECX_EST
3060 | X86_CPUID_FEATURE_ECX_TM2
3061 | X86_CPUID_FEATURE_ECX_CNTXID
3062 | X86_CPUID_FEATURE_ECX_TPRUPDATE
3063 | X86_CPUID_FEATURE_ECX_PDCM
3064 | X86_CPUID_FEATURE_ECX_DCA
3065 | X86_CPUID_FEATURE_ECX_X2APIC
3066 );
3067 au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
3068 | X86_CPUID_FEATURE_ECX_VMX
3069 | X86_CPUID_FEATURE_ECX_SMX
3070 | X86_CPUID_FEATURE_ECX_EST
3071 | X86_CPUID_FEATURE_ECX_TM2
3072 | X86_CPUID_FEATURE_ECX_CNTXID
3073 | X86_CPUID_FEATURE_ECX_TPRUPDATE
3074 | X86_CPUID_FEATURE_ECX_PDCM
3075 | X86_CPUID_FEATURE_ECX_DCA
3076 | X86_CPUID_FEATURE_ECX_X2APIC
3077 );
3078
3079 /* Make sure we don't forget to update the masks when enabling
3080 * features in the future.
3081 */
3082 AssertRelease(!(pVM->cpum.s.aGuestCpuIdStd[1].ecx &
3083 ( X86_CPUID_FEATURE_ECX_DTES64
3084 | X86_CPUID_FEATURE_ECX_VMX
3085 | X86_CPUID_FEATURE_ECX_SMX
3086 | X86_CPUID_FEATURE_ECX_EST
3087 | X86_CPUID_FEATURE_ECX_TM2
3088 | X86_CPUID_FEATURE_ECX_CNTXID
3089 | X86_CPUID_FEATURE_ECX_TPRUPDATE
3090 | X86_CPUID_FEATURE_ECX_PDCM
3091 | X86_CPUID_FEATURE_ECX_DCA
3092 | X86_CPUID_FEATURE_ECX_X2APIC
3093 )));
3094 /* do the compare */
3095 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
3096 {
3097 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
3098 LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
3099 "Saved=%.*Rhxs\n"
3100 "Real =%.*Rhxs\n",
3101 sizeof(au32CpuIdSaved), au32CpuIdSaved,
3102 sizeof(au32CpuId), au32CpuId));
3103 else
3104 {
3105 LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
3106 "Saved=%.*Rhxs\n"
3107 "Real =%.*Rhxs\n",
3108 sizeof(au32CpuIdSaved), au32CpuIdSaved,
3109 sizeof(au32CpuId), au32CpuId));
3110 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
3111 }
3112 }
3113 }
3114
3115 return rc;
3116}
3117
3118
3119/**
3120 * @copydoc FNSSMINTLOADPREP
3121 */
3122static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
3123{
3124 if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
3125 return VINF_SUCCESS;
3126
3127 /* just check this since we can. */ /** @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
3128 if (pVM->cpum.s.fPendingRestore)
3129 {
3130 LogRel(("CPUM: Missing state!\n"));
3131 return VERR_INTERNAL_ERROR_2;
3132 }
3133
3134 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
3135 {
3136 /* Notify PGM of the NXE states in case they've changed. */
3137 PGMNotifyNxeChanged(&pVM->aCpus[iCpu], !!(pVM->aCpus[iCpu].cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
3138
3139 /* Cache the local APIC base from the APIC device. During init. this is done in CPUMR3ResetCpu(). */
3140 PDMApicGetBase(&pVM->aCpus[iCpu], &pVM->aCpus[iCpu].cpum.s.Guest.msrApicBase);
3141 }
3142 return VINF_SUCCESS;
3143}
3144
3145
3146/**
3147 * Checks if the CPUM state restore is still pending.
3148 *
3149 * @returns true / false.
3150 * @param pVM Pointer to the VM.
3151 */
3152VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
3153{
3154 return pVM->cpum.s.fPendingRestore;
3155}
3156
3157
3158/**
3159 * Formats the EFLAGS value into mnemonics.
3160 *
3161 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
3162 * @param efl The EFLAGS value.
3163 */
3164static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
3165{
3166 /*
3167 * Format the flags.
3168 */
3169 static const struct
3170 {
3171 const char *pszSet; const char *pszClear; uint32_t fFlag;
3172 } s_aFlags[] =
3173 {
3174 { "vip",NULL, X86_EFL_VIP },
3175 { "vif",NULL, X86_EFL_VIF },
3176 { "ac", NULL, X86_EFL_AC },
3177 { "vm", NULL, X86_EFL_VM },
3178 { "rf", NULL, X86_EFL_RF },
3179 { "nt", NULL, X86_EFL_NT },
3180 { "ov", "nv", X86_EFL_OF },
3181 { "dn", "up", X86_EFL_DF },
3182 { "ei", "di", X86_EFL_IF },
3183 { "tf", NULL, X86_EFL_TF },
3184 { "nt", "pl", X86_EFL_SF },
3185 { "nz", "zr", X86_EFL_ZF },
3186 { "ac", "na", X86_EFL_AF },
3187 { "po", "pe", X86_EFL_PF },
3188 { "cy", "nc", X86_EFL_CF },
3189 };
3190 char *psz = pszEFlags;
3191 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
3192 {
3193 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
3194 if (pszAdd)
3195 {
3196 strcpy(psz, pszAdd);
3197 psz += strlen(pszAdd);
3198 *psz++ = ' ';
3199 }
3200 }
3201 psz[-1] = '\0';
3202}
3203
3204
3205/**
3206 * Formats a full register dump.
3207 *
3208 * @param pVM Pointer to the VM.
3209 * @param pCtx The context to format.
3210 * @param pCtxCore The context core to format.
3211 * @param pHlp Output functions.
3212 * @param enmType The dump type.
3213 * @param pszPrefix Register name prefix.
3214 */
3215static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
3216 const char *pszPrefix)
3217{
3218 NOREF(pVM);
3219
3220 /*
3221 * Format the EFLAGS.
3222 */
3223 uint32_t efl = pCtxCore->eflags.u32;
3224 char szEFlags[80];
3225 cpumR3InfoFormatFlags(&szEFlags[0], efl);
3226
3227 /*
3228 * Format the registers.
3229 */
3230 switch (enmType)
3231 {
3232 case CPUMDUMPTYPE_TERSE:
3233 if (CPUMIsGuestIn64BitCodeEx(pCtx))
3234 pHlp->pfnPrintf(pHlp,
3235 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3236 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3237 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3238 "%sr14=%016RX64 %sr15=%016RX64\n"
3239 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3240 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
3241 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3242 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3243 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3244 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3245 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3246 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
3247 else
3248 pHlp->pfnPrintf(pHlp,
3249 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3250 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3251 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
3252 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3253 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3254 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3255 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
3256 break;
3257
3258 case CPUMDUMPTYPE_DEFAULT:
3259 if (CPUMIsGuestIn64BitCodeEx(pCtx))
3260 pHlp->pfnPrintf(pHlp,
3261 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3262 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3263 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3264 "%sr14=%016RX64 %sr15=%016RX64\n"
3265 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3266 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
3267 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
3268 ,
3269 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3270 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3271 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3272 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3273 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3274 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
3275 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3276 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
3277 else
3278 pHlp->pfnPrintf(pHlp,
3279 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3280 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3281 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
3282 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
3283 ,
3284 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3285 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3286 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3287 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
3288 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3289 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
3290 break;
3291
3292 case CPUMDUMPTYPE_VERBOSE:
3293 if (CPUMIsGuestIn64BitCodeEx(pCtx))
3294 pHlp->pfnPrintf(pHlp,
3295 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3296 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3297 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3298 "%sr14=%016RX64 %sr15=%016RX64\n"
3299 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3300 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3301 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3302 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3303 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3304 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3305 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3306 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
3307 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
3308 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
3309 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
3310 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3311 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3312 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
3313 ,
3314 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3315 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3316 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3317 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3318 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
3319 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
3320 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
3321 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
3322 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
3323 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
3324 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3325 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
3326 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
3327 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
3328 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
3329 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
3330 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3331 else
3332 pHlp->pfnPrintf(pHlp,
3333 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3334 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3335 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
3336 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
3337 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
3338 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
3339 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
3340 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
3341 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
3342 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3343 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3344 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
3345 ,
3346 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3347 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3348 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
3349 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
3350 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
3351 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
3352 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
3353 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3354 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
3355 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
3356 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
3357 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3358
3359 pHlp->pfnPrintf(pHlp,
3360 "%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
3361 "%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
3362 ,
3363 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW, pszPrefix, pCtx->fpu.FOP,
3364 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK,
3365 pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsrvd1,
3366 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2
3367 );
3368 unsigned iShift = (pCtx->fpu.FSW >> 11) & 7;
3369 for (unsigned iST = 0; iST < RT_ELEMENTS(pCtx->fpu.aRegs); iST++)
3370 {
3371 unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pCtx->fpu.aRegs);
3372 unsigned uTag = pCtx->fpu.FTW & (1 << iFPR) ? 1 : 0;
3373 char chSign = pCtx->fpu.aRegs[0].au16[4] & 0x8000 ? '-' : '+';
3374 unsigned iInteger = (unsigned)(pCtx->fpu.aRegs[0].au64[0] >> 63);
3375 uint64_t u64Fraction = pCtx->fpu.aRegs[0].au64[0] & UINT64_C(0x7fffffffffffffff);
3376 unsigned uExponent = pCtx->fpu.aRegs[0].au16[4] & 0x7fff;
3377 /** @todo This isn't entirenly correct and needs more work! */
3378 pHlp->pfnPrintf(pHlp,
3379 "%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu ^ %u",
3380 pszPrefix, iST, pszPrefix, iFPR,
3381 pCtx->fpu.aRegs[0].au16[4], pCtx->fpu.aRegs[0].au32[1], pCtx->fpu.aRegs[0].au32[0],
3382 uTag, chSign, iInteger, u64Fraction, uExponent);
3383 if (pCtx->fpu.aRegs[0].au16[5] || pCtx->fpu.aRegs[0].au16[6] || pCtx->fpu.aRegs[0].au16[7])
3384 pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
3385 pCtx->fpu.aRegs[0].au16[5], pCtx->fpu.aRegs[0].au16[6], pCtx->fpu.aRegs[0].au16[7]);
3386 else
3387 pHlp->pfnPrintf(pHlp, "\n");
3388 }
3389 for (unsigned iXMM = 0; iXMM < RT_ELEMENTS(pCtx->fpu.aXMM); iXMM++)
3390 pHlp->pfnPrintf(pHlp,
3391 iXMM & 1
3392 ? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
3393 : "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
3394 pszPrefix, iXMM, iXMM < 10 ? " " : "",
3395 pCtx->fpu.aXMM[iXMM].au32[3],
3396 pCtx->fpu.aXMM[iXMM].au32[2],
3397 pCtx->fpu.aXMM[iXMM].au32[1],
3398 pCtx->fpu.aXMM[iXMM].au32[0]);
3399 for (unsigned i = 0; i < RT_ELEMENTS(pCtx->fpu.au32RsrvdRest); i++)
3400 if (pCtx->fpu.au32RsrvdRest[i])
3401 pHlp->pfnPrintf(pHlp, "%sRsrvdRest[i]=%RX32 (offset=%#x)\n",
3402 pszPrefix, i, pCtx->fpu.au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
3403
3404 pHlp->pfnPrintf(pHlp,
3405 "%sEFER =%016RX64\n"
3406 "%sPAT =%016RX64\n"
3407 "%sSTAR =%016RX64\n"
3408 "%sCSTAR =%016RX64\n"
3409 "%sLSTAR =%016RX64\n"
3410 "%sSFMASK =%016RX64\n"
3411 "%sKERNELGSBASE =%016RX64\n",
3412 pszPrefix, pCtx->msrEFER,
3413 pszPrefix, pCtx->msrPAT,
3414 pszPrefix, pCtx->msrSTAR,
3415 pszPrefix, pCtx->msrCSTAR,
3416 pszPrefix, pCtx->msrLSTAR,
3417 pszPrefix, pCtx->msrSFMASK,
3418 pszPrefix, pCtx->msrKERNELGSBASE);
3419 break;
3420 }
3421}
3422
3423
3424/**
3425 * Display all cpu states and any other cpum info.
3426 *
3427 * @param pVM Pointer to the VM.
3428 * @param pHlp The info helper functions.
3429 * @param pszArgs Arguments, ignored.
3430 */
3431static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3432{
3433 cpumR3InfoGuest(pVM, pHlp, pszArgs);
3434 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
3435 cpumR3InfoHyper(pVM, pHlp, pszArgs);
3436 cpumR3InfoHost(pVM, pHlp, pszArgs);
3437}
3438
3439
3440/**
3441 * Parses the info argument.
3442 *
3443 * The argument starts with 'verbose', 'terse' or 'default' and then
3444 * continues with the comment string.
3445 *
3446 * @param pszArgs The pointer to the argument string.
3447 * @param penmType Where to store the dump type request.
3448 * @param ppszComment Where to store the pointer to the comment string.
3449 */
3450static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
3451{
3452 if (!pszArgs)
3453 {
3454 *penmType = CPUMDUMPTYPE_DEFAULT;
3455 *ppszComment = "";
3456 }
3457 else
3458 {
3459 if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
3460 {
3461 pszArgs += 7;
3462 *penmType = CPUMDUMPTYPE_VERBOSE;
3463 }
3464 else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
3465 {
3466 pszArgs += 5;
3467 *penmType = CPUMDUMPTYPE_TERSE;
3468 }
3469 else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
3470 {
3471 pszArgs += 7;
3472 *penmType = CPUMDUMPTYPE_DEFAULT;
3473 }
3474 else
3475 *penmType = CPUMDUMPTYPE_DEFAULT;
3476 *ppszComment = RTStrStripL(pszArgs);
3477 }
3478}
3479
3480
3481/**
3482 * Display the guest cpu state.
3483 *
3484 * @param pVM Pointer to the VM.
3485 * @param pHlp The info helper functions.
3486 * @param pszArgs Arguments, ignored.
3487 */
3488static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3489{
3490 CPUMDUMPTYPE enmType;
3491 const char *pszComment;
3492 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3493
3494 /* @todo SMP support! */
3495 PVMCPU pVCpu = VMMGetCpu(pVM);
3496 if (!pVCpu)
3497 pVCpu = &pVM->aCpus[0];
3498
3499 pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
3500
3501 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3502 cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
3503}
3504
3505
3506/**
3507 * Display the current guest instruction
3508 *
3509 * @param pVM Pointer to the VM.
3510 * @param pHlp The info helper functions.
3511 * @param pszArgs Arguments, ignored.
3512 */
3513static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3514{
3515 NOREF(pszArgs);
3516
3517 /** @todo SMP support! */
3518 PVMCPU pVCpu = VMMGetCpu(pVM);
3519 if (!pVCpu)
3520 pVCpu = &pVM->aCpus[0];
3521
3522 char szInstruction[256];
3523 szInstruction[0] = '\0';
3524 DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
3525 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
3526}
3527
3528
3529/**
3530 * Display the hypervisor cpu state.
3531 *
3532 * @param pVM Pointer to the VM.
3533 * @param pHlp The info helper functions.
3534 * @param pszArgs Arguments, ignored.
3535 */
3536static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3537{
3538 CPUMDUMPTYPE enmType;
3539 const char *pszComment;
3540 /* @todo SMP */
3541 PVMCPU pVCpu = &pVM->aCpus[0];
3542
3543 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3544 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
3545 cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper), pHlp, enmType, ".");
3546 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
3547}
3548
3549
3550/**
3551 * Display the host cpu state.
3552 *
3553 * @param pVM Pointer to the VM.
3554 * @param pHlp The info helper functions.
3555 * @param pszArgs Arguments, ignored.
3556 */
3557static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3558{
3559 CPUMDUMPTYPE enmType;
3560 const char *pszComment;
3561 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3562 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
3563
3564 /*
3565 * Format the EFLAGS.
3566 */
3567 /* @todo SMP */
3568 PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
3569#if HC_ARCH_BITS == 32
3570 uint32_t efl = pCtx->eflags.u32;
3571#else
3572 uint64_t efl = pCtx->rflags;
3573#endif
3574 char szEFlags[80];
3575 cpumR3InfoFormatFlags(&szEFlags[0], efl);
3576
3577 /*
3578 * Format the registers.
3579 */
3580#if HC_ARCH_BITS == 32
3581# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
3582 if (!(pCtx->efer & MSR_K6_EFER_LMA))
3583# endif
3584 {
3585 pHlp->pfnPrintf(pHlp,
3586 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
3587 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
3588 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
3589 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
3590 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
3591 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
3592 ,
3593 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
3594 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
3595 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
3596 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
3597 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
3598 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->ldtr,
3599 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3600 }
3601# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
3602 else
3603# endif
3604#endif
3605#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
3606 {
3607 pHlp->pfnPrintf(pHlp,
3608 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
3609 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
3610 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
3611 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
3612 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
3613 "r14=%016RX64 r15=%016RX64\n"
3614 "iopl=%d %31s\n"
3615 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
3616 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
3617 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
3618 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
3619 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
3620 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
3621 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
3622 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
3623 ,
3624 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
3625 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
3626 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
3627 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
3628 pCtx->r11, pCtx->r12, pCtx->r13,
3629 pCtx->r14, pCtx->r15,
3630 X86_EFL_GET_IOPL(efl), szEFlags,
3631 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
3632 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
3633 pCtx->cr4, pCtx->ldtr, pCtx->tr,
3634 pCtx->dr0, pCtx->dr1, pCtx->dr2,
3635 pCtx->dr3, pCtx->dr6, pCtx->dr7,
3636 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
3637 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
3638 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
3639 }
3640#endif
3641}
3642
3643
3644/**
3645 * Get L1 cache / TLS associativity.
3646 */
3647static const char *getCacheAss(unsigned u, char *pszBuf)
3648{
3649 if (u == 0)
3650 return "res0 ";
3651 if (u == 1)
3652 return "direct";
3653 if (u == 255)
3654 return "fully";
3655 if (u >= 256)
3656 return "???";
3657
3658 RTStrPrintf(pszBuf, 16, "%d way", u);
3659 return pszBuf;
3660}
3661
3662
3663/**
3664 * Get L2 cache associativity.
3665 */
3666const char *getL2CacheAss(unsigned u)
3667{
3668 switch (u)
3669 {
3670 case 0: return "off ";
3671 case 1: return "direct";
3672 case 2: return "2 way ";
3673 case 3: return "res3 ";
3674 case 4: return "4 way ";
3675 case 5: return "res5 ";
3676 case 6: return "8 way ";
3677 case 7: return "res7 ";
3678 case 8: return "16 way";
3679 case 9: return "res9 ";
3680 case 10: return "res10 ";
3681 case 11: return "res11 ";
3682 case 12: return "res12 ";
3683 case 13: return "res13 ";
3684 case 14: return "res14 ";
3685 case 15: return "fully ";
3686 default: return "????";
3687 }
3688}
3689
3690
3691/**
3692 * Display the guest CpuId leaves.
3693 *
3694 * @param pVM Pointer to the VM.
3695 * @param pHlp The info helper functions.
3696 * @param pszArgs "terse", "default" or "verbose".
3697 */
3698static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3699{
3700 /*
3701 * Parse the argument.
3702 */
3703 unsigned iVerbosity = 1;
3704 if (pszArgs)
3705 {
3706 pszArgs = RTStrStripL(pszArgs);
3707 if (!strcmp(pszArgs, "terse"))
3708 iVerbosity--;
3709 else if (!strcmp(pszArgs, "verbose"))
3710 iVerbosity++;
3711 }
3712
3713 /*
3714 * Start cracking.
3715 */
3716 CPUMCPUID Host;
3717 CPUMCPUID Guest;
3718 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
3719
3720 uint32_t cStdHstMax;
3721 uint32_t dummy;
3722 ASMCpuIdExSlow(0, 0, 0, 0, &cStdHstMax, &dummy, &dummy, &dummy);
3723
3724 unsigned cStdLstMax = RT_MAX(RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd), cStdHstMax);
3725
3726 pHlp->pfnPrintf(pHlp,
3727 " RAW Standard CPUIDs\n"
3728 " Function eax ebx ecx edx\n");
3729 for (unsigned i = 0; i <= cStdLstMax ; i++)
3730 {
3731 if (i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
3732 {
3733 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
3734 ASMCpuIdExSlow(i, 0, 0, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3735
3736 pHlp->pfnPrintf(pHlp,
3737 "Gst: %08x %08x %08x %08x %08x%s\n"
3738 "Hst: %08x %08x %08x %08x\n",
3739 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3740 i <= cStdMax ? "" : "*",
3741 Host.eax, Host.ebx, Host.ecx, Host.edx);
3742 }
3743 else
3744 {
3745 ASMCpuIdExSlow(i, 0, 0, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3746
3747 pHlp->pfnPrintf(pHlp,
3748 "Hst: %08x %08x %08x %08x %08x\n",
3749 i, Host.eax, Host.ebx, Host.ecx, Host.edx);
3750 }
3751 }
3752
3753 /*
3754 * If verbose, decode it.
3755 */
3756 if (iVerbosity)
3757 {
3758 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
3759 pHlp->pfnPrintf(pHlp,
3760 "Name: %.04s%.04s%.04s\n"
3761 "Supports: 0-%x\n",
3762 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
3763 }
3764
3765 /*
3766 * Get Features.
3767 */
3768 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
3769 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
3770 pVM->cpum.s.aGuestCpuIdStd[0].edx);
3771 if (cStdMax >= 1 && iVerbosity)
3772 {
3773 static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
3774
3775 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
3776 uint32_t uEAX = Guest.eax;
3777
3778 pHlp->pfnPrintf(pHlp,
3779 "Family: %d \tExtended: %d \tEffective: %d\n"
3780 "Model: %d \tExtended: %d \tEffective: %d\n"
3781 "Stepping: %d\n"
3782 "Type: %d (%s)\n"
3783 "APIC ID: %#04x\n"
3784 "Logical CPUs: %d\n"
3785 "CLFLUSH Size: %d\n"
3786 "Brand ID: %#04x\n",
3787 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
3788 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
3789 ASMGetCpuStepping(uEAX),
3790 (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
3791 (Guest.ebx >> 24) & 0xff,
3792 (Guest.ebx >> 16) & 0xff,
3793 (Guest.ebx >> 8) & 0xff,
3794 (Guest.ebx >> 0) & 0xff);
3795 if (iVerbosity == 1)
3796 {
3797 uint32_t uEDX = Guest.edx;
3798 pHlp->pfnPrintf(pHlp, "Features EDX: ");
3799 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
3800 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
3801 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
3802 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
3803 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
3804 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
3805 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
3806 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
3807 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
3808 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
3809 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
3810 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
3811 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
3812 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
3813 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
3814 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
3815 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
3816 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
3817 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
3818 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
3819 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
3820 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
3821 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
3822 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
3823 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
3824 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
3825 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
3826 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
3827 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
3828 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
3829 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
3830 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
3831 pHlp->pfnPrintf(pHlp, "\n");
3832
3833 uint32_t uECX = Guest.ecx;
3834 pHlp->pfnPrintf(pHlp, "Features ECX: ");
3835 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
3836 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " PCLMUL");
3837 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DTES64");
3838 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
3839 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
3840 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
3841 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SMX");
3842 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
3843 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
3844 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " SSSE3");
3845 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
3846 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
3847 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " FMA");
3848 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
3849 if (uECX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " TPRUPDATE");
3850 if (uECX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " PDCM");
3851 if (uECX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " 16");
3852 if (uECX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PCID");
3853 if (uECX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " DCA");
3854 if (uECX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " SSE4.1");
3855 if (uECX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " SSE4.2");
3856 if (uECX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " X2APIC");
3857 if (uECX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " MOVBE");
3858 if (uECX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " POPCNT");
3859 if (uECX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " TSCDEADL");
3860 if (uECX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " AES");
3861 if (uECX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " XSAVE");
3862 if (uECX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " OSXSAVE");
3863 if (uECX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " AVX");
3864 if (uECX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " F16C");
3865 if (uECX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " RDRAND");
3866 if (uECX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " HVP");
3867 pHlp->pfnPrintf(pHlp, "\n");
3868 }
3869 else
3870 {
3871 ASMCpuIdExSlow(1, 0, 0, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3872
3873 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
3874 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
3875 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
3876 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
3877
3878 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3879 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
3880 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
3881 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
3882 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
3883 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
3884 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
3885 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
3886 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
3887 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
3888 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
3889 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
3890 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
3891 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
3892 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
3893 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
3894 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
3895 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
3896 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
3897 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
3898 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
3899 pHlp->pfnPrintf(pHlp, "20 - Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
3900 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
3901 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
3902 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
3903 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
3904 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
3905 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
3906 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
3907 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technology = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
3908 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
3909 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
3910 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
3911
3912 pHlp->pfnPrintf(pHlp, "Supports SSE3 = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
3913 pHlp->pfnPrintf(pHlp, "PCLMULQDQ = %d (%d)\n", EcxGuest.u1PCLMULQDQ, EcxHost.u1PCLMULQDQ);
3914 pHlp->pfnPrintf(pHlp, "DS Area 64-bit layout = %d (%d)\n", EcxGuest.u1DTE64, EcxHost.u1DTE64);
3915 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
3916 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
3917 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
3918 pHlp->pfnPrintf(pHlp, "SMX - Safer Mode Extensions = %d (%d)\n", EcxGuest.u1SMX, EcxHost.u1SMX);
3919 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
3920 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
3921 pHlp->pfnPrintf(pHlp, "Supplemental SSE3 instructions = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
3922 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
3923 pHlp->pfnPrintf(pHlp, "11 - Reserved = %d (%d)\n", EcxGuest.u1Reserved1, EcxHost.u1Reserved1);
3924 pHlp->pfnPrintf(pHlp, "FMA extensions using YMM state = %d (%d)\n", EcxGuest.u1FMA, EcxHost.u1FMA);
3925 pHlp->pfnPrintf(pHlp, "CMPXCHG16B instruction = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
3926 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
3927 pHlp->pfnPrintf(pHlp, "Perf/Debug Capability MSR = %d (%d)\n", EcxGuest.u1PDCM, EcxHost.u1PDCM);
3928 pHlp->pfnPrintf(pHlp, "16 - Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
3929 pHlp->pfnPrintf(pHlp, "PCID - Process-context identifiers = %d (%d)\n", EcxGuest.u1PCID, EcxHost.u1PCID);
3930 pHlp->pfnPrintf(pHlp, "DCA - Direct Cache Access = %d (%d)\n", EcxGuest.u1DCA, EcxHost.u1DCA);
3931 pHlp->pfnPrintf(pHlp, "SSE4.1 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_1, EcxHost.u1SSE4_1);
3932 pHlp->pfnPrintf(pHlp, "SSE4.2 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_2, EcxHost.u1SSE4_2);
3933 pHlp->pfnPrintf(pHlp, "Supports the x2APIC extensions = %d (%d)\n", EcxGuest.u1x2APIC, EcxHost.u1x2APIC);
3934 pHlp->pfnPrintf(pHlp, "MOVBE instruction = %d (%d)\n", EcxGuest.u1MOVBE, EcxHost.u1MOVBE);
3935 pHlp->pfnPrintf(pHlp, "POPCNT instruction = %d (%d)\n", EcxGuest.u1POPCNT, EcxHost.u1POPCNT);
3936 pHlp->pfnPrintf(pHlp, "TSC-Deadline LAPIC timer mode = %d (%d)\n", EcxGuest.u1TSCDEADLINE,EcxHost.u1TSCDEADLINE);
3937 pHlp->pfnPrintf(pHlp, "AESNI instruction extensions = %d (%d)\n", EcxGuest.u1AES, EcxHost.u1AES);
3938 pHlp->pfnPrintf(pHlp, "XSAVE/XRSTOR extended state feature = %d (%d)\n", EcxGuest.u1XSAVE, EcxHost.u1XSAVE);
3939 pHlp->pfnPrintf(pHlp, "Supports OSXSAVE = %d (%d)\n", EcxGuest.u1OSXSAVE, EcxHost.u1OSXSAVE);
3940 pHlp->pfnPrintf(pHlp, "AVX instruction extensions = %d (%d)\n", EcxGuest.u1AVX, EcxHost.u1AVX);
3941 pHlp->pfnPrintf(pHlp, "16-bit floating point conversion instr = %d (%d)\n", EcxGuest.u1F16C, EcxHost.u1F16C);
3942 pHlp->pfnPrintf(pHlp, "RDRAND instruction = %d (%d)\n", EcxGuest.u1RDRAND, EcxHost.u1RDRAND);
3943 pHlp->pfnPrintf(pHlp, "Hypervisor Present (we're a guest) = %d (%d)\n", EcxGuest.u1HVP, EcxHost.u1HVP);
3944 }
3945 }
3946 if (cStdMax >= 2 && iVerbosity)
3947 {
3948 /** @todo */
3949 }
3950
3951 /*
3952 * Extended.
3953 * Implemented after AMD specs.
3954 */
3955 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
3956
3957 pHlp->pfnPrintf(pHlp,
3958 "\n"
3959 " RAW Extended CPUIDs\n"
3960 " Function eax ebx ecx edx\n");
3961 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
3962 {
3963 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
3964 ASMCpuIdExSlow(0x80000000 | i, 0, 0, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3965
3966 pHlp->pfnPrintf(pHlp,
3967 "Gst: %08x %08x %08x %08x %08x%s\n"
3968 "Hst: %08x %08x %08x %08x\n",
3969 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3970 i <= cExtMax ? "" : "*",
3971 Host.eax, Host.ebx, Host.ecx, Host.edx);
3972 }
3973
3974 /*
3975 * Understandable output
3976 */
3977 if (iVerbosity)
3978 {
3979 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
3980 pHlp->pfnPrintf(pHlp,
3981 "Ext Name: %.4s%.4s%.4s\n"
3982 "Ext Supports: 0x80000000-%#010x\n",
3983 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
3984 }
3985
3986 if (iVerbosity && cExtMax >= 1)
3987 {
3988 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
3989 uint32_t uEAX = Guest.eax;
3990 pHlp->pfnPrintf(pHlp,
3991 "Family: %d \tExtended: %d \tEffective: %d\n"
3992 "Model: %d \tExtended: %d \tEffective: %d\n"
3993 "Stepping: %d\n"
3994 "Brand ID: %#05x\n",
3995 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
3996 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
3997 ASMGetCpuStepping(uEAX),
3998 Guest.ebx & 0xfff);
3999
4000 if (iVerbosity == 1)
4001 {
4002 uint32_t uEDX = Guest.edx;
4003 pHlp->pfnPrintf(pHlp, "Features EDX: ");
4004 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
4005 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
4006 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
4007 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
4008 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
4009 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
4010 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
4011 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
4012 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
4013 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
4014 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
4015 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
4016 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
4017 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
4018 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
4019 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
4020 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
4021 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
4022 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
4023 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
4024 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
4025 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
4026 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
4027 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
4028 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
4029 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
4030 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
4031 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
4032 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
4033 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
4034 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
4035 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
4036 pHlp->pfnPrintf(pHlp, "\n");
4037
4038 uint32_t uECX = Guest.ecx;
4039 pHlp->pfnPrintf(pHlp, "Features ECX: ");
4040 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
4041 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
4042 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
4043 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
4044 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
4045 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
4046 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
4047 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
4048 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
4049 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
4050 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
4051 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
4052 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
4053 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
4054 for (unsigned iBit = 5; iBit < 32; iBit++)
4055 if (uECX & RT_BIT(iBit))
4056 pHlp->pfnPrintf(pHlp, " %d", iBit);
4057 pHlp->pfnPrintf(pHlp, "\n");
4058 }
4059 else
4060 {
4061 ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
4062
4063 uint32_t uEdxGst = Guest.edx;
4064 uint32_t uEdxHst = Host.edx;
4065 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
4066 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
4067 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
4068 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
4069 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
4070 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
4071 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
4072 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
4073 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
4074 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
4075 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
4076 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
4077 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
4078 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
4079 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
4080 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
4081 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
4082 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
4083 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
4084 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
4085 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
4086 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
4087 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
4088 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
4089 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
4090 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
4091 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
4092 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
4093 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
4094 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
4095 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
4096 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow! = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
4097 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow! = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
4098
4099 uint32_t uEcxGst = Guest.ecx;
4100 uint32_t uEcxHst = Host.ecx;
4101 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
4102 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
4103 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
4104 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
4105 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
4106 pHlp->pfnPrintf(pHlp, "5 - Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
4107 pHlp->pfnPrintf(pHlp, "6 - SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
4108 pHlp->pfnPrintf(pHlp, "7 - Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
4109 pHlp->pfnPrintf(pHlp, "8 - PREFETCH and PREFETCHW instruction= %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
4110 pHlp->pfnPrintf(pHlp, "9 - OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
4111 pHlp->pfnPrintf(pHlp, "10 - Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
4112 pHlp->pfnPrintf(pHlp, "11 - SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
4113 pHlp->pfnPrintf(pHlp, "12 - SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
4114 pHlp->pfnPrintf(pHlp, "13 - Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
4115 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
4116 }
4117 }
4118
4119 if (iVerbosity && cExtMax >= 2)
4120 {
4121 char szString[4*4*3+1] = {0};
4122 uint32_t *pu32 = (uint32_t *)szString;
4123 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
4124 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
4125 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
4126 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
4127 if (cExtMax >= 3)
4128 {
4129 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
4130 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
4131 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
4132 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
4133 }
4134 if (cExtMax >= 4)
4135 {
4136 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
4137 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
4138 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
4139 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
4140 }
4141 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
4142 }
4143
4144 if (iVerbosity && cExtMax >= 5)
4145 {
4146 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
4147 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
4148 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
4149 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
4150 char sz1[32];
4151 char sz2[32];
4152
4153 pHlp->pfnPrintf(pHlp,
4154 "TLB 2/4M Instr/Uni: %s %3d entries\n"
4155 "TLB 2/4M Data: %s %3d entries\n",
4156 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
4157 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
4158 pHlp->pfnPrintf(pHlp,
4159 "TLB 4K Instr/Uni: %s %3d entries\n"
4160 "TLB 4K Data: %s %3d entries\n",
4161 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
4162 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
4163 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
4164 "L1 Instr Cache Lines Per Tag: %d\n"
4165 "L1 Instr Cache Associativity: %s\n"
4166 "L1 Instr Cache Size: %d KB\n",
4167 (uEDX >> 0) & 0xff,
4168 (uEDX >> 8) & 0xff,
4169 getCacheAss((uEDX >> 16) & 0xff, sz1),
4170 (uEDX >> 24) & 0xff);
4171 pHlp->pfnPrintf(pHlp,
4172 "L1 Data Cache Line Size: %d bytes\n"
4173 "L1 Data Cache Lines Per Tag: %d\n"
4174 "L1 Data Cache Associativity: %s\n"
4175 "L1 Data Cache Size: %d KB\n",
4176 (uECX >> 0) & 0xff,
4177 (uECX >> 8) & 0xff,
4178 getCacheAss((uECX >> 16) & 0xff, sz1),
4179 (uECX >> 24) & 0xff);
4180 }
4181
4182 if (iVerbosity && cExtMax >= 6)
4183 {
4184 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
4185 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
4186 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
4187
4188 pHlp->pfnPrintf(pHlp,
4189 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
4190 "L2 TLB 2/4M Data: %s %4d entries\n",
4191 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
4192 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
4193 pHlp->pfnPrintf(pHlp,
4194 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
4195 "L2 TLB 4K Data: %s %4d entries\n",
4196 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
4197 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
4198 pHlp->pfnPrintf(pHlp,
4199 "L2 Cache Line Size: %d bytes\n"
4200 "L2 Cache Lines Per Tag: %d\n"
4201 "L2 Cache Associativity: %s\n"
4202 "L2 Cache Size: %d KB\n",
4203 (uEDX >> 0) & 0xff,
4204 (uEDX >> 8) & 0xf,
4205 getL2CacheAss((uEDX >> 12) & 0xf),
4206 (uEDX >> 16) & 0xffff);
4207 }
4208
4209 if (iVerbosity && cExtMax >= 7)
4210 {
4211 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
4212
4213 pHlp->pfnPrintf(pHlp, "APM Features: ");
4214 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
4215 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
4216 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
4217 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
4218 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
4219 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
4220 for (unsigned iBit = 6; iBit < 32; iBit++)
4221 if (uEDX & RT_BIT(iBit))
4222 pHlp->pfnPrintf(pHlp, " %d", iBit);
4223 pHlp->pfnPrintf(pHlp, "\n");
4224 }
4225
4226 if (iVerbosity && cExtMax >= 8)
4227 {
4228 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
4229 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
4230
4231 pHlp->pfnPrintf(pHlp,
4232 "Physical Address Width: %d bits\n"
4233 "Virtual Address Width: %d bits\n"
4234 "Guest Physical Address Width: %d bits\n",
4235 (uEAX >> 0) & 0xff,
4236 (uEAX >> 8) & 0xff,
4237 (uEAX >> 16) & 0xff);
4238 pHlp->pfnPrintf(pHlp,
4239 "Physical Core Count: %d\n",
4240 (uECX >> 0) & 0xff);
4241 }
4242
4243
4244 /*
4245 * Centaur.
4246 */
4247 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
4248
4249 pHlp->pfnPrintf(pHlp,
4250 "\n"
4251 " RAW Centaur CPUIDs\n"
4252 " Function eax ebx ecx edx\n");
4253 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
4254 {
4255 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
4256 ASMCpuIdExSlow(0xc0000000 | i, 0, 0, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
4257
4258 pHlp->pfnPrintf(pHlp,
4259 "Gst: %08x %08x %08x %08x %08x%s\n"
4260 "Hst: %08x %08x %08x %08x\n",
4261 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
4262 i <= cCentaurMax ? "" : "*",
4263 Host.eax, Host.ebx, Host.ecx, Host.edx);
4264 }
4265
4266 /*
4267 * Understandable output
4268 */
4269 if (iVerbosity)
4270 {
4271 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
4272 pHlp->pfnPrintf(pHlp,
4273 "Centaur Supports: 0xc0000000-%#010x\n",
4274 Guest.eax);
4275 }
4276
4277 if (iVerbosity && cCentaurMax >= 1)
4278 {
4279 ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
4280 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdCentaur[1].edx;
4281 uint32_t uEdxHst = Host.edx;
4282
4283 if (iVerbosity == 1)
4284 {
4285 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
4286 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
4287 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
4288 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
4289 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
4290 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
4291 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
4292 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
4293 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
4294 /* possibly indicating MM/HE and MM/HE-E on older chips... */
4295 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
4296 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
4297 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
4298 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
4299 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
4300 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
4301 for (unsigned iBit = 14; iBit < 32; iBit++)
4302 if (uEdxGst & RT_BIT(iBit))
4303 pHlp->pfnPrintf(pHlp, " %d", iBit);
4304 pHlp->pfnPrintf(pHlp, "\n");
4305 }
4306 else
4307 {
4308 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
4309 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
4310 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
4311 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
4312 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
4313 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
4314 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
4315 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
4316 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
4317 /* possibly indicating MM/HE and MM/HE-E on older chips... */
4318 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
4319 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
4320 pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
4321 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
4322 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
4323 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
4324 pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
4325 pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
4326 pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
4327 pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
4328 pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
4329 pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
4330 pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
4331 pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
4332 pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
4333 pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
4334 pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
4335 pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
4336 pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
4337 for (unsigned iBit = 27; iBit < 32; iBit++)
4338 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
4339 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
4340 pHlp->pfnPrintf(pHlp, "\n");
4341 }
4342 }
4343}
4344
4345
4346/**
4347 * Structure used when disassembling and instructions in DBGF.
4348 * This is used so the reader function can get the stuff it needs.
4349 */
4350typedef struct CPUMDISASSTATE
4351{
4352 /** Pointer to the CPU structure. */
4353 PDISCPUSTATE pCpu;
4354 /** Pointer to the VM. */
4355 PVM pVM;
4356 /** Pointer to the VMCPU. */
4357 PVMCPU pVCpu;
4358 /** Pointer to the first byte in the segment. */
4359 RTGCUINTPTR GCPtrSegBase;
4360 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
4361 RTGCUINTPTR GCPtrSegEnd;
4362 /** The size of the segment minus 1. */
4363 RTGCUINTPTR cbSegLimit;
4364 /** Pointer to the current page - R3 Ptr. */
4365 void const *pvPageR3;
4366 /** Pointer to the current page - GC Ptr. */
4367 RTGCPTR pvPageGC;
4368 /** The lock information that PGMPhysReleasePageMappingLock needs. */
4369 PGMPAGEMAPLOCK PageMapLock;
4370 /** Whether the PageMapLock is valid or not. */
4371 bool fLocked;
4372 /** 64 bits mode or not. */
4373 bool f64Bits;
4374} CPUMDISASSTATE, *PCPUMDISASSTATE;
4375
4376
4377/**
4378 * @callback_method_impl{FNDISREADBYTES}
4379 */
4380static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
4381{
4382 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
4383 for (;;)
4384 {
4385 RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
4386
4387 /*
4388 * Need to update the page translation?
4389 */
4390 if ( !pState->pvPageR3
4391 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
4392 {
4393 int rc = VINF_SUCCESS;
4394
4395 /* translate the address */
4396 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
4397 if ( !HMIsEnabled(pState->pVM)
4398 && MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
4399 {
4400 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
4401 if (!pState->pvPageR3)
4402 rc = VERR_INVALID_POINTER;
4403 }
4404 else
4405 {
4406 /* Release mapping lock previously acquired. */
4407 if (pState->fLocked)
4408 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
4409 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
4410 pState->fLocked = RT_SUCCESS_NP(rc);
4411 }
4412 if (RT_FAILURE(rc))
4413 {
4414 pState->pvPageR3 = NULL;
4415 return rc;
4416 }
4417 }
4418
4419 /*
4420 * Check the segment limit.
4421 */
4422 if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
4423 return VERR_OUT_OF_SELECTOR_BOUNDS;
4424
4425 /*
4426 * Calc how much we can read.
4427 */
4428 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
4429 if (!pState->f64Bits)
4430 {
4431 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
4432 if (cb > cbSeg && cbSeg)
4433 cb = cbSeg;
4434 }
4435 if (cb > cbMaxRead)
4436 cb = cbMaxRead;
4437
4438 /*
4439 * Read and advance or exit.
4440 */
4441 memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
4442 offInstr += (uint8_t)cb;
4443 if (cb >= cbMinRead)
4444 {
4445 pDis->cbCachedInstr = offInstr;
4446 return VINF_SUCCESS;
4447 }
4448 cbMinRead -= (uint8_t)cb;
4449 cbMaxRead -= (uint8_t)cb;
4450 }
4451}
4452
4453
4454/**
4455 * Disassemble an instruction and return the information in the provided structure.
4456 *
4457 * @returns VBox status code.
4458 * @param pVM Pointer to the VM.
4459 * @param pVCpu Pointer to the VMCPU.
4460 * @param pCtx Pointer to the guest CPU context.
4461 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
4462 * @param pCpu Disassembly state.
4463 * @param pszPrefix String prefix for logging (debug only).
4464 *
4465 */
4466VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
4467{
4468 CPUMDISASSTATE State;
4469 int rc;
4470
4471 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
4472 State.pCpu = pCpu;
4473 State.pvPageGC = 0;
4474 State.pvPageR3 = NULL;
4475 State.pVM = pVM;
4476 State.pVCpu = pVCpu;
4477 State.fLocked = false;
4478 State.f64Bits = false;
4479
4480 /*
4481 * Get selector information.
4482 */
4483 DISCPUMODE enmDisCpuMode;
4484 if ( (pCtx->cr0 & X86_CR0_PE)
4485 && pCtx->eflags.Bits.u1VM == 0)
4486 {
4487 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4488 {
4489# ifdef VBOX_WITH_RAW_MODE_NOT_R0
4490 CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, &pCtx->cs);
4491# endif
4492 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4493 return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
4494 }
4495 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
4496 State.GCPtrSegBase = pCtx->cs.u64Base;
4497 State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
4498 State.cbSegLimit = pCtx->cs.u32Limit;
4499 enmDisCpuMode = (State.f64Bits)
4500 ? DISCPUMODE_64BIT
4501 : pCtx->cs.Attr.n.u1DefBig
4502 ? DISCPUMODE_32BIT
4503 : DISCPUMODE_16BIT;
4504 }
4505 else
4506 {
4507 /* real or V86 mode */
4508 enmDisCpuMode = DISCPUMODE_16BIT;
4509 State.GCPtrSegBase = pCtx->cs.Sel * 16;
4510 State.GCPtrSegEnd = 0xFFFFFFFF;
4511 State.cbSegLimit = 0xFFFFFFFF;
4512 }
4513
4514 /*
4515 * Disassemble the instruction.
4516 */
4517 uint32_t cbInstr;
4518#ifndef LOG_ENABLED
4519 rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
4520 if (RT_SUCCESS(rc))
4521 {
4522#else
4523 char szOutput[160];
4524 rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
4525 pCpu, &cbInstr, szOutput, sizeof(szOutput));
4526 if (RT_SUCCESS(rc))
4527 {
4528 /* log it */
4529 if (pszPrefix)
4530 Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
4531 else
4532 Log(("%s", szOutput));
4533#endif
4534 rc = VINF_SUCCESS;
4535 }
4536 else
4537 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
4538
4539 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
4540 if (State.fLocked)
4541 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
4542
4543 return rc;
4544}
4545
4546
4547
4548/**
4549 * API for controlling a few of the CPU features found in CR4.
4550 *
4551 * Currently only X86_CR4_TSD is accepted as input.
4552 *
4553 * @returns VBox status code.
4554 *
4555 * @param pVM Pointer to the VM.
4556 * @param fOr The CR4 OR mask.
4557 * @param fAnd The CR4 AND mask.
4558 */
4559VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
4560{
4561 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
4562 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
4563
4564 pVM->cpum.s.CR4.OrMask &= fAnd;
4565 pVM->cpum.s.CR4.OrMask |= fOr;
4566
4567 return VINF_SUCCESS;
4568}
4569
4570
4571/**
4572 * Gets a pointer to the array of standard CPUID leaves.
4573 *
4574 * CPUMR3GetGuestCpuIdStdMax() give the size of the array.
4575 *
4576 * @returns Pointer to the standard CPUID leaves (read-only).
4577 * @param pVM Pointer to the VM.
4578 * @remark Intended for PATM.
4579 */
4580VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM)
4581{
4582 return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
4583}
4584
4585
4586/**
4587 * Gets a pointer to the array of extended CPUID leaves.
4588 *
4589 * CPUMGetGuestCpuIdExtMax() give the size of the array.
4590 *
4591 * @returns Pointer to the extended CPUID leaves (read-only).
4592 * @param pVM Pointer to the VM.
4593 * @remark Intended for PATM.
4594 */
4595VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM)
4596{
4597 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
4598}
4599
4600
4601/**
4602 * Gets a pointer to the array of centaur CPUID leaves.
4603 *
4604 * CPUMGetGuestCpuIdCentaurMax() give the size of the array.
4605 *
4606 * @returns Pointer to the centaur CPUID leaves (read-only).
4607 * @param pVM Pointer to the VM.
4608 * @remark Intended for PATM.
4609 */
4610VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM)
4611{
4612 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
4613}
4614
4615
4616/**
4617 * Gets a pointer to the default CPUID leaf.
4618 *
4619 * @returns Pointer to the default CPUID leaf (read-only).
4620 * @param pVM Pointer to the VM.
4621 * @remark Intended for PATM.
4622 */
4623VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM)
4624{
4625 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
4626}
4627
4628
4629/**
4630 * Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
4631 *
4632 * Only REM should ever call this function!
4633 *
4634 * @returns The changed flags.
4635 * @param pVCpu Pointer to the VMCPU.
4636 * @param puCpl Where to return the current privilege level (CPL).
4637 */
4638VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
4639{
4640 Assert(!pVCpu->cpum.s.fRawEntered);
4641 Assert(!pVCpu->cpum.s.fRemEntered);
4642
4643 /*
4644 * Get the CPL first.
4645 */
4646 *puCpl = CPUMGetGuestCPL(pVCpu);
4647
4648 /*
4649 * Get and reset the flags.
4650 */
4651 uint32_t fFlags = pVCpu->cpum.s.fChanged;
4652 pVCpu->cpum.s.fChanged = 0;
4653
4654 /** @todo change the switcher to use the fChanged flags. */
4655 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
4656 {
4657 fFlags |= CPUM_CHANGED_FPU_REM;
4658 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
4659 }
4660
4661 pVCpu->cpum.s.fRemEntered = true;
4662 return fFlags;
4663}
4664
4665
4666/**
4667 * Leaves REM.
4668 *
4669 * @param pVCpu Pointer to the VMCPU.
4670 * @param fNoOutOfSyncSels This is @c false if there are out of sync
4671 * registers.
4672 */
4673VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
4674{
4675 Assert(!pVCpu->cpum.s.fRawEntered);
4676 Assert(pVCpu->cpum.s.fRemEntered);
4677
4678 pVCpu->cpum.s.fRemEntered = false;
4679}
4680
4681
4682/**
4683 * Called when the ring-3 init phase completes.
4684 *
4685 * @returns VBox status code.
4686 * @param pVM Pointer to the VM.
4687 */
4688VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM)
4689{
4690 for (VMCPUID i = 0; i < pVM->cCpus; i++)
4691 {
4692 /* Cache the APIC base (from the APIC device) once it has been initialized. */
4693 PDMApicGetBase(&pVM->aCpus[i], &pVM->aCpus[i].cpum.s.Guest.msrApicBase);
4694 Log(("CPUMR3InitCompleted pVM=%p APIC base[%u]=%RX64\n", pVM, (unsigned)i, pVM->aCpus[i].cpum.s.Guest.msrApicBase));
4695 }
4696 return VINF_SUCCESS;
4697}
4698
4699/**
4700 * Called when the ring-0 init phases comleted.
4701 *
4702 * @param pVM Pointer to the VM.
4703 */
4704VMMR3DECL(void) CPUMR3LogCpuIds(PVM pVM)
4705{
4706 /*
4707 * Log the cpuid.
4708 */
4709 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
4710 RTCPUSET OnlineSet;
4711 LogRel(("Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
4712 (unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
4713 RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
4714 RTCPUID cCores = RTMpGetCoreCount();
4715 if (cCores)
4716 LogRel(("Physical host cores: %u\n", (unsigned)cCores));
4717 LogRel(("************************* CPUID dump ************************\n"));
4718 DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
4719 LogRel(("\n"));
4720 DBGFR3_INFO_LOG(pVM, "cpuid", "verbose"); /* macro */
4721 RTLogRelSetBuffering(fOldBuffered);
4722 LogRel(("******************** End of CPUID dump **********************\n"));
4723}
4724
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