VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 44078

最後變更 在這個檔案從44078是 44078,由 vboxsync 提交於 12 年 前

VMMR0/CPUMR0: atomic update of aGuestCpuId*(); fix return type of CPUMR3LogCpuIds()
  • 屬性 svn:eol-style 設為 native
  • 屬性 svn:keywords 設為 Id Revision
檔案大小: 212.7 KB
行 
1/* $Id: CPUM.cpp 44078 2012-12-10 13:19:18Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2012 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.alldomusa.eu.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_cpum CPUM - CPU Monitor / Manager
19 *
20 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
21 * also responsible for lazy FPU handling and some of the context loading
22 * in raw mode.
23 *
24 * There are three CPU contexts, the most important one is the guest one (GC).
25 * When running in raw-mode (RC) there is a special hyper context for the VMM
26 * part that floats around inside the guest address space. When running in
27 * raw-mode, CPUM also maintains a host context for saving and restoring
28 * registers across world switches. This latter is done in cooperation with the
29 * world switcher (@see pg_vmm).
30 *
31 * @see grp_cpum
32 */
33
34/*******************************************************************************
35* Header Files *
36*******************************************************************************/
37#define LOG_GROUP LOG_GROUP_CPUM
38#include <VBox/vmm/cpum.h>
39#include <VBox/vmm/cpumdis.h>
40#include <VBox/vmm/cpumctx-v1_6.h>
41#include <VBox/vmm/pgm.h>
42#include <VBox/vmm/pdmapi.h>
43#include <VBox/vmm/mm.h>
44#include <VBox/vmm/selm.h>
45#include <VBox/vmm/dbgf.h>
46#include <VBox/vmm/patm.h>
47#include <VBox/vmm/hm.h>
48#include <VBox/vmm/ssm.h>
49#include "CPUMInternal.h"
50#include <VBox/vmm/vm.h>
51
52#include <VBox/param.h>
53#include <VBox/dis.h>
54#include <VBox/err.h>
55#include <VBox/log.h>
56#include <iprt/assert.h>
57#include <iprt/asm-amd64-x86.h>
58#include <iprt/string.h>
59#include <iprt/mp.h>
60#include <iprt/cpuset.h>
61#include "internal/pgm.h"
62
63
64/*******************************************************************************
65* Defined Constants And Macros *
66*******************************************************************************/
67/** The current saved state version. */
68#define CPUM_SAVED_STATE_VERSION 14
69/** The current saved state version before using SSMR3PutStruct. */
70#define CPUM_SAVED_STATE_VERSION_MEM 13
71/** The saved state version before introducing the MSR size field. */
72#define CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE 12
73/** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
74 * selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
75#define CPUM_SAVED_STATE_VERSION_VER3_2 11
76/** The saved state version of 3.0 and 3.1 trunk before the teleportation
77 * changes. */
78#define CPUM_SAVED_STATE_VERSION_VER3_0 10
79/** The saved state version for the 2.1 trunk before the MSR changes. */
80#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
81/** The saved state version of 2.0, used for backwards compatibility. */
82#define CPUM_SAVED_STATE_VERSION_VER2_0 8
83/** The saved state version of 1.6, used for backwards compatibility. */
84#define CPUM_SAVED_STATE_VERSION_VER1_6 6
85
86
87/**
88 * This was used in the saved state up to the early life of version 14.
89 *
90 * It indicates that we may have some out-of-sync hidden segement registers.
91 * It is only relevant for raw-mode.
92 */
93#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
94
95
96/*******************************************************************************
97* Structures and Typedefs *
98*******************************************************************************/
99
100/**
101 * What kind of cpu info dump to perform.
102 */
103typedef enum CPUMDUMPTYPE
104{
105 CPUMDUMPTYPE_TERSE,
106 CPUMDUMPTYPE_DEFAULT,
107 CPUMDUMPTYPE_VERBOSE
108} CPUMDUMPTYPE;
109/** Pointer to a cpu info dump type. */
110typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
111
112
113/*******************************************************************************
114* Internal Functions *
115*******************************************************************************/
116static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
117static int cpumR3CpuIdInit(PVM pVM);
118static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
119static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
120static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
121static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
122static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
123static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
124static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
125static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
126static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
127static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
128static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
129
130
131/*******************************************************************************
132* Global Variables *
133*******************************************************************************/
134/** Saved state field descriptors for CPUMCTX. */
135static const SSMFIELD g_aCpumCtxFields[] =
136{
137 SSMFIELD_ENTRY( CPUMCTX, fpu.FCW),
138 SSMFIELD_ENTRY( CPUMCTX, fpu.FSW),
139 SSMFIELD_ENTRY( CPUMCTX, fpu.FTW),
140 SSMFIELD_ENTRY( CPUMCTX, fpu.FOP),
141 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUIP),
142 SSMFIELD_ENTRY( CPUMCTX, fpu.CS),
143 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd1),
144 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUDP),
145 SSMFIELD_ENTRY( CPUMCTX, fpu.DS),
146 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd2),
147 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR),
148 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR_MASK),
149 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[0]),
150 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[1]),
151 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[2]),
152 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[3]),
153 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[4]),
154 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[5]),
155 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[6]),
156 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[7]),
157 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[0]),
158 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[1]),
159 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[2]),
160 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[3]),
161 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[4]),
162 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[5]),
163 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[6]),
164 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[7]),
165 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[8]),
166 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[9]),
167 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[10]),
168 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[11]),
169 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[12]),
170 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[13]),
171 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[14]),
172 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[15]),
173 SSMFIELD_ENTRY( CPUMCTX, rdi),
174 SSMFIELD_ENTRY( CPUMCTX, rsi),
175 SSMFIELD_ENTRY( CPUMCTX, rbp),
176 SSMFIELD_ENTRY( CPUMCTX, rax),
177 SSMFIELD_ENTRY( CPUMCTX, rbx),
178 SSMFIELD_ENTRY( CPUMCTX, rdx),
179 SSMFIELD_ENTRY( CPUMCTX, rcx),
180 SSMFIELD_ENTRY( CPUMCTX, rsp),
181 SSMFIELD_ENTRY( CPUMCTX, rflags),
182 SSMFIELD_ENTRY( CPUMCTX, rip),
183 SSMFIELD_ENTRY( CPUMCTX, r8),
184 SSMFIELD_ENTRY( CPUMCTX, r9),
185 SSMFIELD_ENTRY( CPUMCTX, r10),
186 SSMFIELD_ENTRY( CPUMCTX, r11),
187 SSMFIELD_ENTRY( CPUMCTX, r12),
188 SSMFIELD_ENTRY( CPUMCTX, r13),
189 SSMFIELD_ENTRY( CPUMCTX, r14),
190 SSMFIELD_ENTRY( CPUMCTX, r15),
191 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
192 SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
193 SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
194 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
195 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
196 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
197 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
198 SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
199 SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
200 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
201 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
202 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
203 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
204 SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
205 SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
206 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
207 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
208 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
209 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
210 SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
211 SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
212 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
213 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
214 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
215 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
216 SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
217 SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
218 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
219 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
220 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
221 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
222 SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
223 SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
224 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
225 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
226 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
227 SSMFIELD_ENTRY( CPUMCTX, cr0),
228 SSMFIELD_ENTRY( CPUMCTX, cr2),
229 SSMFIELD_ENTRY( CPUMCTX, cr3),
230 SSMFIELD_ENTRY( CPUMCTX, cr4),
231 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
232 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
233 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
234 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
235 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
236 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
237 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
238 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
239 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
240 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
241 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
242 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
243 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
244 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
245 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
246 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
247 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
248 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
249 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
250 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
251 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
252 SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
253 SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
254 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
255 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
256 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
257 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
258 SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
259 SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
260 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
261 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
262 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
263 SSMFIELD_ENTRY_TERM()
264};
265
266/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
267 * registeres changed. */
268static const SSMFIELD g_aCpumCtxFieldsMem[] =
269{
270 SSMFIELD_ENTRY( CPUMCTX, fpu.FCW),
271 SSMFIELD_ENTRY( CPUMCTX, fpu.FSW),
272 SSMFIELD_ENTRY( CPUMCTX, fpu.FTW),
273 SSMFIELD_ENTRY( CPUMCTX, fpu.FOP),
274 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUIP),
275 SSMFIELD_ENTRY( CPUMCTX, fpu.CS),
276 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd1),
277 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUDP),
278 SSMFIELD_ENTRY( CPUMCTX, fpu.DS),
279 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd2),
280 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR),
281 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR_MASK),
282 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[0]),
283 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[1]),
284 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[2]),
285 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[3]),
286 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[4]),
287 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[5]),
288 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[6]),
289 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[7]),
290 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[0]),
291 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[1]),
292 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[2]),
293 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[3]),
294 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[4]),
295 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[5]),
296 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[6]),
297 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[7]),
298 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[8]),
299 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[9]),
300 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[10]),
301 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[11]),
302 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[12]),
303 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[13]),
304 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[14]),
305 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[15]),
306 SSMFIELD_ENTRY_IGNORE( CPUMCTX, fpu.au32RsrvdRest),
307 SSMFIELD_ENTRY( CPUMCTX, rdi),
308 SSMFIELD_ENTRY( CPUMCTX, rsi),
309 SSMFIELD_ENTRY( CPUMCTX, rbp),
310 SSMFIELD_ENTRY( CPUMCTX, rax),
311 SSMFIELD_ENTRY( CPUMCTX, rbx),
312 SSMFIELD_ENTRY( CPUMCTX, rdx),
313 SSMFIELD_ENTRY( CPUMCTX, rcx),
314 SSMFIELD_ENTRY( CPUMCTX, rsp),
315 SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
316 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
317 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
318 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
319 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
320 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
321 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
322 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
323 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
324 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
325 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
326 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
327 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
328 SSMFIELD_ENTRY( CPUMCTX, rflags),
329 SSMFIELD_ENTRY( CPUMCTX, rip),
330 SSMFIELD_ENTRY( CPUMCTX, r8),
331 SSMFIELD_ENTRY( CPUMCTX, r9),
332 SSMFIELD_ENTRY( CPUMCTX, r10),
333 SSMFIELD_ENTRY( CPUMCTX, r11),
334 SSMFIELD_ENTRY( CPUMCTX, r12),
335 SSMFIELD_ENTRY( CPUMCTX, r13),
336 SSMFIELD_ENTRY( CPUMCTX, r14),
337 SSMFIELD_ENTRY( CPUMCTX, r15),
338 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
339 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
340 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
341 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
342 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
343 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
344 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
345 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
346 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
347 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
348 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
349 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
350 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
351 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
352 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
353 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
354 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
355 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
356 SSMFIELD_ENTRY( CPUMCTX, cr0),
357 SSMFIELD_ENTRY( CPUMCTX, cr2),
358 SSMFIELD_ENTRY( CPUMCTX, cr3),
359 SSMFIELD_ENTRY( CPUMCTX, cr4),
360 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
361 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
362 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
363 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
364 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
365 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
366 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
367 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
368 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
369 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
370 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
371 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
372 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
373 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
374 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
375 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
376 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
377 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
378 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
379 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
380 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
381 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
382 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
383 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
384 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
385 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
386 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
387 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
388 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
389 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
390 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
391 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
392 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
393 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
394 SSMFIELD_ENTRY_TERM()
395};
396
397/** Saved state field descriptors for CPUMCTX_VER1_6. */
398static const SSMFIELD g_aCpumCtxFieldsV16[] =
399{
400 SSMFIELD_ENTRY( CPUMCTX, fpu.FCW),
401 SSMFIELD_ENTRY( CPUMCTX, fpu.FSW),
402 SSMFIELD_ENTRY( CPUMCTX, fpu.FTW),
403 SSMFIELD_ENTRY( CPUMCTX, fpu.FOP),
404 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUIP),
405 SSMFIELD_ENTRY( CPUMCTX, fpu.CS),
406 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd1),
407 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUDP),
408 SSMFIELD_ENTRY( CPUMCTX, fpu.DS),
409 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd2),
410 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR),
411 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR_MASK),
412 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[0]),
413 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[1]),
414 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[2]),
415 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[3]),
416 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[4]),
417 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[5]),
418 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[6]),
419 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[7]),
420 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[0]),
421 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[1]),
422 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[2]),
423 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[3]),
424 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[4]),
425 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[5]),
426 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[6]),
427 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[7]),
428 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[8]),
429 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[9]),
430 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[10]),
431 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[11]),
432 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[12]),
433 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[13]),
434 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[14]),
435 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[15]),
436 SSMFIELD_ENTRY_IGNORE( CPUMCTX, fpu.au32RsrvdRest),
437 SSMFIELD_ENTRY( CPUMCTX, rdi),
438 SSMFIELD_ENTRY( CPUMCTX, rsi),
439 SSMFIELD_ENTRY( CPUMCTX, rbp),
440 SSMFIELD_ENTRY( CPUMCTX, rax),
441 SSMFIELD_ENTRY( CPUMCTX, rbx),
442 SSMFIELD_ENTRY( CPUMCTX, rdx),
443 SSMFIELD_ENTRY( CPUMCTX, rcx),
444 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
445 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
446 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
447 SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /*rsp_notused*/),
448 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
449 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
450 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
451 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
452 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
453 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
454 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
455 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
456 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
457 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
458 SSMFIELD_ENTRY( CPUMCTX, rflags),
459 SSMFIELD_ENTRY( CPUMCTX, rip),
460 SSMFIELD_ENTRY( CPUMCTX, r8),
461 SSMFIELD_ENTRY( CPUMCTX, r9),
462 SSMFIELD_ENTRY( CPUMCTX, r10),
463 SSMFIELD_ENTRY( CPUMCTX, r11),
464 SSMFIELD_ENTRY( CPUMCTX, r12),
465 SSMFIELD_ENTRY( CPUMCTX, r13),
466 SSMFIELD_ENTRY( CPUMCTX, r14),
467 SSMFIELD_ENTRY( CPUMCTX, r15),
468 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
469 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
470 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
471 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
472 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
473 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
474 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
475 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
476 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
477 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
478 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
479 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
480 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
481 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
482 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
483 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
484 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
485 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
486 SSMFIELD_ENTRY( CPUMCTX, cr0),
487 SSMFIELD_ENTRY( CPUMCTX, cr2),
488 SSMFIELD_ENTRY( CPUMCTX, cr3),
489 SSMFIELD_ENTRY( CPUMCTX, cr4),
490 SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
491 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
492 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
493 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
494 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
495 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
496 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
497 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
498 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
499 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
500 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
501 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
502 SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
503 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
504 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
505 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
506 SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
507 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
508 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
509 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
510 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
511 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
512 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
513 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
514 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
515 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
516 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
517 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
518 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
519 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
520 SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
521 SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
522 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
523 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
524 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
525 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
526 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
527 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
528 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
529 SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
530 SSMFIELD_ENTRY_TERM()
531};
532
533
534/**
535 * Initializes the CPUM.
536 *
537 * @returns VBox status code.
538 * @param pVM Pointer to the VM.
539 */
540VMMR3DECL(int) CPUMR3Init(PVM pVM)
541{
542 LogFlow(("CPUMR3Init\n"));
543
544 /*
545 * Assert alignment and sizes.
546 */
547 AssertCompileMemberAlignment(VM, cpum.s, 32);
548 AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
549 AssertCompileSizeAlignment(CPUMCTX, 64);
550 AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
551 AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
552 AssertCompileMemberAlignment(VM, cpum, 64);
553 AssertCompileMemberAlignment(VM, aCpus, 64);
554 AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
555 AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
556
557 /* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
558 pVM->cpum.s.offCPUMCPU0 = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
559 Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
560
561 /* Calculate the offset from CPUMCPU to CPUM. */
562 for (VMCPUID i = 0; i < pVM->cCpus; i++)
563 {
564 PVMCPU pVCpu = &pVM->aCpus[i];
565
566 pVCpu->cpum.s.offCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
567 Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
568 }
569
570 /*
571 * Check that the CPU supports the minimum features we require.
572 */
573 if (!ASMHasCpuId())
574 {
575 Log(("The CPU doesn't support CPUID!\n"));
576 return VERR_UNSUPPORTED_CPU;
577 }
578 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
579 ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
580
581 /* Setup the CR4 AND and OR masks used in the switcher */
582 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
583 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
584 {
585 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
586 /* No FXSAVE implies no SSE */
587 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
588 pVM->cpum.s.CR4.OrMask = 0;
589 }
590 else
591 {
592 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
593 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
594 }
595
596 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
597 {
598 Log(("The CPU doesn't support MMX!\n"));
599 return VERR_UNSUPPORTED_CPU;
600 }
601 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
602 {
603 Log(("The CPU doesn't support TSC!\n"));
604 return VERR_UNSUPPORTED_CPU;
605 }
606 /* Bogus on AMD? */
607 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
608 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
609
610 /*
611 * Detect the host CPU vendor.
612 * (The guest CPU vendor is re-detected later on.)
613 */
614 uint32_t uEAX, uEBX, uECX, uEDX;
615 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
616 pVM->cpum.s.enmHostCpuVendor = cpumR3DetectVendor(uEAX, uEBX, uECX, uEDX);
617 pVM->cpum.s.enmGuestCpuVendor = pVM->cpum.s.enmHostCpuVendor;
618
619 /*
620 * Setup hypervisor startup values.
621 */
622
623 /*
624 * Register saved state data item.
625 */
626 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
627 NULL, cpumR3LiveExec, NULL,
628 NULL, cpumR3SaveExec, NULL,
629 cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
630 if (RT_FAILURE(rc))
631 return rc;
632
633 /*
634 * Register info handlers and registers with the debugger facility.
635 */
636 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
637 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
638 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
639 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
640 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
641 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
642
643 rc = cpumR3DbgInit(pVM);
644 if (RT_FAILURE(rc))
645 return rc;
646
647 /*
648 * Initialize the Guest CPUID state.
649 */
650 rc = cpumR3CpuIdInit(pVM);
651 if (RT_FAILURE(rc))
652 return rc;
653 CPUMR3Reset(pVM);
654 return VINF_SUCCESS;
655}
656
657
658/**
659 * Detect the CPU vendor give n the
660 *
661 * @returns The vendor.
662 * @param uEAX EAX from CPUID(0).
663 * @param uEBX EBX from CPUID(0).
664 * @param uECX ECX from CPUID(0).
665 * @param uEDX EDX from CPUID(0).
666 */
667static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
668{
669 if ( uEAX >= 1
670 && uEBX == X86_CPUID_VENDOR_AMD_EBX
671 && uECX == X86_CPUID_VENDOR_AMD_ECX
672 && uEDX == X86_CPUID_VENDOR_AMD_EDX)
673 return CPUMCPUVENDOR_AMD;
674
675 if ( uEAX >= 1
676 && uEBX == X86_CPUID_VENDOR_INTEL_EBX
677 && uECX == X86_CPUID_VENDOR_INTEL_ECX
678 && uEDX == X86_CPUID_VENDOR_INTEL_EDX)
679 return CPUMCPUVENDOR_INTEL;
680
681 if ( uEAX >= 1
682 && uEBX == X86_CPUID_VENDOR_VIA_EBX
683 && uECX == X86_CPUID_VENDOR_VIA_ECX
684 && uEDX == X86_CPUID_VENDOR_VIA_EDX)
685 return CPUMCPUVENDOR_VIA;
686
687 /** @todo detect the other buggers... */
688 return CPUMCPUVENDOR_UNKNOWN;
689}
690
691
692/**
693 * Fetches overrides for a CPUID leaf.
694 *
695 * @returns VBox status code.
696 * @param pLeaf The leaf to load the overrides into.
697 * @param pCfgNode The CFGM node containing the overrides
698 * (/CPUM/HostCPUID/ or /CPUM/CPUID/).
699 * @param iLeaf The CPUID leaf number.
700 */
701static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
702{
703 PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
704 if (pLeafNode)
705 {
706 uint32_t u32;
707 int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
708 if (RT_SUCCESS(rc))
709 pLeaf->eax = u32;
710 else
711 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
712
713 rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
714 if (RT_SUCCESS(rc))
715 pLeaf->ebx = u32;
716 else
717 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
718
719 rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
720 if (RT_SUCCESS(rc))
721 pLeaf->ecx = u32;
722 else
723 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
724
725 rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
726 if (RT_SUCCESS(rc))
727 pLeaf->edx = u32;
728 else
729 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
730
731 }
732 return VINF_SUCCESS;
733}
734
735
736/**
737 * Load the overrides for a set of CPUID leaves.
738 *
739 * @returns VBox status code.
740 * @param paLeaves The leaf array.
741 * @param cLeaves The number of leaves.
742 * @param uStart The start leaf number.
743 * @param pCfgNode The CFGM node containing the overrides
744 * (/CPUM/HostCPUID/ or /CPUM/CPUID/).
745 */
746static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
747{
748 for (uint32_t i = 0; i < cLeaves; i++)
749 {
750 int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
751 if (RT_FAILURE(rc))
752 return rc;
753 }
754
755 return VINF_SUCCESS;
756}
757
758/**
759 * Init a set of host CPUID leaves.
760 *
761 * @returns VBox status code.
762 * @param paLeaves The leaf array.
763 * @param cLeaves The number of leaves.
764 * @param uStart The start leaf number.
765 * @param pCfgNode The /CPUM/HostCPUID/ node.
766 */
767static int cpumR3CpuIdInitHostSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
768{
769 /* Using the ECX variant for all of them can't hurt... */
770 for (uint32_t i = 0; i < cLeaves; i++)
771 ASMCpuId_Idx_ECX(uStart + i, 0, &paLeaves[i].eax, &paLeaves[i].ebx, &paLeaves[i].ecx, &paLeaves[i].edx);
772
773 /* Load CPUID leaf override; we currently don't care if the user
774 specifies features the host CPU doesn't support. */
775 return cpumR3CpuIdInitLoadOverrideSet(uStart, paLeaves, cLeaves, pCfgNode);
776}
777
778
779/**
780 * Initializes the emulated CPU's cpuid information.
781 *
782 * @returns VBox status code.
783 * @param pVM Pointer to the VM.
784 */
785static int cpumR3CpuIdInit(PVM pVM)
786{
787 PCPUM pCPUM = &pVM->cpum.s;
788 PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
789 uint32_t i;
790 int rc;
791
792#define PORTABLE_CLEAR_BITS_WHEN(Lvl, LeafSuffReg, FeatNm, fMask, uValue) \
793 if (pCPUM->u8PortableCpuIdLevel >= (Lvl) && (pCPUM->aGuestCpuId##LeafSuffReg & (fMask)) == (uValue) ) \
794 { \
795 LogRel(("PortableCpuId: " #LeafSuffReg "[" #FeatNm "]: %#x -> 0\n", pCPUM->aGuestCpuId##LeafSuffReg & (fMask))); \
796 pCPUM->aGuestCpuId##LeafSuffReg &= ~(uint32_t)(fMask); \
797 }
798#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, LeafSuffReg, FeatNm, fBitMask) \
799 if (pCPUM->u8PortableCpuIdLevel >= (Lvl) && (pCPUM->aGuestCpuId##LeafSuffReg & (fBitMask)) ) \
800 { \
801 LogRel(("PortableCpuId: " #LeafSuffReg "[" #FeatNm "]: 1 -> 0\n")); \
802 pCPUM->aGuestCpuId##LeafSuffReg &= ~(uint32_t)(fBitMask); \
803 }
804
805 /*
806 * Read the configuration.
807 */
808 /** @cfgm{CPUM/SyntheticCpu, boolean, false}
809 * Enables the Synthetic CPU. The Vendor ID and Processor Name are
810 * completely overridden by VirtualBox custom strings. Some
811 * CPUID information is withheld, like the cache info. */
812 rc = CFGMR3QueryBoolDef(pCpumCfg, "SyntheticCpu", &pCPUM->fSyntheticCpu, false);
813 AssertRCReturn(rc, rc);
814
815 /** @cfgm{CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
816 * When non-zero CPUID features that could cause portability issues will be
817 * stripped. The higher the value the more features gets stripped. Higher
818 * values should only be used when older CPUs are involved since it may
819 * harm performance and maybe also cause problems with specific guests. */
820 rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pCPUM->u8PortableCpuIdLevel, 0);
821 AssertRCReturn(rc, rc);
822
823 AssertLogRelReturn(!pCPUM->fSyntheticCpu || !pCPUM->u8PortableCpuIdLevel, VERR_CPUM_INCOMPATIBLE_CONFIG);
824
825 /*
826 * Get the host CPUID leaves and redetect the guest CPU vendor (could've
827 * been overridden).
828 */
829 /** @cfgm{CPUM/HostCPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
830 * Overrides the host CPUID leaf values used for calculating the guest CPUID
831 * leaves. This can be used to preserve the CPUID values when moving a VM to a
832 * different machine. Another use is restricting (or extending) the feature set
833 * exposed to the guest. */
834 PCFGMNODE pHostOverrideCfg = CFGMR3GetChild(pCpumCfg, "HostCPUID");
835 rc = cpumR3CpuIdInitHostSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pHostOverrideCfg);
836 AssertRCReturn(rc, rc);
837 rc = cpumR3CpuIdInitHostSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pHostOverrideCfg);
838 AssertRCReturn(rc, rc);
839 rc = cpumR3CpuIdInitHostSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pHostOverrideCfg);
840 AssertRCReturn(rc, rc);
841
842 pCPUM->enmGuestCpuVendor = cpumR3DetectVendor(pCPUM->aGuestCpuIdStd[0].eax, pCPUM->aGuestCpuIdStd[0].ebx,
843 pCPUM->aGuestCpuIdStd[0].ecx, pCPUM->aGuestCpuIdStd[0].edx);
844
845 /*
846 * Determine the default leaf.
847 *
848 * Intel returns values of the highest standard function, while AMD
849 * returns zeros. VIA on the other hand seems to returning nothing or
850 * perhaps some random garbage, we don't try to duplicate this behavior.
851 */
852 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10, /** @todo r=bird: Use the host value here in case of overrides and more than 10 leaves being stripped already. */
853 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
854 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
855
856 /** @cfgm{/CPUM/CMPXCHG16B, boolean, false}
857 * Expose CMPXCHG16B to the guest if supported by the host.
858 */
859 bool fCmpXchg16b;
860 rc = CFGMR3QueryBoolDef(pCpumCfg, "CMPXCHG16B", &fCmpXchg16b, false); AssertRCReturn(rc, rc);
861
862 bool fMonitor;
863 rc = CFGMR3QueryBoolDef(pCpumCfg, "MONITOR", &fMonitor, true); AssertRCReturn(rc, rc);
864
865 /* Cpuid 1 & 0x80000001:
866 * Only report features we can support.
867 *
868 * Note! When enabling new features the Synthetic CPU and Portable CPUID
869 * options may require adjusting (i.e. stripping what was enabled).
870 */
871 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
872 | X86_CPUID_FEATURE_EDX_VME
873 | X86_CPUID_FEATURE_EDX_DE
874 | X86_CPUID_FEATURE_EDX_PSE
875 | X86_CPUID_FEATURE_EDX_TSC
876 | X86_CPUID_FEATURE_EDX_MSR
877 //| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
878 | X86_CPUID_FEATURE_EDX_MCE
879 | X86_CPUID_FEATURE_EDX_CX8
880 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
881 /* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
882 //| X86_CPUID_FEATURE_EDX_SEP
883 | X86_CPUID_FEATURE_EDX_MTRR
884 | X86_CPUID_FEATURE_EDX_PGE
885 | X86_CPUID_FEATURE_EDX_MCA
886 | X86_CPUID_FEATURE_EDX_CMOV
887 | X86_CPUID_FEATURE_EDX_PAT
888 | X86_CPUID_FEATURE_EDX_PSE36
889 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
890 | X86_CPUID_FEATURE_EDX_CLFSH
891 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
892 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
893 | X86_CPUID_FEATURE_EDX_MMX
894 | X86_CPUID_FEATURE_EDX_FXSR
895 | X86_CPUID_FEATURE_EDX_SSE
896 | X86_CPUID_FEATURE_EDX_SSE2
897 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
898 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
899 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
900 //| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
901 | 0;
902 pCPUM->aGuestCpuIdStd[1].ecx &= 0
903 | X86_CPUID_FEATURE_ECX_SSE3
904 /* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
905 | ((fMonitor && pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
906 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
907 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
908 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
909 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
910 | X86_CPUID_FEATURE_ECX_SSSE3
911 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
912 | (fCmpXchg16b ? X86_CPUID_FEATURE_ECX_CX16 : 0)
913 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
914 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
915 /* ECX Bit 21 - x2APIC support - not yet. */
916 // | X86_CPUID_FEATURE_ECX_X2APIC
917 /* ECX Bit 23 - POPCNT instruction. */
918 //| X86_CPUID_FEATURE_ECX_POPCNT
919 | 0;
920 if (pCPUM->u8PortableCpuIdLevel > 0)
921 {
922 PORTABLE_CLEAR_BITS_WHEN(1, Std[1].eax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
923 PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
924 PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
925 PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, CX16, X86_CPUID_FEATURE_ECX_CX16);
926 PORTABLE_DISABLE_FEATURE_BIT(2, Std[1].edx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
927 PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, SSE, X86_CPUID_FEATURE_EDX_SSE);
928 PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
929 PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
930
931 Assert(!(pCPUM->aGuestCpuIdStd[1].edx & ( X86_CPUID_FEATURE_EDX_SEP
932 | X86_CPUID_FEATURE_EDX_PSN
933 | X86_CPUID_FEATURE_EDX_DS
934 | X86_CPUID_FEATURE_EDX_ACPI
935 | X86_CPUID_FEATURE_EDX_SS
936 | X86_CPUID_FEATURE_EDX_TM
937 | X86_CPUID_FEATURE_EDX_PBE
938 )));
939 Assert(!(pCPUM->aGuestCpuIdStd[1].ecx & ( X86_CPUID_FEATURE_ECX_PCLMUL
940 | X86_CPUID_FEATURE_ECX_DTES64
941 | X86_CPUID_FEATURE_ECX_CPLDS
942 | X86_CPUID_FEATURE_ECX_VMX
943 | X86_CPUID_FEATURE_ECX_SMX
944 | X86_CPUID_FEATURE_ECX_EST
945 | X86_CPUID_FEATURE_ECX_TM2
946 | X86_CPUID_FEATURE_ECX_CNTXID
947 | X86_CPUID_FEATURE_ECX_FMA
948 | X86_CPUID_FEATURE_ECX_CX16
949 | X86_CPUID_FEATURE_ECX_TPRUPDATE
950 | X86_CPUID_FEATURE_ECX_PDCM
951 | X86_CPUID_FEATURE_ECX_DCA
952 | X86_CPUID_FEATURE_ECX_MOVBE
953 | X86_CPUID_FEATURE_ECX_AES
954 | X86_CPUID_FEATURE_ECX_POPCNT
955 | X86_CPUID_FEATURE_ECX_XSAVE
956 | X86_CPUID_FEATURE_ECX_OSXSAVE
957 | X86_CPUID_FEATURE_ECX_AVX
958 )));
959 }
960
961 /* Cpuid 0x80000001:
962 * Only report features we can support.
963 *
964 * Note! When enabling new features the Synthetic CPU and Portable CPUID
965 * options may require adjusting (i.e. stripping what was enabled).
966 *
967 * ASSUMES that this is ALWAYS the AMD defined feature set if present.
968 */
969 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
970 | X86_CPUID_AMD_FEATURE_EDX_VME
971 | X86_CPUID_AMD_FEATURE_EDX_DE
972 | X86_CPUID_AMD_FEATURE_EDX_PSE
973 | X86_CPUID_AMD_FEATURE_EDX_TSC
974 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
975 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
976 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
977 | X86_CPUID_AMD_FEATURE_EDX_CX8
978 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
979 /* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
980 //| X86_CPUID_EXT_FEATURE_EDX_SEP
981 | X86_CPUID_AMD_FEATURE_EDX_MTRR
982 | X86_CPUID_AMD_FEATURE_EDX_PGE
983 | X86_CPUID_AMD_FEATURE_EDX_MCA
984 | X86_CPUID_AMD_FEATURE_EDX_CMOV
985 | X86_CPUID_AMD_FEATURE_EDX_PAT
986 | X86_CPUID_AMD_FEATURE_EDX_PSE36
987 //| X86_CPUID_EXT_FEATURE_EDX_NX - not virtualized, requires PAE.
988 //| X86_CPUID_AMD_FEATURE_EDX_AXMMX
989 | X86_CPUID_AMD_FEATURE_EDX_MMX
990 | X86_CPUID_AMD_FEATURE_EDX_FXSR
991 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
992 //| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
993 | X86_CPUID_EXT_FEATURE_EDX_RDTSCP
994 //| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
995 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
996 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
997 | 0;
998 pCPUM->aGuestCpuIdExt[1].ecx &= 0
999 //| X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
1000 //| X86_CPUID_AMD_FEATURE_ECX_CMPL
1001 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
1002 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
1003 /* Note: This could prevent teleporting from AMD to Intel CPUs! */
1004 | X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
1005 //| X86_CPUID_AMD_FEATURE_ECX_ABM
1006 //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
1007 //| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
1008 //| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
1009 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
1010 //| X86_CPUID_AMD_FEATURE_ECX_IBS
1011 //| X86_CPUID_AMD_FEATURE_ECX_SSE5
1012 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
1013 //| X86_CPUID_AMD_FEATURE_ECX_WDT
1014 | 0;
1015 if (pCPUM->u8PortableCpuIdLevel > 0)
1016 {
1017 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].ecx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
1018 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1019 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1020 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1021 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1022 PORTABLE_DISABLE_FEATURE_BIT(2, Ext[1].ecx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1023 PORTABLE_DISABLE_FEATURE_BIT(3, Ext[1].ecx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
1024
1025 Assert(!(pCPUM->aGuestCpuIdExt[1].ecx & ( X86_CPUID_AMD_FEATURE_ECX_CMPL
1026 | X86_CPUID_AMD_FEATURE_ECX_SVM
1027 | X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
1028 | X86_CPUID_AMD_FEATURE_ECX_CR8L
1029 | X86_CPUID_AMD_FEATURE_ECX_ABM
1030 | X86_CPUID_AMD_FEATURE_ECX_SSE4A
1031 | X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
1032 | X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
1033 | X86_CPUID_AMD_FEATURE_ECX_OSVW
1034 | X86_CPUID_AMD_FEATURE_ECX_IBS
1035 | X86_CPUID_AMD_FEATURE_ECX_SSE5
1036 | X86_CPUID_AMD_FEATURE_ECX_SKINIT
1037 | X86_CPUID_AMD_FEATURE_ECX_WDT
1038 | UINT32_C(0xffffc000)
1039 )));
1040 Assert(!(pCPUM->aGuestCpuIdExt[1].edx & ( RT_BIT(10)
1041 | X86_CPUID_EXT_FEATURE_EDX_SYSCALL
1042 | RT_BIT(18)
1043 | RT_BIT(19)
1044 | RT_BIT(21)
1045 | X86_CPUID_AMD_FEATURE_EDX_AXMMX
1046 | X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
1047 | RT_BIT(28)
1048 )));
1049 }
1050
1051 /*
1052 * Apply the Synthetic CPU modifications. (TODO: move this up)
1053 */
1054 if (pCPUM->fSyntheticCpu)
1055 {
1056 static const char s_szVendor[13] = "VirtualBox ";
1057 static const char s_szProcessor[48] = "VirtualBox SPARCx86 Processor v1000 "; /* includes null terminator */
1058
1059 pCPUM->enmGuestCpuVendor = CPUMCPUVENDOR_SYNTHETIC;
1060
1061 /* Limit the nr of standard leaves; 5 for monitor/mwait */
1062 pCPUM->aGuestCpuIdStd[0].eax = RT_MIN(pCPUM->aGuestCpuIdStd[0].eax, 5);
1063
1064 /* 0: Vendor */
1065 pCPUM->aGuestCpuIdStd[0].ebx = pCPUM->aGuestCpuIdExt[0].ebx = ((uint32_t *)s_szVendor)[0];
1066 pCPUM->aGuestCpuIdStd[0].ecx = pCPUM->aGuestCpuIdExt[0].ecx = ((uint32_t *)s_szVendor)[2];
1067 pCPUM->aGuestCpuIdStd[0].edx = pCPUM->aGuestCpuIdExt[0].edx = ((uint32_t *)s_szVendor)[1];
1068
1069 /* 1.eax: Version information. family : model : stepping */
1070 pCPUM->aGuestCpuIdStd[1].eax = (0xf << 8) + (0x1 << 4) + 1;
1071
1072 /* Leaves 2 - 4 are Intel only - zero them out */
1073 memset(&pCPUM->aGuestCpuIdStd[2], 0, sizeof(pCPUM->aGuestCpuIdStd[2]));
1074 memset(&pCPUM->aGuestCpuIdStd[3], 0, sizeof(pCPUM->aGuestCpuIdStd[3]));
1075 memset(&pCPUM->aGuestCpuIdStd[4], 0, sizeof(pCPUM->aGuestCpuIdStd[4]));
1076
1077 /* Leaf 5 = monitor/mwait */
1078
1079 /* Limit the nr of extended leaves: 0x80000008 to include the max virtual and physical address size (64 bits guests). */
1080 pCPUM->aGuestCpuIdExt[0].eax = RT_MIN(pCPUM->aGuestCpuIdExt[0].eax, 0x80000008);
1081 /* AMD only - set to zero. */
1082 pCPUM->aGuestCpuIdExt[0].ebx = pCPUM->aGuestCpuIdExt[0].ecx = pCPUM->aGuestCpuIdExt[0].edx = 0;
1083
1084 /* 0x800000001: shared feature bits are set dynamically. */
1085 memset(&pCPUM->aGuestCpuIdExt[1], 0, sizeof(pCPUM->aGuestCpuIdExt[1]));
1086
1087 /* 0x800000002-4: Processor Name String Identifier. */
1088 pCPUM->aGuestCpuIdExt[2].eax = ((uint32_t *)s_szProcessor)[0];
1089 pCPUM->aGuestCpuIdExt[2].ebx = ((uint32_t *)s_szProcessor)[1];
1090 pCPUM->aGuestCpuIdExt[2].ecx = ((uint32_t *)s_szProcessor)[2];
1091 pCPUM->aGuestCpuIdExt[2].edx = ((uint32_t *)s_szProcessor)[3];
1092 pCPUM->aGuestCpuIdExt[3].eax = ((uint32_t *)s_szProcessor)[4];
1093 pCPUM->aGuestCpuIdExt[3].ebx = ((uint32_t *)s_szProcessor)[5];
1094 pCPUM->aGuestCpuIdExt[3].ecx = ((uint32_t *)s_szProcessor)[6];
1095 pCPUM->aGuestCpuIdExt[3].edx = ((uint32_t *)s_szProcessor)[7];
1096 pCPUM->aGuestCpuIdExt[4].eax = ((uint32_t *)s_szProcessor)[8];
1097 pCPUM->aGuestCpuIdExt[4].ebx = ((uint32_t *)s_szProcessor)[9];
1098 pCPUM->aGuestCpuIdExt[4].ecx = ((uint32_t *)s_szProcessor)[10];
1099 pCPUM->aGuestCpuIdExt[4].edx = ((uint32_t *)s_szProcessor)[11];
1100
1101 /* 0x800000005-7 - reserved -> zero */
1102 memset(&pCPUM->aGuestCpuIdExt[5], 0, sizeof(pCPUM->aGuestCpuIdExt[5]));
1103 memset(&pCPUM->aGuestCpuIdExt[6], 0, sizeof(pCPUM->aGuestCpuIdExt[6]));
1104 memset(&pCPUM->aGuestCpuIdExt[7], 0, sizeof(pCPUM->aGuestCpuIdExt[7]));
1105
1106 /* 0x800000008: only the max virtual and physical address size. */
1107 pCPUM->aGuestCpuIdExt[8].ecx = pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
1108 }
1109
1110 /*
1111 * Hide HTT, multicode, SMP, whatever.
1112 * (APIC-ID := 0 and #LogCpus := 0)
1113 */
1114 pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
1115#ifdef VBOX_WITH_MULTI_CORE
1116 if ( pCPUM->enmGuestCpuVendor != CPUMCPUVENDOR_SYNTHETIC
1117 && pVM->cCpus > 1)
1118 {
1119 /* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU core times the number of CPU cores per processor */
1120 pCPUM->aGuestCpuIdStd[1].ebx |= (pVM->cCpus << 16);
1121 pCPUM->aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading *or* multi-core CPUs */
1122 }
1123#endif
1124
1125 /* Cpuid 2:
1126 * Intel: Cache and TLB information
1127 * AMD: Reserved
1128 * VIA: Reserved
1129 * Safe to expose; restrict the number of calls to 1 for the portable case.
1130 */
1131 if ( pCPUM->u8PortableCpuIdLevel > 0
1132 && pCPUM->aGuestCpuIdStd[0].eax >= 2
1133 && (pCPUM->aGuestCpuIdStd[2].eax & 0xff) > 1)
1134 {
1135 LogRel(("PortableCpuId: Std[2].al: %d -> 1\n", pCPUM->aGuestCpuIdStd[2].eax & 0xff));
1136 pCPUM->aGuestCpuIdStd[2].eax &= UINT32_C(0xfffffffe);
1137 }
1138
1139 /* Cpuid 3:
1140 * Intel: EAX, EBX - reserved (transmeta uses these)
1141 * ECX, EDX - Processor Serial Number if available, otherwise reserved
1142 * AMD: Reserved
1143 * VIA: Reserved
1144 * Safe to expose
1145 */
1146 if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
1147 {
1148 pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
1149 if (pCPUM->u8PortableCpuIdLevel > 0)
1150 pCPUM->aGuestCpuIdStd[3].eax = pCPUM->aGuestCpuIdStd[3].ebx = 0;
1151 }
1152
1153 /* Cpuid 4:
1154 * Intel: Deterministic Cache Parameters Leaf
1155 * Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
1156 * AMD: Reserved
1157 * VIA: Reserved
1158 * Safe to expose, except for EAX:
1159 * Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
1160 * Bits 31-26: Maximum number of processor cores in this physical package**
1161 * Note: These SMP values are constant regardless of ECX
1162 */
1163 pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
1164 pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
1165#ifdef VBOX_WITH_MULTI_CORE
1166 if ( pVM->cCpus > 1
1167 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
1168 {
1169 AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
1170 /* One logical processor with possibly multiple cores. */
1171 /* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
1172 pCPUM->aGuestCpuIdStd[4].eax |= ((pVM->cCpus - 1) << 26); /* 6 bits only -> 64 cores! */
1173 }
1174#endif
1175
1176 /* Cpuid 5: Monitor/mwait Leaf
1177 * Intel: ECX, EDX - reserved
1178 * EAX, EBX - Smallest and largest monitor line size
1179 * AMD: EDX - reserved
1180 * EAX, EBX - Smallest and largest monitor line size
1181 * ECX - extensions (ignored for now)
1182 * VIA: Reserved
1183 * Safe to expose
1184 */
1185 if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
1186 pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
1187
1188 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
1189 /** @cfgm{/CPUM/MWaitExtensions, boolean, false}
1190 * Expose MWAIT extended features to the guest. For now we expose
1191 * just MWAIT break on interrupt feature (bit 1).
1192 */
1193 bool fMWaitExtensions;
1194 rc = CFGMR3QueryBoolDef(pCpumCfg, "MWaitExtensions", &fMWaitExtensions, false); AssertRCReturn(rc, rc);
1195 if (fMWaitExtensions)
1196 {
1197 pCPUM->aGuestCpuIdStd[5].ecx = X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
1198 /* @todo: for now we just expose host's MWAIT C-states, although conceptually
1199 it shall be part of our power management virtualization model */
1200#if 0
1201 /* MWAIT sub C-states */
1202 pCPUM->aGuestCpuIdStd[5].edx =
1203 (0 << 0) /* 0 in C0 */ |
1204 (2 << 4) /* 2 in C1 */ |
1205 (2 << 8) /* 2 in C2 */ |
1206 (2 << 12) /* 2 in C3 */ |
1207 (0 << 16) /* 0 in C4 */
1208 ;
1209#endif
1210 }
1211 else
1212 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
1213
1214 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
1215 * Safe to pass on to the guest.
1216 *
1217 * Intel: 0x800000005 reserved
1218 * 0x800000006 L2 cache information
1219 * AMD: 0x800000005 L1 cache information
1220 * 0x800000006 L2/L3 cache information
1221 * VIA: 0x800000005 TLB and L1 cache information
1222 * 0x800000006 L2 cache information
1223 */
1224
1225 /* Cpuid 0x800000007:
1226 * Intel: Reserved
1227 * AMD: EAX, EBX, ECX - reserved
1228 * EDX: Advanced Power Management Information
1229 * VIA: Reserved
1230 */
1231 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
1232 {
1233 Assert(pVM->cpum.s.enmGuestCpuVendor != CPUMCPUVENDOR_INVALID);
1234
1235 pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
1236
1237 if (pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1238 {
1239 /* Only expose the TSC invariant capability bit to the guest. */
1240 pCPUM->aGuestCpuIdExt[7].edx &= 0
1241 //| X86_CPUID_AMD_ADVPOWER_EDX_TS
1242 //| X86_CPUID_AMD_ADVPOWER_EDX_FID
1243 //| X86_CPUID_AMD_ADVPOWER_EDX_VID
1244 //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
1245 //| X86_CPUID_AMD_ADVPOWER_EDX_TM
1246 //| X86_CPUID_AMD_ADVPOWER_EDX_STC
1247 //| X86_CPUID_AMD_ADVPOWER_EDX_MC
1248 //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
1249#if 0
1250 /*
1251 * We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer
1252 * Linux kernels blindly assume that the AMD performance counters work
1253 * if this is set for 64 bits guests. (Can't really find a CPUID feature
1254 * bit for them though.)
1255 */
1256 | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
1257#endif
1258 | 0;
1259 }
1260 else
1261 pCPUM->aGuestCpuIdExt[7].edx = 0;
1262 }
1263
1264 /* Cpuid 0x800000008:
1265 * Intel: EAX: Virtual/Physical address Size
1266 * EBX, ECX, EDX - reserved
1267 * AMD: EBX, EDX - reserved
1268 * EAX: Virtual/Physical/Guest address Size
1269 * ECX: Number of cores + APICIdCoreIdSize
1270 * VIA: EAX: Virtual/Physical address Size
1271 * EBX, ECX, EDX - reserved
1272 */
1273 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
1274 {
1275 /* Only expose the virtual and physical address sizes to the guest. */
1276 pCPUM->aGuestCpuIdExt[8].eax &= UINT32_C(0x0000ffff);
1277 pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
1278 /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
1279 * NC (0-7) Number of cores; 0 equals 1 core */
1280 pCPUM->aGuestCpuIdExt[8].ecx = 0;
1281#ifdef VBOX_WITH_MULTI_CORE
1282 if ( pVM->cCpus > 1
1283 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1284 {
1285 /* Legacy method to determine the number of cores. */
1286 pCPUM->aGuestCpuIdExt[1].ecx |= X86_CPUID_AMD_FEATURE_ECX_CMPL;
1287 pCPUM->aGuestCpuIdExt[8].ecx |= (pVM->cCpus - 1); /* NC: Number of CPU cores - 1; 8 bits */
1288 }
1289#endif
1290 }
1291
1292 /** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
1293 * Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
1294 * bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
1295 * This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
1296 */
1297 bool fNt4LeafLimit;
1298 rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &fNt4LeafLimit, false); AssertRCReturn(rc, rc);
1299 if (fNt4LeafLimit)
1300 pCPUM->aGuestCpuIdStd[0].eax = 3; /** @todo r=bird: shouldn't we check if pCPUM->aGuestCpuIdStd[0].eax > 3 before setting it 3 here? */
1301
1302 /*
1303 * Limit it the number of entries and fill the remaining with the defaults.
1304 *
1305 * The limits are masking off stuff about power saving and similar, this
1306 * is perhaps a bit crudely done as there is probably some relatively harmless
1307 * info too in these leaves (like words about having a constant TSC).
1308 */
1309 if (pCPUM->aGuestCpuIdStd[0].eax > 5)
1310 pCPUM->aGuestCpuIdStd[0].eax = 5;
1311 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
1312 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
1313
1314 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
1315 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
1316 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
1317 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
1318 : 0;
1319 i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
1320 i++)
1321 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
1322
1323 /*
1324 * Centaur stuff (VIA).
1325 *
1326 * The important part here (we think) is to make sure the 0xc0000000
1327 * function returns 0xc0000001. As for the features, we don't currently
1328 * let on about any of those... 0xc0000002 seems to be some
1329 * temperature/hz/++ stuff, include it as well (static).
1330 */
1331 if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
1332 && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
1333 {
1334 pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
1335 pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
1336 for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
1337 i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
1338 i++)
1339 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
1340 }
1341 else
1342 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
1343 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
1344
1345 /*
1346 * Hypervisor identification.
1347 *
1348 * We only return minimal information, primarily ensuring that the
1349 * 0x40000000 function returns 0x40000001 and identifying ourselves.
1350 * Currently we do not support any hypervisor-specific interface.
1351 */
1352 pCPUM->aGuestCpuIdHyper[0].eax = UINT32_C(0x40000001);
1353 pCPUM->aGuestCpuIdHyper[0].ebx = pCPUM->aGuestCpuIdHyper[0].ecx
1354 = pCPUM->aGuestCpuIdHyper[0].edx = 0x786f4256; /* 'VBox' */
1355 pCPUM->aGuestCpuIdHyper[1].eax = 0x656e6f6e; /* 'none' */
1356 pCPUM->aGuestCpuIdHyper[1].ebx = pCPUM->aGuestCpuIdHyper[1].ecx
1357 = pCPUM->aGuestCpuIdHyper[1].edx = 0; /* Reserved */
1358
1359 /*
1360 * Load CPUID overrides from configuration.
1361 * Note: Kind of redundant now, but allows unchanged overrides
1362 */
1363 /** @cfgm{CPUM/CPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
1364 * Overrides the CPUID leaf values. */
1365 PCFGMNODE pOverrideCfg = CFGMR3GetChild(pCpumCfg, "CPUID");
1366 rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pOverrideCfg);
1367 AssertRCReturn(rc, rc);
1368 rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pOverrideCfg);
1369 AssertRCReturn(rc, rc);
1370 rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pOverrideCfg);
1371 AssertRCReturn(rc, rc);
1372
1373 /*
1374 * Check if PAE was explicitely enabled by the user.
1375 */
1376 bool fEnable;
1377 rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false); AssertRCReturn(rc, rc);
1378 if (fEnable)
1379 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1380
1381 /*
1382 * We don't normally enable NX for raw-mode, so give the user a chance to
1383 * force it on.
1384 */
1385 rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false); AssertRCReturn(rc, rc);
1386 if (fEnable)
1387 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1388
1389 /*
1390 * We don't enable the Hypervisor Present bit by default, but it may
1391 * be needed by some guests.
1392 */
1393 rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableHVP", &fEnable, false); AssertRCReturn(rc, rc);
1394 if (fEnable)
1395 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_HVP);
1396
1397#undef PORTABLE_DISABLE_FEATURE_BIT
1398#undef PORTABLE_CLEAR_BITS_WHEN
1399
1400 return VINF_SUCCESS;
1401}
1402
1403
1404/**
1405 * Applies relocations to data and code managed by this
1406 * component. This function will be called at init and
1407 * whenever the VMM need to relocate it self inside the GC.
1408 *
1409 * The CPUM will update the addresses used by the switcher.
1410 *
1411 * @param pVM The VM.
1412 */
1413VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
1414{
1415 LogFlow(("CPUMR3Relocate\n"));
1416 /* nothing to do any more. */
1417}
1418
1419
1420/**
1421 * Apply late CPUM property changes based on the fHWVirtEx setting
1422 *
1423 * @param pVM Pointer to the VM.
1424 * @param fHWVirtExEnabled HWVirtEx enabled/disabled
1425 */
1426VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled)
1427{
1428 /*
1429 * Workaround for missing cpuid(0) patches when leaf 4 returns GuestCpuIdDef:
1430 * If we miss to patch a cpuid(0).eax then Linux tries to determine the number
1431 * of processors from (cpuid(4).eax >> 26) + 1.
1432 *
1433 * Note: this code is obsolete, but let's keep it here for reference.
1434 * Purpose is valid when we artificially cap the max std id to less than 4.
1435 */
1436 if (!fHWVirtExEnabled)
1437 {
1438 Assert( pVM->cpum.s.aGuestCpuIdStd[4].eax == 0
1439 || pVM->cpum.s.aGuestCpuIdStd[0].eax < 0x4);
1440 pVM->cpum.s.aGuestCpuIdStd[4].eax = 0;
1441 }
1442}
1443
1444/**
1445 * Terminates the CPUM.
1446 *
1447 * Termination means cleaning up and freeing all resources,
1448 * the VM it self is at this point powered off or suspended.
1449 *
1450 * @returns VBox status code.
1451 * @param pVM Pointer to the VM.
1452 */
1453VMMR3DECL(int) CPUMR3Term(PVM pVM)
1454{
1455#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1456 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1457 {
1458 PVMCPU pVCpu = &pVM->aCpus[i];
1459 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1460
1461 memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
1462 pVCpu->cpum.s.uMagic = 0;
1463 pCtx->dr[5] = 0;
1464 }
1465#else
1466 NOREF(pVM);
1467#endif
1468 return VINF_SUCCESS;
1469}
1470
1471
1472/**
1473 * Resets a virtual CPU.
1474 *
1475 * Used by CPUMR3Reset and CPU hot plugging.
1476 *
1477 * @param pVCpu Pointer to the VMCPU.
1478 */
1479VMMR3DECL(void) CPUMR3ResetCpu(PVMCPU pVCpu)
1480{
1481 /** @todo anything different for VCPU > 0? */
1482 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1483
1484 /*
1485 * Initialize everything to ZERO first.
1486 */
1487 uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
1488 memset(pCtx, 0, sizeof(*pCtx));
1489 pVCpu->cpum.s.fUseFlags = fUseFlags;
1490
1491 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
1492 pCtx->eip = 0x0000fff0;
1493 pCtx->edx = 0x00000600; /* P6 processor */
1494 pCtx->eflags.Bits.u1Reserved0 = 1;
1495
1496 pCtx->cs.Sel = 0xf000;
1497 pCtx->cs.ValidSel = 0xf000;
1498 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
1499 pCtx->cs.u64Base = UINT64_C(0xffff0000);
1500 pCtx->cs.u32Limit = 0x0000ffff;
1501 pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
1502 pCtx->cs.Attr.n.u1Present = 1;
1503 pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
1504
1505 pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
1506 pCtx->ds.u32Limit = 0x0000ffff;
1507 pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
1508 pCtx->ds.Attr.n.u1Present = 1;
1509 pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1510
1511 pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
1512 pCtx->es.u32Limit = 0x0000ffff;
1513 pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
1514 pCtx->es.Attr.n.u1Present = 1;
1515 pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1516
1517 pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
1518 pCtx->fs.u32Limit = 0x0000ffff;
1519 pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
1520 pCtx->fs.Attr.n.u1Present = 1;
1521 pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1522
1523 pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
1524 pCtx->gs.u32Limit = 0x0000ffff;
1525 pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
1526 pCtx->gs.Attr.n.u1Present = 1;
1527 pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1528
1529 pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
1530 pCtx->ss.u32Limit = 0x0000ffff;
1531 pCtx->ss.Attr.n.u1Present = 1;
1532 pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
1533 pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1534
1535 pCtx->idtr.cbIdt = 0xffff;
1536 pCtx->gdtr.cbGdt = 0xffff;
1537
1538 pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1539 pCtx->ldtr.u32Limit = 0xffff;
1540 pCtx->ldtr.Attr.n.u1Present = 1;
1541 pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
1542
1543 pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
1544 pCtx->tr.u32Limit = 0xffff;
1545 pCtx->tr.Attr.n.u1Present = 1;
1546 pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
1547
1548 pCtx->dr[6] = X86_DR6_INIT_VAL;
1549 pCtx->dr[7] = X86_DR7_INIT_VAL;
1550
1551 pCtx->fpu.FTW = 0x00; /* All empty (abbridged tag reg edition). */
1552 pCtx->fpu.FCW = 0x37f;
1553
1554 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
1555 IA-32 Processor States Following Power-up, Reset, or INIT */
1556 pCtx->fpu.MXCSR = 0x1F80;
1557 pCtx->fpu.MXCSR_MASK = 0xffff; /** @todo REM always changed this for us. Should probably check if the HW really
1558 supports all bits, since a zero value here should be read as 0xffbf. */
1559
1560 /* Init PAT MSR */
1561 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
1562
1563 /* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
1564 * The Intel docs don't mention it.
1565 */
1566 pCtx->msrEFER = 0;
1567
1568 /*
1569 * Get the APIC base MSR from the APIC device. For historical reasons (saved state), the APIC base
1570 * continues to reside in the APIC device and we cache it here in the VCPU for all further accesses.
1571 */
1572 PDMApicGetBase(pVCpu, &pCtx->msrApicBase);
1573}
1574
1575
1576/**
1577 * Resets the CPU.
1578 *
1579 * @returns VINF_SUCCESS.
1580 * @param pVM Pointer to the VM.
1581 */
1582VMMR3DECL(void) CPUMR3Reset(PVM pVM)
1583{
1584 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1585 {
1586 CPUMR3ResetCpu(&pVM->aCpus[i]);
1587
1588#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1589 PCPUMCTX pCtx = &pVM->aCpus[i].cpum.s.Guest;
1590
1591 /* Magic marker for searching in crash dumps. */
1592 strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
1593 pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1594 pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
1595#endif
1596 }
1597}
1598
1599
1600/**
1601 * Called both in pass 0 and the final pass.
1602 *
1603 * @param pVM Pointer to the VM.
1604 * @param pSSM The saved state handle.
1605 */
1606static void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
1607{
1608 /*
1609 * Save all the CPU ID leaves here so we can check them for compatibility
1610 * upon loading.
1611 */
1612 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
1613 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
1614
1615 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
1616 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1617
1618 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
1619 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1620
1621 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1622
1623 /*
1624 * Save a good portion of the raw CPU IDs as well as they may come in
1625 * handy when validating features for raw mode.
1626 */
1627 CPUMCPUID aRawStd[16];
1628 for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
1629 ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1630 SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
1631 SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
1632
1633 CPUMCPUID aRawExt[32];
1634 for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
1635 ASMCpuId(i | UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1636 SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
1637 SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
1638}
1639
1640
1641/**
1642 * Loads the CPU ID leaves saved by pass 0.
1643 *
1644 * @returns VBox status code.
1645 * @param pVM Pointer to the VM.
1646 * @param pSSM The saved state handle.
1647 * @param uVersion The format version.
1648 */
1649static int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
1650{
1651 AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
1652
1653 /*
1654 * Define a bunch of macros for simplifying the code.
1655 */
1656 /* Generic expression + failure message. */
1657#define CPUID_CHECK_RET(expr, fmt) \
1658 do { \
1659 if (!(expr)) \
1660 { \
1661 char *pszMsg = RTStrAPrintf2 fmt; /* lack of variadic macros sucks */ \
1662 if (fStrictCpuIdChecks) \
1663 { \
1664 int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
1665 RTStrFree(pszMsg); \
1666 return rcCpuid; \
1667 } \
1668 LogRel(("CPUM: %s\n", pszMsg)); \
1669 RTStrFree(pszMsg); \
1670 } \
1671 } while (0)
1672#define CPUID_CHECK_WRN(expr, fmt) \
1673 do { \
1674 if (!(expr)) \
1675 LogRel(fmt); \
1676 } while (0)
1677
1678 /* For comparing two values and bitch if they differs. */
1679#define CPUID_CHECK2_RET(what, host, saved) \
1680 do { \
1681 if ((host) != (saved)) \
1682 { \
1683 if (fStrictCpuIdChecks) \
1684 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1685 N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
1686 LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1687 } \
1688 } while (0)
1689#define CPUID_CHECK2_WRN(what, host, saved) \
1690 do { \
1691 if ((host) != (saved)) \
1692 LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1693 } while (0)
1694
1695 /* For checking raw cpu features (raw mode). */
1696#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
1697 do { \
1698 if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1699 { \
1700 if (fStrictCpuIdChecks) \
1701 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1702 N_(#bit " mismatch: host=%d saved=%d"), \
1703 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
1704 LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1705 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1706 } \
1707 } while (0)
1708#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
1709 do { \
1710 if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1711 LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1712 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1713 } while (0)
1714#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
1715
1716 /* For checking guest features. */
1717#define CPUID_GST_FEATURE_RET(set, reg, bit) \
1718 do { \
1719 if ( (aGuestCpuId##set [1].reg & bit) \
1720 && !(aHostRaw##set [1].reg & bit) \
1721 && !(aHostOverride##set [1].reg & bit) \
1722 && !(aGuestOverride##set [1].reg & bit) \
1723 ) \
1724 { \
1725 if (fStrictCpuIdChecks) \
1726 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1727 N_(#bit " is not supported by the host but has already exposed to the guest")); \
1728 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1729 } \
1730 } while (0)
1731#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
1732 do { \
1733 if ( (aGuestCpuId##set [1].reg & bit) \
1734 && !(aHostRaw##set [1].reg & bit) \
1735 && !(aHostOverride##set [1].reg & bit) \
1736 && !(aGuestOverride##set [1].reg & bit) \
1737 ) \
1738 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1739 } while (0)
1740#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
1741 do { \
1742 if ( (aGuestCpuId##set [1].reg & bit) \
1743 && !(aHostRaw##set [1].reg & bit) \
1744 && !(aHostOverride##set [1].reg & bit) \
1745 && !(aGuestOverride##set [1].reg & bit) \
1746 ) \
1747 LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1748 } while (0)
1749#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
1750
1751 /* For checking guest features if AMD guest CPU. */
1752#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
1753 do { \
1754 if ( (aGuestCpuId##set [1].reg & bit) \
1755 && fGuestAmd \
1756 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
1757 && !(aHostOverride##set [1].reg & bit) \
1758 && !(aGuestOverride##set [1].reg & bit) \
1759 ) \
1760 { \
1761 if (fStrictCpuIdChecks) \
1762 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1763 N_(#bit " is not supported by the host but has already exposed to the guest")); \
1764 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1765 } \
1766 } while (0)
1767#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
1768 do { \
1769 if ( (aGuestCpuId##set [1].reg & bit) \
1770 && fGuestAmd \
1771 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
1772 && !(aHostOverride##set [1].reg & bit) \
1773 && !(aGuestOverride##set [1].reg & bit) \
1774 ) \
1775 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1776 } while (0)
1777#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
1778 do { \
1779 if ( (aGuestCpuId##set [1].reg & bit) \
1780 && fGuestAmd \
1781 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
1782 && !(aHostOverride##set [1].reg & bit) \
1783 && !(aGuestOverride##set [1].reg & bit) \
1784 ) \
1785 LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1786 } while (0)
1787#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
1788
1789 /* For checking AMD features which have a corresponding bit in the standard
1790 range. (Intel defines very few bits in the extended feature sets.) */
1791#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
1792 do { \
1793 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1794 && !(fHostAmd \
1795 ? aHostRawExt[1].reg & (ExtBit) \
1796 : aHostRawStd[1].reg & (StdBit)) \
1797 && !(aHostOverrideExt[1].reg & (ExtBit)) \
1798 && !(aGuestOverrideExt[1].reg & (ExtBit)) \
1799 ) \
1800 { \
1801 if (fStrictCpuIdChecks) \
1802 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1803 N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
1804 LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1805 } \
1806 } while (0)
1807#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
1808 do { \
1809 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1810 && !(fHostAmd \
1811 ? aHostRawExt[1].reg & (ExtBit) \
1812 : aHostRawStd[1].reg & (StdBit)) \
1813 && !(aHostOverrideExt[1].reg & (ExtBit)) \
1814 && !(aGuestOverrideExt[1].reg & (ExtBit)) \
1815 ) \
1816 LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1817 } while (0)
1818#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
1819 do { \
1820 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1821 && !(fHostAmd \
1822 ? aHostRawExt[1].reg & (ExtBit) \
1823 : aHostRawStd[1].reg & (StdBit)) \
1824 && !(aHostOverrideExt[1].reg & (ExtBit)) \
1825 && !(aGuestOverrideExt[1].reg & (ExtBit)) \
1826 ) \
1827 LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1828 } while (0)
1829#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
1830
1831 /*
1832 * Load them into stack buffers first.
1833 */
1834 CPUMCPUID aGuestCpuIdStd[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd)];
1835 uint32_t cGuestCpuIdStd;
1836 int rc = SSMR3GetU32(pSSM, &cGuestCpuIdStd); AssertRCReturn(rc, rc);
1837 if (cGuestCpuIdStd > RT_ELEMENTS(aGuestCpuIdStd))
1838 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1839 SSMR3GetMem(pSSM, &aGuestCpuIdStd[0], cGuestCpuIdStd * sizeof(aGuestCpuIdStd[0]));
1840
1841 CPUMCPUID aGuestCpuIdExt[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt)];
1842 uint32_t cGuestCpuIdExt;
1843 rc = SSMR3GetU32(pSSM, &cGuestCpuIdExt); AssertRCReturn(rc, rc);
1844 if (cGuestCpuIdExt > RT_ELEMENTS(aGuestCpuIdExt))
1845 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1846 SSMR3GetMem(pSSM, &aGuestCpuIdExt[0], cGuestCpuIdExt * sizeof(aGuestCpuIdExt[0]));
1847
1848 CPUMCPUID aGuestCpuIdCentaur[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur)];
1849 uint32_t cGuestCpuIdCentaur;
1850 rc = SSMR3GetU32(pSSM, &cGuestCpuIdCentaur); AssertRCReturn(rc, rc);
1851 if (cGuestCpuIdCentaur > RT_ELEMENTS(aGuestCpuIdCentaur))
1852 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1853 SSMR3GetMem(pSSM, &aGuestCpuIdCentaur[0], cGuestCpuIdCentaur * sizeof(aGuestCpuIdCentaur[0]));
1854
1855 CPUMCPUID GuestCpuIdDef;
1856 rc = SSMR3GetMem(pSSM, &GuestCpuIdDef, sizeof(GuestCpuIdDef));
1857 AssertRCReturn(rc, rc);
1858
1859 CPUMCPUID aRawStd[16];
1860 uint32_t cRawStd;
1861 rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
1862 if (cRawStd > RT_ELEMENTS(aRawStd))
1863 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1864 SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
1865
1866 CPUMCPUID aRawExt[32];
1867 uint32_t cRawExt;
1868 rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
1869 if (cRawExt > RT_ELEMENTS(aRawExt))
1870 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1871 rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
1872 AssertRCReturn(rc, rc);
1873
1874 /*
1875 * Note that we support restoring less than the current amount of standard
1876 * leaves because we've been allowed more is newer version of VBox.
1877 *
1878 * So, pad new entries with the default.
1879 */
1880 for (uint32_t i = cGuestCpuIdStd; i < RT_ELEMENTS(aGuestCpuIdStd); i++)
1881 aGuestCpuIdStd[i] = GuestCpuIdDef;
1882
1883 for (uint32_t i = cGuestCpuIdExt; i < RT_ELEMENTS(aGuestCpuIdExt); i++)
1884 aGuestCpuIdExt[i] = GuestCpuIdDef;
1885
1886 for (uint32_t i = cGuestCpuIdCentaur; i < RT_ELEMENTS(aGuestCpuIdCentaur); i++)
1887 aGuestCpuIdCentaur[i] = GuestCpuIdDef;
1888
1889 for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
1890 ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1891
1892 for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
1893 ASMCpuId(i | UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1894
1895 /*
1896 * Get the raw CPU IDs for the current host.
1897 */
1898 CPUMCPUID aHostRawStd[16];
1899 for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
1900 ASMCpuId(i, &aHostRawStd[i].eax, &aHostRawStd[i].ebx, &aHostRawStd[i].ecx, &aHostRawStd[i].edx);
1901
1902 CPUMCPUID aHostRawExt[32];
1903 for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
1904 ASMCpuId(i | UINT32_C(0x80000000), &aHostRawExt[i].eax, &aHostRawExt[i].ebx, &aHostRawExt[i].ecx, &aHostRawExt[i].edx);
1905
1906 /*
1907 * Get the host and guest overrides so we don't reject the state because
1908 * some feature was enabled thru these interfaces.
1909 * Note! We currently only need the feature leaves, so skip rest.
1910 */
1911 PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/CPUID");
1912 CPUMCPUID aGuestOverrideStd[2];
1913 memcpy(&aGuestOverrideStd[0], &aHostRawStd[0], sizeof(aGuestOverrideStd));
1914 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aGuestOverrideStd[0], RT_ELEMENTS(aGuestOverrideStd), pOverrideCfg);
1915
1916 CPUMCPUID aGuestOverrideExt[2];
1917 memcpy(&aGuestOverrideExt[0], &aHostRawExt[0], sizeof(aGuestOverrideExt));
1918 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aGuestOverrideExt[0], RT_ELEMENTS(aGuestOverrideExt), pOverrideCfg);
1919
1920 pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
1921 CPUMCPUID aHostOverrideStd[2];
1922 memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
1923 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
1924
1925 CPUMCPUID aHostOverrideExt[2];
1926 memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
1927 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
1928
1929 /*
1930 * This can be skipped.
1931 */
1932 bool fStrictCpuIdChecks;
1933 CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
1934
1935
1936
1937 /*
1938 * For raw-mode we'll require that the CPUs are very similar since we don't
1939 * intercept CPUID instructions for user mode applications.
1940 */
1941 if (!HMIsEnabled(pVM))
1942 {
1943 /* CPUID(0) */
1944 CPUID_CHECK_RET( aHostRawStd[0].ebx == aRawStd[0].ebx
1945 && aHostRawStd[0].ecx == aRawStd[0].ecx
1946 && aHostRawStd[0].edx == aRawStd[0].edx,
1947 (N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
1948 &aHostRawStd[0].ebx, &aHostRawStd[0].edx, &aHostRawStd[0].ecx,
1949 &aRawStd[0].ebx, &aRawStd[0].edx, &aRawStd[0].ecx));
1950 CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].eax, aRawStd[0].eax);
1951 CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3);
1952 CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
1953
1954 bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].ebx, aRawStd[0].ecx, aRawStd[0].edx);
1955
1956 /* CPUID(1).eax */
1957 CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].eax), ASMGetCpuFamily(aRawStd[1].eax));
1958 CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].eax, fIntel), ASMGetCpuModel(aRawStd[1].eax, fIntel));
1959 CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].eax >> 12) & 3, (aRawStd[1].eax >> 12) & 3 );
1960
1961 /* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
1962 CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].ebx & 0xff, aRawStd[1].ebx & 0xff);
1963 CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].ebx >> 8) & 0xff, (aRawStd[1].ebx >> 8) & 0xff);
1964
1965 /* CPUID(1).ecx */
1966 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3);
1967 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL);
1968 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64);
1969 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
1970 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS);
1971 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_VMX);
1972 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_SMX);
1973 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_EST);
1974 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TM2);
1975 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3);
1976 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID);
1977 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(11) /*reserved*/ );
1978 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA);
1979 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16);
1980 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
1981 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM);
1982 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(16) /*reserved*/);
1983 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(17) /*reserved*/);
1984 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DCA);
1985 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1);
1986 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2);
1987 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
1988 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE);
1989 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT);
1990 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(24) /*reserved*/);
1991 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES);
1992 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE);
1993 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE);
1994 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX);
1995 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(29) /*reserved*/);
1996 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(30) /*reserved*/);
1997 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_HVP);
1998
1999 /* CPUID(1).edx */
2000 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
2001 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
2002 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE);
2003 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
2004 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC);
2005 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR);
2006 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
2007 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
2008 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8);
2009 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
2010 CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(10) /*reserved*/);
2011 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
2012 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
2013 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
2014 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
2015 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV);
2016 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
2017 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
2018 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
2019 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH);
2020 CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(20) /*reserved*/);
2021 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_DS);
2022 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_ACPI);
2023 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX);
2024 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR);
2025 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE);
2026 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2);
2027 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SS);
2028 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_HTT);
2029 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_TM);
2030 CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(30) /*JMPE/IA64*/);
2031 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PBE);
2032
2033 /* CPUID(2) - config, mostly about caches. ignore. */
2034 /* CPUID(3) - processor serial number. ignore. */
2035 /* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
2036 /* CPUID(5) - mwait/monitor config. ignore. */
2037 /* CPUID(6) - power management. ignore. */
2038 /* CPUID(7) - ???. ignore. */
2039 /* CPUID(8) - ???. ignore. */
2040 /* CPUID(9) - DCA. ignore for now. */
2041 /* CPUID(a) - PeMo info. ignore for now. */
2042 /* CPUID(b) - topology info - takes ECX as input. ignore. */
2043
2044 /* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
2045 CPUID_CHECK_WRN( aRawStd[0].eax < UINT32_C(0x0000000d)
2046 || aHostRawStd[0].eax >= UINT32_C(0x0000000d),
2047 ("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
2048 if ( aRawStd[0].eax >= UINT32_C(0x0000000d)
2049 && aHostRawStd[0].eax >= UINT32_C(0x0000000d))
2050 {
2051 CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].eax, aRawStd[0xd].eax);
2052 CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].edx, aRawStd[0xd].edx);
2053 CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].ebx, aRawStd[0xd].ebx);
2054 CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].ecx, aRawStd[0xd].ecx);
2055 }
2056
2057 /* CPUID(0x80000000) - same as CPUID(0) except for eax.
2058 Note! Intel have/is marking many of the fields here as reserved. We
2059 will verify them as if it's an AMD CPU. */
2060 CPUID_CHECK_RET( (aHostRawExt[0].eax >= UINT32_C(0x80000001) && aHostRawExt[0].eax <= UINT32_C(0x8000007f))
2061 || !(aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f)),
2062 (N_("Extended leaves was present on saved state host, but is missing on the current\n")));
2063 if (aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f))
2064 {
2065 CPUID_CHECK_RET( aHostRawExt[0].ebx == aRawExt[0].ebx
2066 && aHostRawExt[0].ecx == aRawExt[0].ecx
2067 && aHostRawExt[0].edx == aRawExt[0].edx,
2068 (N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
2069 &aHostRawExt[0].ebx, &aHostRawExt[0].edx, &aHostRawExt[0].ecx,
2070 &aRawExt[0].ebx, &aRawExt[0].edx, &aRawExt[0].ecx));
2071 CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].eax, aRawExt[0].eax);
2072
2073 /* CPUID(0x80000001).eax - same as CPUID(0).eax. */
2074 CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].eax), ASMGetCpuFamily(aRawExt[1].eax));
2075 CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].eax, fIntel), ASMGetCpuModel(aRawExt[1].eax, fIntel));
2076 CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].eax >> 12) & 3, (aRawExt[1].eax >> 12) & 3 );
2077 CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3 );
2078 CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
2079
2080 /* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
2081 CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].ebx & 0xffff, aRawExt[1].ebx & 0xffff);
2082 CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].ebx >> 16) & 0xfff, (aRawExt[1].ebx >> 16) & 0xfff);
2083 CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].ebx >> 28) & 0xf, (aRawExt[1].ebx >> 28) & 0xf);
2084
2085 /* CPUID(0x80000001).ecx */
2086 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
2087 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
2088 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM);
2089 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
2090 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
2091 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM);
2092 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
2093 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
2094 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
2095 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
2096 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS);
2097 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5);
2098 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
2099 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT);
2100 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
2101 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
2102 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
2103 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
2104 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
2105 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
2106 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
2107 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
2108 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
2109 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
2110 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
2111 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
2112 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
2113 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
2114 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
2115 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
2116 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
2117 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
2118
2119 /* CPUID(0x80000001).edx */
2120 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FPU);
2121 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_VME);
2122 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_DE);
2123 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE);
2124 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_TSC);
2125 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MSR);
2126 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAE);
2127 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCE);
2128 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CX8);
2129 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_APIC);
2130 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(10) /*reserved*/);
2131 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_SEP);
2132 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
2133 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PGE);
2134 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCA);
2135 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
2136 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAT);
2137 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
2138 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(18) /*reserved*/);
2139 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(19) /*reserved*/);
2140 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_NX);
2141 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(21) /*reserved*/);
2142 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
2143 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MMX);
2144 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
2145 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2146 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
2147 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2148 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(28) /*reserved*/);
2149 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
2150 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2151 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2152
2153 /** @todo verify the rest as well. */
2154 }
2155 }
2156
2157
2158
2159 /*
2160 * Verify that we can support the features already exposed to the guest on
2161 * this host.
2162 *
2163 * Most of the features we're emulating requires intercepting instruction
2164 * and doing it the slow way, so there is no need to warn when they aren't
2165 * present in the host CPU. Thus we use IGN instead of EMU on these.
2166 *
2167 * Trailing comments:
2168 * "EMU" - Possible to emulate, could be lots of work and very slow.
2169 * "EMU?" - Can this be emulated?
2170 */
2171 /* CPUID(1).ecx */
2172 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
2173 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
2174 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
2175 CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
2176 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
2177 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
2178 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
2179 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
2180 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
2181 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
2182 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
2183 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(11) /*reserved*/ );
2184 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
2185 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
2186 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
2187 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
2188 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(16) /*reserved*/);
2189 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(17) /*reserved*/);
2190 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
2191 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
2192 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
2193 CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
2194 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
2195 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
2196 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(24) /*reserved*/);
2197 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
2198 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
2199 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE); // -> EMU
2200 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
2201 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(29) /*reserved*/);
2202 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(30) /*reserved*/);
2203 CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
2204
2205 /* CPUID(1).edx */
2206 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
2207 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
2208 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
2209 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
2210 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
2211 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
2212 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
2213 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
2214 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
2215 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
2216 CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(10) /*reserved*/);
2217 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
2218 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
2219 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
2220 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
2221 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
2222 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
2223 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
2224 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
2225 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
2226 CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(20) /*reserved*/);
2227 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
2228 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
2229 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
2230 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
2231 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
2232 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
2233 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
2234 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
2235 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
2236 CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(30) /*JMPE/IA64*/); // -> EMU
2237 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
2238
2239 /* CPUID(0x80000000). */
2240 if ( aGuestCpuIdExt[0].eax >= UINT32_C(0x80000001)
2241 && aGuestCpuIdExt[0].eax < UINT32_C(0x8000007f))
2242 {
2243 /** @todo deal with no 0x80000001 on the host. */
2244 bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].ebx, aHostRawStd[0].ecx, aHostRawStd[0].edx);
2245 bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].ebx, aGuestCpuIdExt[0].ecx, aGuestCpuIdExt[0].edx);
2246
2247 /* CPUID(0x80000001).ecx */
2248 CPUID_GST_FEATURE_WRN(Ext, ecx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
2249 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
2250 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
2251 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
2252 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
2253 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
2254 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
2255 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
2256 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
2257 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
2258 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
2259 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5); // -> EMU
2260 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
2261 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
2262 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
2263 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
2264 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
2265 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
2266 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
2267 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
2268 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
2269 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
2270 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
2271 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
2272 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
2273 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
2274 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
2275 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
2276 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
2277 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
2278 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
2279 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
2280
2281 /* CPUID(0x80000001).edx */
2282 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
2283 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
2284 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
2285 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
2286 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
2287 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
2288 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
2289 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
2290 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
2291 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
2292 CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(10) /*reserved*/);
2293 CPUID_GST_FEATURE_IGN( Ext, edx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
2294 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
2295 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
2296 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
2297 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
2298 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
2299 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
2300 CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(18) /*reserved*/);
2301 CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(19) /*reserved*/);
2302 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_EXT_FEATURE_EDX_NX);
2303 CPUID_GST_FEATURE_WRN( Ext, edx, RT_BIT_32(21) /*reserved*/);
2304 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
2305 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
2306 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
2307 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2308 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
2309 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2310 CPUID_GST_FEATURE_IGN( Ext, edx, RT_BIT_32(28) /*reserved*/);
2311 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
2312 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2313 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2314 }
2315
2316 /*
2317 * We're good, commit the CPU ID leaves.
2318 */
2319 memcpy(&pVM->cpum.s.aGuestCpuIdStd[0], &aGuestCpuIdStd[0], sizeof(aGuestCpuIdStd));
2320 memcpy(&pVM->cpum.s.aGuestCpuIdExt[0], &aGuestCpuIdExt[0], sizeof(aGuestCpuIdExt));
2321 memcpy(&pVM->cpum.s.aGuestCpuIdCentaur[0], &aGuestCpuIdCentaur[0], sizeof(aGuestCpuIdCentaur));
2322 pVM->cpum.s.GuestCpuIdDef = GuestCpuIdDef;
2323
2324#undef CPUID_CHECK_RET
2325#undef CPUID_CHECK_WRN
2326#undef CPUID_CHECK2_RET
2327#undef CPUID_CHECK2_WRN
2328#undef CPUID_RAW_FEATURE_RET
2329#undef CPUID_RAW_FEATURE_WRN
2330#undef CPUID_RAW_FEATURE_IGN
2331#undef CPUID_GST_FEATURE_RET
2332#undef CPUID_GST_FEATURE_WRN
2333#undef CPUID_GST_FEATURE_EMU
2334#undef CPUID_GST_FEATURE_IGN
2335#undef CPUID_GST_FEATURE2_RET
2336#undef CPUID_GST_FEATURE2_WRN
2337#undef CPUID_GST_FEATURE2_EMU
2338#undef CPUID_GST_FEATURE2_IGN
2339#undef CPUID_GST_AMD_FEATURE_RET
2340#undef CPUID_GST_AMD_FEATURE_WRN
2341#undef CPUID_GST_AMD_FEATURE_EMU
2342#undef CPUID_GST_AMD_FEATURE_IGN
2343
2344 return VINF_SUCCESS;
2345}
2346
2347
2348/**
2349 * Pass 0 live exec callback.
2350 *
2351 * @returns VINF_SSM_DONT_CALL_AGAIN.
2352 * @param pVM Pointer to the VM.
2353 * @param pSSM The saved state handle.
2354 * @param uPass The pass (0).
2355 */
2356static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2357{
2358 AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
2359 cpumR3SaveCpuId(pVM, pSSM);
2360 return VINF_SSM_DONT_CALL_AGAIN;
2361}
2362
2363
2364/**
2365 * Execute state save operation.
2366 *
2367 * @returns VBox status code.
2368 * @param pVM Pointer to the VM.
2369 * @param pSSM SSM operation handle.
2370 */
2371static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
2372{
2373 /*
2374 * Save.
2375 */
2376 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2377 {
2378 PVMCPU pVCpu = &pVM->aCpus[i];
2379 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
2380 }
2381
2382 SSMR3PutU32(pSSM, pVM->cCpus);
2383 SSMR3PutU32(pSSM, sizeof(pVM->aCpus[0].cpum.s.GuestMsrs.msr));
2384 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2385 {
2386 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2387
2388 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest), 0, g_aCpumCtxFields, NULL);
2389 SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
2390 SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
2391 AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
2392 SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
2393 }
2394
2395 cpumR3SaveCpuId(pVM, pSSM);
2396 return VINF_SUCCESS;
2397}
2398
2399
2400/**
2401 * @copydoc FNSSMINTLOADPREP
2402 */
2403static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2404{
2405 NOREF(pSSM);
2406 pVM->cpum.s.fPendingRestore = true;
2407 return VINF_SUCCESS;
2408}
2409
2410
2411/**
2412 * @copydoc FNSSMINTLOADEXEC
2413 */
2414static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2415{
2416 /*
2417 * Validate version.
2418 */
2419 if ( uVersion != CPUM_SAVED_STATE_VERSION
2420 && uVersion != CPUM_SAVED_STATE_VERSION_MEM
2421 && uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
2422 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
2423 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
2424 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
2425 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2426 && uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
2427 {
2428 AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
2429 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2430 }
2431
2432 if (uPass == SSM_PASS_FINAL)
2433 {
2434 /*
2435 * Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
2436 * really old SSM file versions.)
2437 */
2438 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2439 SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
2440 else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
2441 SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
2442
2443 uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
2444 PCSSMFIELD paCpumCtxFields = g_aCpumCtxFields;
2445 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2446 paCpumCtxFields = g_aCpumCtxFieldsV16;
2447 else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2448 paCpumCtxFields = g_aCpumCtxFieldsMem;
2449
2450 /*
2451 * Restore.
2452 */
2453 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2454 {
2455 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2456 uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
2457 uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
2458 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), fLoad, paCpumCtxFields, NULL);
2459 pVCpu->cpum.s.Hyper.cr3 = uCR3;
2460 pVCpu->cpum.s.Hyper.rsp = uRSP;
2461 }
2462
2463 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
2464 {
2465 uint32_t cCpus;
2466 int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2467 AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
2468 VERR_SSM_UNEXPECTED_DATA);
2469 }
2470 AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
2471 || pVM->cCpus == 1,
2472 ("cCpus=%u\n", pVM->cCpus),
2473 VERR_SSM_UNEXPECTED_DATA);
2474
2475 uint32_t cbMsrs = 0;
2476 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2477 {
2478 int rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
2479 AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
2480 VERR_SSM_UNEXPECTED_DATA);
2481 AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
2482 VERR_SSM_UNEXPECTED_DATA);
2483 }
2484
2485 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2486 {
2487 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2488 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest), fLoad,
2489 paCpumCtxFields, NULL);
2490 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fUseFlags);
2491 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
2492 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2493 SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
2494 else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
2495 {
2496 SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
2497 SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
2498 }
2499 }
2500
2501 /* Older states does not have the internal selector register flags
2502 and valid selector value. Supply those. */
2503 if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2504 {
2505 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2506 {
2507 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2508 bool const fValid = HMIsEnabled(pVM)
2509 || ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2510 && !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
2511 PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
2512 if (fValid)
2513 {
2514 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2515 {
2516 paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
2517 paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
2518 }
2519
2520 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2521 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2522 }
2523 else
2524 {
2525 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2526 {
2527 paSelReg[iSelReg].fFlags = 0;
2528 paSelReg[iSelReg].ValidSel = 0;
2529 }
2530
2531 /* This might not be 104% correct, but I think it's close
2532 enough for all practical purposes... (REM always loaded
2533 LDTR registers.) */
2534 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2535 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2536 }
2537 pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2538 pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
2539 }
2540 }
2541
2542 /* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
2543 if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2544 && uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2545 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2546 pVM->aCpus[iCpu].cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
2547
2548 /*
2549 * A quick sanity check.
2550 */
2551 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2552 {
2553 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2554 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2555 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2556 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2557 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2558 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2559 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2560 }
2561 }
2562
2563 pVM->cpum.s.fPendingRestore = false;
2564
2565 /*
2566 * Guest CPUIDs.
2567 */
2568 if (uVersion > CPUM_SAVED_STATE_VERSION_VER3_0)
2569 return cpumR3LoadCpuId(pVM, pSSM, uVersion);
2570
2571 /** @todo Merge the code below into cpumR3LoadCpuId when we've found out what is
2572 * actually required. */
2573
2574 /*
2575 * Restore the CPUID leaves.
2576 *
2577 * Note that we support restoring less than the current amount of standard
2578 * leaves because we've been allowed more is newer version of VBox.
2579 */
2580 uint32_t cElements;
2581 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2582 if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
2583 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2584 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
2585
2586 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2587 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
2588 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2589 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
2590
2591 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2592 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
2593 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2594 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
2595
2596 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
2597
2598 /*
2599 * Check that the basic cpuid id information is unchanged.
2600 */
2601 /** @todo we should check the 64 bits capabilities too! */
2602 uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
2603 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
2604 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
2605 uint32_t au32CpuIdSaved[8];
2606 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
2607 if (RT_SUCCESS(rc))
2608 {
2609 /* Ignore CPU stepping. */
2610 au32CpuId[4] &= 0xfffffff0;
2611 au32CpuIdSaved[4] &= 0xfffffff0;
2612
2613 /* Ignore APIC ID (AMD specs). */
2614 au32CpuId[5] &= ~0xff000000;
2615 au32CpuIdSaved[5] &= ~0xff000000;
2616
2617 /* Ignore the number of Logical CPUs (AMD specs). */
2618 au32CpuId[5] &= ~0x00ff0000;
2619 au32CpuIdSaved[5] &= ~0x00ff0000;
2620
2621 /* Ignore some advanced capability bits, that we don't expose to the guest. */
2622 au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2623 | X86_CPUID_FEATURE_ECX_VMX
2624 | X86_CPUID_FEATURE_ECX_SMX
2625 | X86_CPUID_FEATURE_ECX_EST
2626 | X86_CPUID_FEATURE_ECX_TM2
2627 | X86_CPUID_FEATURE_ECX_CNTXID
2628 | X86_CPUID_FEATURE_ECX_TPRUPDATE
2629 | X86_CPUID_FEATURE_ECX_PDCM
2630 | X86_CPUID_FEATURE_ECX_DCA
2631 | X86_CPUID_FEATURE_ECX_X2APIC
2632 );
2633 au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2634 | X86_CPUID_FEATURE_ECX_VMX
2635 | X86_CPUID_FEATURE_ECX_SMX
2636 | X86_CPUID_FEATURE_ECX_EST
2637 | X86_CPUID_FEATURE_ECX_TM2
2638 | X86_CPUID_FEATURE_ECX_CNTXID
2639 | X86_CPUID_FEATURE_ECX_TPRUPDATE
2640 | X86_CPUID_FEATURE_ECX_PDCM
2641 | X86_CPUID_FEATURE_ECX_DCA
2642 | X86_CPUID_FEATURE_ECX_X2APIC
2643 );
2644
2645 /* Make sure we don't forget to update the masks when enabling
2646 * features in the future.
2647 */
2648 AssertRelease(!(pVM->cpum.s.aGuestCpuIdStd[1].ecx &
2649 ( X86_CPUID_FEATURE_ECX_DTES64
2650 | X86_CPUID_FEATURE_ECX_VMX
2651 | X86_CPUID_FEATURE_ECX_SMX
2652 | X86_CPUID_FEATURE_ECX_EST
2653 | X86_CPUID_FEATURE_ECX_TM2
2654 | X86_CPUID_FEATURE_ECX_CNTXID
2655 | X86_CPUID_FEATURE_ECX_TPRUPDATE
2656 | X86_CPUID_FEATURE_ECX_PDCM
2657 | X86_CPUID_FEATURE_ECX_DCA
2658 | X86_CPUID_FEATURE_ECX_X2APIC
2659 )));
2660 /* do the compare */
2661 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
2662 {
2663 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
2664 LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
2665 "Saved=%.*Rhxs\n"
2666 "Real =%.*Rhxs\n",
2667 sizeof(au32CpuIdSaved), au32CpuIdSaved,
2668 sizeof(au32CpuId), au32CpuId));
2669 else
2670 {
2671 LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
2672 "Saved=%.*Rhxs\n"
2673 "Real =%.*Rhxs\n",
2674 sizeof(au32CpuIdSaved), au32CpuIdSaved,
2675 sizeof(au32CpuId), au32CpuId));
2676 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
2677 }
2678 }
2679 }
2680
2681 return rc;
2682}
2683
2684
2685/**
2686 * @copydoc FNSSMINTLOADPREP
2687 */
2688static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
2689{
2690 if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
2691 return VINF_SUCCESS;
2692
2693 /* just check this since we can. */ /** @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
2694 if (pVM->cpum.s.fPendingRestore)
2695 {
2696 LogRel(("CPUM: Missing state!\n"));
2697 return VERR_INTERNAL_ERROR_2;
2698 }
2699
2700 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2701 {
2702 /* Notify PGM of the NXE states in case they've changed. */
2703 PGMNotifyNxeChanged(&pVM->aCpus[iCpu], !!(pVM->aCpus[iCpu].cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
2704
2705 /* Cache the local APIC base from the APIC device. During init. this is done in CPUMR3ResetCpu(). */
2706 PDMApicGetBase(&pVM->aCpus[iCpu], &pVM->aCpus[iCpu].cpum.s.Guest.msrApicBase);
2707 }
2708 return VINF_SUCCESS;
2709}
2710
2711
2712/**
2713 * Checks if the CPUM state restore is still pending.
2714 *
2715 * @returns true / false.
2716 * @param pVM Pointer to the VM.
2717 */
2718VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
2719{
2720 return pVM->cpum.s.fPendingRestore;
2721}
2722
2723
2724/**
2725 * Formats the EFLAGS value into mnemonics.
2726 *
2727 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
2728 * @param efl The EFLAGS value.
2729 */
2730static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
2731{
2732 /*
2733 * Format the flags.
2734 */
2735 static const struct
2736 {
2737 const char *pszSet; const char *pszClear; uint32_t fFlag;
2738 } s_aFlags[] =
2739 {
2740 { "vip",NULL, X86_EFL_VIP },
2741 { "vif",NULL, X86_EFL_VIF },
2742 { "ac", NULL, X86_EFL_AC },
2743 { "vm", NULL, X86_EFL_VM },
2744 { "rf", NULL, X86_EFL_RF },
2745 { "nt", NULL, X86_EFL_NT },
2746 { "ov", "nv", X86_EFL_OF },
2747 { "dn", "up", X86_EFL_DF },
2748 { "ei", "di", X86_EFL_IF },
2749 { "tf", NULL, X86_EFL_TF },
2750 { "nt", "pl", X86_EFL_SF },
2751 { "nz", "zr", X86_EFL_ZF },
2752 { "ac", "na", X86_EFL_AF },
2753 { "po", "pe", X86_EFL_PF },
2754 { "cy", "nc", X86_EFL_CF },
2755 };
2756 char *psz = pszEFlags;
2757 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
2758 {
2759 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
2760 if (pszAdd)
2761 {
2762 strcpy(psz, pszAdd);
2763 psz += strlen(pszAdd);
2764 *psz++ = ' ';
2765 }
2766 }
2767 psz[-1] = '\0';
2768}
2769
2770
2771/**
2772 * Formats a full register dump.
2773 *
2774 * @param pVM Pointer to the VM.
2775 * @param pCtx The context to format.
2776 * @param pCtxCore The context core to format.
2777 * @param pHlp Output functions.
2778 * @param enmType The dump type.
2779 * @param pszPrefix Register name prefix.
2780 */
2781static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
2782 const char *pszPrefix)
2783{
2784 NOREF(pVM);
2785
2786 /*
2787 * Format the EFLAGS.
2788 */
2789 uint32_t efl = pCtxCore->eflags.u32;
2790 char szEFlags[80];
2791 cpumR3InfoFormatFlags(&szEFlags[0], efl);
2792
2793 /*
2794 * Format the registers.
2795 */
2796 switch (enmType)
2797 {
2798 case CPUMDUMPTYPE_TERSE:
2799 if (CPUMIsGuestIn64BitCodeEx(pCtx))
2800 pHlp->pfnPrintf(pHlp,
2801 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2802 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2803 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2804 "%sr14=%016RX64 %sr15=%016RX64\n"
2805 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2806 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2807 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2808 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2809 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2810 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2811 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2812 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
2813 else
2814 pHlp->pfnPrintf(pHlp,
2815 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2816 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2817 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2818 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2819 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2820 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2821 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
2822 break;
2823
2824 case CPUMDUMPTYPE_DEFAULT:
2825 if (CPUMIsGuestIn64BitCodeEx(pCtx))
2826 pHlp->pfnPrintf(pHlp,
2827 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2828 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2829 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2830 "%sr14=%016RX64 %sr15=%016RX64\n"
2831 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2832 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2833 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
2834 ,
2835 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2836 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2837 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2838 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2839 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2840 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
2841 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2842 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
2843 else
2844 pHlp->pfnPrintf(pHlp,
2845 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2846 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2847 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2848 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
2849 ,
2850 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2851 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2852 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2853 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
2854 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2855 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
2856 break;
2857
2858 case CPUMDUMPTYPE_VERBOSE:
2859 if (CPUMIsGuestIn64BitCodeEx(pCtx))
2860 pHlp->pfnPrintf(pHlp,
2861 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2862 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2863 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2864 "%sr14=%016RX64 %sr15=%016RX64\n"
2865 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2866 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2867 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2868 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2869 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2870 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2871 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2872 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
2873 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
2874 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
2875 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2876 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2877 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2878 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
2879 ,
2880 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2881 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2882 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2883 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2884 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
2885 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
2886 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
2887 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
2888 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
2889 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
2890 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2891 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2892 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2893 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2894 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2895 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2896 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2897 else
2898 pHlp->pfnPrintf(pHlp,
2899 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2900 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2901 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
2902 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
2903 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
2904 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
2905 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
2906 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
2907 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2908 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2909 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2910 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2911 ,
2912 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2913 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2914 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
2915 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2916 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
2917 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2918 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
2919 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2920 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2921 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2922 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2923 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2924
2925 pHlp->pfnPrintf(pHlp,
2926 "%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
2927 "%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
2928 ,
2929 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW, pszPrefix, pCtx->fpu.FOP,
2930 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK,
2931 pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsrvd1,
2932 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2
2933 );
2934 unsigned iShift = (pCtx->fpu.FSW >> 11) & 7;
2935 for (unsigned iST = 0; iST < RT_ELEMENTS(pCtx->fpu.aRegs); iST++)
2936 {
2937 unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pCtx->fpu.aRegs);
2938 unsigned uTag = pCtx->fpu.FTW & (1 << iFPR) ? 1 : 0;
2939 char chSign = pCtx->fpu.aRegs[0].au16[4] & 0x8000 ? '-' : '+';
2940 unsigned iInteger = (unsigned)(pCtx->fpu.aRegs[0].au64[0] >> 63);
2941 uint64_t u64Fraction = pCtx->fpu.aRegs[0].au64[0] & UINT64_C(0x7fffffffffffffff);
2942 unsigned uExponent = pCtx->fpu.aRegs[0].au16[4] & 0x7fff;
2943 /** @todo This isn't entirenly correct and needs more work! */
2944 pHlp->pfnPrintf(pHlp,
2945 "%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu ^ %u",
2946 pszPrefix, iST, pszPrefix, iFPR,
2947 pCtx->fpu.aRegs[0].au16[4], pCtx->fpu.aRegs[0].au32[1], pCtx->fpu.aRegs[0].au32[0],
2948 uTag, chSign, iInteger, u64Fraction, uExponent);
2949 if (pCtx->fpu.aRegs[0].au16[5] || pCtx->fpu.aRegs[0].au16[6] || pCtx->fpu.aRegs[0].au16[7])
2950 pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
2951 pCtx->fpu.aRegs[0].au16[5], pCtx->fpu.aRegs[0].au16[6], pCtx->fpu.aRegs[0].au16[7]);
2952 else
2953 pHlp->pfnPrintf(pHlp, "\n");
2954 }
2955 for (unsigned iXMM = 0; iXMM < RT_ELEMENTS(pCtx->fpu.aXMM); iXMM++)
2956 pHlp->pfnPrintf(pHlp,
2957 iXMM & 1
2958 ? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
2959 : "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
2960 pszPrefix, iXMM, iXMM < 10 ? " " : "",
2961 pCtx->fpu.aXMM[iXMM].au32[3],
2962 pCtx->fpu.aXMM[iXMM].au32[2],
2963 pCtx->fpu.aXMM[iXMM].au32[1],
2964 pCtx->fpu.aXMM[iXMM].au32[0]);
2965 for (unsigned i = 0; i < RT_ELEMENTS(pCtx->fpu.au32RsrvdRest); i++)
2966 if (pCtx->fpu.au32RsrvdRest[i])
2967 pHlp->pfnPrintf(pHlp, "%sRsrvdRest[i]=%RX32 (offset=%#x)\n",
2968 pszPrefix, i, pCtx->fpu.au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
2969
2970 pHlp->pfnPrintf(pHlp,
2971 "%sEFER =%016RX64\n"
2972 "%sPAT =%016RX64\n"
2973 "%sSTAR =%016RX64\n"
2974 "%sCSTAR =%016RX64\n"
2975 "%sLSTAR =%016RX64\n"
2976 "%sSFMASK =%016RX64\n"
2977 "%sKERNELGSBASE =%016RX64\n",
2978 pszPrefix, pCtx->msrEFER,
2979 pszPrefix, pCtx->msrPAT,
2980 pszPrefix, pCtx->msrSTAR,
2981 pszPrefix, pCtx->msrCSTAR,
2982 pszPrefix, pCtx->msrLSTAR,
2983 pszPrefix, pCtx->msrSFMASK,
2984 pszPrefix, pCtx->msrKERNELGSBASE);
2985 break;
2986 }
2987}
2988
2989
2990/**
2991 * Display all cpu states and any other cpum info.
2992 *
2993 * @param pVM Pointer to the VM.
2994 * @param pHlp The info helper functions.
2995 * @param pszArgs Arguments, ignored.
2996 */
2997static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2998{
2999 cpumR3InfoGuest(pVM, pHlp, pszArgs);
3000 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
3001 cpumR3InfoHyper(pVM, pHlp, pszArgs);
3002 cpumR3InfoHost(pVM, pHlp, pszArgs);
3003}
3004
3005
3006/**
3007 * Parses the info argument.
3008 *
3009 * The argument starts with 'verbose', 'terse' or 'default' and then
3010 * continues with the comment string.
3011 *
3012 * @param pszArgs The pointer to the argument string.
3013 * @param penmType Where to store the dump type request.
3014 * @param ppszComment Where to store the pointer to the comment string.
3015 */
3016static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
3017{
3018 if (!pszArgs)
3019 {
3020 *penmType = CPUMDUMPTYPE_DEFAULT;
3021 *ppszComment = "";
3022 }
3023 else
3024 {
3025 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
3026 {
3027 pszArgs += 7;
3028 *penmType = CPUMDUMPTYPE_VERBOSE;
3029 }
3030 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
3031 {
3032 pszArgs += 5;
3033 *penmType = CPUMDUMPTYPE_TERSE;
3034 }
3035 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
3036 {
3037 pszArgs += 7;
3038 *penmType = CPUMDUMPTYPE_DEFAULT;
3039 }
3040 else
3041 *penmType = CPUMDUMPTYPE_DEFAULT;
3042 *ppszComment = RTStrStripL(pszArgs);
3043 }
3044}
3045
3046
3047/**
3048 * Display the guest cpu state.
3049 *
3050 * @param pVM Pointer to the VM.
3051 * @param pHlp The info helper functions.
3052 * @param pszArgs Arguments, ignored.
3053 */
3054static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3055{
3056 CPUMDUMPTYPE enmType;
3057 const char *pszComment;
3058 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3059
3060 /* @todo SMP support! */
3061 PVMCPU pVCpu = VMMGetCpu(pVM);
3062 if (!pVCpu)
3063 pVCpu = &pVM->aCpus[0];
3064
3065 pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
3066
3067 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3068 cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
3069}
3070
3071
3072/**
3073 * Display the current guest instruction
3074 *
3075 * @param pVM Pointer to the VM.
3076 * @param pHlp The info helper functions.
3077 * @param pszArgs Arguments, ignored.
3078 */
3079static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3080{
3081 NOREF(pszArgs);
3082
3083 /** @todo SMP support! */
3084 PVMCPU pVCpu = VMMGetCpu(pVM);
3085 if (!pVCpu)
3086 pVCpu = &pVM->aCpus[0];
3087
3088 char szInstruction[256];
3089 int rc = DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
3090 if (RT_SUCCESS(rc))
3091 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
3092}
3093
3094
3095/**
3096 * Display the hypervisor cpu state.
3097 *
3098 * @param pVM Pointer to the VM.
3099 * @param pHlp The info helper functions.
3100 * @param pszArgs Arguments, ignored.
3101 */
3102static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3103{
3104 CPUMDUMPTYPE enmType;
3105 const char *pszComment;
3106 /* @todo SMP */
3107 PVMCPU pVCpu = &pVM->aCpus[0];
3108
3109 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3110 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
3111 cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper), pHlp, enmType, ".");
3112 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
3113}
3114
3115
3116/**
3117 * Display the host cpu state.
3118 *
3119 * @param pVM Pointer to the VM.
3120 * @param pHlp The info helper functions.
3121 * @param pszArgs Arguments, ignored.
3122 */
3123static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3124{
3125 CPUMDUMPTYPE enmType;
3126 const char *pszComment;
3127 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3128 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
3129
3130 /*
3131 * Format the EFLAGS.
3132 */
3133 /* @todo SMP */
3134 PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
3135#if HC_ARCH_BITS == 32
3136 uint32_t efl = pCtx->eflags.u32;
3137#else
3138 uint64_t efl = pCtx->rflags;
3139#endif
3140 char szEFlags[80];
3141 cpumR3InfoFormatFlags(&szEFlags[0], efl);
3142
3143 /*
3144 * Format the registers.
3145 */
3146#if HC_ARCH_BITS == 32
3147# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
3148 if (!(pCtx->efer & MSR_K6_EFER_LMA))
3149# endif
3150 {
3151 pHlp->pfnPrintf(pHlp,
3152 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
3153 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
3154 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
3155 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
3156 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
3157 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
3158 ,
3159 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
3160 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
3161 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
3162 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
3163 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
3164 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->ldtr,
3165 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3166 }
3167# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
3168 else
3169# endif
3170#endif
3171#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
3172 {
3173 pHlp->pfnPrintf(pHlp,
3174 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
3175 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
3176 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
3177 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
3178 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
3179 "r14=%016RX64 r15=%016RX64\n"
3180 "iopl=%d %31s\n"
3181 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
3182 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
3183 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
3184 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
3185 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
3186 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
3187 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
3188 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
3189 ,
3190 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
3191 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
3192 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
3193 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
3194 pCtx->r11, pCtx->r12, pCtx->r13,
3195 pCtx->r14, pCtx->r15,
3196 X86_EFL_GET_IOPL(efl), szEFlags,
3197 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
3198 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
3199 pCtx->cr4, pCtx->ldtr, pCtx->tr,
3200 pCtx->dr0, pCtx->dr1, pCtx->dr2,
3201 pCtx->dr3, pCtx->dr6, pCtx->dr7,
3202 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
3203 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
3204 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
3205 }
3206#endif
3207}
3208
3209
3210/**
3211 * Get L1 cache / TLS associativity.
3212 */
3213static const char *getCacheAss(unsigned u, char *pszBuf)
3214{
3215 if (u == 0)
3216 return "res0 ";
3217 if (u == 1)
3218 return "direct";
3219 if (u == 255)
3220 return "fully";
3221 if (u >= 256)
3222 return "???";
3223
3224 RTStrPrintf(pszBuf, 16, "%d way", u);
3225 return pszBuf;
3226}
3227
3228
3229/**
3230 * Get L2 cache associativity.
3231 */
3232const char *getL2CacheAss(unsigned u)
3233{
3234 switch (u)
3235 {
3236 case 0: return "off ";
3237 case 1: return "direct";
3238 case 2: return "2 way ";
3239 case 3: return "res3 ";
3240 case 4: return "4 way ";
3241 case 5: return "res5 ";
3242 case 6: return "8 way ";
3243 case 7: return "res7 ";
3244 case 8: return "16 way";
3245 case 9: return "res9 ";
3246 case 10: return "res10 ";
3247 case 11: return "res11 ";
3248 case 12: return "res12 ";
3249 case 13: return "res13 ";
3250 case 14: return "res14 ";
3251 case 15: return "fully ";
3252 default: return "????";
3253 }
3254}
3255
3256
3257/**
3258 * Display the guest CpuId leaves.
3259 *
3260 * @param pVM Pointer to the VM.
3261 * @param pHlp The info helper functions.
3262 * @param pszArgs "terse", "default" or "verbose".
3263 */
3264static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3265{
3266 /*
3267 * Parse the argument.
3268 */
3269 unsigned iVerbosity = 1;
3270 if (pszArgs)
3271 {
3272 pszArgs = RTStrStripL(pszArgs);
3273 if (!strcmp(pszArgs, "terse"))
3274 iVerbosity--;
3275 else if (!strcmp(pszArgs, "verbose"))
3276 iVerbosity++;
3277 }
3278
3279 /*
3280 * Start cracking.
3281 */
3282 CPUMCPUID Host;
3283 CPUMCPUID Guest;
3284 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
3285
3286 pHlp->pfnPrintf(pHlp,
3287 " RAW Standard CPUIDs\n"
3288 " Function eax ebx ecx edx\n");
3289 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
3290 {
3291 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
3292 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3293
3294 pHlp->pfnPrintf(pHlp,
3295 "Gst: %08x %08x %08x %08x %08x%s\n"
3296 "Hst: %08x %08x %08x %08x\n",
3297 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3298 i <= cStdMax ? "" : "*",
3299 Host.eax, Host.ebx, Host.ecx, Host.edx);
3300 }
3301
3302 /*
3303 * If verbose, decode it.
3304 */
3305 if (iVerbosity)
3306 {
3307 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
3308 pHlp->pfnPrintf(pHlp,
3309 "Name: %.04s%.04s%.04s\n"
3310 "Supports: 0-%x\n",
3311 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
3312 }
3313
3314 /*
3315 * Get Features.
3316 */
3317 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
3318 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
3319 pVM->cpum.s.aGuestCpuIdStd[0].edx);
3320 if (cStdMax >= 1 && iVerbosity)
3321 {
3322 static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
3323
3324 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
3325 uint32_t uEAX = Guest.eax;
3326
3327 pHlp->pfnPrintf(pHlp,
3328 "Family: %d \tExtended: %d \tEffective: %d\n"
3329 "Model: %d \tExtended: %d \tEffective: %d\n"
3330 "Stepping: %d\n"
3331 "Type: %d (%s)\n"
3332 "APIC ID: %#04x\n"
3333 "Logical CPUs: %d\n"
3334 "CLFLUSH Size: %d\n"
3335 "Brand ID: %#04x\n",
3336 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
3337 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
3338 ASMGetCpuStepping(uEAX),
3339 (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
3340 (Guest.ebx >> 24) & 0xff,
3341 (Guest.ebx >> 16) & 0xff,
3342 (Guest.ebx >> 8) & 0xff,
3343 (Guest.ebx >> 0) & 0xff);
3344 if (iVerbosity == 1)
3345 {
3346 uint32_t uEDX = Guest.edx;
3347 pHlp->pfnPrintf(pHlp, "Features EDX: ");
3348 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
3349 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
3350 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
3351 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
3352 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
3353 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
3354 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
3355 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
3356 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
3357 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
3358 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
3359 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
3360 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
3361 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
3362 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
3363 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
3364 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
3365 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
3366 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
3367 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
3368 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
3369 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
3370 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
3371 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
3372 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
3373 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
3374 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
3375 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
3376 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
3377 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
3378 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
3379 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
3380 pHlp->pfnPrintf(pHlp, "\n");
3381
3382 uint32_t uECX = Guest.ecx;
3383 pHlp->pfnPrintf(pHlp, "Features ECX: ");
3384 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
3385 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " PCLMUL");
3386 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DTES64");
3387 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
3388 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
3389 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
3390 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SMX");
3391 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
3392 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
3393 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " SSSE3");
3394 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
3395 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
3396 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " FMA");
3397 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
3398 if (uECX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " TPRUPDATE");
3399 if (uECX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " PDCM");
3400 if (uECX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " 16");
3401 if (uECX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PCID");
3402 if (uECX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " DCA");
3403 if (uECX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " SSE4.1");
3404 if (uECX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " SSE4.2");
3405 if (uECX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " X2APIC");
3406 if (uECX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " MOVBE");
3407 if (uECX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " POPCNT");
3408 if (uECX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " TSCDEADL");
3409 if (uECX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " AES");
3410 if (uECX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " XSAVE");
3411 if (uECX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " OSXSAVE");
3412 if (uECX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " AVX");
3413 if (uECX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " 29");
3414 if (uECX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
3415 if (uECX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 31");
3416 pHlp->pfnPrintf(pHlp, "\n");
3417 }
3418 else
3419 {
3420 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3421
3422 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
3423 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
3424 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
3425 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
3426
3427 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3428 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
3429 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
3430 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
3431 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
3432 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
3433 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
3434 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
3435 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
3436 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
3437 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
3438 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
3439 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
3440 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
3441 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
3442 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
3443 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
3444 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
3445 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
3446 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
3447 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
3448 pHlp->pfnPrintf(pHlp, "20 - Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
3449 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
3450 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
3451 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
3452 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
3453 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
3454 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
3455 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
3456 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technology = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
3457 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
3458 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
3459 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
3460
3461 pHlp->pfnPrintf(pHlp, "Supports SSE3 = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
3462 pHlp->pfnPrintf(pHlp, "PCLMULQDQ = %d (%d)\n", EcxGuest.u1PCLMULQDQ, EcxHost.u1PCLMULQDQ);
3463 pHlp->pfnPrintf(pHlp, "DS Area 64-bit layout = %d (%d)\n", EcxGuest.u1DTE64, EcxHost.u1DTE64);
3464 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
3465 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
3466 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
3467 pHlp->pfnPrintf(pHlp, "SMX - Safer Mode Extensions = %d (%d)\n", EcxGuest.u1SMX, EcxHost.u1SMX);
3468 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
3469 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
3470 pHlp->pfnPrintf(pHlp, "Supplemental SSE3 instructions = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
3471 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
3472 pHlp->pfnPrintf(pHlp, "11 - Reserved = %d (%d)\n", EcxGuest.u1Reserved1, EcxHost.u1Reserved1);
3473 pHlp->pfnPrintf(pHlp, "FMA extensions using YMM state = %d (%d)\n", EcxGuest.u1FMA, EcxHost.u1FMA);
3474 pHlp->pfnPrintf(pHlp, "CMPXCHG16B instruction = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
3475 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
3476 pHlp->pfnPrintf(pHlp, "Perf/Debug Capability MSR = %d (%d)\n", EcxGuest.u1PDCM, EcxHost.u1PDCM);
3477 pHlp->pfnPrintf(pHlp, "16 - Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
3478 pHlp->pfnPrintf(pHlp, "PCID - Process-context identifiers = %d (%d)\n", EcxGuest.u1PCID, EcxHost.u1PCID);
3479 pHlp->pfnPrintf(pHlp, "DCA - Direct Cache Access = %d (%d)\n", EcxGuest.u1DCA, EcxHost.u1DCA);
3480 pHlp->pfnPrintf(pHlp, "SSE4.1 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_1, EcxHost.u1SSE4_1);
3481 pHlp->pfnPrintf(pHlp, "SSE4.2 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_2, EcxHost.u1SSE4_2);
3482 pHlp->pfnPrintf(pHlp, "Supports the x2APIC extensions = %d (%d)\n", EcxGuest.u1x2APIC, EcxHost.u1x2APIC);
3483 pHlp->pfnPrintf(pHlp, "MOVBE instruction = %d (%d)\n", EcxGuest.u1MOVBE, EcxHost.u1MOVBE);
3484 pHlp->pfnPrintf(pHlp, "POPCNT instruction = %d (%d)\n", EcxGuest.u1POPCNT, EcxHost.u1POPCNT);
3485 pHlp->pfnPrintf(pHlp, "TSC-Deadline LAPIC timer mode = %d (%d)\n", EcxGuest.u1TSCDEADLINE,EcxHost.u1TSCDEADLINE);
3486 pHlp->pfnPrintf(pHlp, "AESNI instruction extensions = %d (%d)\n", EcxGuest.u1AES, EcxHost.u1AES);
3487 pHlp->pfnPrintf(pHlp, "XSAVE/XRSTOR extended state feature = %d (%d)\n", EcxGuest.u1XSAVE, EcxHost.u1XSAVE);
3488 pHlp->pfnPrintf(pHlp, "Supports OSXSAVE = %d (%d)\n", EcxGuest.u1OSXSAVE, EcxHost.u1OSXSAVE);
3489 pHlp->pfnPrintf(pHlp, "AVX instruction extensions = %d (%d)\n", EcxGuest.u1AVX, EcxHost.u1AVX);
3490 pHlp->pfnPrintf(pHlp, "29/30 - Reserved = %#x (%#x)\n",EcxGuest.u2Reserved3, EcxHost.u2Reserved3);
3491 pHlp->pfnPrintf(pHlp, "Hypervisor Present (we're a guest) = %d (%d)\n", EcxGuest.u1HVP, EcxHost.u1HVP);
3492 }
3493 }
3494 if (cStdMax >= 2 && iVerbosity)
3495 {
3496 /** @todo */
3497 }
3498
3499 /*
3500 * Extended.
3501 * Implemented after AMD specs.
3502 */
3503 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
3504
3505 pHlp->pfnPrintf(pHlp,
3506 "\n"
3507 " RAW Extended CPUIDs\n"
3508 " Function eax ebx ecx edx\n");
3509 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
3510 {
3511 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
3512 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3513
3514 pHlp->pfnPrintf(pHlp,
3515 "Gst: %08x %08x %08x %08x %08x%s\n"
3516 "Hst: %08x %08x %08x %08x\n",
3517 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3518 i <= cExtMax ? "" : "*",
3519 Host.eax, Host.ebx, Host.ecx, Host.edx);
3520 }
3521
3522 /*
3523 * Understandable output
3524 */
3525 if (iVerbosity)
3526 {
3527 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
3528 pHlp->pfnPrintf(pHlp,
3529 "Ext Name: %.4s%.4s%.4s\n"
3530 "Ext Supports: 0x80000000-%#010x\n",
3531 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
3532 }
3533
3534 if (iVerbosity && cExtMax >= 1)
3535 {
3536 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
3537 uint32_t uEAX = Guest.eax;
3538 pHlp->pfnPrintf(pHlp,
3539 "Family: %d \tExtended: %d \tEffective: %d\n"
3540 "Model: %d \tExtended: %d \tEffective: %d\n"
3541 "Stepping: %d\n"
3542 "Brand ID: %#05x\n",
3543 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
3544 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
3545 ASMGetCpuStepping(uEAX),
3546 Guest.ebx & 0xfff);
3547
3548 if (iVerbosity == 1)
3549 {
3550 uint32_t uEDX = Guest.edx;
3551 pHlp->pfnPrintf(pHlp, "Features EDX: ");
3552 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
3553 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
3554 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
3555 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
3556 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
3557 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
3558 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
3559 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
3560 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
3561 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
3562 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
3563 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
3564 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
3565 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
3566 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
3567 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
3568 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
3569 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
3570 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
3571 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
3572 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
3573 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
3574 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
3575 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
3576 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
3577 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
3578 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
3579 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
3580 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
3581 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
3582 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
3583 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
3584 pHlp->pfnPrintf(pHlp, "\n");
3585
3586 uint32_t uECX = Guest.ecx;
3587 pHlp->pfnPrintf(pHlp, "Features ECX: ");
3588 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
3589 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
3590 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
3591 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
3592 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
3593 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
3594 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
3595 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
3596 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
3597 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
3598 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
3599 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
3600 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
3601 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
3602 for (unsigned iBit = 5; iBit < 32; iBit++)
3603 if (uECX & RT_BIT(iBit))
3604 pHlp->pfnPrintf(pHlp, " %d", iBit);
3605 pHlp->pfnPrintf(pHlp, "\n");
3606 }
3607 else
3608 {
3609 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3610
3611 uint32_t uEdxGst = Guest.edx;
3612 uint32_t uEdxHst = Host.edx;
3613 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3614 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3615 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3616 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3617 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3618 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3619 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3620 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3621 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3622 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3623 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3624 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3625 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3626 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3627 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3628 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
3629 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
3630 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
3631 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
3632 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
3633 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
3634 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
3635 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
3636 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
3637 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
3638 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
3639 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
3640 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
3641 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
3642 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
3643 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
3644 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow! = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
3645 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow! = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
3646
3647 uint32_t uEcxGst = Guest.ecx;
3648 uint32_t uEcxHst = Host.ecx;
3649 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
3650 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
3651 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
3652 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
3653 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
3654 pHlp->pfnPrintf(pHlp, "5 - Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
3655 pHlp->pfnPrintf(pHlp, "6 - SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
3656 pHlp->pfnPrintf(pHlp, "7 - Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
3657 pHlp->pfnPrintf(pHlp, "8 - PREFETCH and PREFETCHW instruction= %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
3658 pHlp->pfnPrintf(pHlp, "9 - OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
3659 pHlp->pfnPrintf(pHlp, "10 - Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
3660 pHlp->pfnPrintf(pHlp, "11 - SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
3661 pHlp->pfnPrintf(pHlp, "12 - SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
3662 pHlp->pfnPrintf(pHlp, "13 - Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
3663 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
3664 }
3665 }
3666
3667 if (iVerbosity && cExtMax >= 2)
3668 {
3669 char szString[4*4*3+1] = {0};
3670 uint32_t *pu32 = (uint32_t *)szString;
3671 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
3672 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
3673 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
3674 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
3675 if (cExtMax >= 3)
3676 {
3677 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
3678 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
3679 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
3680 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
3681 }
3682 if (cExtMax >= 4)
3683 {
3684 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
3685 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
3686 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
3687 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
3688 }
3689 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
3690 }
3691
3692 if (iVerbosity && cExtMax >= 5)
3693 {
3694 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
3695 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
3696 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
3697 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
3698 char sz1[32];
3699 char sz2[32];
3700
3701 pHlp->pfnPrintf(pHlp,
3702 "TLB 2/4M Instr/Uni: %s %3d entries\n"
3703 "TLB 2/4M Data: %s %3d entries\n",
3704 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
3705 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
3706 pHlp->pfnPrintf(pHlp,
3707 "TLB 4K Instr/Uni: %s %3d entries\n"
3708 "TLB 4K Data: %s %3d entries\n",
3709 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
3710 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
3711 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
3712 "L1 Instr Cache Lines Per Tag: %d\n"
3713 "L1 Instr Cache Associativity: %s\n"
3714 "L1 Instr Cache Size: %d KB\n",
3715 (uEDX >> 0) & 0xff,
3716 (uEDX >> 8) & 0xff,
3717 getCacheAss((uEDX >> 16) & 0xff, sz1),
3718 (uEDX >> 24) & 0xff);
3719 pHlp->pfnPrintf(pHlp,
3720 "L1 Data Cache Line Size: %d bytes\n"
3721 "L1 Data Cache Lines Per Tag: %d\n"
3722 "L1 Data Cache Associativity: %s\n"
3723 "L1 Data Cache Size: %d KB\n",
3724 (uECX >> 0) & 0xff,
3725 (uECX >> 8) & 0xff,
3726 getCacheAss((uECX >> 16) & 0xff, sz1),
3727 (uECX >> 24) & 0xff);
3728 }
3729
3730 if (iVerbosity && cExtMax >= 6)
3731 {
3732 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
3733 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
3734 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
3735
3736 pHlp->pfnPrintf(pHlp,
3737 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
3738 "L2 TLB 2/4M Data: %s %4d entries\n",
3739 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
3740 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
3741 pHlp->pfnPrintf(pHlp,
3742 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
3743 "L2 TLB 4K Data: %s %4d entries\n",
3744 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
3745 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
3746 pHlp->pfnPrintf(pHlp,
3747 "L2 Cache Line Size: %d bytes\n"
3748 "L2 Cache Lines Per Tag: %d\n"
3749 "L2 Cache Associativity: %s\n"
3750 "L2 Cache Size: %d KB\n",
3751 (uEDX >> 0) & 0xff,
3752 (uEDX >> 8) & 0xf,
3753 getL2CacheAss((uEDX >> 12) & 0xf),
3754 (uEDX >> 16) & 0xffff);
3755 }
3756
3757 if (iVerbosity && cExtMax >= 7)
3758 {
3759 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
3760
3761 pHlp->pfnPrintf(pHlp, "APM Features: ");
3762 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
3763 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
3764 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
3765 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
3766 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
3767 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
3768 for (unsigned iBit = 6; iBit < 32; iBit++)
3769 if (uEDX & RT_BIT(iBit))
3770 pHlp->pfnPrintf(pHlp, " %d", iBit);
3771 pHlp->pfnPrintf(pHlp, "\n");
3772 }
3773
3774 if (iVerbosity && cExtMax >= 8)
3775 {
3776 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
3777 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
3778
3779 pHlp->pfnPrintf(pHlp,
3780 "Physical Address Width: %d bits\n"
3781 "Virtual Address Width: %d bits\n"
3782 "Guest Physical Address Width: %d bits\n",
3783 (uEAX >> 0) & 0xff,
3784 (uEAX >> 8) & 0xff,
3785 (uEAX >> 16) & 0xff);
3786 pHlp->pfnPrintf(pHlp,
3787 "Physical Core Count: %d\n",
3788 (uECX >> 0) & 0xff);
3789 }
3790
3791
3792 /*
3793 * Centaur.
3794 */
3795 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
3796
3797 pHlp->pfnPrintf(pHlp,
3798 "\n"
3799 " RAW Centaur CPUIDs\n"
3800 " Function eax ebx ecx edx\n");
3801 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
3802 {
3803 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
3804 ASMCpuId(0xc0000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3805
3806 pHlp->pfnPrintf(pHlp,
3807 "Gst: %08x %08x %08x %08x %08x%s\n"
3808 "Hst: %08x %08x %08x %08x\n",
3809 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3810 i <= cCentaurMax ? "" : "*",
3811 Host.eax, Host.ebx, Host.ecx, Host.edx);
3812 }
3813
3814 /*
3815 * Understandable output
3816 */
3817 if (iVerbosity)
3818 {
3819 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
3820 pHlp->pfnPrintf(pHlp,
3821 "Centaur Supports: 0xc0000000-%#010x\n",
3822 Guest.eax);
3823 }
3824
3825 if (iVerbosity && cCentaurMax >= 1)
3826 {
3827 ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3828 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
3829 uint32_t uEdxHst = Host.edx;
3830
3831 if (iVerbosity == 1)
3832 {
3833 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
3834 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
3835 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
3836 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
3837 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
3838 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
3839 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
3840 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
3841 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
3842 /* possibly indicating MM/HE and MM/HE-E on older chips... */
3843 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
3844 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
3845 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
3846 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
3847 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
3848 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
3849 for (unsigned iBit = 14; iBit < 32; iBit++)
3850 if (uEdxGst & RT_BIT(iBit))
3851 pHlp->pfnPrintf(pHlp, " %d", iBit);
3852 pHlp->pfnPrintf(pHlp, "\n");
3853 }
3854 else
3855 {
3856 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3857 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3858 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3859 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3860 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3861 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3862 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3863 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3864 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3865 /* possibly indicating MM/HE and MM/HE-E on older chips... */
3866 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3867 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3868 pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3869 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3870 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3871 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3872 pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
3873 pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
3874 pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
3875 pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
3876 pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
3877 pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
3878 pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
3879 pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
3880 pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
3881 pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
3882 pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
3883 pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
3884 pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
3885 for (unsigned iBit = 27; iBit < 32; iBit++)
3886 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
3887 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
3888 pHlp->pfnPrintf(pHlp, "\n");
3889 }
3890 }
3891}
3892
3893
3894/**
3895 * Structure used when disassembling and instructions in DBGF.
3896 * This is used so the reader function can get the stuff it needs.
3897 */
3898typedef struct CPUMDISASSTATE
3899{
3900 /** Pointer to the CPU structure. */
3901 PDISCPUSTATE pCpu;
3902 /** Pointer to the VM. */
3903 PVM pVM;
3904 /** Pointer to the VMCPU. */
3905 PVMCPU pVCpu;
3906 /** Pointer to the first byte in the segment. */
3907 RTGCUINTPTR GCPtrSegBase;
3908 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
3909 RTGCUINTPTR GCPtrSegEnd;
3910 /** The size of the segment minus 1. */
3911 RTGCUINTPTR cbSegLimit;
3912 /** Pointer to the current page - R3 Ptr. */
3913 void const *pvPageR3;
3914 /** Pointer to the current page - GC Ptr. */
3915 RTGCPTR pvPageGC;
3916 /** The lock information that PGMPhysReleasePageMappingLock needs. */
3917 PGMPAGEMAPLOCK PageMapLock;
3918 /** Whether the PageMapLock is valid or not. */
3919 bool fLocked;
3920 /** 64 bits mode or not. */
3921 bool f64Bits;
3922} CPUMDISASSTATE, *PCPUMDISASSTATE;
3923
3924
3925/**
3926 * @callback_method_impl{FNDISREADBYTES}
3927 */
3928static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
3929{
3930 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
3931 for (;;)
3932 {
3933 RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
3934
3935 /*
3936 * Need to update the page translation?
3937 */
3938 if ( !pState->pvPageR3
3939 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
3940 {
3941 int rc = VINF_SUCCESS;
3942
3943 /* translate the address */
3944 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
3945 if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
3946 && !HMIsEnabled(pState->pVM))
3947 {
3948 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
3949 if (!pState->pvPageR3)
3950 rc = VERR_INVALID_POINTER;
3951 }
3952 else
3953 {
3954 /* Release mapping lock previously acquired. */
3955 if (pState->fLocked)
3956 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
3957 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
3958 pState->fLocked = RT_SUCCESS_NP(rc);
3959 }
3960 if (RT_FAILURE(rc))
3961 {
3962 pState->pvPageR3 = NULL;
3963 return rc;
3964 }
3965 }
3966
3967 /*
3968 * Check the segment limit.
3969 */
3970 if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
3971 return VERR_OUT_OF_SELECTOR_BOUNDS;
3972
3973 /*
3974 * Calc how much we can read.
3975 */
3976 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
3977 if (!pState->f64Bits)
3978 {
3979 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
3980 if (cb > cbSeg && cbSeg)
3981 cb = cbSeg;
3982 }
3983 if (cb > cbMaxRead)
3984 cb = cbMaxRead;
3985
3986 /*
3987 * Read and advance or exit.
3988 */
3989 memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
3990 offInstr += (uint8_t)cb;
3991 if (cb >= cbMinRead)
3992 {
3993 pDis->cbCachedInstr = offInstr;
3994 return VINF_SUCCESS;
3995 }
3996 cbMinRead -= (uint8_t)cb;
3997 cbMaxRead -= (uint8_t)cb;
3998 }
3999}
4000
4001
4002/**
4003 * Disassemble an instruction and return the information in the provided structure.
4004 *
4005 * @returns VBox status code.
4006 * @param pVM Pointer to the VM.
4007 * @param pVCpu Pointer to the VMCPU.
4008 * @param pCtx Pointer to the guest CPU context.
4009 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
4010 * @param pCpu Disassembly state.
4011 * @param pszPrefix String prefix for logging (debug only).
4012 *
4013 */
4014VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
4015{
4016 CPUMDISASSTATE State;
4017 int rc;
4018
4019 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
4020 State.pCpu = pCpu;
4021 State.pvPageGC = 0;
4022 State.pvPageR3 = NULL;
4023 State.pVM = pVM;
4024 State.pVCpu = pVCpu;
4025 State.fLocked = false;
4026 State.f64Bits = false;
4027
4028 /*
4029 * Get selector information.
4030 */
4031 DISCPUMODE enmDisCpuMode;
4032 if ( (pCtx->cr0 & X86_CR0_PE)
4033 && pCtx->eflags.Bits.u1VM == 0)
4034 {
4035 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4036 {
4037# ifdef VBOX_WITH_RAW_MODE_NOT_R0
4038 CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, &pCtx->cs);
4039# endif
4040 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4041 return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
4042 }
4043 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
4044 State.GCPtrSegBase = pCtx->cs.u64Base;
4045 State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
4046 State.cbSegLimit = pCtx->cs.u32Limit;
4047 enmDisCpuMode = (State.f64Bits)
4048 ? DISCPUMODE_64BIT
4049 : pCtx->cs.Attr.n.u1DefBig
4050 ? DISCPUMODE_32BIT
4051 : DISCPUMODE_16BIT;
4052 }
4053 else
4054 {
4055 /* real or V86 mode */
4056 enmDisCpuMode = DISCPUMODE_16BIT;
4057 State.GCPtrSegBase = pCtx->cs.Sel * 16;
4058 State.GCPtrSegEnd = 0xFFFFFFFF;
4059 State.cbSegLimit = 0xFFFFFFFF;
4060 }
4061
4062 /*
4063 * Disassemble the instruction.
4064 */
4065 uint32_t cbInstr;
4066#ifndef LOG_ENABLED
4067 rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
4068 if (RT_SUCCESS(rc))
4069 {
4070#else
4071 char szOutput[160];
4072 rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
4073 pCpu, &cbInstr, szOutput, sizeof(szOutput));
4074 if (RT_SUCCESS(rc))
4075 {
4076 /* log it */
4077 if (pszPrefix)
4078 Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
4079 else
4080 Log(("%s", szOutput));
4081#endif
4082 rc = VINF_SUCCESS;
4083 }
4084 else
4085 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
4086
4087 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
4088 if (State.fLocked)
4089 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
4090
4091 return rc;
4092}
4093
4094
4095
4096/**
4097 * API for controlling a few of the CPU features found in CR4.
4098 *
4099 * Currently only X86_CR4_TSD is accepted as input.
4100 *
4101 * @returns VBox status code.
4102 *
4103 * @param pVM Pointer to the VM.
4104 * @param fOr The CR4 OR mask.
4105 * @param fAnd The CR4 AND mask.
4106 */
4107VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
4108{
4109 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
4110 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
4111
4112 pVM->cpum.s.CR4.OrMask &= fAnd;
4113 pVM->cpum.s.CR4.OrMask |= fOr;
4114
4115 return VINF_SUCCESS;
4116}
4117
4118
4119/**
4120 * Gets a pointer to the array of standard CPUID leaves.
4121 *
4122 * CPUMR3GetGuestCpuIdStdMax() give the size of the array.
4123 *
4124 * @returns Pointer to the standard CPUID leaves (read-only).
4125 * @param pVM Pointer to the VM.
4126 * @remark Intended for PATM.
4127 */
4128VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM)
4129{
4130 return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
4131}
4132
4133
4134/**
4135 * Gets a pointer to the array of extended CPUID leaves.
4136 *
4137 * CPUMGetGuestCpuIdExtMax() give the size of the array.
4138 *
4139 * @returns Pointer to the extended CPUID leaves (read-only).
4140 * @param pVM Pointer to the VM.
4141 * @remark Intended for PATM.
4142 */
4143VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM)
4144{
4145 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
4146}
4147
4148
4149/**
4150 * Gets a pointer to the array of centaur CPUID leaves.
4151 *
4152 * CPUMGetGuestCpuIdCentaurMax() give the size of the array.
4153 *
4154 * @returns Pointer to the centaur CPUID leaves (read-only).
4155 * @param pVM Pointer to the VM.
4156 * @remark Intended for PATM.
4157 */
4158VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM)
4159{
4160 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
4161}
4162
4163
4164/**
4165 * Gets a pointer to the default CPUID leaf.
4166 *
4167 * @returns Pointer to the default CPUID leaf (read-only).
4168 * @param pVM Pointer to the VM.
4169 * @remark Intended for PATM.
4170 */
4171VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM)
4172{
4173 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
4174}
4175
4176
4177/**
4178 * Transforms the guest CPU state to raw-ring mode.
4179 *
4180 * This function will change the any of the cs and ss register with DPL=0 to DPL=1.
4181 *
4182 * @returns VBox status. (recompiler failure)
4183 * @param pVCpu Pointer to the VMCPU.
4184 * @param pCtxCore The context core (for trap usage).
4185 * @see @ref pg_raw
4186 */
4187VMMR3DECL(int) CPUMR3RawEnter(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
4188{
4189 PVM pVM = pVCpu->CTX_SUFF(pVM);
4190
4191 Assert(!pVCpu->cpum.s.fRawEntered);
4192 Assert(!pVCpu->cpum.s.fRemEntered);
4193 if (!pCtxCore)
4194 pCtxCore = CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
4195
4196 /*
4197 * Are we in Ring-0?
4198 */
4199 if ( pCtxCore->ss.Sel && (pCtxCore->ss.Sel & X86_SEL_RPL) == 0
4200 && !pCtxCore->eflags.Bits.u1VM)
4201 {
4202 /*
4203 * Enter execution mode.
4204 */
4205 PATMRawEnter(pVM, pCtxCore);
4206
4207 /*
4208 * Set CPL to Ring-1.
4209 */
4210 pCtxCore->ss.Sel |= 1;
4211 if (pCtxCore->cs.Sel && (pCtxCore->cs.Sel & X86_SEL_RPL) == 0)
4212 pCtxCore->cs.Sel |= 1;
4213 }
4214 else
4215 {
4216 AssertMsg((pCtxCore->ss.Sel & X86_SEL_RPL) >= 2 || pCtxCore->eflags.Bits.u1VM,
4217 ("ring-1 code not supported\n"));
4218 /*
4219 * PATM takes care of IOPL and IF flags for Ring-3 and Ring-2 code as well.
4220 */
4221 PATMRawEnter(pVM, pCtxCore);
4222 }
4223
4224 /*
4225 * Assert sanity.
4226 */
4227 AssertMsg((pCtxCore->eflags.u32 & X86_EFL_IF), ("X86_EFL_IF is clear\n"));
4228 AssertReleaseMsg( pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss.Sel & X86_SEL_RPL)
4229 || pCtxCore->eflags.Bits.u1VM,
4230 ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss.Sel & X86_SEL_RPL));
4231 Assert((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)) == (X86_CR0_PG | X86_CR0_PE | X86_CR0_WP));
4232
4233 pCtxCore->eflags.u32 |= X86_EFL_IF; /* paranoia */
4234
4235 pVCpu->cpum.s.fRawEntered = true;
4236 return VINF_SUCCESS;
4237}
4238
4239
4240/**
4241 * Transforms the guest CPU state from raw-ring mode to correct values.
4242 *
4243 * This function will change any selector registers with DPL=1 to DPL=0.
4244 *
4245 * @returns Adjusted rc.
4246 * @param pVCpu Pointer to the VMCPU.
4247 * @param rc Raw mode return code
4248 * @param pCtxCore The context core (for trap usage).
4249 * @see @ref pg_raw
4250 */
4251VMMR3DECL(int) CPUMR3RawLeave(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, int rc)
4252{
4253 PVM pVM = pVCpu->CTX_SUFF(pVM);
4254
4255 /*
4256 * Don't leave if we've already left (in GC).
4257 */
4258 Assert(pVCpu->cpum.s.fRawEntered);
4259 Assert(!pVCpu->cpum.s.fRemEntered);
4260 if (!pVCpu->cpum.s.fRawEntered)
4261 return rc;
4262 pVCpu->cpum.s.fRawEntered = false;
4263
4264 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
4265 if (!pCtxCore)
4266 pCtxCore = CPUMCTX2CORE(pCtx);
4267 Assert(pCtxCore->eflags.Bits.u1VM || (pCtxCore->ss.Sel & X86_SEL_RPL));
4268 AssertMsg(pCtxCore->eflags.Bits.u1VM || pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss.Sel & X86_SEL_RPL),
4269 ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss.Sel & X86_SEL_RPL));
4270
4271 /*
4272 * Are we executing in raw ring-1?
4273 */
4274 if ( (pCtxCore->ss.Sel & X86_SEL_RPL) == 1
4275 && !pCtxCore->eflags.Bits.u1VM)
4276 {
4277 /*
4278 * Leave execution mode.
4279 */
4280 PATMRawLeave(pVM, pCtxCore, rc);
4281 /* Not quite sure if this is really required, but shouldn't harm (too much anyways). */
4282 /** @todo See what happens if we remove this. */
4283 if ((pCtxCore->ds.Sel & X86_SEL_RPL) == 1)
4284 pCtxCore->ds.Sel &= ~X86_SEL_RPL;
4285 if ((pCtxCore->es.Sel & X86_SEL_RPL) == 1)
4286 pCtxCore->es.Sel &= ~X86_SEL_RPL;
4287 if ((pCtxCore->fs.Sel & X86_SEL_RPL) == 1)
4288 pCtxCore->fs.Sel &= ~X86_SEL_RPL;
4289 if ((pCtxCore->gs.Sel & X86_SEL_RPL) == 1)
4290 pCtxCore->gs.Sel &= ~X86_SEL_RPL;
4291
4292 /*
4293 * Ring-1 selector => Ring-0.
4294 */
4295 pCtxCore->ss.Sel &= ~X86_SEL_RPL;
4296 if ((pCtxCore->cs.Sel & X86_SEL_RPL) == 1)
4297 pCtxCore->cs.Sel &= ~X86_SEL_RPL;
4298 }
4299 else
4300 {
4301 /*
4302 * PATM is taking care of the IOPL and IF flags for us.
4303 */
4304 PATMRawLeave(pVM, pCtxCore, rc);
4305 if (!pCtxCore->eflags.Bits.u1VM)
4306 {
4307 /** @todo See what happens if we remove this. */
4308 if ((pCtxCore->ds.Sel & X86_SEL_RPL) == 1)
4309 pCtxCore->ds.Sel &= ~X86_SEL_RPL;
4310 if ((pCtxCore->es.Sel & X86_SEL_RPL) == 1)
4311 pCtxCore->es.Sel &= ~X86_SEL_RPL;
4312 if ((pCtxCore->fs.Sel & X86_SEL_RPL) == 1)
4313 pCtxCore->fs.Sel &= ~X86_SEL_RPL;
4314 if ((pCtxCore->gs.Sel & X86_SEL_RPL) == 1)
4315 pCtxCore->gs.Sel &= ~X86_SEL_RPL;
4316 }
4317 }
4318
4319 return rc;
4320}
4321
4322
4323/**
4324 * Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
4325 *
4326 * Only REM should ever call this function!
4327 *
4328 * @returns The changed flags.
4329 * @param pVCpu Pointer to the VMCPU.
4330 * @param puCpl Where to return the current privilege level (CPL).
4331 */
4332VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
4333{
4334 Assert(!pVCpu->cpum.s.fRawEntered);
4335 Assert(!pVCpu->cpum.s.fRemEntered);
4336
4337 /*
4338 * Get the CPL first.
4339 */
4340 *puCpl = CPUMGetGuestCPL(pVCpu);
4341
4342 /*
4343 * Get and reset the flags.
4344 */
4345 uint32_t fFlags = pVCpu->cpum.s.fChanged;
4346 pVCpu->cpum.s.fChanged = 0;
4347
4348 /** @todo change the switcher to use the fChanged flags. */
4349 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
4350 {
4351 fFlags |= CPUM_CHANGED_FPU_REM;
4352 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
4353 }
4354
4355 pVCpu->cpum.s.fRemEntered = true;
4356 return fFlags;
4357}
4358
4359
4360/**
4361 * Leaves REM.
4362 *
4363 * @param pVCpu Pointer to the VMCPU.
4364 * @param fNoOutOfSyncSels This is @c false if there are out of sync
4365 * registers.
4366 */
4367VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
4368{
4369 Assert(!pVCpu->cpum.s.fRawEntered);
4370 Assert(pVCpu->cpum.s.fRemEntered);
4371
4372 pVCpu->cpum.s.fRemEntered = false;
4373}
4374
4375
4376/**
4377 * Called when the ring-3 init phase completes.
4378 *
4379 * @returns VBox status code.
4380 * @param pVM Pointer to the VM.
4381 */
4382VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM)
4383{
4384 for (VMCPUID i = 0; i < pVM->cCpus; i++)
4385 {
4386 /* Cache the APIC base (from the APIC device) once it has been initialized. */
4387 PDMApicGetBase(&pVM->aCpus[i], &pVM->aCpus[i].cpum.s.Guest.msrApicBase);
4388 Log(("CPUMR3InitCompleted pVM=%p APIC base[%u]=%RX64\n", pVM, (unsigned)i, pVM->aCpus[i].cpum.s.Guest.msrApicBase));
4389 }
4390 return VINF_SUCCESS;
4391}
4392
4393/**
4394 * Called when the ring-0 init phases comleted.
4395 *
4396 * @param pVM Pointer to the VM.
4397 */
4398VMMR3DECL(void) CPUMR3LogCpuIds(PVM pVM)
4399{
4400 /*
4401 * Log the cpuid.
4402 */
4403 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
4404 RTCPUSET OnlineSet;
4405 LogRel(("Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
4406 (unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
4407 RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
4408 LogRel(("************************* CPUID dump ************************\n"));
4409 DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
4410 LogRel(("\n"));
4411 DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
4412 RTLogRelSetBuffering(fOldBuffered);
4413 LogRel(("******************** End of CPUID dump **********************\n"));
4414}
注意: 瀏覽 TracBrowser 來幫助您使用儲存庫瀏覽器

© 2025 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette