CPUM.cpp@ 40170

最後變更在這個檔案從40170是 40170,由 vboxsync 提交於 13 年前
MSRs and MTRRs, CPUM saved state changed. (linux 2.4.31 seems to ignore the capabilites when it comes to fixed MTRRs.)
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1	/* $Id: CPUM.cpp 40170 2012-02-17 14:22:26Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2010 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.alldomusa.eu.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_cpum CPUM - CPU Monitor / Manager
19	*
20	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
21	* also responsible for lazy FPU handling and some of the context loading
22	* in raw mode.
23	*
24	* There are three CPU contexts, the most important one is the guest one (GC).
25	* When running in raw-mode (RC) there is a special hyper context for the VMM
26	* part that floats around inside the guest address space. When running in
27	* raw-mode, CPUM also maintains a host context for saving and restoring
28	* registers across world switches. This latter is done in cooperation with the
29	* world switcher (@see pg_vmm).
30	*
31	* @see grp_cpum
32	*/
33
34	/*******************************************************************************
35	* Header Files *
36	*******************************************************************************/
37	#define LOG_GROUP LOG_GROUP_CPUM
38	#include <VBox/vmm/cpum.h>
39	#include <VBox/vmm/cpumdis.h>
40	#include <VBox/vmm/pgm.h>
41	#include <VBox/vmm/mm.h>
42	#include <VBox/vmm/selm.h>
43	#include <VBox/vmm/dbgf.h>
44	#include <VBox/vmm/patm.h>
45	#include <VBox/vmm/hwaccm.h>
46	#include <VBox/vmm/ssm.h>
47	#include "CPUMInternal.h"
48	#include <VBox/vmm/vm.h>
49
50	#include <VBox/param.h>
51	#include <VBox/dis.h>
52	#include <VBox/err.h>
53	#include <VBox/log.h>
54	#include <iprt/assert.h>
55	#include <iprt/asm-amd64-x86.h>
56	#include <iprt/string.h>
57	#include <iprt/mp.h>
58	#include <iprt/cpuset.h>
59	#include "internal/pgm.h"
60
61
62	/*******************************************************************************
63	* Defined Constants And Macros *
64	*******************************************************************************/
65	/** The current saved state version. */
66	#define CPUM_SAVED_STATE_VERSION 13
67	/** The saved state version before introducing the MSR size field. */
68	#define CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE 12
69	/** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
70	* selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
71	#define CPUM_SAVED_STATE_VERSION_VER3_2 11
72	/** The saved state version of 3.0 and 3.1 trunk before the teleportation
73	* changes. */
74	#define CPUM_SAVED_STATE_VERSION_VER3_0 10
75	/** The saved state version for the 2.1 trunk before the MSR changes. */
76	#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
77	/** The saved state version of 2.0, used for backwards compatibility. */
78	#define CPUM_SAVED_STATE_VERSION_VER2_0 8
79	/** The saved state version of 1.6, used for backwards compatibility. */
80	#define CPUM_SAVED_STATE_VERSION_VER1_6 6
81
82
83	/*******************************************************************************
84	* Structures and Typedefs *
85	*******************************************************************************/
86
87	/**
88	* What kind of cpu info dump to perform.
89	*/
90	typedef enum CPUMDUMPTYPE
91	{
92	CPUMDUMPTYPE_TERSE,
93	CPUMDUMPTYPE_DEFAULT,
94	CPUMDUMPTYPE_VERBOSE
95	} CPUMDUMPTYPE;
96	/** Pointer to a cpu info dump type. */
97	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
98
99
100	/*******************************************************************************
101	* Internal Functions *
102	*******************************************************************************/
103	static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
104	static int cpumR3CpuIdInit(PVM pVM);
105	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
106	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
107	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
108	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
109	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
110	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
111	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
112	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
113	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
114	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
115	static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
116
117
118	/**
119	* Initializes the CPUM.
120	*
121	* @returns VBox status code.
122	* @param pVM The VM to operate on.
123	*/
124	VMMR3DECL(int) CPUMR3Init(PVM pVM)
125	{
126	LogFlow(("CPUMR3Init\n"));
127
128	/*
129	* Assert alignment and sizes.
130	*/
131	AssertCompileMemberAlignment(VM, cpum.s, 32);
132	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
133	AssertCompileSizeAlignment(CPUMCTX, 64);
134	AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
135	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
136	AssertCompileMemberAlignment(VM, cpum, 64);
137	AssertCompileMemberAlignment(VM, aCpus, 64);
138	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
139	AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
140
141	/* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
142	pVM->cpum.s.offCPUMCPU0 = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
143	Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
144
145	/* Calculate the offset from CPUMCPU to CPUM. */
146	for (VMCPUID i = 0; i < pVM->cCpus; i++)
147	{
148	PVMCPU pVCpu = &pVM->aCpus[i];
149
150	/*
151	* Setup any fixed pointers and offsets.
152	*/
153	pVCpu->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
154	pVCpu->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper));
155
156	pVCpu->cpum.s.offCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
157	Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
158	}
159
160	/*
161	* Check that the CPU supports the minimum features we require.
162	*/
163	if (!ASMHasCpuId())
164	{
165	Log(("The CPU doesn't support CPUID!\n"));
166	return VERR_UNSUPPORTED_CPU;
167	}
168	ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
169	ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
170
171	/* Setup the CR4 AND and OR masks used in the switcher */
172	/* Depends on the presence of FXSAVE(SSE) support on the host CPU */
173	if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
174	{
175	Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
176	/* No FXSAVE implies no SSE */
177	pVM->cpum.s.CR4.AndMask = X86_CR4_PVI \| X86_CR4_VME;
178	pVM->cpum.s.CR4.OrMask = 0;
179	}
180	else
181	{
182	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
183	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
184	}
185
186	if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
187	{
188	Log(("The CPU doesn't support MMX!\n"));
189	return VERR_UNSUPPORTED_CPU;
190	}
191	if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
192	{
193	Log(("The CPU doesn't support TSC!\n"));
194	return VERR_UNSUPPORTED_CPU;
195	}
196	/* Bogus on AMD? */
197	if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
198	Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
199
200	/*
201	* Detect the host CPU vendor.
202	* (The guest CPU vendor is re-detected later on.)
203	*/
204	uint32_t uEAX, uEBX, uECX, uEDX;
205	ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
206	pVM->cpum.s.enmHostCpuVendor = cpumR3DetectVendor(uEAX, uEBX, uECX, uEDX);
207	pVM->cpum.s.enmGuestCpuVendor = pVM->cpum.s.enmHostCpuVendor;
208
209	/*
210	* Setup hypervisor startup values.
211	*/
212
213	/*
214	* Register saved state data item.
215	*/
216	int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
217	NULL, cpumR3LiveExec, NULL,
218	NULL, cpumR3SaveExec, NULL,
219	cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
220	if (RT_FAILURE(rc))
221	return rc;
222
223	/*
224	* Register info handlers and registers with the debugger facility.
225	*/
226	DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
227	DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
228	DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
229	DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
230	DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
231	DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
232
233	rc = cpumR3DbgInit(pVM);
234	if (RT_FAILURE(rc))
235	return rc;
236
237	/*
238	* Initialize the Guest CPUID state.
239	*/
240	rc = cpumR3CpuIdInit(pVM);
241	if (RT_FAILURE(rc))
242	return rc;
243	CPUMR3Reset(pVM);
244	return VINF_SUCCESS;
245	}
246
247
248	/**
249	* Detect the CPU vendor give n the
250	*
251	* @returns The vendor.
252	* @param uEAX EAX from CPUID(0).
253	* @param uEBX EBX from CPUID(0).
254	* @param uECX ECX from CPUID(0).
255	* @param uEDX EDX from CPUID(0).
256	*/
257	static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
258	{
259	if ( uEAX >= 1
260	&& uEBX == X86_CPUID_VENDOR_AMD_EBX
261	&& uECX == X86_CPUID_VENDOR_AMD_ECX
262	&& uEDX == X86_CPUID_VENDOR_AMD_EDX)
263	return CPUMCPUVENDOR_AMD;
264
265	if ( uEAX >= 1
266	&& uEBX == X86_CPUID_VENDOR_INTEL_EBX
267	&& uECX == X86_CPUID_VENDOR_INTEL_ECX
268	&& uEDX == X86_CPUID_VENDOR_INTEL_EDX)
269	return CPUMCPUVENDOR_INTEL;
270
271	/** @todo detect the other buggers... */
272	return CPUMCPUVENDOR_UNKNOWN;
273	}
274
275
276	/**
277	* Fetches overrides for a CPUID leaf.
278	*
279	* @returns VBox status code.
280	* @param pLeaf The leaf to load the overrides into.
281	* @param pCfgNode The CFGM node containing the overrides
282	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
283	* @param iLeaf The CPUID leaf number.
284	*/
285	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
286	{
287	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
288	if (pLeafNode)
289	{
290	uint32_t u32;
291	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
292	if (RT_SUCCESS(rc))
293	pLeaf->eax = u32;
294	else
295	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
296
297	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
298	if (RT_SUCCESS(rc))
299	pLeaf->ebx = u32;
300	else
301	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
302
303	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
304	if (RT_SUCCESS(rc))
305	pLeaf->ecx = u32;
306	else
307	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
308
309	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
310	if (RT_SUCCESS(rc))
311	pLeaf->edx = u32;
312	else
313	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
314
315	}
316	return VINF_SUCCESS;
317	}
318
319
320	/**
321	* Load the overrides for a set of CPUID leaves.
322	*
323	* @returns VBox status code.
324	* @param paLeaves The leaf array.
325	* @param cLeaves The number of leaves.
326	* @param uStart The start leaf number.
327	* @param pCfgNode The CFGM node containing the overrides
328	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
329	*/
330	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
331	{
332	for (uint32_t i = 0; i < cLeaves; i++)
333	{
334	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
335	if (RT_FAILURE(rc))
336	return rc;
337	}
338
339	return VINF_SUCCESS;
340	}
341
342	/**
343	* Init a set of host CPUID leaves.
344	*
345	* @returns VBox status code.
346	* @param paLeaves The leaf array.
347	* @param cLeaves The number of leaves.
348	* @param uStart The start leaf number.
349	* @param pCfgNode The /CPUM/HostCPUID/ node.
350	*/
351	static int cpumR3CpuIdInitHostSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
352	{
353	/* Using the ECX variant for all of them can't hurt... */
354	for (uint32_t i = 0; i < cLeaves; i++)
355	ASMCpuId_Idx_ECX(uStart + i, 0, &paLeaves[i].eax, &paLeaves[i].ebx, &paLeaves[i].ecx, &paLeaves[i].edx);
356
357	/* Load CPUID leaf override; we currently don't care if the user
358	specifies features the host CPU doesn't support. */
359	return cpumR3CpuIdInitLoadOverrideSet(uStart, paLeaves, cLeaves, pCfgNode);
360	}
361
362
363	/**
364	* Initializes the emulated CPU's cpuid information.
365	*
366	* @returns VBox status code.
367	* @param pVM The VM to operate on.
368	*/
369	static int cpumR3CpuIdInit(PVM pVM)
370	{
371	PCPUM pCPUM = &pVM->cpum.s;
372	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
373	uint32_t i;
374	int rc;
375
376	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, LeafSuffReg, FeatNm, fMask, uValue) \
377	if (pCPUM->u8PortableCpuIdLevel >= (Lvl) && (pCPUM->aGuestCpuId##LeafSuffReg & (fMask)) == (uValue) ) \
378	{ \
379	LogRel(("PortableCpuId: " #LeafSuffReg "[" #FeatNm "]: %#x -> 0\n", pCPUM->aGuestCpuId##LeafSuffReg & (fMask))); \
380	pCPUM->aGuestCpuId##LeafSuffReg &= ~(uint32_t)(fMask); \
381	}
382	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, LeafSuffReg, FeatNm, fBitMask) \
383	if (pCPUM->u8PortableCpuIdLevel >= (Lvl) && (pCPUM->aGuestCpuId##LeafSuffReg & (fBitMask)) ) \
384	{ \
385	LogRel(("PortableCpuId: " #LeafSuffReg "[" #FeatNm "]: 1 -> 0\n")); \
386	pCPUM->aGuestCpuId##LeafSuffReg &= ~(uint32_t)(fBitMask); \
387	}
388
389	/*
390	* Read the configuration.
391	*/
392	/** @cfgm{CPUM/SyntheticCpu, boolean, false}
393	* Enables the Synthetic CPU. The Vendor ID and Processor Name are
394	* completely overridden by VirtualBox custom strings. Some
395	* CPUID information is withheld, like the cache info. */
396	rc = CFGMR3QueryBoolDef(pCpumCfg, "SyntheticCpu", &pCPUM->fSyntheticCpu, false);
397	AssertRCReturn(rc, rc);
398
399	/** @cfgm{CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
400	* When non-zero CPUID features that could cause portability issues will be
401	* stripped. The higher the value the more features gets stripped. Higher
402	* values should only be used when older CPUs are involved since it may
403	* harm performance and maybe also cause problems with specific guests. */
404	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pCPUM->u8PortableCpuIdLevel, 0);
405	AssertRCReturn(rc, rc);
406
407	AssertLogRelReturn(!pCPUM->fSyntheticCpu \|\| !pCPUM->u8PortableCpuIdLevel, VERR_CPUM_INCOMPATIBLE_CONFIG);
408
409	/*
410	* Get the host CPUID leaves and redetect the guest CPU vendor (could've
411	* been overridden).
412	*/
413	/** @cfgm{CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
414	* Overrides the host CPUID leaf values used for calculating the guest CPUID
415	* leaves. This can be used to preserve the CPUID values when moving a VM
416	* to a different machine. Another use is restricting (or extending) the
417	* feature set exposed to the guest. */
418	PCFGMNODE pHostOverrideCfg = CFGMR3GetChild(pCpumCfg, "HostCPUID");
419	rc = cpumR3CpuIdInitHostSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pHostOverrideCfg);
420	AssertRCReturn(rc, rc);
421	rc = cpumR3CpuIdInitHostSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pHostOverrideCfg);
422	AssertRCReturn(rc, rc);
423	rc = cpumR3CpuIdInitHostSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pHostOverrideCfg);
424	AssertRCReturn(rc, rc);
425
426	pCPUM->enmGuestCpuVendor = cpumR3DetectVendor(pCPUM->aGuestCpuIdStd[0].eax, pCPUM->aGuestCpuIdStd[0].ebx,
427	pCPUM->aGuestCpuIdStd[0].ecx, pCPUM->aGuestCpuIdStd[0].edx);
428
429	/*
430	* Determine the default leaf.
431	*
432	* Intel returns values of the highest standard function, while AMD
433	* returns zeros. VIA on the other hand seems to returning nothing or
434	* perhaps some random garbage, we don't try to duplicate this behavior.
435	*/
436	ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10, /** @todo r=bird: Use the host value here in case of overrides and more than 10 leaves being stripped already. */
437	&pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
438	&pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
439
440
441	/* Cpuid 1 & 0x80000001:
442	* Only report features we can support.
443	*
444	* Note! When enabling new features the Synthetic CPU and Portable CPUID
445	* options may require adjusting (i.e. stripping what was enabled).
446	*/
447	pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
448	\| X86_CPUID_FEATURE_EDX_VME
449	\| X86_CPUID_FEATURE_EDX_DE
450	\| X86_CPUID_FEATURE_EDX_PSE
451	\| X86_CPUID_FEATURE_EDX_TSC
452	\| X86_CPUID_FEATURE_EDX_MSR
453	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
454	\| X86_CPUID_FEATURE_EDX_MCE
455	\| X86_CPUID_FEATURE_EDX_CX8
456	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
457	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
458	//\| X86_CPUID_FEATURE_EDX_SEP
459	\| X86_CPUID_FEATURE_EDX_MTRR
460	\| X86_CPUID_FEATURE_EDX_PGE
461	\| X86_CPUID_FEATURE_EDX_MCA
462	\| X86_CPUID_FEATURE_EDX_CMOV
463	\| X86_CPUID_FEATURE_EDX_PAT
464	\| X86_CPUID_FEATURE_EDX_PSE36
465	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
466	\| X86_CPUID_FEATURE_EDX_CLFSH
467	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
468	//\| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
469	\| X86_CPUID_FEATURE_EDX_MMX
470	\| X86_CPUID_FEATURE_EDX_FXSR
471	\| X86_CPUID_FEATURE_EDX_SSE
472	\| X86_CPUID_FEATURE_EDX_SSE2
473	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
474	//\| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
475	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
476	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
477	\| 0;
478	pCPUM->aGuestCpuIdStd[1].ecx &= 0
479	\| X86_CPUID_FEATURE_ECX_SSE3
480	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
481	\| ((pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
482	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
483	//\| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
484	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
485	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
486	\| X86_CPUID_FEATURE_ECX_SSSE3
487	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
488	//\| X86_CPUID_FEATURE_ECX_CX16 - no cmpxchg16b
489	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
490	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
491	/* ECX Bit 21 - x2APIC support - not yet. */
492	// \| X86_CPUID_FEATURE_ECX_X2APIC
493	/* ECX Bit 23 - POPCNT instruction. */
494	//\| X86_CPUID_FEATURE_ECX_POPCNT
495	\| 0;
496	if (pCPUM->u8PortableCpuIdLevel > 0)
497	{
498	PORTABLE_CLEAR_BITS_WHEN(1, Std[1].eax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
499	PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
500	PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
501	PORTABLE_DISABLE_FEATURE_BIT(2, Std[1].edx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
502	PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, SSE, X86_CPUID_FEATURE_EDX_SSE);
503	PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
504	PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
505
506	Assert(!(pCPUM->aGuestCpuIdStd[1].edx & ( X86_CPUID_FEATURE_EDX_SEP
507	\| X86_CPUID_FEATURE_EDX_PSN
508	\| X86_CPUID_FEATURE_EDX_DS
509	\| X86_CPUID_FEATURE_EDX_ACPI
510	\| X86_CPUID_FEATURE_EDX_SS
511	\| X86_CPUID_FEATURE_EDX_TM
512	\| X86_CPUID_FEATURE_EDX_PBE
513	)));
514	Assert(!(pCPUM->aGuestCpuIdStd[1].ecx & ( X86_CPUID_FEATURE_ECX_PCLMUL
515	\| X86_CPUID_FEATURE_ECX_DTES64
516	\| X86_CPUID_FEATURE_ECX_CPLDS
517	\| X86_CPUID_FEATURE_ECX_VMX
518	\| X86_CPUID_FEATURE_ECX_SMX
519	\| X86_CPUID_FEATURE_ECX_EST
520	\| X86_CPUID_FEATURE_ECX_TM2
521	\| X86_CPUID_FEATURE_ECX_CNTXID
522	\| X86_CPUID_FEATURE_ECX_FMA
523	\| X86_CPUID_FEATURE_ECX_CX16
524	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
525	\| X86_CPUID_FEATURE_ECX_PDCM
526	\| X86_CPUID_FEATURE_ECX_DCA
527	\| X86_CPUID_FEATURE_ECX_MOVBE
528	\| X86_CPUID_FEATURE_ECX_AES
529	\| X86_CPUID_FEATURE_ECX_POPCNT
530	\| X86_CPUID_FEATURE_ECX_XSAVE
531	\| X86_CPUID_FEATURE_ECX_OSXSAVE
532	\| X86_CPUID_FEATURE_ECX_AVX
533	)));
534	}
535
536	/* Cpuid 0x80000001:
537	* Only report features we can support.
538	*
539	* Note! When enabling new features the Synthetic CPU and Portable CPUID
540	* options may require adjusting (i.e. stripping what was enabled).
541	*
542	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
543	*/
544	pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
545	\| X86_CPUID_AMD_FEATURE_EDX_VME
546	\| X86_CPUID_AMD_FEATURE_EDX_DE
547	\| X86_CPUID_AMD_FEATURE_EDX_PSE
548	\| X86_CPUID_AMD_FEATURE_EDX_TSC
549	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
550	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
551	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
552	\| X86_CPUID_AMD_FEATURE_EDX_CX8
553	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
554	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
555	//\| X86_CPUID_AMD_FEATURE_EDX_SEP
556	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
557	\| X86_CPUID_AMD_FEATURE_EDX_PGE
558	\| X86_CPUID_AMD_FEATURE_EDX_MCA
559	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
560	\| X86_CPUID_AMD_FEATURE_EDX_PAT
561	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
562	//\| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
563	//\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
564	\| X86_CPUID_AMD_FEATURE_EDX_MMX
565	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
566	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
567	//\| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
568	//\| X86_CPUID_AMD_FEATURE_EDX_RDTSCP - AMD only; turned on when necessary
569	//\| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - turned on when necessary
570	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
571	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
572	\| 0;
573	pCPUM->aGuestCpuIdExt[1].ecx &= 0
574	//\| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
575	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL
576	//\| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
577	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
578	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
579	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
580	//\| X86_CPUID_AMD_FEATURE_ECX_ABM
581	//\| X86_CPUID_AMD_FEATURE_ECX_SSE4A
582	//\| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
583	//\| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
584	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
585	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
586	//\| X86_CPUID_AMD_FEATURE_ECX_SSE5
587	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
588	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
589	\| 0;
590	if (pCPUM->u8PortableCpuIdLevel > 0)
591	{
592	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].ecx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
593	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
594	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
595	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
596	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, RDTSCP, X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
597	PORTABLE_DISABLE_FEATURE_BIT(2, Ext[1].ecx, LAHF_SAHF, X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF);
598	PORTABLE_DISABLE_FEATURE_BIT(3, Ext[1].ecx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
599
600	Assert(!(pCPUM->aGuestCpuIdExt[1].ecx & ( X86_CPUID_AMD_FEATURE_ECX_CMPL
601	\| X86_CPUID_AMD_FEATURE_ECX_SVM
602	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
603	\| X86_CPUID_AMD_FEATURE_ECX_CR8L
604	\| X86_CPUID_AMD_FEATURE_ECX_ABM
605	\| X86_CPUID_AMD_FEATURE_ECX_SSE4A
606	\| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
607	\| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
608	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
609	\| X86_CPUID_AMD_FEATURE_ECX_IBS
610	\| X86_CPUID_AMD_FEATURE_ECX_SSE5
611	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
612	\| X86_CPUID_AMD_FEATURE_ECX_WDT
613	\| UINT32_C(0xffffc000)
614	)));
615	Assert(!(pCPUM->aGuestCpuIdExt[1].edx & ( RT_BIT(10)
616	\| X86_CPUID_AMD_FEATURE_EDX_SEP
617	\| RT_BIT(18)
618	\| RT_BIT(19)
619	\| RT_BIT(21)
620	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
621	\| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
622	\| RT_BIT(28)
623	)));
624	}
625
626	/*
627	* Apply the Synthetic CPU modifications. (TODO: move this up)
628	*/
629	if (pCPUM->fSyntheticCpu)
630	{
631	static const char s_szVendor[13] = "VirtualBox ";
632	static const char s_szProcessor[48] = "VirtualBox SPARCx86 Processor v1000 "; /* includes null terminator */
633
634	pCPUM->enmGuestCpuVendor = CPUMCPUVENDOR_SYNTHETIC;
635
636	/* Limit the nr of standard leaves; 5 for monitor/mwait */
637	pCPUM->aGuestCpuIdStd[0].eax = RT_MIN(pCPUM->aGuestCpuIdStd[0].eax, 5);
638
639	/* 0: Vendor */
640	pCPUM->aGuestCpuIdStd[0].ebx = pCPUM->aGuestCpuIdExt[0].ebx = ((uint32_t *)s_szVendor)[0];
641	pCPUM->aGuestCpuIdStd[0].ecx = pCPUM->aGuestCpuIdExt[0].ecx = ((uint32_t *)s_szVendor)[2];
642	pCPUM->aGuestCpuIdStd[0].edx = pCPUM->aGuestCpuIdExt[0].edx = ((uint32_t *)s_szVendor)[1];
643
644	/* 1.eax: Version information. family : model : stepping */
645	pCPUM->aGuestCpuIdStd[1].eax = (0xf << 8) + (0x1 << 4) + 1;
646
647	/* Leaves 2 - 4 are Intel only - zero them out */
648	memset(&pCPUM->aGuestCpuIdStd[2], 0, sizeof(pCPUM->aGuestCpuIdStd[2]));
649	memset(&pCPUM->aGuestCpuIdStd[3], 0, sizeof(pCPUM->aGuestCpuIdStd[3]));
650	memset(&pCPUM->aGuestCpuIdStd[4], 0, sizeof(pCPUM->aGuestCpuIdStd[4]));
651
652	/* Leaf 5 = monitor/mwait */
653
654	/* Limit the nr of extended leaves: 0x80000008 to include the max virtual and physical address size (64 bits guests). */
655	pCPUM->aGuestCpuIdExt[0].eax = RT_MIN(pCPUM->aGuestCpuIdExt[0].eax, 0x80000008);
656	/* AMD only - set to zero. */
657	pCPUM->aGuestCpuIdExt[0].ebx = pCPUM->aGuestCpuIdExt[0].ecx = pCPUM->aGuestCpuIdExt[0].edx = 0;
658
659	/* 0x800000001: AMD only; shared feature bits are set dynamically. */
660	memset(&pCPUM->aGuestCpuIdExt[1], 0, sizeof(pCPUM->aGuestCpuIdExt[1]));
661
662	/* 0x800000002-4: Processor Name String Identifier. */
663	pCPUM->aGuestCpuIdExt[2].eax = ((uint32_t *)s_szProcessor)[0];
664	pCPUM->aGuestCpuIdExt[2].ebx = ((uint32_t *)s_szProcessor)[1];
665	pCPUM->aGuestCpuIdExt[2].ecx = ((uint32_t *)s_szProcessor)[2];
666	pCPUM->aGuestCpuIdExt[2].edx = ((uint32_t *)s_szProcessor)[3];
667	pCPUM->aGuestCpuIdExt[3].eax = ((uint32_t *)s_szProcessor)[4];
668	pCPUM->aGuestCpuIdExt[3].ebx = ((uint32_t *)s_szProcessor)[5];
669	pCPUM->aGuestCpuIdExt[3].ecx = ((uint32_t *)s_szProcessor)[6];
670	pCPUM->aGuestCpuIdExt[3].edx = ((uint32_t *)s_szProcessor)[7];
671	pCPUM->aGuestCpuIdExt[4].eax = ((uint32_t *)s_szProcessor)[8];
672	pCPUM->aGuestCpuIdExt[4].ebx = ((uint32_t *)s_szProcessor)[9];
673	pCPUM->aGuestCpuIdExt[4].ecx = ((uint32_t *)s_szProcessor)[10];
674	pCPUM->aGuestCpuIdExt[4].edx = ((uint32_t *)s_szProcessor)[11];
675
676	/* 0x800000005-7 - reserved -> zero */
677	memset(&pCPUM->aGuestCpuIdExt[5], 0, sizeof(pCPUM->aGuestCpuIdExt[5]));
678	memset(&pCPUM->aGuestCpuIdExt[6], 0, sizeof(pCPUM->aGuestCpuIdExt[6]));
679	memset(&pCPUM->aGuestCpuIdExt[7], 0, sizeof(pCPUM->aGuestCpuIdExt[7]));
680
681	/* 0x800000008: only the max virtual and physical address size. */
682	pCPUM->aGuestCpuIdExt[8].ecx = pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
683	}
684
685	/*
686	* Hide HTT, multicode, SMP, whatever.
687	* (APIC-ID := 0 and #LogCpus := 0)
688	*/
689	pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
690	#ifdef VBOX_WITH_MULTI_CORE
691	if ( pCPUM->enmGuestCpuVendor != CPUMCPUVENDOR_SYNTHETIC
692	&& pVM->cCpus > 1)
693	{
694	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU core times the number of CPU cores per processor */
695	pCPUM->aGuestCpuIdStd[1].ebx \|= (pVM->cCpus << 16);
696	pCPUM->aGuestCpuIdStd[1].edx \|= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading or multi-core CPUs */
697	}
698	#endif
699
700	/* Cpuid 2:
701	* Intel: Cache and TLB information
702	* AMD: Reserved
703	* Safe to expose; restrict the number of calls to 1 for the portable case.
704	*/
705	if ( pCPUM->u8PortableCpuIdLevel > 0
706	&& pCPUM->aGuestCpuIdStd[0].eax >= 2
707	&& (pCPUM->aGuestCpuIdStd[2].eax & 0xff) > 1)
708	{
709	LogRel(("PortableCpuId: Std[2].al: %d -> 1\n", pCPUM->aGuestCpuIdStd[2].eax & 0xff));
710	pCPUM->aGuestCpuIdStd[2].eax &= UINT32_C(0xfffffffe);
711	}
712
713	/* Cpuid 3:
714	* Intel: EAX, EBX - reserved (transmeta uses these)
715	* ECX, EDX - Processor Serial Number if available, otherwise reserved
716	* AMD: Reserved
717	* Safe to expose
718	*/
719	if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
720	{
721	pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
722	if (pCPUM->u8PortableCpuIdLevel > 0)
723	pCPUM->aGuestCpuIdStd[3].eax = pCPUM->aGuestCpuIdStd[3].ebx = 0;
724	}
725
726	/* Cpuid 4:
727	* Intel: Deterministic Cache Parameters Leaf
728	* Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
729	* AMD: Reserved
730	* Safe to expose, except for EAX:
731	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
732	* Bits 31-26: Maximum number of processor cores in this physical package**
733	* Note: These SMP values are constant regardless of ECX
734	*/
735	pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
736	pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
737	#ifdef VBOX_WITH_MULTI_CORE
738	if ( pVM->cCpus > 1
739	&& pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
740	{
741	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
742	/* One logical processor with possibly multiple cores. */
743	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
744	pCPUM->aGuestCpuIdStd[4].eax \|= ((pVM->cCpus - 1) << 26); /* 6 bits only -> 64 cores! */
745	}
746	#endif
747
748	/* Cpuid 5: Monitor/mwait Leaf
749	* Intel: ECX, EDX - reserved
750	* EAX, EBX - Smallest and largest monitor line size
751	* AMD: EDX - reserved
752	* EAX, EBX - Smallest and largest monitor line size
753	* ECX - extensions (ignored for now)
754	* Safe to expose
755	*/
756	if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
757	pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
758
759	pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
760	/** @cfgm{/CPUM/MWaitExtensions, boolean, false}
761	* Expose MWAIT extended features to the guest. For now we expose
762	* just MWAIT break on interrupt feature (bit 1).
763	*/
764	bool fMWaitExtensions;
765	rc = CFGMR3QueryBoolDef(pCpumCfg, "MWaitExtensions", &fMWaitExtensions, false); AssertRCReturn(rc, rc);
766	if (fMWaitExtensions)
767	{
768	pCPUM->aGuestCpuIdStd[5].ecx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
769	/* @todo: for now we just expose host's MWAIT C-states, although conceptually
770	it shall be part of our power management virtualization model */
771	#if 0
772	/* MWAIT sub C-states */
773	pCPUM->aGuestCpuIdStd[5].edx =
774	(0 << 0) /* 0 in C0 */ \|
775	(2 << 4) /* 2 in C1 */ \|
776	(2 << 8) /* 2 in C2 */ \|
777	(2 << 12) /* 2 in C3 */ \|
778	(0 << 16) /* 0 in C4 */
779	;
780	#endif
781	}
782	else
783	pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
784
785	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
786	* Safe to pass on to the guest.
787	*
788	* Intel: 0x800000005 reserved
789	* 0x800000006 L2 cache information
790	* AMD: 0x800000005 L1 cache information
791	* 0x800000006 L2/L3 cache information
792	*/
793
794	/* Cpuid 0x800000007:
795	* AMD: EAX, EBX, ECX - reserved
796	* EDX: Advanced Power Management Information
797	* Intel: Reserved
798	*/
799	if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
800	{
801	Assert(pVM->cpum.s.enmGuestCpuVendor != CPUMCPUVENDOR_INVALID);
802
803	pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
804
805	if (pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
806	{
807	/* Only expose the TSC invariant capability bit to the guest. */
808	pCPUM->aGuestCpuIdExt[7].edx &= 0
809	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
810	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
811	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
812	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
813	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
814	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
815	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
816	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
817	#if 0 /* We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer
818	* Linux kernels blindly assume that the AMD performance counters work
819	* if this is set for 64 bits guests. (Can't really find a CPUID feature
820	* bit for them though.) */
821	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
822	#endif
823	\| 0;
824	}
825	else
826	pCPUM->aGuestCpuIdExt[7].edx = 0;
827	}
828
829	/* Cpuid 0x800000008:
830	* AMD: EBX, EDX - reserved
831	* EAX: Virtual/Physical/Guest address Size
832	* ECX: Number of cores + APICIdCoreIdSize
833	* Intel: EAX: Virtual/Physical address Size
834	* EBX, ECX, EDX - reserved
835	*/
836	if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
837	{
838	/* Only expose the virtual and physical address sizes to the guest. */
839	pCPUM->aGuestCpuIdExt[8].eax &= UINT32_C(0x0000ffff);
840	pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
841	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
842	* NC (0-7) Number of cores; 0 equals 1 core */
843	pCPUM->aGuestCpuIdExt[8].ecx = 0;
844	#ifdef VBOX_WITH_MULTI_CORE
845	if ( pVM->cCpus > 1
846	&& pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
847	{
848	/* Legacy method to determine the number of cores. */
849	pCPUM->aGuestCpuIdExt[1].ecx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL;
850	pCPUM->aGuestCpuIdExt[8].ecx \|= (pVM->cCpus - 1); /* NC: Number of CPU cores - 1; 8 bits */
851	}
852	#endif
853	}
854
855	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
856	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
857	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
858	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
859	*/
860	bool fNt4LeafLimit;
861	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &fNt4LeafLimit, false); AssertRCReturn(rc, rc);
862	if (fNt4LeafLimit)
863	pCPUM->aGuestCpuIdStd[0].eax = 3; /** @todo r=bird: shouldn't we check if pCPUM->aGuestCpuIdStd[0].eax > 3 before setting it 3 here? */
864
865	/*
866	* Limit it the number of entries and fill the remaining with the defaults.
867	*
868	* The limits are masking off stuff about power saving and similar, this
869	* is perhaps a bit crudely done as there is probably some relatively harmless
870	* info too in these leaves (like words about having a constant TSC).
871	*/
872	if (pCPUM->aGuestCpuIdStd[0].eax > 5)
873	pCPUM->aGuestCpuIdStd[0].eax = 5;
874	for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
875	pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
876
877	if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
878	pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
879	for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
880	? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
881	: 0;
882	i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
883	i++)
884	pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
885
886	/*
887	* Centaur stuff (VIA).
888	*
889	* The important part here (we think) is to make sure the 0xc0000000
890	* function returns 0xc0000001. As for the features, we don't currently
891	* let on about any of those... 0xc0000002 seems to be some
892	* temperature/hz/++ stuff, include it as well (static).
893	*/
894	if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
895	&& pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
896	{
897	pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
898	pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
899	for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
900	i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
901	i++)
902	pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
903	}
904	else
905	for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
906	pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
907
908
909	/*
910	* Load CPUID overrides from configuration.
911	* Note: Kind of redundant now, but allows unchanged overrides
912	*/
913	/** @cfgm{CPUM/CPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
914	* Overrides the CPUID leaf values. */
915	PCFGMNODE pOverrideCfg = CFGMR3GetChild(pCpumCfg, "CPUID");
916	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pOverrideCfg);
917	AssertRCReturn(rc, rc);
918	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pOverrideCfg);
919	AssertRCReturn(rc, rc);
920	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pOverrideCfg);
921	AssertRCReturn(rc, rc);
922
923	/*
924	* Check if PAE was explicitely enabled by the user.
925	*/
926	bool fEnable;
927	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false); AssertRCReturn(rc, rc);
928	if (fEnable)
929	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
930
931	/*
932	* We don't normally enable NX for raw-mode, so give the user a chance to
933	* force it on.
934	*/
935	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false); AssertRCReturn(rc, rc);
936	if (fEnable)
937	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
938
939	/*
940	* We don't enable the Hypervisor Present bit by default, but it may
941	* be needed by some guests.
942	*/
943	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableHVP", &fEnable, false); AssertRCReturn(rc, rc);
944	if (fEnable)
945	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_HVP);
946	/*
947	* Log the cpuid and we're good.
948	*/
949	bool fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
950	RTCPUSET OnlineSet;
951	LogRel(("Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
952	(unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
953	RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
954	LogRel(("*********************** CPUID dump **********************\n"));
955	DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
956	LogRel(("\n"));
957	DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
958	RTLogRelSetBuffering(fOldBuffered);
959	LogRel(("****************** End of CPUID dump ********************\n"));
960
961	#undef PORTABLE_DISABLE_FEATURE_BIT
962	#undef PORTABLE_CLEAR_BITS_WHEN
963
964	return VINF_SUCCESS;
965	}
966
967
968	/**
969	* Applies relocations to data and code managed by this
970	* component. This function will be called at init and
971	* whenever the VMM need to relocate it self inside the GC.
972	*
973	* The CPUM will update the addresses used by the switcher.
974	*
975	* @param pVM The VM.
976	*/
977	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
978	{
979	LogFlow(("CPUMR3Relocate\n"));
980	for (VMCPUID i = 0; i < pVM->cCpus; i++)
981	{
982	/*
983	* Switcher pointers.
984	*/
985	PVMCPU pVCpu = &pVM->aCpus[i];
986	pVCpu->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVCpu->cpum.s.pHyperCoreR3);
987	Assert(pVCpu->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
988
989	}
990	}
991
992
993	/**
994	* Apply late CPUM property changes based on the fHWVirtEx setting
995	*
996	* @param pVM The VM to operate on.
997	* @param fHWVirtExEnabled HWVirtEx enabled/disabled
998	*/
999	VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled)
1000	{
1001	/*
1002	* Workaround for missing cpuid(0) patches when leaf 4 returns GuestCpuIdDef:
1003	* If we miss to patch a cpuid(0).eax then Linux tries to determine the number
1004	* of processors from (cpuid(4).eax >> 26) + 1.
1005	*
1006	* Note: this code is obsolete, but let's keep it here for reference.
1007	* Purpose is valid when we artificially cap the max std id to less than 4.
1008	*/
1009	if (!fHWVirtExEnabled)
1010	{
1011	Assert( pVM->cpum.s.aGuestCpuIdStd[4].eax == 0
1012	\|\| pVM->cpum.s.aGuestCpuIdStd[0].eax < 0x4);
1013	pVM->cpum.s.aGuestCpuIdStd[4].eax = 0;
1014	}
1015	}
1016
1017	/**
1018	* Terminates the CPUM.
1019	*
1020	* Termination means cleaning up and freeing all resources,
1021	* the VM it self is at this point powered off or suspended.
1022	*
1023	* @returns VBox status code.
1024	* @param pVM The VM to operate on.
1025	*/
1026	VMMR3DECL(int) CPUMR3Term(PVM pVM)
1027	{
1028	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1029	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1030	{
1031	PVMCPU pVCpu = &pVM->aCpus[i];
1032	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1033
1034	memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
1035	pVCpu->cpum.s.uMagic = 0;
1036	pCtx->dr[5] = 0;
1037	}
1038	#else
1039	NOREF(pVM);
1040	#endif
1041	return VINF_SUCCESS;
1042	}
1043
1044
1045	/**
1046	* Resets a virtual CPU.
1047	*
1048	* Used by CPUMR3Reset and CPU hot plugging.
1049	*
1050	* @param pVCpu The virtual CPU handle.
1051	*/
1052	VMMR3DECL(void) CPUMR3ResetCpu(PVMCPU pVCpu)
1053	{
1054	/** @todo anything different for VCPU > 0? */
1055	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1056
1057	/*
1058	* Initialize everything to ZERO first.
1059	*/
1060	uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
1061	memset(pCtx, 0, sizeof(*pCtx));
1062	pVCpu->cpum.s.fUseFlags = fUseFlags;
1063
1064	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
1065	pCtx->eip = 0x0000fff0;
1066	pCtx->edx = 0x00000600; /* P6 processor */
1067	pCtx->eflags.Bits.u1Reserved0 = 1;
1068
1069	pCtx->cs = 0xf000;
1070	pCtx->csHid.u64Base = UINT64_C(0xffff0000);
1071	pCtx->csHid.u32Limit = 0x0000ffff;
1072	pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
1073	pCtx->csHid.Attr.n.u1Present = 1;
1074	pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ \| X86_SEL_TYPE_CODE;
1075
1076	pCtx->dsHid.u32Limit = 0x0000ffff;
1077	pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
1078	pCtx->dsHid.Attr.n.u1Present = 1;
1079	pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1080
1081	pCtx->esHid.u32Limit = 0x0000ffff;
1082	pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
1083	pCtx->esHid.Attr.n.u1Present = 1;
1084	pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1085
1086	pCtx->fsHid.u32Limit = 0x0000ffff;
1087	pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
1088	pCtx->fsHid.Attr.n.u1Present = 1;
1089	pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1090
1091	pCtx->gsHid.u32Limit = 0x0000ffff;
1092	pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
1093	pCtx->gsHid.Attr.n.u1Present = 1;
1094	pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1095
1096	pCtx->ssHid.u32Limit = 0x0000ffff;
1097	pCtx->ssHid.Attr.n.u1Present = 1;
1098	pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
1099	pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1100
1101	pCtx->idtr.cbIdt = 0xffff;
1102	pCtx->gdtr.cbGdt = 0xffff;
1103
1104	pCtx->ldtrHid.u32Limit = 0xffff;
1105	pCtx->ldtrHid.Attr.n.u1Present = 1;
1106	pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
1107
1108	pCtx->trHid.u32Limit = 0xffff;
1109	pCtx->trHid.Attr.n.u1Present = 1;
1110	pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
1111
1112	pCtx->dr[6] = X86_DR6_INIT_VAL;
1113	pCtx->dr[7] = X86_DR7_INIT_VAL;
1114
1115	pCtx->fpu.FTW = 0x00; /* All empty (abbridged tag reg edition). */
1116	pCtx->fpu.FCW = 0x37f;
1117
1118	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
1119	IA-32 Processor States Following Power-up, Reset, or INIT */
1120	pCtx->fpu.MXCSR = 0x1F80;
1121	pCtx->fpu.MXCSR_MASK = 0xffff; /** @todo REM always changed this for us. Should probably check if the HW really
1122	supports all bits, since a zero value here should be read as 0xffbf. */
1123
1124	/* Init PAT MSR */
1125	pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
1126
1127	/* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
1128	* The Intel docs don't mention it.
1129	*/
1130	pCtx->msrEFER = 0;
1131	}
1132
1133
1134	/**
1135	* Resets the CPU.
1136	*
1137	* @returns VINF_SUCCESS.
1138	* @param pVM The VM handle.
1139	*/
1140	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
1141	{
1142	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1143	{
1144	CPUMR3ResetCpu(&pVM->aCpus[i]);
1145
1146	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1147	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(&pVM->aCpus[i]);
1148
1149	/* Magic marker for searching in crash dumps. */
1150	strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
1151	pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1152	pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
1153	#endif
1154	}
1155	}
1156
1157
1158	/**
1159	* Called both in pass 0 and the final pass.
1160	*
1161	* @param pVM The VM handle.
1162	* @param pSSM The saved state handle.
1163	*/
1164	static void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
1165	{
1166	/*
1167	* Save all the CPU ID leaves here so we can check them for compatibility
1168	* upon loading.
1169	*/
1170	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
1171	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
1172
1173	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
1174	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1175
1176	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
1177	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1178
1179	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1180
1181	/*
1182	* Save a good portion of the raw CPU IDs as well as they may come in
1183	* handy when validating features for raw mode.
1184	*/
1185	CPUMCPUID aRawStd[16];
1186	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
1187	ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1188	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
1189	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
1190
1191	CPUMCPUID aRawExt[32];
1192	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
1193	ASMCpuId(i \| UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1194	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
1195	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
1196	}
1197
1198
1199	/**
1200	* Loads the CPU ID leaves saved by pass 0.
1201	*
1202	* @returns VBox status code.
1203	* @param pVM The VM handle.
1204	* @param pSSM The saved state handle.
1205	* @param uVersion The format version.
1206	*/
1207	static int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
1208	{
1209	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
1210
1211	/*
1212	* Define a bunch of macros for simplifying the code.
1213	*/
1214	/* Generic expression + failure message. */
1215	#define CPUID_CHECK_RET(expr, fmt) \
1216	do { \
1217	if (!(expr)) \
1218	{ \
1219	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
1220	if (fStrictCpuIdChecks) \
1221	{ \
1222	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
1223	RTStrFree(pszMsg); \
1224	return rcCpuid; \
1225	} \
1226	LogRel(("CPUM: %s\n", pszMsg)); \
1227	RTStrFree(pszMsg); \
1228	} \
1229	} while (0)
1230	#define CPUID_CHECK_WRN(expr, fmt) \
1231	do { \
1232	if (!(expr)) \
1233	LogRel(fmt); \
1234	} while (0)
1235
1236	/* For comparing two values and bitch if they differs. */
1237	#define CPUID_CHECK2_RET(what, host, saved) \
1238	do { \
1239	if ((host) != (saved)) \
1240	{ \
1241	if (fStrictCpuIdChecks) \
1242	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1243	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
1244	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1245	} \
1246	} while (0)
1247	#define CPUID_CHECK2_WRN(what, host, saved) \
1248	do { \
1249	if ((host) != (saved)) \
1250	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1251	} while (0)
1252
1253	/* For checking raw cpu features (raw mode). */
1254	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
1255	do { \
1256	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1257	{ \
1258	if (fStrictCpuIdChecks) \
1259	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1260	N_(#bit " mismatch: host=%d saved=%d"), \
1261	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
1262	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1263	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1264	} \
1265	} while (0)
1266	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
1267	do { \
1268	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1269	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1270	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1271	} while (0)
1272	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
1273
1274	/* For checking guest features. */
1275	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
1276	do { \
1277	if ( (aGuestCpuId##set [1].reg & bit) \
1278	&& !(aHostRaw##set [1].reg & bit) \
1279	&& !(aHostOverride##set [1].reg & bit) \
1280	&& !(aGuestOverride##set [1].reg & bit) \
1281	) \
1282	{ \
1283	if (fStrictCpuIdChecks) \
1284	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1285	N_(#bit " is not supported by the host but has already exposed to the guest")); \
1286	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1287	} \
1288	} while (0)
1289	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
1290	do { \
1291	if ( (aGuestCpuId##set [1].reg & bit) \
1292	&& !(aHostRaw##set [1].reg & bit) \
1293	&& !(aHostOverride##set [1].reg & bit) \
1294	&& !(aGuestOverride##set [1].reg & bit) \
1295	) \
1296	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1297	} while (0)
1298	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
1299	do { \
1300	if ( (aGuestCpuId##set [1].reg & bit) \
1301	&& !(aHostRaw##set [1].reg & bit) \
1302	&& !(aHostOverride##set [1].reg & bit) \
1303	&& !(aGuestOverride##set [1].reg & bit) \
1304	) \
1305	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1306	} while (0)
1307	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
1308
1309	/* For checking guest features if AMD guest CPU. */
1310	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
1311	do { \
1312	if ( (aGuestCpuId##set [1].reg & bit) \
1313	&& fGuestAmd \
1314	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1315	&& !(aHostOverride##set [1].reg & bit) \
1316	&& !(aGuestOverride##set [1].reg & bit) \
1317	) \
1318	{ \
1319	if (fStrictCpuIdChecks) \
1320	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1321	N_(#bit " is not supported by the host but has already exposed to the guest")); \
1322	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1323	} \
1324	} while (0)
1325	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
1326	do { \
1327	if ( (aGuestCpuId##set [1].reg & bit) \
1328	&& fGuestAmd \
1329	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1330	&& !(aHostOverride##set [1].reg & bit) \
1331	&& !(aGuestOverride##set [1].reg & bit) \
1332	) \
1333	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1334	} while (0)
1335	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
1336	do { \
1337	if ( (aGuestCpuId##set [1].reg & bit) \
1338	&& fGuestAmd \
1339	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1340	&& !(aHostOverride##set [1].reg & bit) \
1341	&& !(aGuestOverride##set [1].reg & bit) \
1342	) \
1343	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1344	} while (0)
1345	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
1346
1347	/* For checking AMD features which have a corresponding bit in the standard
1348	range. (Intel defines very few bits in the extended feature sets.) */
1349	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
1350	do { \
1351	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1352	&& !(fHostAmd \
1353	? aHostRawExt[1].reg & (ExtBit) \
1354	: aHostRawStd[1].reg & (StdBit)) \
1355	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1356	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1357	) \
1358	{ \
1359	if (fStrictCpuIdChecks) \
1360	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1361	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
1362	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1363	} \
1364	} while (0)
1365	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
1366	do { \
1367	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1368	&& !(fHostAmd \
1369	? aHostRawExt[1].reg & (ExtBit) \
1370	: aHostRawStd[1].reg & (StdBit)) \
1371	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1372	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1373	) \
1374	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1375	} while (0)
1376	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
1377	do { \
1378	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1379	&& !(fHostAmd \
1380	? aHostRawExt[1].reg & (ExtBit) \
1381	: aHostRawStd[1].reg & (StdBit)) \
1382	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1383	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1384	) \
1385	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1386	} while (0)
1387	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
1388
1389	/*
1390	* Load them into stack buffers first.
1391	*/
1392	CPUMCPUID aGuestCpuIdStd[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd)];
1393	uint32_t cGuestCpuIdStd;
1394	int rc = SSMR3GetU32(pSSM, &cGuestCpuIdStd); AssertRCReturn(rc, rc);
1395	if (cGuestCpuIdStd > RT_ELEMENTS(aGuestCpuIdStd))
1396	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1397	SSMR3GetMem(pSSM, &aGuestCpuIdStd[0], cGuestCpuIdStd * sizeof(aGuestCpuIdStd[0]));
1398
1399	CPUMCPUID aGuestCpuIdExt[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt)];
1400	uint32_t cGuestCpuIdExt;
1401	rc = SSMR3GetU32(pSSM, &cGuestCpuIdExt); AssertRCReturn(rc, rc);
1402	if (cGuestCpuIdExt > RT_ELEMENTS(aGuestCpuIdExt))
1403	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1404	SSMR3GetMem(pSSM, &aGuestCpuIdExt[0], cGuestCpuIdExt * sizeof(aGuestCpuIdExt[0]));
1405
1406	CPUMCPUID aGuestCpuIdCentaur[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur)];
1407	uint32_t cGuestCpuIdCentaur;
1408	rc = SSMR3GetU32(pSSM, &cGuestCpuIdCentaur); AssertRCReturn(rc, rc);
1409	if (cGuestCpuIdCentaur > RT_ELEMENTS(aGuestCpuIdCentaur))
1410	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1411	SSMR3GetMem(pSSM, &aGuestCpuIdCentaur[0], cGuestCpuIdCentaur * sizeof(aGuestCpuIdCentaur[0]));
1412
1413	CPUMCPUID GuestCpuIdDef;
1414	rc = SSMR3GetMem(pSSM, &GuestCpuIdDef, sizeof(GuestCpuIdDef));
1415	AssertRCReturn(rc, rc);
1416
1417	CPUMCPUID aRawStd[16];
1418	uint32_t cRawStd;
1419	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
1420	if (cRawStd > RT_ELEMENTS(aRawStd))
1421	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1422	SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
1423
1424	CPUMCPUID aRawExt[32];
1425	uint32_t cRawExt;
1426	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
1427	if (cRawExt > RT_ELEMENTS(aRawExt))
1428	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1429	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
1430	AssertRCReturn(rc, rc);
1431
1432	/*
1433	* Note that we support restoring less than the current amount of standard
1434	* leaves because we've been allowed more is newer version of VBox.
1435	*
1436	* So, pad new entries with the default.
1437	*/
1438	for (uint32_t i = cGuestCpuIdStd; i < RT_ELEMENTS(aGuestCpuIdStd); i++)
1439	aGuestCpuIdStd[i] = GuestCpuIdDef;
1440
1441	for (uint32_t i = cGuestCpuIdExt; i < RT_ELEMENTS(aGuestCpuIdExt); i++)
1442	aGuestCpuIdExt[i] = GuestCpuIdDef;
1443
1444	for (uint32_t i = cGuestCpuIdCentaur; i < RT_ELEMENTS(aGuestCpuIdCentaur); i++)
1445	aGuestCpuIdCentaur[i] = GuestCpuIdDef;
1446
1447	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
1448	ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1449
1450	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
1451	ASMCpuId(i \| UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1452
1453	/*
1454	* Get the raw CPU IDs for the current host.
1455	*/
1456	CPUMCPUID aHostRawStd[16];
1457	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
1458	ASMCpuId(i, &aHostRawStd[i].eax, &aHostRawStd[i].ebx, &aHostRawStd[i].ecx, &aHostRawStd[i].edx);
1459
1460	CPUMCPUID aHostRawExt[32];
1461	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
1462	ASMCpuId(i \| UINT32_C(0x80000000), &aHostRawExt[i].eax, &aHostRawExt[i].ebx, &aHostRawExt[i].ecx, &aHostRawExt[i].edx);
1463
1464	/*
1465	* Get the host and guest overrides so we don't reject the state because
1466	* some feature was enabled thru these interfaces.
1467	* Note! We currently only need the feature leaves, so skip rest.
1468	*/
1469	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/CPUID");
1470	CPUMCPUID aGuestOverrideStd[2];
1471	memcpy(&aGuestOverrideStd[0], &aHostRawStd[0], sizeof(aGuestOverrideStd));
1472	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aGuestOverrideStd[0], RT_ELEMENTS(aGuestOverrideStd), pOverrideCfg);
1473
1474	CPUMCPUID aGuestOverrideExt[2];
1475	memcpy(&aGuestOverrideExt[0], &aHostRawExt[0], sizeof(aGuestOverrideExt));
1476	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aGuestOverrideExt[0], RT_ELEMENTS(aGuestOverrideExt), pOverrideCfg);
1477
1478	pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
1479	CPUMCPUID aHostOverrideStd[2];
1480	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
1481	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
1482
1483	CPUMCPUID aHostOverrideExt[2];
1484	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
1485	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
1486
1487	/*
1488	* This can be skipped.
1489	*/
1490	bool fStrictCpuIdChecks;
1491	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
1492
1493
1494
1495	/*
1496	* For raw-mode we'll require that the CPUs are very similar since we don't
1497	* intercept CPUID instructions for user mode applications.
1498	*/
1499	if (!HWACCMIsEnabled(pVM))
1500	{
1501	/* CPUID(0) */
1502	CPUID_CHECK_RET( aHostRawStd[0].ebx == aRawStd[0].ebx
1503	&& aHostRawStd[0].ecx == aRawStd[0].ecx
1504	&& aHostRawStd[0].edx == aRawStd[0].edx,
1505	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
1506	&aHostRawStd[0].ebx, &aHostRawStd[0].edx, &aHostRawStd[0].ecx,
1507	&aRawStd[0].ebx, &aRawStd[0].edx, &aRawStd[0].ecx));
1508	CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].eax, aRawStd[0].eax);
1509	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3);
1510	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
1511
1512	bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].ebx, aRawStd[0].ecx, aRawStd[0].edx);
1513
1514	/* CPUID(1).eax */
1515	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].eax), ASMGetCpuFamily(aRawStd[1].eax));
1516	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].eax, fIntel), ASMGetCpuModel(aRawStd[1].eax, fIntel));
1517	CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].eax >> 12) & 3, (aRawStd[1].eax >> 12) & 3 );
1518
1519	/* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
1520	CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].ebx & 0xff, aRawStd[1].ebx & 0xff);
1521	CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].ebx >> 8) & 0xff, (aRawStd[1].ebx >> 8) & 0xff);
1522
1523	/* CPUID(1).ecx */
1524	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3);
1525	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL);
1526	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64);
1527	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
1528	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS);
1529	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_VMX);
1530	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_SMX);
1531	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_EST);
1532	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TM2);
1533	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3);
1534	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID);
1535	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(11) /reserved/ );
1536	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA);
1537	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16);
1538	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
1539	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM);
1540	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(16) /reserved/);
1541	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(17) /reserved/);
1542	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DCA);
1543	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1);
1544	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2);
1545	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
1546	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE);
1547	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT);
1548	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(24) /reserved/);
1549	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES);
1550	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE);
1551	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE);
1552	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX);
1553	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(29) /reserved/);
1554	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(30) /reserved/);
1555	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(31) /reserved/);
1556
1557	/* CPUID(1).edx */
1558	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
1559	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
1560	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE);
1561	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
1562	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC);
1563	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR);
1564	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
1565	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
1566	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8);
1567	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
1568	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(10) /reserved/);
1569	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
1570	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
1571	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
1572	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
1573	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV);
1574	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
1575	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
1576	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
1577	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH);
1578	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(20) /reserved/);
1579	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_DS);
1580	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_ACPI);
1581	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX);
1582	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR);
1583	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE);
1584	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2);
1585	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SS);
1586	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_HTT);
1587	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_TM);
1588	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(30) /JMPE/IA64/);
1589	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PBE);
1590
1591	/* CPUID(2) - config, mostly about caches. ignore. */
1592	/* CPUID(3) - processor serial number. ignore. */
1593	/* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
1594	/* CPUID(5) - mwait/monitor config. ignore. */
1595	/* CPUID(6) - power management. ignore. */
1596	/* CPUID(7) - ???. ignore. */
1597	/* CPUID(8) - ???. ignore. */
1598	/* CPUID(9) - DCA. ignore for now. */
1599	/* CPUID(a) - PeMo info. ignore for now. */
1600	/* CPUID(b) - topology info - takes ECX as input. ignore. */
1601
1602	/* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
1603	CPUID_CHECK_WRN( aRawStd[0].eax < UINT32_C(0x0000000d)
1604	\|\| aHostRawStd[0].eax >= UINT32_C(0x0000000d),
1605	("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
1606	if ( aRawStd[0].eax >= UINT32_C(0x0000000d)
1607	&& aHostRawStd[0].eax >= UINT32_C(0x0000000d))
1608	{
1609	CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].eax, aRawStd[0xd].eax);
1610	CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].edx, aRawStd[0xd].edx);
1611	CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].ebx, aRawStd[0xd].ebx);
1612	CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].ecx, aRawStd[0xd].ecx);
1613	}
1614
1615	/* CPUID(0x80000000) - same as CPUID(0) except for eax.
1616	Note! Intel have/is marking many of the fields here as reserved. We
1617	will verify them as if it's an AMD CPU. */
1618	CPUID_CHECK_RET( (aHostRawExt[0].eax >= UINT32_C(0x80000001) && aHostRawExt[0].eax <= UINT32_C(0x8000007f))
1619	\|\| !(aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f)),
1620	(N_("Extended leaves was present on saved state host, but is missing on the current\n")));
1621	if (aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f))
1622	{
1623	CPUID_CHECK_RET( aHostRawExt[0].ebx == aRawExt[0].ebx
1624	&& aHostRawExt[0].ecx == aRawExt[0].ecx
1625	&& aHostRawExt[0].edx == aRawExt[0].edx,
1626	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
1627	&aHostRawExt[0].ebx, &aHostRawExt[0].edx, &aHostRawExt[0].ecx,
1628	&aRawExt[0].ebx, &aRawExt[0].edx, &aRawExt[0].ecx));
1629	CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].eax, aRawExt[0].eax);
1630
1631	/* CPUID(0x80000001).eax - same as CPUID(0).eax. */
1632	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].eax), ASMGetCpuFamily(aRawExt[1].eax));
1633	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].eax, fIntel), ASMGetCpuModel(aRawExt[1].eax, fIntel));
1634	CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].eax >> 12) & 3, (aRawExt[1].eax >> 12) & 3 );
1635	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3 );
1636	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
1637
1638	/* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
1639	CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].ebx & 0xffff, aRawExt[1].ebx & 0xffff);
1640	CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].ebx >> 16) & 0xfff, (aRawExt[1].ebx >> 16) & 0xfff);
1641	CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].ebx >> 28) & 0xf, (aRawExt[1].ebx >> 28) & 0xf);
1642
1643	/* CPUID(0x80000001).ecx */
1644	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF);
1645	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
1646	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM);
1647	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
1648	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
1649	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM);
1650	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
1651	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
1652	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
1653	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
1654	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS);
1655	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5);
1656	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
1657	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT);
1658	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
1659	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
1660	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
1661	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
1662	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
1663	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
1664	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
1665	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
1666	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
1667	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
1668	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
1669	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
1670	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
1671	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
1672	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
1673	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
1674	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
1675	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
1676
1677	/* CPUID(0x80000001).edx */
1678	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FPU);
1679	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_VME);
1680	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_DE);
1681	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE);
1682	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_TSC);
1683	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MSR);
1684	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAE);
1685	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCE);
1686	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CX8);
1687	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_APIC);
1688	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(10) /reserved/);
1689	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_SEP);
1690	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
1691	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PGE);
1692	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCA);
1693	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
1694	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAT);
1695	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
1696	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(18) /reserved/);
1697	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(19) /reserved/);
1698	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_NX);
1699	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(21) /reserved/);
1700	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1701	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MMX);
1702	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
1703	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1704	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAGE1GB);
1705	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
1706	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(28) /reserved/);
1707	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_LONG_MODE);
1708	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1709	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1710
1711	/** @todo verify the rest as well. */
1712	}
1713	}
1714
1715
1716
1717	/*
1718	* Verify that we can support the features already exposed to the guest on
1719	* this host.
1720	*
1721	* Most of the features we're emulating requires intercepting instruction
1722	* and doing it the slow way, so there is no need to warn when they aren't
1723	* present in the host CPU. Thus we use IGN instead of EMU on these.
1724	*
1725	* Trailing comments:
1726	* "EMU" - Possible to emulate, could be lots of work and very slow.
1727	* "EMU?" - Can this be emulated?
1728	*/
1729	/* CPUID(1).ecx */
1730	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
1731	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
1732	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
1733	CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
1734	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
1735	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
1736	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
1737	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
1738	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
1739	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
1740	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
1741	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(11) /reserved/ );
1742	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
1743	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
1744	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
1745	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
1746	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(16) /reserved/);
1747	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(17) /reserved/);
1748	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
1749	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
1750	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
1751	CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
1752	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
1753	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
1754	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(24) /reserved/);
1755	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
1756	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
1757	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE); // -> EMU
1758	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
1759	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(29) /reserved/);
1760	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(30) /reserved/);
1761	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(31) /reserved/);
1762
1763	/* CPUID(1).edx */
1764	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
1765	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
1766	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
1767	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
1768	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
1769	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
1770	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
1771	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
1772	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
1773	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
1774	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(10) /reserved/);
1775	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
1776	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
1777	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
1778	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
1779	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
1780	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
1781	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
1782	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
1783	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
1784	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(20) /reserved/);
1785	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
1786	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
1787	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
1788	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
1789	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
1790	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
1791	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
1792	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
1793	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
1794	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
1795	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
1796
1797	/* CPUID(0x80000000). */
1798	if ( aGuestCpuIdExt[0].eax >= UINT32_C(0x80000001)
1799	&& aGuestCpuIdExt[0].eax < UINT32_C(0x8000007f))
1800	{
1801	/** @todo deal with no 0x80000001 on the host. */
1802	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].ebx, aHostRawStd[0].ecx, aHostRawStd[0].edx);
1803	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].ebx, aGuestCpuIdExt[0].ecx, aGuestCpuIdExt[0].edx);
1804
1805	/* CPUID(0x80000001).ecx */
1806	CPUID_GST_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF); // -> EMU
1807	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
1808	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
1809	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
1810	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
1811	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
1812	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
1813	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
1814	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
1815	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
1816	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
1817	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5); // -> EMU
1818	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
1819	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
1820	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
1821	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
1822	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
1823	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
1824	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
1825	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
1826	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
1827	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
1828	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
1829	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
1830	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
1831	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
1832	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
1833	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
1834	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
1835	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
1836	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
1837	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
1838
1839	/* CPUID(0x80000001).edx */
1840	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
1841	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
1842	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
1843	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
1844	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
1845	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
1846	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
1847	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
1848	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
1849	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
1850	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(10) /reserved/);
1851	CPUID_GST_FEATURE_IGN( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_SEP); // Intel: long mode only.
1852	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
1853	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
1854	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
1855	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
1856	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
1857	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
1858	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(18) /reserved/);
1859	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(19) /reserved/);
1860	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_NX);
1861	CPUID_GST_FEATURE_WRN( Ext, edx, RT_BIT_32(21) /reserved/);
1862	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1863	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
1864	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
1865	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1866	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAGE1GB);
1867	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
1868	CPUID_GST_FEATURE_IGN( Ext, edx, RT_BIT_32(28) /reserved/);
1869	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_LONG_MODE);
1870	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1871	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1872	}
1873
1874	/*
1875	* We're good, commit the CPU ID leaves.
1876	*/
1877	memcpy(&pVM->cpum.s.aGuestCpuIdStd[0], &aGuestCpuIdStd[0], sizeof(aGuestCpuIdStd));
1878	memcpy(&pVM->cpum.s.aGuestCpuIdExt[0], &aGuestCpuIdExt[0], sizeof(aGuestCpuIdExt));
1879	memcpy(&pVM->cpum.s.aGuestCpuIdCentaur[0], &aGuestCpuIdCentaur[0], sizeof(aGuestCpuIdCentaur));
1880	pVM->cpum.s.GuestCpuIdDef = GuestCpuIdDef;
1881
1882	#undef CPUID_CHECK_RET
1883	#undef CPUID_CHECK_WRN
1884	#undef CPUID_CHECK2_RET
1885	#undef CPUID_CHECK2_WRN
1886	#undef CPUID_RAW_FEATURE_RET
1887	#undef CPUID_RAW_FEATURE_WRN
1888	#undef CPUID_RAW_FEATURE_IGN
1889	#undef CPUID_GST_FEATURE_RET
1890	#undef CPUID_GST_FEATURE_WRN
1891	#undef CPUID_GST_FEATURE_EMU
1892	#undef CPUID_GST_FEATURE_IGN
1893	#undef CPUID_GST_FEATURE2_RET
1894	#undef CPUID_GST_FEATURE2_WRN
1895	#undef CPUID_GST_FEATURE2_EMU
1896	#undef CPUID_GST_FEATURE2_IGN
1897	#undef CPUID_GST_AMD_FEATURE_RET
1898	#undef CPUID_GST_AMD_FEATURE_WRN
1899	#undef CPUID_GST_AMD_FEATURE_EMU
1900	#undef CPUID_GST_AMD_FEATURE_IGN
1901
1902	return VINF_SUCCESS;
1903	}
1904
1905
1906	/**
1907	* Pass 0 live exec callback.
1908	*
1909	* @returns VINF_SSM_DONT_CALL_AGAIN.
1910	* @param pVM The VM handle.
1911	* @param pSSM The saved state handle.
1912	* @param uPass The pass (0).
1913	*/
1914	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1915	{
1916	AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
1917	cpumR3SaveCpuId(pVM, pSSM);
1918	return VINF_SSM_DONT_CALL_AGAIN;
1919	}
1920
1921
1922	/**
1923	* Execute state save operation.
1924	*
1925	* @returns VBox status code.
1926	* @param pVM VM Handle.
1927	* @param pSSM SSM operation handle.
1928	*/
1929	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1930	{
1931	/*
1932	* Save.
1933	*/
1934	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1935	{
1936	PVMCPU pVCpu = &pVM->aCpus[i];
1937
1938	SSMR3PutMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
1939	}
1940
1941	SSMR3PutU32(pSSM, pVM->cCpus);
1942	SSMR3PutU32(pSSM, sizeof(pVM->aCpus[0].cpum.s.GuestMsrs.msr));
1943	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1944	{
1945	PVMCPU pVCpu = &pVM->aCpus[i];
1946
1947	SSMR3PutMem(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest));
1948	SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
1949	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
1950	AssertCompileSizeAlignment(pVM->aCpus[i].cpum.s.GuestMsrs.msr, sizeof(uint64_t));
1951	SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVM->aCpus[i].cpum.s.GuestMsrs.msr));
1952	}
1953
1954	cpumR3SaveCpuId(pVM, pSSM);
1955	return VINF_SUCCESS;
1956	}
1957
1958
1959	/**
1960	* Load a version 1.6 CPUMCTX structure.
1961	*
1962	* @returns VBox status code.
1963	* @param pVM VM Handle.
1964	* @param pCpumctx16 Version 1.6 CPUMCTX
1965	*/
1966	static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
1967	{
1968	#define CPUMCTX16_LOADREG(RegName) \
1969	pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName;
1970
1971	#define CPUMCTX16_LOADDRXREG(RegName) \
1972	pVM->aCpus[0].cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
1973
1974	#define CPUMCTX16_LOADHIDREG(RegName) \
1975	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
1976	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
1977	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
1978
1979	#define CPUMCTX16_LOADSEGREG(RegName) \
1980	pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName; \
1981	CPUMCTX16_LOADHIDREG(RegName);
1982
1983	pVM->aCpus[0].cpum.s.Guest.fpu = pCpumctx16->fpu;
1984
1985	CPUMCTX16_LOADREG(rax);
1986	CPUMCTX16_LOADREG(rbx);
1987	CPUMCTX16_LOADREG(rcx);
1988	CPUMCTX16_LOADREG(rdx);
1989	CPUMCTX16_LOADREG(rdi);
1990	CPUMCTX16_LOADREG(rsi);
1991	CPUMCTX16_LOADREG(rbp);
1992	CPUMCTX16_LOADREG(esp);
1993	CPUMCTX16_LOADREG(rip);
1994	CPUMCTX16_LOADREG(rflags);
1995
1996	CPUMCTX16_LOADSEGREG(cs);
1997	CPUMCTX16_LOADSEGREG(ds);
1998	CPUMCTX16_LOADSEGREG(es);
1999	CPUMCTX16_LOADSEGREG(fs);
2000	CPUMCTX16_LOADSEGREG(gs);
2001	CPUMCTX16_LOADSEGREG(ss);
2002
2003	CPUMCTX16_LOADREG(r8);
2004	CPUMCTX16_LOADREG(r9);
2005	CPUMCTX16_LOADREG(r10);
2006	CPUMCTX16_LOADREG(r11);
2007	CPUMCTX16_LOADREG(r12);
2008	CPUMCTX16_LOADREG(r13);
2009	CPUMCTX16_LOADREG(r14);
2010	CPUMCTX16_LOADREG(r15);
2011
2012	CPUMCTX16_LOADREG(cr0);
2013	CPUMCTX16_LOADREG(cr2);
2014	CPUMCTX16_LOADREG(cr3);
2015	CPUMCTX16_LOADREG(cr4);
2016
2017	CPUMCTX16_LOADDRXREG(0);
2018	CPUMCTX16_LOADDRXREG(1);
2019	CPUMCTX16_LOADDRXREG(2);
2020	CPUMCTX16_LOADDRXREG(3);
2021	CPUMCTX16_LOADDRXREG(4);
2022	CPUMCTX16_LOADDRXREG(5);
2023	CPUMCTX16_LOADDRXREG(6);
2024	CPUMCTX16_LOADDRXREG(7);
2025
2026	pVM->aCpus[0].cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
2027	pVM->aCpus[0].cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
2028	pVM->aCpus[0].cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
2029	pVM->aCpus[0].cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
2030
2031	CPUMCTX16_LOADREG(ldtr);
2032	CPUMCTX16_LOADREG(tr);
2033
2034	pVM->aCpus[0].cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
2035
2036	CPUMCTX16_LOADREG(msrEFER);
2037	CPUMCTX16_LOADREG(msrSTAR);
2038	CPUMCTX16_LOADREG(msrPAT);
2039	CPUMCTX16_LOADREG(msrLSTAR);
2040	CPUMCTX16_LOADREG(msrCSTAR);
2041	CPUMCTX16_LOADREG(msrSFMASK);
2042	CPUMCTX16_LOADREG(msrKERNELGSBASE);
2043
2044	CPUMCTX16_LOADHIDREG(ldtr);
2045	CPUMCTX16_LOADHIDREG(tr);
2046
2047	#undef CPUMCTX16_LOADSEGREG
2048	#undef CPUMCTX16_LOADHIDREG
2049	#undef CPUMCTX16_LOADDRXREG
2050	#undef CPUMCTX16_LOADREG
2051	}
2052
2053
2054	/**
2055	* @copydoc FNSSMINTLOADPREP
2056	*/
2057	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2058	{
2059	NOREF(pSSM);
2060	pVM->cpum.s.fPendingRestore = true;
2061	return VINF_SUCCESS;
2062	}
2063
2064
2065	/**
2066	* @copydoc FNSSMINTLOADEXEC
2067	*/
2068	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2069	{
2070	/*
2071	* Validate version.
2072	*/
2073	if ( uVersion != CPUM_SAVED_STATE_VERSION
2074	&& uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
2075	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
2076	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
2077	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
2078	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2079	&& uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
2080	{
2081	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
2082	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2083	}
2084
2085	if (uPass == SSM_PASS_FINAL)
2086	{
2087	/*
2088	* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
2089	* really old SSM file versions.)
2090	*/
2091	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2092	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
2093	else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
2094	SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
2095
2096	/*
2097	* Restore.
2098	*/
2099	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2100	{
2101	PVMCPU pVCpu = &pVM->aCpus[i];
2102	uint32_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
2103	uint32_t uESP = pVCpu->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
2104
2105	SSMR3GetMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
2106	pVCpu->cpum.s.Hyper.cr3 = uCR3;
2107	pVCpu->cpum.s.Hyper.esp = uESP;
2108	}
2109
2110	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2111	{
2112	CPUMCTX_VER1_6 cpumctx16;
2113	memset(&pVM->aCpus[0].cpum.s.Guest, 0, sizeof(pVM->aCpus[0].cpum.s.Guest));
2114	SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
2115
2116	/* Save the old cpumctx state into the new one. */
2117	cpumR3LoadCPUM1_6(pVM, &cpumctx16);
2118
2119	SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fUseFlags);
2120	SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fChanged);
2121	}
2122	else
2123	{
2124	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
2125	{
2126	uint32_t cCpus;
2127	int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2128	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
2129	VERR_SSM_UNEXPECTED_DATA);
2130	}
2131	AssertLogRelMsgReturn( uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2132	\|\| pVM->cCpus == 1,
2133	("cCpus=%u\n", pVM->cCpus),
2134	VERR_SSM_UNEXPECTED_DATA);
2135
2136	uint32_t cbMsrs = 0;
2137	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2138	{
2139	int rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
2140	AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
2141	VERR_SSM_UNEXPECTED_DATA);
2142	AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
2143	VERR_SSM_UNEXPECTED_DATA);
2144	}
2145
2146	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2147	{
2148	SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
2149	SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fUseFlags);
2150	SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fChanged);
2151	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2152	SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.GuestMsrs.au64[0], cbMsrs);
2153	else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
2154	{
2155	SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
2156	SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
2157	}
2158	}
2159	}
2160
2161	/* Older states does not set CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID for
2162	raw-mode guest, so we have to do it ourselves. */
2163	if ( uVersion <= CPUM_SAVED_STATE_VERSION_VER3_2
2164	&& !HWACCMIsEnabled(pVM))
2165	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2166	pVM->aCpus[iCpu].cpum.s.fChanged \|= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
2167	}
2168
2169	pVM->cpum.s.fPendingRestore = false;
2170
2171	/*
2172	* Guest CPUIDs.
2173	*/
2174	if (uVersion > CPUM_SAVED_STATE_VERSION_VER3_0)
2175	return cpumR3LoadCpuId(pVM, pSSM, uVersion);
2176
2177	/** @todo Merge the code below into cpumR3LoadCpuId when we've found out what is
2178	* actually required. */
2179
2180	/*
2181	* Restore the CPUID leaves.
2182	*
2183	* Note that we support restoring less than the current amount of standard
2184	* leaves because we've been allowed more is newer version of VBox.
2185	*/
2186	uint32_t cElements;
2187	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2188	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
2189	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2190	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
2191
2192	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2193	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
2194	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2195	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
2196
2197	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2198	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
2199	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2200	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
2201
2202	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
2203
2204	/*
2205	* Check that the basic cpuid id information is unchanged.
2206	*/
2207	/** @todo we should check the 64 bits capabilities too! */
2208	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
2209	ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
2210	ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
2211	uint32_t au32CpuIdSaved[8];
2212	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
2213	if (RT_SUCCESS(rc))
2214	{
2215	/* Ignore CPU stepping. */
2216	au32CpuId[4] &= 0xfffffff0;
2217	au32CpuIdSaved[4] &= 0xfffffff0;
2218
2219	/* Ignore APIC ID (AMD specs). */
2220	au32CpuId[5] &= ~0xff000000;
2221	au32CpuIdSaved[5] &= ~0xff000000;
2222
2223	/* Ignore the number of Logical CPUs (AMD specs). */
2224	au32CpuId[5] &= ~0x00ff0000;
2225	au32CpuIdSaved[5] &= ~0x00ff0000;
2226
2227	/* Ignore some advanced capability bits, that we don't expose to the guest. */
2228	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2229	\| X86_CPUID_FEATURE_ECX_VMX
2230	\| X86_CPUID_FEATURE_ECX_SMX
2231	\| X86_CPUID_FEATURE_ECX_EST
2232	\| X86_CPUID_FEATURE_ECX_TM2
2233	\| X86_CPUID_FEATURE_ECX_CNTXID
2234	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2235	\| X86_CPUID_FEATURE_ECX_PDCM
2236	\| X86_CPUID_FEATURE_ECX_DCA
2237	\| X86_CPUID_FEATURE_ECX_X2APIC
2238	);
2239	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2240	\| X86_CPUID_FEATURE_ECX_VMX
2241	\| X86_CPUID_FEATURE_ECX_SMX
2242	\| X86_CPUID_FEATURE_ECX_EST
2243	\| X86_CPUID_FEATURE_ECX_TM2
2244	\| X86_CPUID_FEATURE_ECX_CNTXID
2245	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2246	\| X86_CPUID_FEATURE_ECX_PDCM
2247	\| X86_CPUID_FEATURE_ECX_DCA
2248	\| X86_CPUID_FEATURE_ECX_X2APIC
2249	);
2250
2251	/* Make sure we don't forget to update the masks when enabling
2252	* features in the future.
2253	*/
2254	AssertRelease(!(pVM->cpum.s.aGuestCpuIdStd[1].ecx &
2255	( X86_CPUID_FEATURE_ECX_DTES64
2256	\| X86_CPUID_FEATURE_ECX_VMX
2257	\| X86_CPUID_FEATURE_ECX_SMX
2258	\| X86_CPUID_FEATURE_ECX_EST
2259	\| X86_CPUID_FEATURE_ECX_TM2
2260	\| X86_CPUID_FEATURE_ECX_CNTXID
2261	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2262	\| X86_CPUID_FEATURE_ECX_PDCM
2263	\| X86_CPUID_FEATURE_ECX_DCA
2264	\| X86_CPUID_FEATURE_ECX_X2APIC
2265	)));
2266	/* do the compare */
2267	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
2268	{
2269	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
2270	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
2271	"Saved=%.*Rhxs\n"
2272	"Real =%.*Rhxs\n",
2273	sizeof(au32CpuIdSaved), au32CpuIdSaved,
2274	sizeof(au32CpuId), au32CpuId));
2275	else
2276	{
2277	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
2278	"Saved=%.*Rhxs\n"
2279	"Real =%.*Rhxs\n",
2280	sizeof(au32CpuIdSaved), au32CpuIdSaved,
2281	sizeof(au32CpuId), au32CpuId));
2282	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
2283	}
2284	}
2285	}
2286
2287	return rc;
2288	}
2289
2290
2291	/**
2292	* @copydoc FNSSMINTLOADPREP
2293	*/
2294	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
2295	{
2296	if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
2297	return VINF_SUCCESS;
2298
2299	/* just check this since we can. / /* @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
2300	if (pVM->cpum.s.fPendingRestore)
2301	{
2302	LogRel(("CPUM: Missing state!\n"));
2303	return VERR_INTERNAL_ERROR_2;
2304	}
2305
2306	/* Notify PGM of the NXE states in case they've changed. */
2307	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2308	PGMNotifyNxeChanged(&pVM->aCpus[iCpu], !!(pVM->aCpus[iCpu].cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
2309	return VINF_SUCCESS;
2310	}
2311
2312
2313	/**
2314	* Checks if the CPUM state restore is still pending.
2315	*
2316	* @returns true / false.
2317	* @param pVM The VM handle.
2318	*/
2319	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
2320	{
2321	return pVM->cpum.s.fPendingRestore;
2322	}
2323
2324
2325	/**
2326	* Formats the EFLAGS value into mnemonics.
2327	*
2328	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
2329	* @param efl The EFLAGS value.
2330	*/
2331	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
2332	{
2333	/*
2334	* Format the flags.
2335	*/
2336	static const struct
2337	{
2338	const char pszSet; const char pszClear; uint32_t fFlag;
2339	} s_aFlags[] =
2340	{
2341	{ "vip",NULL, X86_EFL_VIP },
2342	{ "vif",NULL, X86_EFL_VIF },
2343	{ "ac", NULL, X86_EFL_AC },
2344	{ "vm", NULL, X86_EFL_VM },
2345	{ "rf", NULL, X86_EFL_RF },
2346	{ "nt", NULL, X86_EFL_NT },
2347	{ "ov", "nv", X86_EFL_OF },
2348	{ "dn", "up", X86_EFL_DF },
2349	{ "ei", "di", X86_EFL_IF },
2350	{ "tf", NULL, X86_EFL_TF },
2351	{ "nt", "pl", X86_EFL_SF },
2352	{ "nz", "zr", X86_EFL_ZF },
2353	{ "ac", "na", X86_EFL_AF },
2354	{ "po", "pe", X86_EFL_PF },
2355	{ "cy", "nc", X86_EFL_CF },
2356	};
2357	char *psz = pszEFlags;
2358	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
2359	{
2360	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
2361	if (pszAdd)
2362	{
2363	strcpy(psz, pszAdd);
2364	psz += strlen(pszAdd);
2365	*psz++ = ' ';
2366	}
2367	}
2368	psz[-1] = '\0';
2369	}
2370
2371
2372	/**
2373	* Formats a full register dump.
2374	*
2375	* @param pVM VM Handle.
2376	* @param pCtx The context to format.
2377	* @param pCtxCore The context core to format.
2378	* @param pHlp Output functions.
2379	* @param enmType The dump type.
2380	* @param pszPrefix Register name prefix.
2381	*/
2382	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
2383	const char *pszPrefix)
2384	{
2385	NOREF(pVM);
2386
2387	/*
2388	* Format the EFLAGS.
2389	*/
2390	uint32_t efl = pCtxCore->eflags.u32;
2391	char szEFlags[80];
2392	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2393
2394	/*
2395	* Format the registers.
2396	*/
2397	switch (enmType)
2398	{
2399	case CPUMDUMPTYPE_TERSE:
2400	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2401	pHlp->pfnPrintf(pHlp,
2402	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2403	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2404	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2405	"%sr14=%016RX64 %sr15=%016RX64\n"
2406	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2407	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2408	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2409	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2410	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2411	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2412	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2413	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
2414	else
2415	pHlp->pfnPrintf(pHlp,
2416	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2417	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2418	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2419	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2420	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2421	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2422	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
2423	break;
2424
2425	case CPUMDUMPTYPE_DEFAULT:
2426	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2427	pHlp->pfnPrintf(pHlp,
2428	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2429	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2430	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2431	"%sr14=%016RX64 %sr15=%016RX64\n"
2432	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2433	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2434	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
2435	,
2436	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2437	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2438	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2439	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2440	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2441	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
2442	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2443	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
2444	else
2445	pHlp->pfnPrintf(pHlp,
2446	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2447	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2448	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2449	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
2450	,
2451	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2452	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2453	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2454	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
2455	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2456	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
2457	break;
2458
2459	case CPUMDUMPTYPE_VERBOSE:
2460	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2461	pHlp->pfnPrintf(pHlp,
2462	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2463	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2464	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2465	"%sr14=%016RX64 %sr15=%016RX64\n"
2466	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2467	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2468	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2469	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2470	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2471	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2472	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2473	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
2474	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
2475	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
2476	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2477	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2478	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2479	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
2480	,
2481	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2482	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2483	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2484	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2485	pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
2486	pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
2487	pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
2488	pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
2489	pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
2490	pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
2491	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2492	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2493	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2494	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2495	pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
2496	pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
2497	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2498	else
2499	pHlp->pfnPrintf(pHlp,
2500	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2501	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2502	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
2503	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
2504	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
2505	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
2506	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
2507	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
2508	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2509	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2510	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2511	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2512	,
2513	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2514	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2515	pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
2516	pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2517	pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
2518	pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2519	pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
2520	pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2521	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2522	pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
2523	pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
2524	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2525
2526	pHlp->pfnPrintf(pHlp,
2527	"%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
2528	"%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
2529	,
2530	pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW, pszPrefix, pCtx->fpu.FOP,
2531	pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK,
2532	pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsrvd1,
2533	pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2
2534	);
2535	unsigned iShift = (pCtx->fpu.FSW >> 11) & 7;
2536	for (unsigned iST = 0; iST < RT_ELEMENTS(pCtx->fpu.aRegs); iST++)
2537	{
2538	unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pCtx->fpu.aRegs);
2539	unsigned uTag = pCtx->fpu.FTW & (1 << iFPR) ? 1 : 0;
2540	char chSign = pCtx->fpu.aRegs[0].au16[4] & 0x8000 ? '-' : '+';
2541	unsigned iInteger = (unsigned)(pCtx->fpu.aRegs[0].au64[0] >> 63);
2542	uint64_t u64Fraction = pCtx->fpu.aRegs[0].au64[0] & UINT64_C(0x7fffffffffffffff);
2543	unsigned uExponent = pCtx->fpu.aRegs[0].au16[4] & 0x7fff;
2544	/** @todo This isn't entirenly correct and needs more work! */
2545	pHlp->pfnPrintf(pHlp,
2546	"%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu ^ %u",
2547	pszPrefix, iST, pszPrefix, iFPR,
2548	pCtx->fpu.aRegs[0].au16[4], pCtx->fpu.aRegs[0].au32[1], pCtx->fpu.aRegs[0].au32[0],
2549	uTag, chSign, iInteger, u64Fraction, uExponent);
2550	if (pCtx->fpu.aRegs[0].au16[5] \|\| pCtx->fpu.aRegs[0].au16[6] \|\| pCtx->fpu.aRegs[0].au16[7])
2551	pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
2552	pCtx->fpu.aRegs[0].au16[5], pCtx->fpu.aRegs[0].au16[6], pCtx->fpu.aRegs[0].au16[7]);
2553	else
2554	pHlp->pfnPrintf(pHlp, "\n");
2555	}
2556	for (unsigned iXMM = 0; iXMM < RT_ELEMENTS(pCtx->fpu.aXMM); iXMM++)
2557	pHlp->pfnPrintf(pHlp,
2558	iXMM & 1
2559	? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
2560	: "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
2561	pszPrefix, iXMM, iXMM < 10 ? " " : "",
2562	pCtx->fpu.aXMM[iXMM].au32[3],
2563	pCtx->fpu.aXMM[iXMM].au32[2],
2564	pCtx->fpu.aXMM[iXMM].au32[1],
2565	pCtx->fpu.aXMM[iXMM].au32[0]);
2566	for (unsigned i = 0; i < RT_ELEMENTS(pCtx->fpu.au32RsrvdRest); i++)
2567	if (pCtx->fpu.au32RsrvdRest[i])
2568	pHlp->pfnPrintf(pHlp, "%sRsrvdRest[i]=%RX32 (offset=%#x)\n",
2569	pszPrefix, i, pCtx->fpu.au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
2570
2571	pHlp->pfnPrintf(pHlp,
2572	"%sEFER =%016RX64\n"
2573	"%sPAT =%016RX64\n"
2574	"%sSTAR =%016RX64\n"
2575	"%sCSTAR =%016RX64\n"
2576	"%sLSTAR =%016RX64\n"
2577	"%sSFMASK =%016RX64\n"
2578	"%sKERNELGSBASE =%016RX64\n",
2579	pszPrefix, pCtx->msrEFER,
2580	pszPrefix, pCtx->msrPAT,
2581	pszPrefix, pCtx->msrSTAR,
2582	pszPrefix, pCtx->msrCSTAR,
2583	pszPrefix, pCtx->msrLSTAR,
2584	pszPrefix, pCtx->msrSFMASK,
2585	pszPrefix, pCtx->msrKERNELGSBASE);
2586	break;
2587	}
2588	}
2589
2590
2591	/**
2592	* Display all cpu states and any other cpum info.
2593	*
2594	* @param pVM VM Handle.
2595	* @param pHlp The info helper functions.
2596	* @param pszArgs Arguments, ignored.
2597	*/
2598	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2599	{
2600	cpumR3InfoGuest(pVM, pHlp, pszArgs);
2601	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
2602	cpumR3InfoHyper(pVM, pHlp, pszArgs);
2603	cpumR3InfoHost(pVM, pHlp, pszArgs);
2604	}
2605
2606
2607	/**
2608	* Parses the info argument.
2609	*
2610	* The argument starts with 'verbose', 'terse' or 'default' and then
2611	* continues with the comment string.
2612	*
2613	* @param pszArgs The pointer to the argument string.
2614	* @param penmType Where to store the dump type request.
2615	* @param ppszComment Where to store the pointer to the comment string.
2616	*/
2617	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
2618	{
2619	if (!pszArgs)
2620	{
2621	*penmType = CPUMDUMPTYPE_DEFAULT;
2622	*ppszComment = "";
2623	}
2624	else
2625	{
2626	if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
2627	{
2628	pszArgs += 5;
2629	*penmType = CPUMDUMPTYPE_VERBOSE;
2630	}
2631	else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
2632	{
2633	pszArgs += 5;
2634	*penmType = CPUMDUMPTYPE_TERSE;
2635	}
2636	else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
2637	{
2638	pszArgs += 7;
2639	*penmType = CPUMDUMPTYPE_DEFAULT;
2640	}
2641	else
2642	*penmType = CPUMDUMPTYPE_DEFAULT;
2643	*ppszComment = RTStrStripL(pszArgs);
2644	}
2645	}
2646
2647
2648	/**
2649	* Display the guest cpu state.
2650	*
2651	* @param pVM VM Handle.
2652	* @param pHlp The info helper functions.
2653	* @param pszArgs Arguments, ignored.
2654	*/
2655	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2656	{
2657	CPUMDUMPTYPE enmType;
2658	const char *pszComment;
2659	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2660
2661	/* @todo SMP support! */
2662	PVMCPU pVCpu = VMMGetCpu(pVM);
2663	if (!pVCpu)
2664	pVCpu = &pVM->aCpus[0];
2665
2666	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
2667
2668	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2669	cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
2670	}
2671
2672
2673	/**
2674	* Display the current guest instruction
2675	*
2676	* @param pVM VM Handle.
2677	* @param pHlp The info helper functions.
2678	* @param pszArgs Arguments, ignored.
2679	*/
2680	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2681	{
2682	NOREF(pszArgs);
2683
2684	/** @todo SMP support! */
2685	PVMCPU pVCpu = VMMGetCpu(pVM);
2686	if (!pVCpu)
2687	pVCpu = &pVM->aCpus[0];
2688
2689	char szInstruction[256];
2690	int rc = DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
2691	if (RT_SUCCESS(rc))
2692	pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
2693	}
2694
2695
2696	/**
2697	* Display the hypervisor cpu state.
2698	*
2699	* @param pVM VM Handle.
2700	* @param pHlp The info helper functions.
2701	* @param pszArgs Arguments, ignored.
2702	*/
2703	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2704	{
2705	CPUMDUMPTYPE enmType;
2706	const char *pszComment;
2707	/* @todo SMP */
2708	PVMCPU pVCpu = &pVM->aCpus[0];
2709
2710	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2711	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
2712	cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, pVCpu->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
2713	pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
2714	}
2715
2716
2717	/**
2718	* Display the host cpu state.
2719	*
2720	* @param pVM VM Handle.
2721	* @param pHlp The info helper functions.
2722	* @param pszArgs Arguments, ignored.
2723	*/
2724	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2725	{
2726	CPUMDUMPTYPE enmType;
2727	const char *pszComment;
2728	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2729	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
2730
2731	/*
2732	* Format the EFLAGS.
2733	*/
2734	/* @todo SMP */
2735	PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
2736	#if HC_ARCH_BITS == 32
2737	uint32_t efl = pCtx->eflags.u32;
2738	#else
2739	uint64_t efl = pCtx->rflags;
2740	#endif
2741	char szEFlags[80];
2742	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2743
2744	/*
2745	* Format the registers.
2746	*/
2747	#if HC_ARCH_BITS == 32
2748	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2749	if (!(pCtx->efer & MSR_K6_EFER_LMA))
2750	# endif
2751	{
2752	pHlp->pfnPrintf(pHlp,
2753	"eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
2754	"eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
2755	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
2756	"cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
2757	"dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
2758	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2759	,
2760	/pCtx->eax,/ pCtx->ebx, /pCtx->ecx, pCtx->edx,/ pCtx->esi, pCtx->edi,
2761	/pCtx->eip,/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
2762	(RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
2763	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3, pCtx->cr4,
2764	pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
2765	(uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
2766	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2767	}
2768	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2769	else
2770	# endif
2771	#endif
2772	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2773	{
2774	pHlp->pfnPrintf(pHlp,
2775	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
2776	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
2777	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
2778	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
2779	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
2780	"r14=%016RX64 r15=%016RX64\n"
2781	"iopl=%d %31s\n"
2782	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
2783	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
2784	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
2785	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
2786	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
2787	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
2788	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2789	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
2790	,
2791	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
2792	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
2793	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
2794	/pCtx->r8, pCtx->r9,/ pCtx->r10,
2795	pCtx->r11, pCtx->r12, pCtx->r13,
2796	pCtx->r14, pCtx->r15,
2797	X86_EFL_GET_IOPL(efl), szEFlags,
2798	(RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
2799	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
2800	pCtx->cr4, pCtx->ldtr, pCtx->tr,
2801	pCtx->dr0, pCtx->dr1, pCtx->dr2,
2802	pCtx->dr3, pCtx->dr6, pCtx->dr7,
2803	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
2804	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
2805	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
2806	}
2807	#endif
2808	}
2809
2810
2811	/**
2812	* Get L1 cache / TLS associativity.
2813	*/
2814	static const char getCacheAss(unsigned u, char pszBuf)
2815	{
2816	if (u == 0)
2817	return "res0 ";
2818	if (u == 1)
2819	return "direct";
2820	if (u == 255)
2821	return "fully";
2822	if (u >= 256)
2823	return "???";
2824
2825	RTStrPrintf(pszBuf, 16, "%d way", u);
2826	return pszBuf;
2827	}
2828
2829
2830	/**
2831	* Get L2 cache associativity.
2832	*/
2833	const char *getL2CacheAss(unsigned u)
2834	{
2835	switch (u)
2836	{
2837	case 0: return "off ";
2838	case 1: return "direct";
2839	case 2: return "2 way ";
2840	case 3: return "res3 ";
2841	case 4: return "4 way ";
2842	case 5: return "res5 ";
2843	case 6: return "8 way ";
2844	case 7: return "res7 ";
2845	case 8: return "16 way";
2846	case 9: return "res9 ";
2847	case 10: return "res10 ";
2848	case 11: return "res11 ";
2849	case 12: return "res12 ";
2850	case 13: return "res13 ";
2851	case 14: return "res14 ";
2852	case 15: return "fully ";
2853	default: return "????";
2854	}
2855	}
2856
2857
2858	/**
2859	* Display the guest CpuId leaves.
2860	*
2861	* @param pVM VM Handle.
2862	* @param pHlp The info helper functions.
2863	* @param pszArgs "terse", "default" or "verbose".
2864	*/
2865	static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2866	{
2867	/*
2868	* Parse the argument.
2869	*/
2870	unsigned iVerbosity = 1;
2871	if (pszArgs)
2872	{
2873	pszArgs = RTStrStripL(pszArgs);
2874	if (!strcmp(pszArgs, "terse"))
2875	iVerbosity--;
2876	else if (!strcmp(pszArgs, "verbose"))
2877	iVerbosity++;
2878	}
2879
2880	/*
2881	* Start cracking.
2882	*/
2883	CPUMCPUID Host;
2884	CPUMCPUID Guest;
2885	unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
2886
2887	pHlp->pfnPrintf(pHlp,
2888	" RAW Standard CPUIDs\n"
2889	" Function eax ebx ecx edx\n");
2890	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
2891	{
2892	Guest = pVM->cpum.s.aGuestCpuIdStd[i];
2893	ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2894
2895	pHlp->pfnPrintf(pHlp,
2896	"Gst: %08x %08x %08x %08x %08x%s\n"
2897	"Hst: %08x %08x %08x %08x\n",
2898	i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2899	i <= cStdMax ? "" : "*",
2900	Host.eax, Host.ebx, Host.ecx, Host.edx);
2901	}
2902
2903	/*
2904	* If verbose, decode it.
2905	*/
2906	if (iVerbosity)
2907	{
2908	Guest = pVM->cpum.s.aGuestCpuIdStd[0];
2909	pHlp->pfnPrintf(pHlp,
2910	"Name: %.04s%.04s%.04s\n"
2911	"Supports: 0-%x\n",
2912	&Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
2913	}
2914
2915	/*
2916	* Get Features.
2917	*/
2918	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
2919	pVM->cpum.s.aGuestCpuIdStd[0].ecx,
2920	pVM->cpum.s.aGuestCpuIdStd[0].edx);
2921	if (cStdMax >= 1 && iVerbosity)
2922	{
2923	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
2924
2925	Guest = pVM->cpum.s.aGuestCpuIdStd[1];
2926	uint32_t uEAX = Guest.eax;
2927
2928	pHlp->pfnPrintf(pHlp,
2929	"Family: %d \tExtended: %d \tEffective: %d\n"
2930	"Model: %d \tExtended: %d \tEffective: %d\n"
2931	"Stepping: %d\n"
2932	"Type: %d (%s)\n"
2933	"APIC ID: %#04x\n"
2934	"Logical CPUs: %d\n"
2935	"CLFLUSH Size: %d\n"
2936	"Brand ID: %#04x\n",
2937	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
2938	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
2939	ASMGetCpuStepping(uEAX),
2940	(uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
2941	(Guest.ebx >> 24) & 0xff,
2942	(Guest.ebx >> 16) & 0xff,
2943	(Guest.ebx >> 8) & 0xff,
2944	(Guest.ebx >> 0) & 0xff);
2945	if (iVerbosity == 1)
2946	{
2947	uint32_t uEDX = Guest.edx;
2948	pHlp->pfnPrintf(pHlp, "Features EDX: ");
2949	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
2950	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
2951	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
2952	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
2953	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
2954	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
2955	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
2956	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
2957	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
2958	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
2959	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
2960	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
2961	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
2962	if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
2963	if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
2964	if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
2965	if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
2966	if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
2967	if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
2968	if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
2969	if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
2970	if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
2971	if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
2972	if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
2973	if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
2974	if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
2975	if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
2976	if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
2977	if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
2978	if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
2979	if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
2980	if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
2981	pHlp->pfnPrintf(pHlp, "\n");
2982
2983	uint32_t uECX = Guest.ecx;
2984	pHlp->pfnPrintf(pHlp, "Features ECX: ");
2985	if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
2986	if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " PCLMUL");
2987	if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DTES64");
2988	if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
2989	if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
2990	if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
2991	if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SMX");
2992	if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
2993	if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
2994	if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " SSSE3");
2995	if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
2996	if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
2997	if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " FMA");
2998	if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
2999	if (uECX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " TPRUPDATE");
3000	if (uECX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " PDCM");
3001	if (uECX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " 16");
3002	if (uECX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PCID");
3003	if (uECX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " DCA");
3004	if (uECX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " SSE4.1");
3005	if (uECX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " SSE4.2");
3006	if (uECX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " X2APIC");
3007	if (uECX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " MOVBE");
3008	if (uECX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " POPCNT");
3009	if (uECX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " TSCDEADL");
3010	if (uECX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " AES");
3011	if (uECX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " XSAVE");
3012	if (uECX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " OSXSAVE");
3013	if (uECX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " AVX");
3014	if (uECX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " 29");
3015	if (uECX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
3016	if (uECX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 31");
3017	pHlp->pfnPrintf(pHlp, "\n");
3018	}
3019	else
3020	{
3021	ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3022
3023	X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
3024	X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
3025	X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
3026	X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
3027
3028	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3029	pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
3030	pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
3031	pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
3032	pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
3033	pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
3034	pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
3035	pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
3036	pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
3037	pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
3038	pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
3039	pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
3040	pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
3041	pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
3042	pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
3043	pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
3044	pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
3045	pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
3046	pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
3047	pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
3048	pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
3049	pHlp->pfnPrintf(pHlp, "20 - Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
3050	pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
3051	pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
3052	pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
3053	pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
3054	pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
3055	pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
3056	pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
3057	pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technology = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
3058	pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
3059	pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
3060	pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
3061
3062	pHlp->pfnPrintf(pHlp, "Supports SSE3 = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
3063	pHlp->pfnPrintf(pHlp, "PCLMULQDQ = %d (%d)\n", EcxGuest.u1PCLMULQDQ, EcxHost.u1PCLMULQDQ);
3064	pHlp->pfnPrintf(pHlp, "DS Area 64-bit layout = %d (%d)\n", EcxGuest.u1DTE64, EcxHost.u1DTE64);
3065	pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
3066	pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
3067	pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
3068	pHlp->pfnPrintf(pHlp, "SMX - Safer Mode Extensions = %d (%d)\n", EcxGuest.u1SMX, EcxHost.u1SMX);
3069	pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
3070	pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
3071	pHlp->pfnPrintf(pHlp, "Supplemental SSE3 instructions = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
3072	pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
3073	pHlp->pfnPrintf(pHlp, "11 - Reserved = %d (%d)\n", EcxGuest.u1Reserved1, EcxHost.u1Reserved1);
3074	pHlp->pfnPrintf(pHlp, "FMA extensions using YMM state = %d (%d)\n", EcxGuest.u1FMA, EcxHost.u1FMA);
3075	pHlp->pfnPrintf(pHlp, "CMPXCHG16B instruction = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
3076	pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
3077	pHlp->pfnPrintf(pHlp, "Perf/Debug Capability MSR = %d (%d)\n", EcxGuest.u1PDCM, EcxHost.u1PDCM);
3078	pHlp->pfnPrintf(pHlp, "16 - Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
3079	pHlp->pfnPrintf(pHlp, "PCID - Process-context identifiers = %d (%d)\n", EcxGuest.u1PCID, EcxHost.u1PCID);
3080	pHlp->pfnPrintf(pHlp, "DCA - Direct Cache Access = %d (%d)\n", EcxGuest.u1DCA, EcxHost.u1DCA);
3081	pHlp->pfnPrintf(pHlp, "SSE4.1 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_1, EcxHost.u1SSE4_1);
3082	pHlp->pfnPrintf(pHlp, "SSE4.2 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_2, EcxHost.u1SSE4_2);
3083	pHlp->pfnPrintf(pHlp, "Supports the x2APIC extensions = %d (%d)\n", EcxGuest.u1x2APIC, EcxHost.u1x2APIC);
3084	pHlp->pfnPrintf(pHlp, "MOVBE instruction = %d (%d)\n", EcxGuest.u1MOVBE, EcxHost.u1MOVBE);
3085	pHlp->pfnPrintf(pHlp, "POPCNT instruction = %d (%d)\n", EcxGuest.u1POPCNT, EcxHost.u1POPCNT);
3086	pHlp->pfnPrintf(pHlp, "TSC-Deadline LAPIC timer mode = %d (%d)\n", EcxGuest.u1TSCDEADLINE,EcxHost.u1TSCDEADLINE);
3087	pHlp->pfnPrintf(pHlp, "AESNI instruction extensions = %d (%d)\n", EcxGuest.u1AES, EcxHost.u1AES);
3088	pHlp->pfnPrintf(pHlp, "XSAVE/XRSTOR extended state feature = %d (%d)\n", EcxGuest.u1XSAVE, EcxHost.u1XSAVE);
3089	pHlp->pfnPrintf(pHlp, "Supports OSXSAVE = %d (%d)\n", EcxGuest.u1OSXSAVE, EcxHost.u1OSXSAVE);
3090	pHlp->pfnPrintf(pHlp, "AVX instruction extensions = %d (%d)\n", EcxGuest.u1AVX, EcxHost.u1AVX);
3091	pHlp->pfnPrintf(pHlp, "29/30 - Reserved = %#x (%#x)\n",EcxGuest.u2Reserved3, EcxHost.u2Reserved3);
3092	pHlp->pfnPrintf(pHlp, "Hypervisor Present (we're a guest) = %d (%d)\n", EcxGuest.u1HVP, EcxHost.u1HVP);
3093	}
3094	}
3095	if (cStdMax >= 2 && iVerbosity)
3096	{
3097	/** @todo */
3098	}
3099
3100	/*
3101	* Extended.
3102	* Implemented after AMD specs.
3103	*/
3104	unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
3105
3106	pHlp->pfnPrintf(pHlp,
3107	"\n"
3108	" RAW Extended CPUIDs\n"
3109	" Function eax ebx ecx edx\n");
3110	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
3111	{
3112	Guest = pVM->cpum.s.aGuestCpuIdExt[i];
3113	ASMCpuId(0x80000000 \| i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3114
3115	pHlp->pfnPrintf(pHlp,
3116	"Gst: %08x %08x %08x %08x %08x%s\n"
3117	"Hst: %08x %08x %08x %08x\n",
3118	0x80000000 \| i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3119	i <= cExtMax ? "" : "*",
3120	Host.eax, Host.ebx, Host.ecx, Host.edx);
3121	}
3122
3123	/*
3124	* Understandable output
3125	*/
3126	if (iVerbosity)
3127	{
3128	Guest = pVM->cpum.s.aGuestCpuIdExt[0];
3129	pHlp->pfnPrintf(pHlp,
3130	"Ext Name: %.4s%.4s%.4s\n"
3131	"Ext Supports: 0x80000000-%#010x\n",
3132	&Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
3133	}
3134
3135	if (iVerbosity && cExtMax >= 1)
3136	{
3137	Guest = pVM->cpum.s.aGuestCpuIdExt[1];
3138	uint32_t uEAX = Guest.eax;
3139	pHlp->pfnPrintf(pHlp,
3140	"Family: %d \tExtended: %d \tEffective: %d\n"
3141	"Model: %d \tExtended: %d \tEffective: %d\n"
3142	"Stepping: %d\n"
3143	"Brand ID: %#05x\n",
3144	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
3145	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
3146	ASMGetCpuStepping(uEAX),
3147	Guest.ebx & 0xfff);
3148
3149	if (iVerbosity == 1)
3150	{
3151	uint32_t uEDX = Guest.edx;
3152	pHlp->pfnPrintf(pHlp, "Features EDX: ");
3153	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
3154	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
3155	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
3156	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
3157	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
3158	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
3159	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
3160	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
3161	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
3162	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
3163	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
3164	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
3165	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
3166	if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
3167	if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
3168	if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
3169	if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
3170	if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
3171	if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
3172	if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
3173	if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
3174	if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
3175	if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
3176	if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
3177	if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
3178	if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
3179	if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
3180	if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
3181	if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
3182	if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
3183	if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
3184	if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
3185	pHlp->pfnPrintf(pHlp, "\n");
3186
3187	uint32_t uECX = Guest.ecx;
3188	pHlp->pfnPrintf(pHlp, "Features ECX: ");
3189	if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
3190	if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
3191	if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
3192	if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
3193	if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
3194	if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
3195	if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
3196	if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
3197	if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
3198	if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
3199	if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
3200	if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
3201	if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
3202	if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
3203	for (unsigned iBit = 5; iBit < 32; iBit++)
3204	if (uECX & RT_BIT(iBit))
3205	pHlp->pfnPrintf(pHlp, " %d", iBit);
3206	pHlp->pfnPrintf(pHlp, "\n");
3207	}
3208	else
3209	{
3210	ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3211
3212	uint32_t uEdxGst = Guest.edx;
3213	uint32_t uEdxHst = Host.edx;
3214	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3215	pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3216	pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3217	pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3218	pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3219	pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3220	pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3221	pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3222	pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3223	pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3224	pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3225	pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3226	pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3227	pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3228	pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3229	pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
3230	pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
3231	pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
3232	pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
3233	pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
3234	pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
3235	pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
3236	pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
3237	pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
3238	pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
3239	pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
3240	pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
3241	pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
3242	pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
3243	pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
3244	pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
3245	pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
3246	pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
3247
3248	uint32_t uEcxGst = Guest.ecx;
3249	uint32_t uEcxHst = Host.ecx;
3250	pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
3251	pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
3252	pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
3253	pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
3254	pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
3255	pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
3256	pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
3257	pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
3258	pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
3259	pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
3260	pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
3261	pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
3262	pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
3263	pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
3264	pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
3265	}
3266	}
3267
3268	if (iVerbosity && cExtMax >= 2)
3269	{
3270	char szString[443+1] = {0};
3271	uint32_t pu32 = (uint32_t )szString;
3272	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
3273	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
3274	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
3275	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
3276	if (cExtMax >= 3)
3277	{
3278	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
3279	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
3280	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
3281	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
3282	}
3283	if (cExtMax >= 4)
3284	{
3285	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
3286	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
3287	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
3288	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
3289	}
3290	pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
3291	}
3292
3293	if (iVerbosity && cExtMax >= 5)
3294	{
3295	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
3296	uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
3297	uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
3298	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
3299	char sz1[32];
3300	char sz2[32];
3301
3302	pHlp->pfnPrintf(pHlp,
3303	"TLB 2/4M Instr/Uni: %s %3d entries\n"
3304	"TLB 2/4M Data: %s %3d entries\n",
3305	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
3306	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
3307	pHlp->pfnPrintf(pHlp,
3308	"TLB 4K Instr/Uni: %s %3d entries\n"
3309	"TLB 4K Data: %s %3d entries\n",
3310	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
3311	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
3312	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
3313	"L1 Instr Cache Lines Per Tag: %d\n"
3314	"L1 Instr Cache Associativity: %s\n"
3315	"L1 Instr Cache Size: %d KB\n",
3316	(uEDX >> 0) & 0xff,
3317	(uEDX >> 8) & 0xff,
3318	getCacheAss((uEDX >> 16) & 0xff, sz1),
3319	(uEDX >> 24) & 0xff);
3320	pHlp->pfnPrintf(pHlp,
3321	"L1 Data Cache Line Size: %d bytes\n"
3322	"L1 Data Cache Lines Per Tag: %d\n"
3323	"L1 Data Cache Associativity: %s\n"
3324	"L1 Data Cache Size: %d KB\n",
3325	(uECX >> 0) & 0xff,
3326	(uECX >> 8) & 0xff,
3327	getCacheAss((uECX >> 16) & 0xff, sz1),
3328	(uECX >> 24) & 0xff);
3329	}
3330
3331	if (iVerbosity && cExtMax >= 6)
3332	{
3333	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
3334	uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
3335	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
3336
3337	pHlp->pfnPrintf(pHlp,
3338	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
3339	"L2 TLB 2/4M Data: %s %4d entries\n",
3340	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
3341	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
3342	pHlp->pfnPrintf(pHlp,
3343	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
3344	"L2 TLB 4K Data: %s %4d entries\n",
3345	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
3346	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
3347	pHlp->pfnPrintf(pHlp,
3348	"L2 Cache Line Size: %d bytes\n"
3349	"L2 Cache Lines Per Tag: %d\n"
3350	"L2 Cache Associativity: %s\n"
3351	"L2 Cache Size: %d KB\n",
3352	(uEDX >> 0) & 0xff,
3353	(uEDX >> 8) & 0xf,
3354	getL2CacheAss((uEDX >> 12) & 0xf),
3355	(uEDX >> 16) & 0xffff);
3356	}
3357
3358	if (iVerbosity && cExtMax >= 7)
3359	{
3360	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
3361
3362	pHlp->pfnPrintf(pHlp, "APM Features: ");
3363	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
3364	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
3365	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
3366	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
3367	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
3368	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
3369	for (unsigned iBit = 6; iBit < 32; iBit++)
3370	if (uEDX & RT_BIT(iBit))
3371	pHlp->pfnPrintf(pHlp, " %d", iBit);
3372	pHlp->pfnPrintf(pHlp, "\n");
3373	}
3374
3375	if (iVerbosity && cExtMax >= 8)
3376	{
3377	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
3378	uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
3379
3380	pHlp->pfnPrintf(pHlp,
3381	"Physical Address Width: %d bits\n"
3382	"Virtual Address Width: %d bits\n"
3383	"Guest Physical Address Width: %d bits\n",
3384	(uEAX >> 0) & 0xff,
3385	(uEAX >> 8) & 0xff,
3386	(uEAX >> 16) & 0xff);
3387	pHlp->pfnPrintf(pHlp,
3388	"Physical Core Count: %d\n",
3389	(uECX >> 0) & 0xff);
3390	}
3391
3392
3393	/*
3394	* Centaur.
3395	*/
3396	unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
3397
3398	pHlp->pfnPrintf(pHlp,
3399	"\n"
3400	" RAW Centaur CPUIDs\n"
3401	" Function eax ebx ecx edx\n");
3402	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
3403	{
3404	Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
3405	ASMCpuId(0xc0000000 \| i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3406
3407	pHlp->pfnPrintf(pHlp,
3408	"Gst: %08x %08x %08x %08x %08x%s\n"
3409	"Hst: %08x %08x %08x %08x\n",
3410	0xc0000000 \| i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3411	i <= cCentaurMax ? "" : "*",
3412	Host.eax, Host.ebx, Host.ecx, Host.edx);
3413	}
3414
3415	/*
3416	* Understandable output
3417	*/
3418	if (iVerbosity)
3419	{
3420	Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
3421	pHlp->pfnPrintf(pHlp,
3422	"Centaur Supports: 0xc0000000-%#010x\n",
3423	Guest.eax);
3424	}
3425
3426	if (iVerbosity && cCentaurMax >= 1)
3427	{
3428	ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3429	uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
3430	uint32_t uEdxHst = Host.edx;
3431
3432	if (iVerbosity == 1)
3433	{
3434	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
3435	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
3436	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
3437	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
3438	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
3439	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
3440	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
3441	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
3442	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
3443	/* possibly indicating MM/HE and MM/HE-E on older chips... */
3444	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
3445	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
3446	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
3447	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
3448	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
3449	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
3450	for (unsigned iBit = 14; iBit < 32; iBit++)
3451	if (uEdxGst & RT_BIT(iBit))
3452	pHlp->pfnPrintf(pHlp, " %d", iBit);
3453	pHlp->pfnPrintf(pHlp, "\n");
3454	}
3455	else
3456	{
3457	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3458	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3459	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3460	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3461	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3462	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3463	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3464	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3465	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3466	/* possibly indicating MM/HE and MM/HE-E on older chips... */
3467	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3468	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3469	pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3470	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3471	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3472	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3473	for (unsigned iBit = 14; iBit < 32; iBit++)
3474	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
3475	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
3476	pHlp->pfnPrintf(pHlp, "\n");
3477	}
3478	}
3479	}
3480
3481
3482	/**
3483	* Structure used when disassembling and instructions in DBGF.
3484	* This is used so the reader function can get the stuff it needs.
3485	*/
3486	typedef struct CPUMDISASSTATE
3487	{
3488	/** Pointer to the CPU structure. */
3489	PDISCPUSTATE pCpu;
3490	/** The VM handle. */
3491	PVM pVM;
3492	/** The VMCPU handle. */
3493	PVMCPU pVCpu;
3494	/** Pointer to the first byte in the segment. */
3495	RTGCUINTPTR GCPtrSegBase;
3496	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
3497	RTGCUINTPTR GCPtrSegEnd;
3498	/** The size of the segment minus 1. */
3499	RTGCUINTPTR cbSegLimit;
3500	/** Pointer to the current page - R3 Ptr. */
3501	void const *pvPageR3;
3502	/** Pointer to the current page - GC Ptr. */
3503	RTGCPTR pvPageGC;
3504	/** The lock information that PGMPhysReleasePageMappingLock needs. */
3505	PGMPAGEMAPLOCK PageMapLock;
3506	/** Whether the PageMapLock is valid or not. */
3507	bool fLocked;
3508	/** 64 bits mode or not. */
3509	bool f64Bits;
3510	} CPUMDISASSTATE, *PCPUMDISASSTATE;
3511
3512
3513	/**
3514	* Instruction reader.
3515	*
3516	* @returns VBox status code.
3517	* @param PtrSrc Address to read from.
3518	* In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
3519	* @param pu8Dst Where to store the bytes.
3520	* @param cbRead Number of bytes to read.
3521	* @param uDisCpu Pointer to the disassembler cpu state.
3522	* In this context it's always pointer to the Core of a DBGFDISASSTATE.
3523	*/
3524	static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t pu8Dst, unsigned cbRead, void uDisCpu)
3525	{
3526	PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
3527	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
3528	Assert(cbRead > 0);
3529	for (;;)
3530	{
3531	RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
3532
3533	/* Need to update the page translation? */
3534	if ( !pState->pvPageR3
3535	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
3536	{
3537	int rc = VINF_SUCCESS;
3538
3539	/* translate the address */
3540	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
3541	if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
3542	&& !HWACCMIsEnabled(pState->pVM))
3543	{
3544	pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
3545	if (!pState->pvPageR3)
3546	rc = VERR_INVALID_POINTER;
3547	}
3548	else
3549	{
3550	/* Release mapping lock previously acquired. */
3551	if (pState->fLocked)
3552	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
3553	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
3554	pState->fLocked = RT_SUCCESS_NP(rc);
3555	}
3556	if (RT_FAILURE(rc))
3557	{
3558	pState->pvPageR3 = NULL;
3559	return rc;
3560	}
3561	}
3562
3563	/* check the segment limit */
3564	if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
3565	return VERR_OUT_OF_SELECTOR_BOUNDS;
3566
3567	/* calc how much we can read */
3568	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
3569	if (!pState->f64Bits)
3570	{
3571	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
3572	if (cb > cbSeg && cbSeg)
3573	cb = cbSeg;
3574	}
3575	if (cb > cbRead)
3576	cb = cbRead;
3577
3578	/* read and advance */
3579	memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
3580	cbRead -= cb;
3581	if (!cbRead)
3582	return VINF_SUCCESS;
3583	pu8Dst += cb;
3584	PtrSrc += cb;
3585	}
3586	}
3587
3588
3589	/**
3590	* Disassemble an instruction and return the information in the provided structure.
3591	*
3592	* @returns VBox status code.
3593	* @param pVM VM Handle
3594	* @param pVCpu VMCPU Handle
3595	* @param pCtx CPU context
3596	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
3597	* @param pCpu Disassembly state
3598	* @param pszPrefix String prefix for logging (debug only)
3599	*
3600	*/
3601	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
3602	{
3603	CPUMDISASSTATE State;
3604	int rc;
3605
3606	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
3607	State.pCpu = pCpu;
3608	State.pvPageGC = 0;
3609	State.pvPageR3 = NULL;
3610	State.pVM = pVM;
3611	State.pVCpu = pVCpu;
3612	State.fLocked = false;
3613	State.f64Bits = false;
3614
3615	/*
3616	* Get selector information.
3617	*/
3618	if ( (pCtx->cr0 & X86_CR0_PE)
3619	&& pCtx->eflags.Bits.u1VM == 0)
3620	{
3621	if (CPUMAreHiddenSelRegsValid(pVCpu))
3622	{
3623	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
3624	State.GCPtrSegBase = pCtx->csHid.u64Base;
3625	State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
3626	State.cbSegLimit = pCtx->csHid.u32Limit;
3627	pCpu->mode = (State.f64Bits)
3628	? CPUMODE_64BIT
3629	: pCtx->csHid.Attr.n.u1DefBig
3630	? CPUMODE_32BIT
3631	: CPUMODE_16BIT;
3632	}
3633	else
3634	{
3635	DBGFSELINFO SelInfo;
3636
3637	rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
3638	if (RT_FAILURE(rc))
3639	{
3640	AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
3641	return rc;
3642	}
3643
3644	/*
3645	* Validate the selector.
3646	*/
3647	rc = DBGFR3SelInfoValidateCS(&SelInfo, pCtx->ss);
3648	if (RT_FAILURE(rc))
3649	{
3650	AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
3651	return rc;
3652	}
3653	State.GCPtrSegBase = SelInfo.GCPtrBase;
3654	State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
3655	State.cbSegLimit = SelInfo.cbLimit;
3656	pCpu->mode = SelInfo.u.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
3657	}
3658	}
3659	else
3660	{
3661	/* real or V86 mode */
3662	pCpu->mode = CPUMODE_16BIT;
3663	State.GCPtrSegBase = pCtx->cs * 16;
3664	State.GCPtrSegEnd = 0xFFFFFFFF;
3665	State.cbSegLimit = 0xFFFFFFFF;
3666	}
3667
3668	/*
3669	* Disassemble the instruction.
3670	*/
3671	pCpu->pfnReadBytes = cpumR3DisasInstrRead;
3672	pCpu->apvUserData[0] = &State;
3673
3674	uint32_t cbInstr;
3675	#ifndef LOG_ENABLED
3676	rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
3677	if (RT_SUCCESS(rc))
3678	{
3679	#else
3680	char szOutput[160];
3681	rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
3682	if (RT_SUCCESS(rc))
3683	{
3684	/* log it */
3685	if (pszPrefix)
3686	Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
3687	else
3688	Log(("%s", szOutput));
3689	#endif
3690	rc = VINF_SUCCESS;
3691	}
3692	else
3693	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs, GCPtrPC, rc));
3694
3695	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
3696	if (State.fLocked)
3697	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
3698
3699	return rc;
3700	}
3701
3702	#ifdef DEBUG
3703
3704	/**
3705	* Disassemble an instruction and dump it to the log
3706	*
3707	* @returns VBox status code.
3708	* @param pVM VM Handle
3709	* @param pVCpu VMCPU Handle
3710	* @param pCtx CPU context
3711	* @param pc GC instruction pointer
3712	* @param pszPrefix String prefix for logging
3713	*
3714	* @deprecated Use DBGFR3DisasInstrCurrentLog().
3715	*/
3716	VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix)
3717	{
3718	DISCPUSTATE Cpu;
3719	CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pc, &Cpu, pszPrefix);
3720	}
3721
3722
3723	/**
3724	* Debug helper - Saves guest context on raw mode entry (for fatal dump)
3725	*
3726	* @internal
3727	*/
3728	VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
3729	{
3730	/** @todo SMP support!! */
3731	pVM->cpum.s.GuestEntry = *CPUMQueryGuestCtxPtr(VMMGetCpu(pVM));
3732	}
3733
3734	#endif /* DEBUG */
3735
3736	/**
3737	* API for controlling a few of the CPU features found in CR4.
3738	*
3739	* Currently only X86_CR4_TSD is accepted as input.
3740	*
3741	* @returns VBox status code.
3742	*
3743	* @param pVM The VM handle.
3744	* @param fOr The CR4 OR mask.
3745	* @param fAnd The CR4 AND mask.
3746	*/
3747	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
3748	{
3749	AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
3750	AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
3751
3752	pVM->cpum.s.CR4.OrMask &= fAnd;
3753	pVM->cpum.s.CR4.OrMask \|= fOr;
3754
3755	return VINF_SUCCESS;
3756	}
3757
3758
3759	/**
3760	* Gets a pointer to the array of standard CPUID leaves.
3761	*
3762	* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
3763	*
3764	* @returns Pointer to the standard CPUID leaves (read-only).
3765	* @param pVM The VM handle.
3766	* @remark Intended for PATM.
3767	*/
3768	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM)
3769	{
3770	return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
3771	}
3772
3773
3774	/**
3775	* Gets a pointer to the array of extended CPUID leaves.
3776	*
3777	* CPUMGetGuestCpuIdExtMax() give the size of the array.
3778	*
3779	* @returns Pointer to the extended CPUID leaves (read-only).
3780	* @param pVM The VM handle.
3781	* @remark Intended for PATM.
3782	*/
3783	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM)
3784	{
3785	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
3786	}
3787
3788
3789	/**
3790	* Gets a pointer to the array of centaur CPUID leaves.
3791	*
3792	* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
3793	*
3794	* @returns Pointer to the centaur CPUID leaves (read-only).
3795	* @param pVM The VM handle.
3796	* @remark Intended for PATM.
3797	*/
3798	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM)
3799	{
3800	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
3801	}
3802
3803
3804	/**
3805	* Gets a pointer to the default CPUID leaf.
3806	*
3807	* @returns Pointer to the default CPUID leaf (read-only).
3808	* @param pVM The VM handle.
3809	* @remark Intended for PATM.
3810	*/
3811	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM)
3812	{
3813	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
3814	}
3815
3816
3817	/**
3818	* Transforms the guest CPU state to raw-ring mode.
3819	*
3820	* This function will change the any of the cs and ss register with DPL=0 to DPL=1.
3821	*
3822	* @returns VBox status. (recompiler failure)
3823	* @param pVCpu The VMCPU handle.
3824	* @param pCtxCore The context core (for trap usage).
3825	* @see @ref pg_raw
3826	*/
3827	VMMR3DECL(int) CPUMR3RawEnter(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
3828	{
3829	PVM pVM = pVCpu->CTX_SUFF(pVM);
3830
3831	Assert(!pVCpu->cpum.s.fRawEntered);
3832	Assert(!pVCpu->cpum.s.fRemEntered);
3833	if (!pCtxCore)
3834	pCtxCore = CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
3835
3836	/*
3837	* Are we in Ring-0?
3838	*/
3839	if ( pCtxCore->ss && (pCtxCore->ss & X86_SEL_RPL) == 0
3840	&& !pCtxCore->eflags.Bits.u1VM)
3841	{
3842	/*
3843	* Enter execution mode.
3844	*/
3845	PATMRawEnter(pVM, pCtxCore);
3846
3847	/*
3848	* Set CPL to Ring-1.
3849	*/
3850	pCtxCore->ss \|= 1;
3851	if (pCtxCore->cs && (pCtxCore->cs & X86_SEL_RPL) == 0)
3852	pCtxCore->cs \|= 1;
3853	}
3854	else
3855	{
3856	AssertMsg((pCtxCore->ss & X86_SEL_RPL) >= 2 \|\| pCtxCore->eflags.Bits.u1VM,
3857	("ring-1 code not supported\n"));
3858	/*
3859	* PATM takes care of IOPL and IF flags for Ring-3 and Ring-2 code as well.
3860	*/
3861	PATMRawEnter(pVM, pCtxCore);
3862	}
3863
3864	/*
3865	* Invalidate the hidden registers.
3866	*/
3867	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
3868
3869	/*
3870	* Assert sanity.
3871	*/
3872	AssertMsg((pCtxCore->eflags.u32 & X86_EFL_IF), ("X86_EFL_IF is clear\n"));
3873	AssertReleaseMsg( pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss & X86_SEL_RPL)
3874	\|\| pCtxCore->eflags.Bits.u1VM,
3875	("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss & X86_SEL_RPL));
3876	Assert((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE)) == (X86_CR0_PG \| X86_CR0_PE \| X86_CR0_WP));
3877
3878	pCtxCore->eflags.u32 \|= X86_EFL_IF; /* paranoia */
3879
3880	pVCpu->cpum.s.fRawEntered = true;
3881	return VINF_SUCCESS;
3882	}
3883
3884
3885	/**
3886	* Transforms the guest CPU state from raw-ring mode to correct values.
3887	*
3888	* This function will change any selector registers with DPL=1 to DPL=0.
3889	*
3890	* @returns Adjusted rc.
3891	* @param pVCpu The VMCPU handle.
3892	* @param rc Raw mode return code
3893	* @param pCtxCore The context core (for trap usage).
3894	* @see @ref pg_raw
3895	*/
3896	VMMR3DECL(int) CPUMR3RawLeave(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, int rc)
3897	{
3898	PVM pVM = pVCpu->CTX_SUFF(pVM);
3899
3900	/*
3901	* Don't leave if we've already left (in GC).
3902	*/
3903	Assert(pVCpu->cpum.s.fRawEntered);
3904	Assert(!pVCpu->cpum.s.fRemEntered);
3905	if (!pVCpu->cpum.s.fRawEntered)
3906	return rc;
3907	pVCpu->cpum.s.fRawEntered = false;
3908
3909	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3910	if (!pCtxCore)
3911	pCtxCore = CPUMCTX2CORE(pCtx);
3912	Assert(pCtxCore->eflags.Bits.u1VM \|\| (pCtxCore->ss & X86_SEL_RPL));
3913	AssertMsg(pCtxCore->eflags.Bits.u1VM \|\| pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss & X86_SEL_RPL),
3914	("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss & X86_SEL_RPL));
3915
3916	/*
3917	* Are we executing in raw ring-1?
3918	*/
3919	if ( (pCtxCore->ss & X86_SEL_RPL) == 1
3920	&& !pCtxCore->eflags.Bits.u1VM)
3921	{
3922	/*
3923	* Leave execution mode.
3924	*/
3925	PATMRawLeave(pVM, pCtxCore, rc);
3926	/* Not quite sure if this is really required, but shouldn't harm (too much anyways). */
3927	/** @todo See what happens if we remove this. */
3928	if ((pCtxCore->ds & X86_SEL_RPL) == 1)
3929	pCtxCore->ds &= ~X86_SEL_RPL;
3930	if ((pCtxCore->es & X86_SEL_RPL) == 1)
3931	pCtxCore->es &= ~X86_SEL_RPL;
3932	if ((pCtxCore->fs & X86_SEL_RPL) == 1)
3933	pCtxCore->fs &= ~X86_SEL_RPL;
3934	if ((pCtxCore->gs & X86_SEL_RPL) == 1)
3935	pCtxCore->gs &= ~X86_SEL_RPL;
3936
3937	/*
3938	* Ring-1 selector => Ring-0.
3939	*/
3940	pCtxCore->ss &= ~X86_SEL_RPL;
3941	if ((pCtxCore->cs & X86_SEL_RPL) == 1)
3942	pCtxCore->cs &= ~X86_SEL_RPL;
3943	}
3944	else
3945	{
3946	/*
3947	* PATM is taking care of the IOPL and IF flags for us.
3948	*/
3949	PATMRawLeave(pVM, pCtxCore, rc);
3950	if (!pCtxCore->eflags.Bits.u1VM)
3951	{
3952	/** @todo See what happens if we remove this. */
3953	if ((pCtxCore->ds & X86_SEL_RPL) == 1)
3954	pCtxCore->ds &= ~X86_SEL_RPL;
3955	if ((pCtxCore->es & X86_SEL_RPL) == 1)
3956	pCtxCore->es &= ~X86_SEL_RPL;
3957	if ((pCtxCore->fs & X86_SEL_RPL) == 1)
3958	pCtxCore->fs &= ~X86_SEL_RPL;
3959	if ((pCtxCore->gs & X86_SEL_RPL) == 1)
3960	pCtxCore->gs &= ~X86_SEL_RPL;
3961	}
3962	}
3963
3964	return rc;
3965	}
3966
3967
3968	/**
3969	* Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
3970	*
3971	* Only REM should ever call this function!
3972	*
3973	* @returns The changed flags.
3974	* @param pVCpu The VMCPU handle.
3975	* @param puCpl Where to return the current privilege level (CPL).
3976	*/
3977	VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
3978	{
3979	Assert(!pVCpu->cpum.s.fRawEntered);
3980	Assert(!pVCpu->cpum.s.fRemEntered);
3981
3982	/*
3983	* Get the CPL first.
3984	*/
3985	*puCpl = CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(&pVCpu->cpum.s.Guest));
3986
3987	/*
3988	* Get and reset the flags, leaving CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID set.
3989	*/
3990	uint32_t fFlags = pVCpu->cpum.s.fChanged;
3991	pVCpu->cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID; /* leave it set */
3992
3993	/** @todo change the switcher to use the fChanged flags. */
3994	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
3995	{
3996	fFlags \|= CPUM_CHANGED_FPU_REM;
3997	pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
3998	}
3999
4000	pVCpu->cpum.s.fRemEntered = true;
4001	return fFlags;
4002	}
4003
4004
4005	/**
4006	* Leaves REM and works the CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID flag.
4007	*
4008	* @param pVCpu The virtual CPU handle.
4009	* @param fNoOutOfSyncSels This is @c false if there are out of sync
4010	* registers.
4011	*/
4012	VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
4013	{
4014	Assert(!pVCpu->cpum.s.fRawEntered);
4015	Assert(pVCpu->cpum.s.fRemEntered);
4016
4017	if (fNoOutOfSyncSels)
4018	pVCpu->cpum.s.fChanged &= ~CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
4019	else
4020	pVCpu->cpum.s.fChanged \|= ~CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
4021
4022	pVCpu->cpum.s.fRemEntered = false;
4023	}
4024

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 40170

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