HMR0.cpp@ 80587

最後變更在這個檔案從80587是 80587,由 vboxsync 提交於 6 年前
VMM/HM: bugref:9546 Fix registering of the longjmp callback to be soon after enabling VT-x/AMD-V on the CPU. This gives us proper behavior when ring-0 assertions happen prior to VMXR0RunGuestCode/SVMR0RunGuestCode so we can relinquish hardware resources on the way out.
屬性 svn:eol-style 設為 `native` 屬性 svn:keywords 設為 `Id Revision`
檔案大小: 69.8 KB

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1	/* $Id: HMR0.cpp 80587 2019-09-04 17:44:20Z vboxsync $ */
2	/** @file
3	* Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.alldomusa.eu.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include <VBox/vmm/hm.h>
25	#include <VBox/vmm/pgm.h>
26	#include "HMInternal.h"
27	#include <VBox/vmm/vmcc.h>
28	#include <VBox/vmm/hm_svm.h>
29	#include <VBox/vmm/hmvmxinline.h>
30	#include <VBox/err.h>
31	#include <VBox/log.h>
32	#include <iprt/assert.h>
33	#include <iprt/asm.h>
34	#include <iprt/asm-amd64-x86.h>
35	#include <iprt/cpuset.h>
36	#include <iprt/mem.h>
37	#include <iprt/memobj.h>
38	#include <iprt/once.h>
39	#include <iprt/param.h>
40	#include <iprt/power.h>
41	#include <iprt/string.h>
42	#include <iprt/thread.h>
43	#include <iprt/x86.h>
44	#include "HMVMXR0.h"
45	#include "HMSVMR0.h"
46
47
48	/*********************************************************************************************************************************
49	* Internal Functions *
50	*********************************************************************************************************************************/
51	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
52	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
55	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
56	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
57
58
59	/*********************************************************************************************************************************
60	* Structures and Typedefs *
61	*********************************************************************************************************************************/
62	/**
63	* This is used to manage the status code of a RTMpOnAll in HM.
64	*/
65	typedef struct HMR0FIRSTRC
66	{
67	/** The status code. */
68	int32_t volatile rc;
69	/** The ID of the CPU reporting the first failure. */
70	RTCPUID volatile idCpu;
71	} HMR0FIRSTRC;
72	/** Pointer to a first return code structure. */
73	typedef HMR0FIRSTRC *PHMR0FIRSTRC;
74
75
76	/*********************************************************************************************************************************
77	* Global Variables *
78	*********************************************************************************************************************************/
79	/**
80	* Global data.
81	*/
82	static struct
83	{
84	/** Per CPU globals. */
85	HMPHYSCPU aCpuInfo[RTCPUSET_MAX_CPUS];
86
87	/** @name Ring-0 method table for AMD-V and VT-x specific operations.
88	* @{ */
89	DECLR0CALLBACKMEMBER(int, pfnEnterSession, (PVMCPUCC pVCpu));
90	DECLR0CALLBACKMEMBER(void, pfnThreadCtxCallback, (RTTHREADCTXEVENT enmEvent, PVMCPUCC pVCpu, bool fGlobalInit));
91	DECLR0CALLBACKMEMBER(int, pfnCallRing3Callback, (PVMCPUCC pVCpu, VMMCALLRING3 enmOperation));
92	DECLR0CALLBACKMEMBER(int, pfnExportHostState, (PVMCPUCC pVCpu));
93	DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnRunGuestCode, (PVMCPUCC pVCpu));
94	DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHMPHYSCPU pHostCpu, PVMCC pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
95	bool fEnabledByHost, PCSUPHWVIRTMSRS pHwvirtMsrs));
96	DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
97	DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVMCC pVM));
98	DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVMCC pVM));
99	DECLR0CALLBACKMEMBER(int, pfnSetupVM, (PVMCC pVM));
100	/** @} */
101
102	/** Hardware-virtualization data. */
103	struct
104	{
105	union
106	{
107	/** VT-x data. */
108	struct
109	{
110	/** Host CR4 value (set by ring-0 VMX init) */
111	uint64_t u64HostCr4;
112	/** Host EFER value (set by ring-0 VMX init) */
113	uint64_t u64HostMsrEfer;
114	/** Host SMM monitor control (used for logging/diagnostics) */
115	uint64_t u64HostSmmMonitorCtl;
116	/** Last instruction error. */
117	uint32_t ulLastInstrError;
118	/** The shift mask employed by the VMX-Preemption timer. */
119	uint8_t cPreemptTimerShift;
120	/** Padding. */
121	uint8_t abPadding[3];
122	/** Whether we're using the preemption timer or not. */
123	bool fUsePreemptTimer;
124	/** Whether we're using SUPR0EnableVTx or not. */
125	bool fUsingSUPR0EnableVTx;
126	/** Set if we've called SUPR0EnableVTx(true) and should disable it during
127	* module termination. */
128	bool fCalledSUPR0EnableVTx;
129	/** Set to by us to indicate VMX is supported by the CPU. */
130	bool fSupported;
131	} vmx;
132
133	/** AMD-V data. */
134	struct
135	{
136	/** SVM revision. */
137	uint32_t u32Rev;
138	/** SVM feature bits from cpuid 0x8000000a */
139	uint32_t u32Features;
140	/** Padding. */
141	bool afPadding[3];
142	/** Set by us to indicate SVM is supported by the CPU. */
143	bool fSupported;
144	} svm;
145	} u;
146	/** Maximum allowed ASID/VPID (inclusive). */
147	uint32_t uMaxAsid;
148	/** MSRs. */
149	SUPHWVIRTMSRS Msrs;
150	} hwvirt;
151
152	/** Last recorded error code during HM ring-0 init. */
153	int32_t rcInit;
154
155	/** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
156	* enabled and disabled each time it's used to execute guest code. */
157	bool fGlobalInit;
158	/** Indicates whether the host is suspending or not. We'll refuse a few
159	* actions when the host is being suspended to speed up the suspending and
160	* avoid trouble. */
161	bool volatile fSuspended;
162
163	/** Whether we've already initialized all CPUs.
164	* @remarks We could check the EnableAllCpusOnce state, but this is
165	* simpler and hopefully easier to understand. */
166	bool fEnabled;
167	/** Serialize initialization in HMR0EnableAllCpus. */
168	RTONCE EnableAllCpusOnce;
169	} g_HmR0;
170
171
172	/**
173	* Initializes a first return code structure.
174	*
175	* @param pFirstRc The structure to init.
176	*/
177	static void hmR0FirstRcInit(PHMR0FIRSTRC pFirstRc)
178	{
179	pFirstRc->rc = VINF_SUCCESS;
180	pFirstRc->idCpu = NIL_RTCPUID;
181	}
182
183
184	/**
185	* Try set the status code (success ignored).
186	*
187	* @param pFirstRc The first return code structure.
188	* @param rc The status code.
189	*/
190	static void hmR0FirstRcSetStatus(PHMR0FIRSTRC pFirstRc, int rc)
191	{
192	if ( RT_FAILURE(rc)
193	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
194	pFirstRc->idCpu = RTMpCpuId();
195	}
196
197
198	/**
199	* Get the status code of a first return code structure.
200	*
201	* @returns The status code; VINF_SUCCESS or error status, no informational or
202	* warning errors.
203	* @param pFirstRc The first return code structure.
204	*/
205	static int hmR0FirstRcGetStatus(PHMR0FIRSTRC pFirstRc)
206	{
207	return pFirstRc->rc;
208	}
209
210
211	#ifdef VBOX_STRICT
212	# ifndef DEBUG_bird
213	/**
214	* Get the CPU ID on which the failure status code was reported.
215	*
216	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
217	* @param pFirstRc The first return code structure.
218	*/
219	static RTCPUID hmR0FirstRcGetCpuId(PHMR0FIRSTRC pFirstRc)
220	{
221	return pFirstRc->idCpu;
222	}
223	# endif
224	#endif /* VBOX_STRICT */
225
226
227	/** @name Dummy callback handlers.
228	* @{ */
229
230	static DECLCALLBACK(int) hmR0DummyEnter(PVMCPUCC pVCpu)
231	{
232	RT_NOREF1(pVCpu);
233	return VINF_SUCCESS;
234	}
235
236	static DECLCALLBACK(void) hmR0DummyThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPUCC pVCpu, bool fGlobalInit)
237	{
238	RT_NOREF3(enmEvent, pVCpu, fGlobalInit);
239	}
240
241	static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMPHYSCPU pHostCpu, PVMCC pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
242	bool fEnabledBySystem, PCSUPHWVIRTMSRS pHwvirtMsrs)
243	{
244	RT_NOREF6(pHostCpu, pVM, pvCpuPage, HCPhysCpuPage, fEnabledBySystem, pHwvirtMsrs);
245	return VINF_SUCCESS;
246	}
247
248	static DECLCALLBACK(int) hmR0DummyDisableCpu(void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
249	{
250	RT_NOREF2(pvCpuPage, HCPhysCpuPage);
251	return VINF_SUCCESS;
252	}
253
254	static DECLCALLBACK(int) hmR0DummyInitVM(PVMCC pVM)
255	{
256	RT_NOREF1(pVM);
257	return VINF_SUCCESS;
258	}
259
260	static DECLCALLBACK(int) hmR0DummyTermVM(PVMCC pVM)
261	{
262	RT_NOREF1(pVM);
263	return VINF_SUCCESS;
264	}
265
266	static DECLCALLBACK(int) hmR0DummySetupVM(PVMCC pVM)
267	{
268	RT_NOREF1(pVM);
269	return VINF_SUCCESS;
270	}
271
272	static DECLCALLBACK(int) hmR0DummyCallRing3Callback(PVMCPUCC pVCpu, VMMCALLRING3 enmOperation)
273	{
274	RT_NOREF2(pVCpu, enmOperation);
275	return VINF_SUCCESS;
276	}
277
278	static DECLCALLBACK(VBOXSTRICTRC) hmR0DummyRunGuestCode(PVMCPUCC pVCpu)
279	{
280	RT_NOREF(pVCpu);
281	return VINF_SUCCESS;
282	}
283
284	static DECLCALLBACK(int) hmR0DummyExportHostState(PVMCPUCC pVCpu)
285	{
286	RT_NOREF1(pVCpu);
287	return VINF_SUCCESS;
288	}
289
290	/** @} */
291
292
293	/**
294	* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count
295	* Down at the Rate Specified" erratum.
296	*
297	* Errata names and related steppings:
298	* - BA86 - D0.
299	* - AAX65 - C2.
300	* - AAU65 - C2, K0.
301	* - AAO95 - B1.
302	* - AAT59 - C2.
303	* - AAK139 - D0.
304	* - AAM126 - C0, C1, D0.
305	* - AAN92 - B1.
306	* - AAJ124 - C0, D0.
307	* - AAP86 - B1.
308	*
309	* Steppings: B1, C0, C1, C2, D0, K0.
310	*
311	* @returns true if subject to it, false if not.
312	*/
313	static bool hmR0InitIntelIsSubjectToVmxPreemptTimerErratum(void)
314	{
315	uint32_t u = ASMCpuId_EAX(1);
316	u &= ~(RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(28) \| RT_BIT_32(29) \| RT_BIT_32(30) \| RT_BIT_32(31));
317	if ( u == UINT32_C(0x000206E6) /* 323344.pdf - BA86 - D0 - Intel Xeon Processor 7500 Series */
318	\|\| u == UINT32_C(0x00020652) /* 323056.pdf - AAX65 - C2 - Intel Xeon Processor L3406 */
319	/* 322814.pdf - AAT59 - C2 - Intel CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
320	/* 322911.pdf - AAU65 - C2 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
321	\|\| u == UINT32_C(0x00020655) /* 322911.pdf - AAU65 - K0 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
322	\|\| u == UINT32_C(0x000106E5) /* 322373.pdf - AAO95 - B1 - Intel Xeon Processor 3400 Series */
323	/* 322166.pdf - AAN92 - B1 - Intel CoreTM i7-800 and i5-700 Desktop Processor Series */
324	/* 320767.pdf - AAP86 - B1 - Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
325	\|\| u == UINT32_C(0x000106A0) /* 321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification */
326	\|\| u == UINT32_C(0x000106A1) /* 321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification */
327	\|\| u == UINT32_C(0x000106A4) /* 320836.pdf - AAJ124 - C0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
328	\|\| u == UINT32_C(0x000106A5) /* 321333.pdf - AAM126 - D0 - Intel Xeon Processor 3500 Series Specification */
329	/* 321324.pdf - AAK139 - D0 - Intel Xeon Processor 5500 Series Specification */
330	/* 320836.pdf - AAJ124 - D0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
331	)
332	return true;
333	return false;
334	}
335
336
337	/**
338	* Intel specific initialization code.
339	*
340	* @returns VBox status code (will only fail if out of memory).
341	*/
342	static int hmR0InitIntel(void)
343	{
344	/* Read this MSR now as it may be useful for error reporting when initializing VT-x fails. */
345	g_HmR0.hwvirt.Msrs.u.vmx.u64FeatCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
346
347	/*
348	* First try use native kernel API for controlling VT-x.
349	* (This is only supported by some Mac OS X kernels atm.)
350	*/
351	int rc = g_HmR0.rcInit = SUPR0EnableVTx(true /* fEnable */);
352	g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
353	if (g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx)
354	{
355	AssertLogRelMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
356	if (RT_SUCCESS(rc))
357	{
358	g_HmR0.hwvirt.u.vmx.fSupported = true;
359	rc = SUPR0EnableVTx(false /* fEnable */);
360	AssertLogRelRC(rc);
361	}
362	}
363	else
364	{
365	HMR0FIRSTRC FirstRc;
366	hmR0FirstRcInit(&FirstRc);
367	g_HmR0.rcInit = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
368	if (RT_SUCCESS(g_HmR0.rcInit))
369	g_HmR0.rcInit = hmR0FirstRcGetStatus(&FirstRc);
370	}
371
372	if (RT_SUCCESS(g_HmR0.rcInit))
373	{
374	/* Read CR4 and EFER for logging/diagnostic purposes. */
375	g_HmR0.hwvirt.u.vmx.u64HostCr4 = ASMGetCR4();
376	g_HmR0.hwvirt.u.vmx.u64HostMsrEfer = ASMRdMsr(MSR_K6_EFER);
377
378	/* Get VMX MSRs for determining VMX features we can ultimately use. */
379	SUPR0GetHwvirtMsrs(&g_HmR0.hwvirt.Msrs, SUPVTCAPS_VT_X, false /* fForce */);
380
381	/*
382	* Nested KVM workaround: Intel SDM section 34.15.5 describes that
383	* MSR_IA32_SMM_MONITOR_CTL depends on bit 49 of MSR_IA32_VMX_BASIC while
384	* table 35-2 says that this MSR is available if either VMX or SMX is supported.
385	*/
386	uint64_t const uVmxBasicMsr = g_HmR0.hwvirt.Msrs.u.vmx.u64Basic;
387	if (RT_BF_GET(uVmxBasicMsr, VMX_BF_BASIC_DUAL_MON))
388	g_HmR0.hwvirt.u.vmx.u64HostSmmMonitorCtl = ASMRdMsr(MSR_IA32_SMM_MONITOR_CTL);
389
390	/* Initialize VPID - 16 bits ASID. */
391	g_HmR0.hwvirt.uMaxAsid = 0x10000; /* exclusive */
392
393	/*
394	* If the host OS has not enabled VT-x for us, try enter VMX root mode
395	* to really verify if VT-x is usable.
396	*/
397	if (!g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx)
398	{
399	/* Allocate a temporary VMXON region. */
400	RTR0MEMOBJ hScatchMemObj;
401	rc = RTR0MemObjAllocCont(&hScatchMemObj, PAGE_SIZE, false /* fExecutable */);
402	if (RT_FAILURE(rc))
403	{
404	LogRel(("hmR0InitIntel: RTR0MemObjAllocCont(,PAGE_SIZE,false) -> %Rrc\n", rc));
405	return rc;
406	}
407	void *pvScatchPage = RTR0MemObjAddress(hScatchMemObj);
408	RTHCPHYS HCPhysScratchPage = RTR0MemObjGetPagePhysAddr(hScatchMemObj, 0);
409	ASMMemZeroPage(pvScatchPage);
410
411	/* Set revision dword at the beginning of the VMXON structure. */
412	(uint32_t )pvScatchPage = RT_BF_GET(uVmxBasicMsr, VMX_BF_BASIC_VMCS_ID);
413
414	/* Make sure we don't get rescheduled to another CPU during this probe. */
415	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
416
417	/* Check CR4.VMXE. */
418	g_HmR0.hwvirt.u.vmx.u64HostCr4 = ASMGetCR4();
419	if (!(g_HmR0.hwvirt.u.vmx.u64HostCr4 & X86_CR4_VMXE))
420	{
421	/* In theory this bit could be cleared behind our back. Which would cause #UD
422	faults when we try to execute the VMX instructions... */
423	ASMSetCR4(g_HmR0.hwvirt.u.vmx.u64HostCr4 \| X86_CR4_VMXE);
424	}
425
426	/*
427	* The only way of checking if we're in VMX root mode or not is to try and enter it.
428	* There is no instruction or control bit that tells us if we're in VMX root mode.
429	* Therefore, try and enter VMX root mode here.
430	*/
431	rc = VMXEnable(HCPhysScratchPage);
432	if (RT_SUCCESS(rc))
433	{
434	g_HmR0.hwvirt.u.vmx.fSupported = true;
435	VMXDisable();
436	}
437	else
438	{
439	/*
440	* KVM leaves the CPU in VMX root mode. Not only is this not allowed,
441	* it will crash the host when we enter raw mode, because:
442	*
443	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
444	* this bit), and
445	* (b) turning off paging causes a #GP (unavoidable when switching
446	* from long to 32 bits mode or 32 bits to PAE).
447	*
448	* They should fix their code, but until they do we simply refuse to run.
449	*/
450	g_HmR0.rcInit = VERR_VMX_IN_VMX_ROOT_MODE;
451	Assert(g_HmR0.hwvirt.u.vmx.fSupported == false);
452	}
453
454	/*
455	* Restore CR4 again; don't leave the X86_CR4_VMXE flag set if it was not
456	* set before (some software could incorrectly think it is in VMX mode).
457	*/
458	ASMSetCR4(g_HmR0.hwvirt.u.vmx.u64HostCr4);
459	ASMSetFlags(fEFlags);
460
461	RTR0MemObjFree(hScatchMemObj, false);
462	}
463
464	if (g_HmR0.hwvirt.u.vmx.fSupported)
465	{
466	rc = VMXR0GlobalInit();
467	if (RT_FAILURE(rc))
468	g_HmR0.rcInit = rc;
469
470	/*
471	* Install the VT-x methods.
472	*/
473	g_HmR0.pfnEnterSession = VMXR0Enter;
474	g_HmR0.pfnThreadCtxCallback = VMXR0ThreadCtxCallback;
475	g_HmR0.pfnCallRing3Callback = VMXR0CallRing3Callback;
476	g_HmR0.pfnExportHostState = VMXR0ExportHostState;
477	g_HmR0.pfnRunGuestCode = VMXR0RunGuestCode;
478	g_HmR0.pfnEnableCpu = VMXR0EnableCpu;
479	g_HmR0.pfnDisableCpu = VMXR0DisableCpu;
480	g_HmR0.pfnInitVM = VMXR0InitVM;
481	g_HmR0.pfnTermVM = VMXR0TermVM;
482	g_HmR0.pfnSetupVM = VMXR0SetupVM;
483
484	/*
485	* Check for the VMX-Preemption Timer and adjust for the "VMX-Preemption
486	* Timer Does Not Count Down at the Rate Specified" CPU erratum.
487	*/
488	VMXCTLSMSR PinCtls;
489	PinCtls.u = g_HmR0.hwvirt.Msrs.u.vmx.u64PinCtls;
490	if (PinCtls.n.allowed1 & VMX_PIN_CTLS_PREEMPT_TIMER)
491	{
492	uint64_t const uVmxMiscMsr = g_HmR0.hwvirt.Msrs.u.vmx.u64Misc;
493	g_HmR0.hwvirt.u.vmx.fUsePreemptTimer = true;
494	g_HmR0.hwvirt.u.vmx.cPreemptTimerShift = RT_BF_GET(uVmxMiscMsr, VMX_BF_MISC_PREEMPT_TIMER_TSC);
495	if (hmR0InitIntelIsSubjectToVmxPreemptTimerErratum())
496	g_HmR0.hwvirt.u.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
497	}
498	}
499	}
500	#ifdef LOG_ENABLED
501	else
502	SUPR0Printf("hmR0InitIntelCpu failed with rc=%Rrc\n", g_HmR0.rcInit);
503	#endif
504	return VINF_SUCCESS;
505	}
506
507
508	/**
509	* AMD-specific initialization code.
510	*
511	* @returns VBox status code (will only fail if out of memory).
512	*/
513	static int hmR0InitAmd(void)
514	{
515	/* Call the global AMD-V initialization routine (should only fail in out-of-memory situations). */
516	int rc = SVMR0GlobalInit();
517	if (RT_FAILURE(rc))
518	{
519	g_HmR0.rcInit = rc;
520	return rc;
521	}
522
523	/*
524	* Install the AMD-V methods.
525	*/
526	g_HmR0.pfnEnterSession = SVMR0Enter;
527	g_HmR0.pfnThreadCtxCallback = SVMR0ThreadCtxCallback;
528	g_HmR0.pfnCallRing3Callback = SVMR0CallRing3Callback;
529	g_HmR0.pfnExportHostState = SVMR0ExportHostState;
530	g_HmR0.pfnRunGuestCode = SVMR0RunGuestCode;
531	g_HmR0.pfnEnableCpu = SVMR0EnableCpu;
532	g_HmR0.pfnDisableCpu = SVMR0DisableCpu;
533	g_HmR0.pfnInitVM = SVMR0InitVM;
534	g_HmR0.pfnTermVM = SVMR0TermVM;
535	g_HmR0.pfnSetupVM = SVMR0SetupVM;
536
537	/* Query AMD features. */
538	uint32_t u32Dummy;
539	ASMCpuId(0x8000000a, &g_HmR0.hwvirt.u.svm.u32Rev, &g_HmR0.hwvirt.uMaxAsid, &u32Dummy, &g_HmR0.hwvirt.u.svm.u32Features);
540
541	/*
542	* We need to check if AMD-V has been properly initialized on all CPUs.
543	* Some BIOSes might do a poor job.
544	*/
545	HMR0FIRSTRC FirstRc;
546	hmR0FirstRcInit(&FirstRc);
547	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
548	AssertRC(rc);
549	if (RT_SUCCESS(rc))
550	rc = hmR0FirstRcGetStatus(&FirstRc);
551	#ifndef DEBUG_bird
552	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE,
553	("hmR0InitAmdCpu failed for cpu %d with rc=%Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
554	#endif
555	if (RT_SUCCESS(rc))
556	{
557	SUPR0GetHwvirtMsrs(&g_HmR0.hwvirt.Msrs, SUPVTCAPS_AMD_V, false /* fForce */);
558	g_HmR0.hwvirt.u.svm.fSupported = true;
559	}
560	else
561	{
562	g_HmR0.rcInit = rc;
563	if (rc == VERR_SVM_DISABLED \|\| rc == VERR_SVM_IN_USE)
564	rc = VINF_SUCCESS; /* Don't fail if AMD-V is disabled or in use. */
565	}
566	return rc;
567	}
568
569
570	/**
571	* Does global Ring-0 HM initialization (at module init).
572	*
573	* @returns VBox status code.
574	*/
575	VMMR0_INT_DECL(int) HMR0Init(void)
576	{
577	/*
578	* Initialize the globals.
579	*/
580	g_HmR0.fEnabled = false;
581	static RTONCE s_OnceInit = RTONCE_INITIALIZER;
582	g_HmR0.EnableAllCpusOnce = s_OnceInit;
583	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
584	{
585	g_HmR0.aCpuInfo[i].idCpu = NIL_RTCPUID;
586	g_HmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
587	g_HmR0.aCpuInfo[i].HCPhysMemObj = NIL_RTHCPHYS;
588	g_HmR0.aCpuInfo[i].pvMemObj = NULL;
589	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
590	g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm = NIL_RTR0MEMOBJ;
591	g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm = NIL_RTHCPHYS;
592	g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm = NULL;
593	#endif
594	}
595
596	/* Fill in all callbacks with placeholders. */
597	g_HmR0.pfnEnterSession = hmR0DummyEnter;
598	g_HmR0.pfnThreadCtxCallback = hmR0DummyThreadCtxCallback;
599	g_HmR0.pfnCallRing3Callback = hmR0DummyCallRing3Callback;
600	g_HmR0.pfnExportHostState = hmR0DummyExportHostState;
601	g_HmR0.pfnRunGuestCode = hmR0DummyRunGuestCode;
602	g_HmR0.pfnEnableCpu = hmR0DummyEnableCpu;
603	g_HmR0.pfnDisableCpu = hmR0DummyDisableCpu;
604	g_HmR0.pfnInitVM = hmR0DummyInitVM;
605	g_HmR0.pfnTermVM = hmR0DummyTermVM;
606	g_HmR0.pfnSetupVM = hmR0DummySetupVM;
607
608	/* Default is global VT-x/AMD-V init. */
609	g_HmR0.fGlobalInit = true;
610
611	/*
612	* Make sure aCpuInfo is big enough for all the CPUs on this system.
613	*/
614	if (RTMpGetArraySize() > RT_ELEMENTS(g_HmR0.aCpuInfo))
615	{
616	LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HmR0.aCpuInfo)));
617	return VERR_TOO_MANY_CPUS;
618	}
619
620	/*
621	* Check for VT-x or AMD-V support.
622	* Return failure only in out-of-memory situations.
623	*/
624	uint32_t fCaps = 0;
625	int rc = SUPR0GetVTSupport(&fCaps);
626	if (RT_SUCCESS(rc))
627	{
628	if (fCaps & SUPVTCAPS_VT_X)
629	{
630	rc = hmR0InitIntel();
631	if (RT_FAILURE(rc))
632	return rc;
633	}
634	else
635	{
636	Assert(fCaps & SUPVTCAPS_AMD_V);
637	rc = hmR0InitAmd();
638	if (RT_FAILURE(rc))
639	return rc;
640	}
641	}
642	else
643	g_HmR0.rcInit = VERR_UNSUPPORTED_CPU;
644
645	/*
646	* Register notification callbacks that we can use to disable/enable CPUs
647	* when brought offline/online or suspending/resuming.
648	*/
649	if (!g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx)
650	{
651	rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
652	AssertRC(rc);
653
654	rc = RTPowerNotificationRegister(hmR0PowerCallback, NULL);
655	AssertRC(rc);
656	}
657
658	/* We return success here because module init shall not fail if HM fails to initialize. */
659	return VINF_SUCCESS;
660	}
661
662
663	/**
664	* Does global Ring-0 HM termination (at module termination).
665	*
666	* @returns VBox status code.
667	*/
668	VMMR0_INT_DECL(int) HMR0Term(void)
669	{
670	int rc;
671	if ( g_HmR0.hwvirt.u.vmx.fSupported
672	&& g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx)
673	{
674	/*
675	* Simple if the host OS manages VT-x.
676	*/
677	Assert(g_HmR0.fGlobalInit);
678
679	if (g_HmR0.hwvirt.u.vmx.fCalledSUPR0EnableVTx)
680	{
681	rc = SUPR0EnableVTx(false /* fEnable */);
682	g_HmR0.hwvirt.u.vmx.fCalledSUPR0EnableVTx = false;
683	}
684	else
685	rc = VINF_SUCCESS;
686
687	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HmR0.aCpuInfo); iCpu++)
688	{
689	g_HmR0.aCpuInfo[iCpu].fConfigured = false;
690	Assert(g_HmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
691	}
692	}
693	else
694	{
695	Assert(!g_HmR0.hwvirt.u.vmx.fSupported \|\| !g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx);
696
697	/* Doesn't really matter if this fails. */
698	rc = RTMpNotificationDeregister(hmR0MpEventCallback, NULL); AssertRC(rc);
699	rc = RTPowerNotificationDeregister(hmR0PowerCallback, NULL); AssertRC(rc);
700
701	/*
702	* Disable VT-x/AMD-V on all CPUs if we enabled it before.
703	*/
704	if (g_HmR0.fGlobalInit)
705	{
706	HMR0FIRSTRC FirstRc;
707	hmR0FirstRcInit(&FirstRc);
708	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
709	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
710	if (RT_SUCCESS(rc))
711	rc = hmR0FirstRcGetStatus(&FirstRc);
712	}
713
714	/*
715	* Free the per-cpu pages used for VT-x and AMD-V.
716	*/
717	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
718	{
719	if (g_HmR0.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
720	{
721	RTR0MemObjFree(g_HmR0.aCpuInfo[i].hMemObj, false);
722	g_HmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
723	g_HmR0.aCpuInfo[i].HCPhysMemObj = NIL_RTHCPHYS;
724	g_HmR0.aCpuInfo[i].pvMemObj = NULL;
725	}
726	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
727	if (g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm != NIL_RTR0MEMOBJ)
728	{
729	RTR0MemObjFree(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm, false);
730	g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm = NIL_RTR0MEMOBJ;
731	g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm = NIL_RTHCPHYS;
732	g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm = NULL;
733	}
734	#endif
735	}
736	}
737
738	/** @todo This needs cleaning up. There's no matching
739	* hmR0TermIntel()/hmR0TermAmd() and all the VT-x/AMD-V specific bits
740	* should move into their respective modules. */
741	/* Finally, call global VT-x/AMD-V termination. */
742	if (g_HmR0.hwvirt.u.vmx.fSupported)
743	VMXR0GlobalTerm();
744	else if (g_HmR0.hwvirt.u.svm.fSupported)
745	SVMR0GlobalTerm();
746
747	return rc;
748	}
749
750
751	/**
752	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize VT-x
753	* on a CPU.
754	*
755	* @param idCpu The identifier for the CPU the function is called on.
756	* @param pvUser1 Pointer to the first RC structure.
757	* @param pvUser2 Ignored.
758	*/
759	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
760	{
761	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
762	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
763	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
764	NOREF(idCpu); NOREF(pvUser2);
765
766	int rc = SUPR0GetVmxUsability(NULL /* pfIsSmxModeAmbiguous */);
767	hmR0FirstRcSetStatus(pFirstRc, rc);
768	}
769
770
771	/**
772	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize AMD-V
773	* on a CPU.
774	*
775	* @param idCpu The identifier for the CPU the function is called on.
776	* @param pvUser1 Pointer to the first RC structure.
777	* @param pvUser2 Ignored.
778	*/
779	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
780	{
781	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
782	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
783	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
784	NOREF(idCpu); NOREF(pvUser2);
785
786	int rc = SUPR0GetSvmUsability(true /* fInitSvm */);
787	hmR0FirstRcSetStatus(pFirstRc, rc);
788	}
789
790
791	/**
792	* Enable VT-x or AMD-V on the current CPU
793	*
794	* @returns VBox status code.
795	* @param pVM The cross context VM structure. Can be NULL.
796	* @param idCpu The identifier for the CPU the function is called on.
797	*
798	* @remarks Maybe called with interrupts disabled!
799	*/
800	static int hmR0EnableCpu(PVMCC pVM, RTCPUID idCpu)
801	{
802	PHMPHYSCPU pHostCpu = &g_HmR0.aCpuInfo[idCpu];
803
804	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
805	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
806	Assert(!pHostCpu->fConfigured);
807	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
808
809	pHostCpu->idCpu = idCpu;
810	/* Do NOT reset cTlbFlushes here, see @bugref{6255}. */
811
812	int rc;
813	if ( g_HmR0.hwvirt.u.vmx.fSupported
814	&& g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx)
815	rc = g_HmR0.pfnEnableCpu(pHostCpu, pVM, NULL /* pvCpuPage */, NIL_RTHCPHYS, true, &g_HmR0.hwvirt.Msrs);
816	else
817	{
818	AssertLogRelMsgReturn(pHostCpu->hMemObj != NIL_RTR0MEMOBJ, ("hmR0EnableCpu failed idCpu=%u.\n", idCpu), VERR_HM_IPE_1);
819	rc = g_HmR0.pfnEnableCpu(pHostCpu, pVM, pHostCpu->pvMemObj, pHostCpu->HCPhysMemObj, false, &g_HmR0.hwvirt.Msrs);
820	}
821	if (RT_SUCCESS(rc))
822	pHostCpu->fConfigured = true;
823	return rc;
824	}
825
826
827	/**
828	* Worker function passed to RTMpOnAll() that is to be called on all CPUs.
829	*
830	* @param idCpu The identifier for the CPU the function is called on.
831	* @param pvUser1 Opaque pointer to the VM (can be NULL!).
832	* @param pvUser2 The 2nd user argument.
833	*/
834	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
835	{
836	PVMCC pVM = (PVMCC)pvUser1; /* can be NULL! */
837	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
838	AssertReturnVoid(g_HmR0.fGlobalInit);
839	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
840	hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
841	}
842
843
844	/**
845	* RTOnce callback employed by HMR0EnableAllCpus.
846	*
847	* @returns VBox status code.
848	* @param pvUser Pointer to the VM.
849	*/
850	static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void *pvUser)
851	{
852	PVMCC pVM = (PVMCC)pvUser;
853
854	/*
855	* Indicate that we've initialized.
856	*
857	* Note! There is a potential race between this function and the suspend
858	* notification. Kind of unlikely though, so ignored for now.
859	*/
860	AssertReturn(!g_HmR0.fEnabled, VERR_HM_ALREADY_ENABLED_IPE);
861	ASMAtomicWriteBool(&g_HmR0.fEnabled, true);
862
863	/*
864	* The global init variable is set by the first VM.
865	*/
866	g_HmR0.fGlobalInit = pVM->hm.s.fGlobalInit;
867
868	#ifdef VBOX_STRICT
869	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
870	{
871	Assert(g_HmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
872	Assert(g_HmR0.aCpuInfo[i].HCPhysMemObj == NIL_RTHCPHYS);
873	Assert(g_HmR0.aCpuInfo[i].pvMemObj == NULL);
874	Assert(!g_HmR0.aCpuInfo[i].fConfigured);
875	Assert(!g_HmR0.aCpuInfo[i].cTlbFlushes);
876	Assert(!g_HmR0.aCpuInfo[i].uCurrentAsid);
877	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
878	Assert(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm == NIL_RTR0MEMOBJ);
879	Assert(g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm == NIL_RTHCPHYS);
880	Assert(g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm == NULL);
881	# endif
882	}
883	#endif
884
885	int rc;
886	if ( g_HmR0.hwvirt.u.vmx.fSupported
887	&& g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx)
888	{
889	/*
890	* Global VT-x initialization API (only darwin for now).
891	*/
892	rc = SUPR0EnableVTx(true /* fEnable */);
893	if (RT_SUCCESS(rc))
894	{
895	g_HmR0.hwvirt.u.vmx.fCalledSUPR0EnableVTx = true;
896	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
897	g_HmR0.fGlobalInit = pVM->hm.s.fGlobalInit = true;
898	}
899	else
900	AssertMsgFailed(("hmR0EnableAllCpuOnce/SUPR0EnableVTx: rc=%Rrc\n", rc));
901	}
902	else
903	{
904	/*
905	* We're doing the job ourselves.
906	*/
907	/* Allocate one page per cpu for the global VT-x and AMD-V pages */
908	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
909	{
910	Assert(g_HmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
911	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
912	Assert(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm == NIL_RTR0MEMOBJ);
913	#endif
914	if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
915	{
916	/** @todo NUMA */
917	rc = RTR0MemObjAllocCont(&g_HmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, false /* executable R0 mapping */);
918	AssertLogRelRCReturn(rc, rc);
919
920	g_HmR0.aCpuInfo[i].HCPhysMemObj = RTR0MemObjGetPagePhysAddr(g_HmR0.aCpuInfo[i].hMemObj, 0);
921	Assert(g_HmR0.aCpuInfo[i].HCPhysMemObj != NIL_RTHCPHYS);
922	Assert(!(g_HmR0.aCpuInfo[i].HCPhysMemObj & PAGE_OFFSET_MASK));
923
924	g_HmR0.aCpuInfo[i].pvMemObj = RTR0MemObjAddress(g_HmR0.aCpuInfo[i].hMemObj);
925	AssertPtr(g_HmR0.aCpuInfo[i].pvMemObj);
926	ASMMemZeroPage(g_HmR0.aCpuInfo[i].pvMemObj);
927
928	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
929	rc = RTR0MemObjAllocCont(&g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT,
930	false /* executable R0 mapping */);
931	AssertLogRelRCReturn(rc, rc);
932
933	g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm = RTR0MemObjGetPagePhysAddr(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm, 0);
934	Assert(g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm != NIL_RTHCPHYS);
935	Assert(!(g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm & PAGE_OFFSET_MASK));
936
937	g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm = RTR0MemObjAddress(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm);
938	AssertPtr(g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm);
939	ASMMemFill32(g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
940	#endif
941	}
942	}
943
944	rc = VINF_SUCCESS;
945	}
946
947	if ( RT_SUCCESS(rc)
948	&& g_HmR0.fGlobalInit)
949	{
950	/* First time, so initialize each cpu/core. */
951	HMR0FIRSTRC FirstRc;
952	hmR0FirstRcInit(&FirstRc);
953	rc = RTMpOnAll(hmR0EnableCpuCallback, (void *)pVM, &FirstRc);
954	if (RT_SUCCESS(rc))
955	rc = hmR0FirstRcGetStatus(&FirstRc);
956	}
957
958	return rc;
959	}
960
961
962	/**
963	* Sets up HM on all cpus.
964	*
965	* @returns VBox status code.
966	* @param pVM The cross context VM structure.
967	*/
968	VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVMCC pVM)
969	{
970	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
971	if (ASMAtomicReadBool(&g_HmR0.fSuspended))
972	return VERR_HM_SUSPEND_PENDING;
973
974	return RTOnce(&g_HmR0.EnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM);
975	}
976
977
978	/**
979	* Disable VT-x or AMD-V on the current CPU.
980	*
981	* @returns VBox status code.
982	* @param idCpu The identifier for the CPU this function is called on.
983	*
984	* @remarks Must be called with preemption disabled.
985	*/
986	static int hmR0DisableCpu(RTCPUID idCpu)
987	{
988	PHMPHYSCPU pHostCpu = &g_HmR0.aCpuInfo[idCpu];
989
990	Assert(!g_HmR0.hwvirt.u.vmx.fSupported \|\| !g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx);
991	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
992	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
993	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
994	Assert(!pHostCpu->fConfigured \|\| pHostCpu->hMemObj != NIL_RTR0MEMOBJ);
995	AssertRelease(idCpu == RTMpCpuId());
996
997	if (pHostCpu->hMemObj == NIL_RTR0MEMOBJ)
998	return pHostCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
999	AssertPtr(pHostCpu->pvMemObj);
1000	Assert(pHostCpu->HCPhysMemObj != NIL_RTHCPHYS);
1001
1002	int rc;
1003	if (pHostCpu->fConfigured)
1004	{
1005	rc = g_HmR0.pfnDisableCpu(pHostCpu->pvMemObj, pHostCpu->HCPhysMemObj);
1006	AssertRCReturn(rc, rc);
1007
1008	pHostCpu->fConfigured = false;
1009	pHostCpu->idCpu = NIL_RTCPUID;
1010	}
1011	else
1012	rc = VINF_SUCCESS; /* nothing to do */
1013	return rc;
1014	}
1015
1016
1017	/**
1018	* Worker function passed to RTMpOnAll() that is to be called on the target
1019	* CPUs.
1020	*
1021	* @param idCpu The identifier for the CPU the function is called on.
1022	* @param pvUser1 The 1st user argument.
1023	* @param pvUser2 Opaque pointer to the FirstRc.
1024	*/
1025	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1026	{
1027	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; NOREF(pvUser1);
1028	AssertReturnVoid(g_HmR0.fGlobalInit);
1029	hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
1030	}
1031
1032
1033	/**
1034	* Worker function passed to RTMpOnSpecific() that is to be called on the target
1035	* CPU.
1036	*
1037	* @param idCpu The identifier for the CPU the function is called on.
1038	* @param pvUser1 Null, not used.
1039	* @param pvUser2 Null, not used.
1040	*/
1041	static DECLCALLBACK(void) hmR0DisableCpuOnSpecificCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1042	{
1043	NOREF(pvUser1);
1044	NOREF(pvUser2);
1045	hmR0DisableCpu(idCpu);
1046	}
1047
1048
1049	/**
1050	* Callback function invoked when a cpu goes online or offline.
1051	*
1052	* @param enmEvent The Mp event.
1053	* @param idCpu The identifier for the CPU the function is called on.
1054	* @param pvData Opaque data (PVMCC pointer).
1055	*/
1056	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
1057	{
1058	NOREF(pvData);
1059	Assert(!g_HmR0.hwvirt.u.vmx.fSupported \|\| !g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx);
1060
1061	/*
1062	* We only care about uninitializing a CPU that is going offline. When a
1063	* CPU comes online, the initialization is done lazily in HMR0Enter().
1064	*/
1065	switch (enmEvent)
1066	{
1067	case RTMPEVENT_OFFLINE:
1068	{
1069	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1070	RTThreadPreemptDisable(&PreemptState);
1071	if (idCpu == RTMpCpuId())
1072	{
1073	int rc = hmR0DisableCpu(idCpu);
1074	AssertRC(rc);
1075	RTThreadPreemptRestore(&PreemptState);
1076	}
1077	else
1078	{
1079	RTThreadPreemptRestore(&PreemptState);
1080	RTMpOnSpecific(idCpu, hmR0DisableCpuOnSpecificCallback, NULL /* pvUser1 /, NULL / pvUser2 */);
1081	}
1082	break;
1083	}
1084
1085	default:
1086	break;
1087	}
1088	}
1089
1090
1091	/**
1092	* Called whenever a system power state change occurs.
1093	*
1094	* @param enmEvent The Power event.
1095	* @param pvUser User argument.
1096	*/
1097	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
1098	{
1099	NOREF(pvUser);
1100	Assert(!g_HmR0.hwvirt.u.vmx.fSupported \|\| !g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx);
1101
1102	#ifdef LOG_ENABLED
1103	if (enmEvent == RTPOWEREVENT_SUSPEND)
1104	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
1105	else
1106	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
1107	#endif
1108
1109	if (enmEvent == RTPOWEREVENT_SUSPEND)
1110	ASMAtomicWriteBool(&g_HmR0.fSuspended, true);
1111
1112	if (g_HmR0.fEnabled)
1113	{
1114	int rc;
1115	HMR0FIRSTRC FirstRc;
1116	hmR0FirstRcInit(&FirstRc);
1117
1118	if (enmEvent == RTPOWEREVENT_SUSPEND)
1119	{
1120	if (g_HmR0.fGlobalInit)
1121	{
1122	/* Turn off VT-x or AMD-V on all CPUs. */
1123	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
1124	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1125	}
1126	/* else nothing to do here for the local init case */
1127	}
1128	else
1129	{
1130	/* Reinit the CPUs from scratch as the suspend state might have
1131	messed with the MSRs. (lousy BIOSes as usual) */
1132	if (g_HmR0.hwvirt.u.vmx.fSupported)
1133	rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
1134	else
1135	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
1136	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1137	if (RT_SUCCESS(rc))
1138	rc = hmR0FirstRcGetStatus(&FirstRc);
1139	#ifdef LOG_ENABLED
1140	if (RT_FAILURE(rc))
1141	SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
1142	#endif
1143	if (g_HmR0.fGlobalInit)
1144	{
1145	/* Turn VT-x or AMD-V back on on all CPUs. */
1146	rc = RTMpOnAll(hmR0EnableCpuCallback, NULL /* pVM /, &FirstRc / output ignored */);
1147	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1148	}
1149	/* else nothing to do here for the local init case */
1150	}
1151	}
1152
1153	if (enmEvent == RTPOWEREVENT_RESUME)
1154	ASMAtomicWriteBool(&g_HmR0.fSuspended, false);
1155	}
1156
1157
1158	/**
1159	* Does ring-0 per-VM HM initialization.
1160	*
1161	* This will call the CPU specific init. routine which may initialize and allocate
1162	* resources for virtual CPUs.
1163	*
1164	* @returns VBox status code.
1165	* @param pVM The cross context VM structure.
1166	*
1167	* @remarks This is called after HMR3Init(), see vmR3CreateU() and
1168	* vmR3InitRing3().
1169	*/
1170	VMMR0_INT_DECL(int) HMR0InitVM(PVMCC pVM)
1171	{
1172	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1173
1174	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1175	if (ASMAtomicReadBool(&g_HmR0.fSuspended))
1176	return VERR_HM_SUSPEND_PENDING;
1177
1178	/*
1179	* Copy globals to the VM structure.
1180	*/
1181	Assert(!(pVM->hm.s.vmx.fSupported && pVM->hm.s.svm.fSupported));
1182	if (pVM->hm.s.vmx.fSupported)
1183	{
1184	pVM->hm.s.vmx.fUsePreemptTimer &= g_HmR0.hwvirt.u.vmx.fUsePreemptTimer; /* Can be overridden by CFGM in HMR3Init(). */
1185	pVM->hm.s.vmx.cPreemptTimerShift = g_HmR0.hwvirt.u.vmx.cPreemptTimerShift;
1186	pVM->hm.s.vmx.u64HostCr4 = g_HmR0.hwvirt.u.vmx.u64HostCr4;
1187	pVM->hm.s.vmx.u64HostMsrEfer = g_HmR0.hwvirt.u.vmx.u64HostMsrEfer;
1188	pVM->hm.s.vmx.u64HostSmmMonitorCtl = g_HmR0.hwvirt.u.vmx.u64HostSmmMonitorCtl;
1189	HMGetVmxMsrsFromHwvirtMsrs(&g_HmR0.hwvirt.Msrs, &pVM->hm.s.vmx.Msrs);
1190	/* If you need to tweak host MSRs for testing VMX R0 code, do it here. */
1191
1192	/* Enable VPID if supported and configured. */
1193	if (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VPID)
1194	pVM->hm.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid; /* Can be overridden by CFGM in HMR3Init(). */
1195
1196	/* Use VMCS shadowing if supported. */
1197	Assert(!pVM->hm.s.vmx.fUseVmcsShadowing);
1198	if ( pVM->cpum.ro.GuestFeatures.fVmx
1199	&& (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VMCS_SHADOWING))
1200	pVM->hm.s.vmx.fUseVmcsShadowing = true;
1201
1202	/* Use the VMCS controls for swapping the EFER MSR if supported. */
1203	Assert(!pVM->hm.s.vmx.fSupportsVmcsEfer);
1204	if ( (pVM->hm.s.vmx.Msrs.EntryCtls.n.allowed1 & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
1205	&& (pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_LOAD_EFER_MSR)
1206	&& (pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_SAVE_EFER_MSR))
1207	pVM->hm.s.vmx.fSupportsVmcsEfer = true;
1208
1209	#if 0
1210	/* Enable APIC register virtualization and virtual-interrupt delivery if supported. */
1211	if ( (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_APIC_REG_VIRT)
1212	&& (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_INTR_DELIVERY))
1213	pVM->hm.s.fVirtApicRegs = true;
1214
1215	/* Enable posted-interrupt processing if supported. */
1216	/** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1217	* here. */
1218	if ( (pVM->hm.s.vmx.Msrs.PinCtls.n.allowed1 & VMX_PIN_CTLS_POSTED_INT)
1219	&& (pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_ACK_EXT_INT))
1220	pVM->hm.s.fPostedIntrs = true;
1221	#endif
1222	}
1223	else if (pVM->hm.s.svm.fSupported)
1224	{
1225	pVM->hm.s.svm.u32Rev = g_HmR0.hwvirt.u.svm.u32Rev;
1226	pVM->hm.s.svm.u32Features = g_HmR0.hwvirt.u.svm.u32Features;
1227	pVM->hm.s.svm.u64MsrHwcr = g_HmR0.hwvirt.Msrs.u.svm.u64MsrHwcr;
1228	/* If you need to tweak host MSRs for testing SVM R0 code, do it here. */
1229	}
1230	pVM->hm.s.rcInit = g_HmR0.rcInit;
1231	pVM->hm.s.uMaxAsid = g_HmR0.hwvirt.uMaxAsid;
1232
1233	/*
1234	* Set default maximum inner loops in ring-0 before returning to ring-3.
1235	* Can be overriden using CFGM.
1236	*/
1237	if (!pVM->hm.s.cMaxResumeLoops)
1238	{
1239	pVM->hm.s.cMaxResumeLoops = 1024;
1240	if (RTThreadPreemptIsPendingTrusty())
1241	pVM->hm.s.cMaxResumeLoops = 8192;
1242	}
1243
1244	/*
1245	* Initialize some per-VCPU fields.
1246	*/
1247	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1248	{
1249	PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
1250	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1251	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1252
1253	/* We'll aways increment this the first time (host uses ASID 0). */
1254	AssertReturn(!pVCpu->hm.s.uCurrentAsid, VERR_HM_IPE_3);
1255	}
1256
1257	/*
1258	* Get host kernel features that HM might need to know in order
1259	* to co-operate and function properly with the host OS (e.g. SMAP).
1260	*
1261	* Technically, we could do this as part of the pre-init VM procedure
1262	* but it shouldn't be done later than this point so we do it here.
1263	*/
1264	pVM->hm.s.fHostKernelFeatures = SUPR0GetKernelFeatures();
1265
1266	/*
1267	* Call the hardware specific initialization method.
1268	*/
1269	return g_HmR0.pfnInitVM(pVM);
1270	}
1271
1272
1273	/**
1274	* Does ring-0 per VM HM termination.
1275	*
1276	* @returns VBox status code.
1277	* @param pVM The cross context VM structure.
1278	*/
1279	VMMR0_INT_DECL(int) HMR0TermVM(PVMCC pVM)
1280	{
1281	Log(("HMR0TermVM: %p\n", pVM));
1282	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1283
1284	/*
1285	* Call the hardware specific method.
1286	*
1287	* Note! We might be preparing for a suspend, so the pfnTermVM() functions should probably not
1288	* mess with VT-x/AMD-V features on the CPU, currently all they do is free memory so this is safe.
1289	*/
1290	return g_HmR0.pfnTermVM(pVM);
1291	}
1292
1293
1294	/**
1295	* Sets up a VT-x or AMD-V session.
1296	*
1297	* This is mostly about setting up the hardware VM state.
1298	*
1299	* @returns VBox status code.
1300	* @param pVM The cross context VM structure.
1301	*/
1302	VMMR0_INT_DECL(int) HMR0SetupVM(PVMCC pVM)
1303	{
1304	Log(("HMR0SetupVM: %p\n", pVM));
1305	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1306
1307	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1308	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1309
1310	/* On first entry we'll sync everything. */
1311	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST);
1312
1313	/*
1314	* Call the hardware specific setup VM method. This requires the CPU to be
1315	* enabled for AMD-V/VT-x and preemption to be prevented.
1316	*/
1317	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1318	RTThreadPreemptDisable(&PreemptState);
1319	RTCPUID const idCpu = RTMpCpuId();
1320
1321	/* Enable VT-x or AMD-V if local init is required. */
1322	int rc;
1323	if (!g_HmR0.fGlobalInit)
1324	{
1325	Assert(!g_HmR0.hwvirt.u.vmx.fSupported \|\| !g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx);
1326	rc = hmR0EnableCpu(pVM, idCpu);
1327	if (RT_FAILURE(rc))
1328	{
1329	RTThreadPreemptRestore(&PreemptState);
1330	return rc;
1331	}
1332	}
1333
1334	/* Setup VT-x or AMD-V. */
1335	rc = g_HmR0.pfnSetupVM(pVM);
1336
1337	/* Disable VT-x or AMD-V if local init was done before. */
1338	if (!g_HmR0.fGlobalInit)
1339	{
1340	Assert(!g_HmR0.hwvirt.u.vmx.fSupported \|\| !g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx);
1341	int rc2 = hmR0DisableCpu(idCpu);
1342	AssertRC(rc2);
1343	}
1344
1345	RTThreadPreemptRestore(&PreemptState);
1346	return rc;
1347	}
1348
1349
1350	/**
1351	* Notification callback before performing a longjump to ring-3.
1352	*
1353	* @returns VBox status code.
1354	* @param pVCpu The cross context virtual CPU structure.
1355	* @param enmOperation The operation causing the ring-3 longjump.
1356	* @param pvUser User argument, currently unused, NULL.
1357	*/
1358	static DECLCALLBACK(int) hmR0CallRing3Callback(PVMCPUCC pVCpu, VMMCALLRING3 enmOperation, void *pvUser)
1359	{
1360	RT_NOREF(pvUser);
1361	Assert(pVCpu);
1362	Assert(g_HmR0.pfnCallRing3Callback);
1363	return g_HmR0.pfnCallRing3Callback(pVCpu, enmOperation);
1364	}
1365
1366
1367	/**
1368	* Turns on HM on the CPU if necessary and initializes the bare minimum state
1369	* required for entering HM context.
1370	*
1371	* @returns VBox status code.
1372	* @param pVCpu The cross context virtual CPU structure.
1373	*
1374	* @remarks No-long-jump zone!!!
1375	*/
1376	VMMR0_INT_DECL(int) hmR0EnterCpu(PVMCPUCC pVCpu)
1377	{
1378	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1379
1380	int rc = VINF_SUCCESS;
1381	RTCPUID const idCpu = RTMpCpuId();
1382	PHMPHYSCPU pHostCpu = &g_HmR0.aCpuInfo[idCpu];
1383	AssertPtr(pHostCpu);
1384
1385	/* Enable VT-x or AMD-V if local init is required, or enable if it's a freshly onlined CPU. */
1386	if (!pHostCpu->fConfigured)
1387	rc = hmR0EnableCpu(pVCpu->CTX_SUFF(pVM), idCpu);
1388
1389	/* Register a callback to fire prior to performing a longjmp to ring-3 so HM can disable VT-x/AMD-V if needed. */
1390	VMMRZCallRing3SetNotification(pVCpu, hmR0CallRing3Callback, NULL /* pvUser */);
1391
1392	/* Reload host-state (back from ring-3/migrated CPUs) and shared guest/host bits. */
1393	if (g_HmR0.hwvirt.u.vmx.fSupported)
1394	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE;
1395	else
1396	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE;
1397
1398	Assert(pHostCpu->idCpu == idCpu && pHostCpu->idCpu != NIL_RTCPUID);
1399	pVCpu->hm.s.idEnteredCpu = idCpu;
1400	return rc;
1401	}
1402
1403
1404	/**
1405	* Enters the VT-x or AMD-V session.
1406	*
1407	* @returns VBox status code.
1408	* @param pVCpu The cross context virtual CPU structure.
1409	*
1410	* @remarks This is called with preemption disabled.
1411	*/
1412	VMMR0_INT_DECL(int) HMR0Enter(PVMCPUCC pVCpu)
1413	{
1414	/* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
1415	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1416	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1417
1418	/* Load the bare minimum state required for entering HM. */
1419	int rc = hmR0EnterCpu(pVCpu);
1420	if (RT_SUCCESS(rc))
1421	{
1422	if (g_HmR0.hwvirt.u.vmx.fSupported)
1423	{
1424	Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE))
1425	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE));
1426	}
1427	else
1428	{
1429	Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE))
1430	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE));
1431	}
1432
1433	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1434	AssertReturn(!VMMR0ThreadCtxHookIsEnabled(pVCpu), VERR_HM_IPE_5);
1435	bool const fStartedSet = PGMR0DynMapStartOrMigrateAutoSet(pVCpu);
1436	#endif
1437
1438	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1439	rc = g_HmR0.pfnEnterSession(pVCpu);
1440	AssertMsgRCReturnStmt(rc, ("rc=%Rrc pVCpu=%p\n", rc, pVCpu), pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID, rc);
1441
1442	/* Exports the host-state as we may be resuming code after a longjmp and quite
1443	possibly now be scheduled on a different CPU. */
1444	rc = g_HmR0.pfnExportHostState(pVCpu);
1445	AssertMsgRCReturnStmt(rc, ("rc=%Rrc pVCpu=%p\n", rc, pVCpu), pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID, rc);
1446
1447	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1448	if (fStartedSet)
1449	PGMRZDynMapReleaseAutoSet(pVCpu);
1450	#endif
1451	}
1452	return rc;
1453	}
1454
1455
1456	/**
1457	* Deinitializes the bare minimum state used for HM context and if necessary
1458	* disable HM on the CPU.
1459	*
1460	* @returns VBox status code.
1461	* @param pVCpu The cross context virtual CPU structure.
1462	*
1463	* @remarks No-long-jump zone!!!
1464	*/
1465	VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPUCC pVCpu)
1466	{
1467	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1468	VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_HM_WRONG_CPU);
1469
1470	RTCPUID const idCpu = RTMpCpuId();
1471	PCHMPHYSCPU pHostCpu = &g_HmR0.aCpuInfo[idCpu];
1472
1473	if ( !g_HmR0.fGlobalInit
1474	&& pHostCpu->fConfigured)
1475	{
1476	int rc = hmR0DisableCpu(idCpu);
1477	AssertRCReturn(rc, rc);
1478	Assert(!pHostCpu->fConfigured);
1479	Assert(pHostCpu->idCpu == NIL_RTCPUID);
1480
1481	/* For obtaining a non-zero ASID/VPID on next re-entry. */
1482	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1483	}
1484
1485	/* Clear it while leaving HM context, hmPokeCpuForTlbFlush() relies on this. */
1486	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1487
1488	/* De-register the longjmp-to-ring 3 callback now that we have reliquished hardware resources. */
1489	VMMRZCallRing3RemoveNotification(pVCpu);
1490	return VINF_SUCCESS;
1491	}
1492
1493
1494	/**
1495	* Thread-context hook for HM.
1496	*
1497	* @param enmEvent The thread-context event.
1498	* @param pvUser Opaque pointer to the VMCPU.
1499	*/
1500	VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser)
1501	{
1502	PVMCPUCC pVCpu = (PVMCPUCC)pvUser;
1503	Assert(pVCpu);
1504	Assert(g_HmR0.pfnThreadCtxCallback);
1505
1506	g_HmR0.pfnThreadCtxCallback(enmEvent, pVCpu, g_HmR0.fGlobalInit);
1507	}
1508
1509
1510	/**
1511	* Runs guest code in a hardware accelerated VM.
1512	*
1513	* @returns Strict VBox status code. (VBOXSTRICTRC isn't used because it's
1514	* called from setjmp assembly.)
1515	* @param pVM The cross context VM structure.
1516	* @param pVCpu The cross context virtual CPU structure.
1517	*
1518	* @remarks Can be called with preemption enabled if thread-context hooks are
1519	* used!!!
1520	*/
1521	VMMR0_INT_DECL(int) HMR0RunGuestCode(PVMCC pVM, PVMCPUCC pVCpu)
1522	{
1523	RT_NOREF(pVM);
1524
1525	#ifdef VBOX_STRICT
1526	/* With thread-context hooks we would be running this code with preemption enabled. */
1527	if (!RTThreadPreemptIsEnabled(NIL_RTTHREAD))
1528	{
1529	PCHMPHYSCPU pHostCpu = &g_HmR0.aCpuInfo[RTMpCpuId()];
1530	Assert(!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1531	Assert(pHostCpu->fConfigured);
1532	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1533	}
1534	#endif
1535
1536	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1537	AssertReturn(!VMMR0ThreadCtxHookIsEnabled(pVCpu), VERR_HM_IPE_4);
1538	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1539	PGMRZDynMapStartAutoSet(pVCpu);
1540	#endif
1541
1542	VBOXSTRICTRC rcStrict = g_HmR0.pfnRunGuestCode(pVCpu);
1543
1544	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1545	PGMRZDynMapReleaseAutoSet(pVCpu);
1546	#endif
1547	return VBOXSTRICTRC_VAL(rcStrict);
1548	}
1549
1550
1551	/**
1552	* Notification from CPUM that it has unloaded the guest FPU/SSE/AVX state from
1553	* the host CPU and that guest access to it must be intercepted.
1554	*
1555	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1556	*/
1557	VMMR0_INT_DECL(void) HMR0NotifyCpumUnloadedGuestFpuState(PVMCPUCC pVCpu)
1558	{
1559	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR0);
1560	}
1561
1562
1563	/**
1564	* Notification from CPUM that it has modified the host CR0 (because of FPU).
1565	*
1566	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1567	*/
1568	VMMR0_INT_DECL(void) HMR0NotifyCpumModifiedHostCr0(PVMCPUCC pVCpu)
1569	{
1570	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_HOST_CONTEXT);
1571	}
1572
1573
1574	/**
1575	* Returns suspend status of the host.
1576	*
1577	* @returns Suspend pending or not.
1578	*/
1579	VMMR0_INT_DECL(bool) HMR0SuspendPending(void)
1580	{
1581	return ASMAtomicReadBool(&g_HmR0.fSuspended);
1582	}
1583
1584
1585	/**
1586	* Invalidates a guest page from the host TLB.
1587	*
1588	* @param pVCpu The cross context virtual CPU structure.
1589	* @param GCVirt Page to invalidate.
1590	*/
1591	VMMR0_INT_DECL(int) HMR0InvalidatePage(PVMCPUCC pVCpu, RTGCPTR GCVirt)
1592	{
1593	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1594	if (pVM->hm.s.vmx.fSupported)
1595	return VMXR0InvalidatePage(pVCpu, GCVirt);
1596	return SVMR0InvalidatePage(pVCpu, GCVirt);
1597	}
1598
1599
1600	/**
1601	* Returns the cpu structure for the current cpu.
1602	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1603	*
1604	* @returns The cpu structure pointer.
1605	*/
1606	VMMR0_INT_DECL(PHMPHYSCPU) hmR0GetCurrentCpu(void)
1607	{
1608	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1609	RTCPUID const idCpu = RTMpCpuId();
1610	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
1611	return &g_HmR0.aCpuInfo[idCpu];
1612	}
1613
1614
1615	/**
1616	* Interface for importing state on demand (used by IEM).
1617	*
1618	* @returns VBox status code.
1619	* @param pVCpu The cross context CPU structure.
1620	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
1621	*/
1622	VMMR0_INT_DECL(int) HMR0ImportStateOnDemand(PVMCPUCC pVCpu, uint64_t fWhat)
1623	{
1624	if (pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fSupported)
1625	return VMXR0ImportStateOnDemand(pVCpu, fWhat);
1626	return SVMR0ImportStateOnDemand(pVCpu, fWhat);
1627	}
1628
1629	#ifdef VBOX_STRICT
1630
1631	/**
1632	* Dumps a descriptor.
1633	*
1634	* @param pDesc Descriptor to dump.
1635	* @param Sel The selector.
1636	* @param pszSel The name of the selector.
1637	*/
1638	VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszSel)
1639	{
1640	/*
1641	* Make variable description string.
1642	*/
1643	static struct
1644	{
1645	unsigned cch;
1646	const char *psz;
1647	} const s_aTypes[32] =
1648	{
1649	# define STRENTRY(str) { sizeof(str) - 1, str }
1650
1651	/* system */
1652	# if HC_ARCH_BITS == 64
1653	STRENTRY("Reserved0 "), /* 0x00 */
1654	STRENTRY("Reserved1 "), /* 0x01 */
1655	STRENTRY("LDT "), /* 0x02 */
1656	STRENTRY("Reserved3 "), /* 0x03 */
1657	STRENTRY("Reserved4 "), /* 0x04 */
1658	STRENTRY("Reserved5 "), /* 0x05 */
1659	STRENTRY("Reserved6 "), /* 0x06 */
1660	STRENTRY("Reserved7 "), /* 0x07 */
1661	STRENTRY("Reserved8 "), /* 0x08 */
1662	STRENTRY("TSS64Avail "), /* 0x09 */
1663	STRENTRY("ReservedA "), /* 0x0a */
1664	STRENTRY("TSS64Busy "), /* 0x0b */
1665	STRENTRY("Call64 "), /* 0x0c */
1666	STRENTRY("ReservedD "), /* 0x0d */
1667	STRENTRY("Int64 "), /* 0x0e */
1668	STRENTRY("Trap64 "), /* 0x0f */
1669	# else
1670	STRENTRY("Reserved0 "), /* 0x00 */
1671	STRENTRY("TSS16Avail "), /* 0x01 */
1672	STRENTRY("LDT "), /* 0x02 */
1673	STRENTRY("TSS16Busy "), /* 0x03 */
1674	STRENTRY("Call16 "), /* 0x04 */
1675	STRENTRY("Task "), /* 0x05 */
1676	STRENTRY("Int16 "), /* 0x06 */
1677	STRENTRY("Trap16 "), /* 0x07 */
1678	STRENTRY("Reserved8 "), /* 0x08 */
1679	STRENTRY("TSS32Avail "), /* 0x09 */
1680	STRENTRY("ReservedA "), /* 0x0a */
1681	STRENTRY("TSS32Busy "), /* 0x0b */
1682	STRENTRY("Call32 "), /* 0x0c */
1683	STRENTRY("ReservedD "), /* 0x0d */
1684	STRENTRY("Int32 "), /* 0x0e */
1685	STRENTRY("Trap32 "), /* 0x0f */
1686	# endif
1687	/* non system */
1688	STRENTRY("DataRO "), /* 0x10 */
1689	STRENTRY("DataRO Accessed "), /* 0x11 */
1690	STRENTRY("DataRW "), /* 0x12 */
1691	STRENTRY("DataRW Accessed "), /* 0x13 */
1692	STRENTRY("DataDownRO "), /* 0x14 */
1693	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1694	STRENTRY("DataDownRW "), /* 0x16 */
1695	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1696	STRENTRY("CodeEO "), /* 0x18 */
1697	STRENTRY("CodeEO Accessed "), /* 0x19 */
1698	STRENTRY("CodeER "), /* 0x1a */
1699	STRENTRY("CodeER Accessed "), /* 0x1b */
1700	STRENTRY("CodeConfEO "), /* 0x1c */
1701	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1702	STRENTRY("CodeConfER "), /* 0x1e */
1703	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1704	# undef SYSENTRY
1705	};
1706	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1707	char szMsg[128];
1708	char *psz = &szMsg[0];
1709	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1710	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1711	psz += s_aTypes[i].cch;
1712
1713	if (pDesc->Gen.u1Present)
1714	ADD_STR(psz, "Present ");
1715	else
1716	ADD_STR(psz, "Not-Present ");
1717	# if HC_ARCH_BITS == 64
1718	if (pDesc->Gen.u1Long)
1719	ADD_STR(psz, "64-bit ");
1720	else
1721	ADD_STR(psz, "Comp ");
1722	# else
1723	if (pDesc->Gen.u1Granularity)
1724	ADD_STR(psz, "Page ");
1725	if (pDesc->Gen.u1DefBig)
1726	ADD_STR(psz, "32-bit ");
1727	else
1728	ADD_STR(psz, "16-bit ");
1729	# endif
1730	# undef ADD_STR
1731	*psz = '\0';
1732
1733	/*
1734	* Limit and Base and format the output.
1735	*/
1736	#ifdef LOG_ENABLED
1737	uint32_t u32Limit = X86DESC_LIMIT_G(pDesc);
1738
1739	# if HC_ARCH_BITS == 64
1740	uint64_t const u64Base = X86DESC64_BASE(pDesc);
1741	Log((" %s { %#04x - %#RX64 %#RX64 - base=%#RX64 limit=%#08x dpl=%d } %s\n", pszSel,
1742	Sel, pDesc->au64[0], pDesc->au64[1], u64Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1743	# else
1744	uint32_t const u32Base = X86DESC_BASE(pDesc);
1745	Log((" %s { %#04x - %#08x %#08x - base=%#08x limit=%#08x dpl=%d } %s\n", pszSel,
1746	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1747	# endif
1748	#else
1749	NOREF(Sel); NOREF(pszSel);
1750	#endif
1751	}
1752
1753
1754	/**
1755	* Formats a full register dump.
1756	*
1757	* @param pVCpu The cross context virtual CPU structure.
1758	* @param fFlags The dumping flags (HM_DUMP_REG_FLAGS_XXX).
1759	*/
1760	VMMR0_INT_DECL(void) hmR0DumpRegs(PVMCPUCC pVCpu, uint32_t fFlags)
1761	{
1762	/*
1763	* Format the flags.
1764	*/
1765	static struct
1766	{
1767	const char *pszSet;
1768	const char *pszClear;
1769	uint32_t fFlag;
1770	} const s_aFlags[] =
1771	{
1772	{ "vip", NULL, X86_EFL_VIP },
1773	{ "vif", NULL, X86_EFL_VIF },
1774	{ "ac", NULL, X86_EFL_AC },
1775	{ "vm", NULL, X86_EFL_VM },
1776	{ "rf", NULL, X86_EFL_RF },
1777	{ "nt", NULL, X86_EFL_NT },
1778	{ "ov", "nv", X86_EFL_OF },
1779	{ "dn", "up", X86_EFL_DF },
1780	{ "ei", "di", X86_EFL_IF },
1781	{ "tf", NULL, X86_EFL_TF },
1782	{ "nt", "pl", X86_EFL_SF },
1783	{ "nz", "zr", X86_EFL_ZF },
1784	{ "ac", "na", X86_EFL_AF },
1785	{ "po", "pe", X86_EFL_PF },
1786	{ "cy", "nc", X86_EFL_CF },
1787	};
1788	char szEFlags[80];
1789	char *psz = szEFlags;
1790	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1791	uint32_t uEFlags = pCtx->eflags.u32;
1792	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1793	{
1794	const char *pszAdd = s_aFlags[i].fFlag & uEFlags ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1795	if (pszAdd)
1796	{
1797	strcpy(psz, pszAdd);
1798	psz += strlen(pszAdd);
1799	*psz++ = ' ';
1800	}
1801	}
1802	psz[-1] = '\0';
1803
1804	if (fFlags & HM_DUMP_REG_FLAGS_GPRS)
1805	{
1806	/*
1807	* Format the registers.
1808	*/
1809	if (CPUMIsGuestIn64BitCode(pVCpu))
1810	{
1811	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1812	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1813	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1814	"r14=%016RX64 r15=%016RX64\n"
1815	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1816	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1817	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1818	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1819	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1820	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1821	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1822	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1823	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1824	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1825	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1826	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1827	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1828	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1829	,
1830	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1831	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1832	pCtx->r14, pCtx->r15,
1833	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
1834	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
1835	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
1836	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
1837	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
1838	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
1839	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
1840	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1841	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1842	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1843	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
1844	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1845	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1846	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1847	}
1848	else
1849	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
1850	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
1851	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
1852	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
1853	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
1854	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
1855	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
1856	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
1857	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1858	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1859	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1860	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1861	,
1862	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
1863	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
1864	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pCtx->dr[0], pCtx->dr[1],
1865	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pCtx->dr[2], pCtx->dr[3],
1866	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pCtx->dr[4], pCtx->dr[5],
1867	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pCtx->dr[6], pCtx->dr[7],
1868	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pCtx->cr0, pCtx->cr2,
1869	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pCtx->cr3, pCtx->cr4,
1870	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
1871	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1872	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1873	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1874	}
1875
1876	if (fFlags & HM_DUMP_REG_FLAGS_FPU)
1877	{
1878	PCX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
1879	Log(("FPU:\n"
1880	"FCW=%04x FSW=%04x FTW=%02x\n"
1881	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
1882	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
1883	,
1884	pFpuCtx->FCW, pFpuCtx->FSW, pFpuCtx->FTW,
1885	pFpuCtx->FOP, pFpuCtx->FPUIP, pFpuCtx->CS, pFpuCtx->Rsrvd1,
1886	pFpuCtx->FPUDP, pFpuCtx->DS, pFpuCtx->Rsrvd2,
1887	pFpuCtx->MXCSR, pFpuCtx->MXCSR_MASK));
1888	NOREF(pFpuCtx);
1889	}
1890
1891	if (fFlags & HM_DUMP_REG_FLAGS_MSRS)
1892	{
1893	Log(("MSR:\n"
1894	"EFER =%016RX64\n"
1895	"PAT =%016RX64\n"
1896	"STAR =%016RX64\n"
1897	"CSTAR =%016RX64\n"
1898	"LSTAR =%016RX64\n"
1899	"SFMASK =%016RX64\n"
1900	"KERNELGSBASE =%016RX64\n",
1901	pCtx->msrEFER,
1902	pCtx->msrPAT,
1903	pCtx->msrSTAR,
1904	pCtx->msrCSTAR,
1905	pCtx->msrLSTAR,
1906	pCtx->msrSFMASK,
1907	pCtx->msrKERNELGSBASE));
1908	}
1909	}
1910
1911	#endif /* VBOX_STRICT */
1912

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp@ 80587

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