CPUMR0.cpp@ 80274

最後變更在這個檔案從80274是 80274,由 vboxsync 提交於 6 年前
VMM: Refactoring VMMR0/* and VMMRZ/* to use VMCC & VMMCPUCC. bugref:9217
屬性 svn:eol-style 設為 `native` 屬性 svn:keywords 設為 `Id Revision`
檔案大小: 35.1 KB

行
1	/* $Id: CPUMR0.cpp 80274 2019-08-14 14:34:38Z vboxsync $ */
2	/** @file
3	* CPUM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.alldomusa.eu.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define VBOX_BUGREF_9217_PART_I
23	#define LOG_GROUP LOG_GROUP_CPUM
24	#include <VBox/vmm/cpum.h>
25	#include "CPUMInternal.h"
26	#include <VBox/vmm/vmcc.h>
27	#include <VBox/vmm/gvm.h>
28	#include <VBox/err.h>
29	#include <VBox/log.h>
30	#include <VBox/vmm/hm.h>
31	#include <iprt/assert.h>
32	#include <iprt/asm-amd64-x86.h>
33	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
34	# include <iprt/mem.h>
35	# include <iprt/memobj.h>
36	# include <VBox/apic.h>
37	#endif
38	#include <iprt/x86.h>
39
40
41	/*********************************************************************************************************************************
42	* Structures and Typedefs *
43	*********************************************************************************************************************************/
44	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
45	/**
46	* Local APIC mappings.
47	*/
48	typedef struct CPUMHOSTLAPIC
49	{
50	/** Indicates that the entry is in use and have valid data. */
51	bool fEnabled;
52	/** Whether it's operating in X2APIC mode (EXTD). */
53	bool fX2Apic;
54	/** The APIC version number. */
55	uint32_t uVersion;
56	/** The physical address of the APIC registers. */
57	RTHCPHYS PhysBase;
58	/** The memory object entering the physical address. */
59	RTR0MEMOBJ hMemObj;
60	/** The mapping object for hMemObj. */
61	RTR0MEMOBJ hMapObj;
62	/** The mapping address APIC registers.
63	* @remarks Different CPUs may use the same physical address to map their
64	* APICs, so this pointer is only valid when on the CPU owning the
65	* APIC. */
66	void *pv;
67	} CPUMHOSTLAPIC;
68	#endif
69
70
71	/*********************************************************************************************************************************
72	* Global Variables *
73	*********************************************************************************************************************************/
74	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
75	static CPUMHOSTLAPIC g_aLApics[RTCPUSET_MAX_CPUS];
76	#endif
77
78	/**
79	* CPUID bits to unify among all cores.
80	*/
81	static struct
82	{
83	uint32_t uLeaf; /*< Leaf to check. /
84	uint32_t uEcx; /*< which bits in ecx to unify between CPUs. /
85	uint32_t uEdx; /*< which bits in edx to unify between CPUs. /
86	}
87	const g_aCpuidUnifyBits[] =
88	{
89	{
90	0x00000001,
91	X86_CPUID_FEATURE_ECX_CX16 \| X86_CPUID_FEATURE_ECX_MONITOR,
92	X86_CPUID_FEATURE_EDX_CX8
93	}
94	};
95
96
97
98	/*********************************************************************************************************************************
99	* Internal Functions *
100	*********************************************************************************************************************************/
101	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
102	static int cpumR0MapLocalApics(void);
103	static void cpumR0UnmapLocalApics(void);
104	#endif
105	static int cpumR0SaveHostDebugState(PVMCPUCC pVCpu);
106
107
108	/**
109	* Does the Ring-0 CPU initialization once during module load.
110	* XXX Host-CPU hot-plugging?
111	*/
112	VMMR0_INT_DECL(int) CPUMR0ModuleInit(void)
113	{
114	int rc = VINF_SUCCESS;
115	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
116	rc = cpumR0MapLocalApics();
117	#endif
118	return rc;
119	}
120
121
122	/**
123	* Terminate the module.
124	*/
125	VMMR0_INT_DECL(int) CPUMR0ModuleTerm(void)
126	{
127	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
128	cpumR0UnmapLocalApics();
129	#endif
130	return VINF_SUCCESS;
131	}
132
133
134	/**
135	* Check the CPUID features of this particular CPU and disable relevant features
136	* for the guest which do not exist on this CPU. We have seen systems where the
137	* X86_CPUID_FEATURE_ECX_MONITOR feature flag is only set on some host CPUs, see
138	* @bugref{5436}.
139	*
140	* @note This function might be called simultaneously on more than one CPU!
141	*
142	* @param idCpu The identifier for the CPU the function is called on.
143	* @param pvUser1 Pointer to the VM structure.
144	* @param pvUser2 Ignored.
145	*/
146	static DECLCALLBACK(void) cpumR0CheckCpuid(RTCPUID idCpu, void pvUser1, void pvUser2)
147	{
148	PVMCC pVM = (PVMCC)pvUser1;
149
150	NOREF(idCpu); NOREF(pvUser2);
151	for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
152	{
153	/* Note! Cannot use cpumCpuIdGetLeaf from here because we're not
154	necessarily in the VM process context. So, we using the
155	legacy arrays as temporary storage. */
156
157	uint32_t uLeaf = g_aCpuidUnifyBits[i].uLeaf;
158	PCPUMCPUID pLegacyLeaf;
159	if (uLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
160	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmStd[uLeaf];
161	else if (uLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
162	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmExt[uLeaf - UINT32_C(0x80000000)];
163	else if (uLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
164	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmCentaur[uLeaf - UINT32_C(0xc0000000)];
165	else
166	continue;
167
168	uint32_t eax, ebx, ecx, edx;
169	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &eax, &ebx, &ecx, &edx);
170
171	ASMAtomicAndU32(&pLegacyLeaf->uEcx, ecx \| ~g_aCpuidUnifyBits[i].uEcx);
172	ASMAtomicAndU32(&pLegacyLeaf->uEdx, edx \| ~g_aCpuidUnifyBits[i].uEdx);
173	}
174	}
175
176
177	/**
178	* Does Ring-0 CPUM initialization.
179	*
180	* This is mainly to check that the Host CPU mode is compatible
181	* with VBox.
182	*
183	* @returns VBox status code.
184	* @param pVM The cross context VM structure.
185	*/
186	VMMR0_INT_DECL(int) CPUMR0InitVM(PVMCC pVM)
187	{
188	LogFlow(("CPUMR0Init: %p\n", pVM));
189
190	/*
191	* Check CR0 & CR4 flags.
192	*/
193	uint32_t u32CR0 = ASMGetCR0();
194	if ((u32CR0 & (X86_CR0_PE \| X86_CR0_PG)) != (X86_CR0_PE \| X86_CR0_PG)) /* a bit paranoid perhaps.. */
195	{
196	Log(("CPUMR0Init: PE or PG not set. cr0=%#x\n", u32CR0));
197	return VERR_UNSUPPORTED_CPU_MODE;
198	}
199
200	/*
201	* Check for sysenter and syscall usage.
202	*/
203	if (ASMHasCpuId())
204	{
205	/*
206	* SYSENTER/SYSEXIT
207	*
208	* Intel docs claim you should test both the flag and family, model &
209	* stepping because some Pentium Pro CPUs have the SEP cpuid flag set,
210	* but don't support it. AMD CPUs may support this feature in legacy
211	* mode, they've banned it from long mode. Since we switch to 32-bit
212	* mode when entering raw-mode context the feature would become
213	* accessible again on AMD CPUs, so we have to check regardless of
214	* host bitness.
215	*/
216	uint32_t u32CpuVersion;
217	uint32_t u32Dummy;
218	uint32_t fFeatures; /* (Used further down to check for MSRs, so don't clobber.) */
219	ASMCpuId(1, &u32CpuVersion, &u32Dummy, &u32Dummy, &fFeatures);
220	uint32_t const u32Family = u32CpuVersion >> 8;
221	uint32_t const u32Model = (u32CpuVersion >> 4) & 0xF;
222	uint32_t const u32Stepping = u32CpuVersion & 0xF;
223	if ( (fFeatures & X86_CPUID_FEATURE_EDX_SEP)
224	&& ( u32Family != 6 /* (> pentium pro) */
225	\|\| u32Model >= 3
226	\|\| u32Stepping >= 3
227	\|\| !ASMIsIntelCpu())
228	)
229	{
230	/*
231	* Read the MSR and see if it's in use or not.
232	*/
233	uint32_t u32 = ASMRdMsr_Low(MSR_IA32_SYSENTER_CS);
234	if (u32)
235	{
236	pVM->cpum.s.fHostUseFlags \|= CPUM_USE_SYSENTER;
237	Log(("CPUMR0Init: host uses sysenter cs=%08x%08x\n", ASMRdMsr_High(MSR_IA32_SYSENTER_CS), u32));
238	}
239	}
240
241	/*
242	* SYSCALL/SYSRET
243	*
244	* This feature is indicated by the SEP bit returned in EDX by CPUID
245	* function 0x80000001. Intel CPUs only supports this feature in
246	* long mode. Since we're not running 64-bit guests in raw-mode there
247	* are no issues with 32-bit intel hosts.
248	*/
249	uint32_t cExt = 0;
250	ASMCpuId(0x80000000, &cExt, &u32Dummy, &u32Dummy, &u32Dummy);
251	if (ASMIsValidExtRange(cExt))
252	{
253	uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
254	if (fExtFeaturesEDX & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
255	{
256	#ifdef RT_ARCH_X86
257	if (!ASMIsIntelCpu())
258	#endif
259	{
260	uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
261	if (fEfer & MSR_K6_EFER_SCE)
262	{
263	pVM->cpum.s.fHostUseFlags \|= CPUM_USE_SYSCALL;
264	Log(("CPUMR0Init: host uses syscall\n"));
265	}
266	}
267	}
268	}
269
270	/*
271	* Copy MSR_IA32_ARCH_CAPABILITIES bits over into the host and guest feature
272	* structure and as well as the guest MSR.
273	*/
274	pVM->cpum.s.HostFeatures.fArchRdclNo = 0;
275	pVM->cpum.s.HostFeatures.fArchIbrsAll = 0;
276	pVM->cpum.s.HostFeatures.fArchRsbOverride = 0;
277	pVM->cpum.s.HostFeatures.fArchVmmNeedNotFlushL1d = 0;
278	pVM->cpum.s.HostFeatures.fArchMdsNo = 0;
279	uint32_t const cStdRange = ASMCpuId_EAX(0);
280	if ( ASMIsValidStdRange(cStdRange)
281	&& cStdRange >= 7)
282	{
283	uint32_t fEdxFeatures = ASMCpuId_EDX(7);
284	if ( (fEdxFeatures & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP)
285	&& (fFeatures & X86_CPUID_FEATURE_EDX_MSR))
286	{
287	uint64_t const fArchVal = ASMRdMsr(MSR_IA32_ARCH_CAPABILITIES);
288	pVM->cpum.s.GuestFeatures.fArchRdclNo
289	= pVM->cpum.s.HostFeatures.fArchRdclNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RDCL_NO);
290	pVM->cpum.s.GuestFeatures.fArchIbrsAll
291	= pVM->cpum.s.HostFeatures.fArchIbrsAll = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_IBRS_ALL);
292	pVM->cpum.s.GuestFeatures.fArchRsbOverride
293	= pVM->cpum.s.HostFeatures.fArchRsbOverride = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RSBO);
294	pVM->cpum.s.GuestFeatures.fArchVmmNeedNotFlushL1d
295	= pVM->cpum.s.HostFeatures.fArchVmmNeedNotFlushL1d = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D);
296	pVM->cpum.s.GuestFeatures.fArchMdsNo
297	= pVM->cpum.s.HostFeatures.fArchMdsNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_MDS_NO);
298
299	if (pVM->cpum.s.GuestFeatures.fArchCap)
300	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.GuestMsrs.msr.ArchCaps = fArchVal);
301	}
302	else
303	pVM->cpum.s.HostFeatures.fArchCap = 0;
304	}
305
306	/*
307	* Unify/cross check some CPUID feature bits on all available CPU cores
308	* and threads. We've seen CPUs where the monitor support differed.
309	*
310	* Because the hyper heap isn't always mapped into ring-0, we cannot
311	* access it from a RTMpOnAll callback. We use the legacy CPUID arrays
312	* as temp ring-0 accessible memory instead, ASSUMING that they're all
313	* up to date when we get here.
314	*/
315	RTMpOnAll(cpumR0CheckCpuid, pVM, NULL);
316
317	for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
318	{
319	bool fIgnored;
320	uint32_t uLeaf = g_aCpuidUnifyBits[i].uLeaf;
321	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafEx(pVM, uLeaf, 0, &fIgnored);
322	if (pLeaf)
323	{
324	PCPUMCPUID pLegacyLeaf;
325	if (uLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
326	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmStd[uLeaf];
327	else if (uLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
328	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmExt[uLeaf - UINT32_C(0x80000000)];
329	else if (uLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
330	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmCentaur[uLeaf - UINT32_C(0xc0000000)];
331	else
332	continue;
333
334	pLeaf->uEcx = pLegacyLeaf->uEcx;
335	pLeaf->uEdx = pLegacyLeaf->uEdx;
336	}
337	}
338
339	}
340
341
342	/*
343	* Check if debug registers are armed.
344	* This ASSUMES that DR7.GD is not set, or that it's handled transparently!
345	*/
346	uint32_t u32DR7 = ASMGetDR7();
347	if (u32DR7 & X86_DR7_ENABLED_MASK)
348	{
349	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HOST);
350	Log(("CPUMR0Init: host uses debug registers (dr7=%x)\n", u32DR7));
351	}
352
353	return VINF_SUCCESS;
354	}
355
356
357	/**
358	* Trap handler for device-not-available fault (\#NM).
359	* Device not available, FP or (F)WAIT instruction.
360	*
361	* @returns VBox status code.
362	* @retval VINF_SUCCESS if the guest FPU state is loaded.
363	* @retval VINF_EM_RAW_GUEST_TRAP if it is a guest trap.
364	* @retval VINF_CPUM_HOST_CR0_MODIFIED if we modified the host CR0.
365	*
366	* @param pVM The cross context VM structure.
367	* @param pVCpu The cross context virtual CPU structure.
368	*/
369	VMMR0_INT_DECL(int) CPUMR0Trap07Handler(PVMCC pVM, PVMCPUCC pVCpu)
370	{
371	Assert(pVM->cpum.s.HostFeatures.fFxSaveRstor);
372	Assert(ASMGetCR4() & X86_CR4_OSFXSR);
373
374	/* If the FPU state has already been loaded, then it's a guest trap. */
375	if (CPUMIsGuestFPUStateActive(pVCpu))
376	{
377	Assert( ((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_TS))
378	\|\| ((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_TS \| X86_CR0_EM)));
379	return VINF_EM_RAW_GUEST_TRAP;
380	}
381
382	/*
383	* There are two basic actions:
384	* 1. Save host fpu and restore guest fpu.
385	* 2. Generate guest trap.
386	*
387	* When entering the hypervisor we'll always enable MP (for proper wait
388	* trapping) and TS (for intercepting all fpu/mmx/sse stuff). The EM flag
389	* is taken from the guest OS in order to get proper SSE handling.
390	*
391	*
392	* Actions taken depending on the guest CR0 flags:
393	*
394	* 3 2 1
395	* TS \| EM \| MP \| FPUInstr \| WAIT :: VMM Action
396	* ------------------------------------------------------------------------
397	* 0 \| 0 \| 0 \| Exec \| Exec :: Clear TS & MP, Save HC, Load GC.
398	* 0 \| 0 \| 1 \| Exec \| Exec :: Clear TS, Save HC, Load GC.
399	* 0 \| 1 \| 0 \| #NM \| Exec :: Clear TS & MP, Save HC, Load GC.
400	* 0 \| 1 \| 1 \| #NM \| Exec :: Clear TS, Save HC, Load GC.
401	* 1 \| 0 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already cleared.)
402	* 1 \| 0 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
403	* 1 \| 1 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already set.)
404	* 1 \| 1 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
405	*/
406
407	switch (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
408	{
409	case X86_CR0_MP \| X86_CR0_TS:
410	case X86_CR0_MP \| X86_CR0_TS \| X86_CR0_EM:
411	return VINF_EM_RAW_GUEST_TRAP;
412	default:
413	break;
414	}
415
416	return CPUMR0LoadGuestFPU(pVM, pVCpu);
417	}
418
419
420	/**
421	* Saves the host-FPU/XMM state (if necessary) and (always) loads the guest-FPU
422	* state into the CPU.
423	*
424	* @returns VINF_SUCCESS on success, host CR0 unmodified.
425	* @returns VINF_CPUM_HOST_CR0_MODIFIED on success when the host CR0 was
426	* modified and VT-x needs to update the value in the VMCS.
427	*
428	* @param pVM The cross context VM structure.
429	* @param pVCpu The cross context virtual CPU structure.
430	*/
431	VMMR0_INT_DECL(int) CPUMR0LoadGuestFPU(PVMCC pVM, PVMCPUCC pVCpu)
432	{
433	int rc;
434	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
435	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST));
436	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE));
437
438	if (!pVM->cpum.s.HostFeatures.fLeakyFxSR)
439	{
440	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE));
441	rc = cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
442	}
443	else
444	{
445	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE) \|\| (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_HOST));
446	/** @todo r=ramshankar: Can't we used a cached value here
447	* instead of reading the MSR? host EFER doesn't usually
448	* change. */
449	uint64_t uHostEfer = ASMRdMsr(MSR_K6_EFER);
450	if (!(uHostEfer & MSR_K6_EFER_FFXSR))
451	rc = cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
452	else
453	{
454	RTCCUINTREG const uSavedFlags = ASMIntDisableFlags();
455	pVCpu->cpum.s.fUseFlags \|= CPUM_USED_MANUAL_XMM_RESTORE;
456	ASMWrMsr(MSR_K6_EFER, uHostEfer & ~MSR_K6_EFER_FFXSR);
457	rc = cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
458	ASMWrMsr(MSR_K6_EFER, uHostEfer \| MSR_K6_EFER_FFXSR);
459	ASMSetFlags(uSavedFlags);
460	}
461	}
462	Assert( (pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST \| CPUM_USED_FPU_SINCE_REM))
463	== (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST \| CPUM_USED_FPU_SINCE_REM));
464	return rc;
465	}
466
467
468	/**
469	* Saves the guest FPU/XMM state if needed, restores the host FPU/XMM state as
470	* needed.
471	*
472	* @returns true if we saved the guest state.
473	* @param pVCpu The cross context virtual CPU structure.
474	*/
475	VMMR0_INT_DECL(bool) CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(PVMCPUCC pVCpu)
476	{
477	bool fSavedGuest;
478	Assert(pVCpu->CTX_SUFF(pVM)->cpum.s.HostFeatures.fFxSaveRstor);
479	Assert(ASMGetCR4() & X86_CR4_OSFXSR);
480	if (pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST))
481	{
482	fSavedGuest = RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST);
483	if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE))
484	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
485	else
486	{
487	/* Temporarily clear MSR_K6_EFER_FFXSR or else we'll be unable to
488	save/restore the XMM state with fxsave/fxrstor. */
489	uint64_t uHostEfer = ASMRdMsr(MSR_K6_EFER);
490	if (uHostEfer & MSR_K6_EFER_FFXSR)
491	{
492	RTCCUINTREG const uSavedFlags = ASMIntDisableFlags();
493	ASMWrMsr(MSR_K6_EFER, uHostEfer & ~MSR_K6_EFER_FFXSR);
494	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
495	ASMWrMsr(MSR_K6_EFER, uHostEfer \| MSR_K6_EFER_FFXSR);
496	ASMSetFlags(uSavedFlags);
497	}
498	else
499	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
500	pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_MANUAL_XMM_RESTORE;
501	}
502	}
503	else
504	fSavedGuest = false;
505	Assert(!( pVCpu->cpum.s.fUseFlags
506	& (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST \| CPUM_SYNC_FPU_STATE \| CPUM_USED_MANUAL_XMM_RESTORE)));
507	return fSavedGuest;
508	}
509
510
511	/**
512	* Saves the host debug state, setting CPUM_USED_HOST_DEBUG_STATE and loading
513	* DR7 with safe values.
514	*
515	* @returns VBox status code.
516	* @param pVCpu The cross context virtual CPU structure.
517	*/
518	static int cpumR0SaveHostDebugState(PVMCPUCC pVCpu)
519	{
520	/*
521	* Save the host state.
522	*/
523	pVCpu->cpum.s.Host.dr0 = ASMGetDR0();
524	pVCpu->cpum.s.Host.dr1 = ASMGetDR1();
525	pVCpu->cpum.s.Host.dr2 = ASMGetDR2();
526	pVCpu->cpum.s.Host.dr3 = ASMGetDR3();
527	pVCpu->cpum.s.Host.dr6 = ASMGetDR6();
528	/** @todo dr7 might already have been changed to 0x400; don't care right now as it's harmless. */
529	pVCpu->cpum.s.Host.dr7 = ASMGetDR7();
530
531	/* Preemption paranoia. */
532	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HOST);
533
534	/*
535	* Make sure DR7 is harmless or else we could trigger breakpoints when
536	* load guest or hypervisor DRx values later.
537	*/
538	if (pVCpu->cpum.s.Host.dr7 != X86_DR7_INIT_VAL)
539	ASMSetDR7(X86_DR7_INIT_VAL);
540
541	return VINF_SUCCESS;
542	}
543
544
545	/**
546	* Saves the guest DRx state residing in host registers and restore the host
547	* register values.
548	*
549	* The guest DRx state is only saved if CPUMR0LoadGuestDebugState was called,
550	* since it's assumed that we're shadowing the guest DRx register values
551	* accurately when using the combined hypervisor debug register values
552	* (CPUMR0LoadHyperDebugState).
553	*
554	* @returns true if either guest or hypervisor debug registers were loaded.
555	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
556	* @param fDr6 Whether to include DR6 or not.
557	* @thread EMT(pVCpu)
558	*/
559	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(PVMCPUCC pVCpu, bool fDr6)
560	{
561	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
562	bool const fDrXLoaded = RT_BOOL(pVCpu->cpum.s.fUseFlags & (CPUM_USED_DEBUG_REGS_GUEST \| CPUM_USED_DEBUG_REGS_HYPER));
563
564	/*
565	* Do we need to save the guest DRx registered loaded into host registers?
566	* (DR7 and DR6 (if fDr6 is true) are left to the caller.)
567	*/
568	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST)
569	{
570	pVCpu->cpum.s.Guest.dr[0] = ASMGetDR0();
571	pVCpu->cpum.s.Guest.dr[1] = ASMGetDR1();
572	pVCpu->cpum.s.Guest.dr[2] = ASMGetDR2();
573	pVCpu->cpum.s.Guest.dr[3] = ASMGetDR3();
574	if (fDr6)
575	pVCpu->cpum.s.Guest.dr[6] = ASMGetDR6();
576	}
577	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~( CPUM_USED_DEBUG_REGS_GUEST \| CPUM_USED_DEBUG_REGS_HYPER
578	\| CPUM_SYNC_DEBUG_REGS_GUEST \| CPUM_SYNC_DEBUG_REGS_HYPER));
579
580	/*
581	* Restore the host's debug state. DR0-3, DR6 and only then DR7!
582	*/
583	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HOST)
584	{
585	/* A bit of paranoia first... */
586	uint64_t uCurDR7 = ASMGetDR7();
587	if (uCurDR7 != X86_DR7_INIT_VAL)
588	ASMSetDR7(X86_DR7_INIT_VAL);
589
590	ASMSetDR0(pVCpu->cpum.s.Host.dr0);
591	ASMSetDR1(pVCpu->cpum.s.Host.dr1);
592	ASMSetDR2(pVCpu->cpum.s.Host.dr2);
593	ASMSetDR3(pVCpu->cpum.s.Host.dr3);
594	/** @todo consider only updating if they differ, esp. DR6. Need to figure how
595	* expensive DRx reads are over DRx writes. */
596	ASMSetDR6(pVCpu->cpum.s.Host.dr6);
597	ASMSetDR7(pVCpu->cpum.s.Host.dr7);
598
599	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_HOST);
600	}
601
602	return fDrXLoaded;
603	}
604
605
606	/**
607	* Saves the guest DRx state if it resides host registers.
608	*
609	* This does NOT clear any use flags, so the host registers remains loaded with
610	* the guest DRx state upon return. The purpose is only to make sure the values
611	* in the CPU context structure is up to date.
612	*
613	* @returns true if the host registers contains guest values, false if not.
614	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
615	* @param fDr6 Whether to include DR6 or not.
616	* @thread EMT(pVCpu)
617	*/
618	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuest(PVMCPUCC pVCpu, bool fDr6)
619	{
620	/*
621	* Do we need to save the guest DRx registered loaded into host registers?
622	* (DR7 and DR6 (if fDr6 is true) are left to the caller.)
623	*/
624	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST)
625	{
626	pVCpu->cpum.s.Guest.dr[0] = ASMGetDR0();
627	pVCpu->cpum.s.Guest.dr[1] = ASMGetDR1();
628	pVCpu->cpum.s.Guest.dr[2] = ASMGetDR2();
629	pVCpu->cpum.s.Guest.dr[3] = ASMGetDR3();
630	if (fDr6)
631	pVCpu->cpum.s.Guest.dr[6] = ASMGetDR6();
632	return true;
633	}
634	return false;
635	}
636
637
638	/**
639	* Lazily sync in the debug state.
640	*
641	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
642	* @param fDr6 Whether to include DR6 or not.
643	* @thread EMT(pVCpu)
644	*/
645	VMMR0_INT_DECL(void) CPUMR0LoadGuestDebugState(PVMCPUCC pVCpu, bool fDr6)
646	{
647	/*
648	* Save the host state and disarm all host BPs.
649	*/
650	cpumR0SaveHostDebugState(pVCpu);
651	Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
652
653	/*
654	* Activate the guest state DR0-3.
655	* DR7 and DR6 (if fDr6 is true) are left to the caller.
656	*/
657	ASMSetDR0(pVCpu->cpum.s.Guest.dr[0]);
658	ASMSetDR1(pVCpu->cpum.s.Guest.dr[1]);
659	ASMSetDR2(pVCpu->cpum.s.Guest.dr[2]);
660	ASMSetDR3(pVCpu->cpum.s.Guest.dr[3]);
661	if (fDr6)
662	ASMSetDR6(pVCpu->cpum.s.Guest.dr[6]);
663
664	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_GUEST);
665	}
666
667
668	/**
669	* Lazily sync in the hypervisor debug state
670	*
671	* @returns VBox status code.
672	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
673	* @param fDr6 Whether to include DR6 or not.
674	* @thread EMT(pVCpu)
675	*/
676	VMMR0_INT_DECL(void) CPUMR0LoadHyperDebugState(PVMCPUCC pVCpu, bool fDr6)
677	{
678	/*
679	* Save the host state and disarm all host BPs.
680	*/
681	cpumR0SaveHostDebugState(pVCpu);
682	Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
683
684	/*
685	* Make sure the hypervisor values are up to date.
686	*/
687	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX /* no loading, please */, true);
688
689	/*
690	* Activate the guest state DR0-3.
691	* DR7 and DR6 (if fDr6 is true) are left to the caller.
692	*/
693	ASMSetDR0(pVCpu->cpum.s.Hyper.dr[0]);
694	ASMSetDR1(pVCpu->cpum.s.Hyper.dr[1]);
695	ASMSetDR2(pVCpu->cpum.s.Hyper.dr[2]);
696	ASMSetDR3(pVCpu->cpum.s.Hyper.dr[3]);
697	if (fDr6)
698	ASMSetDR6(X86_DR6_INIT_VAL);
699
700	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HYPER);
701	}
702
703	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
704
705	/**
706	* Per-CPU callback that probes the CPU for APIC support.
707	*
708	* @param idCpu The identifier for the CPU the function is called on.
709	* @param pvUser1 Ignored.
710	* @param pvUser2 Ignored.
711	*/
712	static DECLCALLBACK(void) cpumR0MapLocalApicCpuProber(RTCPUID idCpu, void pvUser1, void pvUser2)
713	{
714	NOREF(pvUser1); NOREF(pvUser2);
715	int iCpu = RTMpCpuIdToSetIndex(idCpu);
716	AssertReturnVoid(iCpu >= 0 && (unsigned)iCpu < RT_ELEMENTS(g_aLApics));
717
718	/*
719	* Check for APIC support.
720	*/
721	uint32_t uMaxLeaf, u32EBX, u32ECX, u32EDX;
722	ASMCpuId(0, &uMaxLeaf, &u32EBX, &u32ECX, &u32EDX);
723	if ( ( ASMIsIntelCpuEx(u32EBX, u32ECX, u32EDX)
724	\|\| ASMIsAmdCpuEx(u32EBX, u32ECX, u32EDX)
725	\|\| ASMIsViaCentaurCpuEx(u32EBX, u32ECX, u32EDX)
726	\|\| ASMIsShanghaiCpuEx(u32EBX, u32ECX, u32EDX))
727	&& ASMIsValidStdRange(uMaxLeaf))
728	{
729	uint32_t uDummy;
730	ASMCpuId(1, &uDummy, &u32EBX, &u32ECX, &u32EDX);
731	if ( (u32EDX & X86_CPUID_FEATURE_EDX_APIC)
732	&& (u32EDX & X86_CPUID_FEATURE_EDX_MSR))
733	{
734	/*
735	* Safe to access the MSR. Read it and calc the BASE (a little complicated).
736	*/
737	uint64_t u64ApicBase = ASMRdMsr(MSR_IA32_APICBASE);
738	uint64_t u64Mask = MSR_IA32_APICBASE_BASE_MIN;
739
740	/* see Intel Manual: Local APIC Status and Location: MAXPHYADDR default is bit 36 */
741	uint32_t uMaxExtLeaf;
742	ASMCpuId(0x80000000, &uMaxExtLeaf, &u32EBX, &u32ECX, &u32EDX);
743	if ( uMaxExtLeaf >= UINT32_C(0x80000008)
744	&& ASMIsValidExtRange(uMaxExtLeaf))
745	{
746	uint32_t u32PhysBits;
747	ASMCpuId(0x80000008, &u32PhysBits, &u32EBX, &u32ECX, &u32EDX);
748	u32PhysBits &= 0xff;
749	u64Mask = ((UINT64_C(1) << u32PhysBits) - 1) & UINT64_C(0xfffffffffffff000);
750	}
751
752	AssertCompile(sizeof(g_aLApics[iCpu].PhysBase) == sizeof(u64ApicBase));
753	g_aLApics[iCpu].PhysBase = u64ApicBase & u64Mask;
754	g_aLApics[iCpu].fEnabled = RT_BOOL(u64ApicBase & MSR_IA32_APICBASE_EN);
755	g_aLApics[iCpu].fX2Apic = (u64ApicBase & (MSR_IA32_APICBASE_EXTD \| MSR_IA32_APICBASE_EN))
756	== (MSR_IA32_APICBASE_EXTD \| MSR_IA32_APICBASE_EN);
757	}
758	}
759	}
760
761
762
763	/**
764	* Per-CPU callback that verifies our APIC expectations.
765	*
766	* @param idCpu The identifier for the CPU the function is called on.
767	* @param pvUser1 Ignored.
768	* @param pvUser2 Ignored.
769	*/
770	static DECLCALLBACK(void) cpumR0MapLocalApicCpuChecker(RTCPUID idCpu, void pvUser1, void pvUser2)
771	{
772	NOREF(pvUser1); NOREF(pvUser2);
773
774	int iCpu = RTMpCpuIdToSetIndex(idCpu);
775	AssertReturnVoid(iCpu >= 0 && (unsigned)iCpu < RT_ELEMENTS(g_aLApics));
776	if (!g_aLApics[iCpu].fEnabled)
777	return;
778
779	/*
780	* 0x0X 82489 external APIC
781	* 0x1X Local APIC
782	* 0x2X..0xFF reserved
783	*/
784	uint32_t uApicVersion;
785	if (g_aLApics[iCpu].fX2Apic)
786	uApicVersion = ApicX2RegRead32(APIC_REG_VERSION);
787	else
788	uApicVersion = ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_VERSION);
789	if ((APIC_REG_VERSION_GET_VER(uApicVersion) & 0xF0) == 0x10)
790	{
791	g_aLApics[iCpu].uVersion = uApicVersion;
792
793	# if 0 /* enable if you need it. */
794	if (g_aLApics[iCpu].fX2Apic)
795	SUPR0Printf("CPUM: X2APIC %02u - ver %#010x, lint0=%#07x lint1=%#07x pc=%#07x thmr=%#07x cmci=%#07x\n",
796	iCpu, uApicVersion,
797	ApicX2RegRead32(APIC_REG_LVT_LINT0), ApicX2RegRead32(APIC_REG_LVT_LINT1),
798	ApicX2RegRead32(APIC_REG_LVT_PC), ApicX2RegRead32(APIC_REG_LVT_THMR),
799	ApicX2RegRead32(APIC_REG_LVT_CMCI));
800	else
801	{
802	SUPR0Printf("CPUM: APIC %02u at %RGp (mapped at %p) - ver %#010x, lint0=%#07x lint1=%#07x pc=%#07x thmr=%#07x cmci=%#07x\n",
803	iCpu, g_aLApics[iCpu].PhysBase, g_aLApics[iCpu].pv, uApicVersion,
804	ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_LINT0), ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_LINT1),
805	ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_PC), ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_THMR),
806	ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_CMCI));
807	if (uApicVersion & 0x80000000)
808	{
809	uint32_t uExtFeatures = ApicRegRead(g_aLApics[iCpu].pv, 0x400);
810	uint32_t cEiLvt = (uExtFeatures >> 16) & 0xff;
811	SUPR0Printf("CPUM: APIC %02u: ExtSpace available. extfeat=%08x eilvt[0..3]=%08x %08x %08x %08x\n",
812	iCpu,
813	ApicRegRead(g_aLApics[iCpu].pv, 0x400),
814	cEiLvt >= 1 ? ApicRegRead(g_aLApics[iCpu].pv, 0x500) : 0,
815	cEiLvt >= 2 ? ApicRegRead(g_aLApics[iCpu].pv, 0x510) : 0,
816	cEiLvt >= 3 ? ApicRegRead(g_aLApics[iCpu].pv, 0x520) : 0,
817	cEiLvt >= 4 ? ApicRegRead(g_aLApics[iCpu].pv, 0x530) : 0);
818	}
819	}
820	# endif
821	}
822	else
823	{
824	g_aLApics[iCpu].fEnabled = false;
825	g_aLApics[iCpu].fX2Apic = false;
826	SUPR0Printf("VBox/CPUM: Unsupported APIC version %#x (iCpu=%d)\n", uApicVersion, iCpu);
827	}
828	}
829
830
831	/**
832	* Map the MMIO page of each local APIC in the system.
833	*/
834	static int cpumR0MapLocalApics(void)
835	{
836	/*
837	* Check that we'll always stay within the array bounds.
838	*/
839	if (RTMpGetArraySize() > RT_ELEMENTS(g_aLApics))
840	{
841	LogRel(("CPUM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_aLApics)));
842	return VERR_TOO_MANY_CPUS;
843	}
844
845	/*
846	* Create mappings for all online CPUs we think have legacy APICs.
847	*/
848	int rc = RTMpOnAll(cpumR0MapLocalApicCpuProber, NULL, NULL);
849
850	for (unsigned iCpu = 0; RT_SUCCESS(rc) && iCpu < RT_ELEMENTS(g_aLApics); iCpu++)
851	{
852	if (g_aLApics[iCpu].fEnabled && !g_aLApics[iCpu].fX2Apic)
853	{
854	rc = RTR0MemObjEnterPhys(&g_aLApics[iCpu].hMemObj, g_aLApics[iCpu].PhysBase,
855	PAGE_SIZE, RTMEM_CACHE_POLICY_MMIO);
856	if (RT_SUCCESS(rc))
857	{
858	rc = RTR0MemObjMapKernel(&g_aLApics[iCpu].hMapObj, g_aLApics[iCpu].hMemObj, (void *)-1,
859	PAGE_SIZE, RTMEM_PROT_READ \| RTMEM_PROT_WRITE);
860	if (RT_SUCCESS(rc))
861	{
862	g_aLApics[iCpu].pv = RTR0MemObjAddress(g_aLApics[iCpu].hMapObj);
863	continue;
864	}
865	RTR0MemObjFree(g_aLApics[iCpu].hMemObj, true /* fFreeMappings */);
866	}
867	g_aLApics[iCpu].fEnabled = false;
868	}
869	g_aLApics[iCpu].pv = NULL;
870	}
871
872	/*
873	* Check the APICs.
874	*/
875	if (RT_SUCCESS(rc))
876	rc = RTMpOnAll(cpumR0MapLocalApicCpuChecker, NULL, NULL);
877
878	if (RT_FAILURE(rc))
879	{
880	cpumR0UnmapLocalApics();
881	return rc;
882	}
883
884	# ifdef LOG_ENABLED
885	/*
886	* Log the result (pretty useless, requires enabling CPUM in VBoxDrv
887	* and !VBOX_WITH_R0_LOGGING).
888	*/
889	if (LogIsEnabled())
890	{
891	uint32_t cEnabled = 0;
892	uint32_t cX2Apics = 0;
893	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_aLApics); iCpu++)
894	if (g_aLApics[iCpu].fEnabled)
895	{
896	cEnabled++;
897	cX2Apics += g_aLApics[iCpu].fX2Apic;
898	}
899	Log(("CPUM: %u APICs, %u X2APICs\n", cEnabled, cX2Apics));
900	}
901	# endif
902
903	return VINF_SUCCESS;
904	}
905
906
907	/**
908	* Unmap the Local APIC of all host CPUs.
909	*/
910	static void cpumR0UnmapLocalApics(void)
911	{
912	for (unsigned iCpu = RT_ELEMENTS(g_aLApics); iCpu-- > 0;)
913	{
914	if (g_aLApics[iCpu].pv)
915	{
916	RTR0MemObjFree(g_aLApics[iCpu].hMapObj, true /* fFreeMappings */);
917	RTR0MemObjFree(g_aLApics[iCpu].hMemObj, true /* fFreeMappings */);
918	g_aLApics[iCpu].hMapObj = NIL_RTR0MEMOBJ;
919	g_aLApics[iCpu].hMemObj = NIL_RTR0MEMOBJ;
920	g_aLApics[iCpu].fEnabled = false;
921	g_aLApics[iCpu].fX2Apic = false;
922	g_aLApics[iCpu].pv = NULL;
923	}
924	}
925	}
926
927
928	/**
929	* Updates CPUMCPU::pvApicBase and CPUMCPU::fX2Apic prior to world switch.
930	*
931	* Writes the Local APIC mapping address of the current host CPU to CPUMCPU so
932	* the world switchers can access the APIC registers for the purpose of
933	* disabling and re-enabling the NMIs. Must be called with disabled preemption
934	* or disabled interrupts!
935	*
936	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
937	* @param iHostCpuSet The CPU set index of the current host CPU.
938	*/
939	VMMR0_INT_DECL(void) CPUMR0SetLApic(PVMCPUCC pVCpu, uint32_t iHostCpuSet)
940	{
941	Assert(iHostCpuSet <= RT_ELEMENTS(g_aLApics));
942	pVCpu->cpum.s.pvApicBase = g_aLApics[iHostCpuSet].pv;
943	pVCpu->cpum.s.fX2Apic = g_aLApics[iHostCpuSet].fX2Apic;
944	// Log6(("CPUMR0SetLApic: pvApicBase=%p fX2Apic=%d\n", g_aLApics[idxCpu].pv, g_aLApics[idxCpu].fX2Apic));
945	}
946
947	#endif /* VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI */
948

注意: 瀏覽 TracBrowser 來幫助您使用儲存庫瀏覽器

source: vbox/trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp@ 80274

以其他格式下載: