CPUMR0.cpp@ 54737

最後變更在這個檔案從54737是 54737,由 vboxsync 提交於 10 年前
VMM,REM: CPUID revamp - almost there now.
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1	/* $Id: CPUMR0.cpp 54737 2015-03-12 21:02:21Z vboxsync $ */
2	/** @file
3	* CPUM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.alldomusa.eu.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include "CPUMInternal.h"
25	#include <VBox/vmm/vm.h>
26	#include <VBox/err.h>
27	#include <VBox/log.h>
28	#include <VBox/vmm/hm.h>
29	#include <iprt/assert.h>
30	#include <iprt/asm-amd64-x86.h>
31	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
32	# include <iprt/mem.h>
33	# include <iprt/memobj.h>
34	# include <VBox/apic.h>
35	#endif
36	#include <iprt/x86.h>
37
38
39	/*******************************************************************************
40	* Structures and Typedefs *
41	*******************************************************************************/
42	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
43	/**
44	* Local APIC mappings.
45	*/
46	typedef struct CPUMHOSTLAPIC
47	{
48	/** Indicates that the entry is in use and have valid data. */
49	bool fEnabled;
50	/** Whether it's operating in X2APIC mode (EXTD). */
51	bool fX2Apic;
52	/** The APIC version number. */
53	uint32_t uVersion;
54	/** The physical address of the APIC registers. */
55	RTHCPHYS PhysBase;
56	/** The memory object entering the physical address. */
57	RTR0MEMOBJ hMemObj;
58	/** The mapping object for hMemObj. */
59	RTR0MEMOBJ hMapObj;
60	/** The mapping address APIC registers.
61	* @remarks Different CPUs may use the same physical address to map their
62	* APICs, so this pointer is only valid when on the CPU owning the
63	* APIC. */
64	void *pv;
65	} CPUMHOSTLAPIC;
66	#endif
67
68
69	/*******************************************************************************
70	* Global Variables *
71	*******************************************************************************/
72	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
73	static CPUMHOSTLAPIC g_aLApics[RTCPUSET_MAX_CPUS];
74	#endif
75
76	/**
77	* CPUID bits to unify among all cores.
78	*/
79	static struct
80	{
81	uint32_t uLeaf; /*< Leaf to check. /
82	uint32_t uEcx; /*< which bits in ecx to unify between CPUs. /
83	uint32_t uEdx; /*< which bits in edx to unify between CPUs. /
84	}
85	const g_aCpuidUnifyBits[] =
86	{
87	{
88	0x00000001,
89	X86_CPUID_FEATURE_ECX_CX16 \| X86_CPUID_FEATURE_ECX_MONITOR,
90	X86_CPUID_FEATURE_EDX_CX8
91	}
92	};
93
94
95
96	/*******************************************************************************
97	* Internal Functions *
98	*******************************************************************************/
99	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
100	static int cpumR0MapLocalApics(void);
101	static void cpumR0UnmapLocalApics(void);
102	#endif
103	static int cpumR0SaveHostDebugState(PVMCPU pVCpu);
104
105
106	/**
107	* Does the Ring-0 CPU initialization once during module load.
108	* XXX Host-CPU hot-plugging?
109	*/
110	VMMR0_INT_DECL(int) CPUMR0ModuleInit(void)
111	{
112	int rc = VINF_SUCCESS;
113	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
114	rc = cpumR0MapLocalApics();
115	#endif
116	return rc;
117	}
118
119
120	/**
121	* Terminate the module.
122	*/
123	VMMR0_INT_DECL(int) CPUMR0ModuleTerm(void)
124	{
125	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
126	cpumR0UnmapLocalApics();
127	#endif
128	return VINF_SUCCESS;
129	}
130
131
132	/**
133	*
134	*
135	* Check the CPUID features of this particular CPU and disable relevant features
136	* for the guest which do not exist on this CPU. We have seen systems where the
137	* X86_CPUID_FEATURE_ECX_MONITOR feature flag is only set on some host CPUs, see
138	* @bugref{5436}.
139	*
140	* @note This function might be called simultaneously on more than one CPU!
141	*
142	* @param idCpu The identifier for the CPU the function is called on.
143	* @param pvUser1 Pointer to the VM structure.
144	* @param pvUser2 Ignored.
145	*/
146	static DECLCALLBACK(void) cpumR0CheckCpuid(RTCPUID idCpu, void pvUser1, void pvUser2)
147	{
148	PVM pVM = (PVM)pvUser1;
149	PCPUM pCPUM = &pVM->cpum.s;
150
151	NOREF(idCpu); NOREF(pvUser2);
152	for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
153	{
154	/* Note! Cannot use cpumCpuIdGetLeaf from here because we're not
155	necessarily in the VM process context. So, we using the
156	legacy arrays as temporary storage. */
157
158	uint32_t uLeaf = g_aCpuidUnifyBits[i].uLeaf;
159	PCPUMCPUID pLegacyLeaf;
160	if (uLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
161	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmStd[uLeaf];
162	else if (uLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
163	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmExt[uLeaf - UINT32_C(0x80000000)];
164	else if (uLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
165	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmCentaur[uLeaf - UINT32_C(0xc0000000)];
166	else
167	continue;
168
169	uint32_t eax, ebx, ecx, edx;
170	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &eax, &ebx, &ecx, &edx);
171
172	ASMAtomicAndU32(&pLegacyLeaf->uEcx, ecx \| ~g_aCpuidUnifyBits[i].uEcx);
173	ASMAtomicAndU32(&pLegacyLeaf->uEdx, edx \| ~g_aCpuidUnifyBits[i].uEdx);
174	}
175	}
176
177
178	/**
179	* Does Ring-0 CPUM initialization.
180	*
181	* This is mainly to check that the Host CPU mode is compatible
182	* with VBox.
183	*
184	* @returns VBox status code.
185	* @param pVM Pointer to the VM.
186	*/
187	VMMR0_INT_DECL(int) CPUMR0InitVM(PVM pVM)
188	{
189	LogFlow(("CPUMR0Init: %p\n", pVM));
190
191	/*
192	* Check CR0 & CR4 flags.
193	*/
194	uint32_t u32CR0 = ASMGetCR0();
195	if ((u32CR0 & (X86_CR0_PE \| X86_CR0_PG)) != (X86_CR0_PE \| X86_CR0_PG)) /* a bit paranoid perhaps.. */
196	{
197	Log(("CPUMR0Init: PE or PG not set. cr0=%#x\n", u32CR0));
198	return VERR_UNSUPPORTED_CPU_MODE;
199	}
200
201	/*
202	* Check for sysenter and syscall usage.
203	*/
204	if (ASMHasCpuId())
205	{
206	/*
207	* SYSENTER/SYSEXIT
208	*
209	* Intel docs claim you should test both the flag and family, model &
210	* stepping because some Pentium Pro CPUs have the SEP cpuid flag set,
211	* but don't support it. AMD CPUs may support this feature in legacy
212	* mode, they've banned it from long mode. Since we switch to 32-bit
213	* mode when entering raw-mode context the feature would become
214	* accessible again on AMD CPUs, so we have to check regardless of
215	* host bitness.
216	*/
217	uint32_t u32CpuVersion;
218	uint32_t u32Dummy;
219	uint32_t fFeatures;
220	ASMCpuId(1, &u32CpuVersion, &u32Dummy, &u32Dummy, &fFeatures);
221	uint32_t const u32Family = u32CpuVersion >> 8;
222	uint32_t const u32Model = (u32CpuVersion >> 4) & 0xF;
223	uint32_t const u32Stepping = u32CpuVersion & 0xF;
224	if ( (fFeatures & X86_CPUID_FEATURE_EDX_SEP)
225	&& ( u32Family != 6 /* (> pentium pro) */
226	\|\| u32Model >= 3
227	\|\| u32Stepping >= 3
228	\|\| !ASMIsIntelCpu())
229	)
230	{
231	/*
232	* Read the MSR and see if it's in use or not.
233	*/
234	uint32_t u32 = ASMRdMsr_Low(MSR_IA32_SYSENTER_CS);
235	if (u32)
236	{
237	pVM->cpum.s.fHostUseFlags \|= CPUM_USE_SYSENTER;
238	Log(("CPUMR0Init: host uses sysenter cs=%08x%08x\n", ASMRdMsr_High(MSR_IA32_SYSENTER_CS), u32));
239	}
240	}
241
242	/*
243	* SYSCALL/SYSRET
244	*
245	* This feature is indicated by the SEP bit returned in EDX by CPUID
246	* function 0x80000001. Intel CPUs only supports this feature in
247	* long mode. Since we're not running 64-bit guests in raw-mode there
248	* are no issues with 32-bit intel hosts.
249	*/
250	uint32_t cExt = 0;
251	ASMCpuId(0x80000000, &cExt, &u32Dummy, &u32Dummy, &u32Dummy);
252	if (ASMIsValidExtRange(cExt))
253	{
254	uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
255	if (fExtFeaturesEDX & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
256	{
257	#ifdef RT_ARCH_X86
258	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
259	if (fExtFeaturesEDX & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
260	# else
261	if (!ASMIsIntelCpu())
262	# endif
263	#endif
264	{
265	uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
266	if (fEfer & MSR_K6_EFER_SCE)
267	{
268	pVM->cpum.s.fHostUseFlags \|= CPUM_USE_SYSCALL;
269	Log(("CPUMR0Init: host uses syscall\n"));
270	}
271	}
272	}
273	}
274
275	/*
276	* Unify/cross check some CPUID feature bits on all available CPU cores
277	* and threads. We've seen CPUs where the monitor support differed.
278	*
279	* Because the hyper heap isn't always mapped into ring-0, we cannot
280	* access it from a RTMpOnAll callback. We use the legacy CPUID arrays
281	* as temp ring-0 accessible memory instead, ASSUMING that they're all
282	* up to date when we get here.
283	*/
284	RTMpOnAll(cpumR0CheckCpuid, pVM, NULL);
285
286	for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
287	{
288	bool fIgnored;
289	uint32_t uLeaf = g_aCpuidUnifyBits[i].uLeaf;
290	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafEx(pVM, uLeaf, 0, &fIgnored);
291	if (pLeaf)
292	{
293	PCPUMCPUID pLegacyLeaf;
294	if (uLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
295	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmStd[uLeaf];
296	else if (uLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
297	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmExt[uLeaf - UINT32_C(0x80000000)];
298	else if (uLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
299	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmCentaur[uLeaf - UINT32_C(0xc0000000)];
300	else
301	continue;
302
303	pLeaf->uEcx = pLegacyLeaf->uEcx;
304	pLeaf->uEdx = pLegacyLeaf->uEdx;
305	}
306	}
307
308	}
309
310
311	/*
312	* Check if debug registers are armed.
313	* This ASSUMES that DR7.GD is not set, or that it's handled transparently!
314	*/
315	uint32_t u32DR7 = ASMGetDR7();
316	if (u32DR7 & X86_DR7_ENABLED_MASK)
317	{
318	for (VMCPUID i = 0; i < pVM->cCpus; i++)
319	pVM->aCpus[i].cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HOST;
320	Log(("CPUMR0Init: host uses debug registers (dr7=%x)\n", u32DR7));
321	}
322
323	return VINF_SUCCESS;
324	}
325
326
327	/**
328	* Trap handler for device-not-available fault (#NM).
329	* Device not available, FP or (F)WAIT instruction.
330	*
331	* @returns VBox status code.
332	* @retval VINF_SUCCESS if the guest FPU state is loaded.
333	* @retval VINF_EM_RAW_GUEST_TRAP if it is a guest trap.
334	*
335	* @param pVM Pointer to the VM.
336	* @param pVCpu Pointer to the VMCPU.
337	* @param pCtx Pointer to the guest-CPU context.
338	*/
339	VMMR0_INT_DECL(int) CPUMR0Trap07Handler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
340	{
341	Assert(pVM->cpum.s.CPUFeatures.edx.u1FXSR);
342	Assert(ASMGetCR4() & X86_CR4_OSFSXR);
343
344	/* If the FPU state has already been loaded, then it's a guest trap. */
345	if (CPUMIsGuestFPUStateActive(pVCpu))
346	{
347	Assert( ((pCtx->cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_TS))
348	\|\| ((pCtx->cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_TS \| X86_CR0_EM)));
349	return VINF_EM_RAW_GUEST_TRAP;
350	}
351
352	/*
353	* There are two basic actions:
354	* 1. Save host fpu and restore guest fpu.
355	* 2. Generate guest trap.
356	*
357	* When entering the hypervisor we'll always enable MP (for proper wait
358	* trapping) and TS (for intercepting all fpu/mmx/sse stuff). The EM flag
359	* is taken from the guest OS in order to get proper SSE handling.
360	*
361	*
362	* Actions taken depending on the guest CR0 flags:
363	*
364	* 3 2 1
365	* TS \| EM \| MP \| FPUInstr \| WAIT :: VMM Action
366	* ------------------------------------------------------------------------
367	* 0 \| 0 \| 0 \| Exec \| Exec :: Clear TS & MP, Save HC, Load GC.
368	* 0 \| 0 \| 1 \| Exec \| Exec :: Clear TS, Save HC, Load GC.
369	* 0 \| 1 \| 0 \| #NM \| Exec :: Clear TS & MP, Save HC, Load GC.
370	* 0 \| 1 \| 1 \| #NM \| Exec :: Clear TS, Save HC, Load GC.
371	* 1 \| 0 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already cleared.)
372	* 1 \| 0 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
373	* 1 \| 1 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already set.)
374	* 1 \| 1 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
375	*/
376
377	switch (pCtx->cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
378	{
379	case X86_CR0_MP \| X86_CR0_TS:
380	case X86_CR0_MP \| X86_CR0_TS \| X86_CR0_EM:
381	return VINF_EM_RAW_GUEST_TRAP;
382	default:
383	break;
384	}
385
386	return CPUMR0LoadGuestFPU(pVM, pVCpu, pCtx);
387	}
388
389
390	/**
391	* Saves the host-FPU/XMM state and loads the guest-FPU state into the CPU.
392	*
393	* @returns VBox status code.
394	*
395	* @param pVM Pointer to the VM.
396	* @param pVCpu Pointer to the VMCPU.
397	* @param pCtx Pointer to the guest-CPU context.
398	*/
399	VMMR0_INT_DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
400	{
401
402	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
403	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
404	if (CPUMIsGuestInLongModeEx(pCtx))
405	{
406	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE));
407
408	/* Save the host state and record the fact (CPUM_USED_FPU \| CPUM_USED_FPU_SINCE_REM). */
409	cpumR0SaveHostFPUState(&pVCpu->cpum.s);
410
411	/* Restore the state on entry as we need to be in 64-bit mode to access the full state. */
412	pVCpu->cpum.s.fUseFlags \|= CPUM_SYNC_FPU_STATE;
413	}
414	else
415	#endif
416	{
417	NOREF(pCtx);
418	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE));
419	/** @todo Move the FFXR handling down into
420	* cpumR0SaveHostRestoreGuestFPUState to optimize the
421	* VBOX_WITH_KERNEL_USING_XMM handling. */
422	/* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
423	uint64_t uHostEfer = 0;
424	bool fRestoreEfer = false;
425	if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
426	{
427	/** @todo r=ramshankar: Can't we used a cached value here
428	* instead of reading the MSR? host EFER doesn't usually
429	* change. */
430	uHostEfer = ASMRdMsr(MSR_K6_EFER);
431	if (uHostEfer & MSR_K6_EFER_FFXSR)
432	{
433	ASMWrMsr(MSR_K6_EFER, uHostEfer & ~MSR_K6_EFER_FFXSR);
434	pVCpu->cpum.s.fUseFlags \|= CPUM_USED_MANUAL_XMM_RESTORE;
435	fRestoreEfer = true;
436	}
437	}
438
439	/* Do the job and record that we've switched FPU state. */
440	cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
441
442	/* Restore EFER. */
443	if (fRestoreEfer)
444	ASMWrMsr(MSR_K6_EFER, uHostEfer);
445	}
446
447	Assert((pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU \| CPUM_USED_FPU_SINCE_REM)) == (CPUM_USED_FPU \| CPUM_USED_FPU_SINCE_REM));
448	return VINF_SUCCESS;
449	}
450
451
452	/**
453	* Save guest FPU/XMM state
454	*
455	* @returns VBox status code.
456	* @param pVM Pointer to the VM.
457	* @param pVCpu Pointer to the VMCPU.
458	* @param pCtx Pointer to the guest CPU context.
459	*/
460	VMMR0_INT_DECL(int) CPUMR0SaveGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
461	{
462	Assert(pVM->cpum.s.CPUFeatures.edx.u1FXSR);
463	Assert(ASMGetCR4() & X86_CR4_OSFSXR);
464	AssertReturn((pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU), VINF_SUCCESS);
465	NOREF(pVM); NOREF(pCtx);
466
467	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
468	if (CPUMIsGuestInLongModeEx(pCtx))
469	{
470	if (!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE))
471	{
472	HMR0SaveFPUState(pVM, pVCpu, pCtx);
473	cpumR0RestoreHostFPUState(&pVCpu->cpum.s);
474	}
475	/* else nothing to do; we didn't perform a world switch */
476	}
477	else
478	#endif
479	{
480	#ifdef VBOX_WITH_KERNEL_USING_XMM
481	/*
482	* We've already saved the XMM registers in the assembly wrapper, so
483	* we have to save them before saving the entire FPU state and put them
484	* back afterwards.
485	*/
486	/** @todo This could be skipped if MSR_K6_EFER_FFXSR is set, but
487	* I'm not able to test such an optimization tonight.
488	* We could just all this in assembly. */
489	uint128_t aGuestXmmRegs[16];
490	memcpy(&aGuestXmmRegs[0], &pVCpu->cpum.s.Guest.fpu.aXMM[0], sizeof(aGuestXmmRegs));
491	#endif
492
493	/* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
494	uint64_t uHostEfer = 0;
495	bool fRestoreEfer = false;
496	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE)
497	{
498	uHostEfer = ASMRdMsr(MSR_K6_EFER);
499	if (uHostEfer & MSR_K6_EFER_FFXSR)
500	{
501	ASMWrMsr(MSR_K6_EFER, uHostEfer & ~MSR_K6_EFER_FFXSR);
502	fRestoreEfer = true;
503	}
504	}
505
506	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
507
508	/* Restore EFER MSR */
509	if (fRestoreEfer)
510	ASMWrMsr(MSR_K6_EFER, uHostEfer \| MSR_K6_EFER_FFXSR);
511
512	#ifdef VBOX_WITH_KERNEL_USING_XMM
513	memcpy(&pVCpu->cpum.s.Guest.fpu.aXMM[0], &aGuestXmmRegs[0], sizeof(aGuestXmmRegs));
514	#endif
515	}
516
517	pVCpu->cpum.s.fUseFlags &= ~(CPUM_USED_FPU \| CPUM_SYNC_FPU_STATE \| CPUM_USED_MANUAL_XMM_RESTORE);
518	return VINF_SUCCESS;
519	}
520
521
522	/**
523	* Saves the host debug state, setting CPUM_USED_HOST_DEBUG_STATE and loading
524	* DR7 with safe values.
525	*
526	* @returns VBox status code.
527	* @param pVCpu Pointer to the VMCPU.
528	*/
529	static int cpumR0SaveHostDebugState(PVMCPU pVCpu)
530	{
531	/*
532	* Save the host state.
533	*/
534	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
535	AssertCompile((uintptr_t)&pVCpu->cpum.s.Host.dr3 - (uintptr_t)&pVCpu->cpum.s.Host.dr0 == sizeof(uint64_t) * 3);
536	cpumR0SaveDRx(&pVCpu->cpum.s.Host.dr0);
537	#else
538	pVCpu->cpum.s.Host.dr0 = ASMGetDR0();
539	pVCpu->cpum.s.Host.dr1 = ASMGetDR1();
540	pVCpu->cpum.s.Host.dr2 = ASMGetDR2();
541	pVCpu->cpum.s.Host.dr3 = ASMGetDR3();
542	#endif
543	pVCpu->cpum.s.Host.dr6 = ASMGetDR6();
544	/** @todo dr7 might already have been changed to 0x400; don't care right now as it's harmless. */
545	pVCpu->cpum.s.Host.dr7 = ASMGetDR7();
546
547	/* Preemption paranoia. */
548	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HOST);
549
550	/*
551	* Make sure DR7 is harmless or else we could trigger breakpoints when
552	* load guest or hypervisor DRx values later.
553	*/
554	if (pVCpu->cpum.s.Host.dr7 != X86_DR7_INIT_VAL)
555	ASMSetDR7(X86_DR7_INIT_VAL);
556
557	return VINF_SUCCESS;
558	}
559
560
561	/**
562	* Saves the guest DRx state residing in host registers and restore the host
563	* register values.
564	*
565	* The guest DRx state is only saved if CPUMR0LoadGuestDebugState was called,
566	* since it's assumed that we're shadowing the guest DRx register values
567	* accurately when using the combined hypervisor debug register values
568	* (CPUMR0LoadHyperDebugState).
569	*
570	* @returns true if either guest or hypervisor debug registers were loaded.
571	* @param pVCpu The cross context CPU structure for the calling EMT.
572	* @param fDr6 Whether to include DR6 or not.
573	* @thread EMT(pVCpu)
574	*/
575	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(PVMCPU pVCpu, bool fDr6)
576	{
577	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
578	bool const fDrXLoaded = RT_BOOL(pVCpu->cpum.s.fUseFlags & (CPUM_USED_DEBUG_REGS_GUEST \| CPUM_USED_DEBUG_REGS_HYPER));
579
580	/*
581	* Do we need to save the guest DRx registered loaded into host registers?
582	* (DR7 and DR6 (if fDr6 is true) are left to the caller.)
583	*/
584	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST)
585	{
586	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
587	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
588	{
589	uint64_t uDr6 = pVCpu->cpum.s.Guest.dr[6];
590	HMR0SaveDebugState(pVCpu->CTX_SUFF(pVM), pVCpu, &pVCpu->cpum.s.Guest);
591	if (!fDr6)
592	pVCpu->cpum.s.Guest.dr[6] = uDr6;
593	}
594	else
595	#endif
596	{
597	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
598	cpumR0SaveDRx(&pVCpu->cpum.s.Guest.dr[0]);
599	#else
600	pVCpu->cpum.s.Guest.dr[0] = ASMGetDR0();
601	pVCpu->cpum.s.Guest.dr[1] = ASMGetDR1();
602	pVCpu->cpum.s.Guest.dr[2] = ASMGetDR2();
603	pVCpu->cpum.s.Guest.dr[3] = ASMGetDR3();
604	#endif
605	if (fDr6)
606	pVCpu->cpum.s.Guest.dr[6] = ASMGetDR6();
607	}
608	}
609	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~( CPUM_USED_DEBUG_REGS_GUEST \| CPUM_USED_DEBUG_REGS_HYPER
610	\| CPUM_SYNC_DEBUG_REGS_GUEST \| CPUM_SYNC_DEBUG_REGS_HYPER));
611
612	/*
613	* Restore the host's debug state. DR0-3, DR6 and only then DR7!
614	*/
615	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HOST)
616	{
617	/* A bit of paranoia first... */
618	uint64_t uCurDR7 = ASMGetDR7();
619	if (uCurDR7 != X86_DR7_INIT_VAL)
620	ASMSetDR7(X86_DR7_INIT_VAL);
621
622	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
623	AssertCompile((uintptr_t)&pVCpu->cpum.s.Host.dr3 - (uintptr_t)&pVCpu->cpum.s.Host.dr0 == sizeof(uint64_t) * 3);
624	cpumR0LoadDRx(&pVCpu->cpum.s.Host.dr0);
625	#else
626	ASMSetDR0(pVCpu->cpum.s.Host.dr0);
627	ASMSetDR1(pVCpu->cpum.s.Host.dr1);
628	ASMSetDR2(pVCpu->cpum.s.Host.dr2);
629	ASMSetDR3(pVCpu->cpum.s.Host.dr3);
630	#endif
631	/** @todo consider only updating if they differ, esp. DR6. Need to figure how
632	* expensive DRx reads are over DRx writes. */
633	ASMSetDR6(pVCpu->cpum.s.Host.dr6);
634	ASMSetDR7(pVCpu->cpum.s.Host.dr7);
635
636	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_HOST);
637	}
638
639	return fDrXLoaded;
640	}
641
642
643	/**
644	* Saves the guest DRx state if it resides host registers.
645	*
646	* This does NOT clear any use flags, so the host registers remains loaded with
647	* the guest DRx state upon return. The purpose is only to make sure the values
648	* in the CPU context structure is up to date.
649	*
650	* @returns true if the host registers contains guest values, false if not.
651	* @param pVCpu The cross context CPU structure for the calling EMT.
652	* @param fDr6 Whether to include DR6 or not.
653	* @thread EMT(pVCpu)
654	*/
655	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuest(PVMCPU pVCpu, bool fDr6)
656	{
657	/*
658	* Do we need to save the guest DRx registered loaded into host registers?
659	* (DR7 and DR6 (if fDr6 is true) are left to the caller.)
660	*/
661	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST)
662	{
663	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
664	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
665	{
666	uint64_t uDr6 = pVCpu->cpum.s.Guest.dr[6];
667	HMR0SaveDebugState(pVCpu->CTX_SUFF(pVM), pVCpu, &pVCpu->cpum.s.Guest);
668	if (!fDr6)
669	pVCpu->cpum.s.Guest.dr[6] = uDr6;
670	}
671	else
672	#endif
673	{
674	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
675	cpumR0SaveDRx(&pVCpu->cpum.s.Guest.dr[0]);
676	#else
677	pVCpu->cpum.s.Guest.dr[0] = ASMGetDR0();
678	pVCpu->cpum.s.Guest.dr[1] = ASMGetDR1();
679	pVCpu->cpum.s.Guest.dr[2] = ASMGetDR2();
680	pVCpu->cpum.s.Guest.dr[3] = ASMGetDR3();
681	#endif
682	if (fDr6)
683	pVCpu->cpum.s.Guest.dr[6] = ASMGetDR6();
684	}
685	return true;
686	}
687	return false;
688	}
689
690
691	/**
692	* Lazily sync in the debug state.
693	*
694	* @param pVCpu The cross context CPU structure for the calling EMT.
695	* @param fDr6 Whether to include DR6 or not.
696	* @thread EMT(pVCpu)
697	*/
698	VMMR0_INT_DECL(void) CPUMR0LoadGuestDebugState(PVMCPU pVCpu, bool fDr6)
699	{
700	/*
701	* Save the host state and disarm all host BPs.
702	*/
703	cpumR0SaveHostDebugState(pVCpu);
704	Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
705
706	/*
707	* Activate the guest state DR0-3.
708	* DR7 and DR6 (if fDr6 is true) are left to the caller.
709	*/
710	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
711	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
712	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_SYNC_DEBUG_REGS_GUEST); /* Postpone it to the world switch. */
713	else
714	#endif
715	{
716	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
717	cpumR0LoadDRx(&pVCpu->cpum.s.Guest.dr[0]);
718	#else
719	ASMSetDR0(pVCpu->cpum.s.Guest.dr[0]);
720	ASMSetDR1(pVCpu->cpum.s.Guest.dr[1]);
721	ASMSetDR2(pVCpu->cpum.s.Guest.dr[2]);
722	ASMSetDR3(pVCpu->cpum.s.Guest.dr[3]);
723	#endif
724	if (fDr6)
725	ASMSetDR6(pVCpu->cpum.s.Guest.dr[6]);
726
727	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_GUEST);
728	}
729	}
730
731
732	/**
733	* Lazily sync in the hypervisor debug state
734	*
735	* @returns VBox status code.
736	* @param pVCpu The cross context CPU structure for the calling EMT.
737	* @param fDr6 Whether to include DR6 or not.
738	* @thread EMT(pVCpu)
739	*/
740	VMMR0_INT_DECL(void) CPUMR0LoadHyperDebugState(PVMCPU pVCpu, bool fDr6)
741	{
742	/*
743	* Save the host state and disarm all host BPs.
744	*/
745	cpumR0SaveHostDebugState(pVCpu);
746	Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
747
748	/*
749	* Make sure the hypervisor values are up to date.
750	*/
751	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX /* no loading, please */, true);
752
753	/*
754	* Activate the guest state DR0-3.
755	* DR7 and DR6 (if fDr6 is true) are left to the caller.
756	*/
757	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
758	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
759	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_SYNC_DEBUG_REGS_HYPER); /* Postpone it. */
760	else
761	#endif
762	{
763	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
764	cpumR0LoadDRx(&pVCpu->cpum.s.Hyper.dr[0]);
765	#else
766	ASMSetDR0(pVCpu->cpum.s.Hyper.dr[0]);
767	ASMSetDR1(pVCpu->cpum.s.Hyper.dr[1]);
768	ASMSetDR2(pVCpu->cpum.s.Hyper.dr[2]);
769	ASMSetDR3(pVCpu->cpum.s.Hyper.dr[3]);
770	#endif
771	if (fDr6)
772	ASMSetDR6(X86_DR6_INIT_VAL);
773
774	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HYPER);
775	}
776	}
777
778	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
779
780	/**
781	* Per-CPU callback that probes the CPU for APIC support.
782	*
783	* @param idCpu The identifier for the CPU the function is called on.
784	* @param pvUser1 Ignored.
785	* @param pvUser2 Ignored.
786	*/
787	static DECLCALLBACK(void) cpumR0MapLocalApicCpuProber(RTCPUID idCpu, void pvUser1, void pvUser2)
788	{
789	NOREF(pvUser1); NOREF(pvUser2);
790	int iCpu = RTMpCpuIdToSetIndex(idCpu);
791	AssertReturnVoid(iCpu >= 0 && (unsigned)iCpu < RT_ELEMENTS(g_aLApics));
792
793	/*
794	* Check for APIC support.
795	*/
796	uint32_t uMaxLeaf, u32EBX, u32ECX, u32EDX;
797	ASMCpuId(0, &uMaxLeaf, &u32EBX, &u32ECX, &u32EDX);
798	if ( ( ASMIsIntelCpuEx(u32EBX, u32ECX, u32EDX)
799	\|\| ASMIsAmdCpuEx(u32EBX, u32ECX, u32EDX)
800	\|\| ASMIsViaCentaurCpuEx(u32EBX, u32ECX, u32EDX))
801	&& ASMIsValidStdRange(uMaxLeaf))
802	{
803	uint32_t uDummy;
804	ASMCpuId(1, &uDummy, &u32EBX, &u32ECX, &u32EDX);
805	if ( (u32EDX & X86_CPUID_FEATURE_EDX_APIC)
806	&& (u32EDX & X86_CPUID_FEATURE_EDX_MSR))
807	{
808	/*
809	* Safe to access the MSR. Read it and calc the BASE (a little complicated).
810	*/
811	uint64_t u64ApicBase = ASMRdMsr(MSR_IA32_APICBASE);
812	uint64_t u64Mask = MSR_IA32_APICBASE_BASE_MIN;
813
814	/* see Intel Manual: Local APIC Status and Location: MAXPHYADDR default is bit 36 */
815	uint32_t uMaxExtLeaf;
816	ASMCpuId(0x80000000, &uMaxExtLeaf, &u32EBX, &u32ECX, &u32EDX);
817	if ( uMaxExtLeaf >= UINT32_C(0x80000008)
818	&& ASMIsValidExtRange(uMaxExtLeaf))
819	{
820	uint32_t u32PhysBits;
821	ASMCpuId(0x80000008, &u32PhysBits, &u32EBX, &u32ECX, &u32EDX);
822	u32PhysBits &= 0xff;
823	u64Mask = ((UINT64_C(1) << u32PhysBits) - 1) & UINT64_C(0xfffffffffffff000);
824	}
825
826	AssertCompile(sizeof(g_aLApics[iCpu].PhysBase) == sizeof(u64ApicBase));
827	g_aLApics[iCpu].PhysBase = u64ApicBase & u64Mask;
828	g_aLApics[iCpu].fEnabled = RT_BOOL(u64ApicBase & MSR_IA32_APICBASE_EN);
829	g_aLApics[iCpu].fX2Apic = (u64ApicBase & (MSR_IA32_APICBASE_EXTD \| MSR_IA32_APICBASE_EN))
830	== (MSR_IA32_APICBASE_EXTD \| MSR_IA32_APICBASE_EN);
831	}
832	}
833	}
834
835
836
837	/**
838	* Per-CPU callback that verifies our APIC expectations.
839	*
840	* @param idCpu The identifier for the CPU the function is called on.
841	* @param pvUser1 Ignored.
842	* @param pvUser2 Ignored.
843	*/
844	static DECLCALLBACK(void) cpumR0MapLocalApicCpuChecker(RTCPUID idCpu, void pvUser1, void pvUser2)
845	{
846	NOREF(pvUser1); NOREF(pvUser2);
847
848	int iCpu = RTMpCpuIdToSetIndex(idCpu);
849	AssertReturnVoid(iCpu >= 0 && (unsigned)iCpu < RT_ELEMENTS(g_aLApics));
850	if (!g_aLApics[iCpu].fEnabled)
851	return;
852
853	/*
854	* 0x0X 82489 external APIC
855	* 0x1X Local APIC
856	* 0x2X..0xFF reserved
857	*/
858	uint32_t uApicVersion;
859	if (g_aLApics[iCpu].fX2Apic)
860	uApicVersion = ApicX2RegRead32(APIC_REG_VERSION);
861	else
862	uApicVersion = ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_VERSION);
863	if ((APIC_REG_VERSION_GET_VER(uApicVersion) & 0xF0) == 0x10)
864	{
865	g_aLApics[iCpu].uVersion = uApicVersion;
866
867	#if 0 /* enable if you need it. */
868	if (g_aLApics[iCpu].fX2Apic)
869	SUPR0Printf("CPUM: X2APIC %02u - ver %#010x, lint0=%#07x lint1=%#07x pc=%#07x thmr=%#07x cmci=%#07x\n",
870	iCpu, uApicVersion,
871	ApicX2RegRead32(APIC_REG_LVT_LINT0), ApicX2RegRead32(APIC_REG_LVT_LINT1),
872	ApicX2RegRead32(APIC_REG_LVT_PC), ApicX2RegRead32(APIC_REG_LVT_THMR),
873	ApicX2RegRead32(APIC_REG_LVT_CMCI));
874	else
875	{
876	SUPR0Printf("CPUM: APIC %02u at %RGp (mapped at %p) - ver %#010x, lint0=%#07x lint1=%#07x pc=%#07x thmr=%#07x cmci=%#07x\n",
877	iCpu, g_aLApics[iCpu].PhysBase, g_aLApics[iCpu].pv, uApicVersion,
878	ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_LINT0), ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_LINT1),
879	ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_PC), ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_THMR),
880	ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_CMCI));
881	if (uApicVersion & 0x80000000)
882	{
883	uint32_t uExtFeatures = ApicRegRead(g_aLApics[iCpu].pv, 0x400);
884	uint32_t cEiLvt = (uExtFeatures >> 16) & 0xff;
885	SUPR0Printf("CPUM: APIC %02u: ExtSpace available. extfeat=%08x eilvt[0..3]=%08x %08x %08x %08x\n",
886	iCpu,
887	ApicRegRead(g_aLApics[iCpu].pv, 0x400),
888	cEiLvt >= 1 ? ApicRegRead(g_aLApics[iCpu].pv, 0x500) : 0,
889	cEiLvt >= 2 ? ApicRegRead(g_aLApics[iCpu].pv, 0x510) : 0,
890	cEiLvt >= 3 ? ApicRegRead(g_aLApics[iCpu].pv, 0x520) : 0,
891	cEiLvt >= 4 ? ApicRegRead(g_aLApics[iCpu].pv, 0x530) : 0);
892	}
893	}
894	#endif
895	}
896	else
897	{
898	g_aLApics[iCpu].fEnabled = false;
899	g_aLApics[iCpu].fX2Apic = false;
900	SUPR0Printf("VBox/CPUM: Unsupported APIC version %#x (iCpu=%d)\n", uApicVersion, iCpu);
901	}
902	}
903
904
905	/**
906	* Map the MMIO page of each local APIC in the system.
907	*/
908	static int cpumR0MapLocalApics(void)
909	{
910	/*
911	* Check that we'll always stay within the array bounds.
912	*/
913	if (RTMpGetArraySize() > RT_ELEMENTS(g_aLApics))
914	{
915	LogRel(("CPUM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_aLApics)));
916	return VERR_TOO_MANY_CPUS;
917	}
918
919	/*
920	* Create mappings for all online CPUs we think have legacy APICs.
921	*/
922	int rc = RTMpOnAll(cpumR0MapLocalApicCpuProber, NULL, NULL);
923
924	for (unsigned iCpu = 0; RT_SUCCESS(rc) && iCpu < RT_ELEMENTS(g_aLApics); iCpu++)
925	{
926	if (g_aLApics[iCpu].fEnabled && !g_aLApics[iCpu].fX2Apic)
927	{
928	rc = RTR0MemObjEnterPhys(&g_aLApics[iCpu].hMemObj, g_aLApics[iCpu].PhysBase,
929	PAGE_SIZE, RTMEM_CACHE_POLICY_MMIO);
930	if (RT_SUCCESS(rc))
931	{
932	rc = RTR0MemObjMapKernel(&g_aLApics[iCpu].hMapObj, g_aLApics[iCpu].hMemObj, (void *)-1,
933	PAGE_SIZE, RTMEM_PROT_READ \| RTMEM_PROT_WRITE);
934	if (RT_SUCCESS(rc))
935	{
936	g_aLApics[iCpu].pv = RTR0MemObjAddress(g_aLApics[iCpu].hMapObj);
937	continue;
938	}
939	RTR0MemObjFree(g_aLApics[iCpu].hMemObj, true /* fFreeMappings */);
940	}
941	g_aLApics[iCpu].fEnabled = false;
942	}
943	g_aLApics[iCpu].pv = NULL;
944	}
945
946	/*
947	* Check the APICs.
948	*/
949	if (RT_SUCCESS(rc))
950	rc = RTMpOnAll(cpumR0MapLocalApicCpuChecker, NULL, NULL);
951
952	if (RT_FAILURE(rc))
953	{
954	cpumR0UnmapLocalApics();
955	return rc;
956	}
957
958	#ifdef LOG_ENABLED
959	/*
960	* Log the result (pretty useless, requires enabling CPUM in VBoxDrv
961	* and !VBOX_WITH_R0_LOGGING).
962	*/
963	if (LogIsEnabled())
964	{
965	uint32_t cEnabled = 0;
966	uint32_t cX2Apics = 0;
967	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_aLApics); iCpu++)
968	if (g_aLApics[iCpu].fEnabled)
969	{
970	cEnabled++;
971	cX2Apics += g_aLApics[iCpu].fX2Apic;
972	}
973	Log(("CPUM: %u APICs, %u X2APICs\n", cEnabled, cX2Apics));
974	}
975	#endif
976
977	return VINF_SUCCESS;
978	}
979
980
981	/**
982	* Unmap the Local APIC of all host CPUs.
983	*/
984	static void cpumR0UnmapLocalApics(void)
985	{
986	for (unsigned iCpu = RT_ELEMENTS(g_aLApics); iCpu-- > 0;)
987	{
988	if (g_aLApics[iCpu].pv)
989	{
990	RTR0MemObjFree(g_aLApics[iCpu].hMapObj, true /* fFreeMappings */);
991	RTR0MemObjFree(g_aLApics[iCpu].hMemObj, true /* fFreeMappings */);
992	g_aLApics[iCpu].hMapObj = NIL_RTR0MEMOBJ;
993	g_aLApics[iCpu].hMemObj = NIL_RTR0MEMOBJ;
994	g_aLApics[iCpu].fEnabled = false;
995	g_aLApics[iCpu].fX2Apic = false;
996	g_aLApics[iCpu].pv = NULL;
997	}
998	}
999	}
1000
1001
1002	/**
1003	* Updates CPUMCPU::pvApicBase and CPUMCPU::fX2Apic prior to world switch.
1004	*
1005	* Writes the Local APIC mapping address of the current host CPU to CPUMCPU so
1006	* the world switchers can access the APIC registers for the purpose of
1007	* disabling and re-enabling the NMIs. Must be called with disabled preemption
1008	* or disabled interrupts!
1009	*
1010	* @param pVCpu Pointer to the cross context CPU structure of the
1011	* calling EMT.
1012	* @param iHostCpuSet The CPU set index of the current host CPU.
1013	*/
1014	VMMR0_INT_DECL(void) CPUMR0SetLApic(PVMCPU pVCpu, uint32_t iHostCpuSet)
1015	{
1016	Assert(iHostCpuSet <= RT_ELEMENTS(g_aLApics));
1017	pVCpu->cpum.s.pvApicBase = g_aLApics[iHostCpuSet].pv;
1018	pVCpu->cpum.s.fX2Apic = g_aLApics[iHostCpuSet].fX2Apic;
1019	// Log6(("CPUMR0SetLApic: pvApicBase=%p fX2Apic=%d\n", g_aLApics[idxCpu].pv, g_aLApics[idxCpu].fX2Apic));
1020	}
1021
1022	#endif /* VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI */
1023

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