PGMAllShw.h@ 86453

最後變更在這個檔案從86453是 86453,由 vboxsync 提交於 4 年前
VMM/PGM: Workaround for buggy gcc (10.2.1) clearing high dword of PDE. bugref:9841
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1	/* $Id: PGMAllShw.h 86453 2020-10-05 17:42:00Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow Paging Template - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.alldomusa.eu.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Defined Constants And Macros *
21	*********************************************************************************************************************************/
22	#undef SHWPT
23	#undef PSHWPT
24	#undef SHWPTE
25	#undef PSHWPTE
26	#undef SHWPD
27	#undef PSHWPD
28	#undef SHWPDE
29	#undef PSHWPDE
30	#undef SHW_PDE_PG_MASK
31	#undef SHW_PD_SHIFT
32	#undef SHW_PD_MASK
33	#undef SHW_PDE_ATOMIC_SET
34	#undef SHW_PDE_ATOMIC_SET2
35	#undef SHW_PTE_PG_MASK
36	#undef SHW_PTE_IS_P
37	#undef SHW_PTE_IS_RW
38	#undef SHW_PTE_IS_US
39	#undef SHW_PTE_IS_A
40	#undef SHW_PTE_IS_D
41	#undef SHW_PTE_IS_P_RW
42	#undef SHW_PTE_IS_TRACK_DIRTY
43	#undef SHW_PTE_GET_HCPHYS
44	#undef SHW_PTE_GET_U
45	#undef SHW_PTE_LOG64
46	#undef SHW_PTE_SET
47	#undef SHW_PTE_ATOMIC_SET
48	#undef SHW_PTE_ATOMIC_SET2
49	#undef SHW_PTE_SET_RO
50	#undef SHW_PTE_SET_RW
51	#undef SHW_PT_SHIFT
52	#undef SHW_PT_MASK
53	#undef SHW_TOTAL_PD_ENTRIES
54	#undef SHW_PDPT_SHIFT
55	#undef SHW_PDPT_MASK
56	#undef SHW_PDPE_PG_MASK
57
58	#if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED_32BIT
59	# define SHWPT X86PT
60	# define PSHWPT PX86PT
61	# define SHWPTE X86PTE
62	# define PSHWPTE PX86PTE
63	# define SHWPD X86PD
64	# define PSHWPD PX86PD
65	# define SHWPDE X86PDE
66	# define PSHWPDE PX86PDE
67	# define SHW_PDE_PG_MASK X86_PDE_PG_MASK
68	# define SHW_PD_SHIFT X86_PD_SHIFT
69	# define SHW_PD_MASK X86_PD_MASK
70	# define SHW_TOTAL_PD_ENTRIES X86_PG_ENTRIES
71	# define SHW_PDE_ATOMIC_SET(Pde, uNew) do { ASMAtomicWriteU32(&(Pde).u, (uNew)); } while (0)
72	# define SHW_PDE_ATOMIC_SET2(Pde, Pde2) do { ASMAtomicWriteU32(&(Pde).u, (Pde2).u); } while (0)
73	# define SHW_PTE_PG_MASK X86_PTE_PG_MASK
74	# define SHW_PTE_IS_P(Pte) ( (Pte).n.u1Present )
75	# define SHW_PTE_IS_RW(Pte) ( (Pte).n.u1Write )
76	# define SHW_PTE_IS_US(Pte) ( (Pte).n.u1User )
77	# define SHW_PTE_IS_A(Pte) ( (Pte).n.u1Accessed )
78	# define SHW_PTE_IS_D(Pte) ( (Pte).n.u1Dirty )
79	# define SHW_PTE_IS_P_RW(Pte) ( (Pte).n.u1Present && (Pte).n.u1Write )
80	# define SHW_PTE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
81	# define SHW_PTE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PG_MASK )
82	# define SHW_PTE_LOG64(Pte) ( (uint64_t)(Pte).u )
83	# define SHW_PTE_GET_U(Pte) ( (Pte).u ) /*< Use with care. /
84	# define SHW_PTE_SET(Pte, uNew) do { (Pte).u = (uNew); } while (0)
85	# define SHW_PTE_ATOMIC_SET(Pte, uNew) do { ASMAtomicWriteU32(&(Pte).u, (uNew)); } while (0)
86	# define SHW_PTE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU32(&(Pte).u, (Pte2).u); } while (0)
87	# define SHW_PTE_SET_RO(Pte) do { (Pte).n.u1Write = 0; } while (0)
88	# define SHW_PTE_SET_RW(Pte) do { (Pte).n.u1Write = 1; } while (0)
89	# define SHW_PT_SHIFT X86_PT_SHIFT
90	# define SHW_PT_MASK X86_PT_MASK
91
92	#elif PGM_SHW_TYPE == PGM_TYPE_EPT
93	# define SHWPT EPTPT
94	# define PSHWPT PEPTPT
95	# define SHWPTE EPTPTE
96	# define PSHWPTE PEPTPTE
97	# define SHWPD EPTPD
98	# define PSHWPD PEPTPD
99	# define SHWPDE EPTPDE
100	# define PSHWPDE PEPTPDE
101	# define SHW_PDE_PG_MASK EPT_PDE_PG_MASK
102	# define SHW_PD_SHIFT EPT_PD_SHIFT
103	# define SHW_PD_MASK EPT_PD_MASK
104	# define SHW_PDE_ATOMIC_SET(Pde, uNew) do { ASMAtomicWriteU64(&(Pde).u, (uNew)); } while (0)
105	# define SHW_PDE_ATOMIC_SET2(Pde, Pde2) do { ASMAtomicWriteU64(&(Pde).u, (Pde2).u); } while (0)
106	# define SHW_PTE_PG_MASK EPT_PTE_PG_MASK
107	# define SHW_PTE_IS_P(Pte) ( (Pte).n.u1Present ) /* Approximation, works for us. */
108	# define SHW_PTE_IS_RW(Pte) ( (Pte).n.u1Write )
109	# define SHW_PTE_IS_US(Pte) ( true )
110	# define SHW_PTE_IS_A(Pte) ( true )
111	# define SHW_PTE_IS_D(Pte) ( true )
112	# define SHW_PTE_IS_P_RW(Pte) ( (Pte).n.u1Present && (Pte).n.u1Write )
113	# define SHW_PTE_IS_TRACK_DIRTY(Pte) ( false )
114	# define SHW_PTE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PG_MASK )
115	# define SHW_PTE_LOG64(Pte) ( (Pte).u )
116	# define SHW_PTE_GET_U(Pte) ( (Pte).u ) /*< Use with care. /
117	# define SHW_PTE_SET(Pte, uNew) do { (Pte).u = (uNew); } while (0)
118	# define SHW_PTE_ATOMIC_SET(Pte, uNew) do { ASMAtomicWriteU64(&(Pte).u, (uNew)); } while (0)
119	# define SHW_PTE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
120	# define SHW_PTE_SET_RO(Pte) do { (Pte).n.u1Write = 0; } while (0)
121	# define SHW_PTE_SET_RW(Pte) do { (Pte).n.u1Write = 1; } while (0)
122	# define SHW_PT_SHIFT EPT_PT_SHIFT
123	# define SHW_PT_MASK EPT_PT_MASK
124	# define SHW_PDPT_SHIFT EPT_PDPT_SHIFT
125	# define SHW_PDPT_MASK EPT_PDPT_MASK
126	# define SHW_PDPE_PG_MASK EPT_PDPE_PG_MASK
127	# define SHW_TOTAL_PD_ENTRIES (EPT_PG_AMD64_ENTRIES*EPT_PG_AMD64_PDPE_ENTRIES)
128
129	#else
130	# define SHWPT PGMSHWPTPAE
131	# define PSHWPT PPGMSHWPTPAE
132	# define SHWPTE PGMSHWPTEPAE
133	# define PSHWPTE PPGMSHWPTEPAE
134	# define SHWPD X86PDPAE
135	# define PSHWPD PX86PDPAE
136	# define SHWPDE X86PDEPAE
137	# define PSHWPDE PX86PDEPAE
138	# define SHW_PDE_PG_MASK X86_PDE_PAE_PG_MASK
139	# define SHW_PD_SHIFT X86_PD_PAE_SHIFT
140	# define SHW_PD_MASK X86_PD_PAE_MASK
141	# define SHW_PDE_ATOMIC_SET(Pde, uNew) do { ASMAtomicWriteU64(&(Pde).u, (uNew)); } while (0)
142	# define SHW_PDE_ATOMIC_SET2(Pde, Pde2) do { ASMAtomicWriteU64(&(Pde).u, (Pde2).u); } while (0)
143	# define SHW_PTE_PG_MASK X86_PTE_PAE_PG_MASK
144	# define SHW_PTE_IS_P(Pte) PGMSHWPTEPAE_IS_P(Pte)
145	# define SHW_PTE_IS_RW(Pte) PGMSHWPTEPAE_IS_RW(Pte)
146	# define SHW_PTE_IS_US(Pte) PGMSHWPTEPAE_IS_US(Pte)
147	# define SHW_PTE_IS_A(Pte) PGMSHWPTEPAE_IS_A(Pte)
148	# define SHW_PTE_IS_D(Pte) PGMSHWPTEPAE_IS_D(Pte)
149	# define SHW_PTE_IS_P_RW(Pte) PGMSHWPTEPAE_IS_P_RW(Pte)
150	# define SHW_PTE_IS_TRACK_DIRTY(Pte) PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte)
151	# define SHW_PTE_GET_HCPHYS(Pte) PGMSHWPTEPAE_GET_HCPHYS(Pte)
152	# define SHW_PTE_LOG64(Pte) PGMSHWPTEPAE_GET_LOG(Pte)
153	# define SHW_PTE_GET_U(Pte) PGMSHWPTEPAE_GET_U(Pte) /*< Use with care. /
154	# define SHW_PTE_SET(Pte, uNew) PGMSHWPTEPAE_SET(Pte, uNew)
155	# define SHW_PTE_ATOMIC_SET(Pte, uNew) PGMSHWPTEPAE_ATOMIC_SET(Pte, uNew)
156	# define SHW_PTE_ATOMIC_SET2(Pte, Pte2) PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2)
157	# define SHW_PTE_SET_RO(Pte) PGMSHWPTEPAE_SET_RO(Pte)
158	# define SHW_PTE_SET_RW(Pte) PGMSHWPTEPAE_SET_RW(Pte)
159	# define SHW_PT_SHIFT X86_PT_PAE_SHIFT
160	# define SHW_PT_MASK X86_PT_PAE_MASK
161
162	# if PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED_AMD64 \|\| /* whatever: */ PGM_SHW_TYPE == PGM_TYPE_NONE
163	# define SHW_PDPT_SHIFT X86_PDPT_SHIFT
164	# define SHW_PDPT_MASK X86_PDPT_MASK_AMD64
165	# define SHW_PDPE_PG_MASK X86_PDPE_PG_MASK
166	# define SHW_TOTAL_PD_ENTRIES (X86_PG_AMD64_ENTRIES * X86_PG_AMD64_PDPE_ENTRIES)
167
168	# elif PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED_PAE
169	# define SHW_PDPT_SHIFT X86_PDPT_SHIFT
170	# define SHW_PDPT_MASK X86_PDPT_MASK_PAE
171	# define SHW_PDPE_PG_MASK X86_PDPE_PG_MASK
172	# define SHW_TOTAL_PD_ENTRIES (X86_PG_PAE_ENTRIES * X86_PG_PAE_PDPE_ENTRIES)
173
174	# else
175	# error "Misconfigured PGM_SHW_TYPE or something..."
176	# endif
177	#endif
178
179	#if PGM_SHW_TYPE == PGM_TYPE_NONE && PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE)
180	# error "PGM_TYPE_IS_NESTED_OR_EPT is true for PGM_TYPE_NONE!"
181	#endif
182
183
184
185	/*********************************************************************************************************************************
186	* Internal Functions *
187	*********************************************************************************************************************************/
188	RT_C_DECLS_BEGIN
189	PGM_SHW_DECL(int, GetPage)(PVMCPUCC pVCpu, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
190	PGM_SHW_DECL(int, ModifyPage)(PVMCPUCC pVCpu, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags);
191	PGM_SHW_DECL(int, Enter)(PVMCPUCC pVCpu, bool fIs64BitsPagingMode);
192	PGM_SHW_DECL(int, Exit)(PVMCPUCC pVCpu);
193	#ifdef IN_RING3
194	PGM_SHW_DECL(int, Relocate)(PVMCPUCC pVCpu, RTGCPTR offDelta);
195	#endif
196	RT_C_DECLS_END
197
198
199	/**
200	* Enters the shadow mode.
201	*
202	* @returns VBox status code.
203	* @param pVCpu The cross context virtual CPU structure.
204	* @param fIs64BitsPagingMode New shadow paging mode is for 64 bits? (only relevant for 64 bits guests on a 32 bits AMD-V nested paging host)
205	*/
206	PGM_SHW_DECL(int, Enter)(PVMCPUCC pVCpu, bool fIs64BitsPagingMode)
207	{
208	#if PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE)
209
210	# if PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) && HC_ARCH_BITS == 32
211	/* Must distinguish between 32 and 64 bits guest paging modes as we'll use
212	a different shadow paging root/mode in both cases. */
213	RTGCPHYS GCPhysCR3 = (fIs64BitsPagingMode) ? RT_BIT_64(63) : RT_BIT_64(62);
214	# else
215	RTGCPHYS GCPhysCR3 = RT_BIT_64(63); NOREF(fIs64BitsPagingMode);
216	# endif
217	PPGMPOOLPAGE pNewShwPageCR3;
218	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
219
220	Assert((HMIsNestedPagingActive(pVM) \|\| VM_IS_NEM_ENABLED(pVM)) == pVM->pgm.s.fNestedPaging);
221	Assert(pVM->pgm.s.fNestedPaging);
222	Assert(!pVCpu->pgm.s.pShwPageCR3R3);
223
224	pgmLock(pVM);
225
226	int rc = pgmPoolAlloc(pVM, GCPhysCR3, PGMPOOLKIND_ROOT_NESTED, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
227	NIL_PGMPOOL_IDX, UINT32_MAX, true /fLockPage/,
228	&pNewShwPageCR3);
229	AssertLogRelRCReturnStmt(rc, pgmUnlock(pVM), rc);
230
231	pVCpu->pgm.s.pShwPageCR3R3 = (R3PTRTYPE(PPGMPOOLPAGE))MMHyperCCToR3(pVM, pNewShwPageCR3);
232	pVCpu->pgm.s.pShwPageCR3R0 = (R0PTRTYPE(PPGMPOOLPAGE))MMHyperCCToR0(pVM, pNewShwPageCR3);
233
234	pgmUnlock(pVM);
235
236	Log(("Enter nested shadow paging mode: root %RHv phys %RHp\n", pVCpu->pgm.s.pShwPageCR3R3, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key));
237	#else
238	NOREF(pVCpu); NOREF(fIs64BitsPagingMode);
239	#endif
240	return VINF_SUCCESS;
241	}
242
243
244	/**
245	* Exits the shadow mode.
246	*
247	* @returns VBox status code.
248	* @param pVCpu The cross context virtual CPU structure.
249	*/
250	PGM_SHW_DECL(int, Exit)(PVMCPUCC pVCpu)
251	{
252	#if PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE)
253	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
254	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
255	{
256	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
257
258	pgmLock(pVM);
259
260	/* Do not unlock this page as we have two of them floating around in the 32-bit host & 64-bit guest case.
261	* We currently assert when you try to free one of them; don't bother to really allow this.
262	*
263	* Note that this is two nested paging root pages max. This isn't a leak. They are reused.
264	*/
265	/* pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)); */
266
267	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), NIL_PGMPOOL_IDX, UINT32_MAX);
268	pVCpu->pgm.s.pShwPageCR3R3 = 0;
269	pVCpu->pgm.s.pShwPageCR3R0 = 0;
270
271	pgmUnlock(pVM);
272
273	Log(("Leave nested shadow paging mode\n"));
274	}
275	#else
276	RT_NOREF_PV(pVCpu);
277	#endif
278	return VINF_SUCCESS;
279	}
280
281
282	/**
283	* Gets effective page information (from the VMM page directory).
284	*
285	* @returns VBox status code.
286	* @param pVCpu The cross context virtual CPU structure.
287	* @param GCPtr Guest Context virtual address of the page.
288	* @param pfFlags Where to store the flags. These are X86_PTE_*.
289	* @param pHCPhys Where to store the HC physical address of the page.
290	* This is page aligned.
291	* @remark You should use PGMMapGetPage() for pages in a mapping.
292	*/
293	PGM_SHW_DECL(int, GetPage)(PVMCPUCC pVCpu, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
294	{
295	#if PGM_SHW_TYPE == PGM_TYPE_NONE
296	RT_NOREF(pVCpu, GCPtr);
297	AssertFailed();
298	*pfFlags = 0;
299	*pHCPhys = NIL_RTHCPHYS;
300	return VERR_PGM_SHW_NONE_IPE;
301
302	#else /* PGM_SHW_TYPE != PGM_TYPE_NONE */
303	PVM pVM = pVCpu->CTX_SUFF(pVM);
304
305	PGM_LOCK_ASSERT_OWNER(pVM);
306
307	/*
308	* Get the PDE.
309	*/
310	# if PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED_AMD64
311	X86PDEPAE Pde;
312
313	/* PML4 */
314	X86PML4E Pml4e = pgmShwGetLongModePML4E(pVCpu, GCPtr);
315	if (!Pml4e.n.u1Present)
316	return VERR_PAGE_TABLE_NOT_PRESENT;
317
318	/* PDPT */
319	PX86PDPT pPDPT;
320	int rc = PGM_HCPHYS_2_PTR(pVM, pVCpu, Pml4e.u & X86_PML4E_PG_MASK, &pPDPT);
321	if (RT_FAILURE(rc))
322	return rc;
323	const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
324	X86PDPE Pdpe = pPDPT->a[iPDPT];
325	if (!Pdpe.n.u1Present)
326	return VERR_PAGE_TABLE_NOT_PRESENT;
327
328	/* PD */
329	PX86PDPAE pPd;
330	rc = PGM_HCPHYS_2_PTR(pVM, pVCpu, Pdpe.u & X86_PDPE_PG_MASK, &pPd);
331	if (RT_FAILURE(rc))
332	return rc;
333	const unsigned iPd = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
334	Pde = pPd->a[iPd];
335
336	/* Merge accessed, write, user and no-execute bits into the PDE. */
337	Pde.n.u1Accessed &= Pml4e.n.u1Accessed & Pdpe.lm.u1Accessed;
338	Pde.n.u1Write &= Pml4e.n.u1Write & Pdpe.lm.u1Write;
339	Pde.n.u1User &= Pml4e.n.u1User & Pdpe.lm.u1User;
340	Pde.n.u1NoExecute \|= Pml4e.n.u1NoExecute \| Pdpe.lm.u1NoExecute;
341
342	# elif PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED_PAE
343	X86PDEPAE Pde = pgmShwGetPaePDE(pVCpu, GCPtr);
344
345	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
346	const unsigned iPd = ((GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK);
347	PEPTPD pPDDst;
348	EPTPDE Pde;
349
350	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtr, NULL, &pPDDst);
351	if (rc != VINF_SUCCESS) /** @todo this function isn't expected to return informational status codes. Check callers / fix. */
352	{
353	AssertRC(rc);
354	return rc;
355	}
356	Assert(pPDDst);
357	Pde = pPDDst->a[iPd];
358
359	# elif PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED_32BIT
360	X86PDE Pde = pgmShwGet32BitPDE(pVCpu, GCPtr);
361	# else
362	# error "Misconfigured PGM_SHW_TYPE or something..."
363	# endif
364	if (!Pde.n.u1Present)
365	return VERR_PAGE_TABLE_NOT_PRESENT;
366
367	/* Deal with large pages. */
368	if (Pde.b.u1Size)
369	{
370	/*
371	* Store the results.
372	* RW and US flags depend on the entire page translation hierarchy - except for
373	* legacy PAE which has a simplified PDPE.
374	*/
375	if (pfFlags)
376	{
377	*pfFlags = (Pde.u & ~SHW_PDE_PG_MASK);
378	# if PGM_WITH_NX(PGM_SHW_TYPE, PGM_SHW_TYPE) \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED_AMD64
379	if ( (Pde.u & X86_PTE_PAE_NX)
380	# if PGM_WITH_NX(PGM_SHW_TYPE, PGM_SHW_TYPE)
381	&& CPUMIsGuestNXEnabled(pVCpu) /** @todo why do we have to check the guest state here? */
382	# endif
383	)
384	*pfFlags \|= X86_PTE_PAE_NX;
385	# endif
386	}
387
388	if (pHCPhys)
389	*pHCPhys = (Pde.u & SHW_PDE_PG_MASK) + (GCPtr & (RT_BIT(SHW_PD_SHIFT) - 1) & X86_PAGE_4K_BASE_MASK);
390
391	return VINF_SUCCESS;
392	}
393
394	/*
395	* Get PT entry.
396	*/
397	PSHWPT pPT;
398	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
399	{
400	int rc2 = PGM_HCPHYS_2_PTR(pVM, pVCpu, Pde.u & SHW_PDE_PG_MASK, &pPT);
401	if (RT_FAILURE(rc2))
402	return rc2;
403	}
404	else /* mapping: */
405	{
406	# if PGM_SHW_TYPE == PGM_TYPE_AMD64 \
407	\|\| PGM_SHW_TYPE == PGM_TYPE_EPT \
408	\|\| defined(PGM_WITHOUT_MAPPINGS)
409	AssertFailed(); /* can't happen */
410	pPT = NULL; /* shut up MSC */
411	# else
412	Assert(pgmMapAreMappingsEnabled(pVM));
413
414	PPGMMAPPING pMap = pgmGetMapping(pVM, (RTGCPTR)GCPtr);
415	AssertMsgReturn(pMap, ("GCPtr=%RGv\n", GCPtr), VERR_PGM_MAPPING_IPE);
416	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED_32BIT
417	pPT = pMap->aPTs[(GCPtr - pMap->GCPtr) >> X86_PD_SHIFT].CTX_SUFF(pPT);
418	# else /* PAE */
419	pPT = pMap->aPTs[(GCPtr - pMap->GCPtr) >> X86_PD_SHIFT].CTX_SUFF(paPaePTs);
420	# endif
421	# endif
422	}
423	const unsigned iPt = (GCPtr >> SHW_PT_SHIFT) & SHW_PT_MASK;
424	SHWPTE Pte = pPT->a[iPt];
425	if (!SHW_PTE_IS_P(Pte))
426	return VERR_PAGE_NOT_PRESENT;
427
428	/*
429	* Store the results.
430	* RW and US flags depend on the entire page translation hierarchy - except for
431	* legacy PAE which has a simplified PDPE.
432	*/
433	if (pfFlags)
434	{
435	*pfFlags = (SHW_PTE_GET_U(Pte) & ~SHW_PTE_PG_MASK)
436	& ((Pde.u & (X86_PTE_RW \| X86_PTE_US)) \| ~(uint64_t)(X86_PTE_RW \| X86_PTE_US));
437
438	# if PGM_WITH_NX(PGM_SHW_TYPE, PGM_SHW_TYPE) \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED_AMD64
439	/* The NX bit is determined by a bitwise OR between the PT and PD */
440	if ( ((SHW_PTE_GET_U(Pte) \| Pde.u) & X86_PTE_PAE_NX)
441	# if PGM_WITH_NX(PGM_SHW_TYPE, PGM_SHW_TYPE)
442	&& CPUMIsGuestNXEnabled(pVCpu) /** @todo why do we have to check the guest state here? */
443	# endif
444	)
445	*pfFlags \|= X86_PTE_PAE_NX;
446	# endif
447	}
448
449	if (pHCPhys)
450	*pHCPhys = SHW_PTE_GET_HCPHYS(Pte);
451
452	return VINF_SUCCESS;
453	#endif /* PGM_SHW_TYPE != PGM_TYPE_NONE */
454	}
455
456
457	/**
458	* Modify page flags for a range of pages in the shadow context.
459	*
460	* The existing flags are ANDed with the fMask and ORed with the fFlags.
461	*
462	* @returns VBox status code.
463	* @param pVCpu The cross context virtual CPU structure.
464	* @param GCPtr Virtual address of the first page in the range. Page aligned!
465	* @param cb Size (in bytes) of the range to apply the modification to. Page aligned!
466	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
467	* @param fMask The AND mask - page flags X86_PTE_*.
468	* Be extremely CAREFUL with ~'ing values because they can be 32-bit!
469	* @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
470	* @remark You must use PGMMapModifyPage() for pages in a mapping.
471	*/
472	PGM_SHW_DECL(int, ModifyPage)(PVMCPUCC pVCpu, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags)
473	{
474	#if PGM_SHW_TYPE == PGM_TYPE_NONE
475	RT_NOREF(pVCpu, GCPtr, cb, fFlags, fMask, fOpFlags);
476	AssertFailed();
477	return VERR_PGM_SHW_NONE_IPE;
478
479	#else /* PGM_SHW_TYPE != PGM_TYPE_NONE */
480	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
481	PGM_LOCK_ASSERT_OWNER(pVM);
482
483	/*
484	* Walk page tables and pages till we're done.
485	*/
486	int rc;
487	for (;;)
488	{
489	/*
490	* Get the PDE.
491	*/
492	# if PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED_AMD64
493	X86PDEPAE Pde;
494	/* PML4 */
495	X86PML4E Pml4e = pgmShwGetLongModePML4E(pVCpu, GCPtr);
496	if (!Pml4e.n.u1Present)
497	return VERR_PAGE_TABLE_NOT_PRESENT;
498
499	/* PDPT */
500	PX86PDPT pPDPT;
501	rc = PGM_HCPHYS_2_PTR(pVM, pVCpu, Pml4e.u & X86_PML4E_PG_MASK, &pPDPT);
502	if (RT_FAILURE(rc))
503	return rc;
504	const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
505	X86PDPE Pdpe = pPDPT->a[iPDPT];
506	if (!Pdpe.n.u1Present)
507	return VERR_PAGE_TABLE_NOT_PRESENT;
508
509	/* PD */
510	PX86PDPAE pPd;
511	rc = PGM_HCPHYS_2_PTR(pVM, pVCpu, Pdpe.u & X86_PDPE_PG_MASK, &pPd);
512	if (RT_FAILURE(rc))
513	return rc;
514	const unsigned iPd = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
515	Pde = pPd->a[iPd];
516
517	# elif PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED_PAE
518	X86PDEPAE Pde = pgmShwGetPaePDE(pVCpu, GCPtr);
519
520	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
521	const unsigned iPd = ((GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK);
522	PEPTPD pPDDst;
523	EPTPDE Pde;
524
525	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtr, NULL, &pPDDst);
526	if (rc != VINF_SUCCESS)
527	{
528	AssertRC(rc);
529	return rc;
530	}
531	Assert(pPDDst);
532	Pde = pPDDst->a[iPd];
533
534	# else /* PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED_32BIT */
535	X86PDE Pde = pgmShwGet32BitPDE(pVCpu, GCPtr);
536	# endif
537	if (!Pde.n.u1Present)
538	return VERR_PAGE_TABLE_NOT_PRESENT;
539
540	AssertFatal(!Pde.b.u1Size);
541
542	/*
543	* Map the page table.
544	*/
545	PSHWPT pPT;
546	rc = PGM_HCPHYS_2_PTR(pVM, pVCpu, Pde.u & SHW_PDE_PG_MASK, &pPT);
547	if (RT_FAILURE(rc))
548	return rc;
549
550	unsigned iPTE = (GCPtr >> SHW_PT_SHIFT) & SHW_PT_MASK;
551	while (iPTE < RT_ELEMENTS(pPT->a))
552	{
553	if (SHW_PTE_IS_P(pPT->a[iPTE]))
554	{
555	SHWPTE const OrgPte = pPT->a[iPTE];
556	SHWPTE NewPte;
557
558	SHW_PTE_SET(NewPte, (SHW_PTE_GET_U(OrgPte) & (fMask \| SHW_PTE_PG_MASK)) \| (fFlags & ~SHW_PTE_PG_MASK));
559	if (!SHW_PTE_IS_P(NewPte))
560	{
561	/** @todo Some CSAM code path might end up here and upset
562	* the page pool. */
563	AssertFailed();
564	}
565	else if ( SHW_PTE_IS_RW(NewPte)
566	&& !SHW_PTE_IS_RW(OrgPte)
567	&& !(fOpFlags & PGM_MK_PG_IS_MMIO2) )
568	{
569	/** @todo Optimize \#PF handling by caching data. We can
570	* then use this when PGM_MK_PG_IS_WRITE_FAULT is
571	* set instead of resolving the guest physical
572	* address yet again. */
573	RTGCPHYS GCPhys;
574	uint64_t fGstPte;
575	rc = PGMGstGetPage(pVCpu, GCPtr, &fGstPte, &GCPhys);
576	AssertRC(rc);
577	if (RT_SUCCESS(rc))
578	{
579	Assert((fGstPte & X86_PTE_RW) \|\| !(CPUMGetGuestCR0(pVCpu) & X86_CR0_WP /* allow netware hack */));
580	PPGMPAGE pPage = pgmPhysGetPage(pVM, GCPhys);
581	Assert(pPage);
582	if (pPage)
583	{
584	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
585	AssertRCReturn(rc, rc);
586	Log(("%s: pgmPhysPageMakeWritable on %RGv / %RGp %R[pgmpage]\n", __PRETTY_FUNCTION__, GCPtr, GCPhys, pPage));
587	}
588	}
589	}
590
591	SHW_PTE_ATOMIC_SET2(pPT->a[iPTE], NewPte);
592	# if PGM_SHW_TYPE == PGM_TYPE_EPT
593	HMInvalidatePhysPage(pVM, (RTGCPHYS)GCPtr);
594	# else
595	PGM_INVL_PG_ALL_VCPU(pVM, GCPtr);
596	# endif
597	}
598
599	/* next page */
600	cb -= PAGE_SIZE;
601	if (!cb)
602	return VINF_SUCCESS;
603	GCPtr += PAGE_SIZE;
604	iPTE++;
605	}
606	}
607	#endif /* PGM_SHW_TYPE != PGM_TYPE_NONE */
608	}
609
610
611	#ifdef IN_RING3
612	/**
613	* Relocate any GC pointers related to shadow mode paging.
614	*
615	* @returns VBox status code.
616	* @param pVCpu The cross context virtual CPU structure.
617	* @param offDelta The relocation offset.
618	*/
619	PGM_SHW_DECL(int, Relocate)(PVMCPUCC pVCpu, RTGCPTR offDelta)
620	{
621	RT_NOREF(pVCpu, offDelta);
622	return VINF_SUCCESS;
623	}
624	#endif
625

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllShw.h@ 86453

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