PGMAllPool.cpp@ 55331

最後變更在這個檔案從55331是 55331,由 vboxsync 提交於 10 年前
PGMHandlerPhysicalChangeCallbacks -> PGMHandlerPhysicalChangeUserArgs.
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1	/* $Id: PGMAllPool.cpp 55331 2015-04-17 13:38:38Z vboxsync $ */
2	/** @file
3	* PGM Shadow Page Pool.
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.alldomusa.eu.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_PGM_POOL
23	#include <VBox/vmm/pgm.h>
24	#include <VBox/vmm/mm.h>
25	#include <VBox/vmm/em.h>
26	#include <VBox/vmm/cpum.h>
27	#ifdef IN_RC
28	# include <VBox/vmm/patm.h>
29	#endif
30	#include "PGMInternal.h"
31	#include <VBox/vmm/vm.h>
32	#include "PGMInline.h"
33	#include <VBox/disopcode.h>
34	#include <VBox/vmm/hm_vmx.h>
35
36	#include <VBox/log.h>
37	#include <VBox/err.h>
38	#include <iprt/asm.h>
39	#include <iprt/asm-amd64-x86.h>
40	#include <iprt/string.h>
41
42
43	/*******************************************************************************
44	* Internal Functions *
45	*******************************************************************************/
46	RT_C_DECLS_BEGIN
47	DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind);
48	DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind);
49	static void pgmPoolTrackClearPageUsers(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
50	static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
51	static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
52	static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
53	#ifndef IN_RING3
54	DECLEXPORT(int) pgmPoolAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
55	#endif
56	#if defined(LOG_ENABLED) \|\| defined(VBOX_STRICT)
57	static const char *pgmPoolPoolKindToStr(uint8_t enmKind);
58	#endif
59	#if 0 /defined(VBOX_STRICT) && defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT)/
60	static void pgmPoolTrackCheckPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PTPAE pGstPT);
61	#endif
62
63	int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
64	PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
65	void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
66	void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
67
68	RT_C_DECLS_END
69
70
71	/**
72	* Checks if the specified page pool kind is for a 4MB or 2MB guest page.
73	*
74	* @returns true if it's the shadow of a 4MB or 2MB guest page, otherwise false.
75	* @param enmKind The page kind.
76	*/
77	DECLINLINE(bool) pgmPoolIsBigPage(PGMPOOLKIND enmKind)
78	{
79	switch (enmKind)
80	{
81	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
82	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
83	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
84	return true;
85	default:
86	return false;
87	}
88	}
89
90
91	/**
92	* Flushes a chain of pages sharing the same access monitor.
93	*
94	* @returns VBox status code suitable for scheduling.
95	* @param pPool The pool.
96	* @param pPage A page in the chain.
97	* @todo VBOXSTRICTRC
98	*/
99	int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
100	{
101	LogFlow(("pgmPoolMonitorChainFlush: Flush page %RGp type=%d\n", pPage->GCPhys, pPage->enmKind));
102
103	/*
104	* Find the list head.
105	*/
106	uint16_t idx = pPage->idx;
107	if (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
108	{
109	while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
110	{
111	idx = pPage->iMonitoredPrev;
112	Assert(idx != pPage->idx);
113	pPage = &pPool->aPages[idx];
114	}
115	}
116
117	/*
118	* Iterate the list flushing each shadow page.
119	*/
120	int rc = VINF_SUCCESS;
121	for (;;)
122	{
123	idx = pPage->iMonitoredNext;
124	Assert(idx != pPage->idx);
125	if (pPage->idx >= PGMPOOL_IDX_FIRST)
126	{
127	int rc2 = pgmPoolFlushPage(pPool, pPage);
128	AssertRC(rc2);
129	}
130	/* next */
131	if (idx == NIL_PGMPOOL_IDX)
132	break;
133	pPage = &pPool->aPages[idx];
134	}
135	return rc;
136	}
137
138
139	/**
140	* Wrapper for getting the current context pointer to the entry being modified.
141	*
142	* @returns VBox status code suitable for scheduling.
143	* @param pVM Pointer to the VM.
144	* @param pvDst Destination address
145	* @param pvSrc Source guest virtual address.
146	* @param GCPhysSrc The source guest physical address.
147	* @param cb Size of data to read
148	*/
149	DECLINLINE(int) pgmPoolPhysSimpleReadGCPhys(PVM pVM, void *pvDst, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvSrc,
150	RTGCPHYS GCPhysSrc, size_t cb)
151	{
152	#if defined(IN_RING3)
153	NOREF(pVM); NOREF(GCPhysSrc);
154	memcpy(pvDst, (RTHCPTR)((uintptr_t)pvSrc & ~(RTHCUINTPTR)(cb - 1)), cb);
155	return VINF_SUCCESS;
156	#else
157	/* @todo in RC we could attempt to use the virtual address, although this can cause many faults (PAE Windows XP guest). */
158	NOREF(pvSrc);
159	return PGMPhysSimpleReadGCPhys(pVM, pvDst, GCPhysSrc & ~(RTGCPHYS)(cb - 1), cb);
160	#endif
161	}
162
163
164	/**
165	* Process shadow entries before they are changed by the guest.
166	*
167	* For PT entries we will clear them. For PD entries, we'll simply check
168	* for mapping conflicts and set the SyncCR3 FF if found.
169	*
170	* @param pVCpu Pointer to the VMCPU.
171	* @param pPool The pool.
172	* @param pPage The head page.
173	* @param GCPhysFault The guest physical fault address.
174	* @param uAddress In R0 and GC this is the guest context fault address (flat).
175	* In R3 this is the host context 'fault' address.
176	* @param cbWrite Write size; might be zero if the caller knows we're not crossing entry boundaries
177	*/
178	void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault,
179	CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, unsigned cbWrite)
180	{
181	AssertMsg(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX, ("%u (idx=%u)\n", pPage->iMonitoredPrev, pPage->idx));
182	const unsigned off = GCPhysFault & PAGE_OFFSET_MASK;
183	PVM pVM = pPool->CTX_SUFF(pVM);
184	NOREF(pVCpu);
185
186	LogFlow(("pgmPoolMonitorChainChanging: %RGv phys=%RGp cbWrite=%d\n", (RTGCPTR)(CTXTYPE(RTGCPTR, uintptr_t, RTGCPTR))pvAddress, GCPhysFault, cbWrite));
187
188	for (;;)
189	{
190	union
191	{
192	void *pv;
193	PX86PT pPT;
194	PPGMSHWPTPAE pPTPae;
195	PX86PD pPD;
196	PX86PDPAE pPDPae;
197	PX86PDPT pPDPT;
198	PX86PML4 pPML4;
199	} uShw;
200
201	LogFlow(("pgmPoolMonitorChainChanging: page idx=%d phys=%RGp (next=%d) kind=%s\n", pPage->idx, pPage->GCPhys, pPage->iMonitoredNext, pgmPoolPoolKindToStr(pPage->enmKind), cbWrite));
202
203	uShw.pv = NULL;
204	switch (pPage->enmKind)
205	{
206	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
207	{
208	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPT));
209	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
210	const unsigned iShw = off / sizeof(X86PTE);
211	LogFlow(("PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT iShw=%x\n", iShw));
212	if (uShw.pPT->a[iShw].n.u1Present)
213	{
214	X86PTE GstPte;
215
216	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
217	AssertRC(rc);
218	Log4(("pgmPoolMonitorChainChanging 32_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
219	pgmPoolTracDerefGCPhysHint(pPool, pPage,
220	uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK,
221	GstPte.u & X86_PTE_PG_MASK,
222	iShw);
223	ASMAtomicWriteU32(&uShw.pPT->a[iShw].u, 0);
224	}
225	break;
226	}
227
228	/* page/2 sized */
229	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
230	{
231	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPT));
232	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
233	if (!((off ^ pPage->GCPhys) & (PAGE_SIZE / 2)))
234	{
235	const unsigned iShw = (off / sizeof(X86PTE)) & (X86_PG_PAE_ENTRIES - 1);
236	LogFlow(("PGMPOOLKIND_PAE_PT_FOR_32BIT_PT iShw=%x\n", iShw));
237	if (PGMSHWPTEPAE_IS_P(uShw.pPTPae->a[iShw]))
238	{
239	X86PTE GstPte;
240	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
241	AssertRC(rc);
242
243	Log4(("pgmPoolMonitorChainChanging pae_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
244	pgmPoolTracDerefGCPhysHint(pPool, pPage,
245	PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw]),
246	GstPte.u & X86_PTE_PG_MASK,
247	iShw);
248	PGMSHWPTEPAE_ATOMIC_SET(uShw.pPTPae->a[iShw], 0);
249	}
250	}
251	break;
252	}
253
254	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
255	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
256	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
257	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
258	{
259	unsigned iGst = off / sizeof(X86PDE);
260	unsigned iShwPdpt = iGst / 256;
261	unsigned iShw = (iGst % 256) * 2;
262	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
263
264	LogFlow(("pgmPoolMonitorChainChanging PAE for 32 bits: iGst=%x iShw=%x idx = %d page idx=%d\n", iGst, iShw, iShwPdpt, pPage->enmKind - PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD));
265	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
266	if (iShwPdpt == pPage->enmKind - (unsigned)PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD)
267	{
268	for (unsigned i = 0; i < 2; i++)
269	{
270	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
271	if ((uShw.pPDPae->a[iShw + i].u & (PGM_PDFLAGS_MAPPING \| X86_PDE_P)) == (PGM_PDFLAGS_MAPPING \| X86_PDE_P))
272	{
273	Assert(pgmMapAreMappingsEnabled(pVM));
274	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
275	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw=%#x!\n", iShwPdpt, iShw+i));
276	break;
277	}
278	# endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
279	if (uShw.pPDPae->a[iShw+i].n.u1Present)
280	{
281	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw+i, uShw.pPDPae->a[iShw+i].u));
282	pgmPoolFree(pVM,
283	uShw.pPDPae->a[iShw+i].u & X86_PDE_PAE_PG_MASK,
284	pPage->idx,
285	iShw + i);
286	ASMAtomicWriteU64(&uShw.pPDPae->a[iShw+i].u, 0);
287	}
288
289	/* paranoia / a bit assumptive. */
290	if ( (off & 3)
291	&& (off & 3) + cbWrite > 4)
292	{
293	const unsigned iShw2 = iShw + 2 + i;
294	if (iShw2 < RT_ELEMENTS(uShw.pPDPae->a))
295	{
296	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
297	if ((uShw.pPDPae->a[iShw2].u & (PGM_PDFLAGS_MAPPING \| X86_PDE_P)) == (PGM_PDFLAGS_MAPPING \| X86_PDE_P))
298	{
299	Assert(pgmMapAreMappingsEnabled(pVM));
300	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
301	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw2=%#x!\n", iShwPdpt, iShw2));
302	break;
303	}
304	# endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
305	if (uShw.pPDPae->a[iShw2].n.u1Present)
306	{
307	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
308	pgmPoolFree(pVM,
309	uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
310	pPage->idx,
311	iShw2);
312	ASMAtomicWriteU64(&uShw.pPDPae->a[iShw2].u, 0);
313	}
314	}
315	}
316	}
317	}
318	break;
319	}
320
321	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
322	{
323	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
324	const unsigned iShw = off / sizeof(X86PTEPAE);
325	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPT));
326	if (PGMSHWPTEPAE_IS_P(uShw.pPTPae->a[iShw]))
327	{
328	X86PTEPAE GstPte;
329	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
330	AssertRC(rc);
331
332	Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw]), GstPte.u & X86_PTE_PAE_PG_MASK));
333	pgmPoolTracDerefGCPhysHint(pPool, pPage,
334	PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw]),
335	GstPte.u & X86_PTE_PAE_PG_MASK,
336	iShw);
337	PGMSHWPTEPAE_ATOMIC_SET(uShw.pPTPae->a[iShw], 0);
338	}
339
340	/* paranoia / a bit assumptive. */
341	if ( (off & 7)
342	&& (off & 7) + cbWrite > sizeof(X86PTEPAE))
343	{
344	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTEPAE);
345	AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPTPae->a));
346
347	if (PGMSHWPTEPAE_IS_P(uShw.pPTPae->a[iShw2]))
348	{
349	X86PTEPAE GstPte;
350	# ifdef IN_RING3
351	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, (RTHCPTR)((RTHCUINTPTR)pvAddress + sizeof(GstPte)), GCPhysFault + sizeof(GstPte), sizeof(GstPte));
352	# else
353	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress + sizeof(GstPte), GCPhysFault + sizeof(GstPte), sizeof(GstPte));
354	# endif
355	AssertRC(rc);
356	Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw2]), GstPte.u & X86_PTE_PAE_PG_MASK));
357	pgmPoolTracDerefGCPhysHint(pPool, pPage,
358	PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw2]),
359	GstPte.u & X86_PTE_PAE_PG_MASK,
360	iShw2);
361	PGMSHWPTEPAE_ATOMIC_SET(uShw.pPTPae->a[iShw2], 0);
362	}
363	}
364	break;
365	}
366
367	case PGMPOOLKIND_32BIT_PD:
368	{
369	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
370	const unsigned iShw = off / sizeof(X86PTE); // ASSUMING 32-bit guest paging!
371
372	LogFlow(("pgmPoolMonitorChainChanging: PGMPOOLKIND_32BIT_PD %x\n", iShw));
373	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
374	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
375	if (uShw.pPD->a[iShw].u & PGM_PDFLAGS_MAPPING)
376	{
377	Assert(pgmMapAreMappingsEnabled(pVM));
378	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
379	STAM_COUNTER_INC(&(pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZGuestCR3WriteConflict));
380	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
381	break;
382	}
383	else
384	# endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
385	{
386	if (uShw.pPD->a[iShw].n.u1Present)
387	{
388	LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
389	pgmPoolFree(pVM,
390	uShw.pPD->a[iShw].u & X86_PDE_PAE_PG_MASK,
391	pPage->idx,
392	iShw);
393	ASMAtomicWriteU32(&uShw.pPD->a[iShw].u, 0);
394	}
395	}
396	/* paranoia / a bit assumptive. */
397	if ( (off & 3)
398	&& (off & 3) + cbWrite > sizeof(X86PTE))
399	{
400	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTE);
401	if ( iShw2 != iShw
402	&& iShw2 < RT_ELEMENTS(uShw.pPD->a))
403	{
404	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
405	if (uShw.pPD->a[iShw2].u & PGM_PDFLAGS_MAPPING)
406	{
407	Assert(pgmMapAreMappingsEnabled(pVM));
408	STAM_COUNTER_INC(&(pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZGuestCR3WriteConflict));
409	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
410	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
411	break;
412	}
413	# endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
414	if (uShw.pPD->a[iShw2].n.u1Present)
415	{
416	LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPD->a[iShw2].u));
417	pgmPoolFree(pVM,
418	uShw.pPD->a[iShw2].u & X86_PDE_PAE_PG_MASK,
419	pPage->idx,
420	iShw2);
421	ASMAtomicWriteU32(&uShw.pPD->a[iShw2].u, 0);
422	}
423	}
424	}
425	#if 0 /* useful when running PGMAssertCR3(), a bit too troublesome for general use (TLBs). */
426	if ( uShw.pPD->a[iShw].n.u1Present
427	&& !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
428	{
429	LogFlow(("pgmPoolMonitorChainChanging: iShw=%#x: %RX32 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
430	# ifdef IN_RC /* TLB load - we're pushing things a bit... */
431	ASMProbeReadByte(pvAddress);
432	# endif
433	pgmPoolFree(pVM, uShw.pPD->a[iShw].u & X86_PDE_PG_MASK, pPage->idx, iShw);
434	ASMAtomicWriteU32(&uShw.pPD->a[iShw].u, 0);
435	}
436	#endif
437	break;
438	}
439
440	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
441	{
442	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
443	const unsigned iShw = off / sizeof(X86PDEPAE);
444	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
445	#ifdef VBOX_WITH_RAW_MODE_NOT_R0
446	if (uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING)
447	{
448	Assert(pgmMapAreMappingsEnabled(pVM));
449	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
450	STAM_COUNTER_INC(&(pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZGuestCR3WriteConflict));
451	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
452	break;
453	}
454	#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
455	/*
456	* Causes trouble when the guest uses a PDE to refer to the whole page table level
457	* structure. (Invalidate here; faults later on when it tries to change the page
458	* table entries -> recheck; probably only applies to the RC case.)
459	*/
460	#ifdef VBOX_WITH_RAW_MODE_NOT_R0
461	else
462	#endif
463	{
464	if (uShw.pPDPae->a[iShw].n.u1Present)
465	{
466	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
467	pgmPoolFree(pVM,
468	uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK,
469	pPage->idx,
470	iShw);
471	ASMAtomicWriteU64(&uShw.pPDPae->a[iShw].u, 0);
472	}
473	}
474	/* paranoia / a bit assumptive. */
475	if ( (off & 7)
476	&& (off & 7) + cbWrite > sizeof(X86PDEPAE))
477	{
478	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
479	AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
480
481	#ifdef VBOX_WITH_RAW_MODE_NOT_R0
482	if ( iShw2 != iShw
483	&& uShw.pPDPae->a[iShw2].u & PGM_PDFLAGS_MAPPING)
484	{
485	Assert(pgmMapAreMappingsEnabled(pVM));
486	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
487	STAM_COUNTER_INC(&(pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZGuestCR3WriteConflict));
488	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
489	break;
490	}
491	else
492	#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
493	if (uShw.pPDPae->a[iShw2].n.u1Present)
494	{
495	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
496	pgmPoolFree(pVM,
497	uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
498	pPage->idx,
499	iShw2);
500	ASMAtomicWriteU64(&uShw.pPDPae->a[iShw2].u, 0);
501	}
502	}
503	break;
504	}
505
506	case PGMPOOLKIND_PAE_PDPT:
507	{
508	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPDPT));
509	/*
510	* Hopefully this doesn't happen very often:
511	* - touching unused parts of the page
512	* - messing with the bits of pd pointers without changing the physical address
513	*/
514	/* PDPT roots are not page aligned; 32 byte only! */
515	const unsigned offPdpt = GCPhysFault - pPage->GCPhys;
516
517	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
518	const unsigned iShw = offPdpt / sizeof(X86PDPE);
519	if (iShw < X86_PG_PAE_PDPE_ENTRIES) /* don't use RT_ELEMENTS(uShw.pPDPT->a), because that's for long mode only */
520	{
521	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
522	if (uShw.pPDPT->a[iShw].u & PGM_PLXFLAGS_MAPPING)
523	{
524	Assert(pgmMapAreMappingsEnabled(pVM));
525	STAM_COUNTER_INC(&(pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZGuestCR3WriteConflict));
526	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
527	LogFlow(("pgmPoolMonitorChainChanging: Detected pdpt conflict at iShw=%#x!\n", iShw));
528	break;
529	}
530	else
531	# endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
532	if (uShw.pPDPT->a[iShw].n.u1Present)
533	{
534	LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
535	pgmPoolFree(pVM,
536	uShw.pPDPT->a[iShw].u & X86_PDPE_PG_MASK,
537	pPage->idx,
538	iShw);
539	ASMAtomicWriteU64(&uShw.pPDPT->a[iShw].u, 0);
540	}
541
542	/* paranoia / a bit assumptive. */
543	if ( (offPdpt & 7)
544	&& (offPdpt & 7) + cbWrite > sizeof(X86PDPE))
545	{
546	const unsigned iShw2 = (offPdpt + cbWrite - 1) / sizeof(X86PDPE);
547	if ( iShw2 != iShw
548	&& iShw2 < X86_PG_PAE_PDPE_ENTRIES)
549	{
550	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
551	if (uShw.pPDPT->a[iShw2].u & PGM_PLXFLAGS_MAPPING)
552	{
553	Assert(pgmMapAreMappingsEnabled(pVM));
554	STAM_COUNTER_INC(&(pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZGuestCR3WriteConflict));
555	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
556	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
557	break;
558	}
559	else
560	# endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
561	if (uShw.pPDPT->a[iShw2].n.u1Present)
562	{
563	LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
564	pgmPoolFree(pVM,
565	uShw.pPDPT->a[iShw2].u & X86_PDPE_PG_MASK,
566	pPage->idx,
567	iShw2);
568	ASMAtomicWriteU64(&uShw.pPDPT->a[iShw2].u, 0);
569	}
570	}
571	}
572	}
573	break;
574	}
575
576	#ifndef IN_RC
577	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
578	{
579	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
580	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
581	const unsigned iShw = off / sizeof(X86PDEPAE);
582	Assert(!(uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING));
583	if (uShw.pPDPae->a[iShw].n.u1Present)
584	{
585	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
586	pgmPoolFree(pVM,
587	uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK,
588	pPage->idx,
589	iShw);
590	ASMAtomicWriteU64(&uShw.pPDPae->a[iShw].u, 0);
591	}
592	/* paranoia / a bit assumptive. */
593	if ( (off & 7)
594	&& (off & 7) + cbWrite > sizeof(X86PDEPAE))
595	{
596	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
597	AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
598
599	Assert(!(uShw.pPDPae->a[iShw2].u & PGM_PDFLAGS_MAPPING));
600	if (uShw.pPDPae->a[iShw2].n.u1Present)
601	{
602	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
603	pgmPoolFree(pVM,
604	uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
605	pPage->idx,
606	iShw2);
607	ASMAtomicWriteU64(&uShw.pPDPae->a[iShw2].u, 0);
608	}
609	}
610	break;
611	}
612
613	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
614	{
615	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPDPT));
616	/*
617	* Hopefully this doesn't happen very often:
618	* - messing with the bits of pd pointers without changing the physical address
619	*/
620	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
621	const unsigned iShw = off / sizeof(X86PDPE);
622	if (uShw.pPDPT->a[iShw].n.u1Present)
623	{
624	LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
625	pgmPoolFree(pVM, uShw.pPDPT->a[iShw].u & X86_PDPE_PG_MASK, pPage->idx, iShw);
626	ASMAtomicWriteU64(&uShw.pPDPT->a[iShw].u, 0);
627	}
628	/* paranoia / a bit assumptive. */
629	if ( (off & 7)
630	&& (off & 7) + cbWrite > sizeof(X86PDPE))
631	{
632	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDPE);
633	if (uShw.pPDPT->a[iShw2].n.u1Present)
634	{
635	LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
636	pgmPoolFree(pVM, uShw.pPDPT->a[iShw2].u & X86_PDPE_PG_MASK, pPage->idx, iShw2);
637	ASMAtomicWriteU64(&uShw.pPDPT->a[iShw2].u, 0);
638	}
639	}
640	break;
641	}
642
643	case PGMPOOLKIND_64BIT_PML4:
644	{
645	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPML4));
646	/*
647	* Hopefully this doesn't happen very often:
648	* - messing with the bits of pd pointers without changing the physical address
649	*/
650	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
651	const unsigned iShw = off / sizeof(X86PDPE);
652	if (uShw.pPML4->a[iShw].n.u1Present)
653	{
654	LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPML4->a[iShw].u));
655	pgmPoolFree(pVM, uShw.pPML4->a[iShw].u & X86_PML4E_PG_MASK, pPage->idx, iShw);
656	ASMAtomicWriteU64(&uShw.pPML4->a[iShw].u, 0);
657	}
658	/* paranoia / a bit assumptive. */
659	if ( (off & 7)
660	&& (off & 7) + cbWrite > sizeof(X86PDPE))
661	{
662	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PML4E);
663	if (uShw.pPML4->a[iShw2].n.u1Present)
664	{
665	LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPML4->a[iShw2].u));
666	pgmPoolFree(pVM, uShw.pPML4->a[iShw2].u & X86_PML4E_PG_MASK, pPage->idx, iShw2);
667	ASMAtomicWriteU64(&uShw.pPML4->a[iShw2].u, 0);
668	}
669	}
670	break;
671	}
672	#endif /* IN_RING0 */
673
674	default:
675	AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
676	}
677	PGM_DYNMAP_UNUSED_HINT_VM(pVM, uShw.pv);
678
679	/* next */
680	if (pPage->iMonitoredNext == NIL_PGMPOOL_IDX)
681	return;
682	pPage = &pPool->aPages[pPage->iMonitoredNext];
683	}
684	}
685
686	# ifndef IN_RING3
687
688	/**
689	* Checks if a access could be a fork operation in progress.
690	*
691	* Meaning, that the guest is setting up the parent process for Copy-On-Write.
692	*
693	* @returns true if it's likely that we're forking, otherwise false.
694	* @param pPool The pool.
695	* @param pDis The disassembled instruction.
696	* @param offFault The access offset.
697	*/
698	DECLINLINE(bool) pgmPoolMonitorIsForking(PPGMPOOL pPool, PDISCPUSTATE pDis, unsigned offFault)
699	{
700	/*
701	* i386 linux is using btr to clear X86_PTE_RW.
702	* The functions involved are (2.6.16 source inspection):
703	* clear_bit
704	* ptep_set_wrprotect
705	* copy_one_pte
706	* copy_pte_range
707	* copy_pmd_range
708	* copy_pud_range
709	* copy_page_range
710	* dup_mmap
711	* dup_mm
712	* copy_mm
713	* copy_process
714	* do_fork
715	*/
716	if ( pDis->pCurInstr->uOpcode == OP_BTR
717	&& !(offFault & 4)
718	/** @todo Validate that the bit index is X86_PTE_RW. */
719	)
720	{
721	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,Fork));
722	return true;
723	}
724	return false;
725	}
726
727
728	/**
729	* Determine whether the page is likely to have been reused.
730	*
731	* @returns true if we consider the page as being reused for a different purpose.
732	* @returns false if we consider it to still be a paging page.
733	* @param pVM Pointer to the VM.
734	* @param pVCpu Pointer to the VMCPU.
735	* @param pRegFrame Trap register frame.
736	* @param pDis The disassembly info for the faulting instruction.
737	* @param pvFault The fault address.
738	*
739	* @remark The REP prefix check is left to the caller because of STOSD/W.
740	*/
741	DECLINLINE(bool) pgmPoolMonitorIsReused(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pDis, RTGCPTR pvFault)
742	{
743	#ifndef IN_RC
744	/** @todo could make this general, faulting close to rsp should be a safe reuse heuristic. */
745	if ( HMHasPendingIrq(pVM)
746	&& (pRegFrame->rsp - pvFault) < 32)
747	{
748	/* Fault caused by stack writes while trying to inject an interrupt event. */
749	Log(("pgmPoolMonitorIsReused: reused %RGv for interrupt stack (rsp=%RGv).\n", pvFault, pRegFrame->rsp));
750	return true;
751	}
752	#else
753	NOREF(pVM); NOREF(pvFault);
754	#endif
755
756	LogFlow(("Reused instr %RGv %d at %RGv param1.fUse=%llx param1.reg=%d\n", pRegFrame->rip, pDis->pCurInstr->uOpcode, pvFault, pDis->Param1.fUse, pDis->Param1.Base.idxGenReg));
757
758	/* Non-supervisor mode write means it's used for something else. */
759	if (CPUMGetGuestCPL(pVCpu) == 3)
760	return true;
761
762	switch (pDis->pCurInstr->uOpcode)
763	{
764	/* call implies the actual push of the return address faulted */
765	case OP_CALL:
766	Log4(("pgmPoolMonitorIsReused: CALL\n"));
767	return true;
768	case OP_PUSH:
769	Log4(("pgmPoolMonitorIsReused: PUSH\n"));
770	return true;
771	case OP_PUSHF:
772	Log4(("pgmPoolMonitorIsReused: PUSHF\n"));
773	return true;
774	case OP_PUSHA:
775	Log4(("pgmPoolMonitorIsReused: PUSHA\n"));
776	return true;
777	case OP_FXSAVE:
778	Log4(("pgmPoolMonitorIsReused: FXSAVE\n"));
779	return true;
780	case OP_MOVNTI: /* solaris - block_zero_no_xmm */
781	Log4(("pgmPoolMonitorIsReused: MOVNTI\n"));
782	return true;
783	case OP_MOVNTDQ: /* solaris - hwblkclr & hwblkpagecopy */
784	Log4(("pgmPoolMonitorIsReused: MOVNTDQ\n"));
785	return true;
786	case OP_MOVSWD:
787	case OP_STOSWD:
788	if ( pDis->fPrefix == (DISPREFIX_REP\|DISPREFIX_REX)
789	&& pRegFrame->rcx >= 0x40
790	)
791	{
792	Assert(pDis->uCpuMode == DISCPUMODE_64BIT);
793
794	Log(("pgmPoolMonitorIsReused: OP_STOSQ\n"));
795	return true;
796	}
797	return false;
798	}
799	if ( ( (pDis->Param1.fUse & DISUSE_REG_GEN32)
800	\|\| (pDis->Param1.fUse & DISUSE_REG_GEN64))
801	&& (pDis->Param1.Base.idxGenReg == DISGREG_ESP))
802	{
803	Log4(("pgmPoolMonitorIsReused: ESP\n"));
804	return true;
805	}
806
807	return false;
808	}
809
810
811	/**
812	* Flushes the page being accessed.
813	*
814	* @returns VBox status code suitable for scheduling.
815	* @param pVM Pointer to the VM.
816	* @param pVCpu Pointer to the VMCPU.
817	* @param pPool The pool.
818	* @param pPage The pool page (head).
819	* @param pDis The disassembly of the write instruction.
820	* @param pRegFrame The trap register frame.
821	* @param GCPhysFault The fault address as guest physical address.
822	* @param pvFault The fault address.
823	* @todo VBOXSTRICTRC
824	*/
825	static int pgmPoolAccessHandlerFlush(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
826	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
827	{
828	NOREF(pVM); NOREF(GCPhysFault);
829
830	/*
831	* First, do the flushing.
832	*/
833	int rc = pgmPoolMonitorChainFlush(pPool, pPage);
834
835	/*
836	* Emulate the instruction (xp/w2k problem, requires pc/cr2/sp detection).
837	* Must do this in raw mode (!); XP boot will fail otherwise.
838	*/
839	VBOXSTRICTRC rc2 = EMInterpretInstructionDisasState(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_ALL);
840	if (rc2 == VINF_SUCCESS)
841	{ /* do nothing */ }
842	#ifdef VBOX_WITH_IEM
843	else if (rc2 == VINF_EM_RESCHEDULE)
844	{
845	if (rc == VINF_SUCCESS)
846	rc = VBOXSTRICTRC_VAL(rc2);
847	# ifndef IN_RING3
848	VMCPU_FF_SET(pVCpu, VMCPU_FF_TO_R3);
849	# endif
850	}
851	#endif
852	else if (rc2 == VERR_EM_INTERPRETER)
853	{
854	#ifdef IN_RC
855	if (PATMIsPatchGCAddr(pVM, pRegFrame->eip))
856	{
857	LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for patch code %04x:%RGv, ignoring.\n",
858	pRegFrame->cs.Sel, (RTGCPTR)pRegFrame->eip));
859	rc = VINF_SUCCESS;
860	STAM_COUNTER_INC(&pPool->StatMonitorRZIntrFailPatch2);
861	}
862	else
863	#endif
864	{
865	rc = VINF_EM_RAW_EMULATE_INSTR;
866	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
867	}
868	}
869	else if (RT_FAILURE_NP(rc2))
870	rc = VBOXSTRICTRC_VAL(rc2);
871	else
872	AssertMsgFailed(("%Rrc\n", VBOXSTRICTRC_VAL(rc2))); /* ASSUMES no complicated stuff here. */
873
874	LogFlow(("pgmPoolAccessHandlerPT: returns %Rrc (flushed)\n", rc));
875	return rc;
876	}
877
878
879	/**
880	* Handles the STOSD write accesses.
881	*
882	* @returns VBox status code suitable for scheduling.
883	* @param pVM Pointer to the VM.
884	* @param pPool The pool.
885	* @param pPage The pool page (head).
886	* @param pDis The disassembly of the write instruction.
887	* @param pRegFrame The trap register frame.
888	* @param GCPhysFault The fault address as guest physical address.
889	* @param pvFault The fault address.
890	*/
891	DECLINLINE(int) pgmPoolAccessHandlerSTOSD(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
892	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
893	{
894	unsigned uIncrement = pDis->Param1.cb;
895	NOREF(pVM);
896
897	Assert(pDis->uCpuMode == DISCPUMODE_32BIT \|\| pDis->uCpuMode == DISCPUMODE_64BIT);
898	Assert(pRegFrame->rcx <= 0x20);
899
900	#ifdef VBOX_STRICT
901	if (pDis->uOpMode == DISCPUMODE_32BIT)
902	Assert(uIncrement == 4);
903	else
904	Assert(uIncrement == 8);
905	#endif
906
907	Log3(("pgmPoolAccessHandlerSTOSD\n"));
908
909	/*
910	* Increment the modification counter and insert it into the list
911	* of modified pages the first time.
912	*/
913	if (!pPage->cModifications++)
914	pgmPoolMonitorModifiedInsert(pPool, pPage);
915
916	/*
917	* Execute REP STOSD.
918	*
919	* This ASSUMES that we're not invoked by Trap0e on in a out-of-sync
920	* write situation, meaning that it's safe to write here.
921	*/
922	PVMCPU pVCpu = VMMGetCpu(pPool->CTX_SUFF(pVM));
923	RTGCUINTPTR pu32 = (RTGCUINTPTR)pvFault;
924	while (pRegFrame->rcx)
925	{
926	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
927	uint32_t iPrevSubset = PGMRZDynMapPushAutoSubset(pVCpu);
928	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, (RTGCPTR)pu32, uIncrement);
929	PGMRZDynMapPopAutoSubset(pVCpu, iPrevSubset);
930	#else
931	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, (RTGCPTR)pu32, uIncrement);
932	#endif
933	#ifdef IN_RC
934	(uint32_t )(uintptr_t)pu32 = pRegFrame->eax;
935	#else
936	PGMPhysSimpleWriteGCPhys(pVM, GCPhysFault, &pRegFrame->rax, uIncrement);
937	#endif
938	pu32 += uIncrement;
939	GCPhysFault += uIncrement;
940	pRegFrame->rdi += uIncrement;
941	pRegFrame->rcx--;
942	}
943	pRegFrame->rip += pDis->cbInstr;
944
945	LogFlow(("pgmPoolAccessHandlerSTOSD: returns\n"));
946	return VINF_SUCCESS;
947	}
948
949
950	/**
951	* Handles the simple write accesses.
952	*
953	* @returns VBox status code suitable for scheduling.
954	* @param pVM Pointer to the VM.
955	* @param pVCpu Pointer to the VMCPU.
956	* @param pPool The pool.
957	* @param pPage The pool page (head).
958	* @param pDis The disassembly of the write instruction.
959	* @param pRegFrame The trap register frame.
960	* @param GCPhysFault The fault address as guest physical address.
961	* @param pvFault The fault address.
962	* @param pfReused Reused state (in/out)
963	*/
964	DECLINLINE(int) pgmPoolAccessHandlerSimple(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
965	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault, bool *pfReused)
966	{
967	Log3(("pgmPoolAccessHandlerSimple\n"));
968	NOREF(pVM);
969	NOREF(pfReused); /* initialized by caller */
970
971	/*
972	* Increment the modification counter and insert it into the list
973	* of modified pages the first time.
974	*/
975	if (!pPage->cModifications++)
976	pgmPoolMonitorModifiedInsert(pPool, pPage);
977
978	/*
979	* Clear all the pages. ASSUMES that pvFault is readable.
980	*/
981	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
982	uint32_t iPrevSubset = PGMRZDynMapPushAutoSubset(pVCpu);
983	#endif
984
985	uint32_t cbWrite = DISGetParamSize(pDis, &pDis->Param1);
986	if (cbWrite <= 8)
987	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, cbWrite);
988	else
989	{
990	Assert(cbWrite <= 16);
991	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, 8);
992	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault + 8, pvFault + 8, cbWrite - 8);
993	}
994
995	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
996	PGMRZDynMapPopAutoSubset(pVCpu, iPrevSubset);
997	#endif
998
999	/*
1000	* Interpret the instruction.
1001	*/
1002	VBOXSTRICTRC rc = EMInterpretInstructionDisasState(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_ALL);
1003	if (RT_SUCCESS(rc))
1004	AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rc))); /* ASSUMES no complicated stuff here. */
1005	else if (rc == VERR_EM_INTERPRETER)
1006	{
1007	LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for %04x:%RGv - opcode=%d\n",
1008	pRegFrame->cs.Sel, (RTGCPTR)pRegFrame->rip, pDis->pCurInstr->uOpcode));
1009	rc = VINF_EM_RAW_EMULATE_INSTR;
1010	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
1011	}
1012
1013	#if 0 /* experimental code */
1014	if (rc == VINF_SUCCESS)
1015	{
1016	switch (pPage->enmKind)
1017	{
1018	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1019	{
1020	X86PTEPAE GstPte;
1021	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvFault, GCPhysFault, sizeof(GstPte));
1022	AssertRC(rc);
1023
1024	/* Check the new value written by the guest. If present and with a bogus physical address, then
1025	* it's fairly safe to assume the guest is reusing the PT.
1026	*/
1027	if (GstPte.n.u1Present)
1028	{
1029	RTHCPHYS HCPhys = -1;
1030	int rc = PGMPhysGCPhys2HCPhys(pVM, GstPte.u & X86_PTE_PAE_PG_MASK, &HCPhys);
1031	if (rc != VINF_SUCCESS)
1032	{
1033	*pfReused = true;
1034	STAM_COUNTER_INC(&pPool->StatForceFlushReused);
1035	}
1036	}
1037	break;
1038	}
1039	}
1040	}
1041	#endif
1042
1043	LogFlow(("pgmPoolAccessHandlerSimple: returns %Rrc\n", VBOXSTRICTRC_VAL(rc)));
1044	return VBOXSTRICTRC_VAL(rc);
1045	}
1046
1047
1048	/**
1049	* \#PF Handler callback for PT write accesses.
1050	*
1051	* @returns VBox status code (appropriate for GC return).
1052	* @param pVM Pointer to the VM.
1053	* @param uErrorCode CPU Error code.
1054	* @param pRegFrame Trap register frame.
1055	* NULL on DMA and other non CPU access.
1056	* @param pvFault The fault address (cr2).
1057	* @param GCPhysFault The GC physical address corresponding to pvFault.
1058	* @param pvUser User argument.
1059	*/
1060	DECLEXPORT(int) pgmPoolAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
1061	RTGCPHYS GCPhysFault, void *pvUser)
1062	{
1063	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), a);
1064	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1065	PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)pvUser;
1066	PVMCPU pVCpu = VMMGetCpu(pVM);
1067	unsigned cMaxModifications;
1068	bool fForcedFlush = false;
1069	NOREF(uErrorCode);
1070
1071	LogFlow(("pgmPoolAccessHandler: pvFault=%RGv pPage=%p:{.idx=%d} GCPhysFault=%RGp\n", pvFault, pPage, pPage->idx, GCPhysFault));
1072
1073	pgmLock(pVM);
1074	if (PHYS_PAGE_ADDRESS(GCPhysFault) != PHYS_PAGE_ADDRESS(pPage->GCPhys))
1075	{
1076	/* Pool page changed while we were waiting for the lock; ignore. */
1077	Log(("CPU%d: pgmPoolAccessHandler pgm pool page for %RGp changed (to %RGp) while waiting!\n", pVCpu->idCpu, PHYS_PAGE_ADDRESS(GCPhysFault), PHYS_PAGE_ADDRESS(pPage->GCPhys)));
1078	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,Handled), a);
1079	pgmUnlock(pVM);
1080	return VINF_SUCCESS;
1081	}
1082	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1083	if (pPage->fDirty)
1084	{
1085	Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH));
1086	pgmUnlock(pVM);
1087	return VINF_SUCCESS; /* SMP guest case where we were blocking on the pgm lock while the same page was being marked dirty. */
1088	}
1089	#endif
1090
1091	#if 0 /* test code defined(VBOX_STRICT) && defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) */
1092	if (pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT)
1093	{
1094	void *pvShw = PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
1095	void *pvGst;
1096	int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
1097	pgmPoolTrackCheckPTPaePae(pPool, pPage, (PPGMSHWPTPAE)pvShw, (PCX86PTPAE)pvGst);
1098	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
1099	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvShw);
1100	}
1101	#endif
1102
1103	/*
1104	* Disassemble the faulting instruction.
1105	*/
1106	PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
1107	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL);
1108	if (RT_UNLIKELY(rc != VINF_SUCCESS))
1109	{
1110	AssertMsg(rc == VERR_PAGE_NOT_PRESENT \|\| rc == VERR_PAGE_TABLE_NOT_PRESENT, ("Unexpected rc %d\n", rc));
1111	pgmUnlock(pVM);
1112	return rc;
1113	}
1114
1115	Assert(pPage->enmKind != PGMPOOLKIND_FREE);
1116
1117	/*
1118	* We should ALWAYS have the list head as user parameter. This
1119	* is because we use that page to record the changes.
1120	*/
1121	Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1122
1123	#ifdef IN_RING0
1124	/* Maximum nr of modifications depends on the page type. */
1125	if ( pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1126	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_32BIT_PT)
1127	cMaxModifications = 4;
1128	else
1129	cMaxModifications = 24;
1130	#else
1131	cMaxModifications = 48;
1132	#endif
1133
1134	/*
1135	* Incremental page table updates should weigh more than random ones.
1136	* (Only applies when started from offset 0)
1137	*/
1138	pVCpu->pgm.s.cPoolAccessHandler++;
1139	if ( pPage->GCPtrLastAccessHandlerRip >= pRegFrame->rip - 0x40 /* observed loops in Windows 7 x64 */
1140	&& pPage->GCPtrLastAccessHandlerRip < pRegFrame->rip + 0x40
1141	&& pvFault == (pPage->GCPtrLastAccessHandlerFault + pDis->Param1.cb)
1142	&& pVCpu->pgm.s.cPoolAccessHandler == pPage->cLastAccessHandler + 1)
1143	{
1144	Log(("Possible page reuse cMods=%d -> %d (locked=%d type=%s)\n", pPage->cModifications, pPage->cModifications * 2, pgmPoolIsPageLocked(pPage), pgmPoolPoolKindToStr(pPage->enmKind)));
1145	Assert(pPage->cModifications < 32000);
1146	pPage->cModifications = pPage->cModifications * 2;
1147	pPage->GCPtrLastAccessHandlerFault = pvFault;
1148	pPage->cLastAccessHandler = pVCpu->pgm.s.cPoolAccessHandler;
1149	if (pPage->cModifications >= cMaxModifications)
1150	{
1151	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FlushReinit));
1152	fForcedFlush = true;
1153	}
1154	}
1155
1156	if (pPage->cModifications >= cMaxModifications)
1157	Log(("Mod overflow %RGv cMods=%d (locked=%d type=%s)\n", pvFault, pPage->cModifications, pgmPoolIsPageLocked(pPage), pgmPoolPoolKindToStr(pPage->enmKind)));
1158
1159	/*
1160	* Check if it's worth dealing with.
1161	*/
1162	bool fReused = false;
1163	bool fNotReusedNotForking = false;
1164	if ( ( pPage->cModifications < cMaxModifications /** @todo #define / /* @todo need to check that it's not mapping EIP. / /* @todo adjust this! */
1165	\|\| pgmPoolIsPageLocked(pPage)
1166	)
1167	&& !(fReused = pgmPoolMonitorIsReused(pVM, pVCpu, pRegFrame, pDis, pvFault))
1168	&& !pgmPoolMonitorIsForking(pPool, pDis, GCPhysFault & PAGE_OFFSET_MASK))
1169	{
1170	/*
1171	* Simple instructions, no REP prefix.
1172	*/
1173	if (!(pDis->fPrefix & (DISPREFIX_REP \| DISPREFIX_REPNE)))
1174	{
1175	rc = pgmPoolAccessHandlerSimple(pVM, pVCpu, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault, &fReused);
1176	if (fReused)
1177	goto flushPage;
1178
1179	/* A mov instruction to change the first page table entry will be remembered so we can detect
1180	* full page table changes early on. This will reduce the amount of unnecessary traps we'll take.
1181	*/
1182	if ( rc == VINF_SUCCESS
1183	&& !pPage->cLocked /* only applies to unlocked pages as we can't free locked ones (e.g. cr3 root). */
1184	&& pDis->pCurInstr->uOpcode == OP_MOV
1185	&& (pvFault & PAGE_OFFSET_MASK) == 0)
1186	{
1187	pPage->GCPtrLastAccessHandlerFault = pvFault;
1188	pPage->cLastAccessHandler = pVCpu->pgm.s.cPoolAccessHandler;
1189	pPage->GCPtrLastAccessHandlerRip = pRegFrame->rip;
1190	/* Make sure we don't kick out a page too quickly. */
1191	if (pPage->cModifications > 8)
1192	pPage->cModifications = 2;
1193	}
1194	else if (pPage->GCPtrLastAccessHandlerFault == pvFault)
1195	{
1196	/* ignore the 2nd write to this page table entry. */
1197	pPage->cLastAccessHandler = pVCpu->pgm.s.cPoolAccessHandler;
1198	}
1199	else
1200	{
1201	pPage->GCPtrLastAccessHandlerFault = NIL_RTGCPTR;
1202	pPage->GCPtrLastAccessHandlerRip = 0;
1203	}
1204
1205	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,Handled), a);
1206	pgmUnlock(pVM);
1207	return rc;
1208	}
1209
1210	/*
1211	* Windows is frequently doing small memset() operations (netio test 4k+).
1212	* We have to deal with these or we'll kill the cache and performance.
1213	*/
1214	if ( pDis->pCurInstr->uOpcode == OP_STOSWD
1215	&& !pRegFrame->eflags.Bits.u1DF
1216	&& pDis->uOpMode == pDis->uCpuMode
1217	&& pDis->uAddrMode == pDis->uCpuMode)
1218	{
1219	bool fValidStosd = false;
1220
1221	if ( pDis->uCpuMode == DISCPUMODE_32BIT
1222	&& pDis->fPrefix == DISPREFIX_REP
1223	&& pRegFrame->ecx <= 0x20
1224	&& pRegFrame->ecx * 4 <= PAGE_SIZE - ((uintptr_t)pvFault & PAGE_OFFSET_MASK)
1225	&& !((uintptr_t)pvFault & 3)
1226	&& (pRegFrame->eax == 0 \|\| pRegFrame->eax == 0x80) /* the two values observed. */
1227	)
1228	{
1229	fValidStosd = true;
1230	pRegFrame->rcx &= 0xffffffff; /* paranoia */
1231	}
1232	else
1233	if ( pDis->uCpuMode == DISCPUMODE_64BIT
1234	&& pDis->fPrefix == (DISPREFIX_REP \| DISPREFIX_REX)
1235	&& pRegFrame->rcx <= 0x20
1236	&& pRegFrame->rcx * 8 <= PAGE_SIZE - ((uintptr_t)pvFault & PAGE_OFFSET_MASK)
1237	&& !((uintptr_t)pvFault & 7)
1238	&& (pRegFrame->rax == 0 \|\| pRegFrame->rax == 0x80) /* the two values observed. */
1239	)
1240	{
1241	fValidStosd = true;
1242	}
1243
1244	if (fValidStosd)
1245	{
1246	rc = pgmPoolAccessHandlerSTOSD(pVM, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault);
1247	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,RepStosd), a);
1248	pgmUnlock(pVM);
1249	return rc;
1250	}
1251	}
1252
1253	/* REP prefix, don't bother. */
1254	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,RepPrefix));
1255	Log4(("pgmPoolAccessHandler: eax=%#x ecx=%#x edi=%#x esi=%#x rip=%RGv opcode=%d prefix=%#x\n",
1256	pRegFrame->eax, pRegFrame->ecx, pRegFrame->edi, pRegFrame->esi, (RTGCPTR)pRegFrame->rip, pDis->pCurInstr->uOpcode, pDis->fPrefix));
1257	fNotReusedNotForking = true;
1258	}
1259
1260	#if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) && defined(IN_RING0)
1261	/* E.g. Windows 7 x64 initializes page tables and touches some pages in the table during the process. This
1262	* leads to pgm pool trashing and an excessive amount of write faults due to page monitoring.
1263	*/
1264	if ( pPage->cModifications >= cMaxModifications
1265	&& !fForcedFlush
1266	&& (pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT \|\| pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_32BIT_PT)
1267	&& ( fNotReusedNotForking
1268	\|\| ( !pgmPoolMonitorIsReused(pVM, pVCpu, pRegFrame, pDis, pvFault)
1269	&& !pgmPoolMonitorIsForking(pPool, pDis, GCPhysFault & PAGE_OFFSET_MASK))
1270	)
1271	)
1272	{
1273	Assert(!pgmPoolIsPageLocked(pPage));
1274	Assert(pPage->fDirty == false);
1275
1276	/* Flush any monitored duplicates as we will disable write protection. */
1277	if ( pPage->iMonitoredNext != NIL_PGMPOOL_IDX
1278	\|\| pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
1279	{
1280	PPGMPOOLPAGE pPageHead = pPage;
1281
1282	/* Find the monitor head. */
1283	while (pPageHead->iMonitoredPrev != NIL_PGMPOOL_IDX)
1284	pPageHead = &pPool->aPages[pPageHead->iMonitoredPrev];
1285
1286	while (pPageHead)
1287	{
1288	unsigned idxNext = pPageHead->iMonitoredNext;
1289
1290	if (pPageHead != pPage)
1291	{
1292	STAM_COUNTER_INC(&pPool->StatDirtyPageDupFlush);
1293	Log(("Flush duplicate page idx=%d GCPhys=%RGp type=%s\n", pPageHead->idx, pPageHead->GCPhys, pgmPoolPoolKindToStr(pPageHead->enmKind)));
1294	int rc2 = pgmPoolFlushPage(pPool, pPageHead);
1295	AssertRC(rc2);
1296	}
1297
1298	if (idxNext == NIL_PGMPOOL_IDX)
1299	break;
1300
1301	pPageHead = &pPool->aPages[idxNext];
1302	}
1303	}
1304
1305	/* The flushing above might fail for locked pages, so double check. */
1306	if ( pPage->iMonitoredNext == NIL_PGMPOOL_IDX
1307	&& pPage->iMonitoredPrev == NIL_PGMPOOL_IDX)
1308	{
1309	pgmPoolAddDirtyPage(pVM, pPool, pPage);
1310
1311	/* Temporarily allow write access to the page table again. */
1312	rc = PGMHandlerPhysicalPageTempOff(pVM, pPage->GCPhys & PAGE_BASE_GC_MASK, pPage->GCPhys & PAGE_BASE_GC_MASK);
1313	if (rc == VINF_SUCCESS)
1314	{
1315	rc = PGMShwMakePageWritable(pVCpu, pvFault, PGM_MK_PG_IS_WRITE_FAULT);
1316	AssertMsg(rc == VINF_SUCCESS
1317	/* In the SMP case the page table might be removed while we wait for the PGM lock in the trap handler. */
1318	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
1319	\|\| rc == VERR_PAGE_NOT_PRESENT,
1320	("PGMShwModifyPage -> GCPtr=%RGv rc=%d\n", pvFault, rc));
1321	# ifdef VBOX_STRICT
1322	pPage->GCPtrDirtyFault = pvFault;
1323	# endif
1324
1325	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), a);
1326	pgmUnlock(pVM);
1327	return rc;
1328	}
1329	}
1330	}
1331	#endif /* PGMPOOL_WITH_OPTIMIZED_DIRTY_PT */
1332
1333	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FlushModOverflow));
1334	flushPage:
1335	/*
1336	* Not worth it, so flush it.
1337	*
1338	* If we considered it to be reused, don't go back to ring-3
1339	* to emulate failed instructions since we usually cannot
1340	* interpret then. This may be a bit risky, in which case
1341	* the reuse detection must be fixed.
1342	*/
1343	rc = pgmPoolAccessHandlerFlush(pVM, pVCpu, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault);
1344	if ( rc == VINF_EM_RAW_EMULATE_INSTR
1345	&& fReused)
1346	{
1347	/* Make sure that the current instruction still has shadow page backing, otherwise we'll end up in a loop. */
1348	if (PGMShwGetPage(pVCpu, pRegFrame->rip, NULL, NULL) == VINF_SUCCESS)
1349	rc = VINF_SUCCESS; /* safe to restart the instruction. */
1350	}
1351	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,FlushPage), a);
1352	pgmUnlock(pVM);
1353	return rc;
1354	}
1355
1356	# endif /* !IN_RING3 */
1357
1358	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1359
1360	# if defined(VBOX_STRICT) && !defined(IN_RING3)
1361
1362	/**
1363	* Check references to guest physical memory in a PAE / PAE page table.
1364	*
1365	* @param pPool The pool.
1366	* @param pPage The page.
1367	* @param pShwPT The shadow page table (mapping of the page).
1368	* @param pGstPT The guest page table.
1369	*/
1370	static void pgmPoolTrackCheckPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PTPAE pGstPT)
1371	{
1372	unsigned cErrors = 0;
1373	int LastRc = -1; /* initialized to shut up gcc */
1374	unsigned LastPTE = ~0U; /* initialized to shut up gcc */
1375	RTHCPHYS LastHCPhys = NIL_RTHCPHYS; /* initialized to shut up gcc */
1376	PVM pVM = pPool->CTX_SUFF(pVM);
1377
1378	#ifdef VBOX_STRICT
1379	for (unsigned i = 0; i < RT_MIN(RT_ELEMENTS(pShwPT->a), pPage->iFirstPresent); i++)
1380	AssertMsg(!PGMSHWPTEPAE_IS_P(pShwPT->a[i]), ("Unexpected PTE: idx=%d %RX64 (first=%d)\n", i, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), pPage->iFirstPresent));
1381	#endif
1382	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
1383	{
1384	if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
1385	{
1386	RTHCPHYS HCPhys = NIL_RTHCPHYS;
1387	int rc = PGMPhysGCPhys2HCPhys(pVM, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK, &HCPhys);
1388	if ( rc != VINF_SUCCESS
1389	\|\| PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]) != HCPhys)
1390	{
1391	Log(("rc=%d idx=%d guest %RX64 shw=%RX64 vs %RHp\n", rc, i, pGstPT->a[i].u, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), HCPhys));
1392	LastPTE = i;
1393	LastRc = rc;
1394	LastHCPhys = HCPhys;
1395	cErrors++;
1396
1397	RTHCPHYS HCPhysPT = NIL_RTHCPHYS;
1398	rc = PGMPhysGCPhys2HCPhys(pVM, pPage->GCPhys, &HCPhysPT);
1399	AssertRC(rc);
1400
1401	for (unsigned iPage = 0; iPage < pPool->cCurPages; iPage++)
1402	{
1403	PPGMPOOLPAGE pTempPage = &pPool->aPages[iPage];
1404
1405	if (pTempPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT)
1406	{
1407	PPGMSHWPTPAE pShwPT2 = (PPGMSHWPTPAE)PGMPOOL_PAGE_2_PTR(pVM, pTempPage);
1408
1409	for (unsigned j = 0; j < RT_ELEMENTS(pShwPT->a); j++)
1410	{
1411	if ( PGMSHWPTEPAE_IS_P_RW(pShwPT2->a[j])
1412	&& PGMSHWPTEPAE_GET_HCPHYS(pShwPT2->a[j]) == HCPhysPT)
1413	{
1414	Log(("GCPhys=%RGp idx=%d %RX64 vs %RX64\n", pTempPage->GCPhys, j, PGMSHWPTEPAE_GET_LOG(pShwPT->a[j]), PGMSHWPTEPAE_GET_LOG(pShwPT2->a[j])));
1415	}
1416	}
1417
1418	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pShwPT2);
1419	}
1420	}
1421	}
1422	}
1423	}
1424	AssertMsg(!cErrors, ("cErrors=%d: last rc=%d idx=%d guest %RX64 shw=%RX64 vs %RHp\n", cErrors, LastRc, LastPTE, pGstPT->a[LastPTE].u, PGMSHWPTEPAE_GET_LOG(pShwPT->a[LastPTE]), LastHCPhys));
1425	}
1426
1427
1428	/**
1429	* Check references to guest physical memory in a PAE / 32-bit page table.
1430	*
1431	* @param pPool The pool.
1432	* @param pPage The page.
1433	* @param pShwPT The shadow page table (mapping of the page).
1434	* @param pGstPT The guest page table.
1435	*/
1436	static void pgmPoolTrackCheckPTPae32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PT pGstPT)
1437	{
1438	unsigned cErrors = 0;
1439	int LastRc = -1; /* initialized to shut up gcc */
1440	unsigned LastPTE = ~0U; /* initialized to shut up gcc */
1441	RTHCPHYS LastHCPhys = NIL_RTHCPHYS; /* initialized to shut up gcc */
1442	PVM pVM = pPool->CTX_SUFF(pVM);
1443
1444	#ifdef VBOX_STRICT
1445	for (unsigned i = 0; i < RT_MIN(RT_ELEMENTS(pShwPT->a), pPage->iFirstPresent); i++)
1446	AssertMsg(!PGMSHWPTEPAE_IS_P(pShwPT->a[i]), ("Unexpected PTE: idx=%d %RX64 (first=%d)\n", i, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), pPage->iFirstPresent));
1447	#endif
1448	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
1449	{
1450	if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
1451	{
1452	RTHCPHYS HCPhys = NIL_RTHCPHYS;
1453	int rc = PGMPhysGCPhys2HCPhys(pVM, pGstPT->a[i].u & X86_PTE_PG_MASK, &HCPhys);
1454	if ( rc != VINF_SUCCESS
1455	\|\| PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]) != HCPhys)
1456	{
1457	Log(("rc=%d idx=%d guest %x shw=%RX64 vs %RHp\n", rc, i, pGstPT->a[i].u, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), HCPhys));
1458	LastPTE = i;
1459	LastRc = rc;
1460	LastHCPhys = HCPhys;
1461	cErrors++;
1462
1463	RTHCPHYS HCPhysPT = NIL_RTHCPHYS;
1464	rc = PGMPhysGCPhys2HCPhys(pVM, pPage->GCPhys, &HCPhysPT);
1465	AssertRC(rc);
1466
1467	for (unsigned iPage = 0; iPage < pPool->cCurPages; iPage++)
1468	{
1469	PPGMPOOLPAGE pTempPage = &pPool->aPages[iPage];
1470
1471	if (pTempPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_32BIT_PT)
1472	{
1473	PPGMSHWPTPAE pShwPT2 = (PPGMSHWPTPAE)PGMPOOL_PAGE_2_PTR(pVM, pTempPage);
1474
1475	for (unsigned j = 0; j < RT_ELEMENTS(pShwPT->a); j++)
1476	{
1477	if ( PGMSHWPTEPAE_IS_P_RW(pShwPT2->a[j])
1478	&& PGMSHWPTEPAE_GET_HCPHYS(pShwPT2->a[j]) == HCPhysPT)
1479	{
1480	Log(("GCPhys=%RGp idx=%d %RX64 vs %RX64\n", pTempPage->GCPhys, j, PGMSHWPTEPAE_GET_LOG(pShwPT->a[j]), PGMSHWPTEPAE_GET_LOG(pShwPT2->a[j])));
1481	}
1482	}
1483
1484	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pShwPT2);
1485	}
1486	}
1487	}
1488	}
1489	}
1490	AssertMsg(!cErrors, ("cErrors=%d: last rc=%d idx=%d guest %x shw=%RX64 vs %RHp\n", cErrors, LastRc, LastPTE, pGstPT->a[LastPTE].u, PGMSHWPTEPAE_GET_LOG(pShwPT->a[LastPTE]), LastHCPhys));
1491	}
1492
1493	# endif /* VBOX_STRICT && !IN_RING3 */
1494
1495	/**
1496	* Clear references to guest physical memory in a PAE / PAE page table.
1497	*
1498	* @returns nr of changed PTEs
1499	* @param pPool The pool.
1500	* @param pPage The page.
1501	* @param pShwPT The shadow page table (mapping of the page).
1502	* @param pGstPT The guest page table.
1503	* @param pOldGstPT The old cached guest page table.
1504	* @param fAllowRemoval Bail out as soon as we encounter an invalid PTE
1505	* @param pfFlush Flush reused page table (out)
1506	*/
1507	DECLINLINE(unsigned) pgmPoolTrackFlushPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PTPAE pGstPT,
1508	PCX86PTPAE pOldGstPT, bool fAllowRemoval, bool *pfFlush)
1509	{
1510	unsigned cChanged = 0;
1511
1512	#ifdef VBOX_STRICT
1513	for (unsigned i = 0; i < RT_MIN(RT_ELEMENTS(pShwPT->a), pPage->iFirstPresent); i++)
1514	AssertMsg(!PGMSHWPTEPAE_IS_P(pShwPT->a[i]), ("Unexpected PTE: idx=%d %RX64 (first=%d)\n", i, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), pPage->iFirstPresent));
1515	#endif
1516	*pfFlush = false;
1517
1518	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
1519	{
1520	/* Check the new value written by the guest. If present and with a bogus physical address, then
1521	* it's fairly safe to assume the guest is reusing the PT.
1522	*/
1523	if ( fAllowRemoval
1524	&& pGstPT->a[i].n.u1Present)
1525	{
1526	if (!PGMPhysIsGCPhysValid(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK))
1527	{
1528	*pfFlush = true;
1529	return ++cChanged;
1530	}
1531	}
1532	if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
1533	{
1534	/* If the old cached PTE is identical, then there's no need to flush the shadow copy. */
1535	if ((pGstPT->a[i].u & X86_PTE_PAE_PG_MASK) == (pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK))
1536	{
1537	#ifdef VBOX_STRICT
1538	RTHCPHYS HCPhys = NIL_RTGCPHYS;
1539	int rc = PGMPhysGCPhys2HCPhys(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK, &HCPhys);
1540	AssertMsg(rc == VINF_SUCCESS && PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]) == HCPhys, ("rc=%d guest %RX64 old %RX64 shw=%RX64 vs %RHp\n", rc, pGstPT->a[i].u, pOldGstPT->a[i].u, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), HCPhys));
1541	#endif
1542	uint64_t uHostAttr = PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & (X86_PTE_P \| X86_PTE_US \| X86_PTE_A \| X86_PTE_D \| X86_PTE_G \| X86_PTE_PAE_NX);
1543	bool fHostRW = !!(PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & X86_PTE_RW);
1544	uint64_t uGuestAttr = pGstPT->a[i].u & (X86_PTE_P \| X86_PTE_US \| X86_PTE_A \| X86_PTE_D \| X86_PTE_G \| X86_PTE_PAE_NX);
1545	bool fGuestRW = !!(pGstPT->a[i].u & X86_PTE_RW);
1546
1547	if ( uHostAttr == uGuestAttr
1548	&& fHostRW <= fGuestRW)
1549	continue;
1550	}
1551	cChanged++;
1552	/* Something was changed, so flush it. */
1553	Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX64 hint=%RX64\n",
1554	i, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK));
1555	pgmPoolTracDerefGCPhysHint(pPool, pPage, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK, i);
1556	PGMSHWPTEPAE_ATOMIC_SET(pShwPT->a[i], 0);
1557	}
1558	}
1559	return cChanged;
1560	}
1561
1562
1563	/**
1564	* Clear references to guest physical memory in a PAE / PAE page table.
1565	*
1566	* @returns nr of changed PTEs
1567	* @param pPool The pool.
1568	* @param pPage The page.
1569	* @param pShwPT The shadow page table (mapping of the page).
1570	* @param pGstPT The guest page table.
1571	* @param pOldGstPT The old cached guest page table.
1572	* @param fAllowRemoval Bail out as soon as we encounter an invalid PTE
1573	* @param pfFlush Flush reused page table (out)
1574	*/
1575	DECLINLINE(unsigned) pgmPoolTrackFlushPTPae32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PT pGstPT,
1576	PCX86PT pOldGstPT, bool fAllowRemoval, bool *pfFlush)
1577	{
1578	unsigned cChanged = 0;
1579
1580	#ifdef VBOX_STRICT
1581	for (unsigned i = 0; i < RT_MIN(RT_ELEMENTS(pShwPT->a), pPage->iFirstPresent); i++)
1582	AssertMsg(!PGMSHWPTEPAE_IS_P(pShwPT->a[i]), ("Unexpected PTE: idx=%d %RX64 (first=%d)\n", i, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), pPage->iFirstPresent));
1583	#endif
1584	*pfFlush = false;
1585
1586	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
1587	{
1588	/* Check the new value written by the guest. If present and with a bogus physical address, then
1589	* it's fairly safe to assume the guest is reusing the PT.
1590	*/
1591	if ( fAllowRemoval
1592	&& pGstPT->a[i].n.u1Present)
1593	{
1594	if (!PGMPhysIsGCPhysValid(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PG_MASK))
1595	{
1596	*pfFlush = true;
1597	return ++cChanged;
1598	}
1599	}
1600	if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
1601	{
1602	/* If the old cached PTE is identical, then there's no need to flush the shadow copy. */
1603	if ((pGstPT->a[i].u & X86_PTE_PG_MASK) == (pOldGstPT->a[i].u & X86_PTE_PG_MASK))
1604	{
1605	#ifdef VBOX_STRICT
1606	RTHCPHYS HCPhys = NIL_RTGCPHYS;
1607	int rc = PGMPhysGCPhys2HCPhys(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PG_MASK, &HCPhys);
1608	AssertMsg(rc == VINF_SUCCESS && PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]) == HCPhys, ("rc=%d guest %x old %x shw=%RX64 vs %RHp\n", rc, pGstPT->a[i].u, pOldGstPT->a[i].u, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), HCPhys));
1609	#endif
1610	uint64_t uHostAttr = PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & (X86_PTE_P \| X86_PTE_US \| X86_PTE_A \| X86_PTE_D \| X86_PTE_G);
1611	bool fHostRW = !!(PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & X86_PTE_RW);
1612	uint64_t uGuestAttr = pGstPT->a[i].u & (X86_PTE_P \| X86_PTE_US \| X86_PTE_A \| X86_PTE_D \| X86_PTE_G);
1613	bool fGuestRW = !!(pGstPT->a[i].u & X86_PTE_RW);
1614
1615	if ( uHostAttr == uGuestAttr
1616	&& fHostRW <= fGuestRW)
1617	continue;
1618	}
1619	cChanged++;
1620	/* Something was changed, so flush it. */
1621	Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX64 hint=%x\n",
1622	i, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pOldGstPT->a[i].u & X86_PTE_PG_MASK));
1623	pgmPoolTracDerefGCPhysHint(pPool, pPage, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pOldGstPT->a[i].u & X86_PTE_PG_MASK, i);
1624	PGMSHWPTEPAE_ATOMIC_SET(pShwPT->a[i], 0);
1625	}
1626	}
1627	return cChanged;
1628	}
1629
1630
1631	/**
1632	* Flush a dirty page
1633	*
1634	* @param pVM Pointer to the VM.
1635	* @param pPool The pool.
1636	* @param idxSlot Dirty array slot index
1637	* @param fAllowRemoval Allow a reused page table to be removed
1638	*/
1639	static void pgmPoolFlushDirtyPage(PVM pVM, PPGMPOOL pPool, unsigned idxSlot, bool fAllowRemoval = false)
1640	{
1641	PPGMPOOLPAGE pPage;
1642	unsigned idxPage;
1643
1644	Assert(idxSlot < RT_ELEMENTS(pPool->aDirtyPages));
1645	if (pPool->aDirtyPages[idxSlot].uIdx == NIL_PGMPOOL_IDX)
1646	return;
1647
1648	idxPage = pPool->aDirtyPages[idxSlot].uIdx;
1649	AssertRelease(idxPage != NIL_PGMPOOL_IDX);
1650	pPage = &pPool->aPages[idxPage];
1651	Assert(pPage->idx == idxPage);
1652	Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX && pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1653
1654	AssertMsg(pPage->fDirty, ("Page %RGp (slot=%d) not marked dirty!", pPage->GCPhys, idxSlot));
1655	Log(("Flush dirty page %RGp cMods=%d\n", pPage->GCPhys, pPage->cModifications));
1656
1657	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
1658	PVMCPU pVCpu = VMMGetCpu(pVM);
1659	uint32_t iPrevSubset = PGMRZDynMapPushAutoSubset(pVCpu);
1660	#endif
1661
1662	/* First write protect the page again to catch all write accesses. (before checking for changes -> SMP) */
1663	int rc = PGMHandlerPhysicalReset(pVM, pPage->GCPhys & PAGE_BASE_GC_MASK);
1664	Assert(rc == VINF_SUCCESS);
1665	pPage->fDirty = false;
1666
1667	#ifdef VBOX_STRICT
1668	uint64_t fFlags = 0;
1669	RTHCPHYS HCPhys;
1670	rc = PGMShwGetPage(VMMGetCpu(pVM), pPage->GCPtrDirtyFault, &fFlags, &HCPhys);
1671	AssertMsg( ( rc == VINF_SUCCESS
1672	&& (!(fFlags & X86_PTE_RW) \|\| HCPhys != pPage->Core.Key))
1673	/* In the SMP case the page table might be removed while we wait for the PGM lock in the trap handler. */
1674	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
1675	\|\| rc == VERR_PAGE_NOT_PRESENT,
1676	("PGMShwGetPage -> GCPtr=%RGv rc=%d flags=%RX64\n", pPage->GCPtrDirtyFault, rc, fFlags));
1677	#endif
1678
1679	/* Flush those PTEs that have changed. */
1680	STAM_PROFILE_START(&pPool->StatTrackDeref,a);
1681	void *pvShw = PGMPOOL_PAGE_2_PTR(pVM, pPage);
1682	void *pvGst;
1683	rc = PGM_GCPHYS_2_PTR_EX(pVM, pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
1684	bool fFlush;
1685	unsigned cChanges;
1686
1687	if (pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT)
1688	cChanges = pgmPoolTrackFlushPTPaePae(pPool, pPage, (PPGMSHWPTPAE)pvShw, (PCX86PTPAE)pvGst,
1689	(PCX86PTPAE)&pPool->aDirtyPages[idxSlot].aPage[0], fAllowRemoval, &fFlush);
1690	else
1691	cChanges = pgmPoolTrackFlushPTPae32Bit(pPool, pPage, (PPGMSHWPTPAE)pvShw, (PCX86PT)pvGst,
1692	(PCX86PT)&pPool->aDirtyPages[idxSlot].aPage[0], fAllowRemoval, &fFlush);
1693
1694	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
1695	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvShw);
1696	STAM_PROFILE_STOP(&pPool->StatTrackDeref,a);
1697	/* Note: we might want to consider keeping the dirty page active in case there were many changes. */
1698
1699	/* This page is likely to be modified again, so reduce the nr of modifications just a bit here. */
1700	Assert(pPage->cModifications);
1701	if (cChanges < 4)
1702	pPage->cModifications = 1; /* must use > 0 here */
1703	else
1704	pPage->cModifications = RT_MAX(1, pPage->cModifications / 2);
1705
1706	STAM_COUNTER_INC(&pPool->StatResetDirtyPages);
1707	if (pPool->cDirtyPages == RT_ELEMENTS(pPool->aDirtyPages))
1708	pPool->idxFreeDirtyPage = idxSlot;
1709
1710	pPool->cDirtyPages--;
1711	pPool->aDirtyPages[idxSlot].uIdx = NIL_PGMPOOL_IDX;
1712	Assert(pPool->cDirtyPages <= RT_ELEMENTS(pPool->aDirtyPages));
1713	if (fFlush)
1714	{
1715	Assert(fAllowRemoval);
1716	Log(("Flush reused page table!\n"));
1717	pgmPoolFlushPage(pPool, pPage);
1718	STAM_COUNTER_INC(&pPool->StatForceFlushReused);
1719	}
1720	else
1721	Log(("Removed dirty page %RGp cMods=%d cChanges=%d\n", pPage->GCPhys, pPage->cModifications, cChanges));
1722
1723	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
1724	PGMRZDynMapPopAutoSubset(pVCpu, iPrevSubset);
1725	#endif
1726	}
1727
1728
1729	# ifndef IN_RING3
1730	/**
1731	* Add a new dirty page
1732	*
1733	* @param pVM Pointer to the VM.
1734	* @param pPool The pool.
1735	* @param pPage The page.
1736	*/
1737	void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1738	{
1739	unsigned idxFree;
1740
1741	PGM_LOCK_ASSERT_OWNER(pVM);
1742	AssertCompile(RT_ELEMENTS(pPool->aDirtyPages) == 8 \|\| RT_ELEMENTS(pPool->aDirtyPages) == 16);
1743	Assert(!pPage->fDirty);
1744
1745	idxFree = pPool->idxFreeDirtyPage;
1746	Assert(idxFree < RT_ELEMENTS(pPool->aDirtyPages));
1747	Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX && pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1748
1749	if (pPool->cDirtyPages >= RT_ELEMENTS(pPool->aDirtyPages))
1750	{
1751	STAM_COUNTER_INC(&pPool->StatDirtyPageOverFlowFlush);
1752	pgmPoolFlushDirtyPage(pVM, pPool, idxFree, true /* allow removal of reused page tables*/);
1753	}
1754	Assert(pPool->cDirtyPages < RT_ELEMENTS(pPool->aDirtyPages));
1755	AssertMsg(pPool->aDirtyPages[idxFree].uIdx == NIL_PGMPOOL_IDX, ("idxFree=%d cDirtyPages=%d\n", idxFree, pPool->cDirtyPages));
1756
1757	Log(("Add dirty page %RGp (slot=%d)\n", pPage->GCPhys, idxFree));
1758
1759	/*
1760	* Make a copy of the guest page table as we require valid GCPhys addresses
1761	* when removing references to physical pages.
1762	* (The HCPhys linear lookup is extremely expensive!)
1763	*/
1764	void *pvGst;
1765	int rc = PGM_GCPHYS_2_PTR_EX(pVM, pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
1766	memcpy(&pPool->aDirtyPages[idxFree].aPage[0], pvGst, (pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT) ? PAGE_SIZE : PAGE_SIZE/2);
1767	# ifdef VBOX_STRICT
1768	void *pvShw = PGMPOOL_PAGE_2_PTR(pVM, pPage);
1769	if (pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT)
1770	pgmPoolTrackCheckPTPaePae(pPool, pPage, (PPGMSHWPTPAE)pvShw, (PCX86PTPAE)pvGst);
1771	else
1772	pgmPoolTrackCheckPTPae32Bit(pPool, pPage, (PPGMSHWPTPAE)pvShw, (PCX86PT)pvGst);
1773	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvShw);
1774	# endif
1775	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
1776
1777	STAM_COUNTER_INC(&pPool->StatDirtyPage);
1778	pPage->fDirty = true;
1779	pPage->idxDirtyEntry = (uint8_t)idxFree; Assert(pPage->idxDirtyEntry == idxFree);
1780	pPool->aDirtyPages[idxFree].uIdx = pPage->idx;
1781	pPool->cDirtyPages++;
1782
1783	pPool->idxFreeDirtyPage = (pPool->idxFreeDirtyPage + 1) & (RT_ELEMENTS(pPool->aDirtyPages) - 1);
1784	if ( pPool->cDirtyPages < RT_ELEMENTS(pPool->aDirtyPages)
1785	&& pPool->aDirtyPages[pPool->idxFreeDirtyPage].uIdx != NIL_PGMPOOL_IDX)
1786	{
1787	unsigned i;
1788	for (i = 1; i < RT_ELEMENTS(pPool->aDirtyPages); i++)
1789	{
1790	idxFree = (pPool->idxFreeDirtyPage + i) & (RT_ELEMENTS(pPool->aDirtyPages) - 1);
1791	if (pPool->aDirtyPages[idxFree].uIdx == NIL_PGMPOOL_IDX)
1792	{
1793	pPool->idxFreeDirtyPage = idxFree;
1794	break;
1795	}
1796	}
1797	Assert(i != RT_ELEMENTS(pPool->aDirtyPages));
1798	}
1799
1800	Assert(pPool->cDirtyPages == RT_ELEMENTS(pPool->aDirtyPages) \|\| pPool->aDirtyPages[pPool->idxFreeDirtyPage].uIdx == NIL_PGMPOOL_IDX);
1801
1802	/*
1803	* Clear all references to this shadow table. See @bugref{7298}.
1804	*/
1805	pgmPoolTrackClearPageUsers(pPool, pPage);
1806	}
1807	# endif /* !IN_RING3 */
1808
1809
1810	/**
1811	* Check if the specified page is dirty (not write monitored)
1812	*
1813	* @return dirty or not
1814	* @param pVM Pointer to the VM.
1815	* @param GCPhys Guest physical address
1816	*/
1817	bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys)
1818	{
1819	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1820	PGM_LOCK_ASSERT_OWNER(pVM);
1821	if (!pPool->cDirtyPages)
1822	return false;
1823
1824	GCPhys = GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
1825
1826	for (unsigned i = 0; i < RT_ELEMENTS(pPool->aDirtyPages); i++)
1827	{
1828	if (pPool->aDirtyPages[i].uIdx != NIL_PGMPOOL_IDX)
1829	{
1830	PPGMPOOLPAGE pPage;
1831	unsigned idxPage = pPool->aDirtyPages[i].uIdx;
1832
1833	pPage = &pPool->aPages[idxPage];
1834	if (pPage->GCPhys == GCPhys)
1835	return true;
1836	}
1837	}
1838	return false;
1839	}
1840
1841
1842	/**
1843	* Reset all dirty pages by reinstating page monitoring.
1844	*
1845	* @param pVM Pointer to the VM.
1846	*/
1847	void pgmPoolResetDirtyPages(PVM pVM)
1848	{
1849	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1850	PGM_LOCK_ASSERT_OWNER(pVM);
1851	Assert(pPool->cDirtyPages <= RT_ELEMENTS(pPool->aDirtyPages));
1852
1853	if (!pPool->cDirtyPages)
1854	return;
1855
1856	Log(("pgmPoolResetDirtyPages\n"));
1857	for (unsigned i = 0; i < RT_ELEMENTS(pPool->aDirtyPages); i++)
1858	pgmPoolFlushDirtyPage(pVM, pPool, i, true /* allow removal of reused page tables*/);
1859
1860	pPool->idxFreeDirtyPage = 0;
1861	if ( pPool->cDirtyPages != RT_ELEMENTS(pPool->aDirtyPages)
1862	&& pPool->aDirtyPages[pPool->idxFreeDirtyPage].uIdx != NIL_PGMPOOL_IDX)
1863	{
1864	unsigned i;
1865	for (i = 1; i < RT_ELEMENTS(pPool->aDirtyPages); i++)
1866	{
1867	if (pPool->aDirtyPages[i].uIdx == NIL_PGMPOOL_IDX)
1868	{
1869	pPool->idxFreeDirtyPage = i;
1870	break;
1871	}
1872	}
1873	AssertMsg(i != RT_ELEMENTS(pPool->aDirtyPages), ("cDirtyPages %d", pPool->cDirtyPages));
1874	}
1875
1876	Assert(pPool->aDirtyPages[pPool->idxFreeDirtyPage].uIdx == NIL_PGMPOOL_IDX \|\| pPool->cDirtyPages == RT_ELEMENTS(pPool->aDirtyPages));
1877	return;
1878	}
1879
1880
1881	/**
1882	* Invalidate the PT entry for the specified page
1883	*
1884	* @param pVM Pointer to the VM.
1885	* @param GCPtrPage Guest page to invalidate
1886	*/
1887	void pgmPoolResetDirtyPage(PVM pVM, RTGCPTR GCPtrPage)
1888	{
1889	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1890	PGM_LOCK_ASSERT_OWNER(pVM);
1891	Assert(pPool->cDirtyPages <= RT_ELEMENTS(pPool->aDirtyPages));
1892
1893	if (!pPool->cDirtyPages)
1894	return;
1895
1896	Log(("pgmPoolResetDirtyPage %RGv\n", GCPtrPage));
1897	for (unsigned i = 0; i < RT_ELEMENTS(pPool->aDirtyPages); i++)
1898	{
1899	}
1900	}
1901
1902
1903	/**
1904	* Reset all dirty pages by reinstating page monitoring.
1905	*
1906	* @param pVM Pointer to the VM.
1907	* @param GCPhysPT Physical address of the page table
1908	*/
1909	void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT)
1910	{
1911	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1912	PGM_LOCK_ASSERT_OWNER(pVM);
1913	Assert(pPool->cDirtyPages <= RT_ELEMENTS(pPool->aDirtyPages));
1914	unsigned idxDirtyPage = RT_ELEMENTS(pPool->aDirtyPages);
1915
1916	if (!pPool->cDirtyPages)
1917	return;
1918
1919	GCPhysPT = GCPhysPT & ~(RTGCPHYS)PAGE_OFFSET_MASK;
1920
1921	for (unsigned i = 0; i < RT_ELEMENTS(pPool->aDirtyPages); i++)
1922	{
1923	if (pPool->aDirtyPages[i].uIdx != NIL_PGMPOOL_IDX)
1924	{
1925	unsigned idxPage = pPool->aDirtyPages[i].uIdx;
1926
1927	PPGMPOOLPAGE pPage = &pPool->aPages[idxPage];
1928	if (pPage->GCPhys == GCPhysPT)
1929	{
1930	idxDirtyPage = i;
1931	break;
1932	}
1933	}
1934	}
1935
1936	if (idxDirtyPage != RT_ELEMENTS(pPool->aDirtyPages))
1937	{
1938	pgmPoolFlushDirtyPage(pVM, pPool, idxDirtyPage, true /* allow removal of reused page tables*/);
1939	if ( pPool->cDirtyPages != RT_ELEMENTS(pPool->aDirtyPages)
1940	&& pPool->aDirtyPages[pPool->idxFreeDirtyPage].uIdx != NIL_PGMPOOL_IDX)
1941	{
1942	unsigned i;
1943	for (i = 0; i < RT_ELEMENTS(pPool->aDirtyPages); i++)
1944	{
1945	if (pPool->aDirtyPages[i].uIdx == NIL_PGMPOOL_IDX)
1946	{
1947	pPool->idxFreeDirtyPage = i;
1948	break;
1949	}
1950	}
1951	AssertMsg(i != RT_ELEMENTS(pPool->aDirtyPages), ("cDirtyPages %d", pPool->cDirtyPages));
1952	}
1953	}
1954	}
1955
1956	# endif /* PGMPOOL_WITH_OPTIMIZED_DIRTY_PT */
1957
1958	/**
1959	* Inserts a page into the GCPhys hash table.
1960	*
1961	* @param pPool The pool.
1962	* @param pPage The page.
1963	*/
1964	DECLINLINE(void) pgmPoolHashInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1965	{
1966	Log3(("pgmPoolHashInsert: %RGp\n", pPage->GCPhys));
1967	Assert(pPage->GCPhys != NIL_RTGCPHYS); Assert(pPage->iNext == NIL_PGMPOOL_IDX);
1968	uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1969	pPage->iNext = pPool->aiHash[iHash];
1970	pPool->aiHash[iHash] = pPage->idx;
1971	}
1972
1973
1974	/**
1975	* Removes a page from the GCPhys hash table.
1976	*
1977	* @param pPool The pool.
1978	* @param pPage The page.
1979	*/
1980	DECLINLINE(void) pgmPoolHashRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1981	{
1982	Log3(("pgmPoolHashRemove: %RGp\n", pPage->GCPhys));
1983	uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1984	if (pPool->aiHash[iHash] == pPage->idx)
1985	pPool->aiHash[iHash] = pPage->iNext;
1986	else
1987	{
1988	uint16_t iPrev = pPool->aiHash[iHash];
1989	for (;;)
1990	{
1991	const int16_t i = pPool->aPages[iPrev].iNext;
1992	if (i == pPage->idx)
1993	{
1994	pPool->aPages[iPrev].iNext = pPage->iNext;
1995	break;
1996	}
1997	if (i == NIL_PGMPOOL_IDX)
1998	{
1999	AssertReleaseMsgFailed(("GCPhys=%RGp idx=%d\n", pPage->GCPhys, pPage->idx));
2000	break;
2001	}
2002	iPrev = i;
2003	}
2004	}
2005	pPage->iNext = NIL_PGMPOOL_IDX;
2006	}
2007
2008
2009	/**
2010	* Frees up one cache page.
2011	*
2012	* @returns VBox status code.
2013	* @retval VINF_SUCCESS on success.
2014	* @param pPool The pool.
2015	* @param iUser The user index.
2016	*/
2017	static int pgmPoolCacheFreeOne(PPGMPOOL pPool, uint16_t iUser)
2018	{
2019	#ifndef IN_RC
2020	const PVM pVM = pPool->CTX_SUFF(pVM);
2021	#endif
2022	Assert(pPool->iAgeHead != pPool->iAgeTail); /* We shouldn't be here if there < 2 cached entries! */
2023	STAM_COUNTER_INC(&pPool->StatCacheFreeUpOne);
2024
2025	/*
2026	* Select one page from the tail of the age list.
2027	*/
2028	PPGMPOOLPAGE pPage;
2029	for (unsigned iLoop = 0; ; iLoop++)
2030	{
2031	uint16_t iToFree = pPool->iAgeTail;
2032	if (iToFree == iUser && iUser != NIL_PGMPOOL_IDX)
2033	iToFree = pPool->aPages[iToFree].iAgePrev;
2034	/* This is the alternative to the SyncCR3 pgmPoolCacheUsed calls.
2035	if (pPool->aPages[iToFree].iUserHead != NIL_PGMPOOL_USER_INDEX)
2036	{
2037	uint16_t i = pPool->aPages[iToFree].iAgePrev;
2038	for (unsigned j = 0; j < 10 && i != NIL_PGMPOOL_USER_INDEX; j++, i = pPool->aPages[i].iAgePrev)
2039	{
2040	if (pPool->aPages[iToFree].iUserHead == NIL_PGMPOOL_USER_INDEX)
2041	continue;
2042	iToFree = i;
2043	break;
2044	}
2045	}
2046	*/
2047	Assert(iToFree != iUser);
2048	AssertRelease(iToFree != NIL_PGMPOOL_IDX);
2049	pPage = &pPool->aPages[iToFree];
2050
2051	/*
2052	* Reject any attempts at flushing the currently active shadow CR3 mapping.
2053	* Call pgmPoolCacheUsed to move the page to the head of the age list.
2054	*/
2055	if ( !pgmPoolIsPageLocked(pPage)
2056	&& pPage->idx >= PGMPOOL_IDX_FIRST /* paranoia (#6349) */)
2057	break;
2058	LogFlow(("pgmPoolCacheFreeOne: refuse CR3 mapping\n"));
2059	pgmPoolCacheUsed(pPool, pPage);
2060	AssertLogRelReturn(iLoop < 8192, VERR_PGM_POOL_TOO_MANY_LOOPS);
2061	}
2062
2063	/*
2064	* Found a usable page, flush it and return.
2065	*/
2066	int rc = pgmPoolFlushPage(pPool, pPage);
2067	/* This flush was initiated by us and not the guest, so explicitly flush the TLB. */
2068	/* todo: find out why this is necessary; pgmPoolFlushPage should trigger a flush if one is really needed. */
2069	if (rc == VINF_SUCCESS)
2070	PGM_INVL_ALL_VCPU_TLBS(pVM);
2071	return rc;
2072	}
2073
2074
2075	/**
2076	* Checks if a kind mismatch is really a page being reused
2077	* or if it's just normal remappings.
2078	*
2079	* @returns true if reused and the cached page (enmKind1) should be flushed
2080	* @returns false if not reused.
2081	* @param enmKind1 The kind of the cached page.
2082	* @param enmKind2 The kind of the requested page.
2083	*/
2084	static bool pgmPoolCacheReusedByKind(PGMPOOLKIND enmKind1, PGMPOOLKIND enmKind2)
2085	{
2086	switch (enmKind1)
2087	{
2088	/*
2089	* Never reuse them. There is no remapping in non-paging mode.
2090	*/
2091	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2092	case PGMPOOLKIND_32BIT_PD_PHYS:
2093	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2094	case PGMPOOLKIND_PAE_PD_PHYS:
2095	case PGMPOOLKIND_PAE_PDPT_PHYS:
2096	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2097	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2098	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2099	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2100	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2101	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT: /* never reuse them for other types */
2102	return false;
2103
2104	/*
2105	* It's perfectly fine to reuse these, except for PAE and non-paging stuff.
2106	*/
2107	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2108	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2109	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2110	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2111	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2112	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2113	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2114	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2115	case PGMPOOLKIND_32BIT_PD:
2116	case PGMPOOLKIND_PAE_PDPT:
2117	switch (enmKind2)
2118	{
2119	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2120	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2121	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2122	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2123	case PGMPOOLKIND_64BIT_PML4:
2124	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2125	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2126	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2127	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2128	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2129	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2130	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2131	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2132	return true;
2133	default:
2134	return false;
2135	}
2136
2137	/*
2138	* It's perfectly fine to reuse these, except for PAE and non-paging stuff.
2139	*/
2140	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2141	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2142	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2143	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2144	case PGMPOOLKIND_64BIT_PML4:
2145	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2146	switch (enmKind2)
2147	{
2148	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2149	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2150	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2151	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2152	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2153	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2154	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2155	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2156	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2157	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2158	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2159	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2160	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2161	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2162	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2163	return true;
2164	default:
2165	return false;
2166	}
2167
2168	/*
2169	* These cannot be flushed, and it's common to reuse the PDs as PTs.
2170	*/
2171	case PGMPOOLKIND_ROOT_NESTED:
2172	return false;
2173
2174	default:
2175	AssertFatalMsgFailed(("enmKind1=%d\n", enmKind1));
2176	}
2177	}
2178
2179
2180	/**
2181	* Attempts to satisfy a pgmPoolAlloc request from the cache.
2182	*
2183	* @returns VBox status code.
2184	* @retval VINF_PGM_CACHED_PAGE on success.
2185	* @retval VERR_FILE_NOT_FOUND if not found.
2186	* @param pPool The pool.
2187	* @param GCPhys The GC physical address of the page we're gonna shadow.
2188	* @param enmKind The kind of mapping.
2189	* @param enmAccess Access type for the mapping (only relevant for big pages)
2190	* @param fA20Enabled Whether the CPU has the A20 gate enabled.
2191	* @param iUser The shadow page pool index of the user table. This is
2192	* NIL_PGMPOOL_IDX for root pages.
2193	* @param iUserTable The index into the user table (shadowed). Ignored if
2194	* root page
2195	* @param ppPage Where to store the pointer to the page.
2196	*/
2197	static int pgmPoolCacheAlloc(PPGMPOOL pPool, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
2198	uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage)
2199	{
2200	/*
2201	* Look up the GCPhys in the hash.
2202	*/
2203	unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
2204	Log3(("pgmPoolCacheAlloc: %RGp kind %s iUser=%d iUserTable=%x SLOT=%d\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable, i));
2205	if (i != NIL_PGMPOOL_IDX)
2206	{
2207	do
2208	{
2209	PPGMPOOLPAGE pPage = &pPool->aPages[i];
2210	Log4(("pgmPoolCacheAlloc: slot %d found page %RGp\n", i, pPage->GCPhys));
2211	if (pPage->GCPhys == GCPhys)
2212	{
2213	if ( (PGMPOOLKIND)pPage->enmKind == enmKind
2214	&& (PGMPOOLACCESS)pPage->enmAccess == enmAccess
2215	&& pPage->fA20Enabled == fA20Enabled)
2216	{
2217	/* Put it at the start of the use list to make sure pgmPoolTrackAddUser
2218	* doesn't flush it in case there are no more free use records.
2219	*/
2220	pgmPoolCacheUsed(pPool, pPage);
2221
2222	int rc = VINF_SUCCESS;
2223	if (iUser != NIL_PGMPOOL_IDX)
2224	rc = pgmPoolTrackAddUser(pPool, pPage, iUser, iUserTable);
2225	if (RT_SUCCESS(rc))
2226	{
2227	Assert((PGMPOOLKIND)pPage->enmKind == enmKind);
2228	*ppPage = pPage;
2229	if (pPage->cModifications)
2230	pPage->cModifications = 1; /* reset counter (can't use 0, or else it will be reinserted in the modified list) */
2231	STAM_COUNTER_INC(&pPool->StatCacheHits);
2232	return VINF_PGM_CACHED_PAGE;
2233	}
2234	return rc;
2235	}
2236
2237	if ((PGMPOOLKIND)pPage->enmKind != enmKind)
2238	{
2239	/*
2240	* The kind is different. In some cases we should now flush the page
2241	* as it has been reused, but in most cases this is normal remapping
2242	* of PDs as PT or big pages using the GCPhys field in a slightly
2243	* different way than the other kinds.
2244	*/
2245	if (pgmPoolCacheReusedByKind((PGMPOOLKIND)pPage->enmKind, enmKind))
2246	{
2247	STAM_COUNTER_INC(&pPool->StatCacheKindMismatches);
2248	pgmPoolFlushPage(pPool, pPage);
2249	break;
2250	}
2251	}
2252	}
2253
2254	/* next */
2255	i = pPage->iNext;
2256	} while (i != NIL_PGMPOOL_IDX);
2257	}
2258
2259	Log3(("pgmPoolCacheAlloc: Missed GCPhys=%RGp enmKind=%s\n", GCPhys, pgmPoolPoolKindToStr(enmKind)));
2260	STAM_COUNTER_INC(&pPool->StatCacheMisses);
2261	return VERR_FILE_NOT_FOUND;
2262	}
2263
2264
2265	/**
2266	* Inserts a page into the cache.
2267	*
2268	* @param pPool The pool.
2269	* @param pPage The cached page.
2270	* @param fCanBeCached Set if the page is fit for caching from the caller's point of view.
2271	*/
2272	static void pgmPoolCacheInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fCanBeCached)
2273	{
2274	/*
2275	* Insert into the GCPhys hash if the page is fit for that.
2276	*/
2277	Assert(!pPage->fCached);
2278	if (fCanBeCached)
2279	{
2280	pPage->fCached = true;
2281	pgmPoolHashInsert(pPool, pPage);
2282	Log3(("pgmPoolCacheInsert: Caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
2283	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
2284	STAM_COUNTER_INC(&pPool->StatCacheCacheable);
2285	}
2286	else
2287	{
2288	Log3(("pgmPoolCacheInsert: Not caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
2289	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
2290	STAM_COUNTER_INC(&pPool->StatCacheUncacheable);
2291	}
2292
2293	/*
2294	* Insert at the head of the age list.
2295	*/
2296	pPage->iAgePrev = NIL_PGMPOOL_IDX;
2297	pPage->iAgeNext = pPool->iAgeHead;
2298	if (pPool->iAgeHead != NIL_PGMPOOL_IDX)
2299	pPool->aPages[pPool->iAgeHead].iAgePrev = pPage->idx;
2300	else
2301	pPool->iAgeTail = pPage->idx;
2302	pPool->iAgeHead = pPage->idx;
2303	}
2304
2305
2306	/**
2307	* Flushes a cached page.
2308	*
2309	* @param pPool The pool.
2310	* @param pPage The cached page.
2311	*/
2312	static void pgmPoolCacheFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2313	{
2314	Log3(("pgmPoolCacheFlushPage: %RGp\n", pPage->GCPhys));
2315
2316	/*
2317	* Remove the page from the hash.
2318	*/
2319	if (pPage->fCached)
2320	{
2321	pPage->fCached = false;
2322	pgmPoolHashRemove(pPool, pPage);
2323	}
2324	else
2325	Assert(pPage->iNext == NIL_PGMPOOL_IDX);
2326
2327	/*
2328	* Remove it from the age list.
2329	*/
2330	if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
2331	pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
2332	else
2333	pPool->iAgeTail = pPage->iAgePrev;
2334	if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
2335	pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
2336	else
2337	pPool->iAgeHead = pPage->iAgeNext;
2338	pPage->iAgeNext = NIL_PGMPOOL_IDX;
2339	pPage->iAgePrev = NIL_PGMPOOL_IDX;
2340	}
2341
2342
2343	/**
2344	* Looks for pages sharing the monitor.
2345	*
2346	* @returns Pointer to the head page.
2347	* @returns NULL if not found.
2348	* @param pPool The Pool
2349	* @param pNewPage The page which is going to be monitored.
2350	*/
2351	static PPGMPOOLPAGE pgmPoolMonitorGetPageByGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pNewPage)
2352	{
2353	/*
2354	* Look up the GCPhys in the hash.
2355	*/
2356	RTGCPHYS GCPhys = pNewPage->GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
2357	unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
2358	if (i == NIL_PGMPOOL_IDX)
2359	return NULL;
2360	do
2361	{
2362	PPGMPOOLPAGE pPage = &pPool->aPages[i];
2363	if ( pPage->GCPhys - GCPhys < PAGE_SIZE
2364	&& pPage != pNewPage)
2365	{
2366	switch (pPage->enmKind)
2367	{
2368	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2369	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2370	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2371	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2372	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2373	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2374	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2375	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2376	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2377	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2378	case PGMPOOLKIND_64BIT_PML4:
2379	case PGMPOOLKIND_32BIT_PD:
2380	case PGMPOOLKIND_PAE_PDPT:
2381	{
2382	/* find the head */
2383	while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
2384	{
2385	Assert(pPage->iMonitoredPrev != pPage->idx);
2386	pPage = &pPool->aPages[pPage->iMonitoredPrev];
2387	}
2388	return pPage;
2389	}
2390
2391	/* ignore, no monitoring. */
2392	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2393	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2394	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2395	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2396	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2397	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2398	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2399	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2400	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2401	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2402	case PGMPOOLKIND_ROOT_NESTED:
2403	case PGMPOOLKIND_PAE_PD_PHYS:
2404	case PGMPOOLKIND_PAE_PDPT_PHYS:
2405	case PGMPOOLKIND_32BIT_PD_PHYS:
2406	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
2407	break;
2408	default:
2409	AssertFatalMsgFailed(("enmKind=%d idx=%d\n", pPage->enmKind, pPage->idx));
2410	}
2411	}
2412
2413	/* next */
2414	i = pPage->iNext;
2415	} while (i != NIL_PGMPOOL_IDX);
2416	return NULL;
2417	}
2418
2419
2420	/**
2421	* Enabled write monitoring of a guest page.
2422	*
2423	* @returns VBox status code.
2424	* @retval VINF_SUCCESS on success.
2425	* @param pPool The pool.
2426	* @param pPage The cached page.
2427	*/
2428	static int pgmPoolMonitorInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2429	{
2430	LogFlow(("pgmPoolMonitorInsert %RGp\n", pPage->GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK));
2431
2432	/*
2433	* Filter out the relevant kinds.
2434	*/
2435	switch (pPage->enmKind)
2436	{
2437	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2438	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2439	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2440	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2441	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2442	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2443	case PGMPOOLKIND_64BIT_PML4:
2444	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2445	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2446	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2447	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2448	case PGMPOOLKIND_32BIT_PD:
2449	case PGMPOOLKIND_PAE_PDPT:
2450	break;
2451
2452	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2453	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2454	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2455	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2456	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2457	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2458	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2459	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2460	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2461	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2462	case PGMPOOLKIND_ROOT_NESTED:
2463	/* Nothing to monitor here. */
2464	return VINF_SUCCESS;
2465
2466	case PGMPOOLKIND_32BIT_PD_PHYS:
2467	case PGMPOOLKIND_PAE_PDPT_PHYS:
2468	case PGMPOOLKIND_PAE_PD_PHYS:
2469	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
2470	/* Nothing to monitor here. */
2471	return VINF_SUCCESS;
2472	default:
2473	AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
2474	}
2475
2476	/*
2477	* Install handler.
2478	*/
2479	int rc;
2480	PPGMPOOLPAGE pPageHead = pgmPoolMonitorGetPageByGCPhys(pPool, pPage);
2481	if (pPageHead)
2482	{
2483	Assert(pPageHead != pPage); Assert(pPageHead->iMonitoredNext != pPage->idx);
2484	Assert(pPageHead->iMonitoredPrev != pPage->idx);
2485
2486	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2487	if (pPageHead->fDirty)
2488	pgmPoolFlushDirtyPage(pPool->CTX_SUFF(pVM), pPool, pPageHead->idxDirtyEntry, false /* do not remove */);
2489	#endif
2490
2491	pPage->iMonitoredPrev = pPageHead->idx;
2492	pPage->iMonitoredNext = pPageHead->iMonitoredNext;
2493	if (pPageHead->iMonitoredNext != NIL_PGMPOOL_IDX)
2494	pPool->aPages[pPageHead->iMonitoredNext].iMonitoredPrev = pPage->idx;
2495	pPageHead->iMonitoredNext = pPage->idx;
2496	rc = VINF_SUCCESS;
2497	}
2498	else
2499	{
2500	Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX); Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
2501	PVM pVM = pPool->CTX_SUFF(pVM);
2502	const RTGCPHYS GCPhysPage = pPage->GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
2503	rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
2504	GCPhysPage, GCPhysPage + PAGE_OFFSET_MASK,
2505	pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pPage),
2506	pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pPage),
2507	pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pPage),
2508	pPool->pszAccessHandler);
2509	/** @todo we should probably deal with out-of-memory conditions here, but for now increasing
2510	* the heap size should suffice. */
2511	AssertFatalMsgRC(rc, ("PGMHandlerPhysicalRegisterEx %RGp failed with %Rrc\n", GCPhysPage, rc));
2512	PVMCPU pVCpu = VMMGetCpu(pVM);
2513	AssertFatalMsg(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL) \|\| VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), ("fSyncFlags=%x syncff=%d\n", pVCpu->pgm.s.fSyncFlags, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)));
2514	}
2515	pPage->fMonitored = true;
2516	return rc;
2517	}
2518
2519
2520	/**
2521	* Disables write monitoring of a guest page.
2522	*
2523	* @returns VBox status code.
2524	* @retval VINF_SUCCESS on success.
2525	* @param pPool The pool.
2526	* @param pPage The cached page.
2527	*/
2528	static int pgmPoolMonitorFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2529	{
2530	/*
2531	* Filter out the relevant kinds.
2532	*/
2533	switch (pPage->enmKind)
2534	{
2535	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2536	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2537	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2538	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2539	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2540	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2541	case PGMPOOLKIND_64BIT_PML4:
2542	case PGMPOOLKIND_32BIT_PD:
2543	case PGMPOOLKIND_PAE_PDPT:
2544	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2545	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2546	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2547	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2548	break;
2549
2550	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2551	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2552	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2553	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2554	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2555	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2556	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2557	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2558	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2559	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2560	case PGMPOOLKIND_ROOT_NESTED:
2561	case PGMPOOLKIND_PAE_PD_PHYS:
2562	case PGMPOOLKIND_PAE_PDPT_PHYS:
2563	case PGMPOOLKIND_32BIT_PD_PHYS:
2564	/* Nothing to monitor here. */
2565	Assert(!pPage->fMonitored);
2566	return VINF_SUCCESS;
2567
2568	default:
2569	AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
2570	}
2571	Assert(pPage->fMonitored);
2572
2573	/*
2574	* Remove the page from the monitored list or uninstall it if last.
2575	*/
2576	const PVM pVM = pPool->CTX_SUFF(pVM);
2577	int rc;
2578	if ( pPage->iMonitoredNext != NIL_PGMPOOL_IDX
2579	\|\| pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
2580	{
2581	if (pPage->iMonitoredPrev == NIL_PGMPOOL_IDX)
2582	{
2583	PPGMPOOLPAGE pNewHead = &pPool->aPages[pPage->iMonitoredNext];
2584	pNewHead->iMonitoredPrev = NIL_PGMPOOL_IDX;
2585	rc = PGMHandlerPhysicalChangeUserArgs(pVM, pPage->GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK, MMHyperCCToR3(pVM, pNewHead),
2586	MMHyperCCToR0(pVM, pNewHead), MMHyperCCToRC(pVM, pNewHead));
2587
2588	AssertFatalRCSuccess(rc);
2589	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
2590	}
2591	else
2592	{
2593	pPool->aPages[pPage->iMonitoredPrev].iMonitoredNext = pPage->iMonitoredNext;
2594	if (pPage->iMonitoredNext != NIL_PGMPOOL_IDX)
2595	{
2596	pPool->aPages[pPage->iMonitoredNext].iMonitoredPrev = pPage->iMonitoredPrev;
2597	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
2598	}
2599	pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
2600	rc = VINF_SUCCESS;
2601	}
2602	}
2603	else
2604	{
2605	rc = PGMHandlerPhysicalDeregister(pVM, pPage->GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK);
2606	AssertFatalRC(rc);
2607	PVMCPU pVCpu = VMMGetCpu(pVM);
2608	AssertFatalMsg(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL) \|\| VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3),
2609	("%#x %#x\n", pVCpu->pgm.s.fSyncFlags, pVM->fGlobalForcedActions));
2610	}
2611	pPage->fMonitored = false;
2612
2613	/*
2614	* Remove it from the list of modified pages (if in it).
2615	*/
2616	pgmPoolMonitorModifiedRemove(pPool, pPage);
2617
2618	return rc;
2619	}
2620
2621
2622	/**
2623	* Inserts the page into the list of modified pages.
2624	*
2625	* @param pPool The pool.
2626	* @param pPage The page.
2627	*/
2628	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2629	{
2630	Log3(("pgmPoolMonitorModifiedInsert: idx=%d\n", pPage->idx));
2631	AssertMsg( pPage->iModifiedNext == NIL_PGMPOOL_IDX
2632	&& pPage->iModifiedPrev == NIL_PGMPOOL_IDX
2633	&& pPool->iModifiedHead != pPage->idx,
2634	("Next=%d Prev=%d idx=%d cModifications=%d Head=%d cModifiedPages=%d\n",
2635	pPage->iModifiedNext, pPage->iModifiedPrev, pPage->idx, pPage->cModifications,
2636	pPool->iModifiedHead, pPool->cModifiedPages));
2637
2638	pPage->iModifiedNext = pPool->iModifiedHead;
2639	if (pPool->iModifiedHead != NIL_PGMPOOL_IDX)
2640	pPool->aPages[pPool->iModifiedHead].iModifiedPrev = pPage->idx;
2641	pPool->iModifiedHead = pPage->idx;
2642	pPool->cModifiedPages++;
2643	#ifdef VBOX_WITH_STATISTICS
2644	if (pPool->cModifiedPages > pPool->cModifiedPagesHigh)
2645	pPool->cModifiedPagesHigh = pPool->cModifiedPages;
2646	#endif
2647	}
2648
2649
2650	/**
2651	* Removes the page from the list of modified pages and resets the
2652	* modification counter.
2653	*
2654	* @param pPool The pool.
2655	* @param pPage The page which is believed to be in the list of modified pages.
2656	*/
2657	static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2658	{
2659	Log3(("pgmPoolMonitorModifiedRemove: idx=%d cModifications=%d\n", pPage->idx, pPage->cModifications));
2660	if (pPool->iModifiedHead == pPage->idx)
2661	{
2662	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
2663	pPool->iModifiedHead = pPage->iModifiedNext;
2664	if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
2665	{
2666	pPool->aPages[pPage->iModifiedNext].iModifiedPrev = NIL_PGMPOOL_IDX;
2667	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2668	}
2669	pPool->cModifiedPages--;
2670	}
2671	else if (pPage->iModifiedPrev != NIL_PGMPOOL_IDX)
2672	{
2673	pPool->aPages[pPage->iModifiedPrev].iModifiedNext = pPage->iModifiedNext;
2674	if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
2675	{
2676	pPool->aPages[pPage->iModifiedNext].iModifiedPrev = pPage->iModifiedPrev;
2677	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2678	}
2679	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2680	pPool->cModifiedPages--;
2681	}
2682	else
2683	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
2684	pPage->cModifications = 0;
2685	}
2686
2687
2688	/**
2689	* Zaps the list of modified pages, resetting their modification counters in the process.
2690	*
2691	* @param pVM Pointer to the VM.
2692	*/
2693	static void pgmPoolMonitorModifiedClearAll(PVM pVM)
2694	{
2695	pgmLock(pVM);
2696	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2697	LogFlow(("pgmPoolMonitorModifiedClearAll: cModifiedPages=%d\n", pPool->cModifiedPages));
2698
2699	unsigned cPages = 0; NOREF(cPages);
2700
2701	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2702	pgmPoolResetDirtyPages(pVM);
2703	#endif
2704
2705	uint16_t idx = pPool->iModifiedHead;
2706	pPool->iModifiedHead = NIL_PGMPOOL_IDX;
2707	while (idx != NIL_PGMPOOL_IDX)
2708	{
2709	PPGMPOOLPAGE pPage = &pPool->aPages[idx];
2710	idx = pPage->iModifiedNext;
2711	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2712	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2713	pPage->cModifications = 0;
2714	Assert(++cPages);
2715	}
2716	AssertMsg(cPages == pPool->cModifiedPages, ("%d != %d\n", cPages, pPool->cModifiedPages));
2717	pPool->cModifiedPages = 0;
2718	pgmUnlock(pVM);
2719	}
2720
2721
2722	/**
2723	* Handle SyncCR3 pool tasks
2724	*
2725	* @returns VBox status code.
2726	* @retval VINF_SUCCESS if successfully added.
2727	* @retval VINF_PGM_SYNC_CR3 is it needs to be deferred to ring 3 (GC only)
2728	* @param pVCpu Pointer to the VMCPU.
2729	* @remark Should only be used when monitoring is available, thus placed in
2730	* the PGMPOOL_WITH_MONITORING #ifdef.
2731	*/
2732	int pgmPoolSyncCR3(PVMCPU pVCpu)
2733	{
2734	PVM pVM = pVCpu->CTX_SUFF(pVM);
2735	LogFlow(("pgmPoolSyncCR3 fSyncFlags=%x\n", pVCpu->pgm.s.fSyncFlags));
2736
2737	/*
2738	* When monitoring shadowed pages, we reset the modification counters on CR3 sync.
2739	* Occasionally we will have to clear all the shadow page tables because we wanted
2740	* to monitor a page which was mapped by too many shadowed page tables. This operation
2741	* sometimes referred to as a 'lightweight flush'.
2742	*/
2743	# ifdef IN_RING3 /* Don't flush in ring-0 or raw mode, it's taking too long. */
2744	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2745	pgmR3PoolClearAll(pVM, false /fFlushRemTlb/);
2746	# else /* !IN_RING3 */
2747	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2748	{
2749	Log(("SyncCR3: PGM_SYNC_CLEAR_PGM_POOL is set -> VINF_PGM_SYNC_CR3\n"));
2750	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
2751
2752	/* Make sure all other VCPUs return to ring 3. */
2753	if (pVM->cCpus > 1)
2754	{
2755	VM_FF_SET(pVM, VM_FF_PGM_POOL_FLUSH_PENDING);
2756	PGM_INVL_ALL_VCPU_TLBS(pVM);
2757	}
2758	return VINF_PGM_SYNC_CR3;
2759	}
2760	# endif /* !IN_RING3 */
2761	else
2762	{
2763	pgmPoolMonitorModifiedClearAll(pVM);
2764
2765	/* pgmPoolMonitorModifiedClearAll can cause a pgm pool flush (dirty page clearing), so make sure we handle this! */
2766	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2767	{
2768	Log(("pgmPoolMonitorModifiedClearAll caused a pgm flush -> call pgmPoolSyncCR3 again!\n"));
2769	return pgmPoolSyncCR3(pVCpu);
2770	}
2771	}
2772	return VINF_SUCCESS;
2773	}
2774
2775
2776	/**
2777	* Frees up at least one user entry.
2778	*
2779	* @returns VBox status code.
2780	* @retval VINF_SUCCESS if successfully added.
2781	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2782	* @param pPool The pool.
2783	* @param iUser The user index.
2784	*/
2785	static int pgmPoolTrackFreeOneUser(PPGMPOOL pPool, uint16_t iUser)
2786	{
2787	STAM_COUNTER_INC(&pPool->StatTrackFreeUpOneUser);
2788	/*
2789	* Just free cached pages in a braindead fashion.
2790	*/
2791	/** @todo walk the age list backwards and free the first with usage. */
2792	int rc = VINF_SUCCESS;
2793	do
2794	{
2795	int rc2 = pgmPoolCacheFreeOne(pPool, iUser);
2796	if (RT_FAILURE(rc2) && rc == VINF_SUCCESS)
2797	rc = rc2;
2798	} while (pPool->iUserFreeHead == NIL_PGMPOOL_USER_INDEX);
2799	return rc;
2800	}
2801
2802
2803	/**
2804	* Inserts a page into the cache.
2805	*
2806	* This will create user node for the page, insert it into the GCPhys
2807	* hash, and insert it into the age list.
2808	*
2809	* @returns VBox status code.
2810	* @retval VINF_SUCCESS if successfully added.
2811	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2812	* @param pPool The pool.
2813	* @param pPage The cached page.
2814	* @param GCPhys The GC physical address of the page we're gonna shadow.
2815	* @param iUser The user index.
2816	* @param iUserTable The user table index.
2817	*/
2818	DECLINLINE(int) pgmPoolTrackInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhys, uint16_t iUser, uint32_t iUserTable)
2819	{
2820	int rc = VINF_SUCCESS;
2821	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2822
2823	LogFlow(("pgmPoolTrackInsert GCPhys=%RGp iUser=%d iUserTable=%x\n", GCPhys, iUser, iUserTable));
2824
2825	if (iUser != NIL_PGMPOOL_IDX)
2826	{
2827	#ifdef VBOX_STRICT
2828	/*
2829	* Check that the entry doesn't already exists.
2830	*/
2831	if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
2832	{
2833	uint16_t i = pPage->iUserHead;
2834	do
2835	{
2836	Assert(i < pPool->cMaxUsers);
2837	AssertMsg(paUsers[i].iUser != iUser \|\| paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
2838	i = paUsers[i].iNext;
2839	} while (i != NIL_PGMPOOL_USER_INDEX);
2840	}
2841	#endif
2842
2843	/*
2844	* Find free a user node.
2845	*/
2846	uint16_t i = pPool->iUserFreeHead;
2847	if (i == NIL_PGMPOOL_USER_INDEX)
2848	{
2849	rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2850	if (RT_FAILURE(rc))
2851	return rc;
2852	i = pPool->iUserFreeHead;
2853	}
2854
2855	/*
2856	* Unlink the user node from the free list,
2857	* initialize and insert it into the user list.
2858	*/
2859	pPool->iUserFreeHead = paUsers[i].iNext;
2860	paUsers[i].iNext = NIL_PGMPOOL_USER_INDEX;
2861	paUsers[i].iUser = iUser;
2862	paUsers[i].iUserTable = iUserTable;
2863	pPage->iUserHead = i;
2864	}
2865	else
2866	pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
2867
2868
2869	/*
2870	* Insert into cache and enable monitoring of the guest page if enabled.
2871	*
2872	* Until we implement caching of all levels, including the CR3 one, we'll
2873	* have to make sure we don't try monitor & cache any recursive reuse of
2874	* a monitored CR3 page. Because all windows versions are doing this we'll
2875	* have to be able to do combined access monitoring, CR3 + PT and
2876	* PD + PT (guest PAE).
2877	*
2878	* Update:
2879	* We're now cooperating with the CR3 monitor if an uncachable page is found.
2880	*/
2881	const bool fCanBeMonitored = true;
2882	pgmPoolCacheInsert(pPool, pPage, fCanBeMonitored); /* This can be expanded. */
2883	if (fCanBeMonitored)
2884	{
2885	rc = pgmPoolMonitorInsert(pPool, pPage);
2886	AssertRC(rc);
2887	}
2888	return rc;
2889	}
2890
2891
2892	/**
2893	* Adds a user reference to a page.
2894	*
2895	* This will move the page to the head of the
2896	*
2897	* @returns VBox status code.
2898	* @retval VINF_SUCCESS if successfully added.
2899	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2900	* @param pPool The pool.
2901	* @param pPage The cached page.
2902	* @param iUser The user index.
2903	* @param iUserTable The user table.
2904	*/
2905	static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2906	{
2907	Log3(("pgmPoolTrackAddUser: GCPhys=%RGp iUser=%%x iUserTable=%x\n", pPage->GCPhys, iUser, iUserTable));
2908	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2909	Assert(iUser != NIL_PGMPOOL_IDX);
2910
2911	# ifdef VBOX_STRICT
2912	/*
2913	* Check that the entry doesn't already exists. We only allow multiple
2914	* users of top-level paging structures (SHW_POOL_ROOT_IDX).
2915	*/
2916	if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
2917	{
2918	uint16_t i = pPage->iUserHead;
2919	do
2920	{
2921	Assert(i < pPool->cMaxUsers);
2922	/** @todo this assertion looks odd... Shouldn't it be && here? */
2923	AssertMsg(paUsers[i].iUser != iUser \|\| paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
2924	i = paUsers[i].iNext;
2925	} while (i != NIL_PGMPOOL_USER_INDEX);
2926	}
2927	# endif
2928
2929	/*
2930	* Allocate a user node.
2931	*/
2932	uint16_t i = pPool->iUserFreeHead;
2933	if (i == NIL_PGMPOOL_USER_INDEX)
2934	{
2935	int rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2936	if (RT_FAILURE(rc))
2937	return rc;
2938	i = pPool->iUserFreeHead;
2939	}
2940	pPool->iUserFreeHead = paUsers[i].iNext;
2941
2942	/*
2943	* Initialize the user node and insert it.
2944	*/
2945	paUsers[i].iNext = pPage->iUserHead;
2946	paUsers[i].iUser = iUser;
2947	paUsers[i].iUserTable = iUserTable;
2948	pPage->iUserHead = i;
2949
2950	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2951	if (pPage->fDirty)
2952	pgmPoolFlushDirtyPage(pPool->CTX_SUFF(pVM), pPool, pPage->idxDirtyEntry, false /* do not remove */);
2953	# endif
2954
2955	/*
2956	* Tell the cache to update its replacement stats for this page.
2957	*/
2958	pgmPoolCacheUsed(pPool, pPage);
2959	return VINF_SUCCESS;
2960	}
2961
2962
2963	/**
2964	* Frees a user record associated with a page.
2965	*
2966	* This does not clear the entry in the user table, it simply replaces the
2967	* user record to the chain of free records.
2968	*
2969	* @param pPool The pool.
2970	* @param HCPhys The HC physical address of the shadow page.
2971	* @param iUser The shadow page pool index of the user table.
2972	* @param iUserTable The index into the user table (shadowed).
2973	*
2974	* @remarks Don't call this for root pages.
2975	*/
2976	static void pgmPoolTrackFreeUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2977	{
2978	Log3(("pgmPoolTrackFreeUser %RGp %x %x\n", pPage->GCPhys, iUser, iUserTable));
2979	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2980	Assert(iUser != NIL_PGMPOOL_IDX);
2981
2982	/*
2983	* Unlink and free the specified user entry.
2984	*/
2985
2986	/* Special: For PAE and 32-bit paging, there is usually no more than one user. */
2987	uint16_t i = pPage->iUserHead;
2988	if ( i != NIL_PGMPOOL_USER_INDEX
2989	&& paUsers[i].iUser == iUser
2990	&& paUsers[i].iUserTable == iUserTable)
2991	{
2992	pPage->iUserHead = paUsers[i].iNext;
2993
2994	paUsers[i].iUser = NIL_PGMPOOL_IDX;
2995	paUsers[i].iNext = pPool->iUserFreeHead;
2996	pPool->iUserFreeHead = i;
2997	return;
2998	}
2999
3000	/* General: Linear search. */
3001	uint16_t iPrev = NIL_PGMPOOL_USER_INDEX;
3002	while (i != NIL_PGMPOOL_USER_INDEX)
3003	{
3004	if ( paUsers[i].iUser == iUser
3005	&& paUsers[i].iUserTable == iUserTable)
3006	{
3007	if (iPrev != NIL_PGMPOOL_USER_INDEX)
3008	paUsers[iPrev].iNext = paUsers[i].iNext;
3009	else
3010	pPage->iUserHead = paUsers[i].iNext;
3011
3012	paUsers[i].iUser = NIL_PGMPOOL_IDX;
3013	paUsers[i].iNext = pPool->iUserFreeHead;
3014	pPool->iUserFreeHead = i;
3015	return;
3016	}
3017	iPrev = i;
3018	i = paUsers[i].iNext;
3019	}
3020
3021	/* Fatal: didn't find it */
3022	AssertFatalMsgFailed(("Didn't find the user entry! iUser=%d iUserTable=%#x GCPhys=%RGp\n",
3023	iUser, iUserTable, pPage->GCPhys));
3024	}
3025
3026
3027	/**
3028	* Gets the entry size of a shadow table.
3029	*
3030	* @param enmKind The kind of page.
3031	*
3032	* @returns The size of the entry in bytes. That is, 4 or 8.
3033	* @returns If the kind is not for a table, an assertion is raised and 0 is
3034	* returned.
3035	*/
3036	DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind)
3037	{
3038	switch (enmKind)
3039	{
3040	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3041	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
3042	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3043	case PGMPOOLKIND_32BIT_PD:
3044	case PGMPOOLKIND_32BIT_PD_PHYS:
3045	return 4;
3046
3047	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3048	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3049	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3050	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3051	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3052	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3053	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3054	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3055	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3056	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3057	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3058	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3059	case PGMPOOLKIND_64BIT_PML4:
3060	case PGMPOOLKIND_PAE_PDPT:
3061	case PGMPOOLKIND_ROOT_NESTED:
3062	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3063	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3064	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3065	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3066	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
3067	case PGMPOOLKIND_PAE_PD_PHYS:
3068	case PGMPOOLKIND_PAE_PDPT_PHYS:
3069	return 8;
3070
3071	default:
3072	AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
3073	}
3074	}
3075
3076
3077	/**
3078	* Gets the entry size of a guest table.
3079	*
3080	* @param enmKind The kind of page.
3081	*
3082	* @returns The size of the entry in bytes. That is, 0, 4 or 8.
3083	* @returns If the kind is not for a table, an assertion is raised and 0 is
3084	* returned.
3085	*/
3086	DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind)
3087	{
3088	switch (enmKind)
3089	{
3090	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3091	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3092	case PGMPOOLKIND_32BIT_PD:
3093	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3094	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3095	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3096	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3097	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3098	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3099	return 4;
3100
3101	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3102	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3103	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3104	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3105	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3106	case PGMPOOLKIND_64BIT_PML4:
3107	case PGMPOOLKIND_PAE_PDPT:
3108	return 8;
3109
3110	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
3111	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3112	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3113	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3114	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3115	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3116	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
3117	case PGMPOOLKIND_ROOT_NESTED:
3118	case PGMPOOLKIND_PAE_PD_PHYS:
3119	case PGMPOOLKIND_PAE_PDPT_PHYS:
3120	case PGMPOOLKIND_32BIT_PD_PHYS:
3121	/** @todo can we return 0? (nobody is calling this...) */
3122	AssertFailed();
3123	return 0;
3124
3125	default:
3126	AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
3127	}
3128	}
3129
3130
3131	/**
3132	* Checks one shadow page table entry for a mapping of a physical page.
3133	*
3134	* @returns true / false indicating removal of all relevant PTEs
3135	*
3136	* @param pVM Pointer to the VM.
3137	* @param pPhysPage The guest page in question.
3138	* @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
3139	* @param iShw The shadow page table.
3140	* @param iPte Page table entry or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown
3141	*/
3142	static bool pgmPoolTrackFlushGCPhysPTInt(PVM pVM, PCPGMPAGE pPhysPage, bool fFlushPTEs, uint16_t iShw, uint16_t iPte)
3143	{
3144	LogFlow(("pgmPoolTrackFlushGCPhysPTInt: pPhysPage=%RHp iShw=%d iPte=%d\n", PGM_PAGE_GET_HCPHYS(pPhysPage), iShw, iPte));
3145	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3146	bool fRet = false;
3147
3148	/*
3149	* Assert sanity.
3150	*/
3151	Assert(iPte != NIL_PGMPOOL_PHYSEXT_IDX_PTE);
3152	AssertFatalMsg(iShw < pPool->cCurPages && iShw != NIL_PGMPOOL_IDX, ("iShw=%d\n", iShw));
3153	PPGMPOOLPAGE pPage = &pPool->aPages[iShw];
3154
3155	/*
3156	* Then, clear the actual mappings to the page in the shadow PT.
3157	*/
3158	switch (pPage->enmKind)
3159	{
3160	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3161	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3162	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
3163	{
3164	const uint32_t u32 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
3165	PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3166	uint32_t u32AndMask = 0;
3167	uint32_t u32OrMask = 0;
3168
3169	if (!fFlushPTEs)
3170	{
3171	switch (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage))
3172	{
3173	case PGM_PAGE_HNDL_PHYS_STATE_NONE: /** No handler installed. */
3174	case PGM_PAGE_HNDL_PHYS_STATE_DISABLED: /** Monitoring is temporarily disabled. */
3175	u32OrMask = X86_PTE_RW;
3176	u32AndMask = UINT32_MAX;
3177	fRet = true;
3178	STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
3179	break;
3180
3181	case PGM_PAGE_HNDL_PHYS_STATE_WRITE: /** Write access is monitored. */
3182	u32OrMask = 0;
3183	u32AndMask = ~X86_PTE_RW;
3184	fRet = true;
3185	STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
3186	break;
3187	default:
3188	/* (shouldn't be here, will assert below) */
3189	STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3190	break;
3191	}
3192	}
3193	else
3194	STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3195
3196	/* Update the counter if we're removing references. */
3197	if (!u32AndMask)
3198	{
3199	Assert(pPage->cPresent);
3200	Assert(pPool->cPresent);
3201	pPage->cPresent--;
3202	pPool->cPresent--;
3203	}
3204
3205	if ((pPT->a[iPte].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
3206	{
3207	X86PTE Pte;
3208
3209	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX32\n", iPte, pPT->a[iPte]));
3210	Pte.u = (pPT->a[iPte].u & u32AndMask) \| u32OrMask;
3211	if (Pte.u & PGM_PTFLAGS_TRACK_DIRTY)
3212	Pte.n.u1Write = 0; /* need to disallow writes when dirty bit tracking is still active. */
3213
3214	ASMAtomicWriteU32(&pPT->a[iPte].u, Pte.u);
3215	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
3216	return fRet;
3217	}
3218	#ifdef LOG_ENABLED
3219	Log(("iFirstPresent=%d cPresent=%d\n", pPage->iFirstPresent, pPage->cPresent));
3220	for (unsigned i = 0, cFound = 0; i < RT_ELEMENTS(pPT->a); i++)
3221	if ((pPT->a[i].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
3222	{
3223	Log(("i=%d cFound=%d\n", i, ++cFound));
3224	}
3225	#endif
3226	AssertFatalMsgFailed(("iFirstPresent=%d cPresent=%d u32=%RX32 poolkind=%x\n", pPage->iFirstPresent, pPage->cPresent, u32, pPage->enmKind));
3227	/PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);/
3228	break;
3229	}
3230
3231	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3232	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3233	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3234	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3235	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3236	case PGMPOOLKIND_EPT_PT_FOR_PHYS: /* physical mask the same as PAE; RW bit as well; be careful! */
3237	{
3238	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
3239	PPGMSHWPTPAE pPT = (PPGMSHWPTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3240	uint64_t u64OrMask = 0;
3241	uint64_t u64AndMask = 0;
3242
3243	if (!fFlushPTEs)
3244	{
3245	switch (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage))
3246	{
3247	case PGM_PAGE_HNDL_PHYS_STATE_NONE: /* No handler installed. */
3248	case PGM_PAGE_HNDL_PHYS_STATE_DISABLED: /* Monitoring is temporarily disabled. */
3249	u64OrMask = X86_PTE_RW;
3250	u64AndMask = UINT64_MAX;
3251	fRet = true;
3252	STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
3253	break;
3254
3255	case PGM_PAGE_HNDL_PHYS_STATE_WRITE: /* Write access is monitored. */
3256	u64OrMask = 0;
3257	u64AndMask = ~(uint64_t)X86_PTE_RW;
3258	fRet = true;
3259	STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
3260	break;
3261
3262	default:
3263	/* (shouldn't be here, will assert below) */
3264	STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3265	break;
3266	}
3267	}
3268	else
3269	STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3270
3271	/* Update the counter if we're removing references. */
3272	if (!u64AndMask)
3273	{
3274	Assert(pPage->cPresent);
3275	Assert(pPool->cPresent);
3276	pPage->cPresent--;
3277	pPool->cPresent--;
3278	}
3279
3280	if ((PGMSHWPTEPAE_GET_U(pPT->a[iPte]) & (X86_PTE_PAE_PG_MASK \| X86_PTE_P \| X86_PTE_PAE_MBZ_MASK_NX)) == u64)
3281	{
3282	X86PTEPAE Pte;
3283
3284	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX64\n", iPte, PGMSHWPTEPAE_GET_LOG(pPT->a[iPte])));
3285	Pte.u = (PGMSHWPTEPAE_GET_U(pPT->a[iPte]) & u64AndMask) \| u64OrMask;
3286	if (Pte.u & PGM_PTFLAGS_TRACK_DIRTY)
3287	Pte.n.u1Write = 0; /* need to disallow writes when dirty bit tracking is still active. */
3288
3289	PGMSHWPTEPAE_ATOMIC_SET(pPT->a[iPte], Pte.u);
3290	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
3291	return fRet;
3292	}
3293	#ifdef LOG_ENABLED
3294	Log(("iFirstPresent=%d cPresent=%d\n", pPage->iFirstPresent, pPage->cPresent));
3295	Log(("Found %RX64 expected %RX64\n", PGMSHWPTEPAE_GET_U(pPT->a[iPte]) & (X86_PTE_PAE_PG_MASK \| X86_PTE_P \| X86_PTE_PAE_MBZ_MASK_NX), u64));
3296	for (unsigned i = 0, cFound = 0; i < RT_ELEMENTS(pPT->a); i++)
3297	if ((PGMSHWPTEPAE_GET_U(pPT->a[i]) & (X86_PTE_PAE_PG_MASK \| X86_PTE_P \| X86_PTE_PAE_MBZ_MASK_NX)) == u64)
3298	Log(("i=%d cFound=%d\n", i, ++cFound));
3299	#endif
3300	AssertFatalMsgFailed(("iFirstPresent=%d cPresent=%d u64=%RX64 poolkind=%x iPte=%d PT=%RX64\n", pPage->iFirstPresent, pPage->cPresent, u64, pPage->enmKind, iPte, PGMSHWPTEPAE_GET_LOG(pPT->a[iPte])));
3301	/PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);/
3302	break;
3303	}
3304
3305	#ifdef PGM_WITH_LARGE_PAGES
3306	/* Large page case only. */
3307	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3308	{
3309	Assert(pVM->pgm.s.fNestedPaging);
3310
3311	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PDE4M_P \| X86_PDE4M_PS;
3312	PEPTPD pPD = (PEPTPD)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3313
3314	if ((pPD->a[iPte].u & (EPT_PDE2M_PG_MASK \| X86_PDE4M_P \| X86_PDE4M_PS)) == u64)
3315	{
3316	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pde=%RX64\n", iPte, pPD->a[iPte]));
3317	STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3318	pPD->a[iPte].u = 0;
3319	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPD);
3320
3321	/* Update the counter as we're removing references. */
3322	Assert(pPage->cPresent);
3323	Assert(pPool->cPresent);
3324	pPage->cPresent--;
3325	pPool->cPresent--;
3326
3327	return fRet;
3328	}
3329	# ifdef LOG_ENABLED
3330	Log(("iFirstPresent=%d cPresent=%d\n", pPage->iFirstPresent, pPage->cPresent));
3331	for (unsigned i = 0, cFound = 0; i < RT_ELEMENTS(pPD->a); i++)
3332	if ((pPD->a[i].u & (EPT_PDE2M_PG_MASK \| X86_PDE4M_P \| X86_PDE4M_PS)) == u64)
3333	Log(("i=%d cFound=%d\n", i, ++cFound));
3334	# endif
3335	AssertFatalMsgFailed(("iFirstPresent=%d cPresent=%d\n", pPage->iFirstPresent, pPage->cPresent));
3336	/PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPD);/
3337	break;
3338	}
3339
3340	/* AMD-V nested paging / /* @todo merge with EPT as we only check the parts that are identical. */
3341	case PGMPOOLKIND_PAE_PD_PHYS:
3342	{
3343	Assert(pVM->pgm.s.fNestedPaging);
3344
3345	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PDE4M_P \| X86_PDE4M_PS;
3346	PX86PD pPD = (PX86PD)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3347
3348	if ((pPD->a[iPte].u & (X86_PDE2M_PAE_PG_MASK \| X86_PDE4M_P \| X86_PDE4M_PS)) == u64)
3349	{
3350	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pde=%RX64\n", iPte, pPD->a[iPte]));
3351	STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3352	pPD->a[iPte].u = 0;
3353	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPD);
3354
3355	/* Update the counter as we're removing references. */
3356	Assert(pPage->cPresent);
3357	Assert(pPool->cPresent);
3358	pPage->cPresent--;
3359	pPool->cPresent--;
3360	return fRet;
3361	}
3362	# ifdef LOG_ENABLED
3363	Log(("iFirstPresent=%d cPresent=%d\n", pPage->iFirstPresent, pPage->cPresent));
3364	for (unsigned i = 0, cFound = 0; i < RT_ELEMENTS(pPD->a); i++)
3365	if ((pPD->a[i].u & (X86_PDE2M_PAE_PG_MASK \| X86_PDE4M_P \| X86_PDE4M_PS)) == u64)
3366	Log(("i=%d cFound=%d\n", i, ++cFound));
3367	# endif
3368	AssertFatalMsgFailed(("iFirstPresent=%d cPresent=%d\n", pPage->iFirstPresent, pPage->cPresent));
3369	/PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPD);/
3370	break;
3371	}
3372	#endif /* PGM_WITH_LARGE_PAGES */
3373
3374	default:
3375	AssertFatalMsgFailed(("enmKind=%d iShw=%d\n", pPage->enmKind, iShw));
3376	}
3377
3378	/* not reached. */
3379	#ifndef _MSC_VER
3380	return fRet;
3381	#endif
3382	}
3383
3384
3385	/**
3386	* Scans one shadow page table for mappings of a physical page.
3387	*
3388	* @param pVM Pointer to the VM.
3389	* @param pPhysPage The guest page in question.
3390	* @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
3391	* @param iShw The shadow page table.
3392	*/
3393	static void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, bool fFlushPTEs, uint16_t iShw)
3394	{
3395	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
3396
3397	/* We should only come here with when there's only one reference to this physical page. */
3398	Assert(PGMPOOL_TD_GET_CREFS(PGM_PAGE_GET_TRACKING(pPhysPage)) == 1);
3399
3400	Log2(("pgmPoolTrackFlushGCPhysPT: pPhysPage=%RHp iShw=%d\n", PGM_PAGE_GET_HCPHYS(pPhysPage), iShw));
3401	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPT, f);
3402	bool fKeptPTEs = pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, fFlushPTEs, iShw, PGM_PAGE_GET_PTE_INDEX(pPhysPage));
3403	if (!fKeptPTEs)
3404	PGM_PAGE_SET_TRACKING(pVM, pPhysPage, 0);
3405	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPT, f);
3406	}
3407
3408
3409	/**
3410	* Flushes a list of shadow page tables mapping the same physical page.
3411	*
3412	* @param pVM Pointer to the VM.
3413	* @param pPhysPage The guest page in question.
3414	* @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
3415	* @param iPhysExt The physical cross reference extent list to flush.
3416	*/
3417	static void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, bool fFlushPTEs, uint16_t iPhysExt)
3418	{
3419	PGM_LOCK_ASSERT_OWNER(pVM);
3420	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3421	bool fKeepList = false;
3422
3423	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTs, f);
3424	Log2(("pgmPoolTrackFlushGCPhysPTs: pPhysPage=%RHp iPhysExt\n", PGM_PAGE_GET_HCPHYS(pPhysPage), iPhysExt));
3425
3426	const uint16_t iPhysExtStart = iPhysExt;
3427	PPGMPOOLPHYSEXT pPhysExt;
3428	do
3429	{
3430	Assert(iPhysExt < pPool->cMaxPhysExts);
3431	pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3432	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3433	{
3434	if (pPhysExt->aidx[i] != NIL_PGMPOOL_IDX)
3435	{
3436	bool fKeptPTEs = pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, fFlushPTEs, pPhysExt->aidx[i], pPhysExt->apte[i]);
3437	if (!fKeptPTEs)
3438	{
3439	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3440	pPhysExt->apte[i] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
3441	}
3442	else
3443	fKeepList = true;
3444	}
3445	}
3446	/* next */
3447	iPhysExt = pPhysExt->iNext;
3448	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3449
3450	if (!fKeepList)
3451	{
3452	/* insert the list into the free list and clear the ram range entry. */
3453	pPhysExt->iNext = pPool->iPhysExtFreeHead;
3454	pPool->iPhysExtFreeHead = iPhysExtStart;
3455	/* Invalidate the tracking data. */
3456	PGM_PAGE_SET_TRACKING(pVM, pPhysPage, 0);
3457	}
3458
3459	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTs, f);
3460	}
3461
3462
3463	/**
3464	* Flushes all shadow page table mappings of the given guest page.
3465	*
3466	* This is typically called when the host page backing the guest one has been
3467	* replaced or when the page protection was changed due to a guest access
3468	* caught by the monitoring.
3469	*
3470	* @returns VBox status code.
3471	* @retval VINF_SUCCESS if all references has been successfully cleared.
3472	* @retval VINF_PGM_SYNC_CR3 if we're better off with a CR3 sync and a page
3473	* pool cleaning. FF and sync flags are set.
3474	*
3475	* @param pVM Pointer to the VM.
3476	* @param GCPhysPage GC physical address of the page in question
3477	* @param pPhysPage The guest page in question.
3478	* @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
3479	* @param pfFlushTLBs This is set to @a true if the shadow TLBs should be
3480	* flushed, it is NOT touched if this isn't necessary.
3481	* The caller MUST initialized this to @a false.
3482	*/
3483	int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs)
3484	{
3485	PVMCPU pVCpu = VMMGetCpu(pVM);
3486	pgmLock(pVM);
3487	int rc = VINF_SUCCESS;
3488
3489	#ifdef PGM_WITH_LARGE_PAGES
3490	/* Is this page part of a large page? */
3491	if (PGM_PAGE_GET_PDE_TYPE(pPhysPage) == PGM_PAGE_PDE_TYPE_PDE)
3492	{
3493	RTGCPHYS GCPhysBase = GCPhysPage & X86_PDE2M_PAE_PG_MASK;
3494	GCPhysPage &= X86_PDE_PAE_PG_MASK;
3495
3496	/* Fetch the large page base. */
3497	PPGMPAGE pLargePage;
3498	if (GCPhysBase != GCPhysPage)
3499	{
3500	pLargePage = pgmPhysGetPage(pVM, GCPhysBase);
3501	AssertFatal(pLargePage);
3502	}
3503	else
3504	pLargePage = pPhysPage;
3505
3506	Log(("pgmPoolTrackUpdateGCPhys: update large page PDE for %RGp (%RGp)\n", GCPhysBase, GCPhysPage));
3507
3508	if (PGM_PAGE_GET_PDE_TYPE(pLargePage) == PGM_PAGE_PDE_TYPE_PDE)
3509	{
3510	/* Mark the large page as disabled as we need to break it up to change a single page in the 2 MB range. */
3511	PGM_PAGE_SET_PDE_TYPE(pVM, pLargePage, PGM_PAGE_PDE_TYPE_PDE_DISABLED);
3512	pVM->pgm.s.cLargePagesDisabled++;
3513
3514	/* Update the base as that only that one has a reference and there's only one PDE to clear. */
3515	rc = pgmPoolTrackUpdateGCPhys(pVM, GCPhysBase, pLargePage, fFlushPTEs, pfFlushTLBs);
3516
3517	*pfFlushTLBs = true;
3518	pgmUnlock(pVM);
3519	return rc;
3520	}
3521	}
3522	#else
3523	NOREF(GCPhysPage);
3524	#endif /* PGM_WITH_LARGE_PAGES */
3525
3526	const uint16_t u16 = PGM_PAGE_GET_TRACKING(pPhysPage);
3527	if (u16)
3528	{
3529	/*
3530	* The zero page is currently screwing up the tracking and we'll
3531	* have to flush the whole shebang. Unless VBOX_WITH_NEW_LAZY_PAGE_ALLOC
3532	* is defined, zero pages won't normally be mapped. Some kind of solution
3533	* will be needed for this problem of course, but it will have to wait...
3534	*/
3535	if ( PGM_PAGE_IS_ZERO(pPhysPage)
3536	\|\| PGM_PAGE_IS_BALLOONED(pPhysPage))
3537	rc = VINF_PGM_GCPHYS_ALIASED;
3538	else
3539	{
3540	# if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC) /** @todo we can drop this now. */
3541	/* Start a subset here because pgmPoolTrackFlushGCPhysPTsSlow and
3542	pgmPoolTrackFlushGCPhysPTs will/may kill the pool otherwise. */
3543	uint32_t iPrevSubset = PGMRZDynMapPushAutoSubset(pVCpu);
3544	# endif
3545
3546	if (PGMPOOL_TD_GET_CREFS(u16) != PGMPOOL_TD_CREFS_PHYSEXT)
3547	{
3548	Assert(PGMPOOL_TD_GET_CREFS(u16) == 1);
3549	pgmPoolTrackFlushGCPhysPT(pVM,
3550	pPhysPage,
3551	fFlushPTEs,
3552	PGMPOOL_TD_GET_IDX(u16));
3553	}
3554	else if (u16 != PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED))
3555	pgmPoolTrackFlushGCPhysPTs(pVM, pPhysPage, fFlushPTEs, PGMPOOL_TD_GET_IDX(u16));
3556	else
3557	rc = pgmPoolTrackFlushGCPhysPTsSlow(pVM, pPhysPage);
3558	*pfFlushTLBs = true;
3559
3560	# if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
3561	PGMRZDynMapPopAutoSubset(pVCpu, iPrevSubset);
3562	# endif
3563	}
3564	}
3565
3566	if (rc == VINF_PGM_GCPHYS_ALIASED)
3567	{
3568	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
3569	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3570	rc = VINF_PGM_SYNC_CR3;
3571	}
3572	pgmUnlock(pVM);
3573	return rc;
3574	}
3575
3576
3577	/**
3578	* Scans all shadow page tables for mappings of a physical page.
3579	*
3580	* This may be slow, but it's most likely more efficient than cleaning
3581	* out the entire page pool / cache.
3582	*
3583	* @returns VBox status code.
3584	* @retval VINF_SUCCESS if all references has been successfully cleared.
3585	* @retval VINF_PGM_GCPHYS_ALIASED if we're better off with a CR3 sync and
3586	* a page pool cleaning.
3587	*
3588	* @param pVM Pointer to the VM.
3589	* @param pPhysPage The guest page in question.
3590	*/
3591	int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage)
3592	{
3593	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3594	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTsSlow, s);
3595	LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: cUsedPages=%d cPresent=%d pPhysPage=%R[pgmpage]\n",
3596	pPool->cUsedPages, pPool->cPresent, pPhysPage));
3597
3598	/*
3599	* There is a limit to what makes sense.
3600	*/
3601	if ( pPool->cPresent > 1024
3602	&& pVM->cCpus == 1)
3603	{
3604	LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: giving up... (cPresent=%d)\n", pPool->cPresent));
3605	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
3606	return VINF_PGM_GCPHYS_ALIASED;
3607	}
3608
3609	/*
3610	* Iterate all the pages until we've encountered all that in use.
3611	* This is simple but not quite optimal solution.
3612	*/
3613	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P; /** @todo drop X86_PTE_P here as we always test if present separately, anyway. */
3614	const uint32_t u32 = u64; /** @todo move into the 32BIT_PT_xx case */
3615	unsigned cLeft = pPool->cUsedPages;
3616	unsigned iPage = pPool->cCurPages;
3617	while (--iPage >= PGMPOOL_IDX_FIRST)
3618	{
3619	PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
3620	if ( pPage->GCPhys != NIL_RTGCPHYS
3621	&& pPage->cPresent)
3622	{
3623	switch (pPage->enmKind)
3624	{
3625	/*
3626	* We only care about shadow page tables.
3627	*/
3628	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3629	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3630	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
3631	{
3632	unsigned cPresent = pPage->cPresent;
3633	PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3634	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3635	if (pPT->a[i].n.u1Present)
3636	{
3637	if ((pPT->a[i].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
3638	{
3639	//Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX32\n", iPage, i, pPT->a[i]));
3640	pPT->a[i].u = 0;
3641
3642	/* Update the counter as we're removing references. */
3643	Assert(pPage->cPresent);
3644	Assert(pPool->cPresent);
3645	pPage->cPresent--;
3646	pPool->cPresent--;
3647	}
3648	if (!--cPresent)
3649	break;
3650	}
3651	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
3652	break;
3653	}
3654
3655	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3656	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3657	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3658	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3659	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3660	{
3661	unsigned cPresent = pPage->cPresent;
3662	PPGMSHWPTPAE pPT = (PPGMSHWPTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3663	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3664	if (PGMSHWPTEPAE_IS_P(pPT->a[i]))
3665	{
3666	if ((PGMSHWPTEPAE_GET_U(pPT->a[i]) & (X86_PTE_PAE_PG_MASK \| X86_PTE_P)) == u64)
3667	{
3668	//Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX64\n", iPage, i, pPT->a[i]));
3669	PGMSHWPTEPAE_SET(pPT->a[i], 0); /// @todo why not atomic?
3670
3671	/* Update the counter as we're removing references. */
3672	Assert(pPage->cPresent);
3673	Assert(pPool->cPresent);
3674	pPage->cPresent--;
3675	pPool->cPresent--;
3676	}
3677	if (!--cPresent)
3678	break;
3679	}
3680	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
3681	break;
3682	}
3683	#ifndef IN_RC
3684	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
3685	{
3686	unsigned cPresent = pPage->cPresent;
3687	PEPTPT pPT = (PEPTPT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3688	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3689	if (pPT->a[i].n.u1Present)
3690	{
3691	if ((pPT->a[i].u & (EPT_PTE_PG_MASK \| X86_PTE_P)) == u64)
3692	{
3693	//Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX64\n", iPage, i, pPT->a[i]));
3694	pPT->a[i].u = 0;
3695
3696	/* Update the counter as we're removing references. */
3697	Assert(pPage->cPresent);
3698	Assert(pPool->cPresent);
3699	pPage->cPresent--;
3700	pPool->cPresent--;
3701	}
3702	if (!--cPresent)
3703	break;
3704	}
3705	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
3706	break;
3707	}
3708	#endif
3709	}
3710	if (!--cLeft)
3711	break;
3712	}
3713	}
3714
3715	PGM_PAGE_SET_TRACKING(pVM, pPhysPage, 0);
3716	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
3717
3718	/*
3719	* There is a limit to what makes sense. The above search is very expensive, so force a pgm pool flush.
3720	*/
3721	if (pPool->cPresent > 1024)
3722	{
3723	LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: giving up... (cPresent=%d)\n", pPool->cPresent));
3724	return VINF_PGM_GCPHYS_ALIASED;
3725	}
3726
3727	return VINF_SUCCESS;
3728	}
3729
3730
3731	/**
3732	* Clears the user entry in a user table.
3733	*
3734	* This is used to remove all references to a page when flushing it.
3735	*/
3736	static void pgmPoolTrackClearPageUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PCPGMPOOLUSER pUser)
3737	{
3738	Assert(pUser->iUser != NIL_PGMPOOL_IDX);
3739	Assert(pUser->iUser < pPool->cCurPages);
3740	uint32_t iUserTable = pUser->iUserTable;
3741
3742	/*
3743	* Map the user page. Ignore references made by fictitious pages.
3744	*/
3745	PPGMPOOLPAGE pUserPage = &pPool->aPages[pUser->iUser];
3746	LogFlow(("pgmPoolTrackClearPageUser: clear %x in %s (%RGp) (flushing %s)\n", iUserTable, pgmPoolPoolKindToStr(pUserPage->enmKind), pUserPage->Core.Key, pgmPoolPoolKindToStr(pPage->enmKind)));
3747	union
3748	{
3749	uint64_t *pau64;
3750	uint32_t *pau32;
3751	} u;
3752	if (pUserPage->idx < PGMPOOL_IDX_FIRST)
3753	{
3754	Assert(!pUserPage->pvPageR3);
3755	return;
3756	}
3757	u.pau64 = (uint64_t *)PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pUserPage);
3758
3759
3760	/* Safety precaution in case we change the paging for other modes too in the future. */
3761	Assert(!pgmPoolIsPageLocked(pPage));
3762
3763	#ifdef VBOX_STRICT
3764	/*
3765	* Some sanity checks.
3766	*/
3767	switch (pUserPage->enmKind)
3768	{
3769	case PGMPOOLKIND_32BIT_PD:
3770	case PGMPOOLKIND_32BIT_PD_PHYS:
3771	Assert(iUserTable < X86_PG_ENTRIES);
3772	break;
3773	case PGMPOOLKIND_PAE_PDPT:
3774	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
3775	case PGMPOOLKIND_PAE_PDPT_PHYS:
3776	Assert(iUserTable < 4);
3777	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
3778	break;
3779	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3780	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3781	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3782	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3783	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3784	case PGMPOOLKIND_PAE_PD_PHYS:
3785	Assert(iUserTable < X86_PG_PAE_ENTRIES);
3786	break;
3787	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3788	Assert(iUserTable < X86_PG_PAE_ENTRIES);
3789	Assert(!(u.pau64[iUserTable] & PGM_PDFLAGS_MAPPING));
3790	break;
3791	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3792	Assert(iUserTable < X86_PG_PAE_ENTRIES);
3793	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
3794	break;
3795	case PGMPOOLKIND_64BIT_PML4:
3796	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
3797	/* GCPhys >> PAGE_SHIFT is the index here */
3798	break;
3799	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3800	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3801	Assert(iUserTable < X86_PG_PAE_ENTRIES);
3802	break;
3803
3804	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3805	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3806	Assert(iUserTable < X86_PG_PAE_ENTRIES);
3807	break;
3808
3809	case PGMPOOLKIND_ROOT_NESTED:
3810	Assert(iUserTable < X86_PG_PAE_ENTRIES);
3811	break;
3812
3813	default:
3814	AssertMsgFailed(("enmKind=%d\n", pUserPage->enmKind));
3815	break;
3816	}
3817	#endif /* VBOX_STRICT */
3818
3819	/*
3820	* Clear the entry in the user page.
3821	*/
3822	switch (pUserPage->enmKind)
3823	{
3824	/* 32-bit entries */
3825	case PGMPOOLKIND_32BIT_PD:
3826	case PGMPOOLKIND_32BIT_PD_PHYS:
3827	ASMAtomicWriteU32(&u.pau32[iUserTable], 0);
3828	break;
3829
3830	/* 64-bit entries */
3831	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3832	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3833	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3834	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3835	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3836	#ifdef IN_RC
3837	/*
3838	* In 32 bits PAE mode we must invalidate the TLB when changing a
3839	* PDPT entry; the CPU fetches them only during cr3 load, so any
3840	* non-present PDPT will continue to cause page faults.
3841	*/
3842	ASMReloadCR3();
3843	/* no break */
3844	#endif
3845	case PGMPOOLKIND_PAE_PD_PHYS:
3846	case PGMPOOLKIND_PAE_PDPT_PHYS:
3847	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3848	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3849	case PGMPOOLKIND_64BIT_PML4:
3850	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3851	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3852	case PGMPOOLKIND_PAE_PDPT:
3853	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
3854	case PGMPOOLKIND_ROOT_NESTED:
3855	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3856	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3857	ASMAtomicWriteU64(&u.pau64[iUserTable], 0);
3858	break;
3859
3860	default:
3861	AssertFatalMsgFailed(("enmKind=%d iUser=%d iUserTable=%#x\n", pUserPage->enmKind, pUser->iUser, pUser->iUserTable));
3862	}
3863	PGM_DYNMAP_UNUSED_HINT_VM(pPool->CTX_SUFF(pVM), u.pau64);
3864	}
3865
3866
3867	/**
3868	* Clears all users of a page.
3869	*/
3870	static void pgmPoolTrackClearPageUsers(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3871	{
3872	/*
3873	* Free all the user records.
3874	*/
3875	LogFlow(("pgmPoolTrackClearPageUsers %RGp\n", pPage->GCPhys));
3876
3877	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
3878	uint16_t i = pPage->iUserHead;
3879	while (i != NIL_PGMPOOL_USER_INDEX)
3880	{
3881	/* Clear enter in user table. */
3882	pgmPoolTrackClearPageUser(pPool, pPage, &paUsers[i]);
3883
3884	/* Free it. */
3885	const uint16_t iNext = paUsers[i].iNext;
3886	paUsers[i].iUser = NIL_PGMPOOL_IDX;
3887	paUsers[i].iNext = pPool->iUserFreeHead;
3888	pPool->iUserFreeHead = i;
3889
3890	/* Next. */
3891	i = iNext;
3892	}
3893	pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
3894	}
3895
3896
3897	/**
3898	* Allocates a new physical cross reference extent.
3899	*
3900	* @returns Pointer to the allocated extent on success. NULL if we're out of them.
3901	* @param pVM Pointer to the VM.
3902	* @param piPhysExt Where to store the phys ext index.
3903	*/
3904	PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt)
3905	{
3906	PGM_LOCK_ASSERT_OWNER(pVM);
3907	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3908	uint16_t iPhysExt = pPool->iPhysExtFreeHead;
3909	if (iPhysExt == NIL_PGMPOOL_PHYSEXT_INDEX)
3910	{
3911	STAM_COUNTER_INC(&pPool->StamTrackPhysExtAllocFailures);
3912	return NULL;
3913	}
3914	PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3915	pPool->iPhysExtFreeHead = pPhysExt->iNext;
3916	pPhysExt->iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
3917	*piPhysExt = iPhysExt;
3918	return pPhysExt;
3919	}
3920
3921
3922	/**
3923	* Frees a physical cross reference extent.
3924	*
3925	* @param pVM Pointer to the VM.
3926	* @param iPhysExt The extent to free.
3927	*/
3928	void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt)
3929	{
3930	PGM_LOCK_ASSERT_OWNER(pVM);
3931	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3932	Assert(iPhysExt < pPool->cMaxPhysExts);
3933	PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3934	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3935	{
3936	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3937	pPhysExt->apte[i] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
3938	}
3939	pPhysExt->iNext = pPool->iPhysExtFreeHead;
3940	pPool->iPhysExtFreeHead = iPhysExt;
3941	}
3942
3943
3944	/**
3945	* Frees a physical cross reference extent.
3946	*
3947	* @param pVM Pointer to the VM.
3948	* @param iPhysExt The extent to free.
3949	*/
3950	void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt)
3951	{
3952	PGM_LOCK_ASSERT_OWNER(pVM);
3953	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3954
3955	const uint16_t iPhysExtStart = iPhysExt;
3956	PPGMPOOLPHYSEXT pPhysExt;
3957	do
3958	{
3959	Assert(iPhysExt < pPool->cMaxPhysExts);
3960	pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3961	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3962	{
3963	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3964	pPhysExt->apte[i] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
3965	}
3966
3967	/* next */
3968	iPhysExt = pPhysExt->iNext;
3969	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3970
3971	pPhysExt->iNext = pPool->iPhysExtFreeHead;
3972	pPool->iPhysExtFreeHead = iPhysExtStart;
3973	}
3974
3975
3976	/**
3977	* Insert a reference into a list of physical cross reference extents.
3978	*
3979	* @returns The new tracking data for PGMPAGE.
3980	*
3981	* @param pVM Pointer to the VM.
3982	* @param iPhysExt The physical extent index of the list head.
3983	* @param iShwPT The shadow page table index.
3984	* @param iPte Page table entry
3985	*
3986	*/
3987	static uint16_t pgmPoolTrackPhysExtInsert(PVM pVM, uint16_t iPhysExt, uint16_t iShwPT, uint16_t iPte)
3988	{
3989	PGM_LOCK_ASSERT_OWNER(pVM);
3990	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3991	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3992
3993	/*
3994	* Special common cases.
3995	*/
3996	if (paPhysExts[iPhysExt].aidx[1] == NIL_PGMPOOL_IDX)
3997	{
3998	paPhysExts[iPhysExt].aidx[1] = iShwPT;
3999	paPhysExts[iPhysExt].apte[1] = iPte;
4000	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackAliasedMany);
4001	LogFlow(("pgmPoolTrackPhysExtInsert: %d:{,%d pte %d,}\n", iPhysExt, iShwPT, iPte));
4002	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
4003	}
4004	if (paPhysExts[iPhysExt].aidx[2] == NIL_PGMPOOL_IDX)
4005	{
4006	paPhysExts[iPhysExt].aidx[2] = iShwPT;
4007	paPhysExts[iPhysExt].apte[2] = iPte;
4008	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackAliasedMany);
4009	LogFlow(("pgmPoolTrackPhysExtInsert: %d:{,,%d pte %d}\n", iPhysExt, iShwPT, iPte));
4010	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
4011	}
4012	AssertCompile(RT_ELEMENTS(paPhysExts[iPhysExt].aidx) == 3);
4013
4014	/*
4015	* General treatment.
4016	*/
4017	const uint16_t iPhysExtStart = iPhysExt;
4018	unsigned cMax = 15;
4019	for (;;)
4020	{
4021	Assert(iPhysExt < pPool->cMaxPhysExts);
4022	for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
4023	if (paPhysExts[iPhysExt].aidx[i] == NIL_PGMPOOL_IDX)
4024	{
4025	paPhysExts[iPhysExt].aidx[i] = iShwPT;
4026	paPhysExts[iPhysExt].apte[i] = iPte;
4027	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackAliasedMany);
4028	LogFlow(("pgmPoolTrackPhysExtInsert: %d:{%d pte %d} i=%d cMax=%d\n", iPhysExt, iShwPT, iPte, i, cMax));
4029	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExtStart);
4030	}
4031	if (!--cMax)
4032	{
4033	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackOverflows);
4034	pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
4035	LogFlow(("pgmPoolTrackPhysExtInsert: overflow (1) iShwPT=%d\n", iShwPT));
4036	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
4037	}
4038
4039	/* advance */
4040	iPhysExt = paPhysExts[iPhysExt].iNext;
4041	if (iPhysExt == NIL_PGMPOOL_PHYSEXT_INDEX)
4042	break;
4043	}
4044
4045	/*
4046	* Add another extent to the list.
4047	*/
4048	PPGMPOOLPHYSEXT pNew = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
4049	if (!pNew)
4050	{
4051	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackNoExtentsLeft);
4052	pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
4053	LogFlow(("pgmPoolTrackPhysExtInsert: pgmPoolTrackPhysExtAlloc failed iShwPT=%d\n", iShwPT));
4054	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
4055	}
4056	pNew->iNext = iPhysExtStart;
4057	pNew->aidx[0] = iShwPT;
4058	pNew->apte[0] = iPte;
4059	LogFlow(("pgmPoolTrackPhysExtInsert: added new extent %d:{%d pte %d}->%d\n", iPhysExt, iShwPT, iPte, iPhysExtStart));
4060	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
4061	}
4062
4063
4064	/**
4065	* Add a reference to guest physical page where extents are in use.
4066	*
4067	* @returns The new tracking data for PGMPAGE.
4068	*
4069	* @param pVM Pointer to the VM.
4070	* @param pPhysPage Pointer to the aPages entry in the ram range.
4071	* @param u16 The ram range flags (top 16-bits).
4072	* @param iShwPT The shadow page table index.
4073	* @param iPte Page table entry
4074	*/
4075	uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte)
4076	{
4077	pgmLock(pVM);
4078	if (PGMPOOL_TD_GET_CREFS(u16) != PGMPOOL_TD_CREFS_PHYSEXT)
4079	{
4080	/*
4081	* Convert to extent list.
4082	*/
4083	Assert(PGMPOOL_TD_GET_CREFS(u16) == 1);
4084	uint16_t iPhysExt;
4085	PPGMPOOLPHYSEXT pPhysExt = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
4086	if (pPhysExt)
4087	{
4088	LogFlow(("pgmPoolTrackPhysExtAddref: new extent: %d:{%d, %d}\n", iPhysExt, PGMPOOL_TD_GET_IDX(u16), iShwPT));
4089	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackAliased);
4090	pPhysExt->aidx[0] = PGMPOOL_TD_GET_IDX(u16);
4091	pPhysExt->apte[0] = PGM_PAGE_GET_PTE_INDEX(pPhysPage);
4092	pPhysExt->aidx[1] = iShwPT;
4093	pPhysExt->apte[1] = iPte;
4094	u16 = PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
4095	}
4096	else
4097	u16 = PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
4098	}
4099	else if (u16 != PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED))
4100	{
4101	/*
4102	* Insert into the extent list.
4103	*/
4104	u16 = pgmPoolTrackPhysExtInsert(pVM, PGMPOOL_TD_GET_IDX(u16), iShwPT, iPte);
4105	}
4106	else
4107	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackAliasedLots);
4108	pgmUnlock(pVM);
4109	return u16;
4110	}
4111
4112
4113	/**
4114	* Clear references to guest physical memory.
4115	*
4116	* @param pPool The pool.
4117	* @param pPage The page.
4118	* @param pPhysPage Pointer to the aPages entry in the ram range.
4119	* @param iPte Shadow PTE index
4120	*/
4121	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMPAGE pPhysPage, uint16_t iPte)
4122	{
4123	PVM pVM = pPool->CTX_SUFF(pVM);
4124	const unsigned cRefs = PGM_PAGE_GET_TD_CREFS(pPhysPage);
4125	AssertFatalMsg(cRefs == PGMPOOL_TD_CREFS_PHYSEXT, ("cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
4126
4127	uint16_t iPhysExt = PGM_PAGE_GET_TD_IDX(pPhysPage);
4128	if (iPhysExt != PGMPOOL_TD_IDX_OVERFLOWED)
4129	{
4130	pgmLock(pVM);
4131
4132	uint16_t iPhysExtPrev = NIL_PGMPOOL_PHYSEXT_INDEX;
4133	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
4134	do
4135	{
4136	Assert(iPhysExt < pPool->cMaxPhysExts);
4137
4138	/*
4139	* Look for the shadow page and check if it's all freed.
4140	*/
4141	for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
4142	{
4143	if ( paPhysExts[iPhysExt].aidx[i] == pPage->idx
4144	&& paPhysExts[iPhysExt].apte[i] == iPte)
4145	{
4146	paPhysExts[iPhysExt].aidx[i] = NIL_PGMPOOL_IDX;
4147	paPhysExts[iPhysExt].apte[i] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
4148
4149	for (i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
4150	if (paPhysExts[iPhysExt].aidx[i] != NIL_PGMPOOL_IDX)
4151	{
4152	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d\n", pPhysPage, pPage->idx));
4153	pgmUnlock(pVM);
4154	return;
4155	}
4156
4157	/* we can free the node. */
4158	const uint16_t iPhysExtNext = paPhysExts[iPhysExt].iNext;
4159	if ( iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX
4160	&& iPhysExtNext == NIL_PGMPOOL_PHYSEXT_INDEX)
4161	{
4162	/* lonely node */
4163	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
4164	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d lonely\n", pPhysPage, pPage->idx));
4165	PGM_PAGE_SET_TRACKING(pVM, pPhysPage, 0);
4166	}
4167	else if (iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX)
4168	{
4169	/* head */
4170	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d head\n", pPhysPage, pPage->idx));
4171	PGM_PAGE_SET_TRACKING(pVM, pPhysPage, PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExtNext));
4172	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
4173	}
4174	else
4175	{
4176	/* in list */
4177	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d in list\n", pPhysPage, pPage->idx));
4178	paPhysExts[iPhysExtPrev].iNext = iPhysExtNext;
4179	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
4180	}
4181	iPhysExt = iPhysExtNext;
4182	pgmUnlock(pVM);
4183	return;
4184	}
4185	}
4186
4187	/* next */
4188	iPhysExtPrev = iPhysExt;
4189	iPhysExt = paPhysExts[iPhysExt].iNext;
4190	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
4191
4192	pgmUnlock(pVM);
4193	AssertFatalMsgFailed(("not-found! cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
4194	}
4195	else /* nothing to do */
4196	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage]\n", pPhysPage));
4197	}
4198
4199	/**
4200	* Clear references to guest physical memory.
4201	*
4202	* This is the same as pgmPoolTracDerefGCPhysHint except that the guest
4203	* physical address is assumed to be correct, so the linear search can be
4204	* skipped and we can assert at an earlier point.
4205	*
4206	* @param pPool The pool.
4207	* @param pPage The page.
4208	* @param HCPhys The host physical address corresponding to the guest page.
4209	* @param GCPhys The guest physical address corresponding to HCPhys.
4210	* @param iPte Shadow PTE index
4211	*/
4212	static void pgmPoolTracDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhys, uint16_t iPte)
4213	{
4214	/*
4215	* Lookup the page and check if it checks out before derefing it.
4216	*/
4217	PVM pVM = pPool->CTX_SUFF(pVM);
4218	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhys);
4219	if (pPhysPage)
4220	{
4221	Assert(PGM_PAGE_GET_HCPHYS(pPhysPage));
4222	#ifdef LOG_ENABLED
4223	RTHCPHYS HCPhysPage = PGM_PAGE_GET_HCPHYS(pPhysPage);
4224	Log2(("pgmPoolTracDerefGCPhys %RHp vs %RHp\n", HCPhysPage, HCPhys));
4225	#endif
4226	if (PGM_PAGE_GET_HCPHYS(pPhysPage) == HCPhys)
4227	{
4228	Assert(pPage->cPresent);
4229	Assert(pPool->cPresent);
4230	pPage->cPresent--;
4231	pPool->cPresent--;
4232	pgmTrackDerefGCPhys(pPool, pPage, pPhysPage, iPte);
4233	return;
4234	}
4235
4236	AssertFatalMsgFailed(("HCPhys=%RHp GCPhys=%RGp; found page has HCPhys=%RHp\n",
4237	HCPhys, GCPhys, PGM_PAGE_GET_HCPHYS(pPhysPage)));
4238	}
4239	AssertFatalMsgFailed(("HCPhys=%RHp GCPhys=%RGp\n", HCPhys, GCPhys));
4240	}
4241
4242
4243	/**
4244	* Clear references to guest physical memory.
4245	*
4246	* @param pPool The pool.
4247	* @param pPage The page.
4248	* @param HCPhys The host physical address corresponding to the guest page.
4249	* @param GCPhysHint The guest physical address which may corresponding to HCPhys.
4250	* @param iPte Shadow pte index
4251	*/
4252	void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte)
4253	{
4254	Log4(("pgmPoolTracDerefGCPhysHint %RHp %RGp\n", HCPhys, GCPhysHint));
4255
4256	/*
4257	* Try the hint first.
4258	*/
4259	RTHCPHYS HCPhysHinted;
4260	PVM pVM = pPool->CTX_SUFF(pVM);
4261	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysHint);
4262	if (pPhysPage)
4263	{
4264	HCPhysHinted = PGM_PAGE_GET_HCPHYS(pPhysPage);
4265	Assert(HCPhysHinted);
4266	if (HCPhysHinted == HCPhys)
4267	{
4268	Assert(pPage->cPresent);
4269	Assert(pPool->cPresent);
4270	pPage->cPresent--;
4271	pPool->cPresent--;
4272	pgmTrackDerefGCPhys(pPool, pPage, pPhysPage, iPte);
4273	return;
4274	}
4275	}
4276	else
4277	HCPhysHinted = UINT64_C(0xdeadbeefdeadbeef);
4278
4279	/*
4280	* Damn, the hint didn't work. We'll have to do an expensive linear search.
4281	*/
4282	STAM_COUNTER_INC(&pPool->StatTrackLinearRamSearches);
4283	PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRangesX);
4284	while (pRam)
4285	{
4286	unsigned iPage = pRam->cb >> PAGE_SHIFT;
4287	while (iPage-- > 0)
4288	{
4289	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
4290	{
4291	Log4(("pgmPoolTracDerefGCPhysHint: Linear HCPhys=%RHp GCPhysHint=%RGp GCPhysReal=%RGp\n",
4292	HCPhys, GCPhysHint, pRam->GCPhys + (iPage << PAGE_SHIFT)));
4293	Assert(pPage->cPresent);
4294	Assert(pPool->cPresent);
4295	pPage->cPresent--;
4296	pPool->cPresent--;
4297	pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage], iPte);
4298	return;
4299	}
4300	}
4301	pRam = pRam->CTX_SUFF(pNext);
4302	}
4303
4304	AssertFatalMsgFailed(("HCPhys=%RHp GCPhysHint=%RGp (Hinted page has HCPhys = %RHp)\n", HCPhys, GCPhysHint, HCPhysHinted));
4305	}
4306
4307
4308	/**
4309	* Clear references to guest physical memory in a 32-bit / 32-bit page table.
4310	*
4311	* @param pPool The pool.
4312	* @param pPage The page.
4313	* @param pShwPT The shadow page table (mapping of the page).
4314	* @param pGstPT The guest page table.
4315	*/
4316	DECLINLINE(void) pgmPoolTrackDerefPT32Bit32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT, PCX86PT pGstPT)
4317	{
4318	RTGCPHYS32 const fPgMask = pPage->fA20Enabled ? X86_PTE_PG_MASK : X86_PTE_PG_MASK & ~RT_BIT_32(20);
4319	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
4320	{
4321	Assert(!(pShwPT->a[i].u & RT_BIT_32(10)));
4322	if (pShwPT->a[i].n.u1Present)
4323	{
4324	Log4(("pgmPoolTrackDerefPT32Bit32Bit: i=%d pte=%RX32 hint=%RX32\n",
4325	i, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK));
4326	pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & fPgMask, i);
4327	if (!pPage->cPresent)
4328	break;
4329	}
4330	}
4331	}
4332
4333
4334	/**
4335	* Clear references to guest physical memory in a PAE / 32-bit page table.
4336	*
4337	* @param pPool The pool.
4338	* @param pPage The page.
4339	* @param pShwPT The shadow page table (mapping of the page).
4340	* @param pGstPT The guest page table (just a half one).
4341	*/
4342	DECLINLINE(void) pgmPoolTrackDerefPTPae32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PT pGstPT)
4343	{
4344	RTGCPHYS32 const fPgMask = pPage->fA20Enabled ? X86_PTE_PG_MASK : X86_PTE_PG_MASK & ~RT_BIT_32(20);
4345	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
4346	{
4347	Assert( (PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & UINT64_C(0x7ff0000000000400)) == 0
4348	\|\| (PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & UINT64_C(0x7ff0000000000400)) == UINT64_C(0x7ff0000000000000));
4349	if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
4350	{
4351	Log4(("pgmPoolTrackDerefPTPae32Bit: i=%d pte=%RX64 hint=%RX32\n",
4352	i, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pGstPT->a[i].u & X86_PTE_PG_MASK));
4353	pgmPoolTracDerefGCPhysHint(pPool, pPage, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pGstPT->a[i].u & fPgMask, i);
4354	if (!pPage->cPresent)
4355	break;
4356	}
4357	}
4358	}
4359
4360
4361	/**
4362	* Clear references to guest physical memory in a PAE / PAE page table.
4363	*
4364	* @param pPool The pool.
4365	* @param pPage The page.
4366	* @param pShwPT The shadow page table (mapping of the page).
4367	* @param pGstPT The guest page table.
4368	*/
4369	DECLINLINE(void) pgmPoolTrackDerefPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PTPAE pGstPT)
4370	{
4371	RTGCPHYS const fPgMask = pPage->fA20Enabled ? X86_PTE_PAE_PG_MASK : X86_PTE_PAE_PG_MASK & ~RT_BIT_64(20);
4372	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
4373	{
4374	Assert( (PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & UINT64_C(0x7ff0000000000400)) == 0
4375	\|\| (PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & UINT64_C(0x7ff0000000000400)) == UINT64_C(0x7ff0000000000000));
4376	if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
4377	{
4378	Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX32 hint=%RX32\n",
4379	i, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK));
4380	pgmPoolTracDerefGCPhysHint(pPool, pPage, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pGstPT->a[i].u & fPgMask, i);
4381	if (!pPage->cPresent)
4382	break;
4383	}
4384	}
4385	}
4386
4387
4388	/**
4389	* Clear references to guest physical memory in a 32-bit / 4MB page table.
4390	*
4391	* @param pPool The pool.
4392	* @param pPage The page.
4393	* @param pShwPT The shadow page table (mapping of the page).
4394	*/
4395	DECLINLINE(void) pgmPoolTrackDerefPT32Bit4MB(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT)
4396	{
4397	RTGCPHYS const GCPhysA20Mask = pPage->fA20Enabled ? UINT64_MAX : ~RT_BIT_64(20);
4398	RTGCPHYS GCPhys = pPage->GCPhys + PAGE_SIZE * pPage->iFirstPresent;
4399	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
4400	{
4401	Assert(!(pShwPT->a[i].u & RT_BIT_32(10)));
4402	if (pShwPT->a[i].n.u1Present)
4403	{
4404	Log4(("pgmPoolTrackDerefPT32Bit4MB: i=%d pte=%RX32 GCPhys=%RGp\n",
4405	i, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys));
4406	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys & GCPhysA20Mask, i);
4407	if (!pPage->cPresent)
4408	break;
4409	}
4410	}
4411	}
4412
4413
4414	/**
4415	* Clear references to guest physical memory in a PAE / 2/4MB page table.
4416	*
4417	* @param pPool The pool.
4418	* @param pPage The page.
4419	* @param pShwPT The shadow page table (mapping of the page).
4420	*/
4421	DECLINLINE(void) pgmPoolTrackDerefPTPaeBig(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT)
4422	{
4423	RTGCPHYS const GCPhysA20Mask = pPage->fA20Enabled ? UINT64_MAX : ~RT_BIT_64(20);
4424	RTGCPHYS GCPhys = pPage->GCPhys + PAGE_SIZE * pPage->iFirstPresent;
4425	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
4426	{
4427	Assert( (PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & UINT64_C(0x7ff0000000000400)) == 0
4428	\|\| (PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & UINT64_C(0x7ff0000000000400)) == UINT64_C(0x7ff0000000000000));
4429	if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
4430	{
4431	Log4(("pgmPoolTrackDerefPTPaeBig: i=%d pte=%RX64 hint=%RGp\n",
4432	i, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), GCPhys));
4433	pgmPoolTracDerefGCPhys(pPool, pPage, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), GCPhys & GCPhysA20Mask, i);
4434	if (!pPage->cPresent)
4435	break;
4436	}
4437	}
4438	}
4439
4440
4441	/**
4442	* Clear references to shadowed pages in an EPT page table.
4443	*
4444	* @param pPool The pool.
4445	* @param pPage The page.
4446	* @param pShwPML4 The shadow page directory pointer table (mapping of the page).
4447	*/
4448	DECLINLINE(void) pgmPoolTrackDerefPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPT pShwPT)
4449	{
4450	RTGCPHYS const GCPhysA20Mask = pPage->fA20Enabled ? UINT64_MAX : ~RT_BIT_64(20);
4451	RTGCPHYS GCPhys = pPage->GCPhys + PAGE_SIZE * pPage->iFirstPresent;
4452	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
4453	{
4454	Assert((pShwPT->a[i].u & UINT64_C(0xfff0000000000f80)) == 0);
4455	if (pShwPT->a[i].n.u1Present)
4456	{
4457	Log4(("pgmPoolTrackDerefPTEPT: i=%d pte=%RX64 GCPhys=%RX64\n",
4458	i, pShwPT->a[i].u & EPT_PTE_PG_MASK, pPage->GCPhys));
4459	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & EPT_PTE_PG_MASK, GCPhys & GCPhysA20Mask, i);
4460	if (!pPage->cPresent)
4461	break;
4462	}
4463	}
4464	}
4465
4466
4467	/**
4468	* Clear references to shadowed pages in a 32 bits page directory.
4469	*
4470	* @param pPool The pool.
4471	* @param pPage The page.
4472	* @param pShwPD The shadow page directory (mapping of the page).
4473	*/
4474	DECLINLINE(void) pgmPoolTrackDerefPD(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PD pShwPD)
4475	{
4476	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
4477	{
4478	Assert(!(pShwPD->a[i].u & RT_BIT_32(9)));
4479	if ( pShwPD->a[i].n.u1Present
4480	&& !(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING)
4481	)
4482	{
4483	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PG_MASK);
4484	if (pSubPage)
4485	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4486	else
4487	AssertFatalMsgFailed(("%x\n", pShwPD->a[i].u & X86_PDE_PG_MASK));
4488	}
4489	}
4490	}
4491
4492
4493	/**
4494	* Clear references to shadowed pages in a PAE (legacy or 64 bits) page directory.
4495	*
4496	* @param pPool The pool.
4497	* @param pPage The page.
4498	* @param pShwPD The shadow page directory (mapping of the page).
4499	*/
4500	DECLINLINE(void) pgmPoolTrackDerefPDPae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPAE pShwPD)
4501	{
4502	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
4503	{
4504	if ( pShwPD->a[i].n.u1Present
4505	&& !(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING))
4506	{
4507	#ifdef PGM_WITH_LARGE_PAGES
4508	if (pShwPD->a[i].b.u1Size)
4509	{
4510	Log4(("pgmPoolTrackDerefPDPae: i=%d pde=%RX64 GCPhys=%RX64\n",
4511	i, pShwPD->a[i].u & X86_PDE2M_PAE_PG_MASK, pPage->GCPhys));
4512	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPD->a[i].u & X86_PDE2M_PAE_PG_MASK,
4513	pPage->GCPhys + i * 2 * _1M /* pPage->GCPhys = base address of the memory described by the PD */,
4514	i);
4515	}
4516	else
4517	#endif
4518	{
4519	Assert((pShwPD->a[i].u & (X86_PDE_PAE_MBZ_MASK_NX \| UINT64_C(0x7ff0000000000200))) == 0);
4520	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PAE_PG_MASK);
4521	if (pSubPage)
4522	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4523	else
4524	AssertFatalMsgFailed(("%RX64\n", pShwPD->a[i].u & X86_PDE_PAE_PG_MASK));
4525	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4526	}
4527	}
4528	}
4529	}
4530
4531
4532	/**
4533	* Clear references to shadowed pages in a PAE page directory pointer table.
4534	*
4535	* @param pPool The pool.
4536	* @param pPage The page.
4537	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
4538	*/
4539	DECLINLINE(void) pgmPoolTrackDerefPDPTPae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPT pShwPDPT)
4540	{
4541	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4542	{
4543	Assert((pShwPDPT->a[i].u & (X86_PDPE_PAE_MBZ_MASK \| UINT64_C(0x7ff0000000000200))) == 0);
4544	if ( pShwPDPT->a[i].n.u1Present
4545	&& !(pShwPDPT->a[i].u & PGM_PLXFLAGS_MAPPING)
4546	)
4547	{
4548	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & X86_PDPE_PG_MASK);
4549	if (pSubPage)
4550	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4551	else
4552	AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & X86_PDPE_PG_MASK));
4553	}
4554	}
4555	}
4556
4557
4558	/**
4559	* Clear references to shadowed pages in a 64-bit page directory pointer table.
4560	*
4561	* @param pPool The pool.
4562	* @param pPage The page.
4563	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
4564	*/
4565	DECLINLINE(void) pgmPoolTrackDerefPDPT64Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPT pShwPDPT)
4566	{
4567	for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
4568	{
4569	Assert((pShwPDPT->a[i].u & (X86_PDPE_LM_MBZ_MASK_NX \| UINT64_C(0x7ff0000000000200))) == 0);
4570	if (pShwPDPT->a[i].n.u1Present)
4571	{
4572	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & X86_PDPE_PG_MASK);
4573	if (pSubPage)
4574	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4575	else
4576	AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & X86_PDPE_PG_MASK));
4577	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4578	}
4579	}
4580	}
4581
4582
4583	/**
4584	* Clear references to shadowed pages in a 64-bit level 4 page table.
4585	*
4586	* @param pPool The pool.
4587	* @param pPage The page.
4588	* @param pShwPML4 The shadow page directory pointer table (mapping of the page).
4589	*/
4590	DECLINLINE(void) pgmPoolTrackDerefPML464Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PML4 pShwPML4)
4591	{
4592	for (unsigned i = 0; i < RT_ELEMENTS(pShwPML4->a); i++)
4593	{
4594	Assert((pShwPML4->a[i].u & (X86_PML4E_MBZ_MASK_NX \| UINT64_C(0x7ff0000000000200))) == 0);
4595	if (pShwPML4->a[i].n.u1Present)
4596	{
4597	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPML4->a[i].u & X86_PDPE_PG_MASK);
4598	if (pSubPage)
4599	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4600	else
4601	AssertFatalMsgFailed(("%RX64\n", pShwPML4->a[i].u & X86_PML4E_PG_MASK));
4602	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4603	}
4604	}
4605	}
4606
4607
4608	/**
4609	* Clear references to shadowed pages in an EPT page directory.
4610	*
4611	* @param pPool The pool.
4612	* @param pPage The page.
4613	* @param pShwPD The shadow page directory (mapping of the page).
4614	*/
4615	DECLINLINE(void) pgmPoolTrackDerefPDEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPD pShwPD)
4616	{
4617	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
4618	{
4619	Assert((pShwPD->a[i].u & UINT64_C(0xfff0000000000f80)) == 0);
4620	if (pShwPD->a[i].n.u1Present)
4621	{
4622	#ifdef PGM_WITH_LARGE_PAGES
4623	if (pShwPD->a[i].b.u1Size)
4624	{
4625	Log4(("pgmPoolTrackDerefPDEPT: i=%d pde=%RX64 GCPhys=%RX64\n",
4626	i, pShwPD->a[i].u & X86_PDE2M_PAE_PG_MASK, pPage->GCPhys));
4627	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPD->a[i].u & X86_PDE2M_PAE_PG_MASK,
4628	pPage->GCPhys + i * 2 * _1M /* pPage->GCPhys = base address of the memory described by the PD */,
4629	i);
4630	}
4631	else
4632	#endif
4633	{
4634	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & EPT_PDE_PG_MASK);
4635	if (pSubPage)
4636	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4637	else
4638	AssertFatalMsgFailed(("%RX64\n", pShwPD->a[i].u & EPT_PDE_PG_MASK));
4639	}
4640	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4641	}
4642	}
4643	}
4644
4645
4646	/**
4647	* Clear references to shadowed pages in an EPT page directory pointer table.
4648	*
4649	* @param pPool The pool.
4650	* @param pPage The page.
4651	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
4652	*/
4653	DECLINLINE(void) pgmPoolTrackDerefPDPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPDPT pShwPDPT)
4654	{
4655	for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
4656	{
4657	Assert((pShwPDPT->a[i].u & UINT64_C(0xfff0000000000f80)) == 0);
4658	if (pShwPDPT->a[i].n.u1Present)
4659	{
4660	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & EPT_PDPTE_PG_MASK);
4661	if (pSubPage)
4662	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4663	else
4664	AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & EPT_PDPTE_PG_MASK));
4665	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4666	}
4667	}
4668	}
4669
4670
4671	/**
4672	* Clears all references made by this page.
4673	*
4674	* This includes other shadow pages and GC physical addresses.
4675	*
4676	* @param pPool The pool.
4677	* @param pPage The page.
4678	*/
4679	static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4680	{
4681	/*
4682	* Map the shadow page and take action according to the page kind.
4683	*/
4684	PVM pVM = pPool->CTX_SUFF(pVM);
4685	void *pvShw = PGMPOOL_PAGE_2_PTR(pVM, pPage);
4686	switch (pPage->enmKind)
4687	{
4688	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
4689	{
4690	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4691	void *pvGst;
4692	int rc = PGM_GCPHYS_2_PTR(pVM, pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
4693	pgmPoolTrackDerefPT32Bit32Bit(pPool, pPage, (PX86PT)pvShw, (PCX86PT)pvGst);
4694	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
4695	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4696	break;
4697	}
4698
4699	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
4700	{
4701	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4702	void *pvGst;
4703	int rc = PGM_GCPHYS_2_PTR_EX(pVM, pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
4704	pgmPoolTrackDerefPTPae32Bit(pPool, pPage, (PPGMSHWPTPAE)pvShw, (PCX86PT)pvGst);
4705	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
4706	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4707	break;
4708	}
4709
4710	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
4711	{
4712	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4713	void *pvGst;
4714	int rc = PGM_GCPHYS_2_PTR(pVM, pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
4715	pgmPoolTrackDerefPTPaePae(pPool, pPage, (PPGMSHWPTPAE)pvShw, (PCX86PTPAE)pvGst);
4716	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
4717	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4718	break;
4719	}
4720
4721	case PGMPOOLKIND_32BIT_PT_FOR_PHYS: /* treat it like a 4 MB page */
4722	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
4723	{
4724	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4725	pgmPoolTrackDerefPT32Bit4MB(pPool, pPage, (PX86PT)pvShw);
4726	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4727	break;
4728	}
4729
4730	case PGMPOOLKIND_PAE_PT_FOR_PHYS: /* treat it like a 2 MB page */
4731	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
4732	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
4733	{
4734	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4735	pgmPoolTrackDerefPTPaeBig(pPool, pPage, (PPGMSHWPTPAE)pvShw);
4736	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4737	break;
4738	}
4739
4740	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
4741	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
4742	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
4743	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
4744	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
4745	case PGMPOOLKIND_PAE_PD_PHYS:
4746	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
4747	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
4748	pgmPoolTrackDerefPDPae(pPool, pPage, (PX86PDPAE)pvShw);
4749	break;
4750
4751	case PGMPOOLKIND_32BIT_PD_PHYS:
4752	case PGMPOOLKIND_32BIT_PD:
4753	pgmPoolTrackDerefPD(pPool, pPage, (PX86PD)pvShw);
4754	break;
4755
4756	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
4757	case PGMPOOLKIND_PAE_PDPT:
4758	case PGMPOOLKIND_PAE_PDPT_PHYS:
4759	pgmPoolTrackDerefPDPTPae(pPool, pPage, (PX86PDPT)pvShw);
4760	break;
4761
4762	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
4763	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
4764	pgmPoolTrackDerefPDPT64Bit(pPool, pPage, (PX86PDPT)pvShw);
4765	break;
4766
4767	case PGMPOOLKIND_64BIT_PML4:
4768	pgmPoolTrackDerefPML464Bit(pPool, pPage, (PX86PML4)pvShw);
4769	break;
4770
4771	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
4772	pgmPoolTrackDerefPTEPT(pPool, pPage, (PEPTPT)pvShw);
4773	break;
4774
4775	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
4776	pgmPoolTrackDerefPDEPT(pPool, pPage, (PEPTPD)pvShw);
4777	break;
4778
4779	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
4780	pgmPoolTrackDerefPDPTEPT(pPool, pPage, (PEPTPDPT)pvShw);
4781	break;
4782
4783	default:
4784	AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
4785	}
4786
4787	/* paranoia, clear the shadow page. Remove this laser (i.e. let Alloc and ClearAll do it). */
4788	STAM_PROFILE_START(&pPool->StatZeroPage, z);
4789	ASMMemZeroPage(pvShw);
4790	STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
4791	pPage->fZeroed = true;
4792	Assert(!pPage->cPresent);
4793	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvShw);
4794	}
4795
4796
4797	/**
4798	* Flushes a pool page.
4799	*
4800	* This moves the page to the free list after removing all user references to it.
4801	*
4802	* @returns VBox status code.
4803	* @retval VINF_SUCCESS on success.
4804	* @param pPool The pool.
4805	* @param HCPhys The HC physical address of the shadow page.
4806	* @param fFlush Flush the TLBS when required (should only be false in very specific use cases!!)
4807	*/
4808	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush)
4809	{
4810	PVM pVM = pPool->CTX_SUFF(pVM);
4811	bool fFlushRequired = false;
4812
4813	int rc = VINF_SUCCESS;
4814	STAM_PROFILE_START(&pPool->StatFlushPage, f);
4815	LogFlow(("pgmPoolFlushPage: pPage=%p:{.Key=%RHp, .idx=%d, .enmKind=%s, .GCPhys=%RGp}\n",
4816	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
4817
4818	/*
4819	* Reject any attempts at flushing any of the special root pages (shall
4820	* not happen).
4821	*/
4822	AssertMsgReturn(pPage->idx >= PGMPOOL_IDX_FIRST,
4823	("pgmPoolFlushPage: special root page, rejected. enmKind=%s idx=%d\n",
4824	pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx),
4825	VINF_SUCCESS);
4826
4827	pgmLock(pVM);
4828
4829	/*
4830	* Quietly reject any attempts at flushing the currently active shadow CR3 mapping
4831	*/
4832	if (pgmPoolIsPageLocked(pPage))
4833	{
4834	AssertMsg( pPage->enmKind == PGMPOOLKIND_64BIT_PML4
4835	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PDPT
4836	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PDPT_FOR_32BIT
4837	\|\| pPage->enmKind == PGMPOOLKIND_32BIT_PD
4838	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD_FOR_PAE_PD
4839	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD
4840	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD
4841	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD
4842	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD
4843	\|\| pPage->enmKind == PGMPOOLKIND_ROOT_NESTED,
4844	("Can't free the shadow CR3! (%RHp vs %RHp kind=%d\n", PGMGetHyperCR3(VMMGetCpu(pVM)), pPage->Core.Key, pPage->enmKind));
4845	Log(("pgmPoolFlushPage: current active shadow CR3, rejected. enmKind=%s idx=%d\n", pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx));
4846	pgmUnlock(pVM);
4847	return VINF_SUCCESS;
4848	}
4849
4850	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
4851	/* Start a subset so we won't run out of mapping space. */
4852	PVMCPU pVCpu = VMMGetCpu(pVM);
4853	uint32_t iPrevSubset = PGMRZDynMapPushAutoSubset(pVCpu);
4854	#endif
4855
4856	/*
4857	* Mark the page as being in need of an ASMMemZeroPage().
4858	*/
4859	pPage->fZeroed = false;
4860
4861	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4862	if (pPage->fDirty)
4863	pgmPoolFlushDirtyPage(pVM, pPool, pPage->idxDirtyEntry, false /* do not remove */);
4864	#endif
4865
4866	/* If there are any users of this table, then we must issue a tlb flush on all VCPUs. */
4867	if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
4868	fFlushRequired = true;
4869
4870	/*
4871	* Clear the page.
4872	*/
4873	pgmPoolTrackClearPageUsers(pPool, pPage);
4874	STAM_PROFILE_START(&pPool->StatTrackDeref,a);
4875	pgmPoolTrackDeref(pPool, pPage);
4876	STAM_PROFILE_STOP(&pPool->StatTrackDeref,a);
4877
4878	/*
4879	* Flush it from the cache.
4880	*/
4881	pgmPoolCacheFlushPage(pPool, pPage);
4882
4883	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
4884	/* Heavy stuff done. */
4885	PGMRZDynMapPopAutoSubset(pVCpu, iPrevSubset);
4886	#endif
4887
4888	/*
4889	* Deregistering the monitoring.
4890	*/
4891	if (pPage->fMonitored)
4892	rc = pgmPoolMonitorFlush(pPool, pPage);
4893
4894	/*
4895	* Free the page.
4896	*/
4897	Assert(pPage->iNext == NIL_PGMPOOL_IDX);
4898	pPage->iNext = pPool->iFreeHead;
4899	pPool->iFreeHead = pPage->idx;
4900	pPage->enmKind = PGMPOOLKIND_FREE;
4901	pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
4902	pPage->GCPhys = NIL_RTGCPHYS;
4903	pPage->fReusedFlushPending = false;
4904
4905	pPool->cUsedPages--;
4906
4907	/* Flush the TLBs of all VCPUs if required. */
4908	if ( fFlushRequired
4909	&& fFlush)
4910	{
4911	PGM_INVL_ALL_VCPU_TLBS(pVM);
4912	}
4913
4914	pgmUnlock(pVM);
4915	STAM_PROFILE_STOP(&pPool->StatFlushPage, f);
4916	return rc;
4917	}
4918
4919
4920	/**
4921	* Frees a usage of a pool page.
4922	*
4923	* The caller is responsible to updating the user table so that it no longer
4924	* references the shadow page.
4925	*
4926	* @param pPool The pool.
4927	* @param HCPhys The HC physical address of the shadow page.
4928	* @param iUser The shadow page pool index of the user table.
4929	* NIL_PGMPOOL_IDX for root pages.
4930	* @param iUserTable The index into the user table (shadowed). Ignored if
4931	* root page.
4932	*/
4933	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
4934	{
4935	PVM pVM = pPool->CTX_SUFF(pVM);
4936
4937	STAM_PROFILE_START(&pPool->StatFree, a);
4938	LogFlow(("pgmPoolFreeByPage: pPage=%p:{.Key=%RHp, .idx=%d, enmKind=%s} iUser=%d iUserTable=%#x\n",
4939	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), iUser, iUserTable));
4940	AssertReturnVoid(pPage->idx >= PGMPOOL_IDX_FIRST); /* paranoia (#6349) */
4941
4942	pgmLock(pVM);
4943	if (iUser != NIL_PGMPOOL_IDX)
4944	pgmPoolTrackFreeUser(pPool, pPage, iUser, iUserTable);
4945	if (!pPage->fCached)
4946	pgmPoolFlushPage(pPool, pPage);
4947	pgmUnlock(pVM);
4948	STAM_PROFILE_STOP(&pPool->StatFree, a);
4949	}
4950
4951
4952	/**
4953	* Makes one or more free page free.
4954	*
4955	* @returns VBox status code.
4956	* @retval VINF_SUCCESS on success.
4957	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
4958	*
4959	* @param pPool The pool.
4960	* @param enmKind Page table kind
4961	* @param iUser The user of the page.
4962	*/
4963	static int pgmPoolMakeMoreFreePages(PPGMPOOL pPool, PGMPOOLKIND enmKind, uint16_t iUser)
4964	{
4965	PVM pVM = pPool->CTX_SUFF(pVM);
4966	LogFlow(("pgmPoolMakeMoreFreePages: enmKind=%d iUser=%d\n", enmKind, iUser));
4967	NOREF(enmKind);
4968
4969	/*
4970	* If the pool isn't full grown yet, expand it.
4971	*/
4972	if ( pPool->cCurPages < pPool->cMaxPages
4973	#if defined(IN_RC)
4974	/* Hack alert: we can't deal with jumps to ring 3 when called from MapCR3 and allocating pages for PAE PDs. */
4975	&& enmKind != PGMPOOLKIND_PAE_PD_FOR_PAE_PD
4976	&& (enmKind < PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD \|\| enmKind > PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD)
4977	#endif
4978	)
4979	{
4980	STAM_PROFILE_ADV_SUSPEND(&pPool->StatAlloc, a);
4981	#ifdef IN_RING3
4982	int rc = PGMR3PoolGrow(pVM);
4983	#else
4984	int rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PGM_POOL_GROW, 0);
4985	#endif
4986	if (RT_FAILURE(rc))
4987	return rc;
4988	STAM_PROFILE_ADV_RESUME(&pPool->StatAlloc, a);
4989	if (pPool->iFreeHead != NIL_PGMPOOL_IDX)
4990	return VINF_SUCCESS;
4991	}
4992
4993	/*
4994	* Free one cached page.
4995	*/
4996	return pgmPoolCacheFreeOne(pPool, iUser);
4997	}
4998
4999
5000	/**
5001	* Allocates a page from the pool.
5002	*
5003	* This page may actually be a cached page and not in need of any processing
5004	* on the callers part.
5005	*
5006	* @returns VBox status code.
5007	* @retval VINF_SUCCESS if a NEW page was allocated.
5008	* @retval VINF_PGM_CACHED_PAGE if a CACHED page was returned.
5009	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
5010	*
5011	* @param pVM Pointer to the VM.
5012	* @param GCPhys The GC physical address of the page we're gonna shadow.
5013	* For 4MB and 2MB PD entries, it's the first address the
5014	* shadow PT is covering.
5015	* @param enmKind The kind of mapping.
5016	* @param enmAccess Access type for the mapping (only relevant for big pages)
5017	* @param fA20Enabled Whether the A20 gate is enabled or not.
5018	* @param iUser The shadow page pool index of the user table. Root
5019	* pages should pass NIL_PGMPOOL_IDX.
5020	* @param iUserTable The index into the user table (shadowed). Ignored for
5021	* root pages (iUser == NIL_PGMPOOL_IDX).
5022	* @param fLockPage Lock the page
5023	* @param ppPage Where to store the pointer to the page. NULL is stored here on failure.
5024	*/
5025	int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
5026	uint16_t iUser, uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage)
5027	{
5028	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
5029	STAM_PROFILE_ADV_START(&pPool->StatAlloc, a);
5030	LogFlow(("pgmPoolAlloc: GCPhys=%RGp enmKind=%s iUser=%d iUserTable=%#x\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable));
5031	*ppPage = NULL;
5032	/** @todo CSAM/PGMPrefetchPage messes up here during CSAMR3CheckGates
5033	* (TRPMR3SyncIDT) because of FF priority. Try fix that?
5034	* Assert(!(pVM->pgm.s.fGlobalSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)); */
5035
5036	pgmLock(pVM);
5037
5038	if (pPool->fCacheEnabled)
5039	{
5040	int rc2 = pgmPoolCacheAlloc(pPool, GCPhys, enmKind, enmAccess, fA20Enabled, iUser, iUserTable, ppPage);
5041	if (RT_SUCCESS(rc2))
5042	{
5043	if (fLockPage)
5044	pgmPoolLockPage(pPool, *ppPage);
5045	pgmUnlock(pVM);
5046	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
5047	LogFlow(("pgmPoolAlloc: cached returns %Rrc ppPage=%p:{.Key=%RHp, .idx=%d}\n", rc2, ppPage, (ppPage)->Core.Key, (ppPage)->idx));
5048	return rc2;
5049	}
5050	}
5051
5052	/*
5053	* Allocate a new one.
5054	*/
5055	int rc = VINF_SUCCESS;
5056	uint16_t iNew = pPool->iFreeHead;
5057	if (iNew == NIL_PGMPOOL_IDX)
5058	{
5059	rc = pgmPoolMakeMoreFreePages(pPool, enmKind, iUser);
5060	if (RT_FAILURE(rc))
5061	{
5062	pgmUnlock(pVM);
5063	Log(("pgmPoolAlloc: returns %Rrc (Free)\n", rc));
5064	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
5065	return rc;
5066	}
5067	iNew = pPool->iFreeHead;
5068	AssertReleaseReturn(iNew != NIL_PGMPOOL_IDX, VERR_PGM_POOL_IPE);
5069	}
5070
5071	/* unlink the free head */
5072	PPGMPOOLPAGE pPage = &pPool->aPages[iNew];
5073	pPool->iFreeHead = pPage->iNext;
5074	pPage->iNext = NIL_PGMPOOL_IDX;
5075
5076	/*
5077	* Initialize it.
5078	*/
5079	pPool->cUsedPages++; /* physical handler registration / pgmPoolTrackFlushGCPhysPTsSlow requirement. */
5080	pPage->enmKind = enmKind;
5081	pPage->enmAccess = enmAccess;
5082	pPage->GCPhys = GCPhys;
5083	pPage->fA20Enabled = fA20Enabled;
5084	pPage->fSeenNonGlobal = false; /* Set this to 'true' to disable this feature. */
5085	pPage->fMonitored = false;
5086	pPage->fCached = false;
5087	pPage->fDirty = false;
5088	pPage->fReusedFlushPending = false;
5089	pPage->cModifications = 0;
5090	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
5091	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
5092	pPage->cPresent = 0;
5093	pPage->iFirstPresent = NIL_PGMPOOL_PRESENT_INDEX;
5094	pPage->idxDirtyEntry = 0;
5095	pPage->GCPtrLastAccessHandlerFault = NIL_RTGCPTR;
5096	pPage->GCPtrLastAccessHandlerRip = NIL_RTGCPTR;
5097	pPage->cLastAccessHandler = 0;
5098	pPage->cLocked = 0;
5099	# ifdef VBOX_STRICT
5100	pPage->GCPtrDirtyFault = NIL_RTGCPTR;
5101	# endif
5102
5103	/*
5104	* Insert into the tracking and cache. If this fails, free the page.
5105	*/
5106	int rc3 = pgmPoolTrackInsert(pPool, pPage, GCPhys, iUser, iUserTable);
5107	if (RT_FAILURE(rc3))
5108	{
5109	pPool->cUsedPages--;
5110	pPage->enmKind = PGMPOOLKIND_FREE;
5111	pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
5112	pPage->GCPhys = NIL_RTGCPHYS;
5113	pPage->iNext = pPool->iFreeHead;
5114	pPool->iFreeHead = pPage->idx;
5115	pgmUnlock(pVM);
5116	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
5117	Log(("pgmPoolAlloc: returns %Rrc (Insert)\n", rc3));
5118	return rc3;
5119	}
5120
5121	/*
5122	* Commit the allocation, clear the page and return.
5123	*/
5124	#ifdef VBOX_WITH_STATISTICS
5125	if (pPool->cUsedPages > pPool->cUsedPagesHigh)
5126	pPool->cUsedPagesHigh = pPool->cUsedPages;
5127	#endif
5128
5129	if (!pPage->fZeroed)
5130	{
5131	STAM_PROFILE_START(&pPool->StatZeroPage, z);
5132	void *pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
5133	ASMMemZeroPage(pv);
5134	STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
5135	}
5136
5137	*ppPage = pPage;
5138	if (fLockPage)
5139	pgmPoolLockPage(pPool, pPage);
5140	pgmUnlock(pVM);
5141	LogFlow(("pgmPoolAlloc: returns %Rrc *ppPage=%p:{.Key=%RHp, .idx=%d, .fCached=%RTbool, .fMonitored=%RTbool}\n",
5142	rc, pPage, pPage->Core.Key, pPage->idx, pPage->fCached, pPage->fMonitored));
5143	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
5144	return rc;
5145	}
5146
5147
5148	/**
5149	* Frees a usage of a pool page.
5150	*
5151	* @param pVM Pointer to the VM.
5152	* @param HCPhys The HC physical address of the shadow page.
5153	* @param iUser The shadow page pool index of the user table.
5154	* NIL_PGMPOOL_IDX if root page.
5155	* @param iUserTable The index into the user table (shadowed). Ignored if
5156	* root page.
5157	*/
5158	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable)
5159	{
5160	LogFlow(("pgmPoolFree: HCPhys=%RHp iUser=%d iUserTable=%#x\n", HCPhys, iUser, iUserTable));
5161	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
5162	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, HCPhys), iUser, iUserTable);
5163	}
5164
5165
5166	/**
5167	* Internal worker for finding a 'in-use' shadow page give by it's physical address.
5168	*
5169	* @returns Pointer to the shadow page structure.
5170	* @param pPool The pool.
5171	* @param HCPhys The HC physical address of the shadow page.
5172	*/
5173	PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
5174	{
5175	PGM_LOCK_ASSERT_OWNER(pPool->CTX_SUFF(pVM));
5176
5177	/*
5178	* Look up the page.
5179	*/
5180	PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
5181
5182	AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%RHp pPage=%p idx=%d\n", HCPhys, pPage, (pPage) ? pPage->idx : 0));
5183	return pPage;
5184	}
5185
5186
5187	/**
5188	* Internal worker for finding a page for debugging purposes, no assertions.
5189	*
5190	* @returns Pointer to the shadow page structure. NULL on if not found.
5191	* @param pPool The pool.
5192	* @param HCPhys The HC physical address of the shadow page.
5193	*/
5194	PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys)
5195	{
5196	PGM_LOCK_ASSERT_OWNER(pPool->CTX_SUFF(pVM));
5197	return (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
5198	}
5199
5200	#ifdef IN_RING3 /* currently only used in ring 3; save some space in the R0 & GC modules (left it here as we might need it elsewhere later on) */
5201
5202	/**
5203	* Flush the specified page if present
5204	*
5205	* @param pVM Pointer to the VM.
5206	* @param GCPhys Guest physical address of the page to flush
5207	*/
5208	void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys)
5209	{
5210	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
5211
5212	VM_ASSERT_EMT(pVM);
5213
5214	/*
5215	* Look up the GCPhys in the hash.
5216	*/
5217	GCPhys = GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
5218	unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
5219	if (i == NIL_PGMPOOL_IDX)
5220	return;
5221
5222	do
5223	{
5224	PPGMPOOLPAGE pPage = &pPool->aPages[i];
5225	if (pPage->GCPhys - GCPhys < PAGE_SIZE)
5226	{
5227	switch (pPage->enmKind)
5228	{
5229	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
5230	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
5231	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
5232	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
5233	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
5234	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
5235	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
5236	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
5237	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
5238	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
5239	case PGMPOOLKIND_64BIT_PML4:
5240	case PGMPOOLKIND_32BIT_PD:
5241	case PGMPOOLKIND_PAE_PDPT:
5242	{
5243	Log(("PGMPoolFlushPage: found pgm pool pages for %RGp\n", GCPhys));
5244	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
5245	if (pPage->fDirty)
5246	STAM_COUNTER_INC(&pPool->StatForceFlushDirtyPage);
5247	else
5248	#endif
5249	STAM_COUNTER_INC(&pPool->StatForceFlushPage);
5250	Assert(!pgmPoolIsPageLocked(pPage));
5251	pgmPoolMonitorChainFlush(pPool, pPage);
5252	return;
5253	}
5254
5255	/* ignore, no monitoring. */
5256	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
5257	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
5258	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
5259	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
5260	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
5261	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
5262	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
5263	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
5264	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
5265	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
5266	case PGMPOOLKIND_ROOT_NESTED:
5267	case PGMPOOLKIND_PAE_PD_PHYS:
5268	case PGMPOOLKIND_PAE_PDPT_PHYS:
5269	case PGMPOOLKIND_32BIT_PD_PHYS:
5270	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
5271	break;
5272
5273	default:
5274	AssertFatalMsgFailed(("enmKind=%d idx=%d\n", pPage->enmKind, pPage->idx));
5275	}
5276	}
5277
5278	/* next */
5279	i = pPage->iNext;
5280	} while (i != NIL_PGMPOOL_IDX);
5281	return;
5282	}
5283
5284	#endif /* IN_RING3 */
5285	#ifdef IN_RING3
5286
5287	/**
5288	* Reset CPU on hot plugging.
5289	*
5290	* @param pVM Pointer to the VM.
5291	* @param pVCpu The virtual CPU.
5292	*/
5293	void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu)
5294	{
5295	pgmR3ExitShadowModeBeforePoolFlush(pVCpu);
5296
5297	pgmR3ReEnterShadowModeAfterPoolFlush(pVM, pVCpu);
5298	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
5299	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
5300	}
5301
5302
5303	/**
5304	* Flushes the entire cache.
5305	*
5306	* It will assert a global CR3 flush (FF) and assumes the caller is aware of
5307	* this and execute this CR3 flush.
5308	*
5309	* @param pPool The pool.
5310	*/
5311	void pgmR3PoolReset(PVM pVM)
5312	{
5313	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
5314
5315	PGM_LOCK_ASSERT_OWNER(pVM);
5316	STAM_PROFILE_START(&pPool->StatR3Reset, a);
5317	LogFlow(("pgmR3PoolReset:\n"));
5318
5319	/*
5320	* If there are no pages in the pool, there is nothing to do.
5321	*/
5322	if (pPool->cCurPages <= PGMPOOL_IDX_FIRST)
5323	{
5324	STAM_PROFILE_STOP(&pPool->StatR3Reset, a);
5325	return;
5326	}
5327
5328	/*
5329	* Exit the shadow mode since we're going to clear everything,
5330	* including the root page.
5331	*/
5332	for (VMCPUID i = 0; i < pVM->cCpus; i++)
5333	pgmR3ExitShadowModeBeforePoolFlush(&pVM->aCpus[i]);
5334
5335	/*
5336	* Nuke the free list and reinsert all pages into it.
5337	*/
5338	for (unsigned i = pPool->cCurPages - 1; i >= PGMPOOL_IDX_FIRST; i--)
5339	{
5340	PPGMPOOLPAGE pPage = &pPool->aPages[i];
5341
5342	Assert(pPage->Core.Key == MMPage2Phys(pVM, pPage->pvPageR3));
5343	if (pPage->fMonitored)
5344	pgmPoolMonitorFlush(pPool, pPage);
5345	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
5346	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
5347	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
5348	pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
5349	pPage->cModifications = 0;
5350	pPage->GCPhys = NIL_RTGCPHYS;
5351	pPage->enmKind = PGMPOOLKIND_FREE;
5352	pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
5353	Assert(pPage->idx == i);
5354	pPage->iNext = i + 1;
5355	pPage->fA20Enabled = true;
5356	pPage->fZeroed = false; /* This could probably be optimized, but better safe than sorry. */
5357	pPage->fSeenNonGlobal = false;
5358	pPage->fMonitored = false;
5359	pPage->fDirty = false;
5360	pPage->fCached = false;
5361	pPage->fReusedFlushPending = false;
5362	pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
5363	pPage->iAgeNext = NIL_PGMPOOL_IDX;
5364	pPage->iAgePrev = NIL_PGMPOOL_IDX;
5365	pPage->GCPtrLastAccessHandlerRip = NIL_RTGCPTR;
5366	pPage->GCPtrLastAccessHandlerFault = NIL_RTGCPTR;
5367	pPage->cLastAccessHandler = 0;
5368	pPage->cLocked = 0;
5369	#ifdef VBOX_STRICT
5370	pPage->GCPtrDirtyFault = NIL_RTGCPTR;
5371	#endif
5372	}
5373	pPool->aPages[pPool->cCurPages - 1].iNext = NIL_PGMPOOL_IDX;
5374	pPool->iFreeHead = PGMPOOL_IDX_FIRST;
5375	pPool->cUsedPages = 0;
5376
5377	/*
5378	* Zap and reinitialize the user records.
5379	*/
5380	pPool->cPresent = 0;
5381	pPool->iUserFreeHead = 0;
5382	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
5383	const unsigned cMaxUsers = pPool->cMaxUsers;
5384	for (unsigned i = 0; i < cMaxUsers; i++)
5385	{
5386	paUsers[i].iNext = i + 1;
5387	paUsers[i].iUser = NIL_PGMPOOL_IDX;
5388	paUsers[i].iUserTable = 0xfffffffe;
5389	}
5390	paUsers[cMaxUsers - 1].iNext = NIL_PGMPOOL_USER_INDEX;
5391
5392	/*
5393	* Clear all the GCPhys links and rebuild the phys ext free list.
5394	*/
5395	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRangesX);
5396	pRam;
5397	pRam = pRam->CTX_SUFF(pNext))
5398	{
5399	unsigned iPage = pRam->cb >> PAGE_SHIFT;
5400	while (iPage-- > 0)
5401	PGM_PAGE_SET_TRACKING(pVM, &pRam->aPages[iPage], 0);
5402	}
5403
5404	pPool->iPhysExtFreeHead = 0;
5405	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
5406	const unsigned cMaxPhysExts = pPool->cMaxPhysExts;
5407	for (unsigned i = 0; i < cMaxPhysExts; i++)
5408	{
5409	paPhysExts[i].iNext = i + 1;
5410	paPhysExts[i].aidx[0] = NIL_PGMPOOL_IDX;
5411	paPhysExts[i].apte[0] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
5412	paPhysExts[i].aidx[1] = NIL_PGMPOOL_IDX;
5413	paPhysExts[i].apte[1] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
5414	paPhysExts[i].aidx[2] = NIL_PGMPOOL_IDX;
5415	paPhysExts[i].apte[2] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
5416	}
5417	paPhysExts[cMaxPhysExts - 1].iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
5418
5419	/*
5420	* Just zap the modified list.
5421	*/
5422	pPool->cModifiedPages = 0;
5423	pPool->iModifiedHead = NIL_PGMPOOL_IDX;
5424
5425	/*
5426	* Clear the GCPhys hash and the age list.
5427	*/
5428	for (unsigned i = 0; i < RT_ELEMENTS(pPool->aiHash); i++)
5429	pPool->aiHash[i] = NIL_PGMPOOL_IDX;
5430	pPool->iAgeHead = NIL_PGMPOOL_IDX;
5431	pPool->iAgeTail = NIL_PGMPOOL_IDX;
5432
5433	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
5434	/* Clear all dirty pages. */
5435	pPool->idxFreeDirtyPage = 0;
5436	pPool->cDirtyPages = 0;
5437	for (unsigned i = 0; i < RT_ELEMENTS(pPool->aDirtyPages); i++)
5438	pPool->aDirtyPages[i].uIdx = NIL_PGMPOOL_IDX;
5439	#endif
5440
5441	/*
5442	* Reinsert active pages into the hash and ensure monitoring chains are correct.
5443	*/
5444	for (VMCPUID i = 0; i < pVM->cCpus; i++)
5445	{
5446	/*
5447	* Re-enter the shadowing mode and assert Sync CR3 FF.
5448	*/
5449	PVMCPU pVCpu = &pVM->aCpus[i];
5450	pgmR3ReEnterShadowModeAfterPoolFlush(pVM, pVCpu);
5451	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
5452	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
5453	}
5454
5455	STAM_PROFILE_STOP(&pPool->StatR3Reset, a);
5456	}
5457
5458	#endif /* IN_RING3 */
5459
5460	#if defined(LOG_ENABLED) \|\| defined(VBOX_STRICT)
5461	/**
5462	* Stringifies a PGMPOOLKIND value.
5463	*/
5464	static const char *pgmPoolPoolKindToStr(uint8_t enmKind)
5465	{
5466	switch ((PGMPOOLKIND)enmKind)
5467	{
5468	case PGMPOOLKIND_INVALID:
5469	return "PGMPOOLKIND_INVALID";
5470	case PGMPOOLKIND_FREE:
5471	return "PGMPOOLKIND_FREE";
5472	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
5473	return "PGMPOOLKIND_32BIT_PT_FOR_PHYS";
5474	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
5475	return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT";
5476	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
5477	return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB";
5478	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
5479	return "PGMPOOLKIND_PAE_PT_FOR_PHYS";
5480	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
5481	return "PGMPOOLKIND_PAE_PT_FOR_32BIT_PT";
5482	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
5483	return "PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB";
5484	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
5485	return "PGMPOOLKIND_PAE_PT_FOR_PAE_PT";
5486	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
5487	return "PGMPOOLKIND_PAE_PT_FOR_PAE_2MB";
5488	case PGMPOOLKIND_32BIT_PD:
5489	return "PGMPOOLKIND_32BIT_PD";
5490	case PGMPOOLKIND_32BIT_PD_PHYS:
5491	return "PGMPOOLKIND_32BIT_PD_PHYS";
5492	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
5493	return "PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD";
5494	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
5495	return "PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD";
5496	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
5497	return "PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD";
5498	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
5499	return "PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD";
5500	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
5501	return "PGMPOOLKIND_PAE_PD_FOR_PAE_PD";
5502	case PGMPOOLKIND_PAE_PD_PHYS:
5503	return "PGMPOOLKIND_PAE_PD_PHYS";
5504	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
5505	return "PGMPOOLKIND_PAE_PDPT_FOR_32BIT";
5506	case PGMPOOLKIND_PAE_PDPT:
5507	return "PGMPOOLKIND_PAE_PDPT";
5508	case PGMPOOLKIND_PAE_PDPT_PHYS:
5509	return "PGMPOOLKIND_PAE_PDPT_PHYS";
5510	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
5511	return "PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT";
5512	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
5513	return "PGMPOOLKIND_64BIT_PDPT_FOR_PHYS";
5514	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
5515	return "PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD";
5516	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
5517	return "PGMPOOLKIND_64BIT_PD_FOR_PHYS";
5518	case PGMPOOLKIND_64BIT_PML4:
5519	return "PGMPOOLKIND_64BIT_PML4";
5520	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
5521	return "PGMPOOLKIND_EPT_PDPT_FOR_PHYS";
5522	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
5523	return "PGMPOOLKIND_EPT_PD_FOR_PHYS";
5524	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
5525	return "PGMPOOLKIND_EPT_PT_FOR_PHYS";
5526	case PGMPOOLKIND_ROOT_NESTED:
5527	return "PGMPOOLKIND_ROOT_NESTED";
5528	}
5529	return "Unknown kind!";
5530	}
5531	#endif /* LOG_ENABLED \|\| VBOX_STRICT */
5532

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp@ 55331

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