PGMAllPool.cpp@ 20008

最後變更在這個檔案從20008是 19903,由 vboxsync 提交於 16 年前
Invalidation cleanup
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1	/* $Id: PGMAllPool.cpp 19903 2009-05-22 09:41:32Z vboxsync $ */
2	/** @file
3	* PGM Shadow Page Pool.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.alldomusa.eu.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_PGM_POOL
27	#include <VBox/pgm.h>
28	#include <VBox/mm.h>
29	#include <VBox/em.h>
30	#include <VBox/cpum.h>
31	#ifdef IN_RC
32	# include <VBox/patm.h>
33	#endif
34	#include "PGMInternal.h"
35	#include <VBox/vm.h>
36	#include <VBox/disopcode.h>
37	#include <VBox/hwacc_vmx.h>
38
39	#include <VBox/log.h>
40	#include <VBox/err.h>
41	#include <iprt/asm.h>
42	#include <iprt/string.h>
43
44
45	/*******************************************************************************
46	* Internal Functions *
47	*******************************************************************************/
48	__BEGIN_DECLS
49	static void pgmPoolFlushAllInt(PPGMPOOL pPool);
50	#ifdef PGMPOOL_WITH_USER_TRACKING
51	DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind);
52	DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind);
53	static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
54	#endif
55	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
56	static void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint);
57	#endif
58	#ifdef PGMPOOL_WITH_CACHE
59	static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
60	#endif
61	#ifdef PGMPOOL_WITH_MONITORING
62	static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
63	#endif
64	#ifndef IN_RING3
65	DECLEXPORT(int) pgmPoolAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
66	#endif
67	#ifdef LOG_ENABLED
68	static const char *pgmPoolPoolKindToStr(uint8_t enmKind);
69	#endif
70
71	void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
72	void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
73	int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
74	PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
75	void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
76	void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
77
78	__END_DECLS
79
80
81	/**
82	* Checks if the specified page pool kind is for a 4MB or 2MB guest page.
83	*
84	* @returns true if it's the shadow of a 4MB or 2MB guest page, otherwise false.
85	* @param enmKind The page kind.
86	*/
87	DECLINLINE(bool) pgmPoolIsBigPage(PGMPOOLKIND enmKind)
88	{
89	switch (enmKind)
90	{
91	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
92	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
93	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
94	return true;
95	default:
96	return false;
97	}
98	}
99
100	/** @def PGMPOOL_PAGE_2_LOCKED_PTR
101	* Maps a pool page pool into the current context and lock it (RC only).
102	*
103	* @returns VBox status code.
104	* @param pVM The VM handle.
105	* @param pPage The pool page.
106	*
107	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
108	* small page window employeed by that function. Be careful.
109	* @remark There is no need to assert on the result.
110	*/
111	#if defined(IN_RC)
112	DECLINLINE(void *) PGMPOOL_PAGE_2_LOCKED_PTR(PVM pVM, PPGMPOOLPAGE pPage)
113	{
114	void *pv = pgmPoolMapPageInlined(&pVM->pgm.s, pPage);
115
116	/* Make sure the dynamic mapping will not be reused. */
117	if (pv)
118	PGMDynLockHCPage(pVM, (uint8_t *)pv);
119
120	return pv;
121	}
122	#else
123	# define PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage) PGMPOOL_PAGE_2_PTR(pVM, pPage)
124	#endif
125
126	/** @def PGMPOOL_UNLOCK_PTR
127	* Unlock a previously locked dynamic caching (RC only).
128	*
129	* @returns VBox status code.
130	* @param pVM The VM handle.
131	* @param pPage The pool page.
132	*
133	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
134	* small page window employeed by that function. Be careful.
135	* @remark There is no need to assert on the result.
136	*/
137	#if defined(IN_RC)
138	DECLINLINE(void) PGMPOOL_UNLOCK_PTR(PVM pVM, void *pvPage)
139	{
140	if (pvPage)
141	PGMDynUnlockHCPage(pVM, (uint8_t *)pvPage);
142	}
143	#else
144	# define PGMPOOL_UNLOCK_PTR(pVM, pPage) do {} while (0)
145	#endif
146
147
148	#ifdef PGMPOOL_WITH_MONITORING
149	/**
150	* Determin the size of a write instruction.
151	* @returns number of bytes written.
152	* @param pDis The disassembler state.
153	*/
154	static unsigned pgmPoolDisasWriteSize(PDISCPUSTATE pDis)
155	{
156	/*
157	* This is very crude and possibly wrong for some opcodes,
158	* but since it's not really supposed to be called we can
159	* probably live with that.
160	*/
161	return DISGetParamSize(pDis, &pDis->param1);
162	}
163
164
165	/**
166	* Flushes a chain of pages sharing the same access monitor.
167	*
168	* @returns VBox status code suitable for scheduling.
169	* @param pPool The pool.
170	* @param pPage A page in the chain.
171	*/
172	int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
173	{
174	LogFlow(("pgmPoolMonitorChainFlush: Flush page %RGp type=%d\n", pPage->GCPhys, pPage->enmKind));
175
176	/*
177	* Find the list head.
178	*/
179	uint16_t idx = pPage->idx;
180	if (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
181	{
182	while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
183	{
184	idx = pPage->iMonitoredPrev;
185	Assert(idx != pPage->idx);
186	pPage = &pPool->aPages[idx];
187	}
188	}
189
190	/*
191	* Iterate the list flushing each shadow page.
192	*/
193	int rc = VINF_SUCCESS;
194	for (;;)
195	{
196	idx = pPage->iMonitoredNext;
197	Assert(idx != pPage->idx);
198	if (pPage->idx >= PGMPOOL_IDX_FIRST)
199	{
200	int rc2 = pgmPoolFlushPage(pPool, pPage);
201	AssertRC(rc2);
202	}
203	/* next */
204	if (idx == NIL_PGMPOOL_IDX)
205	break;
206	pPage = &pPool->aPages[idx];
207	}
208	return rc;
209	}
210
211
212	/**
213	* Wrapper for getting the current context pointer to the entry being modified.
214	*
215	* @returns VBox status code suitable for scheduling.
216	* @param pVM VM Handle.
217	* @param pvDst Destination address
218	* @param pvSrc Source guest virtual address.
219	* @param GCPhysSrc The source guest physical address.
220	* @param cb Size of data to read
221	*/
222	DECLINLINE(int) pgmPoolPhysSimpleReadGCPhys(PVM pVM, void *pvDst, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvSrc, RTGCPHYS GCPhysSrc, size_t cb)
223	{
224	#if defined(IN_RING3)
225	memcpy(pvDst, (RTHCPTR)((uintptr_t)pvSrc & ~(RTHCUINTPTR)(cb - 1)), cb);
226	return VINF_SUCCESS;
227	#else
228	/* @todo in RC we could attempt to use the virtual address, although this can cause many faults (PAE Windows XP guest). */
229	return PGMPhysSimpleReadGCPhys(pVM, pvDst, GCPhysSrc & ~(RTGCPHYS)(cb - 1), cb);
230	#endif
231	}
232
233	/**
234	* Process shadow entries before they are changed by the guest.
235	*
236	* For PT entries we will clear them. For PD entries, we'll simply check
237	* for mapping conflicts and set the SyncCR3 FF if found.
238	*
239	* @param pVCpu VMCPU handle
240	* @param pPool The pool.
241	* @param pPage The head page.
242	* @param GCPhysFault The guest physical fault address.
243	* @param uAddress In R0 and GC this is the guest context fault address (flat).
244	* In R3 this is the host context 'fault' address.
245	* @param pCpu The disassembler state for figuring out the write size.
246	* This need not be specified if the caller knows we won't do cross entry accesses.
247	*/
248	void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, PDISCPUSTATE pCpu)
249	{
250	Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
251	const unsigned off = GCPhysFault & PAGE_OFFSET_MASK;
252	const unsigned cbWrite = (pCpu) ? pgmPoolDisasWriteSize(pCpu) : 0;
253	PVM pVM = pPool->CTX_SUFF(pVM);
254
255	LogFlow(("pgmPoolMonitorChainChanging: %RGv phys=%RGp kind=%s cbWrite=%d\n", (RTGCPTR)pvAddress, GCPhysFault, pgmPoolPoolKindToStr(pPage->enmKind), cbWrite));
256	for (;;)
257	{
258	union
259	{
260	void *pv;
261	PX86PT pPT;
262	PX86PTPAE pPTPae;
263	PX86PD pPD;
264	PX86PDPAE pPDPae;
265	PX86PDPT pPDPT;
266	PX86PML4 pPML4;
267	} uShw;
268
269	uShw.pv = NULL;
270	switch (pPage->enmKind)
271	{
272	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
273	{
274	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
275	const unsigned iShw = off / sizeof(X86PTE);
276	LogFlow(("PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT iShw=%x\n", iShw));
277	if (uShw.pPT->a[iShw].n.u1Present)
278	{
279	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
280	X86PTE GstPte;
281
282	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
283	AssertRC(rc);
284	Log4(("pgmPoolMonitorChainChanging 32_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
285	pgmPoolTracDerefGCPhysHint(pPool, pPage,
286	uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK,
287	GstPte.u & X86_PTE_PG_MASK);
288	# endif
289	ASMAtomicWriteSize(&uShw.pPT->a[iShw], 0);
290	}
291	break;
292	}
293
294	/* page/2 sized */
295	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
296	{
297	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
298	if (!((off ^ pPage->GCPhys) & (PAGE_SIZE / 2)))
299	{
300	const unsigned iShw = (off / sizeof(X86PTE)) & (X86_PG_PAE_ENTRIES - 1);
301	LogFlow(("PGMPOOLKIND_PAE_PT_FOR_32BIT_PT iShw=%x\n", iShw));
302	if (uShw.pPTPae->a[iShw].n.u1Present)
303	{
304	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
305	X86PTE GstPte;
306	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
307	AssertRC(rc);
308
309	Log4(("pgmPoolMonitorChainChanging pae_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
310	pgmPoolTracDerefGCPhysHint(pPool, pPage,
311	uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK,
312	GstPte.u & X86_PTE_PG_MASK);
313	# endif
314	ASMAtomicWriteSize(&uShw.pPTPae->a[iShw], 0);
315	}
316	}
317	break;
318	}
319
320	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
321	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
322	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
323	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
324	{
325	unsigned iGst = off / sizeof(X86PDE);
326	unsigned iShwPdpt = iGst / 256;
327	unsigned iShw = (iGst % 256) * 2;
328	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
329
330	LogFlow(("pgmPoolMonitorChainChanging PAE for 32 bits: iGst=%x iShw=%x idx = %d page idx=%d\n", iGst, iShw, iShwPdpt, pPage->enmKind - PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD));
331	if (iShwPdpt == pPage->enmKind - (unsigned)PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD)
332	{
333	for (unsigned i = 0; i < 2; i++)
334	{
335	# ifndef IN_RING0
336	if ((uShw.pPDPae->a[iShw + i].u & (PGM_PDFLAGS_MAPPING \| X86_PDE_P)) == (PGM_PDFLAGS_MAPPING \| X86_PDE_P))
337	{
338	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
339	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
340	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw=%#x!\n", iShwPdpt, iShw+i));
341	break;
342	}
343	else
344	# endif /* !IN_RING0 */
345	if (uShw.pPDPae->a[iShw+i].n.u1Present)
346	{
347	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw+i, uShw.pPDPae->a[iShw+i].u));
348	pgmPoolFree(pVM,
349	uShw.pPDPae->a[iShw+i].u & X86_PDE_PAE_PG_MASK,
350	pPage->idx,
351	iShw + i);
352	ASMAtomicWriteSize(&uShw.pPDPae->a[iShw+i], 0);
353	}
354
355	/* paranoia / a bit assumptive. */
356	if ( pCpu
357	&& (off & 3)
358	&& (off & 3) + cbWrite > 4)
359	{
360	const unsigned iShw2 = iShw + 2 + i;
361	if (iShw2 < RT_ELEMENTS(uShw.pPDPae->a))
362	{
363	# ifndef IN_RING0
364	if ((uShw.pPDPae->a[iShw2].u & (PGM_PDFLAGS_MAPPING \| X86_PDE_P)) == (PGM_PDFLAGS_MAPPING \| X86_PDE_P))
365	{
366	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
367	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
368	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw2=%#x!\n", iShwPdpt, iShw2));
369	break;
370	}
371	else
372	# endif /* !IN_RING0 */
373	if (uShw.pPDPae->a[iShw2].n.u1Present)
374	{
375	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
376	pgmPoolFree(pVM,
377	uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
378	pPage->idx,
379	iShw2);
380	ASMAtomicWriteSize(&uShw.pPDPae->a[iShw2].u, 0);
381	}
382	}
383	}
384	}
385	}
386	break;
387	}
388
389	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
390	{
391	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
392	const unsigned iShw = off / sizeof(X86PTEPAE);
393	if (uShw.pPTPae->a[iShw].n.u1Present)
394	{
395	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
396	X86PTEPAE GstPte;
397	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
398	AssertRC(rc);
399
400	Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PAE_PG_MASK));
401	pgmPoolTracDerefGCPhysHint(pPool, pPage,
402	uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK,
403	GstPte.u & X86_PTE_PAE_PG_MASK);
404	# endif
405	ASMAtomicWriteSize(&uShw.pPTPae->a[iShw].u, 0);
406	}
407
408	/* paranoia / a bit assumptive. */
409	if ( pCpu
410	&& (off & 7)
411	&& (off & 7) + cbWrite > sizeof(X86PTEPAE))
412	{
413	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTEPAE);
414	AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPTPae->a));
415
416	if (uShw.pPTPae->a[iShw2].n.u1Present)
417	{
418	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
419	X86PTEPAE GstPte;
420	# ifdef IN_RING3
421	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, (RTHCPTR)((RTHCUINTPTR)pvAddress + sizeof(GstPte)), GCPhysFault + sizeof(GstPte), sizeof(GstPte));
422	# else
423	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress + sizeof(GstPte), GCPhysFault + sizeof(GstPte), sizeof(GstPte));
424	# endif
425	AssertRC(rc);
426	Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", uShw.pPTPae->a[iShw2].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PAE_PG_MASK));
427	pgmPoolTracDerefGCPhysHint(pPool, pPage,
428	uShw.pPTPae->a[iShw2].u & X86_PTE_PAE_PG_MASK,
429	GstPte.u & X86_PTE_PAE_PG_MASK);
430	# endif
431	ASMAtomicWriteSize(&uShw.pPTPae->a[iShw2].u ,0);
432	}
433	}
434	break;
435	}
436
437	case PGMPOOLKIND_32BIT_PD:
438	{
439	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
440	const unsigned iShw = off / sizeof(X86PTE); // ASSUMING 32-bit guest paging!
441
442	LogFlow(("pgmPoolMonitorChainChanging: PGMPOOLKIND_32BIT_PD %x\n", iShw));
443	# ifndef IN_RING0
444	if (uShw.pPD->a[iShw].u & PGM_PDFLAGS_MAPPING)
445	{
446	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
447	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
448	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
449	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
450	break;
451	}
452	# endif /* !IN_RING0 */
453	# ifndef IN_RING0
454	else
455	# endif /* !IN_RING0 */
456	{
457	if (uShw.pPD->a[iShw].n.u1Present)
458	{
459	LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
460	pgmPoolFree(pVM,
461	uShw.pPD->a[iShw].u & X86_PDE_PAE_PG_MASK,
462	pPage->idx,
463	iShw);
464	ASMAtomicWriteSize(&uShw.pPD->a[iShw].u, 0);
465	}
466	}
467	/* paranoia / a bit assumptive. */
468	if ( pCpu
469	&& (off & 3)
470	&& (off & 3) + cbWrite > sizeof(X86PTE))
471	{
472	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTE);
473	if ( iShw2 != iShw
474	&& iShw2 < RT_ELEMENTS(uShw.pPD->a))
475	{
476	# ifndef IN_RING0
477	if (uShw.pPD->a[iShw2].u & PGM_PDFLAGS_MAPPING)
478	{
479	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
480	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
481	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
482	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
483	break;
484	}
485	# endif /* !IN_RING0 */
486	# ifndef IN_RING0
487	else
488	# endif /* !IN_RING0 */
489	{
490	if (uShw.pPD->a[iShw2].n.u1Present)
491	{
492	LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPD->a[iShw2].u));
493	pgmPoolFree(pVM,
494	uShw.pPD->a[iShw2].u & X86_PDE_PAE_PG_MASK,
495	pPage->idx,
496	iShw2);
497	ASMAtomicWriteSize(&uShw.pPD->a[iShw2].u, 0);
498	}
499	}
500	}
501	}
502	#if 0 /* useful when running PGMAssertCR3(), a bit too troublesome for general use (TLBs). */
503	if ( uShw.pPD->a[iShw].n.u1Present
504	&& !VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
505	{
506	LogFlow(("pgmPoolMonitorChainChanging: iShw=%#x: %RX32 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
507	# ifdef IN_RC /* TLB load - we're pushing things a bit... */
508	ASMProbeReadByte(pvAddress);
509	# endif
510	pgmPoolFree(pVM, uShw.pPD->a[iShw].u & X86_PDE_PG_MASK, pPage->idx, iShw);
511	ASMAtomicWriteSize(&uShw.pPD->a[iShw].u, 0);
512	}
513	#endif
514	break;
515	}
516
517	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
518	{
519	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
520	const unsigned iShw = off / sizeof(X86PDEPAE);
521	#ifndef IN_RING0
522	if (uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING)
523	{
524	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
525	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
526	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
527	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
528	break;
529	}
530	#endif /* !IN_RING0 */
531	/*
532	* Causes trouble when the guest uses a PDE to refer to the whole page table level
533	* structure. (Invalidate here; faults later on when it tries to change the page
534	* table entries -> recheck; probably only applies to the RC case.)
535	*/
536	# ifndef IN_RING0
537	else
538	# endif /* !IN_RING0 */
539	{
540	if (uShw.pPDPae->a[iShw].n.u1Present)
541	{
542	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
543	pgmPoolFree(pVM,
544	uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK,
545	pPage->idx,
546	iShw);
547	ASMAtomicWriteSize(&uShw.pPDPae->a[iShw].u, 0);
548	}
549	}
550	/* paranoia / a bit assumptive. */
551	if ( pCpu
552	&& (off & 7)
553	&& (off & 7) + cbWrite > sizeof(X86PDEPAE))
554	{
555	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
556	AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
557
558	#ifndef IN_RING0
559	if ( iShw2 != iShw
560	&& uShw.pPDPae->a[iShw2].u & PGM_PDFLAGS_MAPPING)
561	{
562	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
563	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
564	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
565	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
566	break;
567	}
568	#endif /* !IN_RING0 */
569	# ifndef IN_RING0
570	else
571	# endif /* !IN_RING0 */
572	if (uShw.pPDPae->a[iShw2].n.u1Present)
573	{
574	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
575	pgmPoolFree(pVM,
576	uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
577	pPage->idx,
578	iShw2);
579	ASMAtomicWriteSize(&uShw.pPDPae->a[iShw2].u, 0);
580	}
581	}
582	break;
583	}
584
585	case PGMPOOLKIND_PAE_PDPT:
586	{
587	/*
588	* Hopefully this doesn't happen very often:
589	* - touching unused parts of the page
590	* - messing with the bits of pd pointers without changing the physical address
591	*/
592	/* PDPT roots are not page aligned; 32 byte only! */
593	const unsigned offPdpt = GCPhysFault - pPage->GCPhys;
594
595	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
596	const unsigned iShw = offPdpt / sizeof(X86PDPE);
597	if (iShw < X86_PG_PAE_PDPE_ENTRIES) /* don't use RT_ELEMENTS(uShw.pPDPT->a), because that's for long mode only */
598	{
599	# ifndef IN_RING0
600	if (uShw.pPDPT->a[iShw].u & PGM_PLXFLAGS_MAPPING)
601	{
602	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
603	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
604	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
605	LogFlow(("pgmPoolMonitorChainChanging: Detected pdpt conflict at iShw=%#x!\n", iShw));
606	break;
607	}
608	# endif /* !IN_RING0 */
609	# ifndef IN_RING0
610	else
611	# endif /* !IN_RING0 */
612	if (uShw.pPDPT->a[iShw].n.u1Present)
613	{
614	LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
615	pgmPoolFree(pVM,
616	uShw.pPDPT->a[iShw].u & X86_PDPE_PG_MASK,
617	pPage->idx,
618	iShw);
619	ASMAtomicWriteSize(&uShw.pPDPT->a[iShw].u, 0);
620	}
621
622	/* paranoia / a bit assumptive. */
623	if ( pCpu
624	&& (offPdpt & 7)
625	&& (offPdpt & 7) + cbWrite > sizeof(X86PDPE))
626	{
627	const unsigned iShw2 = (offPdpt + cbWrite - 1) / sizeof(X86PDPE);
628	if ( iShw2 != iShw
629	&& iShw2 < X86_PG_PAE_PDPE_ENTRIES)
630	{
631	# ifndef IN_RING0
632	if (uShw.pPDPT->a[iShw2].u & PGM_PLXFLAGS_MAPPING)
633	{
634	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
635	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
636	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
637	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
638	break;
639	}
640	# endif /* !IN_RING0 */
641	# ifndef IN_RING0
642	else
643	# endif /* !IN_RING0 */
644	if (uShw.pPDPT->a[iShw2].n.u1Present)
645	{
646	LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
647	pgmPoolFree(pVM,
648	uShw.pPDPT->a[iShw2].u & X86_PDPE_PG_MASK,
649	pPage->idx,
650	iShw2);
651	ASMAtomicWriteSize(&uShw.pPDPT->a[iShw2].u, 0);
652	}
653	}
654	}
655	}
656	break;
657	}
658
659	#ifndef IN_RC
660	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
661	{
662	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
663	const unsigned iShw = off / sizeof(X86PDEPAE);
664	Assert(!(uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING));
665	if (uShw.pPDPae->a[iShw].n.u1Present)
666	{
667	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
668	pgmPoolFree(pVM,
669	uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK,
670	pPage->idx,
671	iShw);
672	ASMAtomicWriteSize(&uShw.pPDPae->a[iShw].u, 0);
673	}
674	/* paranoia / a bit assumptive. */
675	if ( pCpu
676	&& (off & 7)
677	&& (off & 7) + cbWrite > sizeof(X86PDEPAE))
678	{
679	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
680	AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
681
682	Assert(!(uShw.pPDPae->a[iShw2].u & PGM_PDFLAGS_MAPPING));
683	if (uShw.pPDPae->a[iShw2].n.u1Present)
684	{
685	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
686	pgmPoolFree(pVM,
687	uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
688	pPage->idx,
689	iShw2);
690	ASMAtomicWriteSize(&uShw.pPDPae->a[iShw2].u, 0);
691	}
692	}
693	break;
694	}
695
696	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
697	{
698	/*
699	* Hopefully this doesn't happen very often:
700	* - messing with the bits of pd pointers without changing the physical address
701	*/
702	if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
703	{
704	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
705	const unsigned iShw = off / sizeof(X86PDPE);
706	if (uShw.pPDPT->a[iShw].n.u1Present)
707	{
708	LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
709	pgmPoolFree(pVM, uShw.pPDPT->a[iShw].u & X86_PDPE_PG_MASK, pPage->idx, iShw);
710	ASMAtomicWriteSize(&uShw.pPDPT->a[iShw].u, 0);
711	}
712	/* paranoia / a bit assumptive. */
713	if ( pCpu
714	&& (off & 7)
715	&& (off & 7) + cbWrite > sizeof(X86PDPE))
716	{
717	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDPE);
718	if (uShw.pPDPT->a[iShw2].n.u1Present)
719	{
720	LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
721	pgmPoolFree(pVM, uShw.pPDPT->a[iShw2].u & X86_PDPE_PG_MASK, pPage->idx, iShw2);
722	ASMAtomicWriteSize(&uShw.pPDPT->a[iShw2].u, 0);
723	}
724	}
725	}
726	break;
727	}
728
729	case PGMPOOLKIND_64BIT_PML4:
730	{
731	/*
732	* Hopefully this doesn't happen very often:
733	* - messing with the bits of pd pointers without changing the physical address
734	*/
735	if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
736	{
737	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
738	const unsigned iShw = off / sizeof(X86PDPE);
739	if (uShw.pPML4->a[iShw].n.u1Present)
740	{
741	LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPML4->a[iShw].u));
742	pgmPoolFree(pVM, uShw.pPML4->a[iShw].u & X86_PML4E_PG_MASK, pPage->idx, iShw);
743	ASMAtomicWriteSize(&uShw.pPML4->a[iShw].u, 0);
744	}
745	/* paranoia / a bit assumptive. */
746	if ( pCpu
747	&& (off & 7)
748	&& (off & 7) + cbWrite > sizeof(X86PDPE))
749	{
750	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PML4E);
751	if (uShw.pPML4->a[iShw2].n.u1Present)
752	{
753	LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPML4->a[iShw2].u));
754	pgmPoolFree(pVM, uShw.pPML4->a[iShw2].u & X86_PML4E_PG_MASK, pPage->idx, iShw2);
755	ASMAtomicWriteSize(&uShw.pPML4->a[iShw2].u, 0);
756	}
757	}
758	}
759	break;
760	}
761	#endif /* IN_RING0 */
762
763	default:
764	AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
765	}
766	PGMPOOL_UNLOCK_PTR(pVM, uShw.pv);
767
768	/* next */
769	if (pPage->iMonitoredNext == NIL_PGMPOOL_IDX)
770	return;
771	pPage = &pPool->aPages[pPage->iMonitoredNext];
772	}
773	}
774
775	# ifndef IN_RING3
776	/**
777	* Checks if a access could be a fork operation in progress.
778	*
779	* Meaning, that the guest is setuping up the parent process for Copy-On-Write.
780	*
781	* @returns true if it's likly that we're forking, otherwise false.
782	* @param pPool The pool.
783	* @param pCpu The disassembled instruction.
784	* @param offFault The access offset.
785	*/
786	DECLINLINE(bool) pgmPoolMonitorIsForking(PPGMPOOL pPool, PDISCPUSTATE pCpu, unsigned offFault)
787	{
788	/*
789	* i386 linux is using btr to clear X86_PTE_RW.
790	* The functions involved are (2.6.16 source inspection):
791	* clear_bit
792	* ptep_set_wrprotect
793	* copy_one_pte
794	* copy_pte_range
795	* copy_pmd_range
796	* copy_pud_range
797	* copy_page_range
798	* dup_mmap
799	* dup_mm
800	* copy_mm
801	* copy_process
802	* do_fork
803	*/
804	if ( pCpu->pCurInstr->opcode == OP_BTR
805	&& !(offFault & 4)
806	/** @todo Validate that the bit index is X86_PTE_RW. */
807	)
808	{
809	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,Fork));
810	return true;
811	}
812	return false;
813	}
814
815
816	/**
817	* Determine whether the page is likely to have been reused.
818	*
819	* @returns true if we consider the page as being reused for a different purpose.
820	* @returns false if we consider it to still be a paging page.
821	* @param pVM VM Handle.
822	* @param pRegFrame Trap register frame.
823	* @param pCpu The disassembly info for the faulting instruction.
824	* @param pvFault The fault address.
825	*
826	* @remark The REP prefix check is left to the caller because of STOSD/W.
827	*/
828	DECLINLINE(bool) pgmPoolMonitorIsReused(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, RTGCPTR pvFault)
829	{
830	#ifndef IN_RC
831	/** @todo could make this general, faulting close to rsp should be safe reuse heuristic. */
832	if ( HWACCMHasPendingIrq(pVM)
833	&& (pRegFrame->rsp - pvFault) < 32)
834	{
835	/* Fault caused by stack writes while trying to inject an interrupt event. */
836	Log(("pgmPoolMonitorIsReused: reused %RGv for interrupt stack (rsp=%RGv).\n", pvFault, pRegFrame->rsp));
837	return true;
838	}
839	#else
840	NOREF(pVM); NOREF(pvFault);
841	#endif
842
843	switch (pCpu->pCurInstr->opcode)
844	{
845	/* call implies the actual push of the return address faulted */
846	case OP_CALL:
847	Log4(("pgmPoolMonitorIsReused: CALL\n"));
848	return true;
849	case OP_PUSH:
850	Log4(("pgmPoolMonitorIsReused: PUSH\n"));
851	return true;
852	case OP_PUSHF:
853	Log4(("pgmPoolMonitorIsReused: PUSHF\n"));
854	return true;
855	case OP_PUSHA:
856	Log4(("pgmPoolMonitorIsReused: PUSHA\n"));
857	return true;
858	case OP_FXSAVE:
859	Log4(("pgmPoolMonitorIsReused: FXSAVE\n"));
860	return true;
861	case OP_MOVNTI: /* solaris - block_zero_no_xmm */
862	Log4(("pgmPoolMonitorIsReused: MOVNTI\n"));
863	return true;
864	case OP_MOVNTDQ: /* solaris - hwblkclr & hwblkpagecopy */
865	Log4(("pgmPoolMonitorIsReused: MOVNTDQ\n"));
866	return true;
867	case OP_MOVSWD:
868	case OP_STOSWD:
869	if ( pCpu->prefix == (PREFIX_REP\|PREFIX_REX)
870	&& pRegFrame->rcx >= 0x40
871	)
872	{
873	Assert(pCpu->mode == CPUMODE_64BIT);
874
875	Log(("pgmPoolMonitorIsReused: OP_STOSQ\n"));
876	return true;
877	}
878	return false;
879	}
880	if ( (pCpu->param1.flags & USE_REG_GEN32)
881	&& (pCpu->param1.base.reg_gen == USE_REG_ESP))
882	{
883	Log4(("pgmPoolMonitorIsReused: ESP\n"));
884	return true;
885	}
886
887	return false;
888	}
889
890
891	/**
892	* Flushes the page being accessed.
893	*
894	* @returns VBox status code suitable for scheduling.
895	* @param pVM The VM handle.
896	* @param pVCpu The VMCPU handle.
897	* @param pPool The pool.
898	* @param pPage The pool page (head).
899	* @param pCpu The disassembly of the write instruction.
900	* @param pRegFrame The trap register frame.
901	* @param GCPhysFault The fault address as guest physical address.
902	* @param pvFault The fault address.
903	*/
904	static int pgmPoolAccessHandlerFlush(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pCpu,
905	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
906	{
907	/*
908	* First, do the flushing.
909	*/
910	int rc = pgmPoolMonitorChainFlush(pPool, pPage);
911
912	/*
913	* Emulate the instruction (xp/w2k problem, requires pc/cr2/sp detection).
914	*/
915	uint32_t cbWritten;
916	int rc2 = EMInterpretInstructionCPU(pVM, pVCpu, pCpu, pRegFrame, pvFault, &cbWritten);
917	if (RT_SUCCESS(rc2))
918	pRegFrame->rip += pCpu->opsize;
919	else if (rc2 == VERR_EM_INTERPRETER)
920	{
921	#ifdef IN_RC
922	if (PATMIsPatchGCAddr(pVM, (RTRCPTR)pRegFrame->eip))
923	{
924	LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for patch code %04x:%RGv, ignoring.\n",
925	pRegFrame->cs, (RTGCPTR)pRegFrame->eip));
926	rc = VINF_SUCCESS;
927	STAM_COUNTER_INC(&pPool->StatMonitorRZIntrFailPatch2);
928	}
929	else
930	#endif
931	{
932	rc = VINF_EM_RAW_EMULATE_INSTR;
933	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
934	}
935	}
936	else
937	rc = rc2;
938
939	/* See use in pgmPoolAccessHandlerSimple(). */
940	PGM_INVL_VCPU_TLBS(pVCpu);
941
942	LogFlow(("pgmPoolAccessHandlerPT: returns %Rrc (flushed)\n", rc));
943	return rc;
944
945	}
946
947
948	/**
949	* Handles the STOSD write accesses.
950	*
951	* @returns VBox status code suitable for scheduling.
952	* @param pVM The VM handle.
953	* @param pPool The pool.
954	* @param pPage The pool page (head).
955	* @param pCpu The disassembly of the write instruction.
956	* @param pRegFrame The trap register frame.
957	* @param GCPhysFault The fault address as guest physical address.
958	* @param pvFault The fault address.
959	*/
960	DECLINLINE(int) pgmPoolAccessHandlerSTOSD(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pCpu,
961	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
962	{
963	Assert(pCpu->mode == CPUMODE_32BIT);
964
965	Log3(("pgmPoolAccessHandlerSTOSD\n"));
966
967	/*
968	* Increment the modification counter and insert it into the list
969	* of modified pages the first time.
970	*/
971	if (!pPage->cModifications++)
972	pgmPoolMonitorModifiedInsert(pPool, pPage);
973
974	/*
975	* Execute REP STOSD.
976	*
977	* This ASSUMES that we're not invoked by Trap0e on in a out-of-sync
978	* write situation, meaning that it's safe to write here.
979	*/
980	PVMCPU pVCpu = VMMGetCpu(pPool->CTX_SUFF(pVM));
981	RTGCUINTPTR pu32 = (RTGCUINTPTR)pvFault;
982	while (pRegFrame->ecx)
983	{
984	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
985	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
986	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, (RTGCPTR)pu32, NULL);
987	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
988	#else
989	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, (RTGCPTR)pu32, NULL);
990	#endif
991	#ifdef IN_RC
992	(uint32_t )pu32 = pRegFrame->eax;
993	#else
994	PGMPhysSimpleWriteGCPhys(pVM, GCPhysFault, &pRegFrame->eax, 4);
995	#endif
996	pu32 += 4;
997	GCPhysFault += 4;
998	pRegFrame->edi += 4;
999	pRegFrame->ecx--;
1000	}
1001	pRegFrame->rip += pCpu->opsize;
1002
1003	#ifdef IN_RC
1004	/* See use in pgmPoolAccessHandlerSimple(). */
1005	PGM_INVL_VCPU_TLBS(pVCpu);
1006	#endif
1007
1008	LogFlow(("pgmPoolAccessHandlerSTOSD: returns\n"));
1009	return VINF_SUCCESS;
1010	}
1011
1012
1013	/**
1014	* Handles the simple write accesses.
1015	*
1016	* @returns VBox status code suitable for scheduling.
1017	* @param pVM The VM handle.
1018	* @param pVCpu The VMCPU handle.
1019	* @param pPool The pool.
1020	* @param pPage The pool page (head).
1021	* @param pCpu The disassembly of the write instruction.
1022	* @param pRegFrame The trap register frame.
1023	* @param GCPhysFault The fault address as guest physical address.
1024	* @param pvFault The fault address.
1025	*/
1026	DECLINLINE(int) pgmPoolAccessHandlerSimple(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pCpu,
1027	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
1028	{
1029	Log3(("pgmPoolAccessHandlerSimple\n"));
1030	/*
1031	* Increment the modification counter and insert it into the list
1032	* of modified pages the first time.
1033	*/
1034	if (!pPage->cModifications++)
1035	pgmPoolMonitorModifiedInsert(pPool, pPage);
1036
1037	/*
1038	* Clear all the pages. ASSUMES that pvFault is readable.
1039	*/
1040	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1041	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
1042	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, pCpu);
1043	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
1044	#else
1045	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, pCpu);
1046	#endif
1047
1048	/*
1049	* Interpret the instruction.
1050	*/
1051	uint32_t cb;
1052	int rc = EMInterpretInstructionCPU(pVM, pVCpu, pCpu, pRegFrame, pvFault, &cb);
1053	if (RT_SUCCESS(rc))
1054	pRegFrame->rip += pCpu->opsize;
1055	else if (rc == VERR_EM_INTERPRETER)
1056	{
1057	LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for %04x:%RGv - opcode=%d\n",
1058	pRegFrame->cs, (RTGCPTR)pRegFrame->rip, pCpu->pCurInstr->opcode));
1059	rc = VINF_EM_RAW_EMULATE_INSTR;
1060	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
1061	}
1062
1063	#ifdef IN_RC
1064	/*
1065	* Quick hack, with logging enabled we're getting stale
1066	* code TLBs but no data TLB for EIP and crash in EMInterpretDisasOne.
1067	* Flushing here is BAD and expensive, I think EMInterpretDisasOne will
1068	* have to be fixed to support this. But that'll have to wait till next week.
1069	*
1070	* An alternative is to keep track of the changed PTEs together with the
1071	* GCPhys from the guest PT. This may proove expensive though.
1072	*
1073	* At the moment, it's VITAL that it's done AFTER the instruction interpreting
1074	* because we need the stale TLBs in some cases (XP boot). This MUST be fixed properly!
1075	*/
1076	PGM_INVL_VCPU_TLBS(pVCpu);
1077	#endif
1078
1079	LogFlow(("pgmPoolAccessHandlerSimple: returns %Rrc cb=%d\n", rc, cb));
1080	return rc;
1081	}
1082
1083	/**
1084	* \#PF Handler callback for PT write accesses.
1085	*
1086	* @returns VBox status code (appropriate for GC return).
1087	* @param pVM VM Handle.
1088	* @param uErrorCode CPU Error code.
1089	* @param pRegFrame Trap register frame.
1090	* NULL on DMA and other non CPU access.
1091	* @param pvFault The fault address (cr2).
1092	* @param GCPhysFault The GC physical address corresponding to pvFault.
1093	* @param pvUser User argument.
1094	*/
1095	DECLEXPORT(int) pgmPoolAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1096	{
1097	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), a);
1098	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1099	PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)pvUser;
1100	PVMCPU pVCpu = VMMGetCpu(pVM);
1101
1102	LogFlow(("pgmPoolAccessHandler: pvFault=%RGv pPage=%p:{.idx=%d} GCPhysFault=%RGp\n", pvFault, pPage, pPage->idx, GCPhysFault));
1103
1104	/*
1105	* We should ALWAYS have the list head as user parameter. This
1106	* is because we use that page to record the changes.
1107	*/
1108	Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1109
1110	/*
1111	* Disassemble the faulting instruction.
1112	*/
1113	DISCPUSTATE Cpu;
1114	int rc = EMInterpretDisasOne(pVM, pVCpu, pRegFrame, &Cpu, NULL);
1115	AssertRCReturn(rc, rc);
1116
1117	pgmLock(pVM);
1118	AssertMsg(PHYS_PAGE_ADDRESS(GCPhysFault) == PHYS_PAGE_ADDRESS(pPage->GCPhys), ("%RGp vs %RGp\n", PHYS_PAGE_ADDRESS(GCPhysFault), pPage->GCPhys));
1119
1120	/*
1121	* Check if it's worth dealing with.
1122	*/
1123	bool fReused = false;
1124	if ( ( pPage->cModifications < 48 /** @todo #define / /* @todo need to check that it's not mapping EIP. / /* @todo adjust this! */
1125	\|\| pgmPoolIsPageLocked(&pVM->pgm.s, pPage)
1126	)
1127	&& !(fReused = pgmPoolMonitorIsReused(pVM, pRegFrame, &Cpu, pvFault))
1128	&& !pgmPoolMonitorIsForking(pPool, &Cpu, GCPhysFault & PAGE_OFFSET_MASK))
1129	{
1130	/*
1131	* Simple instructions, no REP prefix.
1132	*/
1133	if (!(Cpu.prefix & (PREFIX_REP \| PREFIX_REPNE)))
1134	{
1135	rc = pgmPoolAccessHandlerSimple(pVM, pVCpu, pPool, pPage, &Cpu, pRegFrame, GCPhysFault, pvFault);
1136	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,Handled), a);
1137	pgmUnlock(pVM);
1138	return rc;
1139	}
1140
1141	/*
1142	* Windows is frequently doing small memset() operations (netio test 4k+).
1143	* We have to deal with these or we'll kill the cache and performance.
1144	*/
1145	if ( Cpu.pCurInstr->opcode == OP_STOSWD
1146	&& CPUMGetGuestCPL(pVCpu, pRegFrame) == 0
1147	&& pRegFrame->ecx <= 0x20
1148	&& pRegFrame->ecx * 4 <= PAGE_SIZE - ((uintptr_t)pvFault & PAGE_OFFSET_MASK)
1149	&& !((uintptr_t)pvFault & 3)
1150	&& (pRegFrame->eax == 0 \|\| pRegFrame->eax == 0x80) /* the two values observed. */
1151	&& Cpu.mode == CPUMODE_32BIT
1152	&& Cpu.opmode == CPUMODE_32BIT
1153	&& Cpu.addrmode == CPUMODE_32BIT
1154	&& Cpu.prefix == PREFIX_REP
1155	&& !pRegFrame->eflags.Bits.u1DF
1156	)
1157	{
1158	rc = pgmPoolAccessHandlerSTOSD(pVM, pPool, pPage, &Cpu, pRegFrame, GCPhysFault, pvFault);
1159	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,RepStosd), a);
1160	pgmUnlock(pVM);
1161	return rc;
1162	}
1163
1164	/* REP prefix, don't bother. */
1165	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,RepPrefix));
1166	Log4(("pgmPoolAccessHandler: eax=%#x ecx=%#x edi=%#x esi=%#x rip=%RGv opcode=%d prefix=%#x\n",
1167	pRegFrame->eax, pRegFrame->ecx, pRegFrame->edi, pRegFrame->esi, (RTGCPTR)pRegFrame->rip, Cpu.pCurInstr->opcode, Cpu.prefix));
1168	}
1169
1170	/*
1171	* Not worth it, so flush it.
1172	*
1173	* If we considered it to be reused, don't go back to ring-3
1174	* to emulate failed instructions since we usually cannot
1175	* interpret then. This may be a bit risky, in which case
1176	* the reuse detection must be fixed.
1177	*/
1178	rc = pgmPoolAccessHandlerFlush(pVM, pVCpu, pPool, pPage, &Cpu, pRegFrame, GCPhysFault, pvFault);
1179	if (rc == VINF_EM_RAW_EMULATE_INSTR && fReused)
1180	rc = VINF_SUCCESS;
1181	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,FlushPage), a);
1182	pgmUnlock(pVM);
1183	return rc;
1184	}
1185
1186	# endif /* !IN_RING3 */
1187	#endif /* PGMPOOL_WITH_MONITORING */
1188
1189	#ifdef PGMPOOL_WITH_CACHE
1190
1191	/**
1192	* Inserts a page into the GCPhys hash table.
1193	*
1194	* @param pPool The pool.
1195	* @param pPage The page.
1196	*/
1197	DECLINLINE(void) pgmPoolHashInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1198	{
1199	Log3(("pgmPoolHashInsert: %RGp\n", pPage->GCPhys));
1200	Assert(pPage->GCPhys != NIL_RTGCPHYS); Assert(pPage->iNext == NIL_PGMPOOL_IDX);
1201	uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1202	pPage->iNext = pPool->aiHash[iHash];
1203	pPool->aiHash[iHash] = pPage->idx;
1204	}
1205
1206
1207	/**
1208	* Removes a page from the GCPhys hash table.
1209	*
1210	* @param pPool The pool.
1211	* @param pPage The page.
1212	*/
1213	DECLINLINE(void) pgmPoolHashRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1214	{
1215	Log3(("pgmPoolHashRemove: %RGp\n", pPage->GCPhys));
1216	uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1217	if (pPool->aiHash[iHash] == pPage->idx)
1218	pPool->aiHash[iHash] = pPage->iNext;
1219	else
1220	{
1221	uint16_t iPrev = pPool->aiHash[iHash];
1222	for (;;)
1223	{
1224	const int16_t i = pPool->aPages[iPrev].iNext;
1225	if (i == pPage->idx)
1226	{
1227	pPool->aPages[iPrev].iNext = pPage->iNext;
1228	break;
1229	}
1230	if (i == NIL_PGMPOOL_IDX)
1231	{
1232	AssertReleaseMsgFailed(("GCPhys=%RGp idx=%#x\n", pPage->GCPhys, pPage->idx));
1233	break;
1234	}
1235	iPrev = i;
1236	}
1237	}
1238	pPage->iNext = NIL_PGMPOOL_IDX;
1239	}
1240
1241
1242	/**
1243	* Frees up one cache page.
1244	*
1245	* @returns VBox status code.
1246	* @retval VINF_SUCCESS on success.
1247	* @param pPool The pool.
1248	* @param iUser The user index.
1249	*/
1250	static int pgmPoolCacheFreeOne(PPGMPOOL pPool, uint16_t iUser)
1251	{
1252	#ifndef IN_RC
1253	const PVM pVM = pPool->CTX_SUFF(pVM);
1254	#endif
1255	Assert(pPool->iAgeHead != pPool->iAgeTail); /* We shouldn't be here if there < 2 cached entries! */
1256	STAM_COUNTER_INC(&pPool->StatCacheFreeUpOne);
1257
1258	/*
1259	* Select one page from the tail of the age list.
1260	*/
1261	PPGMPOOLPAGE pPage;
1262	for (unsigned iLoop = 0; ; iLoop++)
1263	{
1264	uint16_t iToFree = pPool->iAgeTail;
1265	if (iToFree == iUser)
1266	iToFree = pPool->aPages[iToFree].iAgePrev;
1267	/* This is the alternative to the SyncCR3 pgmPoolCacheUsed calls.
1268	if (pPool->aPages[iToFree].iUserHead != NIL_PGMPOOL_USER_INDEX)
1269	{
1270	uint16_t i = pPool->aPages[iToFree].iAgePrev;
1271	for (unsigned j = 0; j < 10 && i != NIL_PGMPOOL_USER_INDEX; j++, i = pPool->aPages[i].iAgePrev)
1272	{
1273	if (pPool->aPages[iToFree].iUserHead == NIL_PGMPOOL_USER_INDEX)
1274	continue;
1275	iToFree = i;
1276	break;
1277	}
1278	}
1279	*/
1280	Assert(iToFree != iUser);
1281	AssertRelease(iToFree != NIL_PGMPOOL_IDX);
1282	pPage = &pPool->aPages[iToFree];
1283
1284	/*
1285	* Reject any attempts at flushing the currently active shadow CR3 mapping.
1286	* Call pgmPoolCacheUsed to move the page to the head of the age list.
1287	*/
1288	if (!pgmPoolIsPageLocked(&pPool->CTX_SUFF(pVM)->pgm.s, pPage))
1289	break;
1290	LogFlow(("pgmPoolCacheFreeOne: refuse CR3 mapping\n"));
1291	pgmPoolCacheUsed(pPool, pPage);
1292	AssertLogRelReturn(iLoop < 8192, VERR_INTERNAL_ERROR);
1293	}
1294
1295	/*
1296	* Found a usable page, flush it and return.
1297	*/
1298	int rc = pgmPoolFlushPage(pPool, pPage);
1299	/* This flush was initiated by us and not the guest, so explicitly flush the TLB. */
1300	if (rc == VINF_SUCCESS)
1301	PGM_INVL_ALL_VCPU_TLBS(pVM);
1302	return rc;
1303	}
1304
1305
1306	/**
1307	* Checks if a kind mismatch is really a page being reused
1308	* or if it's just normal remappings.
1309	*
1310	* @returns true if reused and the cached page (enmKind1) should be flushed
1311	* @returns false if not reused.
1312	* @param enmKind1 The kind of the cached page.
1313	* @param enmKind2 The kind of the requested page.
1314	*/
1315	static bool pgmPoolCacheReusedByKind(PGMPOOLKIND enmKind1, PGMPOOLKIND enmKind2)
1316	{
1317	switch (enmKind1)
1318	{
1319	/*
1320	* Never reuse them. There is no remapping in non-paging mode.
1321	*/
1322	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1323	case PGMPOOLKIND_32BIT_PD_PHYS:
1324	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1325	case PGMPOOLKIND_PAE_PD_PHYS:
1326	case PGMPOOLKIND_PAE_PDPT_PHYS:
1327	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1328	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1329	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1330	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1331	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1332	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT: /* never reuse them for other types */
1333	return false;
1334
1335	/*
1336	* It's perfectly fine to reuse these, except for PAE and non-paging stuff.
1337	*/
1338	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1339	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1340	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1341	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1342	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1343	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1344	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1345	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1346	case PGMPOOLKIND_32BIT_PD:
1347	case PGMPOOLKIND_PAE_PDPT:
1348	switch (enmKind2)
1349	{
1350	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1351	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1352	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1353	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1354	case PGMPOOLKIND_64BIT_PML4:
1355	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1356	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1357	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1358	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1359	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1360	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1361	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1362	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1363	return true;
1364	default:
1365	return false;
1366	}
1367
1368	/*
1369	* It's perfectly fine to reuse these, except for PAE and non-paging stuff.
1370	*/
1371	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1372	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1373	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1374	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1375	case PGMPOOLKIND_64BIT_PML4:
1376	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1377	switch (enmKind2)
1378	{
1379	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1380	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1381	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1382	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1383	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1384	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1385	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1386	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1387	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1388	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1389	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1390	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1391	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1392	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1393	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1394	return true;
1395	default:
1396	return false;
1397	}
1398
1399	/*
1400	* These cannot be flushed, and it's common to reuse the PDs as PTs.
1401	*/
1402	case PGMPOOLKIND_ROOT_NESTED:
1403	return false;
1404
1405	default:
1406	AssertFatalMsgFailed(("enmKind1=%d\n", enmKind1));
1407	}
1408	}
1409
1410
1411	/**
1412	* Attempts to satisfy a pgmPoolAlloc request from the cache.
1413	*
1414	* @returns VBox status code.
1415	* @retval VINF_PGM_CACHED_PAGE on success.
1416	* @retval VERR_FILE_NOT_FOUND if not found.
1417	* @param pPool The pool.
1418	* @param GCPhys The GC physical address of the page we're gonna shadow.
1419	* @param enmKind The kind of mapping.
1420	* @param iUser The shadow page pool index of the user table.
1421	* @param iUserTable The index into the user table (shadowed).
1422	* @param ppPage Where to store the pointer to the page.
1423	*/
1424	static int pgmPoolCacheAlloc(PPGMPOOL pPool, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage)
1425	{
1426	#ifndef IN_RC
1427	const PVM pVM = pPool->CTX_SUFF(pVM);
1428	#endif
1429	/*
1430	* Look up the GCPhys in the hash.
1431	*/
1432	unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
1433	Log3(("pgmPoolCacheAlloc: %RGp kind %s iUser=%x iUserTable=%x SLOT=%d\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable, i));
1434	if (i != NIL_PGMPOOL_IDX)
1435	{
1436	do
1437	{
1438	PPGMPOOLPAGE pPage = &pPool->aPages[i];
1439	Log4(("pgmPoolCacheAlloc: slot %d found page %RGp\n", i, pPage->GCPhys));
1440	if (pPage->GCPhys == GCPhys)
1441	{
1442	if ((PGMPOOLKIND)pPage->enmKind == enmKind)
1443	{
1444	/* Put it at the start of the use list to make sure pgmPoolTrackAddUser
1445	* doesn't flush it in case there are no more free use records.
1446	*/
1447	pgmPoolCacheUsed(pPool, pPage);
1448
1449	int rc = pgmPoolTrackAddUser(pPool, pPage, iUser, iUserTable);
1450	if (RT_SUCCESS(rc))
1451	{
1452	Assert((PGMPOOLKIND)pPage->enmKind == enmKind);
1453	*ppPage = pPage;
1454	STAM_COUNTER_INC(&pPool->StatCacheHits);
1455	return VINF_PGM_CACHED_PAGE;
1456	}
1457	return rc;
1458	}
1459
1460	/*
1461	* The kind is different. In some cases we should now flush the page
1462	* as it has been reused, but in most cases this is normal remapping
1463	* of PDs as PT or big pages using the GCPhys field in a slightly
1464	* different way than the other kinds.
1465	*/
1466	if (pgmPoolCacheReusedByKind((PGMPOOLKIND)pPage->enmKind, enmKind))
1467	{
1468	STAM_COUNTER_INC(&pPool->StatCacheKindMismatches);
1469	pgmPoolFlushPage(pPool, pPage);
1470	PGM_INVL_VCPU_TLBS(VMMGetCpu(pVM)); /* see PT handler. */
1471	break;
1472	}
1473	}
1474
1475	/* next */
1476	i = pPage->iNext;
1477	} while (i != NIL_PGMPOOL_IDX);
1478	}
1479
1480	Log3(("pgmPoolCacheAlloc: Missed GCPhys=%RGp enmKind=%s\n", GCPhys, pgmPoolPoolKindToStr(enmKind)));
1481	STAM_COUNTER_INC(&pPool->StatCacheMisses);
1482	return VERR_FILE_NOT_FOUND;
1483	}
1484
1485
1486	/**
1487	* Inserts a page into the cache.
1488	*
1489	* @param pPool The pool.
1490	* @param pPage The cached page.
1491	* @param fCanBeCached Set if the page is fit for caching from the caller's point of view.
1492	*/
1493	static void pgmPoolCacheInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fCanBeCached)
1494	{
1495	/*
1496	* Insert into the GCPhys hash if the page is fit for that.
1497	*/
1498	Assert(!pPage->fCached);
1499	if (fCanBeCached)
1500	{
1501	pPage->fCached = true;
1502	pgmPoolHashInsert(pPool, pPage);
1503	Log3(("pgmPoolCacheInsert: Caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
1504	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
1505	STAM_COUNTER_INC(&pPool->StatCacheCacheable);
1506	}
1507	else
1508	{
1509	Log3(("pgmPoolCacheInsert: Not caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
1510	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
1511	STAM_COUNTER_INC(&pPool->StatCacheUncacheable);
1512	}
1513
1514	/*
1515	* Insert at the head of the age list.
1516	*/
1517	pPage->iAgePrev = NIL_PGMPOOL_IDX;
1518	pPage->iAgeNext = pPool->iAgeHead;
1519	if (pPool->iAgeHead != NIL_PGMPOOL_IDX)
1520	pPool->aPages[pPool->iAgeHead].iAgePrev = pPage->idx;
1521	else
1522	pPool->iAgeTail = pPage->idx;
1523	pPool->iAgeHead = pPage->idx;
1524	}
1525
1526
1527	/**
1528	* Flushes a cached page.
1529	*
1530	* @param pPool The pool.
1531	* @param pPage The cached page.
1532	*/
1533	static void pgmPoolCacheFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1534	{
1535	Log3(("pgmPoolCacheFlushPage: %RGp\n", pPage->GCPhys));
1536
1537	/*
1538	* Remove the page from the hash.
1539	*/
1540	if (pPage->fCached)
1541	{
1542	pPage->fCached = false;
1543	pgmPoolHashRemove(pPool, pPage);
1544	}
1545	else
1546	Assert(pPage->iNext == NIL_PGMPOOL_IDX);
1547
1548	/*
1549	* Remove it from the age list.
1550	*/
1551	if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
1552	pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
1553	else
1554	pPool->iAgeTail = pPage->iAgePrev;
1555	if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
1556	pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
1557	else
1558	pPool->iAgeHead = pPage->iAgeNext;
1559	pPage->iAgeNext = NIL_PGMPOOL_IDX;
1560	pPage->iAgePrev = NIL_PGMPOOL_IDX;
1561	}
1562
1563	#endif /* PGMPOOL_WITH_CACHE */
1564	#ifdef PGMPOOL_WITH_MONITORING
1565
1566	/**
1567	* Looks for pages sharing the monitor.
1568	*
1569	* @returns Pointer to the head page.
1570	* @returns NULL if not found.
1571	* @param pPool The Pool
1572	* @param pNewPage The page which is going to be monitored.
1573	*/
1574	static PPGMPOOLPAGE pgmPoolMonitorGetPageByGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pNewPage)
1575	{
1576	#ifdef PGMPOOL_WITH_CACHE
1577	/*
1578	* Look up the GCPhys in the hash.
1579	*/
1580	RTGCPHYS GCPhys = pNewPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
1581	unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
1582	if (i == NIL_PGMPOOL_IDX)
1583	return NULL;
1584	do
1585	{
1586	PPGMPOOLPAGE pPage = &pPool->aPages[i];
1587	if ( pPage->GCPhys - GCPhys < PAGE_SIZE
1588	&& pPage != pNewPage)
1589	{
1590	switch (pPage->enmKind)
1591	{
1592	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1593	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1594	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1595	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1596	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1597	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1598	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1599	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1600	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1601	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1602	case PGMPOOLKIND_64BIT_PML4:
1603	case PGMPOOLKIND_32BIT_PD:
1604	case PGMPOOLKIND_PAE_PDPT:
1605	{
1606	/* find the head */
1607	while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
1608	{
1609	Assert(pPage->iMonitoredPrev != pPage->idx);
1610	pPage = &pPool->aPages[pPage->iMonitoredPrev];
1611	}
1612	return pPage;
1613	}
1614
1615	/* ignore, no monitoring. */
1616	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1617	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1618	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1619	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1620	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1621	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1622	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1623	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1624	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1625	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1626	case PGMPOOLKIND_ROOT_NESTED:
1627	case PGMPOOLKIND_PAE_PD_PHYS:
1628	case PGMPOOLKIND_PAE_PDPT_PHYS:
1629	case PGMPOOLKIND_32BIT_PD_PHYS:
1630	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
1631	break;
1632	default:
1633	AssertFatalMsgFailed(("enmKind=%d idx=%d\n", pPage->enmKind, pPage->idx));
1634	}
1635	}
1636
1637	/* next */
1638	i = pPage->iNext;
1639	} while (i != NIL_PGMPOOL_IDX);
1640	#endif
1641	return NULL;
1642	}
1643
1644
1645	/**
1646	* Enabled write monitoring of a guest page.
1647	*
1648	* @returns VBox status code.
1649	* @retval VINF_SUCCESS on success.
1650	* @param pPool The pool.
1651	* @param pPage The cached page.
1652	*/
1653	static int pgmPoolMonitorInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1654	{
1655	LogFlow(("pgmPoolMonitorInsert %RGp\n", pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1)));
1656
1657	/*
1658	* Filter out the relevant kinds.
1659	*/
1660	switch (pPage->enmKind)
1661	{
1662	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1663	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1664	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1665	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1666	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1667	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1668	case PGMPOOLKIND_64BIT_PML4:
1669	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1670	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1671	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1672	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1673	case PGMPOOLKIND_32BIT_PD:
1674	case PGMPOOLKIND_PAE_PDPT:
1675	break;
1676
1677	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1678	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1679	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1680	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1681	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1682	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1683	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1684	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1685	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1686	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1687	case PGMPOOLKIND_ROOT_NESTED:
1688	/* Nothing to monitor here. */
1689	return VINF_SUCCESS;
1690
1691	case PGMPOOLKIND_32BIT_PD_PHYS:
1692	case PGMPOOLKIND_PAE_PDPT_PHYS:
1693	case PGMPOOLKIND_PAE_PD_PHYS:
1694	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
1695	/* Nothing to monitor here. */
1696	return VINF_SUCCESS;
1697	#ifdef PGMPOOL_WITH_MIXED_PT_CR3
1698	break;
1699	#else
1700	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1701	#endif
1702	default:
1703	AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
1704	}
1705
1706	/*
1707	* Install handler.
1708	*/
1709	int rc;
1710	PPGMPOOLPAGE pPageHead = pgmPoolMonitorGetPageByGCPhys(pPool, pPage);
1711	if (pPageHead)
1712	{
1713	Assert(pPageHead != pPage); Assert(pPageHead->iMonitoredNext != pPage->idx);
1714	Assert(pPageHead->iMonitoredPrev != pPage->idx);
1715	pPage->iMonitoredPrev = pPageHead->idx;
1716	pPage->iMonitoredNext = pPageHead->iMonitoredNext;
1717	if (pPageHead->iMonitoredNext != NIL_PGMPOOL_IDX)
1718	pPool->aPages[pPageHead->iMonitoredNext].iMonitoredPrev = pPage->idx;
1719	pPageHead->iMonitoredNext = pPage->idx;
1720	rc = VINF_SUCCESS;
1721	}
1722	else
1723	{
1724	Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX); Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1725	PVM pVM = pPool->CTX_SUFF(pVM);
1726	const RTGCPHYS GCPhysPage = pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
1727	rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
1728	GCPhysPage, GCPhysPage + (PAGE_SIZE - 1),
1729	pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pPage),
1730	pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pPage),
1731	pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pPage),
1732	pPool->pszAccessHandler);
1733	/** @todo we should probably deal with out-of-memory conditions here, but for now increasing
1734	* the heap size should suffice. */
1735	AssertFatalMsgRC(rc, ("PGMHandlerPhysicalRegisterEx %RGp failed with %Rrc\n", GCPhysPage, rc));
1736	Assert(!(pVM->pgm.s.fGlobalSyncFlags & PGM_GLOBAL_SYNC_CLEAR_PGM_POOL) \|\| VMCPU_FF_ISSET(VMMGetCpu(pVM), VMCPU_FF_PGM_SYNC_CR3));
1737	}
1738	pPage->fMonitored = true;
1739	return rc;
1740	}
1741
1742
1743	/**
1744	* Disables write monitoring of a guest page.
1745	*
1746	* @returns VBox status code.
1747	* @retval VINF_SUCCESS on success.
1748	* @param pPool The pool.
1749	* @param pPage The cached page.
1750	*/
1751	static int pgmPoolMonitorFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1752	{
1753	/*
1754	* Filter out the relevant kinds.
1755	*/
1756	switch (pPage->enmKind)
1757	{
1758	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1759	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1760	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1761	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1762	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1763	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1764	case PGMPOOLKIND_64BIT_PML4:
1765	case PGMPOOLKIND_32BIT_PD:
1766	case PGMPOOLKIND_PAE_PDPT:
1767	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1768	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1769	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1770	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1771	break;
1772
1773	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1774	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1775	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1776	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1777	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1778	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1779	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1780	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1781	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1782	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1783	case PGMPOOLKIND_ROOT_NESTED:
1784	case PGMPOOLKIND_PAE_PD_PHYS:
1785	case PGMPOOLKIND_PAE_PDPT_PHYS:
1786	case PGMPOOLKIND_32BIT_PD_PHYS:
1787	/* Nothing to monitor here. */
1788	return VINF_SUCCESS;
1789
1790	#ifdef PGMPOOL_WITH_MIXED_PT_CR3
1791	break;
1792	#endif
1793	default:
1794	AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
1795	}
1796
1797	/*
1798	* Remove the page from the monitored list or uninstall it if last.
1799	*/
1800	const PVM pVM = pPool->CTX_SUFF(pVM);
1801	int rc;
1802	if ( pPage->iMonitoredNext != NIL_PGMPOOL_IDX
1803	\|\| pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
1804	{
1805	if (pPage->iMonitoredPrev == NIL_PGMPOOL_IDX)
1806	{
1807	PPGMPOOLPAGE pNewHead = &pPool->aPages[pPage->iMonitoredNext];
1808	pNewHead->iMonitoredPrev = NIL_PGMPOOL_IDX;
1809	rc = PGMHandlerPhysicalChangeCallbacks(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1),
1810	pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pNewHead),
1811	pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pNewHead),
1812	pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pNewHead),
1813	pPool->pszAccessHandler);
1814	AssertFatalRCSuccess(rc);
1815	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
1816	}
1817	else
1818	{
1819	pPool->aPages[pPage->iMonitoredPrev].iMonitoredNext = pPage->iMonitoredNext;
1820	if (pPage->iMonitoredNext != NIL_PGMPOOL_IDX)
1821	{
1822	pPool->aPages[pPage->iMonitoredNext].iMonitoredPrev = pPage->iMonitoredPrev;
1823	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
1824	}
1825	pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
1826	rc = VINF_SUCCESS;
1827	}
1828	}
1829	else
1830	{
1831	rc = PGMHandlerPhysicalDeregister(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1));
1832	AssertFatalRC(rc);
1833	AssertMsg(!(pVM->pgm.s.fGlobalSyncFlags & PGM_GLOBAL_SYNC_CLEAR_PGM_POOL) \|\| VMCPU_FF_ISSET(VMMGetCpu(pVM), VMCPU_FF_PGM_SYNC_CR3),
1834	("%#x %#x\n", pVM->pgm.s.fGlobalSyncFlags, pVM->fGlobalForcedActions));
1835	}
1836	pPage->fMonitored = false;
1837
1838	/*
1839	* Remove it from the list of modified pages (if in it).
1840	*/
1841	pgmPoolMonitorModifiedRemove(pPool, pPage);
1842
1843	return rc;
1844	}
1845
1846
1847	/**
1848	* Inserts the page into the list of modified pages.
1849	*
1850	* @param pPool The pool.
1851	* @param pPage The page.
1852	*/
1853	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1854	{
1855	Log3(("pgmPoolMonitorModifiedInsert: idx=%d\n", pPage->idx));
1856	AssertMsg( pPage->iModifiedNext == NIL_PGMPOOL_IDX
1857	&& pPage->iModifiedPrev == NIL_PGMPOOL_IDX
1858	&& pPool->iModifiedHead != pPage->idx,
1859	("Next=%d Prev=%d idx=%d cModifications=%d Head=%d cModifiedPages=%d\n",
1860	pPage->iModifiedNext, pPage->iModifiedPrev, pPage->idx, pPage->cModifications,
1861	pPool->iModifiedHead, pPool->cModifiedPages));
1862
1863	pPage->iModifiedNext = pPool->iModifiedHead;
1864	if (pPool->iModifiedHead != NIL_PGMPOOL_IDX)
1865	pPool->aPages[pPool->iModifiedHead].iModifiedPrev = pPage->idx;
1866	pPool->iModifiedHead = pPage->idx;
1867	pPool->cModifiedPages++;
1868	#ifdef VBOX_WITH_STATISTICS
1869	if (pPool->cModifiedPages > pPool->cModifiedPagesHigh)
1870	pPool->cModifiedPagesHigh = pPool->cModifiedPages;
1871	#endif
1872	}
1873
1874
1875	/**
1876	* Removes the page from the list of modified pages and resets the
1877	* moficiation counter.
1878	*
1879	* @param pPool The pool.
1880	* @param pPage The page which is believed to be in the list of modified pages.
1881	*/
1882	static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1883	{
1884	Log3(("pgmPoolMonitorModifiedRemove: idx=%d cModifications=%d\n", pPage->idx, pPage->cModifications));
1885	if (pPool->iModifiedHead == pPage->idx)
1886	{
1887	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
1888	pPool->iModifiedHead = pPage->iModifiedNext;
1889	if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
1890	{
1891	pPool->aPages[pPage->iModifiedNext].iModifiedPrev = NIL_PGMPOOL_IDX;
1892	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
1893	}
1894	pPool->cModifiedPages--;
1895	}
1896	else if (pPage->iModifiedPrev != NIL_PGMPOOL_IDX)
1897	{
1898	pPool->aPages[pPage->iModifiedPrev].iModifiedNext = pPage->iModifiedNext;
1899	if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
1900	{
1901	pPool->aPages[pPage->iModifiedNext].iModifiedPrev = pPage->iModifiedPrev;
1902	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
1903	}
1904	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
1905	pPool->cModifiedPages--;
1906	}
1907	else
1908	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
1909	pPage->cModifications = 0;
1910	}
1911
1912
1913	/**
1914	* Zaps the list of modified pages, resetting their modification counters in the process.
1915	*
1916	* @param pVM The VM handle.
1917	*/
1918	void pgmPoolMonitorModifiedClearAll(PVM pVM)
1919	{
1920	pgmLock(pVM);
1921	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1922	LogFlow(("pgmPoolMonitorModifiedClearAll: cModifiedPages=%d\n", pPool->cModifiedPages));
1923
1924	unsigned cPages = 0; NOREF(cPages);
1925	uint16_t idx = pPool->iModifiedHead;
1926	pPool->iModifiedHead = NIL_PGMPOOL_IDX;
1927	while (idx != NIL_PGMPOOL_IDX)
1928	{
1929	PPGMPOOLPAGE pPage = &pPool->aPages[idx];
1930	idx = pPage->iModifiedNext;
1931	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
1932	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
1933	pPage->cModifications = 0;
1934	Assert(++cPages);
1935	}
1936	AssertMsg(cPages == pPool->cModifiedPages, ("%d != %d\n", cPages, pPool->cModifiedPages));
1937	pPool->cModifiedPages = 0;
1938	pgmUnlock(pVM);
1939	}
1940
1941
1942	#ifdef IN_RING3
1943	/**
1944	* Callback to clear all shadow pages and clear all modification counters.
1945	*
1946	* @returns VBox status code.
1947	* @param pVM The VM handle.
1948	* @param pvUser Unused parameter
1949	* @remark Should only be used when monitoring is available, thus placed in
1950	* the PGMPOOL_WITH_MONITORING #ifdef.
1951	*/
1952	DECLCALLBACK(int) pgmPoolClearAll(PVM pVM, void *pvUser)
1953	{
1954	NOREF(pvUser);
1955	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1956	STAM_PROFILE_START(&pPool->StatClearAll, c);
1957	LogFlow(("pgmPoolClearAll: cUsedPages=%d\n", pPool->cUsedPages));
1958
1959	pgmLock(pVM);
1960
1961	/*
1962	* Iterate all the pages until we've encountered all that in use.
1963	* This is simple but not quite optimal solution.
1964	*/
1965	unsigned cModifiedPages = 0; NOREF(cModifiedPages);
1966	unsigned cLeft = pPool->cUsedPages;
1967	unsigned iPage = pPool->cCurPages;
1968	while (--iPage >= PGMPOOL_IDX_FIRST)
1969	{
1970	PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
1971	if (pPage->GCPhys != NIL_RTGCPHYS)
1972	{
1973	switch (pPage->enmKind)
1974	{
1975	/*
1976	* We only care about shadow page tables.
1977	*/
1978	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1979	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1980	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1981	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1982	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1983	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1984	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1985	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1986	{
1987	#ifdef PGMPOOL_WITH_USER_TRACKING
1988	if (pPage->cPresent)
1989	#endif
1990	{
1991	void *pvShw = PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
1992	STAM_PROFILE_START(&pPool->StatZeroPage, z);
1993	ASMMemZeroPage(pvShw);
1994	STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
1995	#ifdef PGMPOOL_WITH_USER_TRACKING
1996	pPage->cPresent = 0;
1997	pPage->iFirstPresent = ~0;
1998	#endif
1999	}
2000	}
2001	/* fall thru */
2002
2003	default:
2004	Assert(!pPage->cModifications \|\| ++cModifiedPages);
2005	Assert(pPage->iModifiedNext == NIL_PGMPOOL_IDX \|\| pPage->cModifications);
2006	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX \|\| pPage->cModifications);
2007	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2008	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2009	pPage->cModifications = 0;
2010	break;
2011
2012	}
2013	if (!--cLeft)
2014	break;
2015	}
2016	}
2017
2018	/* swipe the special pages too. */
2019	for (iPage = PGMPOOL_IDX_FIRST_SPECIAL; iPage < PGMPOOL_IDX_FIRST; iPage++)
2020	{
2021	PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
2022	if (pPage->GCPhys != NIL_RTGCPHYS)
2023	{
2024	Assert(!pPage->cModifications \|\| ++cModifiedPages);
2025	Assert(pPage->iModifiedNext == NIL_PGMPOOL_IDX \|\| pPage->cModifications);
2026	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX \|\| pPage->cModifications);
2027	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2028	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2029	pPage->cModifications = 0;
2030	}
2031	}
2032
2033	#ifndef DEBUG_michael
2034	AssertMsg(cModifiedPages == pPool->cModifiedPages, ("%d != %d\n", cModifiedPages, pPool->cModifiedPages));
2035	#endif
2036	pPool->iModifiedHead = NIL_PGMPOOL_IDX;
2037	pPool->cModifiedPages = 0;
2038
2039	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2040	/*
2041	* Clear all the GCPhys links and rebuild the phys ext free list.
2042	*/
2043	for (PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
2044	pRam;
2045	pRam = pRam->CTX_SUFF(pNext))
2046	{
2047	unsigned iPage = pRam->cb >> PAGE_SHIFT;
2048	while (iPage-- > 0)
2049	PGM_PAGE_SET_TRACKING(&pRam->aPages[iPage], 0);
2050	}
2051
2052	pPool->iPhysExtFreeHead = 0;
2053	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
2054	const unsigned cMaxPhysExts = pPool->cMaxPhysExts;
2055	for (unsigned i = 0; i < cMaxPhysExts; i++)
2056	{
2057	paPhysExts[i].iNext = i + 1;
2058	paPhysExts[i].aidx[0] = NIL_PGMPOOL_IDX;
2059	paPhysExts[i].aidx[1] = NIL_PGMPOOL_IDX;
2060	paPhysExts[i].aidx[2] = NIL_PGMPOOL_IDX;
2061	}
2062	paPhysExts[cMaxPhysExts - 1].iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
2063	#endif
2064
2065	pPool->cPresent = 0;
2066	pgmUnlock(pVM);
2067	PGM_INVL_ALL_VCPU_TLBS(pVM);
2068	STAM_PROFILE_STOP(&pPool->StatClearAll, c);
2069	return VINF_SUCCESS;
2070	}
2071	#endif /* IN_RING3 */
2072
2073
2074	/**
2075	* Handle SyncCR3 pool tasks
2076	*
2077	* @returns VBox status code.
2078	* @retval VINF_SUCCESS if successfully added.
2079	* @retval VINF_PGM_SYNC_CR3 is it needs to be deferred to ring 3 (GC only)
2080	* @param pVM The VM handle.
2081	* @remark Should only be used when monitoring is available, thus placed in
2082	* the PGMPOOL_WITH_MONITORING #ifdef.
2083	*/
2084	int pgmPoolSyncCR3(PVM pVM)
2085	{
2086	LogFlow(("pgmPoolSyncCR3\n"));
2087	/*
2088	* When monitoring shadowed pages, we reset the modification counters on CR3 sync.
2089	* Occasionally we will have to clear all the shadow page tables because we wanted
2090	* to monitor a page which was mapped by too many shadowed page tables. This operation
2091	* sometimes refered to as a 'lightweight flush'.
2092	*/
2093	# ifdef IN_RING3 /* Don't flush in ring-0 or raw mode, it's taking too long. */
2094	if (ASMBitTestAndClear(&pVM->pgm.s.fGlobalSyncFlags, PGM_GLOBAL_SYNC_CLEAR_PGM_POOL_BIT))
2095	{
2096	VMMR3AtomicExecuteHandler(pVM, pgmPoolClearAll, NULL);
2097	# else /* !IN_RING3 */
2098	if (pVM->pgm.s.fGlobalSyncFlags & PGM_GLOBAL_SYNC_CLEAR_PGM_POOL)
2099	{
2100	LogFlow(("SyncCR3: PGM_GLOBAL_SYNC_CLEAR_PGM_POOL is set -> VINF_PGM_SYNC_CR3\n"));
2101	VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
2102	return VINF_PGM_SYNC_CR3;
2103	# endif /* !IN_RING3 */
2104	}
2105	else
2106	pgmPoolMonitorModifiedClearAll(pVM);
2107
2108	return VINF_SUCCESS;
2109	}
2110
2111	#endif /* PGMPOOL_WITH_MONITORING */
2112	#ifdef PGMPOOL_WITH_USER_TRACKING
2113
2114	/**
2115	* Frees up at least one user entry.
2116	*
2117	* @returns VBox status code.
2118	* @retval VINF_SUCCESS if successfully added.
2119	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2120	* @param pPool The pool.
2121	* @param iUser The user index.
2122	*/
2123	static int pgmPoolTrackFreeOneUser(PPGMPOOL pPool, uint16_t iUser)
2124	{
2125	STAM_COUNTER_INC(&pPool->StatTrackFreeUpOneUser);
2126	#ifdef PGMPOOL_WITH_CACHE
2127	/*
2128	* Just free cached pages in a braindead fashion.
2129	*/
2130	/** @todo walk the age list backwards and free the first with usage. */
2131	int rc = VINF_SUCCESS;
2132	do
2133	{
2134	int rc2 = pgmPoolCacheFreeOne(pPool, iUser);
2135	if (RT_FAILURE(rc2) && rc == VINF_SUCCESS)
2136	rc = rc2;
2137	} while (pPool->iUserFreeHead == NIL_PGMPOOL_USER_INDEX);
2138	return rc;
2139	#else
2140	/*
2141	* Lazy approach.
2142	*/
2143	/* @todo This path no longer works (CR3 root pages will be flushed)!! */
2144	AssertCompileFailed();
2145	Assert(!CPUMIsGuestInLongMode(pVM));
2146	pgmPoolFlushAllInt(pPool);
2147	return VERR_PGM_POOL_FLUSHED;
2148	#endif
2149	}
2150
2151
2152	/**
2153	* Inserts a page into the cache.
2154	*
2155	* This will create user node for the page, insert it into the GCPhys
2156	* hash, and insert it into the age list.
2157	*
2158	* @returns VBox status code.
2159	* @retval VINF_SUCCESS if successfully added.
2160	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2161	* @param pPool The pool.
2162	* @param pPage The cached page.
2163	* @param GCPhys The GC physical address of the page we're gonna shadow.
2164	* @param iUser The user index.
2165	* @param iUserTable The user table index.
2166	*/
2167	DECLINLINE(int) pgmPoolTrackInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhys, uint16_t iUser, uint32_t iUserTable)
2168	{
2169	int rc = VINF_SUCCESS;
2170	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2171
2172	LogFlow(("pgmPoolTrackInsert GCPhys=%RGp iUser %x iUserTable %x\n", GCPhys, iUser, iUserTable));
2173
2174	#ifdef VBOX_STRICT
2175	/*
2176	* Check that the entry doesn't already exists.
2177	*/
2178	if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
2179	{
2180	uint16_t i = pPage->iUserHead;
2181	do
2182	{
2183	Assert(i < pPool->cMaxUsers);
2184	AssertMsg(paUsers[i].iUser != iUser \|\| paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
2185	i = paUsers[i].iNext;
2186	} while (i != NIL_PGMPOOL_USER_INDEX);
2187	}
2188	#endif
2189
2190	/*
2191	* Find free a user node.
2192	*/
2193	uint16_t i = pPool->iUserFreeHead;
2194	if (i == NIL_PGMPOOL_USER_INDEX)
2195	{
2196	int rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2197	if (RT_FAILURE(rc))
2198	return rc;
2199	i = pPool->iUserFreeHead;
2200	}
2201
2202	/*
2203	* Unlink the user node from the free list,
2204	* initialize and insert it into the user list.
2205	*/
2206	pPool->iUserFreeHead = paUsers[i].iNext;
2207	paUsers[i].iNext = NIL_PGMPOOL_USER_INDEX;
2208	paUsers[i].iUser = iUser;
2209	paUsers[i].iUserTable = iUserTable;
2210	pPage->iUserHead = i;
2211
2212	/*
2213	* Insert into cache and enable monitoring of the guest page if enabled.
2214	*
2215	* Until we implement caching of all levels, including the CR3 one, we'll
2216	* have to make sure we don't try monitor & cache any recursive reuse of
2217	* a monitored CR3 page. Because all windows versions are doing this we'll
2218	* have to be able to do combined access monitoring, CR3 + PT and
2219	* PD + PT (guest PAE).
2220	*
2221	* Update:
2222	* We're now cooperating with the CR3 monitor if an uncachable page is found.
2223	*/
2224	#if defined(PGMPOOL_WITH_MONITORING) \|\| defined(PGMPOOL_WITH_CACHE)
2225	# ifdef PGMPOOL_WITH_MIXED_PT_CR3
2226	const bool fCanBeMonitored = true;
2227	# else
2228	bool fCanBeMonitored = pPool->CTX_SUFF(pVM)->pgm.s.GCPhysGstCR3Monitored == NIL_RTGCPHYS
2229	\|\| (GCPhys & X86_PTE_PAE_PG_MASK) != (pPool->CTX_SUFF(pVM)->pgm.s.GCPhysGstCR3Monitored & X86_PTE_PAE_PG_MASK)
2230	\|\| pgmPoolIsBigPage((PGMPOOLKIND)pPage->enmKind);
2231	# endif
2232	# ifdef PGMPOOL_WITH_CACHE
2233	pgmPoolCacheInsert(pPool, pPage, fCanBeMonitored); /* This can be expanded. */
2234	# endif
2235	if (fCanBeMonitored)
2236	{
2237	# ifdef PGMPOOL_WITH_MONITORING
2238	rc = pgmPoolMonitorInsert(pPool, pPage);
2239	AssertRC(rc);
2240	}
2241	# endif
2242	#endif /* PGMPOOL_WITH_MONITORING */
2243	return rc;
2244	}
2245
2246
2247	# ifdef PGMPOOL_WITH_CACHE /* (only used when the cache is enabled.) */
2248	/**
2249	* Adds a user reference to a page.
2250	*
2251	* This will move the page to the head of the
2252	*
2253	* @returns VBox status code.
2254	* @retval VINF_SUCCESS if successfully added.
2255	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2256	* @param pPool The pool.
2257	* @param pPage The cached page.
2258	* @param iUser The user index.
2259	* @param iUserTable The user table.
2260	*/
2261	static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2262	{
2263	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2264
2265	Log3(("pgmPoolTrackAddUser GCPhys = %RGp iUser %x iUserTable %x\n", pPage->GCPhys, iUser, iUserTable));
2266
2267	# ifdef VBOX_STRICT
2268	/*
2269	* Check that the entry doesn't already exists. We only allow multiple users of top-level paging structures (SHW_POOL_ROOT_IDX).
2270	*/
2271	if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
2272	{
2273	uint16_t i = pPage->iUserHead;
2274	do
2275	{
2276	Assert(i < pPool->cMaxUsers);
2277	AssertMsg(iUser != PGMPOOL_IDX_PD \|\| iUser != PGMPOOL_IDX_PDPT \|\| iUser != PGMPOOL_IDX_NESTED_ROOT \|\| iUser != PGMPOOL_IDX_AMD64_CR3 \|\|
2278	paUsers[i].iUser != iUser \|\| paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
2279	i = paUsers[i].iNext;
2280	} while (i != NIL_PGMPOOL_USER_INDEX);
2281	}
2282	# endif
2283
2284	/*
2285	* Allocate a user node.
2286	*/
2287	uint16_t i = pPool->iUserFreeHead;
2288	if (i == NIL_PGMPOOL_USER_INDEX)
2289	{
2290	int rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2291	if (RT_FAILURE(rc))
2292	return rc;
2293	i = pPool->iUserFreeHead;
2294	}
2295	pPool->iUserFreeHead = paUsers[i].iNext;
2296
2297	/*
2298	* Initialize the user node and insert it.
2299	*/
2300	paUsers[i].iNext = pPage->iUserHead;
2301	paUsers[i].iUser = iUser;
2302	paUsers[i].iUserTable = iUserTable;
2303	pPage->iUserHead = i;
2304
2305	# ifdef PGMPOOL_WITH_CACHE
2306	/*
2307	* Tell the cache to update its replacement stats for this page.
2308	*/
2309	pgmPoolCacheUsed(pPool, pPage);
2310	# endif
2311	return VINF_SUCCESS;
2312	}
2313	# endif /* PGMPOOL_WITH_CACHE */
2314
2315
2316	/**
2317	* Frees a user record associated with a page.
2318	*
2319	* This does not clear the entry in the user table, it simply replaces the
2320	* user record to the chain of free records.
2321	*
2322	* @param pPool The pool.
2323	* @param HCPhys The HC physical address of the shadow page.
2324	* @param iUser The shadow page pool index of the user table.
2325	* @param iUserTable The index into the user table (shadowed).
2326	*/
2327	static void pgmPoolTrackFreeUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2328	{
2329	/*
2330	* Unlink and free the specified user entry.
2331	*/
2332	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2333
2334	Log3(("pgmPoolTrackFreeUser %RGp %x %x\n", pPage->GCPhys, iUser, iUserTable));
2335	/* Special: For PAE and 32-bit paging, there is usually no more than one user. */
2336	uint16_t i = pPage->iUserHead;
2337	if ( i != NIL_PGMPOOL_USER_INDEX
2338	&& paUsers[i].iUser == iUser
2339	&& paUsers[i].iUserTable == iUserTable)
2340	{
2341	pPage->iUserHead = paUsers[i].iNext;
2342
2343	paUsers[i].iUser = NIL_PGMPOOL_IDX;
2344	paUsers[i].iNext = pPool->iUserFreeHead;
2345	pPool->iUserFreeHead = i;
2346	return;
2347	}
2348
2349	/* General: Linear search. */
2350	uint16_t iPrev = NIL_PGMPOOL_USER_INDEX;
2351	while (i != NIL_PGMPOOL_USER_INDEX)
2352	{
2353	if ( paUsers[i].iUser == iUser
2354	&& paUsers[i].iUserTable == iUserTable)
2355	{
2356	if (iPrev != NIL_PGMPOOL_USER_INDEX)
2357	paUsers[iPrev].iNext = paUsers[i].iNext;
2358	else
2359	pPage->iUserHead = paUsers[i].iNext;
2360
2361	paUsers[i].iUser = NIL_PGMPOOL_IDX;
2362	paUsers[i].iNext = pPool->iUserFreeHead;
2363	pPool->iUserFreeHead = i;
2364	return;
2365	}
2366	iPrev = i;
2367	i = paUsers[i].iNext;
2368	}
2369
2370	/* Fatal: didn't find it */
2371	AssertFatalMsgFailed(("Didn't find the user entry! iUser=%#x iUserTable=%#x GCPhys=%RGp\n",
2372	iUser, iUserTable, pPage->GCPhys));
2373	}
2374
2375
2376	/**
2377	* Gets the entry size of a shadow table.
2378	*
2379	* @param enmKind The kind of page.
2380	*
2381	* @returns The size of the entry in bytes. That is, 4 or 8.
2382	* @returns If the kind is not for a table, an assertion is raised and 0 is
2383	* returned.
2384	*/
2385	DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind)
2386	{
2387	switch (enmKind)
2388	{
2389	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2390	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2391	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2392	case PGMPOOLKIND_32BIT_PD:
2393	case PGMPOOLKIND_32BIT_PD_PHYS:
2394	return 4;
2395
2396	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2397	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2398	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2399	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2400	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2401	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2402	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2403	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2404	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2405	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2406	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2407	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2408	case PGMPOOLKIND_64BIT_PML4:
2409	case PGMPOOLKIND_PAE_PDPT:
2410	case PGMPOOLKIND_ROOT_NESTED:
2411	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2412	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2413	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2414	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2415	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2416	case PGMPOOLKIND_PAE_PD_PHYS:
2417	case PGMPOOLKIND_PAE_PDPT_PHYS:
2418	return 8;
2419
2420	default:
2421	AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
2422	}
2423	}
2424
2425
2426	/**
2427	* Gets the entry size of a guest table.
2428	*
2429	* @param enmKind The kind of page.
2430	*
2431	* @returns The size of the entry in bytes. That is, 0, 4 or 8.
2432	* @returns If the kind is not for a table, an assertion is raised and 0 is
2433	* returned.
2434	*/
2435	DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind)
2436	{
2437	switch (enmKind)
2438	{
2439	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2440	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2441	case PGMPOOLKIND_32BIT_PD:
2442	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2443	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2444	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2445	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2446	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2447	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2448	return 4;
2449
2450	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2451	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2452	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2453	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2454	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2455	case PGMPOOLKIND_64BIT_PML4:
2456	case PGMPOOLKIND_PAE_PDPT:
2457	return 8;
2458
2459	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2460	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2461	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2462	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2463	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2464	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2465	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2466	case PGMPOOLKIND_ROOT_NESTED:
2467	case PGMPOOLKIND_PAE_PD_PHYS:
2468	case PGMPOOLKIND_PAE_PDPT_PHYS:
2469	case PGMPOOLKIND_32BIT_PD_PHYS:
2470	/** @todo can we return 0? (nobody is calling this...) */
2471	AssertFailed();
2472	return 0;
2473
2474	default:
2475	AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
2476	}
2477	}
2478
2479	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2480
2481	/**
2482	* Scans one shadow page table for mappings of a physical page.
2483	*
2484	* @param pVM The VM handle.
2485	* @param pPhysPage The guest page in question.
2486	* @param iShw The shadow page table.
2487	* @param cRefs The number of references made in that PT.
2488	*/
2489	static void pgmPoolTrackFlushGCPhysPTInt(PVM pVM, PCPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs)
2490	{
2491	LogFlow(("pgmPoolTrackFlushGCPhysPT: pPhysPage=%R[pgmpage] iShw=%d cRefs=%d\n", pPhysPage, iShw, cRefs));
2492	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2493
2494	/*
2495	* Assert sanity.
2496	*/
2497	Assert(cRefs == 1);
2498	AssertFatalMsg(iShw < pPool->cCurPages && iShw != NIL_PGMPOOL_IDX, ("iShw=%d\n", iShw));
2499	PPGMPOOLPAGE pPage = &pPool->aPages[iShw];
2500
2501	/*
2502	* Then, clear the actual mappings to the page in the shadow PT.
2503	*/
2504	switch (pPage->enmKind)
2505	{
2506	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2507	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2508	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2509	{
2510	const uint32_t u32 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
2511	PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2512	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2513	if ((pPT->a[i].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
2514	{
2515	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX32 cRefs=%#x\n", i, pPT->a[i], cRefs));
2516	pPT->a[i].u = 0;
2517	cRefs--;
2518	if (!cRefs)
2519	return;
2520	}
2521	#ifdef LOG_ENABLED
2522	RTLogPrintf("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent);
2523	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
2524	if ((pPT->a[i].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
2525	{
2526	RTLogPrintf("i=%d cRefs=%d\n", i, cRefs--);
2527	pPT->a[i].u = 0;
2528	}
2529	#endif
2530	AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
2531	break;
2532	}
2533
2534	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2535	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2536	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2537	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2538	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2539	{
2540	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
2541	PX86PTPAE pPT = (PX86PTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2542	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2543	if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK \| X86_PTE_P)) == u64)
2544	{
2545	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX64 cRefs=%#x\n", i, pPT->a[i], cRefs));
2546	pPT->a[i].u = 0;
2547	cRefs--;
2548	if (!cRefs)
2549	return;
2550	}
2551	#ifdef LOG_ENABLED
2552	RTLogPrintf("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent);
2553	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
2554	if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK \| X86_PTE_P)) == u64)
2555	{
2556	RTLogPrintf("i=%d cRefs=%d\n", i, cRefs--);
2557	pPT->a[i].u = 0;
2558	}
2559	#endif
2560	AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d u64=%RX64\n", cRefs, pPage->iFirstPresent, pPage->cPresent, u64));
2561	break;
2562	}
2563
2564	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2565	{
2566	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
2567	PEPTPT pPT = (PEPTPT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2568	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2569	if ((pPT->a[i].u & (EPT_PTE_PG_MASK \| X86_PTE_P)) == u64)
2570	{
2571	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX64 cRefs=%#x\n", i, pPT->a[i], cRefs));
2572	pPT->a[i].u = 0;
2573	cRefs--;
2574	if (!cRefs)
2575	return;
2576	}
2577	#ifdef LOG_ENABLED
2578	RTLogPrintf("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent);
2579	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
2580	if ((pPT->a[i].u & (EPT_PTE_PG_MASK \| X86_PTE_P)) == u64)
2581	{
2582	RTLogPrintf("i=%d cRefs=%d\n", i, cRefs--);
2583	pPT->a[i].u = 0;
2584	}
2585	#endif
2586	AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
2587	break;
2588	}
2589
2590	default:
2591	AssertFatalMsgFailed(("enmKind=%d iShw=%d\n", pPage->enmKind, iShw));
2592	}
2593	}
2594
2595
2596	/**
2597	* Scans one shadow page table for mappings of a physical page.
2598	*
2599	* @param pVM The VM handle.
2600	* @param pPhysPage The guest page in question.
2601	* @param iShw The shadow page table.
2602	* @param cRefs The number of references made in that PT.
2603	*/
2604	void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs)
2605	{
2606	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
2607	LogFlow(("pgmPoolTrackFlushGCPhysPT: pPhysPage=%R[pgmpage] iShw=%d cRefs=%d\n", pPhysPage, iShw, cRefs));
2608	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPT, f);
2609	pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, iShw, cRefs);
2610	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
2611	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPT, f);
2612	}
2613
2614
2615	/**
2616	* Flushes a list of shadow page tables mapping the same physical page.
2617	*
2618	* @param pVM The VM handle.
2619	* @param pPhysPage The guest page in question.
2620	* @param iPhysExt The physical cross reference extent list to flush.
2621	*/
2622	void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt)
2623	{
2624	Assert(PGMIsLockOwner(pVM));
2625	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2626	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTs, f);
2627	LogFlow(("pgmPoolTrackFlushGCPhysPTs: pPhysPage=%R[pgmpage] iPhysExt\n", pPhysPage, iPhysExt));
2628
2629	const uint16_t iPhysExtStart = iPhysExt;
2630	PPGMPOOLPHYSEXT pPhysExt;
2631	do
2632	{
2633	Assert(iPhysExt < pPool->cMaxPhysExts);
2634	pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
2635	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
2636	if (pPhysExt->aidx[i] != NIL_PGMPOOL_IDX)
2637	{
2638	pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, pPhysExt->aidx[i], 1);
2639	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
2640	}
2641
2642	/* next */
2643	iPhysExt = pPhysExt->iNext;
2644	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
2645
2646	/* insert the list into the free list and clear the ram range entry. */
2647	pPhysExt->iNext = pPool->iPhysExtFreeHead;
2648	pPool->iPhysExtFreeHead = iPhysExtStart;
2649	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
2650
2651	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTs, f);
2652	}
2653
2654	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
2655
2656	/**
2657	* Flushes all shadow page table mappings of the given guest page.
2658	*
2659	* This is typically called when the host page backing the guest one has been
2660	* replaced or when the page protection was changed due to an access handler.
2661	*
2662	* @returns VBox status code.
2663	* @retval VINF_SUCCESS if all references has been successfully cleared.
2664	* @retval VINF_PGM_SYNC_CR3 if we're better off with a CR3 sync and a page
2665	* pool cleaning. FF and sync flags are set.
2666	*
2667	* @param pVM The VM handle.
2668	* @param pPhysPage The guest page in question.
2669	* @param pfFlushTLBs This is set to @a true if the shadow TLBs should be
2670	* flushed, it is NOT touched if this isn't necessary.
2671	* The caller MUST initialized this to @a false.
2672	*/
2673	int pgmPoolTrackFlushGCPhys(PVM pVM, PPGMPAGE pPhysPage, bool *pfFlushTLBs)
2674	{
2675	pgmLock(pVM);
2676	int rc = VINF_SUCCESS;
2677	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2678	const uint16_t u16 = PGM_PAGE_GET_TRACKING(pPhysPage);
2679	if (u16)
2680	{
2681	/*
2682	* The zero page is currently screwing up the tracking and we'll
2683	* have to flush the whole shebang. Unless VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2684	* is defined, zero pages won't normally be mapped. Some kind of solution
2685	* will be needed for this problem of course, but it will have to wait...
2686	*/
2687	if (PGM_PAGE_IS_ZERO(pPhysPage))
2688	rc = VINF_PGM_GCPHYS_ALIASED;
2689	else
2690	{
2691	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2692	/* Start a subset here because pgmPoolTrackFlushGCPhysPTsSlow and
2693	pgmPoolTrackFlushGCPhysPTs will/may kill the pool otherwise. */
2694	PVMCPU pVCpu = VMMGetCpu(pVM);
2695	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
2696	# endif
2697
2698	if (PGMPOOL_TD_GET_CREFS(u16) != PGMPOOL_TD_CREFS_PHYSEXT)
2699	pgmPoolTrackFlushGCPhysPT(pVM,
2700	pPhysPage,
2701	PGMPOOL_TD_GET_IDX(u16),
2702	PGMPOOL_TD_GET_CREFS(u16));
2703	else if (u16 != PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED))
2704	pgmPoolTrackFlushGCPhysPTs(pVM, pPhysPage, PGMPOOL_TD_GET_IDX(u16));
2705	else
2706	rc = pgmPoolTrackFlushGCPhysPTsSlow(pVM, pPhysPage);
2707	*pfFlushTLBs = true;
2708
2709	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2710	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
2711	# endif
2712	}
2713	}
2714
2715	#elif defined(PGMPOOL_WITH_CACHE)
2716	if (PGM_PAGE_IS_ZERO(pPhysPage))
2717	rc = VINF_PGM_GCPHYS_ALIASED;
2718	else
2719	{
2720	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2721	/* Start a subset here because pgmPoolTrackFlushGCPhysPTsSlow kill the pool otherwise. */
2722	PVMCPU pVCpu = VMMGetCpu(pVM);
2723	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
2724	# endif
2725	rc = pgmPoolTrackFlushGCPhysPTsSlow(pVM, pPhysPage);
2726	if (rc == VINF_SUCCESS)
2727	*pfFlushTLBs = true;
2728	}
2729
2730	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2731	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
2732	# endif
2733
2734	#else
2735	rc = VINF_PGM_GCPHYS_ALIASED;
2736	#endif
2737
2738	if (rc == VINF_PGM_GCPHYS_ALIASED)
2739	{
2740	pVM->pgm.s.fGlobalSyncFlags \|= PGM_GLOBAL_SYNC_CLEAR_PGM_POOL;
2741	for (unsigned i=0;i<pVM->cCPUs;i++)
2742	{
2743	PVMCPU pVCpu = &pVM->aCpus[i];
2744	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2745	}
2746	rc = VINF_PGM_SYNC_CR3;
2747	}
2748	pgmUnlock(pVM);
2749	return rc;
2750	}
2751
2752
2753	/**
2754	* Scans all shadow page tables for mappings of a physical page.
2755	*
2756	* This may be slow, but it's most likely more efficient than cleaning
2757	* out the entire page pool / cache.
2758	*
2759	* @returns VBox status code.
2760	* @retval VINF_SUCCESS if all references has been successfully cleared.
2761	* @retval VINF_PGM_GCPHYS_ALIASED if we're better off with a CR3 sync and
2762	* a page pool cleaning.
2763	*
2764	* @param pVM The VM handle.
2765	* @param pPhysPage The guest page in question.
2766	*/
2767	int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage)
2768	{
2769	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2770	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTsSlow, s);
2771	LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: cUsedPages=%d cPresent=%d pPhysPage=%R[pgmpage]\n",
2772	pPool->cUsedPages, pPool->cPresent, pPhysPage));
2773
2774	#if 1
2775	/*
2776	* There is a limit to what makes sense.
2777	*/
2778	if (pPool->cPresent > 1024)
2779	{
2780	LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: giving up... (cPresent=%d)\n", pPool->cPresent));
2781	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
2782	return VINF_PGM_GCPHYS_ALIASED;
2783	}
2784	#endif
2785
2786	/*
2787	* Iterate all the pages until we've encountered all that in use.
2788	* This is simple but not quite optimal solution.
2789	*/
2790	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
2791	const uint32_t u32 = u64;
2792	unsigned cLeft = pPool->cUsedPages;
2793	unsigned iPage = pPool->cCurPages;
2794	while (--iPage >= PGMPOOL_IDX_FIRST)
2795	{
2796	PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
2797	if (pPage->GCPhys != NIL_RTGCPHYS)
2798	{
2799	switch (pPage->enmKind)
2800	{
2801	/*
2802	* We only care about shadow page tables.
2803	*/
2804	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2805	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2806	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2807	{
2808	unsigned cPresent = pPage->cPresent;
2809	PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2810	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2811	if (pPT->a[i].n.u1Present)
2812	{
2813	if ((pPT->a[i].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
2814	{
2815	//Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX32\n", iPage, i, pPT->a[i]));
2816	pPT->a[i].u = 0;
2817	}
2818	if (!--cPresent)
2819	break;
2820	}
2821	break;
2822	}
2823
2824	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2825	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2826	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2827	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2828	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2829	{
2830	unsigned cPresent = pPage->cPresent;
2831	PX86PTPAE pPT = (PX86PTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2832	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2833	if (pPT->a[i].n.u1Present)
2834	{
2835	if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK \| X86_PTE_P)) == u64)
2836	{
2837	//Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX64\n", iPage, i, pPT->a[i]));
2838	pPT->a[i].u = 0;
2839	}
2840	if (!--cPresent)
2841	break;
2842	}
2843	break;
2844	}
2845	}
2846	if (!--cLeft)
2847	break;
2848	}
2849	}
2850
2851	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
2852	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
2853	return VINF_SUCCESS;
2854	}
2855
2856
2857	/**
2858	* Clears the user entry in a user table.
2859	*
2860	* This is used to remove all references to a page when flushing it.
2861	*/
2862	static void pgmPoolTrackClearPageUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PCPGMPOOLUSER pUser)
2863	{
2864	Assert(pUser->iUser != NIL_PGMPOOL_IDX);
2865	Assert(pUser->iUser < pPool->cCurPages);
2866	uint32_t iUserTable = pUser->iUserTable;
2867
2868	/*
2869	* Map the user page.
2870	*/
2871	PPGMPOOLPAGE pUserPage = &pPool->aPages[pUser->iUser];
2872	union
2873	{
2874	uint64_t *pau64;
2875	uint32_t *pau32;
2876	} u;
2877	u.pau64 = (uint64_t *)PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pUserPage);
2878
2879	LogFlow(("pgmPoolTrackClearPageUser: clear %x in %s (%RGp) (flushing %s)\n", iUserTable, pgmPoolPoolKindToStr(pUserPage->enmKind), pUserPage->Core.Key, pgmPoolPoolKindToStr(pPage->enmKind)));
2880
2881	/* Safety precaution in case we change the paging for other modes too in the future. */
2882	Assert(!pgmPoolIsPageLocked(&pPool->CTX_SUFF(pVM)->pgm.s, pPage));
2883
2884	#ifdef VBOX_STRICT
2885	/*
2886	* Some sanity checks.
2887	*/
2888	switch (pUserPage->enmKind)
2889	{
2890	case PGMPOOLKIND_32BIT_PD:
2891	case PGMPOOLKIND_32BIT_PD_PHYS:
2892	Assert(iUserTable < X86_PG_ENTRIES);
2893	break;
2894	case PGMPOOLKIND_PAE_PDPT:
2895	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
2896	case PGMPOOLKIND_PAE_PDPT_PHYS:
2897	Assert(iUserTable < 4);
2898	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
2899	break;
2900	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2901	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2902	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2903	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2904	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2905	case PGMPOOLKIND_PAE_PD_PHYS:
2906	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2907	break;
2908	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2909	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2910	Assert(!(u.pau64[iUserTable] & PGM_PDFLAGS_MAPPING));
2911	break;
2912	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2913	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2914	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
2915	break;
2916	case PGMPOOLKIND_64BIT_PML4:
2917	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
2918	/* GCPhys >> PAGE_SHIFT is the index here */
2919	break;
2920	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2921	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2922	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2923	break;
2924
2925	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2926	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2927	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2928	break;
2929
2930	case PGMPOOLKIND_ROOT_NESTED:
2931	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2932	break;
2933
2934	default:
2935	AssertMsgFailed(("enmKind=%d\n", pUserPage->enmKind));
2936	break;
2937	}
2938	#endif /* VBOX_STRICT */
2939
2940	/*
2941	* Clear the entry in the user page.
2942	*/
2943	switch (pUserPage->enmKind)
2944	{
2945	/* 32-bit entries */
2946	case PGMPOOLKIND_32BIT_PD:
2947	case PGMPOOLKIND_32BIT_PD_PHYS:
2948	u.pau32[iUserTable] = 0;
2949	break;
2950
2951	/* 64-bit entries */
2952	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2953	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2954	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2955	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2956	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2957	#if defined(IN_RC)
2958	/* In 32 bits PAE mode we must invalidate the TLB when changing a PDPT entry; the CPU fetches them only during cr3 load, so any
2959	* non-present PDPT will continue to cause page faults.
2960	*/
2961	ASMReloadCR3();
2962	#endif
2963	/* no break */
2964	case PGMPOOLKIND_PAE_PD_PHYS:
2965	case PGMPOOLKIND_PAE_PDPT_PHYS:
2966	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2967	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2968	case PGMPOOLKIND_64BIT_PML4:
2969	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2970	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2971	case PGMPOOLKIND_PAE_PDPT:
2972	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
2973	case PGMPOOLKIND_ROOT_NESTED:
2974	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2975	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2976	u.pau64[iUserTable] = 0;
2977	break;
2978
2979	default:
2980	AssertFatalMsgFailed(("enmKind=%d iUser=%#x iUserTable=%#x\n", pUserPage->enmKind, pUser->iUser, pUser->iUserTable));
2981	}
2982	}
2983
2984
2985	/**
2986	* Clears all users of a page.
2987	*/
2988	static void pgmPoolTrackClearPageUsers(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2989	{
2990	/*
2991	* Free all the user records.
2992	*/
2993	LogFlow(("pgmPoolTrackClearPageUsers %RGp\n", pPage->GCPhys));
2994
2995	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2996	uint16_t i = pPage->iUserHead;
2997	while (i != NIL_PGMPOOL_USER_INDEX)
2998	{
2999	/* Clear enter in user table. */
3000	pgmPoolTrackClearPageUser(pPool, pPage, &paUsers[i]);
3001
3002	/* Free it. */
3003	const uint16_t iNext = paUsers[i].iNext;
3004	paUsers[i].iUser = NIL_PGMPOOL_IDX;
3005	paUsers[i].iNext = pPool->iUserFreeHead;
3006	pPool->iUserFreeHead = i;
3007
3008	/* Next. */
3009	i = iNext;
3010	}
3011	pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
3012	}
3013
3014	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3015
3016	/**
3017	* Allocates a new physical cross reference extent.
3018	*
3019	* @returns Pointer to the allocated extent on success. NULL if we're out of them.
3020	* @param pVM The VM handle.
3021	* @param piPhysExt Where to store the phys ext index.
3022	*/
3023	PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt)
3024	{
3025	Assert(PGMIsLockOwner(pVM));
3026	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3027	uint16_t iPhysExt = pPool->iPhysExtFreeHead;
3028	if (iPhysExt == NIL_PGMPOOL_PHYSEXT_INDEX)
3029	{
3030	STAM_COUNTER_INC(&pPool->StamTrackPhysExtAllocFailures);
3031	return NULL;
3032	}
3033	PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3034	pPool->iPhysExtFreeHead = pPhysExt->iNext;
3035	pPhysExt->iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
3036	*piPhysExt = iPhysExt;
3037	return pPhysExt;
3038	}
3039
3040
3041	/**
3042	* Frees a physical cross reference extent.
3043	*
3044	* @param pVM The VM handle.
3045	* @param iPhysExt The extent to free.
3046	*/
3047	void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt)
3048	{
3049	Assert(PGMIsLockOwner(pVM));
3050	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3051	Assert(iPhysExt < pPool->cMaxPhysExts);
3052	PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3053	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3054	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3055	pPhysExt->iNext = pPool->iPhysExtFreeHead;
3056	pPool->iPhysExtFreeHead = iPhysExt;
3057	}
3058
3059
3060	/**
3061	* Frees a physical cross reference extent.
3062	*
3063	* @param pVM The VM handle.
3064	* @param iPhysExt The extent to free.
3065	*/
3066	void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt)
3067	{
3068	Assert(PGMIsLockOwner(pVM));
3069	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3070
3071	const uint16_t iPhysExtStart = iPhysExt;
3072	PPGMPOOLPHYSEXT pPhysExt;
3073	do
3074	{
3075	Assert(iPhysExt < pPool->cMaxPhysExts);
3076	pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3077	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3078	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3079
3080	/* next */
3081	iPhysExt = pPhysExt->iNext;
3082	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3083
3084	pPhysExt->iNext = pPool->iPhysExtFreeHead;
3085	pPool->iPhysExtFreeHead = iPhysExtStart;
3086	}
3087
3088
3089	/**
3090	* Insert a reference into a list of physical cross reference extents.
3091	*
3092	* @returns The new tracking data for PGMPAGE.
3093	*
3094	* @param pVM The VM handle.
3095	* @param iPhysExt The physical extent index of the list head.
3096	* @param iShwPT The shadow page table index.
3097	*
3098	*/
3099	static uint16_t pgmPoolTrackPhysExtInsert(PVM pVM, uint16_t iPhysExt, uint16_t iShwPT)
3100	{
3101	Assert(PGMIsLockOwner(pVM));
3102	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3103	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3104
3105	/* special common case. */
3106	if (paPhysExts[iPhysExt].aidx[2] == NIL_PGMPOOL_IDX)
3107	{
3108	paPhysExts[iPhysExt].aidx[2] = iShwPT;
3109	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedMany);
3110	LogFlow(("pgmPoolTrackPhysExtAddref: %d:{,,%d}\n", iPhysExt, iShwPT));
3111	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3112	}
3113
3114	/* general treatment. */
3115	const uint16_t iPhysExtStart = iPhysExt;
3116	unsigned cMax = 15;
3117	for (;;)
3118	{
3119	Assert(iPhysExt < pPool->cMaxPhysExts);
3120	for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3121	if (paPhysExts[iPhysExt].aidx[i] == NIL_PGMPOOL_IDX)
3122	{
3123	paPhysExts[iPhysExt].aidx[i] = iShwPT;
3124	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedMany);
3125	LogFlow(("pgmPoolTrackPhysExtAddref: %d:{%d} i=%d cMax=%d\n", iPhysExt, iShwPT, i, cMax));
3126	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExtStart);
3127	}
3128	if (!--cMax)
3129	{
3130	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackOverflows);
3131	pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
3132	LogFlow(("pgmPoolTrackPhysExtAddref: overflow (1) iShwPT=%d\n", iShwPT));
3133	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3134	}
3135	}
3136
3137	/* add another extent to the list. */
3138	PPGMPOOLPHYSEXT pNew = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
3139	if (!pNew)
3140	{
3141	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackOverflows);
3142	pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
3143	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3144	}
3145	pNew->iNext = iPhysExtStart;
3146	pNew->aidx[0] = iShwPT;
3147	LogFlow(("pgmPoolTrackPhysExtAddref: added new extent %d:{%d}->%d\n", iPhysExt, iShwPT, iPhysExtStart));
3148	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3149	}
3150
3151
3152	/**
3153	* Add a reference to guest physical page where extents are in use.
3154	*
3155	* @returns The new tracking data for PGMPAGE.
3156	*
3157	* @param pVM The VM handle.
3158	* @param u16 The ram range flags (top 16-bits).
3159	* @param iShwPT The shadow page table index.
3160	*/
3161	uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT)
3162	{
3163	pgmLock(pVM);
3164	if (PGMPOOL_TD_GET_CREFS(u16) != PGMPOOL_TD_CREFS_PHYSEXT)
3165	{
3166	/*
3167	* Convert to extent list.
3168	*/
3169	Assert(PGMPOOL_TD_GET_CREFS(u16) == 1);
3170	uint16_t iPhysExt;
3171	PPGMPOOLPHYSEXT pPhysExt = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
3172	if (pPhysExt)
3173	{
3174	LogFlow(("pgmPoolTrackPhysExtAddref: new extent: %d:{%d, %d}\n", iPhysExt, PGMPOOL_TD_GET_IDX(u16), iShwPT));
3175	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliased);
3176	pPhysExt->aidx[0] = PGMPOOL_TD_GET_IDX(u16);
3177	pPhysExt->aidx[1] = iShwPT;
3178	u16 = PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3179	}
3180	else
3181	u16 = PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3182	}
3183	else if (u16 != PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED))
3184	{
3185	/*
3186	* Insert into the extent list.
3187	*/
3188	u16 = pgmPoolTrackPhysExtInsert(pVM, PGMPOOL_TD_GET_IDX(u16), iShwPT);
3189	}
3190	else
3191	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedLots);
3192	pgmUnlock(pVM);
3193	return u16;
3194	}
3195
3196
3197	/**
3198	* Clear references to guest physical memory.
3199	*
3200	* @param pPool The pool.
3201	* @param pPage The page.
3202	* @param pPhysPage Pointer to the aPages entry in the ram range.
3203	*/
3204	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMPAGE pPhysPage)
3205	{
3206	const unsigned cRefs = PGM_PAGE_GET_TD_CREFS(pPhysPage);
3207	AssertFatalMsg(cRefs == PGMPOOL_TD_CREFS_PHYSEXT, ("cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
3208
3209	uint16_t iPhysExt = PGM_PAGE_GET_TD_IDX(pPhysPage);
3210	if (iPhysExt != PGMPOOL_TD_IDX_OVERFLOWED)
3211	{
3212	PVM pVM = pPool->CTX_SUFF(pVM);
3213	pgmLock(pVM);
3214
3215	uint16_t iPhysExtPrev = NIL_PGMPOOL_PHYSEXT_INDEX;
3216	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3217	do
3218	{
3219	Assert(iPhysExt < pPool->cMaxPhysExts);
3220
3221	/*
3222	* Look for the shadow page and check if it's all freed.
3223	*/
3224	for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3225	{
3226	if (paPhysExts[iPhysExt].aidx[i] == pPage->idx)
3227	{
3228	paPhysExts[iPhysExt].aidx[i] = NIL_PGMPOOL_IDX;
3229
3230	for (i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3231	if (paPhysExts[iPhysExt].aidx[i] != NIL_PGMPOOL_IDX)
3232	{
3233	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d\n", pPhysPage, pPage->idx));
3234	pgmUnlock(pVM);
3235	return;
3236	}
3237
3238	/* we can free the node. */
3239	const uint16_t iPhysExtNext = paPhysExts[iPhysExt].iNext;
3240	if ( iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX
3241	&& iPhysExtNext == NIL_PGMPOOL_PHYSEXT_INDEX)
3242	{
3243	/* lonely node */
3244	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3245	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d lonely\n", pPhysPage, pPage->idx));
3246	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
3247	}
3248	else if (iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX)
3249	{
3250	/* head */
3251	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d head\n", pPhysPage, pPage->idx));
3252	PGM_PAGE_SET_TRACKING(pPhysPage, PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExtNext));
3253	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3254	}
3255	else
3256	{
3257	/* in list */
3258	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d\n", pPhysPage, pPage->idx));
3259	paPhysExts[iPhysExtPrev].iNext = iPhysExtNext;
3260	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3261	}
3262	iPhysExt = iPhysExtNext;
3263	pgmUnlock(pVM);
3264	return;
3265	}
3266	}
3267
3268	/* next */
3269	iPhysExtPrev = iPhysExt;
3270	iPhysExt = paPhysExts[iPhysExt].iNext;
3271	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3272
3273	pgmUnlock(pVM);
3274	AssertFatalMsgFailed(("not-found! cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
3275	}
3276	else /* nothing to do */
3277	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage]\n", pPhysPage));
3278	}
3279
3280
3281	/**
3282	* Clear references to guest physical memory.
3283	*
3284	* This is the same as pgmPoolTracDerefGCPhys except that the guest physical address
3285	* is assumed to be correct, so the linear search can be skipped and we can assert
3286	* at an earlier point.
3287	*
3288	* @param pPool The pool.
3289	* @param pPage The page.
3290	* @param HCPhys The host physical address corresponding to the guest page.
3291	* @param GCPhys The guest physical address corresponding to HCPhys.
3292	*/
3293	static void pgmPoolTracDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhys)
3294	{
3295	/*
3296	* Walk range list.
3297	*/
3298	PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
3299	while (pRam)
3300	{
3301	RTGCPHYS off = GCPhys - pRam->GCPhys;
3302	if (off < pRam->cb)
3303	{
3304	/* does it match? */
3305	const unsigned iPage = off >> PAGE_SHIFT;
3306	Assert(PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]));
3307	#ifdef LOG_ENABLED
3308	RTHCPHYS HCPhysPage = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]);
3309	Log2(("pgmPoolTracDerefGCPhys %RHp vs %RHp\n", HCPhysPage, HCPhys));
3310	#endif
3311	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
3312	{
3313	pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
3314	return;
3315	}
3316	break;
3317	}
3318	pRam = pRam->CTX_SUFF(pNext);
3319	}
3320	AssertFatalMsgFailed(("HCPhys=%RHp GCPhys=%RGp\n", HCPhys, GCPhys));
3321	}
3322
3323
3324	/**
3325	* Clear references to guest physical memory.
3326	*
3327	* @param pPool The pool.
3328	* @param pPage The page.
3329	* @param HCPhys The host physical address corresponding to the guest page.
3330	* @param GCPhysHint The guest physical address which may corresponding to HCPhys.
3331	*/
3332	static void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint)
3333	{
3334	Log4(("pgmPoolTracDerefGCPhysHint %RHp %RGp\n", HCPhys, GCPhysHint));
3335
3336	/*
3337	* Walk range list.
3338	*/
3339	PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
3340	while (pRam)
3341	{
3342	RTGCPHYS off = GCPhysHint - pRam->GCPhys;
3343	if (off < pRam->cb)
3344	{
3345	/* does it match? */
3346	const unsigned iPage = off >> PAGE_SHIFT;
3347	Assert(PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]));
3348	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
3349	{
3350	pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
3351	return;
3352	}
3353	break;
3354	}
3355	pRam = pRam->CTX_SUFF(pNext);
3356	}
3357
3358	/*
3359	* Damn, the hint didn't work. We'll have to do an expensive linear search.
3360	*/
3361	STAM_COUNTER_INC(&pPool->StatTrackLinearRamSearches);
3362	pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
3363	while (pRam)
3364	{
3365	unsigned iPage = pRam->cb >> PAGE_SHIFT;
3366	while (iPage-- > 0)
3367	{
3368	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
3369	{
3370	Log4(("pgmPoolTracDerefGCPhysHint: Linear HCPhys=%RHp GCPhysHint=%RGp GCPhysReal=%RGp\n",
3371	HCPhys, GCPhysHint, pRam->GCPhys + (iPage << PAGE_SHIFT)));
3372	pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
3373	return;
3374	}
3375	}
3376	pRam = pRam->CTX_SUFF(pNext);
3377	}
3378
3379	AssertFatalMsgFailed(("HCPhys=%RHp GCPhysHint=%RGp\n", HCPhys, GCPhysHint));
3380	}
3381
3382
3383	/**
3384	* Clear references to guest physical memory in a 32-bit / 32-bit page table.
3385	*
3386	* @param pPool The pool.
3387	* @param pPage The page.
3388	* @param pShwPT The shadow page table (mapping of the page).
3389	* @param pGstPT The guest page table.
3390	*/
3391	DECLINLINE(void) pgmPoolTrackDerefPT32Bit32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT, PCX86PT pGstPT)
3392	{
3393	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
3394	if (pShwPT->a[i].n.u1Present)
3395	{
3396	Log4(("pgmPoolTrackDerefPT32Bit32Bit: i=%d pte=%RX32 hint=%RX32\n",
3397	i, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK));
3398	pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK);
3399	if (!--pPage->cPresent)
3400	break;
3401	}
3402	}
3403
3404
3405	/**
3406	* Clear references to guest physical memory in a PAE / 32-bit page table.
3407	*
3408	* @param pPool The pool.
3409	* @param pPage The page.
3410	* @param pShwPT The shadow page table (mapping of the page).
3411	* @param pGstPT The guest page table (just a half one).
3412	*/
3413	DECLINLINE(void) pgmPoolTrackDerefPTPae32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PT pGstPT)
3414	{
3415	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++)
3416	if (pShwPT->a[i].n.u1Present)
3417	{
3418	Log4(("pgmPoolTrackDerefPTPae32Bit: i=%d pte=%RX64 hint=%RX32\n",
3419	i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK));
3420	pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK);
3421	}
3422	}
3423
3424
3425	/**
3426	* Clear references to guest physical memory in a PAE / PAE page table.
3427	*
3428	* @param pPool The pool.
3429	* @param pPage The page.
3430	* @param pShwPT The shadow page table (mapping of the page).
3431	* @param pGstPT The guest page table.
3432	*/
3433	DECLINLINE(void) pgmPoolTrackDerefPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PTPAE pGstPT)
3434	{
3435	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++)
3436	if (pShwPT->a[i].n.u1Present)
3437	{
3438	Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX32 hint=%RX32\n",
3439	i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK));
3440	pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK);
3441	}
3442	}
3443
3444
3445	/**
3446	* Clear references to guest physical memory in a 32-bit / 4MB page table.
3447	*
3448	* @param pPool The pool.
3449	* @param pPage The page.
3450	* @param pShwPT The shadow page table (mapping of the page).
3451	*/
3452	DECLINLINE(void) pgmPoolTrackDerefPT32Bit4MB(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT)
3453	{
3454	RTGCPHYS GCPhys = pPage->GCPhys;
3455	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
3456	if (pShwPT->a[i].n.u1Present)
3457	{
3458	Log4(("pgmPoolTrackDerefPT32Bit4MB: i=%d pte=%RX32 GCPhys=%RGp\n",
3459	i, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys));
3460	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys);
3461	}
3462	}
3463
3464
3465	/**
3466	* Clear references to guest physical memory in a PAE / 2/4MB page table.
3467	*
3468	* @param pPool The pool.
3469	* @param pPage The page.
3470	* @param pShwPT The shadow page table (mapping of the page).
3471	*/
3472	DECLINLINE(void) pgmPoolTrackDerefPTPaeBig(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT)
3473	{
3474	RTGCPHYS GCPhys = pPage->GCPhys;
3475	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
3476	if (pShwPT->a[i].n.u1Present)
3477	{
3478	Log4(("pgmPoolTrackDerefPTPaeBig: i=%d pte=%RX64 hint=%RGp\n",
3479	i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, GCPhys));
3480	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, GCPhys);
3481	}
3482	}
3483
3484	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
3485
3486
3487	/**
3488	* Clear references to shadowed pages in a 32 bits page directory.
3489	*
3490	* @param pPool The pool.
3491	* @param pPage The page.
3492	* @param pShwPD The shadow page directory (mapping of the page).
3493	*/
3494	DECLINLINE(void) pgmPoolTrackDerefPD(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PD pShwPD)
3495	{
3496	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
3497	{
3498	if ( pShwPD->a[i].n.u1Present
3499	&& !(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING)
3500	)
3501	{
3502	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PG_MASK);
3503	if (pSubPage)
3504	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3505	else
3506	AssertFatalMsgFailed(("%x\n", pShwPD->a[i].u & X86_PDE_PG_MASK));
3507	}
3508	}
3509	}
3510
3511	/**
3512	* Clear references to shadowed pages in a PAE (legacy or 64 bits) page directory.
3513	*
3514	* @param pPool The pool.
3515	* @param pPage The page.
3516	* @param pShwPD The shadow page directory (mapping of the page).
3517	*/
3518	DECLINLINE(void) pgmPoolTrackDerefPDPae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPAE pShwPD)
3519	{
3520	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
3521	{
3522	if ( pShwPD->a[i].n.u1Present
3523	&& !(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING)
3524	)
3525	{
3526	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PAE_PG_MASK);
3527	if (pSubPage)
3528	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3529	else
3530	AssertFatalMsgFailed(("%RX64\n", pShwPD->a[i].u & X86_PDE_PAE_PG_MASK));
3531	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3532	}
3533	}
3534	}
3535
3536	/**
3537	* Clear references to shadowed pages in a PAE page directory pointer table.
3538	*
3539	* @param pPool The pool.
3540	* @param pPage The page.
3541	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
3542	*/
3543	DECLINLINE(void) pgmPoolTrackDerefPDPTPae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPT pShwPDPT)
3544	{
3545	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
3546	{
3547	if ( pShwPDPT->a[i].n.u1Present
3548	&& !(pShwPDPT->a[i].u & PGM_PLXFLAGS_MAPPING)
3549	)
3550	{
3551	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & X86_PDPE_PG_MASK);
3552	if (pSubPage)
3553	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3554	else
3555	AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & X86_PDPE_PG_MASK));
3556	}
3557	}
3558	}
3559
3560
3561	/**
3562	* Clear references to shadowed pages in a 64-bit page directory pointer table.
3563	*
3564	* @param pPool The pool.
3565	* @param pPage The page.
3566	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
3567	*/
3568	DECLINLINE(void) pgmPoolTrackDerefPDPT64Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPT pShwPDPT)
3569	{
3570	for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
3571	{
3572	Assert(!(pShwPDPT->a[i].u & PGM_PLXFLAGS_MAPPING));
3573	if (pShwPDPT->a[i].n.u1Present)
3574	{
3575	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & X86_PDPE_PG_MASK);
3576	if (pSubPage)
3577	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3578	else
3579	AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & X86_PDPE_PG_MASK));
3580	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3581	}
3582	}
3583	}
3584
3585
3586	/**
3587	* Clear references to shadowed pages in a 64-bit level 4 page table.
3588	*
3589	* @param pPool The pool.
3590	* @param pPage The page.
3591	* @param pShwPML4 The shadow page directory pointer table (mapping of the page).
3592	*/
3593	DECLINLINE(void) pgmPoolTrackDerefPML464Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PML4 pShwPML4)
3594	{
3595	for (unsigned i = 0; i < RT_ELEMENTS(pShwPML4->a); i++)
3596	{
3597	if (pShwPML4->a[i].n.u1Present)
3598	{
3599	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPML4->a[i].u & X86_PDPE_PG_MASK);
3600	if (pSubPage)
3601	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3602	else
3603	AssertFatalMsgFailed(("%RX64\n", pShwPML4->a[i].u & X86_PML4E_PG_MASK));
3604	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3605	}
3606	}
3607	}
3608
3609
3610	/**
3611	* Clear references to shadowed pages in an EPT page table.
3612	*
3613	* @param pPool The pool.
3614	* @param pPage The page.
3615	* @param pShwPML4 The shadow page directory pointer table (mapping of the page).
3616	*/
3617	DECLINLINE(void) pgmPoolTrackDerefPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPT pShwPT)
3618	{
3619	RTGCPHYS GCPhys = pPage->GCPhys;
3620	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
3621	if (pShwPT->a[i].n.u1Present)
3622	{
3623	Log4(("pgmPoolTrackDerefPTEPT: i=%d pte=%RX64 GCPhys=%RX64\n",
3624	i, pShwPT->a[i].u & EPT_PTE_PG_MASK, pPage->GCPhys));
3625	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & EPT_PTE_PG_MASK, GCPhys);
3626	}
3627	}
3628
3629
3630	/**
3631	* Clear references to shadowed pages in an EPT page directory.
3632	*
3633	* @param pPool The pool.
3634	* @param pPage The page.
3635	* @param pShwPD The shadow page directory (mapping of the page).
3636	*/
3637	DECLINLINE(void) pgmPoolTrackDerefPDEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPD pShwPD)
3638	{
3639	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
3640	{
3641	if (pShwPD->a[i].n.u1Present)
3642	{
3643	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & EPT_PDE_PG_MASK);
3644	if (pSubPage)
3645	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3646	else
3647	AssertFatalMsgFailed(("%RX64\n", pShwPD->a[i].u & EPT_PDE_PG_MASK));
3648	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3649	}
3650	}
3651	}
3652
3653
3654	/**
3655	* Clear references to shadowed pages in an EPT page directory pointer table.
3656	*
3657	* @param pPool The pool.
3658	* @param pPage The page.
3659	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
3660	*/
3661	DECLINLINE(void) pgmPoolTrackDerefPDPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPDPT pShwPDPT)
3662	{
3663	for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
3664	{
3665	if (pShwPDPT->a[i].n.u1Present)
3666	{
3667	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & EPT_PDPTE_PG_MASK);
3668	if (pSubPage)
3669	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3670	else
3671	AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & EPT_PDPTE_PG_MASK));
3672	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3673	}
3674	}
3675	}
3676
3677
3678	/**
3679	* Clears all references made by this page.
3680	*
3681	* This includes other shadow pages and GC physical addresses.
3682	*
3683	* @param pPool The pool.
3684	* @param pPage The page.
3685	*/
3686	static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3687	{
3688	/*
3689	* Map the shadow page and take action according to the page kind.
3690	*/
3691	void *pvShw = PGMPOOL_PAGE_2_LOCKED_PTR(pPool->CTX_SUFF(pVM), pPage);
3692	switch (pPage->enmKind)
3693	{
3694	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3695	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3696	{
3697	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3698	void *pvGst;
3699	int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
3700	pgmPoolTrackDerefPT32Bit32Bit(pPool, pPage, (PX86PT)pvShw, (PCX86PT)pvGst);
3701	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3702	break;
3703	}
3704
3705	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3706	{
3707	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3708	void *pvGst;
3709	int rc = PGM_GCPHYS_2_PTR_EX(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
3710	pgmPoolTrackDerefPTPae32Bit(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PT)pvGst);
3711	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3712	break;
3713	}
3714
3715	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3716	{
3717	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3718	void *pvGst;
3719	int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
3720	pgmPoolTrackDerefPTPaePae(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PTPAE)pvGst);
3721	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3722	break;
3723	}
3724
3725	case PGMPOOLKIND_32BIT_PT_FOR_PHYS: /* treat it like a 4 MB page */
3726	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3727	{
3728	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3729	pgmPoolTrackDerefPT32Bit4MB(pPool, pPage, (PX86PT)pvShw);
3730	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3731	break;
3732	}
3733
3734	case PGMPOOLKIND_PAE_PT_FOR_PHYS: /* treat it like a 2 MB page */
3735	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3736	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3737	{
3738	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3739	pgmPoolTrackDerefPTPaeBig(pPool, pPage, (PX86PTPAE)pvShw);
3740	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3741	break;
3742	}
3743
3744	#else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
3745	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3746	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3747	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3748	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3749	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3750	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3751	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
3752	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3753	break;
3754	#endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
3755
3756	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3757	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3758	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3759	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3760	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3761	case PGMPOOLKIND_PAE_PD_PHYS:
3762	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3763	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3764	pgmPoolTrackDerefPDPae(pPool, pPage, (PX86PDPAE)pvShw);
3765	break;
3766
3767	case PGMPOOLKIND_32BIT_PD_PHYS:
3768	case PGMPOOLKIND_32BIT_PD:
3769	pgmPoolTrackDerefPD(pPool, pPage, (PX86PD)pvShw);
3770	break;
3771
3772	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
3773	case PGMPOOLKIND_PAE_PDPT:
3774	case PGMPOOLKIND_PAE_PDPT_PHYS:
3775	pgmPoolTrackDerefPDPTPae(pPool, pPage, (PX86PDPT)pvShw);
3776	break;
3777
3778	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3779	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3780	pgmPoolTrackDerefPDPT64Bit(pPool, pPage, (PX86PDPT)pvShw);
3781	break;
3782
3783	case PGMPOOLKIND_64BIT_PML4:
3784	pgmPoolTrackDerefPML464Bit(pPool, pPage, (PX86PML4)pvShw);
3785	break;
3786
3787	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
3788	pgmPoolTrackDerefPTEPT(pPool, pPage, (PEPTPT)pvShw);
3789	break;
3790
3791	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3792	pgmPoolTrackDerefPDEPT(pPool, pPage, (PEPTPD)pvShw);
3793	break;
3794
3795	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3796	pgmPoolTrackDerefPDPTEPT(pPool, pPage, (PEPTPDPT)pvShw);
3797	break;
3798
3799	default:
3800	AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
3801	}
3802
3803	/* paranoia, clear the shadow page. Remove this laser (i.e. let Alloc and ClearAll do it). */
3804	STAM_PROFILE_START(&pPool->StatZeroPage, z);
3805	ASMMemZeroPage(pvShw);
3806	STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
3807	pPage->fZeroed = true;
3808	PGMPOOL_UNLOCK_PTR(pPool->CTX_SUFF(pVM), pvShw);
3809	}
3810	#endif /* PGMPOOL_WITH_USER_TRACKING */
3811
3812	/**
3813	* Flushes a pool page.
3814	*
3815	* This moves the page to the free list after removing all user references to it.
3816	*
3817	* @returns VBox status code.
3818	* @retval VINF_SUCCESS on success.
3819	* @param pPool The pool.
3820	* @param HCPhys The HC physical address of the shadow page.
3821	*/
3822	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3823	{
3824	PVM pVM = pPool->CTX_SUFF(pVM);
3825
3826	int rc = VINF_SUCCESS;
3827	STAM_PROFILE_START(&pPool->StatFlushPage, f);
3828	LogFlow(("pgmPoolFlushPage: pPage=%p:{.Key=%RHp, .idx=%d, .enmKind=%s, .GCPhys=%RGp}\n",
3829	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
3830
3831	/*
3832	* Quietly reject any attempts at flushing any of the special root pages.
3833	*/
3834	if (pPage->idx < PGMPOOL_IDX_FIRST)
3835	{
3836	AssertFailed(); /* can no longer happen */
3837	Log(("pgmPoolFlushPage: special root page, rejected. enmKind=%s idx=%d\n", pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx));
3838	return VINF_SUCCESS;
3839	}
3840
3841	pgmLock(pVM);
3842
3843	/*
3844	* Quietly reject any attempts at flushing the currently active shadow CR3 mapping
3845	*/
3846	if (pgmPoolIsPageLocked(&pVM->pgm.s, pPage))
3847	{
3848	AssertMsg( pPage->enmKind == PGMPOOLKIND_64BIT_PML4
3849	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PDPT
3850	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PDPT_FOR_32BIT
3851	\|\| pPage->enmKind == PGMPOOLKIND_32BIT_PD
3852	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD_FOR_PAE_PD
3853	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD
3854	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD
3855	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD
3856	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
3857	("Can't free the shadow CR3! (%RHp vs %RHp kind=%d\n", PGMGetHyperCR3(VMMGetCpu(pVM)), pPage->Core.Key, pPage->enmKind));
3858	Log(("pgmPoolFlushPage: current active shadow CR3, rejected. enmKind=%s idx=%d\n", pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx));
3859	pgmUnlock(pVM);
3860	return VINF_SUCCESS;
3861	}
3862
3863	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3864	/* Start a subset so we won't run out of mapping space. */
3865	PVMCPU pVCpu = VMMGetCpu(pVM);
3866	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
3867	#endif
3868
3869	/*
3870	* Mark the page as being in need of a ASMMemZeroPage().
3871	*/
3872	pPage->fZeroed = false;
3873
3874	#ifdef PGMPOOL_WITH_USER_TRACKING
3875	/*
3876	* Clear the page.
3877	*/
3878	pgmPoolTrackClearPageUsers(pPool, pPage);
3879	STAM_PROFILE_START(&pPool->StatTrackDeref,a);
3880	pgmPoolTrackDeref(pPool, pPage);
3881	STAM_PROFILE_STOP(&pPool->StatTrackDeref,a);
3882	#endif
3883
3884	#ifdef PGMPOOL_WITH_CACHE
3885	/*
3886	* Flush it from the cache.
3887	*/
3888	pgmPoolCacheFlushPage(pPool, pPage);
3889	#endif /* PGMPOOL_WITH_CACHE */
3890
3891	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3892	/* Heavy stuff done. */
3893	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
3894	#endif
3895
3896	#ifdef PGMPOOL_WITH_MONITORING
3897	/*
3898	* Deregistering the monitoring.
3899	*/
3900	if (pPage->fMonitored)
3901	rc = pgmPoolMonitorFlush(pPool, pPage);
3902	#endif
3903
3904	/*
3905	* Free the page.
3906	*/
3907	Assert(pPage->iNext == NIL_PGMPOOL_IDX);
3908	pPage->iNext = pPool->iFreeHead;
3909	pPool->iFreeHead = pPage->idx;
3910	pPage->enmKind = PGMPOOLKIND_FREE;
3911	pPage->GCPhys = NIL_RTGCPHYS;
3912	pPage->fReusedFlushPending = false;
3913
3914	pPool->cUsedPages--;
3915	pgmUnlock(pVM);
3916	STAM_PROFILE_STOP(&pPool->StatFlushPage, f);
3917	return rc;
3918	}
3919
3920
3921	/**
3922	* Frees a usage of a pool page.
3923	*
3924	* The caller is responsible to updating the user table so that it no longer
3925	* references the shadow page.
3926	*
3927	* @param pPool The pool.
3928	* @param HCPhys The HC physical address of the shadow page.
3929	* @param iUser The shadow page pool index of the user table.
3930	* @param iUserTable The index into the user table (shadowed).
3931	*/
3932	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
3933	{
3934	PVM pVM = pPool->CTX_SUFF(pVM);
3935
3936	STAM_PROFILE_START(&pPool->StatFree, a);
3937	LogFlow(("pgmPoolFreeByPage: pPage=%p:{.Key=%RHp, .idx=%d, enmKind=%s} iUser=%#x iUserTable=%#x\n",
3938	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), iUser, iUserTable));
3939	Assert(pPage->idx >= PGMPOOL_IDX_FIRST);
3940	pgmLock(pVM);
3941	#ifdef PGMPOOL_WITH_USER_TRACKING
3942	pgmPoolTrackFreeUser(pPool, pPage, iUser, iUserTable);
3943	#endif
3944	#ifdef PGMPOOL_WITH_CACHE
3945	if (!pPage->fCached)
3946	#endif
3947	pgmPoolFlushPage(pPool, pPage);
3948	pgmUnlock(pVM);
3949	STAM_PROFILE_STOP(&pPool->StatFree, a);
3950	}
3951
3952
3953	/**
3954	* Makes one or more free page free.
3955	*
3956	* @returns VBox status code.
3957	* @retval VINF_SUCCESS on success.
3958	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
3959	*
3960	* @param pPool The pool.
3961	* @param enmKind Page table kind
3962	* @param iUser The user of the page.
3963	*/
3964	static int pgmPoolMakeMoreFreePages(PPGMPOOL pPool, PGMPOOLKIND enmKind, uint16_t iUser)
3965	{
3966	PVM pVM = pPool->CTX_SUFF(pVM);
3967
3968	LogFlow(("pgmPoolMakeMoreFreePages: iUser=%#x\n", iUser));
3969
3970	/*
3971	* If the pool isn't full grown yet, expand it.
3972	*/
3973	if ( pPool->cCurPages < pPool->cMaxPages
3974	#if defined(IN_RC)
3975	/* Hack alert: we can't deal with jumps to ring 3 when called from MapCR3 and allocating pages for PAE PDs. */
3976	&& enmKind != PGMPOOLKIND_PAE_PD_FOR_PAE_PD
3977	&& (enmKind < PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD \|\| enmKind > PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD)
3978	#endif
3979	)
3980	{
3981	STAM_PROFILE_ADV_SUSPEND(&pPool->StatAlloc, a);
3982	#ifdef IN_RING3
3983	int rc = PGMR3PoolGrow(pVM);
3984	#else
3985	int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_POOL_GROW, 0);
3986	#endif
3987	if (RT_FAILURE(rc))
3988	return rc;
3989	STAM_PROFILE_ADV_RESUME(&pPool->StatAlloc, a);
3990	if (pPool->iFreeHead != NIL_PGMPOOL_IDX)
3991	return VINF_SUCCESS;
3992	}
3993
3994	#ifdef PGMPOOL_WITH_CACHE
3995	/*
3996	* Free one cached page.
3997	*/
3998	return pgmPoolCacheFreeOne(pPool, iUser);
3999	#else
4000	/*
4001	* Flush the pool.
4002	*
4003	* If we have tracking enabled, it should be possible to come up with
4004	* a cheap replacement strategy...
4005	*/
4006	/* @todo This path no longer works (CR3 root pages will be flushed)!! */
4007	AssertCompileFailed();
4008	Assert(!CPUMIsGuestInLongMode(pVM));
4009	pgmPoolFlushAllInt(pPool);
4010	return VERR_PGM_POOL_FLUSHED;
4011	#endif
4012	}
4013
4014
4015	/**
4016	* Allocates a page from the pool.
4017	*
4018	* This page may actually be a cached page and not in need of any processing
4019	* on the callers part.
4020	*
4021	* @returns VBox status code.
4022	* @retval VINF_SUCCESS if a NEW page was allocated.
4023	* @retval VINF_PGM_CACHED_PAGE if a CACHED page was returned.
4024	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
4025	* @param pVM The VM handle.
4026	* @param GCPhys The GC physical address of the page we're gonna shadow.
4027	* For 4MB and 2MB PD entries, it's the first address the
4028	* shadow PT is covering.
4029	* @param enmKind The kind of mapping.
4030	* @param iUser The shadow page pool index of the user table.
4031	* @param iUserTable The index into the user table (shadowed).
4032	* @param ppPage Where to store the pointer to the page. NULL is stored here on failure.
4033	*/
4034	int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage)
4035	{
4036	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4037	STAM_PROFILE_ADV_START(&pPool->StatAlloc, a);
4038	LogFlow(("pgmPoolAlloc: GCPhys=%RGp enmKind=%s iUser=%#x iUserTable=%#x\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable));
4039	*ppPage = NULL;
4040	/** @todo CSAM/PGMPrefetchPage messes up here during CSAMR3CheckGates
4041	* (TRPMR3SyncIDT) because of FF priority. Try fix that?
4042	* Assert(!(pVM->pgm.s.fGlobalSyncFlags & PGM_GLOBAL_SYNC_CLEAR_PGM_POOL)); */
4043
4044	pgmLock(pVM);
4045
4046	#ifdef PGMPOOL_WITH_CACHE
4047	if (pPool->fCacheEnabled)
4048	{
4049	int rc2 = pgmPoolCacheAlloc(pPool, GCPhys, enmKind, iUser, iUserTable, ppPage);
4050	if (RT_SUCCESS(rc2))
4051	{
4052	pgmUnlock(pVM);
4053	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4054	LogFlow(("pgmPoolAlloc: cached returns %Rrc ppPage=%p:{.Key=%RHp, .idx=%d}\n", rc2, ppPage, (ppPage)->Core.Key, (ppPage)->idx));
4055	return rc2;
4056	}
4057	}
4058	#endif
4059
4060	/*
4061	* Allocate a new one.
4062	*/
4063	int rc = VINF_SUCCESS;
4064	uint16_t iNew = pPool->iFreeHead;
4065	if (iNew == NIL_PGMPOOL_IDX)
4066	{
4067	rc = pgmPoolMakeMoreFreePages(pPool, enmKind, iUser);
4068	if (RT_FAILURE(rc))
4069	{
4070	pgmUnlock(pVM);
4071	Log(("pgmPoolAlloc: returns %Rrc (Free)\n", rc));
4072	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4073	return rc;
4074	}
4075	iNew = pPool->iFreeHead;
4076	AssertReleaseReturn(iNew != NIL_PGMPOOL_IDX, VERR_INTERNAL_ERROR);
4077	}
4078
4079	/* unlink the free head */
4080	PPGMPOOLPAGE pPage = &pPool->aPages[iNew];
4081	pPool->iFreeHead = pPage->iNext;
4082	pPage->iNext = NIL_PGMPOOL_IDX;
4083
4084	/*
4085	* Initialize it.
4086	*/
4087	pPool->cUsedPages++; /* physical handler registration / pgmPoolTrackFlushGCPhysPTsSlow requirement. */
4088	pPage->enmKind = enmKind;
4089	pPage->GCPhys = GCPhys;
4090	pPage->fSeenNonGlobal = false; /* Set this to 'true' to disable this feature. */
4091	pPage->fMonitored = false;
4092	pPage->fCached = false;
4093	pPage->fReusedFlushPending = false;
4094	#ifdef PGMPOOL_WITH_MONITORING
4095	pPage->cModifications = 0;
4096	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
4097	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
4098	#else
4099	pPage->fCR3Mix = false;
4100	#endif
4101	#ifdef PGMPOOL_WITH_USER_TRACKING
4102	pPage->cPresent = 0;
4103	pPage->iFirstPresent = ~0;
4104
4105	/*
4106	* Insert into the tracking and cache. If this fails, free the page.
4107	*/
4108	int rc3 = pgmPoolTrackInsert(pPool, pPage, GCPhys, iUser, iUserTable);
4109	if (RT_FAILURE(rc3))
4110	{
4111	pPool->cUsedPages--;
4112	pPage->enmKind = PGMPOOLKIND_FREE;
4113	pPage->GCPhys = NIL_RTGCPHYS;
4114	pPage->iNext = pPool->iFreeHead;
4115	pPool->iFreeHead = pPage->idx;
4116	pgmUnlock(pVM);
4117	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4118	Log(("pgmPoolAlloc: returns %Rrc (Insert)\n", rc3));
4119	return rc3;
4120	}
4121	#endif /* PGMPOOL_WITH_USER_TRACKING */
4122
4123	/*
4124	* Commit the allocation, clear the page and return.
4125	*/
4126	#ifdef VBOX_WITH_STATISTICS
4127	if (pPool->cUsedPages > pPool->cUsedPagesHigh)
4128	pPool->cUsedPagesHigh = pPool->cUsedPages;
4129	#endif
4130
4131	if (!pPage->fZeroed)
4132	{
4133	STAM_PROFILE_START(&pPool->StatZeroPage, z);
4134	void *pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
4135	ASMMemZeroPage(pv);
4136	STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
4137	}
4138
4139	*ppPage = pPage;
4140	pgmUnlock(pVM);
4141	LogFlow(("pgmPoolAlloc: returns %Rrc *ppPage=%p:{.Key=%RHp, .idx=%d, .fCached=%RTbool, .fMonitored=%RTbool}\n",
4142	rc, pPage, pPage->Core.Key, pPage->idx, pPage->fCached, pPage->fMonitored));
4143	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4144	return rc;
4145	}
4146
4147
4148	/**
4149	* Frees a usage of a pool page.
4150	*
4151	* @param pVM The VM handle.
4152	* @param HCPhys The HC physical address of the shadow page.
4153	* @param iUser The shadow page pool index of the user table.
4154	* @param iUserTable The index into the user table (shadowed).
4155	*/
4156	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable)
4157	{
4158	LogFlow(("pgmPoolFree: HCPhys=%RHp iUser=%#x iUserTable=%#x\n", HCPhys, iUser, iUserTable));
4159	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4160	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, HCPhys), iUser, iUserTable);
4161	}
4162
4163	/**
4164	* Internal worker for finding a 'in-use' shadow page give by it's physical address.
4165	*
4166	* @returns Pointer to the shadow page structure.
4167	* @param pPool The pool.
4168	* @param HCPhys The HC physical address of the shadow page.
4169	*/
4170	PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
4171	{
4172	PVM pVM = pPool->CTX_SUFF(pVM);
4173
4174	/*
4175	* Look up the page.
4176	*/
4177	pgmLock(pVM);
4178	PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
4179	pgmUnlock(pVM);
4180
4181	AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%RHp pPage=%p idx=%d\n", HCPhys, pPage, (pPage) ? pPage->idx : 0));
4182	return pPage;
4183	}
4184
4185
4186	#ifdef IN_RING3
4187	/**
4188	* Flushes the entire cache.
4189	*
4190	* It will assert a global CR3 flush (FF) and assumes the caller is aware of this
4191	* and execute this CR3 flush.
4192	*
4193	* @param pPool The pool.
4194	*/
4195	void pgmR3PoolReset(PVM pVM)
4196	{
4197	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4198
4199	Assert(PGMIsLockOwner(pVM));
4200	STAM_PROFILE_START(&pPool->StatFlushAllInt, a);
4201	LogFlow(("pgmPoolFlushAllInt:\n"));
4202
4203	/*
4204	* If there are no pages in the pool, there is nothing to do.
4205	*/
4206	if (pPool->cCurPages <= PGMPOOL_IDX_FIRST)
4207	{
4208	STAM_PROFILE_STOP(&pPool->StatFlushAllInt, a);
4209	return;
4210	}
4211
4212	/*
4213	* Exit the shadow mode since we're going to clear everything,
4214	* including the root page.
4215	*/
4216	for (unsigned i=0;i<pVM->cCPUs;i++)
4217	{
4218	PVMCPU pVCpu = &pVM->aCpus[i];
4219	pgmR3ExitShadowModeBeforePoolFlush(pVM, pVCpu);
4220	}
4221
4222	/*
4223	* Nuke the free list and reinsert all pages into it.
4224	*/
4225	for (unsigned i = pPool->cCurPages - 1; i >= PGMPOOL_IDX_FIRST; i--)
4226	{
4227	PPGMPOOLPAGE pPage = &pPool->aPages[i];
4228
4229	Assert(pPage->Core.Key == MMPage2Phys(pVM, pPage->pvPageR3));
4230	#ifdef PGMPOOL_WITH_MONITORING
4231	if (pPage->fMonitored)
4232	pgmPoolMonitorFlush(pPool, pPage);
4233	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
4234	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
4235	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
4236	pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
4237	pPage->cModifications = 0;
4238	#endif
4239	pPage->GCPhys = NIL_RTGCPHYS;
4240	pPage->enmKind = PGMPOOLKIND_FREE;
4241	Assert(pPage->idx == i);
4242	pPage->iNext = i + 1;
4243	pPage->fZeroed = false; /* This could probably be optimized, but better safe than sorry. */
4244	pPage->fSeenNonGlobal = false;
4245	pPage->fMonitored= false;
4246	pPage->fCached = false;
4247	pPage->fReusedFlushPending = false;
4248	#ifdef PGMPOOL_WITH_USER_TRACKING
4249	pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
4250	#else
4251	pPage->fCR3Mix = false;
4252	#endif
4253	#ifdef PGMPOOL_WITH_CACHE
4254	pPage->iAgeNext = NIL_PGMPOOL_IDX;
4255	pPage->iAgePrev = NIL_PGMPOOL_IDX;
4256	#endif
4257	pPage->cLocked = 0;
4258	}
4259	pPool->aPages[pPool->cCurPages - 1].iNext = NIL_PGMPOOL_IDX;
4260	pPool->iFreeHead = PGMPOOL_IDX_FIRST;
4261	pPool->cUsedPages = 0;
4262
4263	#ifdef PGMPOOL_WITH_USER_TRACKING
4264	/*
4265	* Zap and reinitialize the user records.
4266	*/
4267	pPool->cPresent = 0;
4268	pPool->iUserFreeHead = 0;
4269	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
4270	const unsigned cMaxUsers = pPool->cMaxUsers;
4271	for (unsigned i = 0; i < cMaxUsers; i++)
4272	{
4273	paUsers[i].iNext = i + 1;
4274	paUsers[i].iUser = NIL_PGMPOOL_IDX;
4275	paUsers[i].iUserTable = 0xfffffffe;
4276	}
4277	paUsers[cMaxUsers - 1].iNext = NIL_PGMPOOL_USER_INDEX;
4278	#endif
4279
4280	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
4281	/*
4282	* Clear all the GCPhys links and rebuild the phys ext free list.
4283	*/
4284	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
4285	pRam;
4286	pRam = pRam->CTX_SUFF(pNext))
4287	{
4288	unsigned iPage = pRam->cb >> PAGE_SHIFT;
4289	while (iPage-- > 0)
4290	PGM_PAGE_SET_TRACKING(&pRam->aPages[iPage], 0);
4291	}
4292
4293	pPool->iPhysExtFreeHead = 0;
4294	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
4295	const unsigned cMaxPhysExts = pPool->cMaxPhysExts;
4296	for (unsigned i = 0; i < cMaxPhysExts; i++)
4297	{
4298	paPhysExts[i].iNext = i + 1;
4299	paPhysExts[i].aidx[0] = NIL_PGMPOOL_IDX;
4300	paPhysExts[i].aidx[1] = NIL_PGMPOOL_IDX;
4301	paPhysExts[i].aidx[2] = NIL_PGMPOOL_IDX;
4302	}
4303	paPhysExts[cMaxPhysExts - 1].iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
4304	#endif
4305
4306	#ifdef PGMPOOL_WITH_MONITORING
4307	/*
4308	* Just zap the modified list.
4309	*/
4310	pPool->cModifiedPages = 0;
4311	pPool->iModifiedHead = NIL_PGMPOOL_IDX;
4312	#endif
4313
4314	#ifdef PGMPOOL_WITH_CACHE
4315	/*
4316	* Clear the GCPhys hash and the age list.
4317	*/
4318	for (unsigned i = 0; i < RT_ELEMENTS(pPool->aiHash); i++)
4319	pPool->aiHash[i] = NIL_PGMPOOL_IDX;
4320	pPool->iAgeHead = NIL_PGMPOOL_IDX;
4321	pPool->iAgeTail = NIL_PGMPOOL_IDX;
4322	#endif
4323
4324	/*
4325	* Reinsert active pages into the hash and ensure monitoring chains are correct.
4326	*/
4327	for (unsigned i = PGMPOOL_IDX_FIRST_SPECIAL; i < PGMPOOL_IDX_FIRST; i++)
4328	{
4329	PPGMPOOLPAGE pPage = &pPool->aPages[i];
4330	pPage->iNext = NIL_PGMPOOL_IDX;
4331	#ifdef PGMPOOL_WITH_MONITORING
4332	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
4333	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
4334	pPage->cModifications = 0;
4335	/* ASSUMES that we're not sharing with any of the other special pages (safe for now). */
4336	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
4337	pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
4338	if (pPage->fMonitored)
4339	{
4340	int rc = PGMHandlerPhysicalChangeCallbacks(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1),
4341	pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pPage),
4342	pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pPage),
4343	pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pPage),
4344	pPool->pszAccessHandler);
4345	AssertFatalRCSuccess(rc);
4346	# ifdef PGMPOOL_WITH_CACHE
4347	pgmPoolHashInsert(pPool, pPage);
4348	# endif
4349	}
4350	#endif
4351	#ifdef PGMPOOL_WITH_USER_TRACKING
4352	Assert(pPage->iUserHead == NIL_PGMPOOL_USER_INDEX); /* for now */
4353	#endif
4354	#ifdef PGMPOOL_WITH_CACHE
4355	Assert(pPage->iAgeNext == NIL_PGMPOOL_IDX);
4356	Assert(pPage->iAgePrev == NIL_PGMPOOL_IDX);
4357	#endif
4358	}
4359
4360	for (unsigned i=0;i<pVM->cCPUs;i++)
4361	{
4362	PVMCPU pVCpu = &pVM->aCpus[i];
4363	/*
4364	* Re-enter the shadowing mode and assert Sync CR3 FF.
4365	*/
4366	pgmR3ReEnterShadowModeAfterPoolFlush(pVM, pVCpu);
4367	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4368	}
4369
4370	STAM_PROFILE_STOP(&pPool->StatFlushAllInt, a);
4371	}
4372	#endif /* IN_RING3 */
4373
4374	#ifdef LOG_ENABLED
4375	static const char *pgmPoolPoolKindToStr(uint8_t enmKind)
4376	{
4377	switch(enmKind)
4378	{
4379	case PGMPOOLKIND_INVALID:
4380	return "PGMPOOLKIND_INVALID";
4381	case PGMPOOLKIND_FREE:
4382	return "PGMPOOLKIND_FREE";
4383	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
4384	return "PGMPOOLKIND_32BIT_PT_FOR_PHYS";
4385	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
4386	return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT";
4387	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
4388	return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB";
4389	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
4390	return "PGMPOOLKIND_PAE_PT_FOR_PHYS";
4391	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
4392	return "PGMPOOLKIND_PAE_PT_FOR_32BIT_PT";
4393	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
4394	return "PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB";
4395	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
4396	return "PGMPOOLKIND_PAE_PT_FOR_PAE_PT";
4397	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
4398	return "PGMPOOLKIND_PAE_PT_FOR_PAE_2MB";
4399	case PGMPOOLKIND_32BIT_PD:
4400	return "PGMPOOLKIND_32BIT_PD";
4401	case PGMPOOLKIND_32BIT_PD_PHYS:
4402	return "PGMPOOLKIND_32BIT_PD_PHYS";
4403	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
4404	return "PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD";
4405	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
4406	return "PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD";
4407	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
4408	return "PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD";
4409	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
4410	return "PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD";
4411	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
4412	return "PGMPOOLKIND_PAE_PD_FOR_PAE_PD";
4413	case PGMPOOLKIND_PAE_PD_PHYS:
4414	return "PGMPOOLKIND_PAE_PD_PHYS";
4415	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
4416	return "PGMPOOLKIND_PAE_PDPT_FOR_32BIT";
4417	case PGMPOOLKIND_PAE_PDPT:
4418	return "PGMPOOLKIND_PAE_PDPT";
4419	case PGMPOOLKIND_PAE_PDPT_PHYS:
4420	return "PGMPOOLKIND_PAE_PDPT_PHYS";
4421	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
4422	return "PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT";
4423	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
4424	return "PGMPOOLKIND_64BIT_PDPT_FOR_PHYS";
4425	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
4426	return "PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD";
4427	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
4428	return "PGMPOOLKIND_64BIT_PD_FOR_PHYS";
4429	case PGMPOOLKIND_64BIT_PML4:
4430	return "PGMPOOLKIND_64BIT_PML4";
4431	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
4432	return "PGMPOOLKIND_EPT_PDPT_FOR_PHYS";
4433	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
4434	return "PGMPOOLKIND_EPT_PD_FOR_PHYS";
4435	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
4436	return "PGMPOOLKIND_EPT_PT_FOR_PHYS";
4437	case PGMPOOLKIND_ROOT_NESTED:
4438	return "PGMPOOLKIND_ROOT_NESTED";
4439	}
4440	return "Unknown kind!";
4441	}
4442	#endif /* LOG_ENABLED*/

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp@ 20008

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