PGMAllBth.h@ 20125

最後變更在這個檔案從20125是 20125,由 vboxsync 提交於 16 年前
Prevent reuse of cached large pages with different access attributes.
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1	/* $Id: PGMAllBth.h 20125 2009-05-28 15:44:30Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* This file is a big challenge!
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.alldomusa.eu.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*
19	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
20	* Clara, CA 95054 USA or visit http://www.sun.com if you need
21	* additional information or have any questions.
22	*/
23
24	/*******************************************************************************
25	* Internal Functions *
26	*******************************************************************************/
27	__BEGIN_DECLS
28	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
29	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
30	PGM_BTH_DECL(int, SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
31	PGM_BTH_DECL(int, CheckPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage);
32	PGM_BTH_DECL(int, SyncPT)(PVMCPU pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
33	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
34	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
35	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
36	#ifdef VBOX_STRICT
37	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
38	#endif
39	#ifdef PGMPOOL_WITH_USER_TRACKING
40	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
41	#endif
42	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
43	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu);
44	__END_DECLS
45
46
47	/* Filter out some illegal combinations of guest and shadow paging, so we can remove redundant checks inside functions. */
48	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
49	# error "Invalid combination; PAE guest implies PAE shadow"
50	#endif
51
52	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
53	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
54	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
55	#endif
56
57	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
58	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
59	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
60	#endif
61
62	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
63	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
64	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
65	#endif
66
67	#ifdef IN_RING0 /* no mappings in VT-x and AMD-V mode */
68	# define PGM_WITHOUT_MAPPINGS
69	#endif
70
71
72	#ifndef IN_RING3
73	/**
74	* #PF Handler for raw-mode guest execution.
75	*
76	* @returns VBox status code (appropriate for trap handling and GC return).
77	*
78	* @param pVCpu VMCPU Handle.
79	* @param uErr The trap error code.
80	* @param pRegFrame Trap register frame.
81	* @param pvFault The fault address.
82	*/
83	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
84	{
85	PVM pVM = pVCpu->CTX_SUFF(pVM);
86
87	# if defined(IN_RC) && defined(VBOX_STRICT)
88	PGMDynCheckLocks(pVM);
89	# endif
90
91	# if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
92	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
93	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
94
95	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_PAE
96	/*
97	* Hide the instruction fetch trap indicator for now.
98	*/
99	/** @todo NXE will change this and we must fix NXE in the switcher too! */
100	if (uErr & X86_TRAP_PF_ID)
101	{
102	uErr &= ~X86_TRAP_PF_ID;
103	TRPMSetErrorCode(pVCpu, uErr);
104	}
105	# endif
106
107	/*
108	* Get PDs.
109	*/
110	int rc;
111	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
112	# if PGM_GST_TYPE == PGM_TYPE_32BIT
113	const unsigned iPDSrc = pvFault >> GST_PD_SHIFT;
114	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
115
116	# elif PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
117
118	# if PGM_GST_TYPE == PGM_TYPE_PAE
119	unsigned iPDSrc;
120	X86PDPE PdpeSrc;
121	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, pvFault, &iPDSrc, &PdpeSrc);
122
123	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
124	unsigned iPDSrc;
125	PX86PML4E pPml4eSrc;
126	X86PDPE PdpeSrc;
127	PGSTPD pPDSrc;
128
129	pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, pvFault, &pPml4eSrc, &PdpeSrc, &iPDSrc);
130	Assert(pPml4eSrc);
131	# endif
132
133	/* Quick check for a valid guest trap. (PAE & AMD64) */
134	if (!pPDSrc)
135	{
136	# if PGM_GST_TYPE == PGM_TYPE_AMD64 && GC_ARCH_BITS == 64
137	LogFlow(("Trap0eHandler: guest PML4 %d not present CR3=%RGp\n", (int)((pvFault >> X86_PML4_SHIFT) & X86_PML4_MASK), CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK));
138	# else
139	LogFlow(("Trap0eHandler: guest iPDSrc=%u not present CR3=%RGp\n", iPDSrc, CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK));
140	# endif
141	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2GuestTrap; });
142	TRPMSetErrorCode(pVCpu, uErr);
143	return VINF_EM_RAW_GUEST_TRAP;
144	}
145	# endif
146
147	# else /* !PGM_WITH_PAGING */
148	PGSTPD pPDSrc = NULL;
149	const unsigned iPDSrc = 0;
150	# endif /* !PGM_WITH_PAGING */
151
152	/* Fetch the guest PDE */
153	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
154	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
155	# else
156	GSTPDE PdeSrc;
157	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
158	PdeSrc.n.u1Present = 1;
159	PdeSrc.n.u1Write = 1;
160	PdeSrc.n.u1Accessed = 1;
161	PdeSrc.n.u1User = 1;
162	# endif
163
164	pgmLock(pVM);
165	{ /* Force the shadow pointers to go out of scope after releasing the lock. */
166	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
167	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
168	PX86PD pPDDst = pgmShwGet32BitPDPtr(&pVCpu->pgm.s);
169
170	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
171	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
172
173	PX86PDPAE pPDDst;
174	# if PGM_GST_TYPE != PGM_TYPE_PAE
175	X86PDPE PdpeSrc;
176
177	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
178	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
179	# endif
180	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, &PdpeSrc, &pPDDst);
181	if (rc != VINF_SUCCESS)
182	{
183	pgmUnlock(pVM);
184	AssertRC(rc);
185	return rc;
186	}
187	Assert(pPDDst);
188
189	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
190	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
191	PX86PDPAE pPDDst;
192	# if PGM_GST_TYPE == PGM_TYPE_PROT
193	/* AMD-V nested paging */
194	X86PML4E Pml4eSrc;
195	X86PDPE PdpeSrc;
196	PX86PML4E pPml4eSrc = &Pml4eSrc;
197
198	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
199	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
200	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
201	# endif
202
203	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, pPml4eSrc, &PdpeSrc, &pPDDst);
204	if (rc != VINF_SUCCESS)
205	{
206	pgmUnlock(pVM);
207	AssertRC(rc);
208	return rc;
209	}
210	Assert(pPDDst);
211
212	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
213	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
214	PEPTPD pPDDst;
215
216	rc = pgmShwGetEPTPDPtr(pVCpu, pvFault, NULL, &pPDDst);
217	if (rc != VINF_SUCCESS)
218	{
219	pgmUnlock(pVM);
220	AssertRC(rc);
221	return rc;
222	}
223	Assert(pPDDst);
224	# endif
225
226	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
227	/*
228	* If we successfully correct the write protection fault due to dirty bit
229	* tracking, or this page fault is a genuine one, then return immediately.
230	*/
231	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
232	rc = PGM_BTH_NAME(CheckPageFault)(pVCpu, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], pvFault);
233	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
234	if ( rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
235	\|\| rc == VINF_EM_RAW_GUEST_TRAP)
236	{
237	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
238	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVCpu->pgm.s.StatRZTrap0eTime2DirtyAndAccessed : &pVCpu->pgm.s.StatRZTrap0eTime2GuestTrap; });
239	LogBird(("Trap0eHandler: returns %s\n", rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? "VINF_SUCCESS" : "VINF_EM_RAW_GUEST_TRAP"));
240	pgmUnlock(pVM);
241	return rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? VINF_SUCCESS : rc;
242	}
243
244	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
245	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
246
247	/*
248	* A common case is the not-present error caused by lazy page table syncing.
249	*
250	* It is IMPORTANT that we weed out any access to non-present shadow PDEs here
251	* so we can safely assume that the shadow PT is present when calling SyncPage later.
252	*
253	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
254	* of mapping conflict and defer to SyncCR3 in R3.
255	* (Again, we do NOT support access handlers for non-present guest pages.)
256	*
257	*/
258	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
259	&& !pPDDst->a[iPDDst].n.u1Present
260	&& PdeSrc.n.u1Present
261	)
262	{
263	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2SyncPT; });
264	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeSyncPT, f);
265	LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
266	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, pvFault);
267	pgmUnlock(pVM);
268	if (RT_SUCCESS(rc))
269	{
270	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeSyncPT, f);
271	return rc;
272	}
273	Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
274	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
275	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeSyncPT, f);
276	return VINF_PGM_SYNC_CR3;
277	}
278	pgmUnlock(pVM);
279	}
280
281	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
282	/*
283	* Check if this address is within any of our mappings.
284	*
285	* This is very fast and it's gonna save us a bit of effort below and prevent
286	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
287	* (BTW, it's impossible to have physical access handlers in a mapping.)
288	*/
289	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
290	{
291	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
292	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
293	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
294	{
295	if (pvFault < pMapping->GCPtr)
296	break;
297	if (pvFault - pMapping->GCPtr < pMapping->cb)
298	{
299	/*
300	* The first thing we check is if we've got an undetected conflict.
301	*/
302	if (!pVM->pgm.s.fMappingsFixed)
303	{
304	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
305	while (iPT-- > 0)
306	if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
307	{
308	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eConflicts);
309	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
310	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
311	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
312	return VINF_PGM_SYNC_CR3;
313	}
314	}
315
316	/*
317	* Check if the fault address is in a virtual page access handler range.
318	*/
319	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
320	if ( pCur
321	&& pvFault - pCur->Core.Key < pCur->cb
322	&& uErr & X86_TRAP_PF_RW)
323	{
324	# ifdef IN_RC
325	STAM_PROFILE_START(&pCur->Stat, h);
326	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
327	STAM_PROFILE_STOP(&pCur->Stat, h);
328	# else
329	AssertFailed();
330	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
331	# endif
332	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersMapping);
333	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
334	return rc;
335	}
336
337	/*
338	* Pretend we're not here and let the guest handle the trap.
339	*/
340	TRPMSetErrorCode(pVCpu, uErr & ~X86_TRAP_PF_P);
341	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eGuestPFMapping);
342	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
343	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
344	return VINF_EM_RAW_GUEST_TRAP;
345	}
346	}
347	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
348	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
349	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
350
351	/*
352	* Check if this fault address is flagged for special treatment,
353	* which means we'll have to figure out the physical address and
354	* check flags associated with it.
355	*
356	* ASSUME that we can limit any special access handling to pages
357	* in page tables which the guest believes to be present.
358	*/
359	if (PdeSrc.n.u1Present)
360	{
361	RTGCPHYS GCPhys = NIL_RTGCPHYS;
362
363	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
364	# if PGM_GST_TYPE == PGM_TYPE_AMD64
365	bool fBigPagesSupported = true;
366	# else
367	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
368	# endif
369	if ( PdeSrc.b.u1Size
370	&& fBigPagesSupported)
371	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc)
372	\| ((RTGCPHYS)pvFault & (GST_BIG_PAGE_OFFSET_MASK ^ PAGE_OFFSET_MASK));
373	else
374	{
375	PGSTPT pPTSrc;
376	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
377	if (RT_SUCCESS(rc))
378	{
379	unsigned iPTESrc = (pvFault >> GST_PT_SHIFT) & GST_PT_MASK;
380	if (pPTSrc->a[iPTESrc].n.u1Present)
381	GCPhys = pPTSrc->a[iPTESrc].u & GST_PTE_PG_MASK;
382	}
383	}
384	# else
385	/* No paging so the fault address is the physical address */
386	GCPhys = (RTGCPHYS)(pvFault & ~PAGE_OFFSET_MASK);
387	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
388
389	/*
390	* If we have a GC address we'll check if it has any flags set.
391	*/
392	if (GCPhys != NIL_RTGCPHYS)
393	{
394	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
395
396	PPGMPAGE pPage;
397	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
398	if (RT_SUCCESS(rc)) /** just handle the failure immediate (it returns) and make things easier to read. */
399	{
400	if ( PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage)
401	\|\| PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage))
402	{
403	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
404	{
405	/*
406	* Physical page access handler.
407	*/
408	const RTGCPHYS GCPhysFault = GCPhys \| (pvFault & PAGE_OFFSET_MASK);
409	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhysFault);
410	if (pCur)
411	{
412	# ifdef PGM_SYNC_N_PAGES
413	/*
414	* If the region is write protected and we got a page not present fault, then sync
415	* the pages. If the fault was caused by a read, then restart the instruction.
416	* In case of write access continue to the GC write handler.
417	*
418	* ASSUMES that there is only one handler per page or that they have similar write properties.
419	*/
420	if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
421	&& !(uErr & X86_TRAP_PF_P))
422	{
423	pgmLock(pVM);
424	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
425	pgmUnlock(pVM);
426	if ( RT_FAILURE(rc)
427	\|\| !(uErr & X86_TRAP_PF_RW)
428	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
429	{
430	AssertRC(rc);
431	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersOutOfSync);
432	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
433	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
434	return rc;
435	}
436	}
437	# endif
438
439	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
440	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
441	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
442
443	# if defined(IN_RC) \|\| defined(IN_RING0)
444	if (pCur->CTX_SUFF(pfnHandler))
445	{
446	STAM_PROFILE_START(&pCur->Stat, h);
447	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pCur->CTX_SUFF(pvUser));
448	STAM_PROFILE_STOP(&pCur->Stat, h);
449	}
450	else
451	# endif
452	rc = VINF_EM_RAW_EMULATE_INSTR;
453	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersPhysical);
454	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
455	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndPhys; });
456	return rc;
457	}
458	}
459	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
460	else
461	{
462	# ifdef PGM_SYNC_N_PAGES
463	/*
464	* If the region is write protected and we got a page not present fault, then sync
465	* the pages. If the fault was caused by a read, then restart the instruction.
466	* In case of write access continue to the GC write handler.
467	*/
468	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
469	&& !(uErr & X86_TRAP_PF_P))
470	{
471	pgmLock(pVM);
472	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
473	pgmUnlock(pVM);
474	if ( RT_FAILURE(rc)
475	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
476	\|\| !(uErr & X86_TRAP_PF_RW))
477	{
478	AssertRC(rc);
479	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersOutOfSync);
480	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
481	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndVirt; });
482	return rc;
483	}
484	}
485	# endif
486	/*
487	* Ok, it's an virtual page access handler.
488	*
489	* Since it's faster to search by address, we'll do that first
490	* and then retry by GCPhys if that fails.
491	*/
492	/** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
493	/** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
494	* page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
495	*/
496	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
497	if (pCur)
498	{
499	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
500	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
501	\|\| !(uErr & X86_TRAP_PF_P)
502	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
503	("Unexpected trap for virtual handler: %RGv (phys=%RGp) pPage=%R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
504
505	if ( pvFault - pCur->Core.Key < pCur->cb
506	&& ( uErr & X86_TRAP_PF_RW
507	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
508	{
509	# ifdef IN_RC
510	STAM_PROFILE_START(&pCur->Stat, h);
511	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
512	STAM_PROFILE_STOP(&pCur->Stat, h);
513	# else
514	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
515	# endif
516	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersVirtual);
517	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
518	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndVirt; });
519	return rc;
520	}
521	/* Unhandled part of a monitored page */
522	}
523	else
524	{
525	/* Check by physical address. */
526	PPGMVIRTHANDLER pCur;
527	unsigned iPage;
528	rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + (pvFault & PAGE_OFFSET_MASK),
529	&pCur, &iPage);
530	Assert(RT_SUCCESS(rc) \|\| !pCur);
531	if ( pCur
532	&& ( uErr & X86_TRAP_PF_RW
533	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
534	{
535	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
536	# ifdef IN_RC
537	RTGCPTR off = (iPage << PAGE_SHIFT) + (pvFault & PAGE_OFFSET_MASK) - (pCur->Core.Key & PAGE_OFFSET_MASK);
538	Assert(off < pCur->cb);
539	STAM_PROFILE_START(&pCur->Stat, h);
540	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, off);
541	STAM_PROFILE_STOP(&pCur->Stat, h);
542	# else
543	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
544	# endif
545	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersVirtualByPhys);
546	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
547	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndVirt; });
548	return rc;
549	}
550	}
551	}
552	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
553
554	/*
555	* There is a handled area of the page, but this fault doesn't belong to it.
556	* We must emulate the instruction.
557	*
558	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
559	* we first check if this was a page-not-present fault for a page with only
560	* write access handlers. Restart the instruction if it wasn't a write access.
561	*/
562	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersUnhandled);
563
564	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
565	&& !(uErr & X86_TRAP_PF_P))
566	{
567	pgmLock(pVM);
568	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
569	pgmUnlock(pVM);
570	if ( RT_FAILURE(rc)
571	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
572	\|\| !(uErr & X86_TRAP_PF_RW))
573	{
574	AssertRC(rc);
575	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersOutOfSync);
576	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
577	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
578	return rc;
579	}
580	}
581
582	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
583	* It's writing to an unhandled part of the LDT page several million times.
584	*/
585	rc = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);
586	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
587	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
588	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndUnhandled; });
589	return rc;
590	} /* if any kind of handler */
591
592	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
593	if (uErr & X86_TRAP_PF_P)
594	{
595	/*
596	* The page isn't marked, but it might still be monitored by a virtual page access handler.
597	* (ASSUMES no temporary disabling of virtual handlers.)
598	*/
599	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
600	* we should correct both the shadow page table and physical memory flags, and not only check for
601	* accesses within the handler region but for access to pages with virtual handlers. */
602	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
603	if (pCur)
604	{
605	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
606	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
607	\|\| !(uErr & X86_TRAP_PF_P)
608	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
609	("Unexpected trap for virtual handler: %08X (phys=%08x) %R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
610
611	if ( pvFault - pCur->Core.Key < pCur->cb
612	&& ( uErr & X86_TRAP_PF_RW
613	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
614	{
615	# ifdef IN_RC
616	STAM_PROFILE_START(&pCur->Stat, h);
617	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
618	STAM_PROFILE_STOP(&pCur->Stat, h);
619	# else
620	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
621	# endif
622	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersVirtualUnmarked);
623	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
624	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndVirt; });
625	return rc;
626	}
627	}
628	}
629	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
630	}
631	else
632	{
633	/*
634	* When the guest accesses invalid physical memory (e.g. probing
635	* of RAM or accessing a remapped MMIO range), then we'll fall
636	* back to the recompiler to emulate the instruction.
637	*/
638	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
639	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersInvalid);
640	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
641	return VINF_EM_RAW_EMULATE_INSTR;
642	}
643
644	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
645
646	# ifdef PGM_OUT_OF_SYNC_IN_GC /** @todo remove this bugger. */
647	/*
648	* We are here only if page is present in Guest page tables and
649	* trap is not handled by our handlers.
650	*
651	* Check it for page out-of-sync situation.
652	*/
653	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
654
655	if (!(uErr & X86_TRAP_PF_P))
656	{
657	/*
658	* Page is not present in our page tables.
659	* Try to sync it!
660	* BTW, fPageShw is invalid in this branch!
661	*/
662	if (uErr & X86_TRAP_PF_US)
663	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
664	else /* supervisor */
665	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
666
667	# if defined(LOG_ENABLED) && !defined(IN_RING0)
668	RTGCPHYS GCPhys;
669	uint64_t fPageGst;
670	PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys);
671	Log(("Page out of sync: %RGv eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%RGp scan=%d\n",
672	pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst, GCPhys, CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)));
673	# endif /* LOG_ENABLED */
674
675	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
676	if (CPUMGetGuestCPL(pVCpu, pRegFrame) == 0)
677	{
678	uint64_t fPageGst;
679	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
680	if ( RT_SUCCESS(rc)
681	&& !(fPageGst & X86_PTE_US))
682	{
683	/* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
684	if ( pvFault == (RTGCPTR)pRegFrame->eip
685	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
686	# ifdef CSAM_DETECT_NEW_CODE_PAGES
687	\|\| ( !PATMIsPatchGCAddr(pVM, (RTGCPTR)pRegFrame->eip)
688	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)) /* any new code we encounter here */
689	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
690	)
691	{
692	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
693	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
694	if (rc != VINF_SUCCESS)
695	{
696	/*
697	* CSAM needs to perform a job in ring 3.
698	*
699	* Sync the page before going to the host context; otherwise we'll end up in a loop if
700	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
701	*/
702	LogFlow(("CSAM ring 3 job\n"));
703	pgmLock(pVM);
704	int rc2 = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, 1, uErr);
705	pgmUnlock(pVM);
706	AssertRC(rc2);
707
708	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
709	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2CSAM; });
710	return rc;
711	}
712	}
713	# ifdef CSAM_DETECT_NEW_CODE_PAGES
714	else if ( uErr == X86_TRAP_PF_RW
715	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
716	&& pRegFrame->ecx < 0x10000)
717	{
718	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
719	* to detect loading of new code pages.
720	*/
721
722	/*
723	* Decode the instruction.
724	*/
725	RTGCPTR PC;
726	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
727	if (rc == VINF_SUCCESS)
728	{
729	DISCPUSTATE Cpu;
730	uint32_t cbOp;
731	rc = EMInterpretDisasOneEx(pVM, pVCpu, PC, pRegFrame, &Cpu, &cbOp);
732
733	/* For now we'll restrict this to rep movsw/d instructions */
734	if ( rc == VINF_SUCCESS
735	&& Cpu.pCurInstr->opcode == OP_MOVSWD
736	&& (Cpu.prefix & PREFIX_REP))
737	{
738	CSAMMarkPossibleCodePage(pVM, pvFault);
739	}
740	}
741	}
742	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
743
744	/*
745	* Mark this page as safe.
746	*/
747	/** @todo not correct for pages that contain both code and data!! */
748	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
749	CSAMMarkPage(pVM, (RTRCPTR)pvFault, true);
750	}
751	}
752	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
753	pgmLock(pVM);
754	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
755	pgmUnlock(pVM);
756	if (RT_SUCCESS(rc))
757	{
758	/* The page was successfully synced, return to the guest. */
759	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
760	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSync; });
761	return VINF_SUCCESS;
762	}
763	}
764	else /* uErr & X86_TRAP_PF_P: */
765	{
766	/*
767	* Write protected pages are make writable when the guest makes the first
768	* write to it. This happens for pages that are shared, write monitored
769	* and not yet allocated.
770	*
771	* Also, a side effect of not flushing global PDEs are out of sync pages due
772	* to physical monitored regions, that are no longer valid.
773	* Assume for now it only applies to the read/write flag.
774	*/
775	if (RT_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
776	{
777	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
778	{
779	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n",
780	GCPhys, pPage, pvFault, uErr));
781	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
782	if (rc != VINF_SUCCESS)
783	{
784	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
785	return rc;
786	}
787	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
788	return VINF_EM_NO_MEMORY;
789	}
790	/// @todo count the above case; else
791	if (uErr & X86_TRAP_PF_US)
792	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
793	else /* supervisor */
794	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
795
796	/*
797	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
798	* page is not present, which is not true in this case.
799	*/
800	pgmLock(pVM);
801	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, 1, uErr);
802	# ifndef VBOX_STRICT
803	/* Keep it locked in VBOX_STRICT mode so the next checks won't trigger without reason with guest SMP. */
804	pgmUnlock(pVM);
805	# endif
806	if (RT_SUCCESS(rc))
807	{
808	/*
809	* Page was successfully synced, return to guest.
810	*/
811	# ifdef VBOX_STRICT
812	RTGCPHYS GCPhys;
813	uint64_t fPageGst;
814	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys);
815	Assert(RT_SUCCESS(rc) && fPageGst & X86_PTE_RW);
816	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst));
817
818	uint64_t fPageShw;
819	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
820	AssertMsg((RT_SUCCESS(rc) && ((fPageShw & X86_PTE_RW) \|\| pVM->cCPUs > 1 /* new monitor can be installed during trap e execution */)), ("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw));
821	pgmUnlock(pVM);
822	# endif /* VBOX_STRICT */
823	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
824	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndObs; });
825	return VINF_SUCCESS;
826	}
827	# ifdef VBOX_STRICT
828	pgmUnlock(pVM);
829	# endif
830
831	/* Check to see if we need to emulate the instruction as X86_CR0_WP has been cleared. */
832	if ( CPUMGetGuestCPL(pVCpu, pRegFrame) == 0
833	&& ((CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG)
834	&& (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P))
835	{
836	uint64_t fPageGst;
837	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
838	if ( RT_SUCCESS(rc)
839	&& !(fPageGst & X86_PTE_RW))
840	{
841	rc = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);
842	if (RT_SUCCESS(rc))
843	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eWPEmulInRZ);
844	else
845	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eWPEmulToR3);
846	return rc;
847	}
848	AssertMsgFailed(("Unexpected r/w page %RGv flag=%x rc=%Rrc\n", pvFault, (uint32_t)fPageGst, rc));
849	}
850	}
851
852	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
853	# ifdef VBOX_STRICT
854	/*
855	* Check for VMM page flags vs. Guest page flags consistency.
856	* Currently only for debug purposes.
857	*/
858	if (RT_SUCCESS(rc))
859	{
860	/* Get guest page flags. */
861	uint64_t fPageGst;
862	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
863	if (RT_SUCCESS(rc))
864	{
865	uint64_t fPageShw;
866	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
867
868	/*
869	* Compare page flags.
870	* Note: we have AVL, A, D bits desynched.
871	*/
872	AssertMsg((fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
873	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64\n", pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst));
874	}
875	else
876	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
877	}
878	else
879	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
880	# endif /* VBOX_STRICT */
881	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
882	}
883	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
884	# endif /* PGM_OUT_OF_SYNC_IN_GC */
885	}
886	else /* GCPhys == NIL_RTGCPHYS */
887	{
888	/*
889	* Page not present in Guest OS or invalid page table address.
890	* This is potential virtual page access handler food.
891	*
892	* For the present we'll say that our access handlers don't
893	* work for this case - we've already discarded the page table
894	* not present case which is identical to this.
895	*
896	* When we perchance find we need this, we will probably have AVL
897	* trees (offset based) to operate on and we can measure their speed
898	* agains mapping a page table and probably rearrange this handling
899	* a bit. (Like, searching virtual ranges before checking the
900	* physical address.)
901	*/
902	}
903	}
904	/* else: !present (guest) */
905
906
907	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
908	/*
909	* Conclusion, this is a guest trap.
910	*/
911	LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
912	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eGuestPFUnh);
913	return VINF_EM_RAW_GUEST_TRAP;
914	# else
915	/* present, but not a monitored page; perhaps the guest is probing physical memory */
916	return VINF_EM_RAW_EMULATE_INSTR;
917	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
918
919
920	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
921
922	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
923	return VERR_INTERNAL_ERROR;
924	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
925	}
926	#endif /* !IN_RING3 */
927
928
929	/**
930	* Emulation of the invlpg instruction.
931	*
932	*
933	* @returns VBox status code.
934	*
935	* @param pVCpu The VMCPU handle.
936	* @param GCPtrPage Page to invalidate.
937	*
938	* @remark ASSUMES that the guest is updating before invalidating. This order
939	* isn't required by the CPU, so this is speculative and could cause
940	* trouble.
941	* @remark No TLB shootdown is done on any other VCPU as we assume that
942	* invlpg emulation is the only reason for calling this function.
943	* (The guest has to shoot down TLB entries on other CPUs itself)
944	* Currently true, but keep in mind!
945	*
946	* @todo Flush page or page directory only if necessary!
947	* @todo Add a #define for simply invalidating the page.
948	*/
949	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
950	{
951	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
952	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
953	&& PGM_SHW_TYPE != PGM_TYPE_EPT
954	int rc;
955	PVM pVM = pVCpu->CTX_SUFF(pVM);
956	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
957
958	Assert(PGMIsLockOwner(pVM));
959
960	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
961	/*
962	* Get the shadow PD entry and skip out if this PD isn't present.
963	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
964	*/
965	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
966	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
967	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
968
969	/* Fetch the pgm pool shadow descriptor. */
970	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
971	Assert(pShwPde);
972
973	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
974	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
975	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVCpu->pgm.s);
976
977	/* If the shadow PDPE isn't present, then skip the invalidate. */
978	if (!pPdptDst->a[iPdpt].n.u1Present)
979	{
980	Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
981	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
982	return VINF_SUCCESS;
983	}
984
985	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
986	PPGMPOOLPAGE pShwPde = NULL;
987	PX86PDPAE pPDDst;
988
989	/* Fetch the pgm pool shadow descriptor. */
990	rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
991	AssertRCSuccessReturn(rc, rc);
992	Assert(pShwPde);
993
994	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
995	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
996
997	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
998	/* PML4 */
999	const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
1000	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1001	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1002	PX86PDPAE pPDDst;
1003	PX86PDPT pPdptDst;
1004	PX86PML4E pPml4eDst;
1005	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
1006	if (rc != VINF_SUCCESS)
1007	{
1008	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
1009	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1010	if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
1011	PGM_INVL_VCPU_TLBS(pVCpu);
1012	return VINF_SUCCESS;
1013	}
1014	Assert(pPDDst);
1015
1016	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1017	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
1018
1019	if (!pPdpeDst->n.u1Present)
1020	{
1021	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1022	if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
1023	PGM_INVL_VCPU_TLBS(pVCpu);
1024	return VINF_SUCCESS;
1025	}
1026
1027	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1028
1029	const SHWPDE PdeDst = *pPdeDst;
1030	if (!PdeDst.n.u1Present)
1031	{
1032	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1033	return VINF_SUCCESS;
1034	}
1035
1036	# if defined(IN_RC)
1037	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1038	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
1039	# endif
1040
1041	/*
1042	* Get the guest PD entry and calc big page.
1043	*/
1044	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1045	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
1046	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
1047	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1048	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1049	unsigned iPDSrc = 0;
1050	# if PGM_GST_TYPE == PGM_TYPE_PAE
1051	X86PDPE PdpeSrc;
1052	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
1053	# else /* AMD64 */
1054	PX86PML4E pPml4eSrc;
1055	X86PDPE PdpeSrc;
1056	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
1057	# endif
1058	GSTPDE PdeSrc;
1059
1060	if (pPDSrc)
1061	PdeSrc = pPDSrc->a[iPDSrc];
1062	else
1063	PdeSrc.u = 0;
1064	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1065
1066	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1067	const bool fIsBigPage = PdeSrc.b.u1Size;
1068	# else
1069	const bool fIsBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
1070	# endif
1071
1072	# ifdef IN_RING3
1073	/*
1074	* If a CR3 Sync is pending we may ignore the invalidate page operation
1075	* depending on the kind of sync and if it's a global page or not.
1076	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1077	*/
1078	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1079	if ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1080	\|\| ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1081	&& fIsBigPage
1082	&& PdeSrc.b.u1Global
1083	)
1084	)
1085	# else
1086	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1087	# endif
1088	{
1089	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1090	return VINF_SUCCESS;
1091	}
1092	# endif /* IN_RING3 */
1093
1094	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1095	/* Fetch the pgm pool shadow descriptor. */
1096	PPGMPOOLPAGE pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
1097	Assert(pShwPdpt);
1098
1099	/* Fetch the pgm pool shadow descriptor. */
1100	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1101	Assert(pShwPde);
1102
1103	Assert(pPml4eDst->n.u1Present && (pPml4eDst->u & SHW_PDPT_MASK));
1104	RTGCPHYS GCPhysPdpt = pPml4eSrc->u & X86_PML4E_PG_MASK;
1105
1106	if ( !pPml4eSrc->n.u1Present
1107	\|\| pShwPdpt->GCPhys != GCPhysPdpt)
1108	{
1109	LogFlow(("InvalidatePage: Out-of-sync PML4E (P/GCPhys) at %RGv GCPhys=%RGp vs %RGp Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1110	GCPtrPage, pShwPdpt->GCPhys, GCPhysPdpt, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1111	pgmPoolFreeByPage(pPool, pShwPdpt, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1112	ASMAtomicWriteSize(pPml4eDst, 0);
1113	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1114	PGM_INVL_VCPU_TLBS(pVCpu);
1115	return VINF_SUCCESS;
1116	}
1117	if ( pPml4eSrc->n.u1User != pPml4eDst->n.u1User
1118	\|\| (!pPml4eSrc->n.u1Write && pPml4eDst->n.u1Write))
1119	{
1120	/*
1121	* Mark not present so we can resync the PML4E when it's used.
1122	*/
1123	LogFlow(("InvalidatePage: Out-of-sync PML4E at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1124	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1125	pgmPoolFreeByPage(pPool, pShwPdpt, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1126	ASMAtomicWriteSize(pPml4eDst, 0);
1127	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1128	PGM_INVL_VCPU_TLBS(pVCpu);
1129	}
1130	else if (!pPml4eSrc->n.u1Accessed)
1131	{
1132	/*
1133	* Mark not present so we can set the accessed bit.
1134	*/
1135	LogFlow(("InvalidatePage: Out-of-sync PML4E (A) at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1136	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1137	pgmPoolFreeByPage(pPool, pShwPdpt, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1138	ASMAtomicWriteSize(pPml4eDst, 0);
1139	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1140	PGM_INVL_VCPU_TLBS(pVCpu);
1141	}
1142
1143	/* Check if the PDPT entry has changed. */
1144	Assert(pPdpeDst->n.u1Present && pPdpeDst->u & SHW_PDPT_MASK);
1145	RTGCPHYS GCPhysPd = PdpeSrc.u & GST_PDPE_PG_MASK;
1146	if ( !PdpeSrc.n.u1Present
1147	\|\| pShwPde->GCPhys != GCPhysPd)
1148	{
1149	LogFlow(("InvalidatePage: Out-of-sync PDPE (P/GCPhys) at %RGv GCPhys=%RGp vs %RGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
1150	GCPtrPage, pShwPde->GCPhys, GCPhysPd, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1151	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1152	ASMAtomicWriteSize(pPdpeDst, 0);
1153	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1154	PGM_INVL_VCPU_TLBS(pVCpu);
1155	return VINF_SUCCESS;
1156	}
1157	if ( PdpeSrc.lm.u1User != pPdpeDst->lm.u1User
1158	\|\| (!PdpeSrc.lm.u1Write && pPdpeDst->lm.u1Write))
1159	{
1160	/*
1161	* Mark not present so we can resync the PDPTE when it's used.
1162	*/
1163	LogFlow(("InvalidatePage: Out-of-sync PDPE at %RGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1164	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1165	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1166	ASMAtomicWriteSize(pPdpeDst, 0);
1167	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1168	PGM_INVL_VCPU_TLBS(pVCpu);
1169	}
1170	else if (!PdpeSrc.lm.u1Accessed)
1171	{
1172	/*
1173	* Mark not present so we can set the accessed bit.
1174	*/
1175	LogFlow(("InvalidatePage: Out-of-sync PDPE (A) at %RGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1176	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1177	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1178	ASMAtomicWriteSize(pPdpeDst, 0);
1179	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1180	PGM_INVL_VCPU_TLBS(pVCpu);
1181	}
1182	# endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
1183
1184	/*
1185	* Deal with the Guest PDE.
1186	*/
1187	rc = VINF_SUCCESS;
1188	if (PdeSrc.n.u1Present)
1189	{
1190	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1191	{
1192	/*
1193	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1194	*/
1195	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1196	Assert(PGMGetGuestMode(pVCpu) <= PGMMODE_PAE);
1197	pgmLock(pVM);
1198	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
1199	pgmUnlock(pVM);
1200	}
1201	else if ( PdeSrc.n.u1User != PdeDst.n.u1User
1202	\|\| (!PdeSrc.n.u1Write && PdeDst.n.u1Write))
1203	{
1204	/*
1205	* Mark not present so we can resync the PDE when it's used.
1206	*/
1207	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1208	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1209	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1210	ASMAtomicWriteSize(pPdeDst, 0);
1211	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1212	PGM_INVL_VCPU_TLBS(pVCpu);
1213	}
1214	else if (!PdeSrc.n.u1Accessed)
1215	{
1216	/*
1217	* Mark not present so we can set the accessed bit.
1218	*/
1219	LogFlow(("InvalidatePage: Out-of-sync (A) at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1220	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1221	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1222	ASMAtomicWriteSize(pPdeDst, 0);
1223	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1224	PGM_INVL_VCPU_TLBS(pVCpu);
1225	}
1226	else if (!fIsBigPage)
1227	{
1228	/*
1229	* 4KB - page.
1230	*/
1231	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1232	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1233	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1234	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1235	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1236	# endif
1237	if (pShwPage->GCPhys == GCPhys)
1238	{
1239	# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
1240	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1241	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1242	if (pPT->a[iPTEDst].n.u1Present)
1243	{
1244	# ifdef PGMPOOL_WITH_USER_TRACKING
1245	/* This is very unlikely with caching/monitoring enabled. */
1246	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
1247	# endif
1248	ASMAtomicWriteSize(&pPT->a[iPTEDst], 0);
1249	}
1250	# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1251	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
1252	if (RT_SUCCESS(rc))
1253	rc = VINF_SUCCESS;
1254	# endif
1255	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4KBPages));
1256	PGM_INVL_PG(pVCpu, GCPtrPage);
1257	}
1258	else
1259	{
1260	/*
1261	* The page table address changed.
1262	*/
1263	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1264	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1265	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1266	ASMAtomicWriteSize(pPdeDst, 0);
1267	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1268	PGM_INVL_VCPU_TLBS(pVCpu);
1269	}
1270	}
1271	else
1272	{
1273	/*
1274	* 2/4MB - page.
1275	*/
1276	/* Before freeing the page, check if anything really changed. */
1277	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1278	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1279	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1280	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1281	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1282	# endif
1283	if ( pShwPage->GCPhys == GCPhys
1284	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1285	{
1286	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1287	/** @todo PAT */
1288	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1289	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1290	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1291	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1292	{
1293	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1294	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1295	# if defined(IN_RC)
1296	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1297	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1298	# endif
1299	return VINF_SUCCESS;
1300	}
1301	}
1302
1303	/*
1304	* Ok, the page table is present and it's been changed in the guest.
1305	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1306	* We could do this for some flushes in GC too, but we need an algorithm for
1307	* deciding which 4MB pages containing code likely to be executed very soon.
1308	*/
1309	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1310	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1311	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1312	ASMAtomicWriteSize(pPdeDst, 0);
1313	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPages));
1314	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
1315	}
1316	}
1317	else
1318	{
1319	/*
1320	* Page directory is not present, mark shadow PDE not present.
1321	*/
1322	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1323	{
1324	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1325	ASMAtomicWriteSize(pPdeDst, 0);
1326	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1327	PGM_INVL_PG(pVCpu, GCPtrPage);
1328	}
1329	else
1330	{
1331	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1332	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDMappings));
1333	}
1334	}
1335	# if defined(IN_RC)
1336	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1337	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1338	# endif
1339	return rc;
1340
1341	#else /* guest real and protected mode */
1342	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1343	return VINF_SUCCESS;
1344	#endif
1345	}
1346
1347
1348	#ifdef PGMPOOL_WITH_USER_TRACKING
1349	/**
1350	* Update the tracking of shadowed pages.
1351	*
1352	* @param pVCpu The VMCPU handle.
1353	* @param pShwPage The shadow page.
1354	* @param HCPhys The physical page we is being dereferenced.
1355	*/
1356	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
1357	{
1358	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1359	PVM pVM = pVCpu->CTX_SUFF(pVM);
1360
1361	STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1362	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1363
1364	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1365	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1366	* 2. write protect all shadowed pages. I.e. implement caching.
1367	*/
1368	/*
1369	* Find the guest address.
1370	*/
1371	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1372	pRam;
1373	pRam = pRam->CTX_SUFF(pNext))
1374	{
1375	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1376	while (iPage-- > 0)
1377	{
1378	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1379	{
1380	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1381	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage]);
1382	pShwPage->cPresent--;
1383	pPool->cPresent--;
1384	STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1385	return;
1386	}
1387	}
1388	}
1389
1390	for (;;)
1391	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1392	# else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1393	pShwPage->cPresent--;
1394	pVM->pgm.s.CTX_SUFF(pPool)->cPresent--;
1395	# endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1396	}
1397
1398
1399	/**
1400	* Update the tracking of shadowed pages.
1401	*
1402	* @param pVCpu The VMCPU handle.
1403	* @param pShwPage The shadow page.
1404	* @param u16 The top 16-bit of the pPage->HCPhys.
1405	* @param pPage Pointer to the guest page. this will be modified.
1406	* @param iPTDst The index into the shadow table.
1407	*/
1408	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1409	{
1410	PVM pVM = pVCpu->CTX_SUFF(pVM);
1411	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1412	/*
1413	* Just deal with the simple first time here.
1414	*/
1415	if (!u16)
1416	{
1417	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1418	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1419	}
1420	else
1421	u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1422
1423	/* write back */
1424	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1425	PGM_PAGE_SET_TRACKING(pPage, u16);
1426
1427	# endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1428
1429	/* update statistics. */
1430	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1431	pShwPage->cPresent++;
1432	if (pShwPage->iFirstPresent > iPTDst)
1433	pShwPage->iFirstPresent = iPTDst;
1434	}
1435	#endif /* PGMPOOL_WITH_USER_TRACKING */
1436
1437
1438	/**
1439	* Creates a 4K shadow page for a guest page.
1440	*
1441	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1442	* physical address. The PdeSrc argument only the flags are used. No page structured
1443	* will be mapped in this function.
1444	*
1445	* @param pVCpu The VMCPU handle.
1446	* @param pPteDst Destination page table entry.
1447	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1448	* Can safely assume that only the flags are being used.
1449	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1450	* @param pShwPage Pointer to the shadow page.
1451	* @param iPTDst The index into the shadow table.
1452	*
1453	* @remark Not used for 2/4MB pages!
1454	*/
1455	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1456	{
1457	if (PteSrc.n.u1Present)
1458	{
1459	PVM pVM = pVCpu->CTX_SUFF(pVM);
1460
1461	/*
1462	* Find the ram range.
1463	*/
1464	PPGMPAGE pPage;
1465	int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK, &pPage);
1466	if (RT_SUCCESS(rc))
1467	{
1468	#ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1469	/* Try make the page writable if necessary. */
1470	if ( PteSrc.n.u1Write
1471	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1472	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1473	{
1474	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, PteSrc.u & GST_PTE_PG_MASK);
1475	AssertRC(rc);
1476	}
1477	#endif
1478
1479	/** @todo investiage PWT, PCD and PAT. */
1480	/*
1481	* Make page table entry.
1482	*/
1483	SHWPTE PteDst;
1484	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1485	{
1486	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1487	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1488	{
1489	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1490	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1491	PteDst.n.u1Present = 1;
1492	PteDst.n.u1Execute = 1;
1493	PteDst.n.u1IgnorePAT = 1;
1494	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1495	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1496	#else
1497	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1498	\| PGM_PAGE_GET_HCPHYS(pPage);
1499	#endif
1500	}
1501	else
1502	{
1503	LogFlow(("SyncPageWorker: monitored page (%RHp) -> mark not present\n", PGM_PAGE_GET_HCPHYS(pPage)));
1504	PteDst.u = 0;
1505	}
1506	/** @todo count these two kinds. */
1507	}
1508	else
1509	{
1510	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1511	/*
1512	* If the page or page directory entry is not marked accessed,
1513	* we mark the page not present.
1514	*/
1515	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1516	{
1517	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1518	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,AccessedPage));
1519	PteDst.u = 0;
1520	}
1521	else
1522	/*
1523	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1524	* when the page is modified.
1525	*/
1526	if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1527	{
1528	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPage));
1529	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1530	\| PGM_PAGE_GET_HCPHYS(pPage)
1531	\| PGM_PTFLAGS_TRACK_DIRTY;
1532	}
1533	else
1534	#endif
1535	{
1536	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageSkipped));
1537	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1538	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1539	PteDst.n.u1Present = 1;
1540	PteDst.n.u1Write = 1;
1541	PteDst.n.u1Execute = 1;
1542	PteDst.n.u1IgnorePAT = 1;
1543	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1544	/* PteDst.n.u1Size = 0 */
1545	#else
1546	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1547	\| PGM_PAGE_GET_HCPHYS(pPage);
1548	#endif
1549	}
1550	}
1551
1552	/*
1553	* Make sure only allocated pages are mapped writable.
1554	*/
1555	if ( PteDst.n.u1Write
1556	&& PteDst.n.u1Present
1557	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1558	{
1559	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet. */
1560	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", (RTGCPHYS)(PteSrc.u & X86_PTE_PAE_PG_MASK), pPage, iPTDst));
1561	}
1562
1563	#ifdef PGMPOOL_WITH_USER_TRACKING
1564	/*
1565	* Keep user track up to date.
1566	*/
1567	if (PteDst.n.u1Present)
1568	{
1569	if (!pPteDst->n.u1Present)
1570	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1571	else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1572	{
1573	Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1574	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1575	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1576	}
1577	}
1578	else if (pPteDst->n.u1Present)
1579	{
1580	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1581	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1582	}
1583	#endif /* PGMPOOL_WITH_USER_TRACKING */
1584
1585	/*
1586	* Update statistics and commit the entry.
1587	*/
1588	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1589	if (!PteSrc.n.u1Global)
1590	pShwPage->fSeenNonGlobal = true;
1591	#endif
1592	ASMAtomicWriteSize(pPteDst, PteDst.u);
1593	}
1594	/* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1595	/** @todo count these. */
1596	}
1597	else
1598	{
1599	/*
1600	* Page not-present.
1601	*/
1602	LogFlow(("SyncPageWorker: page not present in Pte\n"));
1603	#ifdef PGMPOOL_WITH_USER_TRACKING
1604	/* Keep user track up to date. */
1605	if (pPteDst->n.u1Present)
1606	{
1607	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1608	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1609	}
1610	#endif /* PGMPOOL_WITH_USER_TRACKING */
1611	ASMAtomicWriteSize(pPteDst, 0);
1612	/** @todo count these. */
1613	}
1614	}
1615
1616
1617	/**
1618	* Syncs a guest OS page.
1619	*
1620	* There are no conflicts at this point, neither is there any need for
1621	* page table allocations.
1622	*
1623	* @returns VBox status code.
1624	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1625	* @param pVCpu The VMCPU handle.
1626	* @param PdeSrc Page directory entry of the guest.
1627	* @param GCPtrPage Guest context page address.
1628	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1629	* @param uErr Fault error (X86_TRAP_PF_*).
1630	*/
1631	PGM_BTH_DECL(int, SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1632	{
1633	PVM pVM = pVCpu->CTX_SUFF(pVM);
1634	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1635	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1636
1637	Assert(PGMIsLockOwner(pVM));
1638
1639	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1640	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1641	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1642	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1643	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1644
1645	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1646	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVCpu) & MSR_K6_EFER_NXE);
1647	# endif
1648
1649	/*
1650	* Assert preconditions.
1651	*/
1652	Assert(PdeSrc.n.u1Present);
1653	Assert(cPages);
1654	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1655
1656	/*
1657	* Get the shadow PDE, find the shadow page table in the pool.
1658	*/
1659	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1660	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1661	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
1662
1663	/* Fetch the pgm pool shadow descriptor. */
1664	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1665	Assert(pShwPde);
1666
1667	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1668	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1669	PPGMPOOLPAGE pShwPde = NULL;
1670	PX86PDPAE pPDDst;
1671
1672	/* Fetch the pgm pool shadow descriptor. */
1673	int rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
1674	AssertRCSuccessReturn(rc, rc);
1675	Assert(pShwPde);
1676
1677	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
1678	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1679
1680	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1681	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1682	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1683	PX86PDPAE pPDDst;
1684	PX86PDPT pPdptDst;
1685
1686	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1687	AssertRCSuccessReturn(rc, rc);
1688	Assert(pPDDst && pPdptDst);
1689	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1690	# endif
1691	SHWPDE PdeDst = *pPdeDst;
1692	if (!PdeDst.n.u1Present)
1693	{
1694	AssertMsg(pVM->cCPUs > 1, ("%Unexpected missing PDE p=%llx\n", pPdeDst, (uint64_t)PdeDst.u));
1695	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", GCPtrPage));
1696	return VINF_SUCCESS; /* force the instruction to be executed again. */
1697	}
1698
1699	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1700
1701	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1702	/* Fetch the pgm pool shadow descriptor. */
1703	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1704	Assert(pShwPde);
1705	# endif
1706
1707	# if defined(IN_RC)
1708	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1709	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
1710	# endif
1711
1712	/*
1713	* Check that the page is present and that the shadow PDE isn't out of sync.
1714	*/
1715	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1716	const bool fBigPage = PdeSrc.b.u1Size;
1717	# else
1718	const bool fBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
1719	# endif
1720	RTGCPHYS GCPhys;
1721	if (!fBigPage)
1722	{
1723	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1724	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1725	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1726	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1727	# endif
1728	}
1729	else
1730	{
1731	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1732	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1733	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1734	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1735	# endif
1736	}
1737	if ( pShwPage->GCPhys == GCPhys
1738	&& PdeSrc.n.u1Present
1739	&& (PdeSrc.n.u1User == PdeDst.n.u1User)
1740	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1741	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1742	&& (!fNoExecuteBitValid \|\| PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute)
1743	# endif
1744	)
1745	{
1746	/*
1747	* Check that the PDE is marked accessed already.
1748	* Since we set the accessed bit before getting here on a #PF, this
1749	* check is only meant for dealing with non-#PF'ing paths.
1750	*/
1751	if (PdeSrc.n.u1Accessed)
1752	{
1753	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1754	if (!fBigPage)
1755	{
1756	/*
1757	* 4KB Page - Map the guest page table.
1758	*/
1759	PGSTPT pPTSrc;
1760	int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1761	if (RT_SUCCESS(rc))
1762	{
1763	# ifdef PGM_SYNC_N_PAGES
1764	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1765	if ( cPages > 1
1766	&& !(uErr & X86_TRAP_PF_P)
1767	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1768	{
1769	/*
1770	* This code path is currently only taken when the caller is PGMTrap0eHandler
1771	* for non-present pages!
1772	*
1773	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1774	* deal with locality.
1775	*/
1776	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1777	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1778	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1779	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1780	# else
1781	const unsigned offPTSrc = 0;
1782	# endif
1783	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1784	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1785	iPTDst = 0;
1786	else
1787	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1788	for (; iPTDst < iPTDstEnd; iPTDst++)
1789	{
1790	if (!pPTDst->a[iPTDst].n.u1Present)
1791	{
1792	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1793	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1794	NOREF(GCPtrCurPage);
1795	#ifndef IN_RING0
1796	/*
1797	* Assuming kernel code will be marked as supervisor - and not as user level
1798	* and executed using a conforming code selector - And marked as readonly.
1799	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1800	*/
1801	PPGMPAGE pPage;
1802	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1803	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1804	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)GCPtrCurPage)
1805	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1806	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1807	)
1808	#endif /* else: CSAM not active */
1809	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1810	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1811	GCPtrCurPage, PteSrc.n.u1Present,
1812	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1813	PteSrc.n.u1User & PdeSrc.n.u1User,
1814	(uint64_t)PteSrc.u,
1815	(uint64_t)pPTDst->a[iPTDst].u,
1816	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1817	}
1818	}
1819	}
1820	else
1821	# endif /* PGM_SYNC_N_PAGES */
1822	{
1823	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1824	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1825	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1826	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1827	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1828	GCPtrPage, PteSrc.n.u1Present,
1829	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1830	PteSrc.n.u1User & PdeSrc.n.u1User,
1831	(uint64_t)PteSrc.u,
1832	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1833	}
1834	}
1835	else /* MMIO or invalid page: emulated in #PF handler. */
1836	{
1837	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
1838	Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1839	}
1840	}
1841	else
1842	{
1843	/*
1844	* 4/2MB page - lazy syncing shadow 4K pages.
1845	* (There are many causes of getting here, it's no longer only CSAM.)
1846	*/
1847	/* Calculate the GC physical address of this 4KB shadow page. */
1848	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1849	/* Find ram range. */
1850	PPGMPAGE pPage;
1851	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1852	if (RT_SUCCESS(rc))
1853	{
1854	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1855	/* Try make the page writable if necessary. */
1856	if ( PdeSrc.n.u1Write
1857	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1858	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1859	{
1860	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
1861	AssertRC(rc);
1862	}
1863	# endif
1864
1865	/*
1866	* Make shadow PTE entry.
1867	*/
1868	SHWPTE PteDst;
1869	PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1870	\| PGM_PAGE_GET_HCPHYS(pPage);
1871	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1872	{
1873	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1874	PteDst.n.u1Write = 0;
1875	else
1876	PteDst.u = 0;
1877	}
1878	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1879	# ifdef PGMPOOL_WITH_USER_TRACKING
1880	if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1881	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1882	# endif
1883	/* Make sure only allocated pages are mapped writable. */
1884	if ( PteDst.n.u1Write
1885	&& PteDst.n.u1Present
1886	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1887	{
1888	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet... */
1889	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
1890	}
1891
1892	ASMAtomicWriteSize(&pPTDst->a[iPTDst], PteDst.u);
1893
1894	/*
1895	* If the page is not flagged as dirty and is writable, then make it read-only
1896	* at PD level, so we can set the dirty bit when the page is modified.
1897	*
1898	* ASSUMES that page access handlers are implemented on page table entry level.
1899	* Thus we will first catch the dirty access and set PDE.D and restart. If
1900	* there is an access handler, we'll trap again and let it work on the problem.
1901	*/
1902	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1903	* As for invlpg, it simply frees the whole shadow PT.
1904	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1905	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1906	{
1907	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
1908	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1909	PdeDst.n.u1Write = 0;
1910	}
1911	else
1912	{
1913	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1914	PdeDst.n.u1Write = PdeSrc.n.u1Write;
1915	}
1916	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
1917	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
1918	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1919	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1920	}
1921	else
1922	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
1923	}
1924	# if defined(IN_RC)
1925	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1926	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1927	# endif
1928	return VINF_SUCCESS;
1929	}
1930	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDNAs));
1931	}
1932	else
1933	{
1934	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSync));
1935	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
1936	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
1937	}
1938
1939	/*
1940	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1941	* Yea, I'm lazy.
1942	*/
1943	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
1944	ASMAtomicWriteSize(pPdeDst, 0);
1945
1946	# if defined(IN_RC)
1947	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1948	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1949	# endif
1950	PGM_INVL_VCPU_TLBS(pVCpu);
1951	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
1952
1953	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
1954	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1955	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
1956	&& !defined(IN_RC)
1957
1958	# ifdef PGM_SYNC_N_PAGES
1959	/*
1960	* Get the shadow PDE, find the shadow page table in the pool.
1961	*/
1962	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1963	X86PDE PdeDst = pgmShwGet32BitPDE(&pVCpu->pgm.s, GCPtrPage);
1964
1965	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1966	X86PDEPAE PdeDst = pgmShwGetPaePDE(&pVCpu->pgm.s, GCPtrPage);
1967
1968	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1969	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1970	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
1971	PX86PDPAE pPDDst;
1972	X86PDEPAE PdeDst;
1973	PX86PDPT pPdptDst;
1974
1975	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1976	AssertRCSuccessReturn(rc, rc);
1977	Assert(pPDDst && pPdptDst);
1978	PdeDst = pPDDst->a[iPDDst];
1979	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
1980	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1981	PEPTPD pPDDst;
1982	EPTPDE PdeDst;
1983
1984	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, NULL, &pPDDst);
1985	if (rc != VINF_SUCCESS)
1986	{
1987	AssertRC(rc);
1988	return rc;
1989	}
1990	Assert(pPDDst);
1991	PdeDst = pPDDst->a[iPDDst];
1992	# endif
1993	AssertMsg(PdeDst.n.u1Present, ("%#llx\n", (uint64_t)PdeDst.u));
1994	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1995	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1996
1997	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1998	if ( cPages > 1
1999	&& !(uErr & X86_TRAP_PF_P)
2000	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2001	{
2002	/*
2003	* This code path is currently only taken when the caller is PGMTrap0eHandler
2004	* for non-present pages!
2005	*
2006	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2007	* deal with locality.
2008	*/
2009	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2010	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2011	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2012	iPTDst = 0;
2013	else
2014	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2015	for (; iPTDst < iPTDstEnd; iPTDst++)
2016	{
2017	if (!pPTDst->a[iPTDst].n.u1Present)
2018	{
2019	GSTPTE PteSrc;
2020
2021	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2022
2023	/* Fake the page table entry */
2024	PteSrc.u = GCPtrCurPage;
2025	PteSrc.n.u1Present = 1;
2026	PteSrc.n.u1Dirty = 1;
2027	PteSrc.n.u1Accessed = 1;
2028	PteSrc.n.u1Write = 1;
2029	PteSrc.n.u1User = 1;
2030
2031	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2032
2033	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
2034	GCPtrCurPage, PteSrc.n.u1Present,
2035	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2036	PteSrc.n.u1User & PdeSrc.n.u1User,
2037	(uint64_t)PteSrc.u,
2038	(uint64_t)pPTDst->a[iPTDst].u,
2039	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2040
2041	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
2042	break;
2043	}
2044	else
2045	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, pPTDst->a[iPTDst].u));
2046	}
2047	}
2048	else
2049	# endif /* PGM_SYNC_N_PAGES */
2050	{
2051	GSTPTE PteSrc;
2052	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2053	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2054
2055	/* Fake the page table entry */
2056	PteSrc.u = GCPtrCurPage;
2057	PteSrc.n.u1Present = 1;
2058	PteSrc.n.u1Dirty = 1;
2059	PteSrc.n.u1Accessed = 1;
2060	PteSrc.n.u1Write = 1;
2061	PteSrc.n.u1User = 1;
2062	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2063
2064	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}PteDst=%08llx%s\n",
2065	GCPtrPage, PteSrc.n.u1Present,
2066	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2067	PteSrc.n.u1User & PdeSrc.n.u1User,
2068	(uint64_t)PteSrc.u,
2069	(uint64_t)pPTDst->a[iPTDst].u,
2070	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2071	}
2072	return VINF_SUCCESS;
2073
2074	#else
2075	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2076	return VERR_INTERNAL_ERROR;
2077	#endif
2078	}
2079
2080
2081	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2082	/**
2083	* Investigate page fault and handle write protection page faults caused by
2084	* dirty bit tracking.
2085	*
2086	* @returns VBox status code.
2087	* @param pVCpu The VMCPU handle.
2088	* @param uErr Page fault error code.
2089	* @param pPdeDst Shadow page directory entry.
2090	* @param pPdeSrc Guest page directory entry.
2091	* @param GCPtrPage Guest context page address.
2092	*/
2093	PGM_BTH_DECL(int, CheckPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage)
2094	{
2095	bool fWriteProtect = !!(CPUMGetGuestCR0(pVCpu) & X86_CR0_WP);
2096	bool fUserLevelFault = !!(uErr & X86_TRAP_PF_US);
2097	bool fWriteFault = !!(uErr & X86_TRAP_PF_RW);
2098	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2099	bool fBigPagesSupported = true;
2100	# else
2101	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2102	# endif
2103	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2104	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVCpu) & MSR_K6_EFER_NXE);
2105	# endif
2106	unsigned uPageFaultLevel;
2107	int rc;
2108	PVM pVM = pVCpu->CTX_SUFF(pVM);
2109	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2110
2111	Assert(PGMIsLockOwner(pVM));
2112
2113	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2114	LogFlow(("CheckPageFault: GCPtrPage=%RGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
2115
2116	# if PGM_GST_TYPE == PGM_TYPE_PAE \
2117	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
2118
2119	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2120	PX86PML4E pPml4eSrc;
2121	PX86PDPE pPdpeSrc;
2122
2123	pPdpeSrc = pgmGstGetLongModePDPTPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc);
2124	Assert(pPml4eSrc);
2125
2126	/*
2127	* Real page fault? (PML4E level)
2128	*/
2129	if ( (uErr & X86_TRAP_PF_RSVD)
2130	\|\| !pPml4eSrc->n.u1Present
2131	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPml4eSrc->n.u1NoExecute)
2132	\|\| (fWriteFault && !pPml4eSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2133	\|\| (fUserLevelFault && !pPml4eSrc->n.u1User)
2134	)
2135	{
2136	uPageFaultLevel = 0;
2137	goto l_UpperLevelPageFault;
2138	}
2139	Assert(pPdpeSrc);
2140
2141	# else /* PAE */
2142	PX86PDPE pPdpeSrc = pgmGstGetPaePDPEPtr(&pVCpu->pgm.s, GCPtrPage);
2143	# endif /* PAE */
2144
2145	/*
2146	* Real page fault? (PDPE level)
2147	*/
2148	if ( (uErr & X86_TRAP_PF_RSVD)
2149	\|\| !pPdpeSrc->n.u1Present
2150	# if PGM_GST_TYPE == PGM_TYPE_AMD64 /* NX, r/w, u/s bits in the PDPE are long mode only */
2151	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdpeSrc->lm.u1NoExecute)
2152	\|\| (fWriteFault && !pPdpeSrc->lm.u1Write && (fUserLevelFault \|\| fWriteProtect))
2153	\|\| (fUserLevelFault && !pPdpeSrc->lm.u1User)
2154	# endif
2155	)
2156	{
2157	uPageFaultLevel = 1;
2158	goto l_UpperLevelPageFault;
2159	}
2160	# endif
2161
2162	/*
2163	* Real page fault? (PDE level)
2164	*/
2165	if ( (uErr & X86_TRAP_PF_RSVD)
2166	\|\| !pPdeSrc->n.u1Present
2167	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2168	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdeSrc->n.u1NoExecute)
2169	# endif
2170	\|\| (fWriteFault && !pPdeSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2171	\|\| (fUserLevelFault && !pPdeSrc->n.u1User) )
2172	{
2173	uPageFaultLevel = 2;
2174	goto l_UpperLevelPageFault;
2175	}
2176
2177	/*
2178	* First check the easy case where the page directory has been marked read-only to track
2179	* the dirty bit of an emulated BIG page
2180	*/
2181	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2182	{
2183	/* Mark guest page directory as accessed */
2184	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2185	pPml4eSrc->n.u1Accessed = 1;
2186	pPdpeSrc->lm.u1Accessed = 1;
2187	# endif
2188	pPdeSrc->b.u1Accessed = 1;
2189
2190	/*
2191	* Only write protection page faults are relevant here.
2192	*/
2193	if (fWriteFault)
2194	{
2195	/* Mark guest page directory as dirty (BIG page only). */
2196	pPdeSrc->b.u1Dirty = 1;
2197
2198	if (pPdeDst->n.u1Present)
2199	{
2200	if (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY)
2201	{
2202	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2203	Assert(pPdeSrc->b.u1Write);
2204
2205	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2206	* fault again and take this path to only invalidate the entry.
2207	*/
2208	pPdeDst->n.u1Write = 1;
2209	pPdeDst->n.u1Accessed = 1;
2210	pPdeDst->au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2211	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
2212	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2213	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2214	}
2215	# ifdef IN_RING0
2216	else
2217	/* Check for stale TLB entry; only applies to the SMP guest case. */
2218	if ( pVM->cCPUs > 1
2219	&& pPdeDst->n.u1Write
2220	&& pPdeDst->n.u1Accessed)
2221	{
2222	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2223	if (pShwPage)
2224	{
2225	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2226	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2227	if ( pPteDst->n.u1Present
2228	&& pPteDst->n.u1Write)
2229	{
2230	/* Stale TLB entry. */
2231	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageStale));
2232	PGM_INVL_PG(pVCpu, GCPtrPage);
2233
2234	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2235	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2236	}
2237	}
2238	}
2239	# endif /* IN_RING0 */
2240	}
2241	}
2242	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2243	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2244	}
2245	/* else: 4KB page table */
2246
2247	/*
2248	* Map the guest page table.
2249	*/
2250	PGSTPT pPTSrc;
2251	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2252	if (RT_SUCCESS(rc))
2253	{
2254	/*
2255	* Real page fault?
2256	*/
2257	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2258	const GSTPTE PteSrc = *pPteSrc;
2259	if ( !PteSrc.n.u1Present
2260	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2261	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && PteSrc.n.u1NoExecute)
2262	# endif
2263	\|\| (fWriteFault && !PteSrc.n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2264	\|\| (fUserLevelFault && !PteSrc.n.u1User)
2265	)
2266	{
2267	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2268	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2269	LogFlow(("CheckPageFault: real page fault at %RGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
2270
2271	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
2272	* See the 2nd case above as well.
2273	*/
2274	if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
2275	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2276
2277	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2278	return VINF_EM_RAW_GUEST_TRAP;
2279	}
2280	LogFlow(("CheckPageFault: page fault at %RGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
2281
2282	/*
2283	* Set the accessed bits in the page directory and the page table.
2284	*/
2285	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2286	pPml4eSrc->n.u1Accessed = 1;
2287	pPdpeSrc->lm.u1Accessed = 1;
2288	# endif
2289	pPdeSrc->n.u1Accessed = 1;
2290	pPteSrc->n.u1Accessed = 1;
2291
2292	/*
2293	* Only write protection page faults are relevant here.
2294	*/
2295	if (fWriteFault)
2296	{
2297	/* Write access, so mark guest entry as dirty. */
2298	# ifdef VBOX_WITH_STATISTICS
2299	if (!pPteSrc->n.u1Dirty)
2300	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtiedPage));
2301	else
2302	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageAlreadyDirty));
2303	# endif
2304
2305	pPteSrc->n.u1Dirty = 1;
2306
2307	if (pPdeDst->n.u1Present)
2308	{
2309	#ifndef IN_RING0
2310	/* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
2311	* Our individual shadow handlers will provide more information and force a fatal exit.
2312	*/
2313	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2314	{
2315	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2316	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2317	return VINF_SUCCESS;
2318	}
2319	#endif
2320	/*
2321	* Map shadow page table.
2322	*/
2323	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2324	if (pShwPage)
2325	{
2326	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2327	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2328	if (pPteDst->n.u1Present) /** @todo Optimize accessed bit emulation? */
2329	{
2330	if (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY)
2331	{
2332	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2333	# ifdef VBOX_STRICT
2334	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
2335	if (pPage)
2336	AssertMsg(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage),
2337	("Unexpected dirty bit tracking on monitored page %RGv (phys %RGp)!!!!!!\n", GCPtrPage, pPteSrc->u & X86_PTE_PAE_PG_MASK));
2338	# endif
2339	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2340
2341	Assert(pPteSrc->n.u1Write);
2342
2343	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2344	* fault again and take this path to only invalidate the entry.
2345	*/
2346	pPteDst->n.u1Write = 1;
2347	pPteDst->n.u1Dirty = 1;
2348	pPteDst->n.u1Accessed = 1;
2349	pPteDst->au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
2350	PGM_INVL_PG(pVCpu, GCPtrPage);
2351
2352	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2353	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2354	}
2355	# ifdef IN_RING0
2356	else
2357	/* Check for stale TLB entry; only applies to the SMP guest case. */
2358	if ( pVM->cCPUs > 1
2359	&& pPteDst->n.u1Write == 1
2360	&& pPteDst->n.u1Accessed == 1)
2361	{
2362	/* Stale TLB entry. */
2363	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageStale));
2364	PGM_INVL_PG(pVCpu, GCPtrPage);
2365
2366	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2367	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2368	}
2369	# endif
2370	}
2371	}
2372	else
2373	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2374	}
2375	}
2376	/** @todo Optimize accessed bit emulation? */
2377	# ifdef VBOX_STRICT
2378	/*
2379	* Sanity check.
2380	*/
2381	else if ( !pPteSrc->n.u1Dirty
2382	&& (pPdeSrc->n.u1Write & pPteSrc->n.u1Write)
2383	&& pPdeDst->n.u1Present)
2384	{
2385	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2386	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2387	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2388	if ( pPteDst->n.u1Present
2389	&& pPteDst->n.u1Write)
2390	LogFlow(("Writable present page %RGv not marked for dirty bit tracking!!!\n", GCPtrPage));
2391	}
2392	# endif /* VBOX_STRICT */
2393	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2394	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2395	}
2396	AssertRC(rc);
2397	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2398	return rc;
2399
2400
2401	l_UpperLevelPageFault:
2402	/*
2403	* Pagefault detected while checking the PML4E, PDPE or PDE.
2404	* Single exit handler to get rid of duplicate code paths.
2405	*/
2406	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2407	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2408	Log(("CheckPageFault: real page fault at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2409
2410	if (
2411	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2412	pPml4eSrc->n.u1Present &&
2413	# endif
2414	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
2415	pPdpeSrc->n.u1Present &&
2416	# endif
2417	pPdeSrc->n.u1Present)
2418	{
2419	/* Check the present bit as the shadow tables can cause different error codes by being out of sync. */
2420	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2421	{
2422	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2423	}
2424	else
2425	{
2426	/*
2427	* Map the guest page table.
2428	*/
2429	PGSTPT pPTSrc;
2430	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2431	if (RT_SUCCESS(rc))
2432	{
2433	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2434	const GSTPTE PteSrc = *pPteSrc;
2435	if (pPteSrc->n.u1Present)
2436	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2437	}
2438	AssertRC(rc);
2439	}
2440	}
2441	return VINF_EM_RAW_GUEST_TRAP;
2442	}
2443	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2444
2445
2446	/**
2447	* Sync a shadow page table.
2448	*
2449	* The shadow page table is not present. This includes the case where
2450	* there is a conflict with a mapping.
2451	*
2452	* @returns VBox status code.
2453	* @param pVCpu The VMCPU handle.
2454	* @param iPD Page directory index.
2455	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2456	* Assume this is a temporary mapping.
2457	* @param GCPtrPage GC Pointer of the page that caused the fault
2458	*/
2459	PGM_BTH_DECL(int, SyncPT)(PVMCPU pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2460	{
2461	PVM pVM = pVCpu->CTX_SUFF(pVM);
2462	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2463
2464	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2465	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
2466	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage));
2467
2468	Assert(PGMIsLocked(pVM));
2469
2470	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2471	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2472	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2473	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2474	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2475
2476	int rc = VINF_SUCCESS;
2477
2478	/*
2479	* Validate input a little bit.
2480	*/
2481	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2482	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2483	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2484	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
2485
2486	/* Fetch the pgm pool shadow descriptor. */
2487	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2488	Assert(pShwPde);
2489
2490	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2491	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2492	PPGMPOOLPAGE pShwPde = NULL;
2493	PX86PDPAE pPDDst;
2494	PSHWPDE pPdeDst;
2495
2496	/* Fetch the pgm pool shadow descriptor. */
2497	rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
2498	AssertRCSuccessReturn(rc, rc);
2499	Assert(pShwPde);
2500
2501	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
2502	pPdeDst = &pPDDst->a[iPDDst];
2503
2504	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2505	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2506	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2507	PX86PDPAE pPDDst;
2508	PX86PDPT pPdptDst;
2509	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2510	AssertRCSuccessReturn(rc, rc);
2511	Assert(pPDDst);
2512	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2513	# endif
2514	SHWPDE PdeDst = *pPdeDst;
2515
2516	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2517	/* Fetch the pgm pool shadow descriptor. */
2518	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2519	Assert(pShwPde);
2520	# endif
2521
2522	# ifndef PGM_WITHOUT_MAPPINGS
2523	/*
2524	* Check for conflicts.
2525	* GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2526	* HC: Simply resolve the conflict.
2527	*/
2528	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2529	{
2530	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2531	# ifndef IN_RING3
2532	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2533	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2534	return VERR_ADDRESS_CONFLICT;
2535	# else
2536	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2537	Assert(pMapping);
2538	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2539	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2540	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2541	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2542	# else
2543	AssertFailed(); /* can't happen for amd64 */
2544	# endif
2545	if (RT_FAILURE(rc))
2546	{
2547	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2548	return rc;
2549	}
2550	PdeDst = *pPdeDst;
2551	# endif
2552	}
2553	# else /* PGM_WITHOUT_MAPPINGS */
2554	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
2555	# endif /* PGM_WITHOUT_MAPPINGS */
2556	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2557
2558	# if defined(IN_RC)
2559	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
2560	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
2561	# endif
2562
2563	/*
2564	* Sync page directory entry.
2565	*/
2566	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2567	if (PdeSrc.n.u1Present)
2568	{
2569	/*
2570	* Allocate & map the page table.
2571	*/
2572	PSHWPT pPTDst;
2573	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2574	const bool fPageTable = !PdeSrc.b.u1Size;
2575	# else
2576	const bool fPageTable = !PdeSrc.b.u1Size \|\| !(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2577	# endif
2578	PPGMPOOLPAGE pShwPage;
2579	RTGCPHYS GCPhys;
2580	if (fPageTable)
2581	{
2582	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2583	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2584	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2585	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2586	# endif
2587	/* Modify the physical address to distinguish between different access types to prevent incorrect reuse of cached entries. */
2588	if (PdeSrc.n.u1Write)
2589	GCPhys \|= PGMPOOL_PHYS_ACCESS_RW;
2590	if (PdeSrc.n.u1User)
2591	GCPhys \|= PGMPOOL_PHYS_ACCESS_USER;
2592
2593	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2594	}
2595	else
2596	{
2597	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
2598	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2599	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2600	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
2601	# endif
2602	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, pShwPde->idx, iPDDst, &pShwPage);
2603	}
2604	if (rc == VINF_SUCCESS)
2605	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2606	else if (rc == VINF_PGM_CACHED_PAGE)
2607	{
2608	/*
2609	* The PT was cached, just hook it up.
2610	*/
2611	if (fPageTable)
2612	PdeDst.u = pShwPage->Core.Key
2613	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2614	else
2615	{
2616	PdeDst.u = pShwPage->Core.Key
2617	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2618	/* (see explanation and assumptions further down.) */
2619	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2620	{
2621	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2622	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2623	PdeDst.b.u1Write = 0;
2624	}
2625	}
2626	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2627	# if defined(IN_RC)
2628	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2629	# endif
2630	return VINF_SUCCESS;
2631	}
2632	else if (rc == VERR_PGM_POOL_FLUSHED)
2633	{
2634	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2635	# if defined(IN_RC)
2636	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2637	# endif
2638	return VINF_PGM_SYNC_CR3;
2639	}
2640	else
2641	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2642	PdeDst.u &= X86_PDE_AVL_MASK;
2643	PdeDst.u \|= pShwPage->Core.Key;
2644
2645	/*
2646	* Page directory has been accessed (this is a fault situation, remember).
2647	*/
2648	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2649	if (fPageTable)
2650	{
2651	/*
2652	* Page table - 4KB.
2653	*
2654	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2655	*/
2656	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2657	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2658	PGSTPT pPTSrc;
2659	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
2660	if (RT_SUCCESS(rc))
2661	{
2662	/*
2663	* Start by syncing the page directory entry so CSAM's TLB trick works.
2664	*/
2665	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2666	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2667	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2668	# if defined(IN_RC)
2669	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2670	# endif
2671
2672	/*
2673	* Directory/page user or supervisor privilege: (same goes for read/write)
2674	*
2675	* Directory Page Combined
2676	* U/S U/S U/S
2677	* 0 0 0
2678	* 0 1 0
2679	* 1 0 0
2680	* 1 1 1
2681	*
2682	* Simple AND operation. Table listed for completeness.
2683	*
2684	*/
2685	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT4K));
2686	# ifdef PGM_SYNC_N_PAGES
2687	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2688	unsigned iPTDst = iPTBase;
2689	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2690	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2691	iPTDst = 0;
2692	else
2693	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2694	# else /* !PGM_SYNC_N_PAGES */
2695	unsigned iPTDst = 0;
2696	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2697	# endif /* !PGM_SYNC_N_PAGES */
2698	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2699	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2700	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2701	# else
2702	const unsigned offPTSrc = 0;
2703	# endif
2704	for (; iPTDst < iPTDstEnd; iPTDst++)
2705	{
2706	const unsigned iPTSrc = iPTDst + offPTSrc;
2707	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2708
2709	if (PteSrc.n.u1Present) /* we've already cleared it above */
2710	{
2711	# ifndef IN_RING0
2712	/*
2713	* Assuming kernel code will be marked as supervisor - and not as user level
2714	* and executed using a conforming code selector - And marked as readonly.
2715	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2716	*/
2717	PPGMPAGE pPage;
2718	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2719	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)))
2720	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
2721	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2722	)
2723	# endif
2724	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2725	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2726	(RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)),
2727	PteSrc.n.u1Present,
2728	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2729	PteSrc.n.u1User & PdeSrc.n.u1User,
2730	(uint64_t)PteSrc.u,
2731	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2732	(RTGCPHYS)((PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)) ));
2733	}
2734	} /* for PTEs */
2735	}
2736	}
2737	else
2738	{
2739	/*
2740	* Big page - 2/4MB.
2741	*
2742	* We'll walk the ram range list in parallel and optimize lookups.
2743	* We will only sync on shadow page table at a time.
2744	*/
2745	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT4M));
2746
2747	/**
2748	* @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2749	*/
2750
2751	/*
2752	* Start by syncing the page directory entry.
2753	*/
2754	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2755	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2756
2757	/*
2758	* If the page is not flagged as dirty and is writable, then make it read-only
2759	* at PD level, so we can set the dirty bit when the page is modified.
2760	*
2761	* ASSUMES that page access handlers are implemented on page table entry level.
2762	* Thus we will first catch the dirty access and set PDE.D and restart. If
2763	* there is an access handler, we'll trap again and let it work on the problem.
2764	*/
2765	/** @todo move the above stuff to a section in the PGM documentation. */
2766	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2767	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2768	{
2769	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2770	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2771	PdeDst.b.u1Write = 0;
2772	}
2773	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2774	# if defined(IN_RC)
2775	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2776	# endif
2777
2778	/*
2779	* Fill the shadow page table.
2780	*/
2781	/* Get address and flags from the source PDE. */
2782	SHWPTE PteDstBase;
2783	PteDstBase.u = PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT);
2784
2785	/* Loop thru the entries in the shadow PT. */
2786	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2787	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2788	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2789	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2790	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2791	unsigned iPTDst = 0;
2792	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2793	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2794	{
2795	/* Advance ram range list. */
2796	while (pRam && GCPhys > pRam->GCPhysLast)
2797	pRam = pRam->CTX_SUFF(pNext);
2798	if (pRam && GCPhys >= pRam->GCPhys)
2799	{
2800	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2801	do
2802	{
2803	/* Make shadow PTE. */
2804	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2805	SHWPTE PteDst;
2806
2807	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2808	/* Try make the page writable if necessary. */
2809	if ( PteDstBase.n.u1Write
2810	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2811	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2812	{
2813	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
2814	AssertRCReturn(rc, rc);
2815	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2816	break;
2817	}
2818	# endif
2819
2820	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2821	{
2822	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2823	{
2824	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2825	PteDst.n.u1Write = 0;
2826	}
2827	else
2828	PteDst.u = 0;
2829	}
2830	# ifndef IN_RING0
2831	/*
2832	* Assuming kernel code will be marked as supervisor and not as user level and executed
2833	* using a conforming code selector. Don't check for readonly, as that implies the whole
2834	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2835	*/
2836	else if ( !PdeSrc.n.u1User
2837	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))))
2838	PteDst.u = 0;
2839	# endif
2840	else
2841	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2842
2843	/* Only map writable pages writable. */
2844	if ( PteDst.n.u1Write
2845	&& PteDst.n.u1Present
2846	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2847	{
2848	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet... */
2849	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
2850	}
2851
2852	# ifdef PGMPOOL_WITH_USER_TRACKING
2853	if (PteDst.n.u1Present)
2854	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2855	# endif
2856	/* commit it */
2857	pPTDst->a[iPTDst] = PteDst;
2858	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2859	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2860	PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2861
2862	/* advance */
2863	GCPhys += PAGE_SIZE;
2864	iHCPage++;
2865	iPTDst++;
2866	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2867	&& GCPhys <= pRam->GCPhysLast);
2868	}
2869	else if (pRam)
2870	{
2871	Log(("Invalid pages at %RGp\n", GCPhys));
2872	do
2873	{
2874	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2875	GCPhys += PAGE_SIZE;
2876	iPTDst++;
2877	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2878	&& GCPhys < pRam->GCPhys);
2879	}
2880	else
2881	{
2882	Log(("Invalid pages at %RGp (2)\n", GCPhys));
2883	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
2884	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2885	}
2886	} /* while more PTEs */
2887	} /* 4KB / 4MB */
2888	}
2889	else
2890	AssertRelease(!PdeDst.n.u1Present);
2891
2892	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2893	if (RT_FAILURE(rc))
2894	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPTFailed));
2895	return rc;
2896
2897	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2898	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2899	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2900	&& !defined(IN_RC)
2901
2902	/*
2903	* Validate input a little bit.
2904	*/
2905	int rc = VINF_SUCCESS;
2906	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2907	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2908	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
2909
2910	/* Fetch the pgm pool shadow descriptor. */
2911	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2912	Assert(pShwPde);
2913
2914	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2915	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2916	PPGMPOOLPAGE pShwPde;
2917	PX86PDPAE pPDDst;
2918	PSHWPDE pPdeDst;
2919
2920	/* Fetch the pgm pool shadow descriptor. */
2921	rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
2922	AssertRCSuccessReturn(rc, rc);
2923	Assert(pShwPde);
2924
2925	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
2926	pPdeDst = &pPDDst->a[iPDDst];
2927
2928	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2929	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2930	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2931	PX86PDPAE pPDDst;
2932	PX86PDPT pPdptDst;
2933	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2934	AssertRCSuccessReturn(rc, rc);
2935	Assert(pPDDst);
2936	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2937
2938	/* Fetch the pgm pool shadow descriptor. */
2939	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2940	Assert(pShwPde);
2941
2942	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2943	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
2944	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2945	PEPTPD pPDDst;
2946	PEPTPDPT pPdptDst;
2947
2948	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
2949	if (rc != VINF_SUCCESS)
2950	{
2951	AssertRC(rc);
2952	return rc;
2953	}
2954	Assert(pPDDst);
2955	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2956
2957	/* Fetch the pgm pool shadow descriptor. */
2958	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
2959	Assert(pShwPde);
2960	# endif
2961	SHWPDE PdeDst = *pPdeDst;
2962
2963	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
2964	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2965
2966	GSTPDE PdeSrc;
2967	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2968	PdeSrc.n.u1Present = 1;
2969	PdeSrc.n.u1Write = 1;
2970	PdeSrc.n.u1Accessed = 1;
2971	PdeSrc.n.u1User = 1;
2972
2973	/*
2974	* Allocate & map the page table.
2975	*/
2976	PSHWPT pPTDst;
2977	PPGMPOOLPAGE pShwPage;
2978	RTGCPHYS GCPhys;
2979
2980	/* Virtual address = physical address */
2981	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK;
2982	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2983
2984	if ( rc == VINF_SUCCESS
2985	\|\| rc == VINF_PGM_CACHED_PAGE)
2986	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2987	else
2988	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2989
2990	PdeDst.u &= X86_PDE_AVL_MASK;
2991	PdeDst.u \|= pShwPage->Core.Key;
2992	PdeDst.n.u1Present = 1;
2993	PdeDst.n.u1Write = 1;
2994	# if PGM_SHW_TYPE == PGM_TYPE_EPT
2995	PdeDst.n.u1Execute = 1;
2996	# else
2997	PdeDst.n.u1User = 1;
2998	PdeDst.n.u1Accessed = 1;
2999	# endif
3000	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3001
3002	pgmLock(pVM);
3003	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
3004	pgmUnlock(pVM);
3005	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
3006	return rc;
3007
3008	#else
3009	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
3010	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
3011	return VERR_INTERNAL_ERROR;
3012	#endif
3013	}
3014
3015
3016
3017	/**
3018	* Prefetch a page/set of pages.
3019	*
3020	* Typically used to sync commonly used pages before entering raw mode
3021	* after a CR3 reload.
3022	*
3023	* @returns VBox status code.
3024	* @param pVCpu The VMCPU handle.
3025	* @param GCPtrPage Page to invalidate.
3026	*/
3027	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
3028	{
3029	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
3030	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3031	/*
3032	* Check that all Guest levels thru the PDE are present, getting the
3033	* PD and PDE in the processes.
3034	*/
3035	int rc = VINF_SUCCESS;
3036	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3037	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3038	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3039	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
3040	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3041	unsigned iPDSrc;
3042	X86PDPE PdpeSrc;
3043	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
3044	if (!pPDSrc)
3045	return VINF_SUCCESS; /* not present */
3046	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3047	unsigned iPDSrc;
3048	PX86PML4E pPml4eSrc;
3049	X86PDPE PdpeSrc;
3050	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3051	if (!pPDSrc)
3052	return VINF_SUCCESS; /* not present */
3053	# endif
3054	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3055	# else
3056	PGSTPD pPDSrc = NULL;
3057	const unsigned iPDSrc = 0;
3058	GSTPDE PdeSrc;
3059
3060	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
3061	PdeSrc.n.u1Present = 1;
3062	PdeSrc.n.u1Write = 1;
3063	PdeSrc.n.u1Accessed = 1;
3064	PdeSrc.n.u1User = 1;
3065	# endif
3066
3067	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
3068	{
3069	PVM pVM = pVCpu->CTX_SUFF(pVM);
3070	pgmLock(pVM);
3071
3072	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3073	const X86PDE PdeDst = pgmShwGet32BitPDE(&pVCpu->pgm.s, GCPtrPage);
3074	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3075	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3076	PX86PDPAE pPDDst;
3077	X86PDEPAE PdeDst;
3078	# if PGM_GST_TYPE != PGM_TYPE_PAE
3079	X86PDPE PdpeSrc;
3080
3081	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3082	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3083	# endif
3084	int rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, &PdpeSrc, &pPDDst);
3085	if (rc != VINF_SUCCESS)
3086	{
3087	pgmUnlock(pVM);
3088	AssertRC(rc);
3089	return rc;
3090	}
3091	Assert(pPDDst);
3092	PdeDst = pPDDst->a[iPDDst];
3093
3094	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3095	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3096	PX86PDPAE pPDDst;
3097	X86PDEPAE PdeDst;
3098
3099	# if PGM_GST_TYPE == PGM_TYPE_PROT
3100	/* AMD-V nested paging */
3101	X86PML4E Pml4eSrc;
3102	X86PDPE PdpeSrc;
3103	PX86PML4E pPml4eSrc = &Pml4eSrc;
3104
3105	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3106	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
3107	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
3108	# endif
3109
3110	int rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
3111	if (rc != VINF_SUCCESS)
3112	{
3113	pgmUnlock(pVM);
3114	AssertRC(rc);
3115	return rc;
3116	}
3117	Assert(pPDDst);
3118	PdeDst = pPDDst->a[iPDDst];
3119	# endif
3120	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
3121	{
3122	if (!PdeDst.n.u1Present)
3123	{
3124	/** r=bird: This guy will set the A bit on the PDE, probably harmless. */
3125	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3126	}
3127	else
3128	{
3129	/** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3130	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3131	* makes no sense to prefetch more than one page.
3132	*/
3133	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3134	if (RT_SUCCESS(rc))
3135	rc = VINF_SUCCESS;
3136	}
3137	}
3138	pgmUnlock(pVM);
3139	}
3140	return rc;
3141
3142	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3143	return VINF_SUCCESS; /* ignore */
3144	#endif
3145	}
3146
3147
3148
3149
3150	/**
3151	* Syncs a page during a PGMVerifyAccess() call.
3152	*
3153	* @returns VBox status code (informational included).
3154	* @param pVCpu The VMCPU handle.
3155	* @param GCPtrPage The address of the page to sync.
3156	* @param fPage The effective guest page flags.
3157	* @param uErr The trap error code.
3158	*/
3159	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3160	{
3161	PVM pVM = pVCpu->CTX_SUFF(pVM);
3162
3163	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3164
3165	Assert(!HWACCMIsNestedPagingActive(pVM));
3166	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_TYPE_AMD64) \
3167	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3168
3169	# ifndef IN_RING0
3170	if (!(fPage & X86_PTE_US))
3171	{
3172	/*
3173	* Mark this page as safe.
3174	*/
3175	/** @todo not correct for pages that contain both code and data!! */
3176	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
3177	CSAMMarkPage(pVM, (RTRCPTR)GCPtrPage, true);
3178	}
3179	# endif
3180
3181	/*
3182	* Get guest PD and index.
3183	*/
3184	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3185	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3186	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3187	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
3188	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3189	unsigned iPDSrc = 0;
3190	X86PDPE PdpeSrc;
3191	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
3192
3193	if (pPDSrc)
3194	{
3195	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3196	return VINF_EM_RAW_GUEST_TRAP;
3197	}
3198	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3199	unsigned iPDSrc;
3200	PX86PML4E pPml4eSrc;
3201	X86PDPE PdpeSrc;
3202	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3203	if (!pPDSrc)
3204	{
3205	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3206	return VINF_EM_RAW_GUEST_TRAP;
3207	}
3208	# endif
3209	# else
3210	PGSTPD pPDSrc = NULL;
3211	const unsigned iPDSrc = 0;
3212	# endif
3213	int rc = VINF_SUCCESS;
3214
3215	pgmLock(pVM);
3216
3217	/*
3218	* First check if the shadow pd is present.
3219	*/
3220	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3221	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
3222	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3223	PX86PDEPAE pPdeDst;
3224	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3225	PX86PDPAE pPDDst;
3226	# if PGM_GST_TYPE != PGM_TYPE_PAE
3227	X86PDPE PdpeSrc;
3228
3229	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3230	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3231	# endif
3232	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, &PdpeSrc, &pPDDst);
3233	if (rc != VINF_SUCCESS)
3234	{
3235	pgmUnlock(pVM);
3236	AssertRC(rc);
3237	return rc;
3238	}
3239	Assert(pPDDst);
3240	pPdeDst = &pPDDst->a[iPDDst];
3241
3242	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3243	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3244	PX86PDPAE pPDDst;
3245	PX86PDEPAE pPdeDst;
3246
3247	# if PGM_GST_TYPE == PGM_TYPE_PROT
3248	/* AMD-V nested paging */
3249	X86PML4E Pml4eSrc;
3250	X86PDPE PdpeSrc;
3251	PX86PML4E pPml4eSrc = &Pml4eSrc;
3252
3253	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3254	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
3255	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
3256	# endif
3257
3258	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
3259	if (rc != VINF_SUCCESS)
3260	{
3261	pgmUnlock(pVM);
3262	AssertRC(rc);
3263	return rc;
3264	}
3265	Assert(pPDDst);
3266	pPdeDst = &pPDDst->a[iPDDst];
3267	# endif
3268
3269	# if defined(IN_RC)
3270	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3271	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
3272	# endif
3273
3274	if (!pPdeDst->n.u1Present)
3275	{
3276	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3277	if (rc != VINF_SUCCESS)
3278	{
3279	# if defined(IN_RC)
3280	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3281	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
3282	# endif
3283	pgmUnlock(pVM);
3284	AssertRC(rc);
3285	return rc;
3286	}
3287	}
3288
3289	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3290	/* Check for dirty bit fault */
3291	rc = PGM_BTH_NAME(CheckPageFault)(pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3292	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3293	Log(("PGMVerifyAccess: success (dirty)\n"));
3294	else
3295	{
3296	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3297	# else
3298	{
3299	GSTPDE PdeSrc;
3300	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
3301	PdeSrc.n.u1Present = 1;
3302	PdeSrc.n.u1Write = 1;
3303	PdeSrc.n.u1Accessed = 1;
3304	PdeSrc.n.u1User = 1;
3305
3306	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
3307	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3308	if (uErr & X86_TRAP_PF_US)
3309	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
3310	else /* supervisor */
3311	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3312
3313	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3314	if (RT_SUCCESS(rc))
3315	{
3316	/* Page was successfully synced */
3317	Log2(("PGMVerifyAccess: success (sync)\n"));
3318	rc = VINF_SUCCESS;
3319	}
3320	else
3321	{
3322	Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", GCPtrPage, rc));
3323	rc = VINF_EM_RAW_GUEST_TRAP;
3324	}
3325	}
3326	# if defined(IN_RC)
3327	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3328	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
3329	# endif
3330	pgmUnlock(pVM);
3331	return rc;
3332
3333	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3334
3335	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3336	return VERR_INTERNAL_ERROR;
3337	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3338	}
3339
3340
3341	#if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3342	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
3343	/**
3344	* Figures out which kind of shadow page this guest PDE warrants.
3345	*
3346	* @returns Shadow page kind.
3347	* @param pPdeSrc The guest PDE in question.
3348	* @param cr4 The current guest cr4 value.
3349	*/
3350	DECLINLINE(PGMPOOLKIND) PGM_BTH_NAME(CalcPageKind)(const GSTPDE *pPdeSrc, uint32_t cr4)
3351	{
3352	# if PMG_GST_TYPE == PGM_TYPE_AMD64
3353	if (!pPdeSrc->n.u1Size)
3354	# else
3355	if (!pPdeSrc->n.u1Size \|\| !(cr4 & X86_CR4_PSE))
3356	# endif
3357	return BTH_PGMPOOLKIND_PT_FOR_PT;
3358	//switch (pPdeSrc->u & (X86_PDE4M_RW \| X86_PDE4M_US /\| X86_PDE4M_PAE_NX/))
3359	//{
3360	// case 0:
3361	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RO;
3362	// case X86_PDE4M_RW:
3363	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW;
3364	// case X86_PDE4M_US:
3365	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US;
3366	// case X86_PDE4M_RW \| X86_PDE4M_US:
3367	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US;
3368	# if 0
3369	// case X86_PDE4M_PAE_NX:
3370	// return BTH_PGMPOOLKIND_PT_FOR_BIG_NX;
3371	// case X86_PDE4M_RW \| X86_PDE4M_PAE_NX:
3372	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_NX;
3373	// case X86_PDE4M_US \| X86_PDE4M_PAE_NX:
3374	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US_NX;
3375	// case X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PAE_NX:
3376	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US_NX;
3377	# endif
3378	return BTH_PGMPOOLKIND_PT_FOR_BIG;
3379	//}
3380	}
3381	# endif
3382	#endif
3383
3384	#undef MY_STAM_COUNTER_INC
3385	#define MY_STAM_COUNTER_INC(a) do { } while (0)
3386
3387
3388	/**
3389	* Syncs the paging hierarchy starting at CR3.
3390	*
3391	* @returns VBox status code, no specials.
3392	* @param pVCpu The VMCPU handle.
3393	* @param cr0 Guest context CR0 register
3394	* @param cr3 Guest context CR3 register
3395	* @param cr4 Guest context CR4 register
3396	* @param fGlobal Including global page directories or not
3397	*/
3398	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3399	{
3400	PVM pVM = pVCpu->CTX_SUFF(pVM);
3401
3402	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
3403	fGlobal = true; /* Change this CR3 reload to be a global one. */
3404
3405	LogFlow(("SyncCR3 %d\n", fGlobal));
3406
3407	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3408	/*
3409	* Update page access handlers.
3410	* The virtual are always flushed, while the physical are only on demand.
3411	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3412	* have to look into that later because it will have a bad influence on the performance.
3413	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3414	* bird: Yes, but that won't work for aliases.
3415	*/
3416	/** @todo this MUST go away. See #1557. */
3417	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3418	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3419	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3420	#endif
3421
3422	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3423	/*
3424	* Nested / EPT - almost no work.
3425	*/
3426	/** @todo check if this is really necessary; the call does it as well... */
3427	HWACCMFlushTLB(pVCpu);
3428	return VINF_SUCCESS;
3429
3430	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3431	/*
3432	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3433	* out the shadow parts when the guest modifies its tables.
3434	*/
3435	return VINF_SUCCESS;
3436
3437	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3438
3439	# ifdef PGM_WITHOUT_MAPPINGS
3440	Assert(pVM->pgm.s.fMappingsFixed);
3441	return VINF_SUCCESS;
3442	# else
3443	/* Nothing to do when mappings are fixed. */
3444	if (pVM->pgm.s.fMappingsFixed)
3445	return VINF_SUCCESS;
3446
3447	int rc = PGMMapResolveConflicts(pVM);
3448	Assert(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3);
3449	if (rc == VINF_PGM_SYNC_CR3)
3450	{
3451	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3452	return VINF_PGM_SYNC_CR3;
3453	}
3454	# endif
3455	return VINF_SUCCESS;
3456	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3457	}
3458
3459
3460
3461
3462	#ifdef VBOX_STRICT
3463	#ifdef IN_RC
3464	# undef AssertMsgFailed
3465	# define AssertMsgFailed Log
3466	#endif
3467	#ifdef IN_RING3
3468	# include <VBox/dbgf.h>
3469
3470	/**
3471	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3472	*
3473	* @returns VBox status code (VINF_SUCCESS).
3474	* @param cr3 The root of the hierarchy.
3475	* @param crr The cr4, only PAE and PSE is currently used.
3476	* @param fLongMode Set if long mode, false if not long mode.
3477	* @param cMaxDepth Number of levels to dump.
3478	* @param pHlp Pointer to the output functions.
3479	*/
3480	__BEGIN_DECLS
3481	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
3482	__END_DECLS
3483
3484	#endif
3485
3486	/**
3487	* Checks that the shadow page table is in sync with the guest one.
3488	*
3489	* @returns The number of errors.
3490	* @param pVM The virtual machine.
3491	* @param pVCpu The VMCPU handle.
3492	* @param cr3 Guest context CR3 register
3493	* @param cr4 Guest context CR4 register
3494	* @param GCPtr Where to start. Defaults to 0.
3495	* @param cb How much to check. Defaults to everything.
3496	*/
3497	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3498	{
3499	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3500	return 0;
3501	#else
3502	unsigned cErrors = 0;
3503	PVM pVM = pVCpu->CTX_SUFF(pVM);
3504	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3505
3506	#if PGM_GST_TYPE == PGM_TYPE_PAE
3507	/** @todo currently broken; crashes below somewhere */
3508	AssertFailed();
3509	#endif
3510
3511	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
3512	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3513	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3514
3515	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3516	bool fBigPagesSupported = true;
3517	# else
3518	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
3519	# endif
3520	PPGMCPU pPGM = &pVCpu->pgm.s;
3521	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3522	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3523	# ifndef IN_RING0
3524	RTHCPHYS HCPhys; /* general usage. */
3525	# endif
3526	int rc;
3527
3528	/*
3529	* Check that the Guest CR3 and all its mappings are correct.
3530	*/
3531	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
3532	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3533	false);
3534	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3535	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3536	rc = PGMShwGetPage(pVCpu, (RTGCPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3537	# else
3538	rc = PGMShwGetPage(pVCpu, (RTGCPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3539	# endif
3540	AssertRCReturn(rc, 1);
3541	HCPhys = NIL_RTHCPHYS;
3542	rc = pgmRamGCPhys2HCPhys(&pVM->pgm.s, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
3543	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3544	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3545	pgmGstGet32bitPDPtr(pPGM);
3546	RTGCPHYS GCPhys;
3547	rc = PGMR3DbgR3Ptr2GCPhys(pVM, pPGM->pGst32BitPdR3, &GCPhys);
3548	AssertRCReturn(rc, 1);
3549	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3550	# endif
3551	# endif /* !IN_RING0 */
3552
3553	/*
3554	* Get and check the Shadow CR3.
3555	*/
3556	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3557	unsigned cPDEs = X86_PG_ENTRIES;
3558	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3559	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3560	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3561	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3562	# else
3563	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3564	# endif
3565	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3566	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3567	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3568	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3569	# endif
3570	if (cb != ~(RTGCPTR)0)
3571	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3572
3573	/** @todo call the other two PGMAssert() functions. /
3574
3575	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3576	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3577
3578	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3579	{
3580	PPGMPOOLPAGE pShwPdpt = NULL;
3581	PX86PML4E pPml4eSrc;
3582	PX86PML4E pPml4eDst;
3583	RTGCPHYS GCPhysPdptSrc;
3584
3585	pPml4eSrc = pgmGstGetLongModePML4EPtr(&pVCpu->pgm.s, iPml4);
3586	pPml4eDst = pgmShwGetLongModePML4EPtr(&pVCpu->pgm.s, iPml4);
3587
3588	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3589	if (!pPml4eDst->n.u1Present)
3590	{
3591	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3592	continue;
3593	}
3594
3595	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3596	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK_FULL;
3597
3598	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3599	{
3600	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3601	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3602	cErrors++;
3603	continue;
3604	}
3605
3606	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3607	{
3608	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3609	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3610	cErrors++;
3611	continue;
3612	}
3613
3614	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3615	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3616	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3617	{
3618	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3619	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3620	cErrors++;
3621	continue;
3622	}
3623	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3624	{
3625	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3626
3627	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3628	/*
3629	* Check the PDPTEs too.
3630	*/
3631	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3632
3633	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3634	{
3635	unsigned iPDSrc;
3636	PPGMPOOLPAGE pShwPde = NULL;
3637	PX86PDPE pPdpeDst;
3638	RTGCPHYS GCPhysPdeSrc;
3639	# if PGM_GST_TYPE == PGM_TYPE_PAE
3640	X86PDPE PdpeSrc;
3641	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtr, &iPDSrc, &PdpeSrc);
3642	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVCpu->pgm.s);
3643	# else
3644	PX86PML4E pPml4eSrc;
3645	X86PDPE PdpeSrc;
3646	PX86PDPT pPdptDst;
3647	PX86PDPAE pPDDst;
3648	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtr, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3649
3650	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
3651	if (rc != VINF_SUCCESS)
3652	{
3653	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3654	GCPtr += 512 * _2M;
3655	continue; /* next PDPTE */
3656	}
3657	Assert(pPDDst);
3658	# endif
3659	Assert(iPDSrc == 0);
3660
3661	pPdpeDst = &pPdptDst->a[iPdpt];
3662
3663	if (!pPdpeDst->n.u1Present)
3664	{
3665	GCPtr += 512 * _2M;
3666	continue; /* next PDPTE */
3667	}
3668
3669	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3670	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3671
3672	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3673	{
3674	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3675	GCPtr += 512 * _2M;
3676	cErrors++;
3677	continue;
3678	}
3679
3680	if (GCPhysPdeSrc != pShwPde->GCPhys)
3681	{
3682	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3683	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3684	# else
3685	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3686	# endif
3687	GCPtr += 512 * _2M;
3688	cErrors++;
3689	continue;
3690	}
3691
3692	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3693	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3694	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3695	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3696	{
3697	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3698	GCPtr += 512 * _2M;
3699	cErrors++;
3700	continue;
3701	}
3702	# endif
3703
3704	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3705	{
3706	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3707	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3708	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
3709	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3710	PCX86PD pPDDst = pgmShwGet32BitPDPtr(&pVCpu->pgm.s);
3711	# endif
3712	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3713	/*
3714	* Iterate the shadow page directory.
3715	*/
3716	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3717	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3718
3719	for (;
3720	iPDDst < cPDEs;
3721	iPDDst++, GCPtr += cIncrement)
3722	{
3723	# if PGM_SHW_TYPE == PGM_TYPE_PAE
3724	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pPGM, GCPtr);
3725	# else
3726	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3727	# endif
3728	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3729	{
3730	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3731	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3732	{
3733	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3734	cErrors++;
3735	continue;
3736	}
3737	}
3738	else if ( (PdeDst.u & X86_PDE_P)
3739	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3740	)
3741	{
3742	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3743	PPGMPOOLPAGE pPoolPage = pgmPoolGetPage(pPool, HCPhysShw);
3744	if (!pPoolPage)
3745	{
3746	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
3747	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3748	cErrors++;
3749	continue;
3750	}
3751	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR(pVM, pPoolPage);
3752
3753	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3754	{
3755	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
3756	GCPtr, (uint64_t)PdeDst.u));
3757	cErrors++;
3758	}
3759
3760	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3761	{
3762	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
3763	GCPtr, (uint64_t)PdeDst.u));
3764	cErrors++;
3765	}
3766
3767	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3768	if (!PdeSrc.n.u1Present)
3769	{
3770	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3771	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3772	cErrors++;
3773	continue;
3774	}
3775
3776	if ( !PdeSrc.b.u1Size
3777	\|\| !fBigPagesSupported)
3778	{
3779	GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
3780	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3781	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3782	# endif
3783	}
3784	else
3785	{
3786	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3787	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3788	{
3789	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3790	GCPtr, (uint64_t)PdeSrc.u));
3791	cErrors++;
3792	continue;
3793	}
3794	# endif
3795	GCPhysGst = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
3796	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3797	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3798	# endif
3799	}
3800
3801	if ( pPoolPage->enmKind
3802	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3803	{
3804	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
3805	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3806	cErrors++;
3807	}
3808
3809	PPGMPAGE pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
3810	if (!pPhysPage)
3811	{
3812	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3813	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3814	cErrors++;
3815	continue;
3816	}
3817
3818	if (GCPhysGst != pPoolPage->GCPhys)
3819	{
3820	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
3821	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3822	cErrors++;
3823	continue;
3824	}
3825
3826	if ( !PdeSrc.b.u1Size
3827	\|\| !fBigPagesSupported)
3828	{
3829	/*
3830	* Page Table.
3831	*/
3832	const GSTPT *pPTSrc;
3833	rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3834	if (RT_FAILURE(rc))
3835	{
3836	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3837	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3838	cErrors++;
3839	continue;
3840	}
3841	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3842	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3843	{
3844	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3845	// (This problem will go away when/if we shadow multiple CR3s.)
3846	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3847	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3848	cErrors++;
3849	continue;
3850	}
3851	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3852	{
3853	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
3854	GCPtr, (uint64_t)PdeDst.u));
3855	cErrors++;
3856	continue;
3857	}
3858
3859	/* iterate the page table. */
3860	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3861	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3862	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3863	# else
3864	const unsigned offPTSrc = 0;
3865	# endif
3866	for (unsigned iPT = 0, off = 0;
3867	iPT < RT_ELEMENTS(pPTDst->a);
3868	iPT++, off += PAGE_SIZE)
3869	{
3870	const SHWPTE PteDst = pPTDst->a[iPT];
3871
3872	/* skip not-present entries. */
3873	if (!(PteDst.u & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3874	continue;
3875	Assert(PteDst.n.u1Present);
3876
3877	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3878	if (!PteSrc.n.u1Present)
3879	{
3880	# ifdef IN_RING3
3881	PGMAssertHandlerAndFlagsInSync(pVM);
3882	PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
3883	# endif
3884	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
3885	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3886	(PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
3887	cErrors++;
3888	continue;
3889	}
3890
3891	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3892	# if 1 /** @todo sync accessed bit properly... */
3893	fIgnoreFlags \|= X86_PTE_A;
3894	# endif
3895
3896	/* match the physical addresses */
3897	HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
3898	GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
3899
3900	# ifdef IN_RING3
3901	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3902	if (RT_FAILURE(rc))
3903	{
3904	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
3905	{
3906	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3907	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3908	cErrors++;
3909	continue;
3910	}
3911	}
3912	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
3913	{
3914	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3915	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3916	cErrors++;
3917	continue;
3918	}
3919	# endif
3920
3921	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
3922	if (!pPhysPage)
3923	{
3924	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3925	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
3926	{
3927	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3928	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3929	cErrors++;
3930	continue;
3931	}
3932	# endif
3933	if (PteDst.n.u1Write)
3934	{
3935	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3936	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3937	cErrors++;
3938	}
3939	fIgnoreFlags \|= X86_PTE_RW;
3940	}
3941	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
3942	{
3943	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3944	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3945	cErrors++;
3946	continue;
3947	}
3948
3949	/* flags */
3950	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
3951	{
3952	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
3953	{
3954	if (PteDst.n.u1Write)
3955	{
3956	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
3957	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3958	cErrors++;
3959	continue;
3960	}
3961	fIgnoreFlags \|= X86_PTE_RW;
3962	}
3963	else
3964	{
3965	if (PteDst.n.u1Present)
3966	{
3967	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
3968	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3969	cErrors++;
3970	continue;
3971	}
3972	fIgnoreFlags \|= X86_PTE_P;
3973	}
3974	}
3975	else
3976	{
3977	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
3978	{
3979	if (PteDst.n.u1Write)
3980	{
3981	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
3982	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3983	cErrors++;
3984	continue;
3985	}
3986	if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
3987	{
3988	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3989	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3990	cErrors++;
3991	continue;
3992	}
3993	if (PteDst.n.u1Dirty)
3994	{
3995	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3996	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3997	cErrors++;
3998	}
3999	# if 0 /** @todo sync access bit properly... */
4000	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4001	{
4002	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4003	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4004	cErrors++;
4005	}
4006	fIgnoreFlags \|= X86_PTE_RW;
4007	# else
4008	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4009	# endif
4010	}
4011	else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4012	{
4013	/* access bit emulation (not implemented). */
4014	if (PteSrc.n.u1Accessed \|\| PteDst.n.u1Present)
4015	{
4016	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4017	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4018	cErrors++;
4019	continue;
4020	}
4021	if (!PteDst.n.u1Accessed)
4022	{
4023	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4024	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4025	cErrors++;
4026	}
4027	fIgnoreFlags \|= X86_PTE_P;
4028	}
4029	# ifdef DEBUG_sandervl
4030	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4031	# endif
4032	}
4033
4034	if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4035	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
4036	)
4037	{
4038	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4039	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4040	fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4041	cErrors++;
4042	continue;
4043	}
4044	} /* foreach PTE */
4045	}
4046	else
4047	{
4048	/*
4049	* Big Page.
4050	*/
4051	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4052	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4053	{
4054	if (PdeDst.n.u1Write)
4055	{
4056	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4057	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4058	cErrors++;
4059	continue;
4060	}
4061	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4062	{
4063	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4064	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4065	cErrors++;
4066	continue;
4067	}
4068	# if 0 /** @todo sync access bit properly... */
4069	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4070	{
4071	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4072	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4073	cErrors++;
4074	}
4075	fIgnoreFlags \|= X86_PTE_RW;
4076	# else
4077	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4078	# endif
4079	}
4080	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4081	{
4082	/* access bit emulation (not implemented). */
4083	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4084	{
4085	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4086	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4087	cErrors++;
4088	continue;
4089	}
4090	if (!PdeDst.n.u1Accessed)
4091	{
4092	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4093	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4094	cErrors++;
4095	}
4096	fIgnoreFlags \|= X86_PTE_P;
4097	}
4098
4099	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4100	{
4101	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4102	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4103	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4104	cErrors++;
4105	}
4106
4107	/* iterate the page table. */
4108	for (unsigned iPT = 0, off = 0;
4109	iPT < RT_ELEMENTS(pPTDst->a);
4110	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
4111	{
4112	const SHWPTE PteDst = pPTDst->a[iPT];
4113
4114	if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4115	{
4116	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4117	GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4118	cErrors++;
4119	}
4120
4121	/* skip not-present entries. */
4122	if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
4123	continue;
4124
4125	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4126
4127	/* match the physical addresses */
4128	HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
4129
4130	# ifdef IN_RING3
4131	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4132	if (RT_FAILURE(rc))
4133	{
4134	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4135	{
4136	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4137	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4138	cErrors++;
4139	}
4140	}
4141	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4142	{
4143	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4144	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4145	cErrors++;
4146	continue;
4147	}
4148	# endif
4149	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
4150	if (!pPhysPage)
4151	{
4152	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4153	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4154	{
4155	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4156	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4157	cErrors++;
4158	continue;
4159	}
4160	# endif
4161	if (PteDst.n.u1Write)
4162	{
4163	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4164	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4165	cErrors++;
4166	}
4167	fIgnoreFlags \|= X86_PTE_RW;
4168	}
4169	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4170	{
4171	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4172	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4173	cErrors++;
4174	continue;
4175	}
4176
4177	/* flags */
4178	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4179	{
4180	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4181	{
4182	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4183	{
4184	if (PteDst.n.u1Write)
4185	{
4186	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4187	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4188	cErrors++;
4189	continue;
4190	}
4191	fIgnoreFlags \|= X86_PTE_RW;
4192	}
4193	}
4194	else
4195	{
4196	if (PteDst.n.u1Present)
4197	{
4198	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4199	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4200	cErrors++;
4201	continue;
4202	}
4203	fIgnoreFlags \|= X86_PTE_P;
4204	}
4205	}
4206
4207	if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4208	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
4209	)
4210	{
4211	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4212	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4213	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4214	cErrors++;
4215	continue;
4216	}
4217	} /* for each PTE */
4218	}
4219	}
4220	/* not present */
4221
4222	} /* for each PDE */
4223
4224	} /* for each PDPTE */
4225
4226	} /* for each PML4E */
4227
4228	# ifdef DEBUG
4229	if (cErrors)
4230	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4231	# endif
4232
4233	#endif /* GST == 32BIT, PAE or AMD64 */
4234	return cErrors;
4235
4236	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4237	}
4238	#endif /* VBOX_STRICT */
4239
4240
4241	/**
4242	* Sets up the CR3 for shadow paging
4243	*
4244	* @returns Strict VBox status code.
4245	* @retval VINF_SUCCESS.
4246	*
4247	* @param pVCpu The VMCPU handle.
4248	* @param GCPhysCR3 The physical address in the CR3 register.
4249	*/
4250	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3)
4251	{
4252	PVM pVM = pVCpu->CTX_SUFF(pVM);
4253
4254	/* Update guest paging info. */
4255	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4256	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4257	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4258
4259	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4260
4261	/*
4262	* Map the page CR3 points at.
4263	*/
4264	RTHCPTR HCPtrGuestCR3;
4265	RTHCPHYS HCPhysGuestCR3;
4266	pgmLock(pVM);
4267	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysCR3);
4268	AssertReturn(pPage, VERR_INTERNAL_ERROR_2);
4269	HCPhysGuestCR3 = PGM_PAGE_GET_HCPHYS(pPage);
4270	/** @todo this needs some reworking wrt. locking. */
4271	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4272	HCPtrGuestCR3 = NIL_RTHCPTR;
4273	int rc = VINF_SUCCESS;
4274	# else
4275	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhysCR3 & GST_CR3_PAGE_MASK, (void **)&HCPtrGuestCR3);
4276	# endif
4277	pgmUnlock(pVM);
4278	if (RT_SUCCESS(rc))
4279	{
4280	rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
4281	if (RT_SUCCESS(rc))
4282	{
4283	# ifdef IN_RC
4284	PGM_INVL_PG(pVCpu, pVM->pgm.s.GCPtrCR3Mapping);
4285	# endif
4286	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4287	pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
4288	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4289	pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
4290	# endif
4291	pVCpu->pgm.s.pGst32BitPdRC = (RCPTRTYPE(PX86PD))pVM->pgm.s.GCPtrCR3Mapping;
4292
4293	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4294	unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
4295	pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4296	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4297	pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4298	# endif
4299	pVCpu->pgm.s.pGstPaePdptRC = (RCPTRTYPE(PX86PDPT))((RCPTRTYPE(uint8_t *))pVM->pgm.s.GCPtrCR3Mapping + off);
4300	Log(("Cached mapping %RRv\n", pVCpu->pgm.s.pGstPaePdptRC));
4301
4302	/*
4303	* Map the 4 PDs too.
4304	*/
4305	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(&pVCpu->pgm.s);
4306	RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
4307	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
4308	{
4309	if (pGuestPDPT->a[i].n.u1Present)
4310	{
4311	RTHCPTR HCPtr;
4312	RTHCPHYS HCPhys;
4313	RTGCPHYS GCPhys = pGuestPDPT->a[i].u & X86_PDPE_PG_MASK;
4314	pgmLock(pVM);
4315	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
4316	AssertReturn(pPage, VERR_INTERNAL_ERROR_2);
4317	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
4318	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4319	HCPtr = NIL_RTHCPTR;
4320	int rc2 = VINF_SUCCESS;
4321	# else
4322	int rc2 = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, (void **)&HCPtr);
4323	# endif
4324	pgmUnlock(pVM);
4325	if (RT_SUCCESS(rc2))
4326	{
4327	rc = PGMMap(pVM, GCPtr, HCPhys, PAGE_SIZE, 0);
4328	AssertRCReturn(rc, rc);
4329
4330	pVCpu->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
4331	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4332	pVCpu->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
4333	# endif
4334	pVCpu->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))GCPtr;
4335	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
4336	# ifdef IN_RC
4337	PGM_INVL_PG(pVCpu, GCPtr);
4338	# endif
4339	continue;
4340	}
4341	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
4342	}
4343
4344	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4345	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4346	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4347	# endif
4348	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4349	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4350	# ifdef IN_RC
4351	PGM_INVL_PG(pVCpu, GCPtr); /** @todo this shouldn't be necessary? */
4352	# endif
4353	}
4354
4355	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4356	pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
4357	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4358	pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
4359	# endif
4360	# endif
4361	}
4362	else
4363	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4364	}
4365	else
4366	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4367
4368	#else /* prot/real stub */
4369	int rc = VINF_SUCCESS;
4370	#endif
4371
4372	/* Update shadow paging info for guest modes with paging (32, pae, 64). */
4373	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4374	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4375	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4376	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
4377	&& PGM_GST_TYPE != PGM_TYPE_PROT))
4378
4379	Assert(!HWACCMIsNestedPagingActive(pVM));
4380
4381	/*
4382	* Update the shadow root page as well since that's not fixed.
4383	*/
4384	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4385	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
4386	uint32_t iOldShwUserTable = pVCpu->pgm.s.iShwUserTable;
4387	uint32_t iOldShwUser = pVCpu->pgm.s.iShwUser;
4388	PPGMPOOLPAGE pNewShwPageCR3;
4389
4390	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4391	rc = pgmPoolAlloc(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, SHW_POOL_ROOT_IDX, GCPhysCR3 >> PAGE_SHIFT, &pNewShwPageCR3);
4392	AssertFatalRC(rc);
4393	rc = VINF_SUCCESS;
4394
4395	/* Mark the page as locked; disallow flushing. */
4396	pgmPoolLockPage(pPool, pNewShwPageCR3);
4397
4398	# ifdef IN_RC
4399	/* NOTE: We can't deal with jumps to ring 3 here as we're now in an inconsistent state! */
4400	bool fLog = VMMGCLogDisable(pVM);
4401	pgmLock(pVM);
4402	# endif
4403
4404	pVCpu->pgm.s.iShwUser = SHW_POOL_ROOT_IDX;
4405	pVCpu->pgm.s.iShwUserTable = GCPhysCR3 >> PAGE_SHIFT;
4406	pVCpu->pgm.s.CTX_SUFF(pShwPageCR3) = pNewShwPageCR3;
4407	# ifdef IN_RING0
4408	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4409	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4410	# elif defined(IN_RC)
4411	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4412	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4413	# else
4414	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4415	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4416	# endif
4417
4418	# ifndef PGM_WITHOUT_MAPPINGS
4419	/*
4420	* Apply all hypervisor mappings to the new CR3.
4421	* Note that SyncCR3 will be executed in case CR3 is changed in a guest paging mode; this will
4422	* make sure we check for conflicts in the new CR3 root.
4423	*/
4424	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4425	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL) \|\| VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4426	# endif
4427	rc = pgmMapActivateCR3(pVM, pNewShwPageCR3);
4428	AssertRCReturn(rc, rc);
4429	# endif
4430
4431	/* Set the current hypervisor CR3. */
4432	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
4433	SELMShadowCR3Changed(pVM, pVCpu);
4434
4435	# ifdef IN_RC
4436	pgmUnlock(pVM);
4437	VMMGCLogRestore(pVM, fLog);
4438	# endif
4439
4440	/* Clean up the old CR3 root. */
4441	if (pOldShwPageCR3)
4442	{
4443	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
4444	# ifndef PGM_WITHOUT_MAPPINGS
4445	/* Remove the hypervisor mappings from the shadow page table. */
4446	pgmMapDeactivateCR3(pVM, pOldShwPageCR3);
4447	# endif
4448	/* Mark the page as unlocked; allow flushing again. */
4449	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
4450
4451	pgmPoolFreeByPage(pPool, pOldShwPageCR3, iOldShwUser, iOldShwUserTable);
4452	}
4453
4454	# endif
4455
4456	return rc;
4457	}
4458
4459	/**
4460	* Unmaps the shadow CR3.
4461	*
4462	* @returns VBox status, no specials.
4463	* @param pVCpu The VMCPU handle.
4464	*/
4465	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu)
4466	{
4467	LogFlow(("UnmapCR3\n"));
4468
4469	int rc = VINF_SUCCESS;
4470	PVM pVM = pVCpu->CTX_SUFF(pVM);
4471
4472	/*
4473	* Update guest paging info.
4474	*/
4475	#if PGM_GST_TYPE == PGM_TYPE_32BIT
4476	pVCpu->pgm.s.pGst32BitPdR3 = 0;
4477	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4478	pVCpu->pgm.s.pGst32BitPdR0 = 0;
4479	# endif
4480	pVCpu->pgm.s.pGst32BitPdRC = 0;
4481
4482	#elif PGM_GST_TYPE == PGM_TYPE_PAE
4483	pVCpu->pgm.s.pGstPaePdptR3 = 0;
4484	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4485	pVCpu->pgm.s.pGstPaePdptR0 = 0;
4486	# endif
4487	pVCpu->pgm.s.pGstPaePdptRC = 0;
4488	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4489	{
4490	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4491	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4492	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4493	# endif
4494	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4495	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4496	}
4497
4498	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4499	pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
4500	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4501	pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
4502	# endif
4503
4504	#else /* prot/real mode stub */
4505	/* nothing to do */
4506	#endif
4507
4508	#if !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
4509	/*
4510	* Update shadow paging info.
4511	*/
4512	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4513	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4514	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
4515
4516	# if PGM_GST_TYPE != PGM_TYPE_REAL
4517	Assert(!HWACCMIsNestedPagingActive(pVM));
4518	# endif
4519
4520	# ifndef PGM_WITHOUT_MAPPINGS
4521	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4522	/* Remove the hypervisor mappings from the shadow page table. */
4523	pgmMapDeactivateCR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4524	# endif
4525
4526	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4527	{
4528	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4529
4530	Assert(pVCpu->pgm.s.iShwUser != PGMPOOL_IDX_NESTED_ROOT);
4531
4532	/* Mark the page as unlocked; allow flushing again. */
4533	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4534
4535	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), pVCpu->pgm.s.iShwUser, pVCpu->pgm.s.iShwUserTable);
4536	pVCpu->pgm.s.pShwPageCR3R3 = 0;
4537	pVCpu->pgm.s.pShwPageCR3R0 = 0;
4538	pVCpu->pgm.s.pShwPageCR3RC = 0;
4539	pVCpu->pgm.s.iShwUser = 0;
4540	pVCpu->pgm.s.iShwUserTable = 0;
4541	}
4542	# endif
4543	#endif /* !IN_RC*/
4544
4545	return rc;
4546	}
4547

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 20125

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