PGMAllBth.h@ 27254

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1	/* $Id: PGMAllBth.h 27210 2010-03-09 12:37:34Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* This file is a big challenge!
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.alldomusa.eu.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*
19	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
20	* Clara, CA 95054 USA or visit http://www.sun.com if you need
21	* additional information or have any questions.
22	*/
23
24	/*******************************************************************************
25	* Internal Functions *
26	*******************************************************************************/
27	RT_C_DECLS_BEGIN
28	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken);
29	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
30	PGM_BTH_DECL(int, SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
31	PGM_BTH_DECL(int, CheckPageFault)(PVMCPU pVCpu, uint32_t uErr, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage);
32	PGM_BTH_DECL(int, CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage);
33	PGM_BTH_DECL(int, SyncPT)(PVMCPU pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
34	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
35	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
36	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
37	#ifdef VBOX_STRICT
38	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
39	#endif
40	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
41	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
42	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu);
43	RT_C_DECLS_END
44
45
46	/* Filter out some illegal combinations of guest and shadow paging, so we can remove redundant checks inside functions. */
47	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
48	# error "Invalid combination; PAE guest implies PAE shadow"
49	#endif
50
51	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
52	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
53	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
54	#endif
55
56	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
57	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
58	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
59	#endif
60
61	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
62	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
63	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
64	#endif
65
66
67	#ifndef IN_RING3
68	/**
69	* #PF Handler for raw-mode guest execution.
70	*
71	* @returns VBox status code (appropriate for trap handling and GC return).
72	*
73	* @param pVCpu VMCPU Handle.
74	* @param uErr The trap error code.
75	* @param pRegFrame Trap register frame.
76	* @param pvFault The fault address.
77	* @param pfLockTaken PGM lock taken here or not (out)
78	*/
79	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken)
80	{
81	PVM pVM = pVCpu->CTX_SUFF(pVM);
82
83	*pfLockTaken = false;
84
85	# if defined(IN_RC) && defined(VBOX_STRICT)
86	PGMDynCheckLocks(pVM);
87	# endif
88
89	# if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
90	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
91	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
92
93	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_PAE
94	/*
95	* Hide the instruction fetch trap indicator for now.
96	*/
97	/** @todo NXE will change this and we must fix NXE in the switcher too! */
98	if (uErr & X86_TRAP_PF_ID)
99	{
100	uErr &= ~X86_TRAP_PF_ID;
101	TRPMSetErrorCode(pVCpu, uErr);
102	}
103	# endif
104
105	/*
106	* Get PDs.
107	*/
108	int rc;
109	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
110	# if PGM_GST_TYPE == PGM_TYPE_32BIT
111	const unsigned iPDSrc = pvFault >> GST_PD_SHIFT;
112	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
113
114	# elif PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
115
116	# if PGM_GST_TYPE == PGM_TYPE_PAE
117	unsigned iPDSrc = 0; /* initialized to shut up gcc */
118	X86PDPE PdpeSrc;
119	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, pvFault, &iPDSrc, &PdpeSrc);
120
121	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
122	unsigned iPDSrc = 0; /* initialized to shut up gcc */
123	PX86PML4E pPml4eSrc;
124	X86PDPE PdpeSrc;
125	PGSTPD pPDSrc;
126
127	pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, pvFault, &pPml4eSrc, &PdpeSrc, &iPDSrc);
128	Assert(pPml4eSrc);
129	# endif
130
131	/* Quick check for a valid guest trap. (PAE & AMD64) */
132	if (!pPDSrc)
133	{
134	# if PGM_GST_TYPE == PGM_TYPE_AMD64 && GC_ARCH_BITS == 64
135	LogFlow(("Trap0eHandler: guest PML4 %d not present CR3=%RGp\n", (int)((pvFault >> X86_PML4_SHIFT) & X86_PML4_MASK), CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK));
136	# else
137	LogFlow(("Trap0eHandler: guest iPDSrc=%u not present CR3=%RGp\n", iPDSrc, CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK));
138	# endif
139	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2GuestTrap; });
140	TRPMSetErrorCode(pVCpu, uErr);
141	return VINF_EM_RAW_GUEST_TRAP;
142	}
143	# endif
144
145	# else /* !PGM_WITH_PAGING */
146	PGSTPD pPDSrc = NULL;
147	const unsigned iPDSrc = 0;
148	# endif /* !PGM_WITH_PAGING */
149
150	/* First check for a genuine guest page fault. */
151	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
152	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
153	rc = PGM_BTH_NAME(CheckPageFault)(pVCpu, uErr, &pPDSrc->a[iPDSrc], pvFault);
154	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
155	if (rc == VINF_EM_RAW_GUEST_TRAP)
156	{
157	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
158	= &pVCpu->pgm.s.StatRZTrap0eTime2GuestTrap; });
159	return rc;
160	}
161	# endif /* PGM_WITH_PAGING */
162
163	/* Take the big lock now. */
164	*pfLockTaken = true;
165	pgmLock(pVM);
166
167	/* Fetch the guest PDE */
168	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
169	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
170	# else
171	GSTPDE PdeSrc;
172	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
173	PdeSrc.n.u1Present = 1;
174	PdeSrc.n.u1Write = 1;
175	PdeSrc.n.u1Accessed = 1;
176	PdeSrc.n.u1User = 1;
177	# endif
178
179	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
180	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
181	PX86PD pPDDst = pgmShwGet32BitPDPtr(&pVCpu->pgm.s);
182
183	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
184	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
185
186	PX86PDPAE pPDDst;
187	# if PGM_GST_TYPE != PGM_TYPE_PAE
188	X86PDPE PdpeSrc;
189
190	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
191	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
192	# endif
193	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, &PdpeSrc, &pPDDst);
194	if (rc != VINF_SUCCESS)
195	{
196	AssertRC(rc);
197	return rc;
198	}
199	Assert(pPDDst);
200
201	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
202	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
203	PX86PDPAE pPDDst;
204	# if PGM_GST_TYPE == PGM_TYPE_PROT
205	/* AMD-V nested paging */
206	X86PML4E Pml4eSrc;
207	X86PDPE PdpeSrc;
208	PX86PML4E pPml4eSrc = &Pml4eSrc;
209
210	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
211	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
212	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
213	# endif
214
215	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, pPml4eSrc, &PdpeSrc, &pPDDst);
216	if (rc != VINF_SUCCESS)
217	{
218	AssertRC(rc);
219	return rc;
220	}
221	Assert(pPDDst);
222
223	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
224	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
225	PEPTPD pPDDst;
226
227	rc = pgmShwGetEPTPDPtr(pVCpu, pvFault, NULL, &pPDDst);
228	if (rc != VINF_SUCCESS)
229	{
230	AssertRC(rc);
231	return rc;
232	}
233	Assert(pPDDst);
234	# endif
235
236	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
237	/* Dirty page handling. */
238	if (uErr & X86_TRAP_PF_RW) /* write fault? */
239	{
240	/*
241	* If we successfully correct the write protection fault due to dirty bit
242	* tracking, then return immediately.
243	*/
244	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
245	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], pvFault);
246	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
247	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
248	{
249	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
250	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVCpu->pgm.s.StatRZTrap0eTime2DirtyAndAccessed : &pVCpu->pgm.s.StatRZTrap0eTime2GuestTrap; });
251	LogBird(("Trap0eHandler: returns VINF_SUCCESS\n"));
252	return VINF_SUCCESS;
253	}
254	}
255
256	# if 0 /* rarely useful; leave for debugging. */
257	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
258	# endif
259	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
260
261	/*
262	* A common case is the not-present error caused by lazy page table syncing.
263	*
264	* It is IMPORTANT that we weed out any access to non-present shadow PDEs here
265	* so we can safely assume that the shadow PT is present when calling SyncPage later.
266	*
267	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
268	* of mapping conflict and defer to SyncCR3 in R3.
269	* (Again, we do NOT support access handlers for non-present guest pages.)
270	*
271	*/
272	Assert(PdeSrc.n.u1Present);
273	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
274	&& !pPDDst->a[iPDDst].n.u1Present
275	)
276	{
277	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2SyncPT; });
278	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeSyncPT, f);
279	LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
280	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, pvFault);
281	if (RT_SUCCESS(rc))
282	{
283	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeSyncPT, f);
284	return rc;
285	}
286	Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
287	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
288	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeSyncPT, f);
289	return VINF_PGM_SYNC_CR3;
290	}
291
292	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(PGM_WITHOUT_MAPPINGS)
293	/*
294	* Check if this address is within any of our mappings.
295	*
296	* This is very fast and it's gonna save us a bit of effort below and prevent
297	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
298	* (BTW, it's impossible to have physical access handlers in a mapping.)
299	*/
300	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
301	{
302	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
303	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
304	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
305	{
306	if (pvFault < pMapping->GCPtr)
307	break;
308	if (pvFault - pMapping->GCPtr < pMapping->cb)
309	{
310	/*
311	* The first thing we check is if we've got an undetected conflict.
312	*/
313	if (pgmMapAreMappingsFloating(&pVM->pgm.s))
314	{
315	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
316	while (iPT-- > 0)
317	if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
318	{
319	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eConflicts);
320	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
321	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
322	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
323	return VINF_PGM_SYNC_CR3;
324	}
325	}
326
327	/*
328	* Check if the fault address is in a virtual page access handler range.
329	*/
330	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
331	if ( pCur
332	&& pvFault - pCur->Core.Key < pCur->cb
333	&& uErr & X86_TRAP_PF_RW)
334	{
335	# ifdef IN_RC
336	STAM_PROFILE_START(&pCur->Stat, h);
337	pgmUnlock(pVM);
338	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
339	pgmLock(pVM);
340	STAM_PROFILE_STOP(&pCur->Stat, h);
341	# else
342	AssertFailed();
343	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
344	# endif
345	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersMapping);
346	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
347	return rc;
348	}
349
350	/*
351	* Pretend we're not here and let the guest handle the trap.
352	*/
353	TRPMSetErrorCode(pVCpu, uErr & ~X86_TRAP_PF_P);
354	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eGuestPFMapping);
355	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
356	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
357	return VINF_EM_RAW_GUEST_TRAP;
358	}
359	}
360	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
361	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
362	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
363
364	/*
365	* Check if this fault address is flagged for special treatment,
366	* which means we'll have to figure out the physical address and
367	* check flags associated with it.
368	*
369	* ASSUME that we can limit any special access handling to pages
370	* in page tables which the guest believes to be present.
371	*/
372	Assert(PdeSrc.n.u1Present);
373	{
374	RTGCPHYS GCPhys = NIL_RTGCPHYS;
375
376	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
377	if ( PdeSrc.b.u1Size
378	# if PGM_GST_TYPE == PGM_TYPE_32BIT
379	&& CPUMIsGuestPageSizeExtEnabled(pVCpu)
380	# endif
381	)
382	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc)
383	\| ((RTGCPHYS)pvFault & (GST_BIG_PAGE_OFFSET_MASK ^ PAGE_OFFSET_MASK));
384	else
385	{
386	PGSTPT pPTSrc;
387	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
388	if (RT_SUCCESS(rc))
389	{
390	unsigned iPTESrc = (pvFault >> GST_PT_SHIFT) & GST_PT_MASK;
391	if (pPTSrc->a[iPTESrc].n.u1Present)
392	GCPhys = pPTSrc->a[iPTESrc].u & GST_PTE_PG_MASK;
393	}
394	}
395	# else
396	/* No paging so the fault address is the physical address */
397	GCPhys = (RTGCPHYS)(pvFault & ~PAGE_OFFSET_MASK);
398	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
399
400	/*
401	* If we have a GC address we'll check if it has any flags set.
402	*/
403	if (GCPhys != NIL_RTGCPHYS)
404	{
405	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
406
407	PPGMPAGE pPage;
408	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
409	if (RT_SUCCESS(rc)) /** just handle the failure immediate (it returns) and make things easier to read. */
410	{
411	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
412	{
413	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
414	{
415	/*
416	* Physical page access handler.
417	*/
418	const RTGCPHYS GCPhysFault = GCPhys \| (pvFault & PAGE_OFFSET_MASK);
419	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhysFault);
420	if (pCur)
421	{
422	# ifdef PGM_SYNC_N_PAGES
423	/*
424	* If the region is write protected and we got a page not present fault, then sync
425	* the pages. If the fault was caused by a read, then restart the instruction.
426	* In case of write access continue to the GC write handler.
427	*
428	* ASSUMES that there is only one handler per page or that they have similar write properties.
429	*/
430	if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
431	&& !(uErr & X86_TRAP_PF_P))
432	{
433	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
434	if ( RT_FAILURE(rc)
435	\|\| !(uErr & X86_TRAP_PF_RW)
436	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
437	{
438	AssertRC(rc);
439	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersOutOfSync);
440	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
441	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
442	return rc;
443	}
444	}
445	# endif
446
447	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
448	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
449	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
450
451	# if defined(IN_RC) \|\| defined(IN_RING0)
452	if (pCur->CTX_SUFF(pfnHandler))
453	{
454	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
455	# ifdef IN_RING0
456	PFNPGMR0PHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
457	# else
458	PFNPGMRCPHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
459	# endif
460	bool fLeaveLock = (pfnHandler != pPool->CTX_SUFF(pfnAccessHandler));
461	void *pvUser = pCur->CTX_SUFF(pvUser);
462
463	STAM_PROFILE_START(&pCur->Stat, h);
464	if (fLeaveLock)
465	pgmUnlock(pVM); /* @todo: Not entirely safe. */
466
467	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pvUser);
468	if (fLeaveLock)
469	pgmLock(pVM);
470	# ifdef VBOX_WITH_STATISTICS
471	pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhysFault);
472	if (pCur)
473	STAM_PROFILE_STOP(&pCur->Stat, h);
474	# else
475	pCur = NULL; /* might be invalid by now. */
476	# endif
477
478	}
479	else
480	# endif
481	rc = VINF_EM_RAW_EMULATE_INSTR;
482
483	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersPhysical);
484	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
485	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndPhys; });
486	return rc;
487	}
488	}
489	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
490	else
491	{
492	# ifdef PGM_SYNC_N_PAGES
493	/*
494	* If the region is write protected and we got a page not present fault, then sync
495	* the pages. If the fault was caused by a read, then restart the instruction.
496	* In case of write access continue to the GC write handler.
497	*/
498	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
499	&& !(uErr & X86_TRAP_PF_P))
500	{
501	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
502	if ( RT_FAILURE(rc)
503	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
504	\|\| !(uErr & X86_TRAP_PF_RW))
505	{
506	AssertRC(rc);
507	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersOutOfSync);
508	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
509	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndVirt; });
510	return rc;
511	}
512	}
513	# endif
514	/*
515	* Ok, it's an virtual page access handler.
516	*
517	* Since it's faster to search by address, we'll do that first
518	* and then retry by GCPhys if that fails.
519	*/
520	/** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
521	/** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
522	* page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
523	*/
524	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
525	if (pCur)
526	{
527	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
528	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
529	\|\| !(uErr & X86_TRAP_PF_P)
530	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
531	("Unexpected trap for virtual handler: %RGv (phys=%RGp) pPage=%R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
532
533	if ( pvFault - pCur->Core.Key < pCur->cb
534	&& ( uErr & X86_TRAP_PF_RW
535	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
536	{
537	# ifdef IN_RC
538	STAM_PROFILE_START(&pCur->Stat, h);
539	pgmUnlock(pVM);
540	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
541	pgmLock(pVM);
542	STAM_PROFILE_STOP(&pCur->Stat, h);
543	# else
544	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
545	# endif
546	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersVirtual);
547	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
548	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndVirt; });
549	return rc;
550	}
551	/* Unhandled part of a monitored page */
552	}
553	else
554	{
555	/* Check by physical address. */
556	unsigned iPage;
557	rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + (pvFault & PAGE_OFFSET_MASK),
558	&pCur, &iPage);
559	Assert(RT_SUCCESS(rc) \|\| !pCur);
560	if ( pCur
561	&& ( uErr & X86_TRAP_PF_RW
562	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
563	{
564	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
565	# ifdef IN_RC
566	RTGCPTR off = (iPage << PAGE_SHIFT) + (pvFault & PAGE_OFFSET_MASK) - (pCur->Core.Key & PAGE_OFFSET_MASK);
567	Assert(off < pCur->cb);
568	STAM_PROFILE_START(&pCur->Stat, h);
569	pgmUnlock(pVM);
570	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, off);
571	pgmLock(pVM);
572	STAM_PROFILE_STOP(&pCur->Stat, h);
573	# else
574	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
575	# endif
576	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersVirtualByPhys);
577	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
578	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndVirt; });
579	return rc;
580	}
581	}
582	}
583	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
584
585	/*
586	* There is a handled area of the page, but this fault doesn't belong to it.
587	* We must emulate the instruction.
588	*
589	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
590	* we first check if this was a page-not-present fault for a page with only
591	* write access handlers. Restart the instruction if it wasn't a write access.
592	*/
593	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersUnhandled);
594
595	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
596	&& !(uErr & X86_TRAP_PF_P))
597	{
598	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
599	if ( RT_FAILURE(rc)
600	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
601	\|\| !(uErr & X86_TRAP_PF_RW))
602	{
603	AssertRC(rc);
604	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersOutOfSync);
605	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
606	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
607	return rc;
608	}
609	}
610
611	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
612	* It's writing to an unhandled part of the LDT page several million times.
613	*/
614	rc = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);
615	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
616	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
617	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndUnhandled; });
618	return rc;
619	} /* if any kind of handler */
620
621	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
622	if (uErr & X86_TRAP_PF_P)
623	{
624	/*
625	* The page isn't marked, but it might still be monitored by a virtual page access handler.
626	* (ASSUMES no temporary disabling of virtual handlers.)
627	*/
628	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
629	* we should correct both the shadow page table and physical memory flags, and not only check for
630	* accesses within the handler region but for access to pages with virtual handlers. */
631	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
632	if (pCur)
633	{
634	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
635	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
636	\|\| !(uErr & X86_TRAP_PF_P)
637	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
638	("Unexpected trap for virtual handler: %08X (phys=%08x) %R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
639
640	if ( pvFault - pCur->Core.Key < pCur->cb
641	&& ( uErr & X86_TRAP_PF_RW
642	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
643	{
644	# ifdef IN_RC
645	STAM_PROFILE_START(&pCur->Stat, h);
646	pgmUnlock(pVM);
647	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
648	pgmLock(pVM);
649	STAM_PROFILE_STOP(&pCur->Stat, h);
650	# else
651	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
652	# endif
653	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersVirtualUnmarked);
654	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
655	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndVirt; });
656	return rc;
657	}
658	}
659	}
660	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
661	}
662	else
663	{
664	/*
665	* When the guest accesses invalid physical memory (e.g. probing
666	* of RAM or accessing a remapped MMIO range), then we'll fall
667	* back to the recompiler to emulate the instruction.
668	*/
669	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
670	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersInvalid);
671	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
672	return VINF_EM_RAW_EMULATE_INSTR;
673	}
674
675	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
676
677	# ifdef PGM_OUT_OF_SYNC_IN_GC /** @todo remove this bugger. */
678	/*
679	* We are here only if page is present in Guest page tables and
680	* trap is not handled by our handlers.
681	*
682	* Check it for page out-of-sync situation.
683	*/
684	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
685
686	if (!(uErr & X86_TRAP_PF_P))
687	{
688	/*
689	* Page is not present in our page tables.
690	* Try to sync it!
691	* BTW, fPageShw is invalid in this branch!
692	*/
693	if (uErr & X86_TRAP_PF_US)
694	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
695	else /* supervisor */
696	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
697
698	# if defined(LOG_ENABLED) && !defined(IN_RING0)
699	RTGCPHYS GCPhys2;
700	uint64_t fPageGst2;
701	PGMGstGetPage(pVCpu, pvFault, &fPageGst2, &GCPhys2);
702	Log(("Page out of sync: %RGv eip=%08x PdeSrc.n.u1User=%d fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
703	pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
704	# endif /* LOG_ENABLED */
705
706	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
707	if (CPUMGetGuestCPL(pVCpu, pRegFrame) == 0)
708	{
709	uint64_t fPageGst;
710	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
711	if ( RT_SUCCESS(rc)
712	&& !(fPageGst & X86_PTE_US))
713	{
714	/* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
715	if ( pvFault == (RTGCPTR)pRegFrame->eip
716	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
717	# ifdef CSAM_DETECT_NEW_CODE_PAGES
718	\|\| ( !PATMIsPatchGCAddr(pVM, pRegFrame->eip)
719	&& CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)) /* any new code we encounter here */
720	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
721	)
722	{
723	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
724	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
725	if (rc != VINF_SUCCESS)
726	{
727	/*
728	* CSAM needs to perform a job in ring 3.
729	*
730	* Sync the page before going to the host context; otherwise we'll end up in a loop if
731	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
732	*/
733	LogFlow(("CSAM ring 3 job\n"));
734	int rc2 = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, 1, uErr);
735	AssertRC(rc2);
736
737	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
738	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2CSAM; });
739	return rc;
740	}
741	}
742	# ifdef CSAM_DETECT_NEW_CODE_PAGES
743	else if ( uErr == X86_TRAP_PF_RW
744	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
745	&& pRegFrame->ecx < 0x10000)
746	{
747	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
748	* to detect loading of new code pages.
749	*/
750
751	/*
752	* Decode the instruction.
753	*/
754	RTGCPTR PC;
755	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
756	if (rc == VINF_SUCCESS)
757	{
758	PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
759	uint32_t cbOp;
760	rc = EMInterpretDisasOneEx(pVM, pVCpu, PC, pRegFrame, pDis, &cbOp);
761
762	/* For now we'll restrict this to rep movsw/d instructions */
763	if ( rc == VINF_SUCCESS
764	&& pDis->pCurInstr->opcode == OP_MOVSWD
765	&& (pDis->prefix & PREFIX_REP))
766	{
767	CSAMMarkPossibleCodePage(pVM, pvFault);
768	}
769	}
770	}
771	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
772
773	/*
774	* Mark this page as safe.
775	*/
776	/** @todo not correct for pages that contain both code and data!! */
777	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
778	CSAMMarkPage(pVM, pvFault, true);
779	}
780	}
781	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
782	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
783	if (RT_SUCCESS(rc))
784	{
785	/* The page was successfully synced, return to the guest. */
786	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
787	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSync; });
788	return VINF_SUCCESS;
789	}
790	}
791	else /* uErr & X86_TRAP_PF_P: */
792	{
793	/*
794	* Write protected pages are make writable when the guest makes the first
795	* write to it. This happens for pages that are shared, write monitored
796	* and not yet allocated.
797	*
798	* Also, a side effect of not flushing global PDEs are out of sync pages due
799	* to physical monitored regions, that are no longer valid.
800	* Assume for now it only applies to the read/write flag.
801	*/
802	if (RT_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
803	{
804	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
805	{
806	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n",
807	GCPhys, pPage, pvFault, uErr));
808	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
809	if (rc != VINF_SUCCESS)
810	{
811	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
812	return rc;
813	}
814	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
815	return VINF_EM_NO_MEMORY;
816	}
817
818	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
819	/* Check to see if we need to emulate the instruction as X86_CR0_WP has been cleared. */
820	if ( CPUMGetGuestCPL(pVCpu, pRegFrame) == 0
821	&& ((CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG))
822	{
823	Assert((uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P));
824	uint64_t fPageGst;
825	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
826	if ( RT_SUCCESS(rc)
827	&& !(fPageGst & X86_PTE_RW))
828	{
829	rc = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);
830	if (RT_SUCCESS(rc))
831	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eWPEmulInRZ);
832	else
833	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eWPEmulToR3);
834	return rc;
835	}
836	AssertMsg(RT_SUCCESS(rc), ("Unexpected r/w page %RGv flag=%x rc=%Rrc\n", pvFault, (uint32_t)fPageGst, rc));
837	}
838	# endif
839	/// @todo count the above case; else
840	if (uErr & X86_TRAP_PF_US)
841	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUserWrite));
842	else /* supervisor */
843	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisorWrite));
844
845	/*
846	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
847	* page is not present, which is not true in this case.
848	*/
849	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, 1, uErr);
850	if (RT_SUCCESS(rc))
851	{
852	/*
853	* Page was successfully synced, return to guest.
854	* First invalidate the page as it might be in the TLB.
855	*/
856	# if PGM_SHW_TYPE == PGM_TYPE_EPT
857	HWACCMInvalidatePhysPage(pVM, (RTGCPHYS)pvFault);
858	# else
859	PGM_INVL_PG(pVCpu, pvFault);
860	# endif
861	# ifdef VBOX_STRICT
862	RTGCPHYS GCPhys2;
863	uint64_t fPageGst;
864	if (!HWACCMIsNestedPagingActive(pVM))
865	{
866	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys2);
867	AssertMsg(RT_SUCCESS(rc) && (fPageGst & X86_PTE_RW), ("rc=%d fPageGst=%RX64\n"));
868	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys2, (uint64_t)fPageGst));
869	}
870	uint64_t fPageShw;
871	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
872	AssertMsg((RT_SUCCESS(rc) && (fPageShw & X86_PTE_RW)) \|\| pVM->cCpus > 1 /* new monitor can be installed/page table flushed between the trap exit and PGMTrap0eHandler */, ("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw));
873	# endif /* VBOX_STRICT */
874	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
875	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndObs; });
876	return VINF_SUCCESS;
877	}
878	}
879
880	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
881	# ifdef VBOX_STRICT
882	/*
883	* Check for VMM page flags vs. Guest page flags consistency.
884	* Currently only for debug purposes.
885	*/
886	if (RT_SUCCESS(rc))
887	{
888	/* Get guest page flags. */
889	uint64_t fPageGst;
890	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
891	if (RT_SUCCESS(rc))
892	{
893	uint64_t fPageShw;
894	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
895
896	/*
897	* Compare page flags.
898	* Note: we have AVL, A, D bits desynched.
899	*/
900	AssertMsg((fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
901	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64\n", pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst));
902	}
903	else
904	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
905	}
906	else
907	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
908	# endif /* VBOX_STRICT */
909	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
910	}
911	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
912	# endif /* PGM_OUT_OF_SYNC_IN_GC */
913	}
914	else /* GCPhys == NIL_RTGCPHYS */
915	{
916	/*
917	* Page not present in Guest OS or invalid page table address.
918	* This is potential virtual page access handler food.
919	*
920	* For the present we'll say that our access handlers don't
921	* work for this case - we've already discarded the page table
922	* not present case which is identical to this.
923	*
924	* When we perchance find we need this, we will probably have AVL
925	* trees (offset based) to operate on and we can measure their speed
926	* agains mapping a page table and probably rearrange this handling
927	* a bit. (Like, searching virtual ranges before checking the
928	* physical address.)
929	*/
930	}
931	}
932
933	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
934	/*
935	* Conclusion, this is a guest trap.
936	*/
937	LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
938	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eGuestPFUnh);
939	return VINF_EM_RAW_GUEST_TRAP;
940	# else
941	/* present, but not a monitored page; perhaps the guest is probing physical memory */
942	return VINF_EM_RAW_EMULATE_INSTR;
943	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
944
945
946	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
947
948	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
949	return VERR_INTERNAL_ERROR;
950	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
951	}
952	#endif /* !IN_RING3 */
953
954
955	/**
956	* Emulation of the invlpg instruction.
957	*
958	*
959	* @returns VBox status code.
960	*
961	* @param pVCpu The VMCPU handle.
962	* @param GCPtrPage Page to invalidate.
963	*
964	* @remark ASSUMES that the guest is updating before invalidating. This order
965	* isn't required by the CPU, so this is speculative and could cause
966	* trouble.
967	* @remark No TLB shootdown is done on any other VCPU as we assume that
968	* invlpg emulation is the only reason for calling this function.
969	* (The guest has to shoot down TLB entries on other CPUs itself)
970	* Currently true, but keep in mind!
971	*
972	* @todo Clean this up! Most of it is (or should be) no longer necessary as we catch all page table accesses.
973	*/
974	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
975	{
976	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
977	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
978	&& PGM_SHW_TYPE != PGM_TYPE_EPT
979	int rc;
980	PVM pVM = pVCpu->CTX_SUFF(pVM);
981	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
982
983	Assert(PGMIsLockOwner(pVM));
984
985	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
986
987	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
988	if (pPool->cDirtyPages)
989	pgmPoolResetDirtyPages(pVM);
990	# endif
991
992	/*
993	* Get the shadow PD entry and skip out if this PD isn't present.
994	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
995	*/
996	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
997	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
998	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
999
1000	/* Fetch the pgm pool shadow descriptor. */
1001	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1002	Assert(pShwPde);
1003
1004	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1005	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
1006	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVCpu->pgm.s);
1007
1008	/* If the shadow PDPE isn't present, then skip the invalidate. */
1009	if (!pPdptDst->a[iPdpt].n.u1Present)
1010	{
1011	Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
1012	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1013	return VINF_SUCCESS;
1014	}
1015
1016	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1017	PPGMPOOLPAGE pShwPde = NULL;
1018	PX86PDPAE pPDDst;
1019
1020	/* Fetch the pgm pool shadow descriptor. */
1021	rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
1022	AssertRCSuccessReturn(rc, rc);
1023	Assert(pShwPde);
1024
1025	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
1026	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1027
1028	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1029	/* PML4 */
1030	const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
1031	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1032	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1033	PX86PDPAE pPDDst;
1034	PX86PDPT pPdptDst;
1035	PX86PML4E pPml4eDst;
1036	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
1037	if (rc != VINF_SUCCESS)
1038	{
1039	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
1040	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1041	return VINF_SUCCESS;
1042	}
1043	Assert(pPDDst);
1044
1045	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1046	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
1047
1048	if (!pPdpeDst->n.u1Present)
1049	{
1050	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1051	return VINF_SUCCESS;
1052	}
1053
1054	/* Fetch the pgm pool shadow descriptor. */
1055	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1056	Assert(pShwPde);
1057
1058	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1059
1060	const SHWPDE PdeDst = *pPdeDst;
1061	if (!PdeDst.n.u1Present)
1062	{
1063	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1064	return VINF_SUCCESS;
1065	}
1066
1067	# if defined(IN_RC)
1068	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1069	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
1070	# endif
1071
1072	/*
1073	* Get the guest PD entry and calc big page.
1074	*/
1075	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1076	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
1077	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
1078	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1079	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1080	unsigned iPDSrc = 0;
1081	# if PGM_GST_TYPE == PGM_TYPE_PAE
1082	X86PDPE PdpeSrc;
1083	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
1084	# else /* AMD64 */
1085	PX86PML4E pPml4eSrc;
1086	X86PDPE PdpeSrc;
1087	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
1088	# endif
1089	GSTPDE PdeSrc;
1090
1091	if (pPDSrc)
1092	PdeSrc = pPDSrc->a[iPDSrc];
1093	else
1094	PdeSrc.u = 0;
1095	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1096
1097	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1098	const bool fIsBigPage = PdeSrc.b.u1Size && CPUMIsGuestPageSizeExtEnabled(pVCpu);
1099	# else
1100	const bool fIsBigPage = PdeSrc.b.u1Size;
1101	# endif
1102
1103	# ifdef IN_RING3
1104	/*
1105	* If a CR3 Sync is pending we may ignore the invalidate page operation
1106	* depending on the kind of sync and if it's a global page or not.
1107	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1108	*/
1109	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1110	if ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1111	\|\| ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1112	&& fIsBigPage
1113	&& PdeSrc.b.u1Global
1114	)
1115	)
1116	# else
1117	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1118	# endif
1119	{
1120	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1121	return VINF_SUCCESS;
1122	}
1123	# endif /* IN_RING3 */
1124
1125	/*
1126	* Deal with the Guest PDE.
1127	*/
1128	rc = VINF_SUCCESS;
1129	if (PdeSrc.n.u1Present)
1130	{
1131	Assert( PdeSrc.n.u1User == PdeDst.n.u1User
1132	&& (PdeSrc.n.u1Write \|\| !PdeDst.n.u1Write));
1133	# ifndef PGM_WITHOUT_MAPPING
1134	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1135	{
1136	/*
1137	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1138	*/
1139	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1140	Assert(PGMGetGuestMode(pVCpu) <= PGMMODE_PAE);
1141	pgmLock(pVM);
1142	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
1143	pgmUnlock(pVM);
1144	}
1145	else
1146	# endif /* !PGM_WITHOUT_MAPPING */
1147	if (!fIsBigPage)
1148	{
1149	/*
1150	* 4KB - page.
1151	*/
1152	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1153	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1154
1155	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1156	/* Reset the modification counter (OpenSolaris trashes tlb entries very often) */
1157	if (pShwPage->cModifications)
1158	pShwPage->cModifications = 1;
1159	# endif
1160
1161	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1162	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1163	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1164	# endif
1165	if (pShwPage->GCPhys == GCPhys)
1166	{
1167	# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
1168	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1169	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1170	if (pPT->a[iPTEDst].n.u1Present)
1171	{
1172	/* This is very unlikely with caching/monitoring enabled. */
1173	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
1174	ASMAtomicWriteSize(&pPT->a[iPTEDst], 0);
1175	}
1176	# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1177	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
1178	if (RT_SUCCESS(rc))
1179	rc = VINF_SUCCESS;
1180	# endif
1181	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4KBPages));
1182	PGM_INVL_PG(pVCpu, GCPtrPage);
1183	}
1184	else
1185	{
1186	/*
1187	* The page table address changed.
1188	*/
1189	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1190	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1191	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1192	ASMAtomicWriteSize(pPdeDst, 0);
1193	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1194	PGM_INVL_VCPU_TLBS(pVCpu);
1195	}
1196	}
1197	else
1198	{
1199	/*
1200	* 2/4MB - page.
1201	*/
1202	/* Before freeing the page, check if anything really changed. */
1203	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1204	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1205	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1206	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1207	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1208	# endif
1209	if ( pShwPage->GCPhys == GCPhys
1210	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1211	{
1212	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1213	/** @todo PAT */
1214	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1215	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1216	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1217	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1218	{
1219	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1220	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1221	# if defined(IN_RC)
1222	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1223	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1224	# endif
1225	return VINF_SUCCESS;
1226	}
1227	}
1228
1229	/*
1230	* Ok, the page table is present and it's been changed in the guest.
1231	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1232	* We could do this for some flushes in GC too, but we need an algorithm for
1233	* deciding which 4MB pages containing code likely to be executed very soon.
1234	*/
1235	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1236	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1237	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1238	ASMAtomicWriteSize(pPdeDst, 0);
1239	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPages));
1240	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
1241	}
1242	}
1243	else
1244	{
1245	/*
1246	* Page directory is not present, mark shadow PDE not present.
1247	*/
1248	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1249	{
1250	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1251	ASMAtomicWriteSize(pPdeDst, 0);
1252	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1253	PGM_INVL_PG(pVCpu, GCPtrPage);
1254	}
1255	else
1256	{
1257	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1258	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDMappings));
1259	}
1260	}
1261	# if defined(IN_RC)
1262	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1263	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1264	# endif
1265	return rc;
1266
1267	#else /* guest real and protected mode */
1268	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1269	return VINF_SUCCESS;
1270	#endif
1271	}
1272
1273
1274	/**
1275	* Update the tracking of shadowed pages.
1276	*
1277	* @param pVCpu The VMCPU handle.
1278	* @param pShwPage The shadow page.
1279	* @param HCPhys The physical page we is being dereferenced.
1280	*/
1281	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
1282	{
1283	PVM pVM = pVCpu->CTX_SUFF(pVM);
1284
1285	STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1286	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1287
1288	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1289	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1290	* 2. write protect all shadowed pages. I.e. implement caching.
1291	*/
1292	/** @todo duplicated in the 2nd half of pgmPoolTracDerefGCPhysHint */
1293
1294	/*
1295	* Find the guest address.
1296	*/
1297	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1298	pRam;
1299	pRam = pRam->CTX_SUFF(pNext))
1300	{
1301	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1302	while (iPage-- > 0)
1303	{
1304	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1305	{
1306	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1307
1308	Assert(pShwPage->cPresent);
1309	Assert(pPool->cPresent);
1310	pShwPage->cPresent--;
1311	pPool->cPresent--;
1312
1313	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage]);
1314	STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1315	return;
1316	}
1317	}
1318	}
1319
1320	for (;;)
1321	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1322	}
1323
1324
1325	/**
1326	* Update the tracking of shadowed pages.
1327	*
1328	* @param pVCpu The VMCPU handle.
1329	* @param pShwPage The shadow page.
1330	* @param u16 The top 16-bit of the pPage->HCPhys.
1331	* @param pPage Pointer to the guest page. this will be modified.
1332	* @param iPTDst The index into the shadow table.
1333	*/
1334	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1335	{
1336	PVM pVM = pVCpu->CTX_SUFF(pVM);
1337	/*
1338	* Just deal with the simple first time here.
1339	*/
1340	if (!u16)
1341	{
1342	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1343	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1344	}
1345	else
1346	u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1347
1348	/* write back */
1349	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1350	PGM_PAGE_SET_TRACKING(pPage, u16);
1351
1352	/* update statistics. */
1353	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1354	pShwPage->cPresent++;
1355	if (pShwPage->iFirstPresent > iPTDst)
1356	pShwPage->iFirstPresent = iPTDst;
1357	}
1358
1359
1360	/**
1361	* Creates a 4K shadow page for a guest page.
1362	*
1363	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1364	* physical address. The PdeSrc argument only the flags are used. No page structured
1365	* will be mapped in this function.
1366	*
1367	* @param pVCpu The VMCPU handle.
1368	* @param pPteDst Destination page table entry.
1369	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1370	* Can safely assume that only the flags are being used.
1371	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1372	* @param pShwPage Pointer to the shadow page.
1373	* @param iPTDst The index into the shadow table.
1374	*
1375	* @remark Not used for 2/4MB pages!
1376	*/
1377	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1378	{
1379	if (PteSrc.n.u1Present)
1380	{
1381	PVM pVM = pVCpu->CTX_SUFF(pVM);
1382
1383	# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1384	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1385	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64)
1386	if (pShwPage->fDirty)
1387	{
1388	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1389	PX86PTPAE pGstPT;
1390
1391	pGstPT = (PX86PTPAE)&pPool->aDirtyPages[pShwPage->idxDirty][0];
1392	pGstPT->a[iPTDst].u = PteSrc.u;
1393	}
1394	# endif
1395	/*
1396	* Find the ram range.
1397	*/
1398	PPGMPAGE pPage;
1399	int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK, &pPage);
1400	if (RT_SUCCESS(rc))
1401	{
1402	#ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1403	/* Try make the page writable if necessary. */
1404	if ( PteSrc.n.u1Write
1405	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1406	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1407	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1408	# endif
1409	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1410	{
1411	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, PteSrc.u & GST_PTE_PG_MASK);
1412	AssertRC(rc);
1413	}
1414	#endif
1415
1416	/** @todo investiage PWT, PCD and PAT. */
1417	/*
1418	* Make page table entry.
1419	*/
1420	SHWPTE PteDst;
1421	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1422	{
1423	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1424	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1425	{
1426	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1427	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1428	PteDst.n.u1Present = 1;
1429	PteDst.n.u1Execute = 1;
1430	PteDst.n.u1IgnorePAT = 1;
1431	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1432	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1433	#else
1434	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1435	\| PGM_PAGE_GET_HCPHYS(pPage);
1436	#endif
1437	}
1438	else
1439	{
1440	LogFlow(("SyncPageWorker: monitored page (%RHp) -> mark not present\n", PGM_PAGE_GET_HCPHYS(pPage)));
1441	PteDst.u = 0;
1442	}
1443	/** @todo count these two kinds. */
1444	}
1445	else
1446	{
1447	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1448	/*
1449	* If the page or page directory entry is not marked accessed,
1450	* we mark the page not present.
1451	*/
1452	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1453	{
1454	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1455	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,AccessedPage));
1456	PteDst.u = 0;
1457	}
1458	else
1459	/*
1460	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1461	* when the page is modified.
1462	*/
1463	if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1464	{
1465	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPage));
1466	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1467	\| PGM_PAGE_GET_HCPHYS(pPage)
1468	\| PGM_PTFLAGS_TRACK_DIRTY;
1469	}
1470	else
1471	#endif
1472	{
1473	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageSkipped));
1474	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1475	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1476	PteDst.n.u1Present = 1;
1477	PteDst.n.u1Write = 1;
1478	PteDst.n.u1Execute = 1;
1479	PteDst.n.u1IgnorePAT = 1;
1480	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1481	/* PteDst.n.u1Size = 0 */
1482	#else
1483	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1484	\| PGM_PAGE_GET_HCPHYS(pPage);
1485	#endif
1486	}
1487	}
1488
1489	/*
1490	* Make sure only allocated pages are mapped writable.
1491	*/
1492	if ( PteDst.n.u1Write
1493	&& PteDst.n.u1Present
1494	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1495	{
1496	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet. */
1497	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", (RTGCPHYS)(PteSrc.u & X86_PTE_PAE_PG_MASK), pPage, iPTDst));
1498	}
1499
1500	/*
1501	* Keep user track up to date.
1502	*/
1503	if (PteDst.n.u1Present)
1504	{
1505	if (!pPteDst->n.u1Present)
1506	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1507	else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1508	{
1509	Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1510	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1511	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1512	}
1513	}
1514	else if (pPteDst->n.u1Present)
1515	{
1516	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1517	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1518	}
1519
1520	/*
1521	* Update statistics and commit the entry.
1522	*/
1523	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1524	if (!PteSrc.n.u1Global)
1525	pShwPage->fSeenNonGlobal = true;
1526	#endif
1527	ASMAtomicWriteSize(pPteDst, PteDst.u);
1528	}
1529	/* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1530	/** @todo count these. */
1531	}
1532	else
1533	{
1534	/*
1535	* Page not-present.
1536	*/
1537	Log2(("SyncPageWorker: page not present in Pte\n"));
1538	/* Keep user track up to date. */
1539	if (pPteDst->n.u1Present)
1540	{
1541	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1542	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1543	}
1544	ASMAtomicWriteSize(pPteDst, 0);
1545	/** @todo count these. */
1546	}
1547	}
1548
1549
1550	/**
1551	* Syncs a guest OS page.
1552	*
1553	* There are no conflicts at this point, neither is there any need for
1554	* page table allocations.
1555	*
1556	* @returns VBox status code.
1557	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1558	* @param pVCpu The VMCPU handle.
1559	* @param PdeSrc Page directory entry of the guest.
1560	* @param GCPtrPage Guest context page address.
1561	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1562	* @param uErr Fault error (X86_TRAP_PF_*).
1563	*/
1564	PGM_BTH_DECL(int, SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1565	{
1566	PVM pVM = pVCpu->CTX_SUFF(pVM);
1567	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1568	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1569
1570	Assert(PGMIsLockOwner(pVM));
1571
1572	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1573	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1574	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1575	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1576	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1577
1578	/*
1579	* Assert preconditions.
1580	*/
1581	Assert(PdeSrc.n.u1Present);
1582	Assert(cPages);
1583	# if 0 /* rarely useful; leave for debugging. */
1584	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1585	# endif
1586
1587	/*
1588	* Get the shadow PDE, find the shadow page table in the pool.
1589	*/
1590	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1591	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1592	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
1593
1594	/* Fetch the pgm pool shadow descriptor. */
1595	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1596	Assert(pShwPde);
1597
1598	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1599	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1600	PPGMPOOLPAGE pShwPde = NULL;
1601	PX86PDPAE pPDDst;
1602
1603	/* Fetch the pgm pool shadow descriptor. */
1604	int rc2 = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
1605	AssertRCSuccessReturn(rc2, rc2);
1606	Assert(pShwPde);
1607
1608	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
1609	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1610
1611	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1612	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1613	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1614	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
1615	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
1616
1617	int rc2 = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1618	AssertRCSuccessReturn(rc2, rc2);
1619	Assert(pPDDst && pPdptDst);
1620	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1621	# endif
1622	SHWPDE PdeDst = *pPdeDst;
1623
1624	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
1625	if (!PdeDst.n.u1Present)
1626	{
1627	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE p=%p/%RX64\n", pPdeDst, (uint64_t)PdeDst.u));
1628	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", pVCpu->idCpu, GCPtrPage));
1629	return VINF_SUCCESS; /* force the instruction to be executed again. */
1630	}
1631
1632	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1633	Assert(pShwPage);
1634
1635	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1636	/* Fetch the pgm pool shadow descriptor. */
1637	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1638	Assert(pShwPde);
1639	# endif
1640
1641	# if defined(IN_RC)
1642	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1643	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
1644	# endif
1645
1646	/*
1647	* Check that the page is present and that the shadow PDE isn't out of sync.
1648	*/
1649	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1650	const bool fBigPage = PdeSrc.b.u1Size && CPUMIsGuestPageSizeExtEnabled(pVCpu);
1651	# else
1652	const bool fBigPage = PdeSrc.b.u1Size;
1653	# endif
1654	RTGCPHYS GCPhys;
1655	if (!fBigPage)
1656	{
1657	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1658	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1659	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1660	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
1661	# endif
1662	}
1663	else
1664	{
1665	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1666	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1667	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1668	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1669	# endif
1670	}
1671	if ( pShwPage->GCPhys == GCPhys
1672	&& PdeSrc.n.u1Present
1673	&& (PdeSrc.n.u1User == PdeDst.n.u1User)
1674	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1675	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1676	&& (PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute \|\| !CPUMIsGuestNXEnabled(pVCpu))
1677	# endif
1678	)
1679	{
1680	/*
1681	* Check that the PDE is marked accessed already.
1682	* Since we set the accessed bit before getting here on a #PF, this
1683	* check is only meant for dealing with non-#PF'ing paths.
1684	*/
1685	if (PdeSrc.n.u1Accessed)
1686	{
1687	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1688	if (!fBigPage)
1689	{
1690	/*
1691	* 4KB Page - Map the guest page table.
1692	*/
1693	PGSTPT pPTSrc;
1694	int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1695	if (RT_SUCCESS(rc))
1696	{
1697	# ifdef PGM_SYNC_N_PAGES
1698	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1699	if ( cPages > 1
1700	&& !(uErr & X86_TRAP_PF_P)
1701	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1702	{
1703	/*
1704	* This code path is currently only taken when the caller is PGMTrap0eHandler
1705	* for non-present pages!
1706	*
1707	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1708	* deal with locality.
1709	*/
1710	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1711	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1712	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1713	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1714	# else
1715	const unsigned offPTSrc = 0;
1716	# endif
1717	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1718	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1719	iPTDst = 0;
1720	else
1721	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1722	for (; iPTDst < iPTDstEnd; iPTDst++)
1723	{
1724	if (!pPTDst->a[iPTDst].n.u1Present)
1725	{
1726	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1727	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1728	NOREF(GCPtrCurPage);
1729	#ifndef IN_RING0
1730	/*
1731	* Assuming kernel code will be marked as supervisor - and not as user level
1732	* and executed using a conforming code selector - And marked as readonly.
1733	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1734	*/
1735	PPGMPAGE pPage;
1736	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1737	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1738	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCurPage)
1739	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1740	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1741	)
1742	#endif /* else: CSAM not active */
1743	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1744	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1745	GCPtrCurPage, PteSrc.n.u1Present,
1746	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1747	PteSrc.n.u1User & PdeSrc.n.u1User,
1748	(uint64_t)PteSrc.u,
1749	(uint64_t)pPTDst->a[iPTDst].u,
1750	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1751	}
1752	}
1753	}
1754	else
1755	# endif /* PGM_SYNC_N_PAGES */
1756	{
1757	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1758	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1759	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1760	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1761	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
1762	GCPtrPage, PteSrc.n.u1Present,
1763	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1764	PteSrc.n.u1User & PdeSrc.n.u1User,
1765	(uint64_t)PteSrc.u,
1766	(uint64_t)pPTDst->a[iPTDst].u,
1767	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1768	}
1769	}
1770	else /* MMIO or invalid page: emulated in #PF handler. */
1771	{
1772	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
1773	Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1774	}
1775	}
1776	else
1777	{
1778	/*
1779	* 4/2MB page - lazy syncing shadow 4K pages.
1780	* (There are many causes of getting here, it's no longer only CSAM.)
1781	*/
1782	/* Calculate the GC physical address of this 4KB shadow page. */
1783	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1784	/* Find ram range. */
1785	PPGMPAGE pPage;
1786	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1787	if (RT_SUCCESS(rc))
1788	{
1789	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1790	/* Try make the page writable if necessary. */
1791	if ( PdeSrc.n.u1Write
1792	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1793	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1794	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1795	# endif
1796	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1797	{
1798	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
1799	AssertRC(rc);
1800	}
1801	# endif
1802
1803	/*
1804	* Make shadow PTE entry.
1805	*/
1806	SHWPTE PteDst;
1807	PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1808	\| PGM_PAGE_GET_HCPHYS(pPage);
1809	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1810	{
1811	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1812	PteDst.n.u1Write = 0;
1813	else
1814	PteDst.u = 0;
1815	}
1816	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1817	if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1818	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1819
1820	/* Make sure only allocated pages are mapped writable. */
1821	if ( PteDst.n.u1Write
1822	&& PteDst.n.u1Present
1823	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1824	{
1825	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet... */
1826	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
1827	}
1828
1829	ASMAtomicWriteSize(&pPTDst->a[iPTDst], PteDst.u);
1830
1831	/*
1832	* If the page is not flagged as dirty and is writable, then make it read-only
1833	* at PD level, so we can set the dirty bit when the page is modified.
1834	*
1835	* ASSUMES that page access handlers are implemented on page table entry level.
1836	* Thus we will first catch the dirty access and set PDE.D and restart. If
1837	* there is an access handler, we'll trap again and let it work on the problem.
1838	*/
1839	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1840	* As for invlpg, it simply frees the whole shadow PT.
1841	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1842	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1843	{
1844	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
1845	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1846	PdeDst.n.u1Write = 0;
1847	}
1848	else
1849	{
1850	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1851	PdeDst.n.u1Write = PdeSrc.n.u1Write;
1852	}
1853	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
1854	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
1855	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1856	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1857	}
1858	else
1859	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
1860	}
1861	# if defined(IN_RC)
1862	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1863	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1864	# endif
1865	return VINF_SUCCESS;
1866	}
1867	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDNAs));
1868	}
1869	else
1870	{
1871	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSync));
1872	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
1873	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
1874	}
1875
1876	/*
1877	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1878	* Yea, I'm lazy.
1879	*/
1880	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
1881	ASMAtomicWriteSize(pPdeDst, 0);
1882
1883	# if defined(IN_RC)
1884	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1885	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1886	# endif
1887	PGM_INVL_VCPU_TLBS(pVCpu);
1888	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
1889
1890	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
1891	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1892	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
1893	&& !defined(IN_RC)
1894
1895	# ifdef PGM_SYNC_N_PAGES
1896	/*
1897	* Get the shadow PDE, find the shadow page table in the pool.
1898	*/
1899	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1900	X86PDE PdeDst = pgmShwGet32BitPDE(&pVCpu->pgm.s, GCPtrPage);
1901
1902	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1903	X86PDEPAE PdeDst = pgmShwGetPaePDE(&pVCpu->pgm.s, GCPtrPage);
1904
1905	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1906	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1907	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
1908	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
1909	X86PDEPAE PdeDst;
1910	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
1911
1912	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1913	AssertRCSuccessReturn(rc, rc);
1914	Assert(pPDDst && pPdptDst);
1915	PdeDst = pPDDst->a[iPDDst];
1916	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
1917	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1918	PEPTPD pPDDst;
1919	EPTPDE PdeDst;
1920
1921	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, NULL, &pPDDst);
1922	if (rc != VINF_SUCCESS)
1923	{
1924	AssertRC(rc);
1925	return rc;
1926	}
1927	Assert(pPDDst);
1928	PdeDst = pPDDst->a[iPDDst];
1929	# endif
1930	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
1931	if (!PdeDst.n.u1Present)
1932	{
1933	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE %RX64\n", (uint64_t)PdeDst.u));
1934	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", pVCpu->idCpu, GCPtrPage));
1935	return VINF_SUCCESS; /* force the instruction to be executed again. */
1936	}
1937
1938	/* Can happen in the guest SMP case; other VCPU activated this PDE while we were blocking to handle the page fault. */
1939	if (PdeDst.n.u1Size)
1940	{
1941	Assert(HWACCMIsNestedPagingActive(pVM));
1942	Log(("CPU%d: SyncPage: Pde (big:%RX64) at %RGv changed behind our back!\n", pVCpu->idCpu, PdeDst.u, GCPtrPage));
1943	return VINF_SUCCESS;
1944	}
1945
1946	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1947	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1948
1949	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1950	if ( cPages > 1
1951	&& !(uErr & X86_TRAP_PF_P)
1952	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1953	{
1954	/*
1955	* This code path is currently only taken when the caller is PGMTrap0eHandler
1956	* for non-present pages!
1957	*
1958	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1959	* deal with locality.
1960	*/
1961	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1962	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1963	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1964	iPTDst = 0;
1965	else
1966	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1967	for (; iPTDst < iPTDstEnd; iPTDst++)
1968	{
1969	if (!pPTDst->a[iPTDst].n.u1Present)
1970	{
1971	GSTPTE PteSrc;
1972
1973	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
1974
1975	/* Fake the page table entry */
1976	PteSrc.u = GCPtrCurPage;
1977	PteSrc.n.u1Present = 1;
1978	PteSrc.n.u1Dirty = 1;
1979	PteSrc.n.u1Accessed = 1;
1980	PteSrc.n.u1Write = 1;
1981	PteSrc.n.u1User = 1;
1982
1983	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1984
1985	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1986	GCPtrCurPage, PteSrc.n.u1Present,
1987	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1988	PteSrc.n.u1User & PdeSrc.n.u1User,
1989	(uint64_t)PteSrc.u,
1990	(uint64_t)pPTDst->a[iPTDst].u,
1991	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1992
1993	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
1994	break;
1995	}
1996	else
1997	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, pPTDst->a[iPTDst].u));
1998	}
1999	}
2000	else
2001	# endif /* PGM_SYNC_N_PAGES */
2002	{
2003	GSTPTE PteSrc;
2004	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2005	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2006
2007	/* Fake the page table entry */
2008	PteSrc.u = GCPtrCurPage;
2009	PteSrc.n.u1Present = 1;
2010	PteSrc.n.u1Dirty = 1;
2011	PteSrc.n.u1Accessed = 1;
2012	PteSrc.n.u1Write = 1;
2013	PteSrc.n.u1User = 1;
2014	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2015
2016	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}PteDst=%08llx%s\n",
2017	GCPtrPage, PteSrc.n.u1Present,
2018	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2019	PteSrc.n.u1User & PdeSrc.n.u1User,
2020	(uint64_t)PteSrc.u,
2021	(uint64_t)pPTDst->a[iPTDst].u,
2022	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2023	}
2024	return VINF_SUCCESS;
2025
2026	#else
2027	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2028	return VERR_INTERNAL_ERROR;
2029	#endif
2030	}
2031
2032
2033	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2034	/**
2035	* Investigate page fault and handle write protection page faults caused by
2036	* dirty bit tracking.
2037	*
2038	* @returns VBox status code.
2039	* @param pVCpu The VMCPU handle.
2040	* @param uErr Page fault error code.
2041	* @param pPdeSrc Guest page directory entry.
2042	* @param GCPtrPage Guest context page address.
2043	*/
2044	PGM_BTH_DECL(int, CheckPageFault)(PVMCPU pVCpu, uint32_t uErr, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage)
2045	{
2046	bool fUserLevelFault = !!(uErr & X86_TRAP_PF_US);
2047	bool fWriteFault = !!(uErr & X86_TRAP_PF_RW);
2048	bool fMaybeWriteProtFault = fWriteFault && (fUserLevelFault \|\| CPUMIsGuestR0WriteProtEnabled(pVCpu));
2049	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2050	bool fMaybeNXEFault = (uErr & X86_TRAP_PF_ID) && CPUMIsGuestNXEnabled(pVCpu);
2051	# endif
2052	unsigned uPageFaultLevel;
2053	int rc;
2054	PVM pVM = pVCpu->CTX_SUFF(pVM);
2055
2056	LogFlow(("CheckPageFault: GCPtrPage=%RGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
2057
2058	# if PGM_GST_TYPE == PGM_TYPE_PAE \
2059	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
2060
2061	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2062	PX86PML4E pPml4eSrc;
2063	PX86PDPE pPdpeSrc;
2064
2065	pPdpeSrc = pgmGstGetLongModePDPTPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc);
2066	Assert(pPml4eSrc);
2067
2068	/*
2069	* Real page fault? (PML4E level)
2070	*/
2071	if ( (uErr & X86_TRAP_PF_RSVD)
2072	\|\| !pPml4eSrc->n.u1Present
2073	\|\| (fMaybeWriteProtFault && !pPml4eSrc->n.u1Write)
2074	\|\| (fMaybeNXEFault && pPml4eSrc->n.u1NoExecute)
2075	\|\| (fUserLevelFault && !pPml4eSrc->n.u1User)
2076	)
2077	{
2078	uPageFaultLevel = 0;
2079	goto l_UpperLevelPageFault;
2080	}
2081	Assert(pPdpeSrc);
2082
2083	# else /* PAE */
2084	PX86PDPE pPdpeSrc = pgmGstGetPaePDPEPtr(&pVCpu->pgm.s, GCPtrPage);
2085	# endif /* PAE */
2086
2087	/*
2088	* Real page fault? (PDPE level)
2089	*/
2090	if ( (uErr & X86_TRAP_PF_RSVD)
2091	\|\| !pPdpeSrc->n.u1Present
2092	# if PGM_GST_TYPE == PGM_TYPE_AMD64 /* NX, r/w, u/s bits in the PDPE are long mode only */
2093	\|\| (fMaybeWriteProtFault && !pPdpeSrc->lm.u1Write)
2094	\|\| (fMaybeNXEFault && pPdpeSrc->lm.u1NoExecute)
2095	\|\| (fUserLevelFault && !pPdpeSrc->lm.u1User)
2096	# endif
2097	)
2098	{
2099	uPageFaultLevel = 1;
2100	goto l_UpperLevelPageFault;
2101	}
2102	# endif
2103
2104	/*
2105	* Real page fault? (PDE level)
2106	*/
2107	if ( (uErr & X86_TRAP_PF_RSVD)
2108	\|\| !pPdeSrc->n.u1Present
2109	\|\| (fMaybeWriteProtFault && !pPdeSrc->n.u1Write)
2110	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2111	\|\| (fMaybeNXEFault && pPdeSrc->n.u1NoExecute)
2112	# endif
2113	\|\| (fUserLevelFault && !pPdeSrc->n.u1User) )
2114	{
2115	uPageFaultLevel = 2;
2116	goto l_UpperLevelPageFault;
2117	}
2118
2119	/*
2120	* First check the easy case where the page directory has been marked read-only to track
2121	* the dirty bit of an emulated BIG page
2122	*/
2123	if ( pPdeSrc->b.u1Size
2124	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2125	&& CPUMIsGuestPageSizeExtEnabled(pVCpu)
2126	# endif
2127	)
2128	{
2129	/* Mark guest page directory as accessed */
2130	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2131	pPml4eSrc->n.u1Accessed = 1;
2132	pPdpeSrc->lm.u1Accessed = 1;
2133	# endif
2134	pPdeSrc->b.u1Accessed = 1;
2135
2136	/*
2137	* Only write protection page faults are relevant here.
2138	*/
2139	if (fWriteFault)
2140	{
2141	/* Mark guest page directory as dirty (BIG page only). */
2142	pPdeSrc->b.u1Dirty = 1;
2143	}
2144	return VINF_SUCCESS;
2145	}
2146	/* else: 4KB page table */
2147
2148	/*
2149	* Map the guest page table.
2150	*/
2151	PGSTPT pPTSrc;
2152	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2153	if (RT_SUCCESS(rc))
2154	{
2155	/*
2156	* Real page fault?
2157	*/
2158	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2159	const GSTPTE PteSrc = *pPteSrc;
2160	if ( !PteSrc.n.u1Present
2161	\|\| (fMaybeWriteProtFault && !PteSrc.n.u1Write)
2162	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2163	\|\| (fMaybeNXEFault && PteSrc.n.u1NoExecute)
2164	# endif
2165	\|\| (fUserLevelFault && !PteSrc.n.u1User)
2166	)
2167	{
2168	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2169	LogFlow(("CheckPageFault: real page fault at %RGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
2170
2171	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
2172	* See the 2nd case above as well.
2173	*/
2174	if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
2175	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2176
2177	return VINF_EM_RAW_GUEST_TRAP;
2178	}
2179	LogFlow(("CheckPageFault: page fault at %RGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
2180
2181	/*
2182	* Set the accessed bits in the page directory and the page table.
2183	*/
2184	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2185	pPml4eSrc->n.u1Accessed = 1;
2186	pPdpeSrc->lm.u1Accessed = 1;
2187	# endif
2188	pPdeSrc->n.u1Accessed = 1;
2189	pPteSrc->n.u1Accessed = 1;
2190
2191	/*
2192	* Only write protection page faults are relevant here.
2193	*/
2194	if (fWriteFault)
2195	{
2196	/* Write access, so mark guest entry as dirty. */
2197	# ifdef VBOX_WITH_STATISTICS
2198	if (!pPteSrc->n.u1Dirty)
2199	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtiedPage));
2200	else
2201	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageAlreadyDirty));
2202	# endif
2203
2204	pPteSrc->n.u1Dirty = 1;
2205	}
2206	return VINF_SUCCESS;
2207	}
2208	AssertRC(rc);
2209	return rc;
2210
2211
2212	l_UpperLevelPageFault:
2213	/*
2214	* Pagefault detected while checking the PML4E, PDPE or PDE.
2215	* Single exit handler to get rid of duplicate code paths.
2216	*/
2217	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2218	Log(("CheckPageFault: real page fault at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2219
2220	if ( 1
2221	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2222	&& pPml4eSrc->n.u1Present
2223	# endif
2224	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
2225	&& pPdpeSrc->n.u1Present
2226	# endif
2227	&& pPdeSrc->n.u1Present)
2228	{
2229	/* Check the present bit as the shadow tables can cause different error codes by being out of sync. */
2230	if ( pPdeSrc->b.u1Size
2231	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2232	&& CPUMIsGuestPageSizeExtEnabled(pVCpu)
2233	# endif
2234	)
2235	{
2236	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2237	}
2238	else
2239	{
2240	/*
2241	* Map the guest page table.
2242	*/
2243	PGSTPT pPTSrc2;
2244	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc2);
2245	if (RT_SUCCESS(rc))
2246	{
2247	PGSTPTE pPteSrc = &pPTSrc2->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2248	if (pPteSrc->n.u1Present)
2249	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2250	}
2251	AssertRC(rc);
2252	}
2253	}
2254	return VINF_EM_RAW_GUEST_TRAP;
2255	}
2256
2257	/**
2258	* Handle dirty bit tracking faults.
2259	*
2260	* @returns VBox status code.
2261	* @param pVCpu The VMCPU handle.
2262	* @param uErr Page fault error code.
2263	* @param pPdeSrc Guest page directory entry.
2264	* @param pPdeDst Shadow page directory entry.
2265	* @param GCPtrPage Guest context page address.
2266	*/
2267	PGM_BTH_DECL(int, CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage)
2268	{
2269	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2270	const bool fBigPagesSupported = CPUMIsGuestPageSizeExtEnabled(pVCpu);
2271	# else
2272	const bool fBigPagesSupported = true;
2273	# endif
2274	PVM pVM = pVCpu->CTX_SUFF(pVM);
2275	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2276
2277	Assert(PGMIsLockOwner(pVM));
2278
2279	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2280	{
2281	if ( pPdeDst->n.u1Present
2282	&& (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
2283	{
2284	SHWPDE PdeDst = *pPdeDst;
2285
2286	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2287	Assert(pPdeSrc->b.u1Write);
2288
2289	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2290	* fault again and take this path to only invalidate the entry.
2291	*/
2292	PdeDst.n.u1Write = 1;
2293	PdeDst.n.u1Accessed = 1;
2294	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2295	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2296	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
2297	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2298	}
2299	# ifdef IN_RING0
2300	else
2301	/* Check for stale TLB entry; only applies to the SMP guest case. */
2302	if ( pVM->cCpus > 1
2303	&& pPdeDst->n.u1Write
2304	&& pPdeDst->n.u1Accessed)
2305	{
2306	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2307	if (pShwPage)
2308	{
2309	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2310	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2311	if ( pPteDst->n.u1Present
2312	&& pPteDst->n.u1Write)
2313	{
2314	/* Stale TLB entry. */
2315	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageStale));
2316	PGM_INVL_PG(pVCpu, GCPtrPage);
2317	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2318	}
2319	}
2320	}
2321	# endif /* IN_RING0 */
2322	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2323	}
2324
2325	/*
2326	* Map the guest page table.
2327	*/
2328	PGSTPT pPTSrc;
2329	int rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2330	if (RT_SUCCESS(rc))
2331	{
2332	if (pPdeDst->n.u1Present)
2333	{
2334	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2335	const GSTPTE PteSrc = *pPteSrc;
2336	#ifndef IN_RING0
2337	/* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
2338	* Our individual shadow handlers will provide more information and force a fatal exit.
2339	*/
2340	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2341	{
2342	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2343	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2344	}
2345	#endif
2346	/*
2347	* Map shadow page table.
2348	*/
2349	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2350	if (pShwPage)
2351	{
2352	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2353	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2354	if (pPteDst->n.u1Present) /** @todo Optimize accessed bit emulation? */
2355	{
2356	if (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY)
2357	{
2358	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
2359	SHWPTE PteDst = *pPteDst;
2360
2361	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2362	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2363
2364	Assert(pPteSrc->n.u1Write);
2365
2366	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2367	* fault again and take this path to only invalidate the entry.
2368	*/
2369	if (RT_LIKELY(pPage))
2370	{
2371	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2372	/* Assuming write handlers here as the PTE is present (otherwise we wouldn't be here). */
2373	PteDst.n.u1Write = 0;
2374	else
2375	{
2376	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
2377	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2378	{
2379	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, pPteSrc->u & GST_PTE_PG_MASK);
2380	AssertRC(rc);
2381	}
2382	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
2383	PteDst.n.u1Write = 1;
2384	else
2385	PteDst.n.u1Write = 0;
2386	}
2387	}
2388	else
2389	PteDst.n.u1Write = 1;
2390
2391	PteDst.n.u1Dirty = 1;
2392	PteDst.n.u1Accessed = 1;
2393	PteDst.au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
2394	ASMAtomicWriteSize(pPteDst, PteDst.u);
2395	PGM_INVL_PG(pVCpu, GCPtrPage);
2396	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2397	}
2398	# ifdef IN_RING0
2399	else
2400	/* Check for stale TLB entry; only applies to the SMP guest case. */
2401	if ( pVM->cCpus > 1
2402	&& pPteDst->n.u1Write == 1
2403	&& pPteDst->n.u1Accessed == 1)
2404	{
2405	/* Stale TLB entry. */
2406	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageStale));
2407	PGM_INVL_PG(pVCpu, GCPtrPage);
2408	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2409	}
2410	# endif
2411	}
2412	}
2413	else
2414	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2415	}
2416	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2417	}
2418	AssertRC(rc);
2419	return rc;
2420	}
2421	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2422
2423
2424	/**
2425	* Sync a shadow page table.
2426	*
2427	* The shadow page table is not present. This includes the case where
2428	* there is a conflict with a mapping.
2429	*
2430	* @returns VBox status code.
2431	* @param pVCpu The VMCPU handle.
2432	* @param iPD Page directory index.
2433	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2434	* Assume this is a temporary mapping.
2435	* @param GCPtrPage GC Pointer of the page that caused the fault
2436	*/
2437	PGM_BTH_DECL(int, SyncPT)(PVMCPU pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2438	{
2439	PVM pVM = pVCpu->CTX_SUFF(pVM);
2440	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2441
2442	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2443	#if 0 /* rarely useful; leave for debugging. */
2444	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
2445	#endif
2446	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage));
2447
2448	Assert(PGMIsLocked(pVM));
2449
2450	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2451	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2452	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2453	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2454	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2455
2456	int rc = VINF_SUCCESS;
2457
2458	/*
2459	* Validate input a little bit.
2460	*/
2461	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2462	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2463	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2464	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
2465
2466	/* Fetch the pgm pool shadow descriptor. */
2467	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2468	Assert(pShwPde);
2469
2470	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2471	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2472	PPGMPOOLPAGE pShwPde = NULL;
2473	PX86PDPAE pPDDst;
2474	PSHWPDE pPdeDst;
2475
2476	/* Fetch the pgm pool shadow descriptor. */
2477	rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
2478	AssertRCSuccessReturn(rc, rc);
2479	Assert(pShwPde);
2480
2481	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
2482	pPdeDst = &pPDDst->a[iPDDst];
2483
2484	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2485	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2486	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2487	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2488	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2489	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2490	AssertRCSuccessReturn(rc, rc);
2491	Assert(pPDDst);
2492	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2493	# endif
2494	SHWPDE PdeDst = *pPdeDst;
2495
2496	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2497	/* Fetch the pgm pool shadow descriptor. */
2498	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2499	Assert(pShwPde);
2500	# endif
2501
2502	# ifndef PGM_WITHOUT_MAPPINGS
2503	/*
2504	* Check for conflicts.
2505	* GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2506	* HC: Simply resolve the conflict.
2507	*/
2508	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2509	{
2510	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2511	# ifndef IN_RING3
2512	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2513	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2514	return VERR_ADDRESS_CONFLICT;
2515	# else
2516	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2517	Assert(pMapping);
2518	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2519	rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2520	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2521	rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2522	# else
2523	AssertFailed(); /* can't happen for amd64 */
2524	# endif
2525	if (RT_FAILURE(rc))
2526	{
2527	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2528	return rc;
2529	}
2530	PdeDst = *pPdeDst;
2531	# endif
2532	}
2533	# endif /* !PGM_WITHOUT_MAPPINGS */
2534	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2535
2536	# if defined(IN_RC)
2537	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
2538	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
2539	# endif
2540
2541	/*
2542	* Sync page directory entry.
2543	*/
2544	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2545	if (PdeSrc.n.u1Present)
2546	{
2547	/*
2548	* Allocate & map the page table.
2549	*/
2550	PSHWPT pPTDst;
2551	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2552	const bool fPageTable = !PdeSrc.b.u1Size \|\| !CPUMIsGuestPageSizeExtEnabled(pVCpu);
2553	# else
2554	const bool fPageTable = !PdeSrc.b.u1Size;
2555	# endif
2556	PPGMPOOLPAGE pShwPage;
2557	RTGCPHYS GCPhys;
2558	if (fPageTable)
2559	{
2560	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2561	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2562	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2563	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2564	# endif
2565	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2566	}
2567	else
2568	{
2569	PGMPOOLACCESS enmAccess;
2570	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2571	const bool fNoExecute = PdeSrc.n.u1NoExecute && CPUMIsGuestNXEnabled(pVCpu);
2572	# else
2573	const bool fNoExecute = false;
2574	# endif
2575
2576	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
2577	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2578	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2579	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
2580	# endif
2581	/* Determine the right kind of large page to avoid incorrect cached entry reuse. */
2582	if (PdeSrc.n.u1User)
2583	{
2584	if (PdeSrc.n.u1Write)
2585	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_RW_NX : PGMPOOLACCESS_USER_RW;
2586	else
2587	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_R_NX : PGMPOOLACCESS_USER_R;
2588	}
2589	else
2590	{
2591	if (PdeSrc.n.u1Write)
2592	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_RW_NX : PGMPOOLACCESS_SUPERVISOR_RW;
2593	else
2594	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_R_NX : PGMPOOLACCESS_SUPERVISOR_R;
2595	}
2596	rc = pgmPoolAllocEx(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, enmAccess, pShwPde->idx, iPDDst, &pShwPage);
2597	}
2598	if (rc == VINF_SUCCESS)
2599	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2600	else if (rc == VINF_PGM_CACHED_PAGE)
2601	{
2602	/*
2603	* The PT was cached, just hook it up.
2604	*/
2605	if (fPageTable)
2606	PdeDst.u = pShwPage->Core.Key
2607	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2608	else
2609	{
2610	PdeDst.u = pShwPage->Core.Key
2611	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2612	/* (see explanation and assumptions further down.) */
2613	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2614	{
2615	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2616	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2617	PdeDst.b.u1Write = 0;
2618	}
2619	}
2620	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2621	# if defined(IN_RC)
2622	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2623	# endif
2624	return VINF_SUCCESS;
2625	}
2626	else if (rc == VERR_PGM_POOL_FLUSHED)
2627	{
2628	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2629	# if defined(IN_RC)
2630	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2631	# endif
2632	return VINF_PGM_SYNC_CR3;
2633	}
2634	else
2635	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2636	PdeDst.u &= X86_PDE_AVL_MASK;
2637	PdeDst.u \|= pShwPage->Core.Key;
2638
2639	/*
2640	* Page directory has been accessed (this is a fault situation, remember).
2641	*/
2642	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2643	if (fPageTable)
2644	{
2645	/*
2646	* Page table - 4KB.
2647	*
2648	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2649	*/
2650	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2651	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2652	PGSTPT pPTSrc;
2653	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
2654	if (RT_SUCCESS(rc))
2655	{
2656	/*
2657	* Start by syncing the page directory entry so CSAM's TLB trick works.
2658	*/
2659	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2660	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2661	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2662	# if defined(IN_RC)
2663	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2664	# endif
2665
2666	/*
2667	* Directory/page user or supervisor privilege: (same goes for read/write)
2668	*
2669	* Directory Page Combined
2670	* U/S U/S U/S
2671	* 0 0 0
2672	* 0 1 0
2673	* 1 0 0
2674	* 1 1 1
2675	*
2676	* Simple AND operation. Table listed for completeness.
2677	*
2678	*/
2679	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT4K));
2680	# ifdef PGM_SYNC_N_PAGES
2681	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2682	unsigned iPTDst = iPTBase;
2683	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2684	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2685	iPTDst = 0;
2686	else
2687	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2688	# else /* !PGM_SYNC_N_PAGES */
2689	unsigned iPTDst = 0;
2690	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2691	# endif /* !PGM_SYNC_N_PAGES */
2692	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2693	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2694	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2695	# else
2696	const unsigned offPTSrc = 0;
2697	# endif
2698	for (; iPTDst < iPTDstEnd; iPTDst++)
2699	{
2700	const unsigned iPTSrc = iPTDst + offPTSrc;
2701	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2702
2703	if (PteSrc.n.u1Present) /* we've already cleared it above */
2704	{
2705	# ifndef IN_RING0
2706	/*
2707	* Assuming kernel code will be marked as supervisor - and not as user level
2708	* and executed using a conforming code selector - And marked as readonly.
2709	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2710	*/
2711	PPGMPAGE pPage;
2712	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2713	\|\| !CSAMDoesPageNeedScanning(pVM, (iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT))
2714	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
2715	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2716	)
2717	# endif
2718	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2719	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2720	(RTGCPTR)(((RTGCPTR)iPDSrc << GST_PD_SHIFT) \| ((RTGCPTR)iPTSrc << PAGE_SHIFT)),
2721	PteSrc.n.u1Present,
2722	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2723	PteSrc.n.u1User & PdeSrc.n.u1User,
2724	(uint64_t)PteSrc.u,
2725	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2726	(RTGCPHYS)((PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)) ));
2727	}
2728	} /* for PTEs */
2729	}
2730	}
2731	else
2732	{
2733	/*
2734	* Big page - 2/4MB.
2735	*
2736	* We'll walk the ram range list in parallel and optimize lookups.
2737	* We will only sync on shadow page table at a time.
2738	*/
2739	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT4M));
2740
2741	/**
2742	* @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2743	*/
2744
2745	/*
2746	* Start by syncing the page directory entry.
2747	*/
2748	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2749	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2750
2751	/*
2752	* If the page is not flagged as dirty and is writable, then make it read-only
2753	* at PD level, so we can set the dirty bit when the page is modified.
2754	*
2755	* ASSUMES that page access handlers are implemented on page table entry level.
2756	* Thus we will first catch the dirty access and set PDE.D and restart. If
2757	* there is an access handler, we'll trap again and let it work on the problem.
2758	*/
2759	/** @todo move the above stuff to a section in the PGM documentation. */
2760	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2761	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2762	{
2763	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2764	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2765	PdeDst.b.u1Write = 0;
2766	}
2767	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2768	# if defined(IN_RC)
2769	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2770	# endif
2771
2772	/*
2773	* Fill the shadow page table.
2774	*/
2775	/* Get address and flags from the source PDE. */
2776	SHWPTE PteDstBase;
2777	PteDstBase.u = PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT);
2778
2779	/* Loop thru the entries in the shadow PT. */
2780	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2781	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2782	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2783	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2784	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2785	unsigned iPTDst = 0;
2786	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2787	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2788	{
2789	/* Advance ram range list. */
2790	while (pRam && GCPhys > pRam->GCPhysLast)
2791	pRam = pRam->CTX_SUFF(pNext);
2792	if (pRam && GCPhys >= pRam->GCPhys)
2793	{
2794	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2795	do
2796	{
2797	/* Make shadow PTE. */
2798	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2799	SHWPTE PteDst;
2800
2801	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2802	/* Try make the page writable if necessary. */
2803	if ( PteDstBase.n.u1Write
2804	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2805	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2806	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2807	# endif
2808	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2809	{
2810	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
2811	AssertRCReturn(rc, rc);
2812	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2813	break;
2814	}
2815	# endif
2816
2817	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2818	{
2819	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2820	{
2821	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2822	PteDst.n.u1Write = 0;
2823	}
2824	else
2825	PteDst.u = 0;
2826	}
2827	# ifndef IN_RING0
2828	/*
2829	* Assuming kernel code will be marked as supervisor and not as user level and executed
2830	* using a conforming code selector. Don't check for readonly, as that implies the whole
2831	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2832	*/
2833	else if ( !PdeSrc.n.u1User
2834	&& CSAMDoesPageNeedScanning(pVM, GCPtr \| (iPTDst << SHW_PT_SHIFT)))
2835	PteDst.u = 0;
2836	# endif
2837	else
2838	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2839
2840	/* Only map writable pages writable. */
2841	if ( PteDst.n.u1Write
2842	&& PteDst.n.u1Present
2843	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2844	{
2845	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet... */
2846	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
2847	}
2848
2849	if (PteDst.n.u1Present)
2850	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2851
2852	/* commit it */
2853	pPTDst->a[iPTDst] = PteDst;
2854	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2855	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2856	PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2857
2858	/* advance */
2859	GCPhys += PAGE_SIZE;
2860	iHCPage++;
2861	iPTDst++;
2862	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2863	&& GCPhys <= pRam->GCPhysLast);
2864	}
2865	else if (pRam)
2866	{
2867	Log(("Invalid pages at %RGp\n", GCPhys));
2868	do
2869	{
2870	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2871	GCPhys += PAGE_SIZE;
2872	iPTDst++;
2873	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2874	&& GCPhys < pRam->GCPhys);
2875	}
2876	else
2877	{
2878	Log(("Invalid pages at %RGp (2)\n", GCPhys));
2879	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
2880	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2881	}
2882	} /* while more PTEs */
2883	} /* 4KB / 4MB */
2884	}
2885	else
2886	AssertRelease(!PdeDst.n.u1Present);
2887
2888	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2889	if (RT_FAILURE(rc))
2890	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPTFailed));
2891	return rc;
2892
2893	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2894	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2895	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2896	&& !defined(IN_RC)
2897
2898	/*
2899	* Validate input a little bit.
2900	*/
2901	int rc = VINF_SUCCESS;
2902	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2903	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2904	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
2905
2906	/* Fetch the pgm pool shadow descriptor. */
2907	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2908	Assert(pShwPde);
2909
2910	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2911	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2912	PPGMPOOLPAGE pShwPde = NULL; /* initialized to shut up gcc */
2913	PX86PDPAE pPDDst;
2914	PSHWPDE pPdeDst;
2915
2916	/* Fetch the pgm pool shadow descriptor. */
2917	rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
2918	AssertRCSuccessReturn(rc, rc);
2919	Assert(pShwPde);
2920
2921	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
2922	pPdeDst = &pPDDst->a[iPDDst];
2923
2924	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2925	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2926	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2927	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2928	PX86PDPT pPdptDst= NULL; /* initialized to shut up gcc */
2929	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2930	AssertRCSuccessReturn(rc, rc);
2931	Assert(pPDDst);
2932	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2933
2934	/* Fetch the pgm pool shadow descriptor. */
2935	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2936	Assert(pShwPde);
2937
2938	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2939	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
2940	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2941	PEPTPD pPDDst;
2942	PEPTPDPT pPdptDst;
2943
2944	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
2945	if (rc != VINF_SUCCESS)
2946	{
2947	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2948	AssertRC(rc);
2949	return rc;
2950	}
2951	Assert(pPDDst);
2952	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2953
2954	/* Fetch the pgm pool shadow descriptor. */
2955	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
2956	Assert(pShwPde);
2957	# endif
2958	SHWPDE PdeDst = *pPdeDst;
2959
2960	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
2961	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2962
2963	# if defined(PGM_WITH_LARGE_PAGES) && (PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE)
2964	# if (PGM_SHW_TYPE != PGM_TYPE_EPT) /* PGM_TYPE_EPT implies nested paging */
2965	if (HWACCMIsNestedPagingActive(pVM))
2966	# endif
2967	{
2968	PPGMPAGE pPage;
2969
2970	/* Check if we allocated a big page before for this 2 MB range. */
2971	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPtrPage & X86_PDE2M_PAE_PG_MASK, &pPage);
2972	if (RT_SUCCESS(rc))
2973	{
2974	RTHCPHYS HCPhys = NIL_RTHCPHYS;
2975
2976	if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
2977	{
2978	STAM_REL_COUNTER_INC(&pVM->pgm.s.StatLargePageReused);
2979	AssertRelease(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
2980	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
2981	}
2982	else
2983	if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED)
2984	{
2985	/* Recheck the entire 2 MB range to see if we can use it again as a large page. */
2986	rc = pgmPhysIsValidLargePage(pVM, GCPtrPage, pPage);
2987	if (RT_SUCCESS(rc))
2988	{
2989	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
2990	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
2991	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
2992	}
2993	}
2994	else
2995	if (PGMIsUsingLargePages(pVM))
2996	{
2997	rc = pgmPhysAllocLargePage(pVM, GCPtrPage);
2998	if (RT_SUCCESS(rc))
2999	{
3000	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3001	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3002	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3003	}
3004	else
3005	LogFlow(("pgmPhysAllocLargePage failed with %Rrc\n", rc));
3006	}
3007
3008	if (HCPhys != NIL_RTHCPHYS)
3009	{
3010	PdeDst.u &= X86_PDE_AVL_MASK;
3011	PdeDst.u \|= HCPhys;
3012	PdeDst.n.u1Present = 1;
3013	PdeDst.n.u1Write = 1;
3014	PdeDst.b.u1Size = 1;
3015	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3016	PdeDst.n.u1Execute = 1;
3017	PdeDst.b.u1IgnorePAT = 1;
3018	PdeDst.b.u3EMT = VMX_EPT_MEMTYPE_WB;
3019	# else
3020	PdeDst.n.u1User = 1;
3021	# endif
3022	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3023
3024	Log(("SyncPT: Use large page at %RGp PDE=%RX64\n", GCPtrPage, PdeDst.u));
3025	/* Add a reference to the first page only. */
3026	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPde, PGM_PAGE_GET_TRACKING(pPage), pPage, iPDDst);
3027
3028	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
3029	return VINF_SUCCESS;
3030	}
3031	}
3032	}
3033	# endif /* HC_ARCH_BITS == 64 */
3034
3035	GSTPDE PdeSrc;
3036	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
3037	PdeSrc.n.u1Present = 1;
3038	PdeSrc.n.u1Write = 1;
3039	PdeSrc.n.u1Accessed = 1;
3040	PdeSrc.n.u1User = 1;
3041
3042	/*
3043	* Allocate & map the page table.
3044	*/
3045	PSHWPT pPTDst;
3046	PPGMPOOLPAGE pShwPage;
3047	RTGCPHYS GCPhys;
3048
3049	/* Virtual address = physical address */
3050	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK;
3051	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
3052
3053	if ( rc == VINF_SUCCESS
3054	\|\| rc == VINF_PGM_CACHED_PAGE)
3055	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
3056	else
3057	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
3058
3059	PdeDst.u &= X86_PDE_AVL_MASK;
3060	PdeDst.u \|= pShwPage->Core.Key;
3061	PdeDst.n.u1Present = 1;
3062	PdeDst.n.u1Write = 1;
3063	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3064	PdeDst.n.u1Execute = 1;
3065	# else
3066	PdeDst.n.u1User = 1;
3067	PdeDst.n.u1Accessed = 1;
3068	# endif
3069	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3070
3071	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
3072	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
3073	return rc;
3074
3075	#else
3076	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
3077	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
3078	return VERR_INTERNAL_ERROR;
3079	#endif
3080	}
3081
3082
3083
3084	/**
3085	* Prefetch a page/set of pages.
3086	*
3087	* Typically used to sync commonly used pages before entering raw mode
3088	* after a CR3 reload.
3089	*
3090	* @returns VBox status code.
3091	* @param pVCpu The VMCPU handle.
3092	* @param GCPtrPage Page to invalidate.
3093	*/
3094	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
3095	{
3096	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
3097	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3098	/*
3099	* Check that all Guest levels thru the PDE are present, getting the
3100	* PD and PDE in the processes.
3101	*/
3102	int rc = VINF_SUCCESS;
3103	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3104	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3105	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3106	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
3107	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3108	unsigned iPDSrc;
3109	X86PDPE PdpeSrc;
3110	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
3111	if (!pPDSrc)
3112	return VINF_SUCCESS; /* not present */
3113	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3114	unsigned iPDSrc;
3115	PX86PML4E pPml4eSrc;
3116	X86PDPE PdpeSrc;
3117	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3118	if (!pPDSrc)
3119	return VINF_SUCCESS; /* not present */
3120	# endif
3121	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3122	# else
3123	PGSTPD pPDSrc = NULL;
3124	const unsigned iPDSrc = 0;
3125	GSTPDE PdeSrc;
3126
3127	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
3128	PdeSrc.n.u1Present = 1;
3129	PdeSrc.n.u1Write = 1;
3130	PdeSrc.n.u1Accessed = 1;
3131	PdeSrc.n.u1User = 1;
3132	# endif
3133
3134	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
3135	{
3136	PVM pVM = pVCpu->CTX_SUFF(pVM);
3137	pgmLock(pVM);
3138
3139	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3140	const X86PDE PdeDst = pgmShwGet32BitPDE(&pVCpu->pgm.s, GCPtrPage);
3141	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3142	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3143	PX86PDPAE pPDDst;
3144	X86PDEPAE PdeDst;
3145	# if PGM_GST_TYPE != PGM_TYPE_PAE
3146	X86PDPE PdpeSrc;
3147
3148	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3149	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3150	# endif
3151	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, &PdpeSrc, &pPDDst);
3152	if (rc != VINF_SUCCESS)
3153	{
3154	pgmUnlock(pVM);
3155	AssertRC(rc);
3156	return rc;
3157	}
3158	Assert(pPDDst);
3159	PdeDst = pPDDst->a[iPDDst];
3160
3161	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3162	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3163	PX86PDPAE pPDDst;
3164	X86PDEPAE PdeDst;
3165
3166	# if PGM_GST_TYPE == PGM_TYPE_PROT
3167	/* AMD-V nested paging */
3168	X86PML4E Pml4eSrc;
3169	X86PDPE PdpeSrc;
3170	PX86PML4E pPml4eSrc = &Pml4eSrc;
3171
3172	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3173	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
3174	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
3175	# endif
3176
3177	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
3178	if (rc != VINF_SUCCESS)
3179	{
3180	pgmUnlock(pVM);
3181	AssertRC(rc);
3182	return rc;
3183	}
3184	Assert(pPDDst);
3185	PdeDst = pPDDst->a[iPDDst];
3186	# endif
3187	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
3188	{
3189	if (!PdeDst.n.u1Present)
3190	{
3191	/** r=bird: This guy will set the A bit on the PDE, probably harmless. */
3192	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3193	}
3194	else
3195	{
3196	/** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3197	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3198	* makes no sense to prefetch more than one page.
3199	*/
3200	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3201	if (RT_SUCCESS(rc))
3202	rc = VINF_SUCCESS;
3203	}
3204	}
3205	pgmUnlock(pVM);
3206	}
3207	return rc;
3208
3209	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3210	return VINF_SUCCESS; /* ignore */
3211	#endif
3212	}
3213
3214
3215
3216
3217	/**
3218	* Syncs a page during a PGMVerifyAccess() call.
3219	*
3220	* @returns VBox status code (informational included).
3221	* @param pVCpu The VMCPU handle.
3222	* @param GCPtrPage The address of the page to sync.
3223	* @param fPage The effective guest page flags.
3224	* @param uErr The trap error code.
3225	*/
3226	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3227	{
3228	PVM pVM = pVCpu->CTX_SUFF(pVM);
3229
3230	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3231
3232	Assert(!HWACCMIsNestedPagingActive(pVM));
3233	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_TYPE_AMD64) \
3234	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3235
3236	# ifndef IN_RING0
3237	if (!(fPage & X86_PTE_US))
3238	{
3239	/*
3240	* Mark this page as safe.
3241	*/
3242	/** @todo not correct for pages that contain both code and data!! */
3243	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
3244	CSAMMarkPage(pVM, GCPtrPage, true);
3245	}
3246	# endif
3247
3248	/*
3249	* Get guest PD and index.
3250	*/
3251	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3252	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3253	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3254	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
3255	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3256	unsigned iPDSrc = 0;
3257	X86PDPE PdpeSrc;
3258	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
3259
3260	if (pPDSrc)
3261	{
3262	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3263	return VINF_EM_RAW_GUEST_TRAP;
3264	}
3265	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3266	unsigned iPDSrc;
3267	PX86PML4E pPml4eSrc;
3268	X86PDPE PdpeSrc;
3269	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3270	if (!pPDSrc)
3271	{
3272	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3273	return VINF_EM_RAW_GUEST_TRAP;
3274	}
3275	# endif
3276	# else
3277	PGSTPD pPDSrc = NULL;
3278	const unsigned iPDSrc = 0;
3279	# endif
3280	int rc = VINF_SUCCESS;
3281
3282	pgmLock(pVM);
3283
3284	/*
3285	* First check if the shadow pd is present.
3286	*/
3287	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3288	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
3289	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3290	PX86PDEPAE pPdeDst;
3291	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3292	PX86PDPAE pPDDst;
3293	# if PGM_GST_TYPE != PGM_TYPE_PAE
3294	X86PDPE PdpeSrc;
3295
3296	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3297	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3298	# endif
3299	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, &PdpeSrc, &pPDDst);
3300	if (rc != VINF_SUCCESS)
3301	{
3302	pgmUnlock(pVM);
3303	AssertRC(rc);
3304	return rc;
3305	}
3306	Assert(pPDDst);
3307	pPdeDst = &pPDDst->a[iPDDst];
3308
3309	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3310	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3311	PX86PDPAE pPDDst;
3312	PX86PDEPAE pPdeDst;
3313
3314	# if PGM_GST_TYPE == PGM_TYPE_PROT
3315	/* AMD-V nested paging */
3316	X86PML4E Pml4eSrc;
3317	X86PDPE PdpeSrc;
3318	PX86PML4E pPml4eSrc = &Pml4eSrc;
3319
3320	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3321	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
3322	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
3323	# endif
3324
3325	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
3326	if (rc != VINF_SUCCESS)
3327	{
3328	pgmUnlock(pVM);
3329	AssertRC(rc);
3330	return rc;
3331	}
3332	Assert(pPDDst);
3333	pPdeDst = &pPDDst->a[iPDDst];
3334	# endif
3335
3336	# if defined(IN_RC)
3337	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3338	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
3339	# endif
3340
3341	if (!pPdeDst->n.u1Present)
3342	{
3343	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3344	if (rc != VINF_SUCCESS)
3345	{
3346	# if defined(IN_RC)
3347	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3348	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
3349	# endif
3350	pgmUnlock(pVM);
3351	AssertRC(rc);
3352	return rc;
3353	}
3354	}
3355
3356	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3357	/* Check for dirty bit fault */
3358	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3359	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3360	Log(("PGMVerifyAccess: success (dirty)\n"));
3361	else
3362	{
3363	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3364	# else
3365	{
3366	GSTPDE PdeSrc;
3367	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
3368	PdeSrc.n.u1Present = 1;
3369	PdeSrc.n.u1Write = 1;
3370	PdeSrc.n.u1Accessed = 1;
3371	PdeSrc.n.u1User = 1;
3372
3373	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
3374	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3375	if (uErr & X86_TRAP_PF_US)
3376	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
3377	else /* supervisor */
3378	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3379
3380	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3381	if (RT_SUCCESS(rc))
3382	{
3383	/* Page was successfully synced */
3384	Log2(("PGMVerifyAccess: success (sync)\n"));
3385	rc = VINF_SUCCESS;
3386	}
3387	else
3388	{
3389	Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", GCPtrPage, rc));
3390	rc = VINF_EM_RAW_GUEST_TRAP;
3391	}
3392	}
3393	# if defined(IN_RC)
3394	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3395	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
3396	# endif
3397	pgmUnlock(pVM);
3398	return rc;
3399
3400	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3401
3402	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3403	return VERR_INTERNAL_ERROR;
3404	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3405	}
3406
3407	#undef MY_STAM_COUNTER_INC
3408	#define MY_STAM_COUNTER_INC(a) do { } while (0)
3409
3410
3411	/**
3412	* Syncs the paging hierarchy starting at CR3.
3413	*
3414	* @returns VBox status code, no specials.
3415	* @param pVCpu The VMCPU handle.
3416	* @param cr0 Guest context CR0 register
3417	* @param cr3 Guest context CR3 register
3418	* @param cr4 Guest context CR4 register
3419	* @param fGlobal Including global page directories or not
3420	*/
3421	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3422	{
3423	PVM pVM = pVCpu->CTX_SUFF(pVM);
3424
3425	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
3426	fGlobal = true; /* Change this CR3 reload to be a global one. */
3427
3428	LogFlow(("SyncCR3 %d\n", fGlobal));
3429
3430	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3431
3432	pgmLock(pVM);
3433	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
3434	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3435	if (pPool->cDirtyPages)
3436	pgmPoolResetDirtyPages(pVM);
3437	# endif
3438
3439	/*
3440	* Update page access handlers.
3441	* The virtual are always flushed, while the physical are only on demand.
3442	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3443	* have to look into that later because it will have a bad influence on the performance.
3444	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3445	* bird: Yes, but that won't work for aliases.
3446	*/
3447	/** @todo this MUST go away. See #1557. */
3448	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3449	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3450	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3451	pgmUnlock(pVM);
3452	#endif /* !NESTED && !EPT */
3453
3454	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3455	/*
3456	* Nested / EPT - almost no work.
3457	*/
3458	/** @todo check if this is really necessary; the call does it as well... */
3459	HWACCMFlushTLB(pVCpu);
3460	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3461	return VINF_SUCCESS;
3462
3463	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3464	/*
3465	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3466	* out the shadow parts when the guest modifies its tables.
3467	*/
3468	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3469	return VINF_SUCCESS;
3470
3471	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3472
3473	# ifndef PGM_WITHOUT_MAPPINGS
3474	/*
3475	* Check for and resolve conflicts with our guest mappings if they
3476	* are enabled and not fixed.
3477	*/
3478	if (pgmMapAreMappingsFloating(&pVM->pgm.s))
3479	{
3480	int rc = pgmMapResolveConflicts(pVM);
3481	Assert(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3);
3482	if (rc == VINF_PGM_SYNC_CR3)
3483	{
3484	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3485	return VINF_PGM_SYNC_CR3;
3486	}
3487	}
3488	# else
3489	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3490	# endif
3491	return VINF_SUCCESS;
3492	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3493	}
3494
3495
3496
3497
3498	#ifdef VBOX_STRICT
3499	#ifdef IN_RC
3500	# undef AssertMsgFailed
3501	# define AssertMsgFailed Log
3502	#endif
3503	#ifdef IN_RING3
3504	# include <VBox/dbgf.h>
3505
3506	/**
3507	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3508	*
3509	* @returns VBox status code (VINF_SUCCESS).
3510	* @param cr3 The root of the hierarchy.
3511	* @param crr The cr4, only PAE and PSE is currently used.
3512	* @param fLongMode Set if long mode, false if not long mode.
3513	* @param cMaxDepth Number of levels to dump.
3514	* @param pHlp Pointer to the output functions.
3515	*/
3516	RT_C_DECLS_BEGIN
3517	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
3518	RT_C_DECLS_END
3519
3520	#endif
3521
3522	/**
3523	* Checks that the shadow page table is in sync with the guest one.
3524	*
3525	* @returns The number of errors.
3526	* @param pVM The virtual machine.
3527	* @param pVCpu The VMCPU handle.
3528	* @param cr3 Guest context CR3 register
3529	* @param cr4 Guest context CR4 register
3530	* @param GCPtr Where to start. Defaults to 0.
3531	* @param cb How much to check. Defaults to everything.
3532	*/
3533	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3534	{
3535	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3536	return 0;
3537	#else
3538	unsigned cErrors = 0;
3539	PVM pVM = pVCpu->CTX_SUFF(pVM);
3540	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3541
3542	#if PGM_GST_TYPE == PGM_TYPE_PAE
3543	/** @todo currently broken; crashes below somewhere */
3544	AssertFailed();
3545	#endif
3546
3547	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
3548	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3549	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3550
3551	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3552	bool fBigPagesSupported = CPUMIsGuestPageSizeExtEnabled(pVCpu);
3553	# else
3554	bool fBigPagesSupported = true;
3555	# endif
3556	PPGMCPU pPGM = &pVCpu->pgm.s;
3557	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3558	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3559	# ifndef IN_RING0
3560	RTHCPHYS HCPhys; /* general usage. */
3561	# endif
3562	int rc;
3563
3564	/*
3565	* Check that the Guest CR3 and all its mappings are correct.
3566	*/
3567	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
3568	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3569	false);
3570	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3571	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3572	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3573	# else
3574	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3575	# endif
3576	AssertRCReturn(rc, 1);
3577	HCPhys = NIL_RTHCPHYS;
3578	rc = pgmRamGCPhys2HCPhys(&pVM->pgm.s, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
3579	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3580	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3581	pgmGstGet32bitPDPtr(pPGM);
3582	RTGCPHYS GCPhys;
3583	rc = PGMR3DbgR3Ptr2GCPhys(pVM, pPGM->pGst32BitPdR3, &GCPhys);
3584	AssertRCReturn(rc, 1);
3585	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3586	# endif
3587	# endif /* !IN_RING0 */
3588
3589	/*
3590	* Get and check the Shadow CR3.
3591	*/
3592	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3593	unsigned cPDEs = X86_PG_ENTRIES;
3594	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3595	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3596	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3597	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3598	# else
3599	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3600	# endif
3601	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3602	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3603	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3604	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3605	# endif
3606	if (cb != ~(RTGCPTR)0)
3607	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3608
3609	/** @todo call the other two PGMAssert() functions. /
3610
3611	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3612	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3613
3614	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3615	{
3616	PPGMPOOLPAGE pShwPdpt = NULL;
3617	PX86PML4E pPml4eSrc;
3618	PX86PML4E pPml4eDst;
3619	RTGCPHYS GCPhysPdptSrc;
3620
3621	pPml4eSrc = pgmGstGetLongModePML4EPtr(&pVCpu->pgm.s, iPml4);
3622	pPml4eDst = pgmShwGetLongModePML4EPtr(&pVCpu->pgm.s, iPml4);
3623
3624	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3625	if (!pPml4eDst->n.u1Present)
3626	{
3627	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3628	continue;
3629	}
3630
3631	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3632	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK_FULL;
3633
3634	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3635	{
3636	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3637	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3638	cErrors++;
3639	continue;
3640	}
3641
3642	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3643	{
3644	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3645	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3646	cErrors++;
3647	continue;
3648	}
3649
3650	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3651	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3652	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3653	{
3654	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3655	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3656	cErrors++;
3657	continue;
3658	}
3659	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3660	{
3661	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3662
3663	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3664	/*
3665	* Check the PDPTEs too.
3666	*/
3667	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3668
3669	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3670	{
3671	unsigned iPDSrc = 0; /* initialized to shut up gcc */
3672	PPGMPOOLPAGE pShwPde = NULL;
3673	PX86PDPE pPdpeDst;
3674	RTGCPHYS GCPhysPdeSrc;
3675	# if PGM_GST_TYPE == PGM_TYPE_PAE
3676	X86PDPE PdpeSrc;
3677	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtr, &iPDSrc, &PdpeSrc);
3678	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVCpu->pgm.s);
3679	# else
3680	PX86PML4E pPml4eSrcIgn;
3681	X86PDPE PdpeSrc;
3682	PX86PDPT pPdptDst;
3683	PX86PDPAE pPDDst;
3684	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtr, &pPml4eSrcIgn, &PdpeSrc, &iPDSrc);
3685
3686	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
3687	if (rc != VINF_SUCCESS)
3688	{
3689	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3690	GCPtr += 512 * _2M;
3691	continue; /* next PDPTE */
3692	}
3693	Assert(pPDDst);
3694	# endif
3695	Assert(iPDSrc == 0);
3696
3697	pPdpeDst = &pPdptDst->a[iPdpt];
3698
3699	if (!pPdpeDst->n.u1Present)
3700	{
3701	GCPtr += 512 * _2M;
3702	continue; /* next PDPTE */
3703	}
3704
3705	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3706	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3707
3708	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3709	{
3710	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3711	GCPtr += 512 * _2M;
3712	cErrors++;
3713	continue;
3714	}
3715
3716	if (GCPhysPdeSrc != pShwPde->GCPhys)
3717	{
3718	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3719	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3720	# else
3721	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3722	# endif
3723	GCPtr += 512 * _2M;
3724	cErrors++;
3725	continue;
3726	}
3727
3728	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3729	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3730	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3731	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3732	{
3733	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3734	GCPtr += 512 * _2M;
3735	cErrors++;
3736	continue;
3737	}
3738	# endif
3739
3740	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3741	{
3742	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3743	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3744	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
3745	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3746	PCX86PD pPDDst = pgmShwGet32BitPDPtr(&pVCpu->pgm.s);
3747	# endif
3748	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3749	/*
3750	* Iterate the shadow page directory.
3751	*/
3752	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3753	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3754
3755	for (;
3756	iPDDst < cPDEs;
3757	iPDDst++, GCPtr += cIncrement)
3758	{
3759	# if PGM_SHW_TYPE == PGM_TYPE_PAE
3760	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pPGM, GCPtr);
3761	# else
3762	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3763	# endif
3764	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3765	{
3766	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3767	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3768	{
3769	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3770	cErrors++;
3771	continue;
3772	}
3773	}
3774	else if ( (PdeDst.u & X86_PDE_P)
3775	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3776	)
3777	{
3778	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3779	PPGMPOOLPAGE pPoolPage = pgmPoolGetPage(pPool, HCPhysShw);
3780	if (!pPoolPage)
3781	{
3782	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
3783	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3784	cErrors++;
3785	continue;
3786	}
3787	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR(pVM, pPoolPage);
3788
3789	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3790	{
3791	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
3792	GCPtr, (uint64_t)PdeDst.u));
3793	cErrors++;
3794	}
3795
3796	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3797	{
3798	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
3799	GCPtr, (uint64_t)PdeDst.u));
3800	cErrors++;
3801	}
3802
3803	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3804	if (!PdeSrc.n.u1Present)
3805	{
3806	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3807	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3808	cErrors++;
3809	continue;
3810	}
3811
3812	if ( !PdeSrc.b.u1Size
3813	\|\| !fBigPagesSupported)
3814	{
3815	GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
3816	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3817	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3818	# endif
3819	}
3820	else
3821	{
3822	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3823	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3824	{
3825	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3826	GCPtr, (uint64_t)PdeSrc.u));
3827	cErrors++;
3828	continue;
3829	}
3830	# endif
3831	GCPhysGst = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
3832	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3833	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3834	# endif
3835	}
3836
3837	if ( pPoolPage->enmKind
3838	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3839	{
3840	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
3841	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3842	cErrors++;
3843	}
3844
3845	PPGMPAGE pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
3846	if (!pPhysPage)
3847	{
3848	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3849	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3850	cErrors++;
3851	continue;
3852	}
3853
3854	if (GCPhysGst != pPoolPage->GCPhys)
3855	{
3856	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
3857	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3858	cErrors++;
3859	continue;
3860	}
3861
3862	if ( !PdeSrc.b.u1Size
3863	\|\| !fBigPagesSupported)
3864	{
3865	/*
3866	* Page Table.
3867	*/
3868	const GSTPT *pPTSrc;
3869	rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3870	if (RT_FAILURE(rc))
3871	{
3872	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3873	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3874	cErrors++;
3875	continue;
3876	}
3877	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3878	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3879	{
3880	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3881	// (This problem will go away when/if we shadow multiple CR3s.)
3882	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3883	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3884	cErrors++;
3885	continue;
3886	}
3887	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3888	{
3889	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
3890	GCPtr, (uint64_t)PdeDst.u));
3891	cErrors++;
3892	continue;
3893	}
3894
3895	/* iterate the page table. */
3896	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3897	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3898	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3899	# else
3900	const unsigned offPTSrc = 0;
3901	# endif
3902	for (unsigned iPT = 0, off = 0;
3903	iPT < RT_ELEMENTS(pPTDst->a);
3904	iPT++, off += PAGE_SIZE)
3905	{
3906	const SHWPTE PteDst = pPTDst->a[iPT];
3907
3908	/* skip not-present entries. */
3909	if (!(PteDst.u & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3910	continue;
3911	Assert(PteDst.n.u1Present);
3912
3913	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3914	if (!PteSrc.n.u1Present)
3915	{
3916	# ifdef IN_RING3
3917	PGMAssertHandlerAndFlagsInSync(pVM);
3918	PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
3919	# endif
3920	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
3921	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3922	(PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
3923	cErrors++;
3924	continue;
3925	}
3926
3927	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3928	# if 1 /** @todo sync accessed bit properly... */
3929	fIgnoreFlags \|= X86_PTE_A;
3930	# endif
3931
3932	/* match the physical addresses */
3933	HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
3934	GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
3935
3936	# ifdef IN_RING3
3937	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3938	if (RT_FAILURE(rc))
3939	{
3940	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
3941	{
3942	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3943	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3944	cErrors++;
3945	continue;
3946	}
3947	}
3948	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
3949	{
3950	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3951	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3952	cErrors++;
3953	continue;
3954	}
3955	# endif
3956
3957	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
3958	if (!pPhysPage)
3959	{
3960	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3961	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
3962	{
3963	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3964	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3965	cErrors++;
3966	continue;
3967	}
3968	# endif
3969	if (PteDst.n.u1Write)
3970	{
3971	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3972	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3973	cErrors++;
3974	}
3975	fIgnoreFlags \|= X86_PTE_RW;
3976	}
3977	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
3978	{
3979	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3980	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3981	cErrors++;
3982	continue;
3983	}
3984
3985	/* flags */
3986	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
3987	{
3988	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
3989	{
3990	if (PteDst.n.u1Write)
3991	{
3992	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
3993	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3994	cErrors++;
3995	continue;
3996	}
3997	fIgnoreFlags \|= X86_PTE_RW;
3998	}
3999	else
4000	{
4001	if (PteDst.n.u1Present)
4002	{
4003	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4004	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4005	cErrors++;
4006	continue;
4007	}
4008	fIgnoreFlags \|= X86_PTE_P;
4009	}
4010	}
4011	else
4012	{
4013	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
4014	{
4015	if (PteDst.n.u1Write)
4016	{
4017	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4018	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4019	cErrors++;
4020	continue;
4021	}
4022	if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
4023	{
4024	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4025	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4026	cErrors++;
4027	continue;
4028	}
4029	if (PteDst.n.u1Dirty)
4030	{
4031	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4032	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4033	cErrors++;
4034	}
4035	# if 0 /** @todo sync access bit properly... */
4036	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4037	{
4038	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4039	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4040	cErrors++;
4041	}
4042	fIgnoreFlags \|= X86_PTE_RW;
4043	# else
4044	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4045	# endif
4046	}
4047	else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4048	{
4049	/* access bit emulation (not implemented). */
4050	if (PteSrc.n.u1Accessed \|\| PteDst.n.u1Present)
4051	{
4052	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4053	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4054	cErrors++;
4055	continue;
4056	}
4057	if (!PteDst.n.u1Accessed)
4058	{
4059	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4060	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4061	cErrors++;
4062	}
4063	fIgnoreFlags \|= X86_PTE_P;
4064	}
4065	# ifdef DEBUG_sandervl
4066	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4067	# endif
4068	}
4069
4070	if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4071	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
4072	)
4073	{
4074	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4075	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4076	fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4077	cErrors++;
4078	continue;
4079	}
4080	} /* foreach PTE */
4081	}
4082	else
4083	{
4084	/*
4085	* Big Page.
4086	*/
4087	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4088	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4089	{
4090	if (PdeDst.n.u1Write)
4091	{
4092	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4093	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4094	cErrors++;
4095	continue;
4096	}
4097	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4098	{
4099	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4100	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4101	cErrors++;
4102	continue;
4103	}
4104	# if 0 /** @todo sync access bit properly... */
4105	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4106	{
4107	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4108	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4109	cErrors++;
4110	}
4111	fIgnoreFlags \|= X86_PTE_RW;
4112	# else
4113	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4114	# endif
4115	}
4116	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4117	{
4118	/* access bit emulation (not implemented). */
4119	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4120	{
4121	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4122	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4123	cErrors++;
4124	continue;
4125	}
4126	if (!PdeDst.n.u1Accessed)
4127	{
4128	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4129	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4130	cErrors++;
4131	}
4132	fIgnoreFlags \|= X86_PTE_P;
4133	}
4134
4135	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4136	{
4137	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4138	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4139	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4140	cErrors++;
4141	}
4142
4143	/* iterate the page table. */
4144	for (unsigned iPT = 0, off = 0;
4145	iPT < RT_ELEMENTS(pPTDst->a);
4146	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
4147	{
4148	const SHWPTE PteDst = pPTDst->a[iPT];
4149
4150	if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4151	{
4152	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4153	GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4154	cErrors++;
4155	}
4156
4157	/* skip not-present entries. */
4158	if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
4159	continue;
4160
4161	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4162
4163	/* match the physical addresses */
4164	HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
4165
4166	# ifdef IN_RING3
4167	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4168	if (RT_FAILURE(rc))
4169	{
4170	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4171	{
4172	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4173	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4174	cErrors++;
4175	}
4176	}
4177	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4178	{
4179	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4180	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4181	cErrors++;
4182	continue;
4183	}
4184	# endif
4185	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
4186	if (!pPhysPage)
4187	{
4188	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4189	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4190	{
4191	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4192	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4193	cErrors++;
4194	continue;
4195	}
4196	# endif
4197	if (PteDst.n.u1Write)
4198	{
4199	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4200	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4201	cErrors++;
4202	}
4203	fIgnoreFlags \|= X86_PTE_RW;
4204	}
4205	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4206	{
4207	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4208	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4209	cErrors++;
4210	continue;
4211	}
4212
4213	/* flags */
4214	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4215	{
4216	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4217	{
4218	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4219	{
4220	if (PteDst.n.u1Write)
4221	{
4222	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4223	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4224	cErrors++;
4225	continue;
4226	}
4227	fIgnoreFlags \|= X86_PTE_RW;
4228	}
4229	}
4230	else
4231	{
4232	if (PteDst.n.u1Present)
4233	{
4234	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4235	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4236	cErrors++;
4237	continue;
4238	}
4239	fIgnoreFlags \|= X86_PTE_P;
4240	}
4241	}
4242
4243	if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4244	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
4245	)
4246	{
4247	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4248	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4249	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4250	cErrors++;
4251	continue;
4252	}
4253	} /* for each PTE */
4254	}
4255	}
4256	/* not present */
4257
4258	} /* for each PDE */
4259
4260	} /* for each PDPTE */
4261
4262	} /* for each PML4E */
4263
4264	# ifdef DEBUG
4265	if (cErrors)
4266	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4267	# endif
4268
4269	#endif /* GST == 32BIT, PAE or AMD64 */
4270	return cErrors;
4271
4272	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4273	}
4274	#endif /* VBOX_STRICT */
4275
4276
4277	/**
4278	* Sets up the CR3 for shadow paging
4279	*
4280	* @returns Strict VBox status code.
4281	* @retval VINF_SUCCESS.
4282	*
4283	* @param pVCpu The VMCPU handle.
4284	* @param GCPhysCR3 The physical address in the CR3 register.
4285	*/
4286	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3)
4287	{
4288	PVM pVM = pVCpu->CTX_SUFF(pVM);
4289
4290	/* Update guest paging info. */
4291	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4292	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4293	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4294
4295	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4296
4297	/*
4298	* Map the page CR3 points at.
4299	*/
4300	RTHCPTR HCPtrGuestCR3;
4301	RTHCPHYS HCPhysGuestCR3;
4302	pgmLock(pVM);
4303	PPGMPAGE pPageCR3 = pgmPhysGetPage(&pVM->pgm.s, GCPhysCR3);
4304	AssertReturn(pPageCR3, VERR_INTERNAL_ERROR_2);
4305	HCPhysGuestCR3 = PGM_PAGE_GET_HCPHYS(pPageCR3);
4306	/** @todo this needs some reworking wrt. locking. */
4307	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4308	HCPtrGuestCR3 = NIL_RTHCPTR;
4309	int rc = VINF_SUCCESS;
4310	# else
4311	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPageCR3, GCPhysCR3 & GST_CR3_PAGE_MASK, (void )&HCPtrGuestCR3); / @todo r=bird: This GCPhysCR3 masking isn't necessary. */
4312	# endif
4313	pgmUnlock(pVM);
4314	if (RT_SUCCESS(rc))
4315	{
4316	rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
4317	if (RT_SUCCESS(rc))
4318	{
4319	# ifdef IN_RC
4320	PGM_INVL_PG(pVCpu, pVM->pgm.s.GCPtrCR3Mapping);
4321	# endif
4322	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4323	pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
4324	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4325	pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
4326	# endif
4327	pVCpu->pgm.s.pGst32BitPdRC = (RCPTRTYPE(PX86PD))(RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping;
4328
4329	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4330	unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
4331	pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4332	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4333	pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4334	# endif
4335	pVCpu->pgm.s.pGstPaePdptRC = (RCPTRTYPE(PX86PDPT))((RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping + off);
4336	Log(("Cached mapping %RRv\n", pVCpu->pgm.s.pGstPaePdptRC));
4337
4338	/*
4339	* Map the 4 PDs too.
4340	*/
4341	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(&pVCpu->pgm.s);
4342	RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
4343	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
4344	{
4345	if (pGuestPDPT->a[i].n.u1Present)
4346	{
4347	RTHCPTR HCPtr;
4348	RTHCPHYS HCPhys;
4349	RTGCPHYS GCPhys = pGuestPDPT->a[i].u & X86_PDPE_PG_MASK;
4350	pgmLock(pVM);
4351	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
4352	AssertReturn(pPage, VERR_INTERNAL_ERROR_2);
4353	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
4354	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4355	HCPtr = NIL_RTHCPTR;
4356	int rc2 = VINF_SUCCESS;
4357	# else
4358	int rc2 = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, (void **)&HCPtr);
4359	# endif
4360	pgmUnlock(pVM);
4361	if (RT_SUCCESS(rc2))
4362	{
4363	rc = PGMMap(pVM, GCPtr, HCPhys, PAGE_SIZE, 0);
4364	AssertRCReturn(rc, rc);
4365
4366	pVCpu->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
4367	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4368	pVCpu->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
4369	# endif
4370	pVCpu->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))(RTRCUINTPTR)GCPtr;
4371	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
4372	# ifdef IN_RC
4373	PGM_INVL_PG(pVCpu, GCPtr);
4374	# endif
4375	continue;
4376	}
4377	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
4378	}
4379
4380	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4381	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4382	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4383	# endif
4384	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4385	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4386	# ifdef IN_RC
4387	PGM_INVL_PG(pVCpu, GCPtr); /** @todo this shouldn't be necessary? */
4388	# endif
4389	}
4390
4391	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4392	pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
4393	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4394	pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
4395	# endif
4396	# endif
4397	}
4398	else
4399	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4400	}
4401	else
4402	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4403
4404	#else /* prot/real stub */
4405	int rc = VINF_SUCCESS;
4406	#endif
4407
4408	/* Update shadow paging info for guest modes with paging (32, pae, 64). */
4409	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4410	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4411	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4412	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
4413	&& PGM_GST_TYPE != PGM_TYPE_PROT))
4414
4415	Assert(!HWACCMIsNestedPagingActive(pVM));
4416
4417	/*
4418	* Update the shadow root page as well since that's not fixed.
4419	*/
4420	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4421	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
4422	uint32_t iOldShwUserTable = pVCpu->pgm.s.iShwUserTable;
4423	uint32_t iOldShwUser = pVCpu->pgm.s.iShwUser;
4424	PPGMPOOLPAGE pNewShwPageCR3;
4425
4426	pgmLock(pVM);
4427
4428	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4429	if (pPool->cDirtyPages)
4430	pgmPoolResetDirtyPages(pVM);
4431	# endif
4432
4433	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4434	rc = pgmPoolAlloc(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, SHW_POOL_ROOT_IDX, GCPhysCR3 >> PAGE_SHIFT, &pNewShwPageCR3, true /* lock page */);
4435	AssertFatalRC(rc);
4436	rc = VINF_SUCCESS;
4437
4438	# ifdef IN_RC
4439	/*
4440	* WARNING! We can't deal with jumps to ring 3 in the code below as the
4441	* state will be inconsistent! Flush important things now while
4442	* we still can and then make sure there are no ring-3 calls.
4443	*/
4444	REMNotifyHandlerPhysicalFlushIfAlmostFull(pVM, pVCpu);
4445	VMMRZCallRing3Disable(pVCpu);
4446	# endif
4447
4448	pVCpu->pgm.s.iShwUser = SHW_POOL_ROOT_IDX;
4449	pVCpu->pgm.s.iShwUserTable = GCPhysCR3 >> PAGE_SHIFT;
4450	pVCpu->pgm.s.CTX_SUFF(pShwPageCR3) = pNewShwPageCR3;
4451	# ifdef IN_RING0
4452	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4453	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4454	# elif defined(IN_RC)
4455	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4456	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4457	# else
4458	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4459	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4460	# endif
4461
4462	# ifndef PGM_WITHOUT_MAPPINGS
4463	/*
4464	* Apply all hypervisor mappings to the new CR3.
4465	* Note that SyncCR3 will be executed in case CR3 is changed in a guest paging mode; this will
4466	* make sure we check for conflicts in the new CR3 root.
4467	*/
4468	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4469	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL) \|\| VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4470	# endif
4471	rc = pgmMapActivateCR3(pVM, pNewShwPageCR3);
4472	AssertRCReturn(rc, rc);
4473	# endif
4474
4475	/* Set the current hypervisor CR3. */
4476	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
4477	SELMShadowCR3Changed(pVM, pVCpu);
4478
4479	# ifdef IN_RC
4480	/* NOTE: The state is consistent again. */
4481	VMMRZCallRing3Enable(pVCpu);
4482	# endif
4483
4484	/* Clean up the old CR3 root. */
4485	if ( pOldShwPageCR3
4486	&& pOldShwPageCR3 != pNewShwPageCR3 /* @todo can happen due to incorrect syncing between REM & PGM; find the real cause */)
4487	{
4488	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
4489	# ifndef PGM_WITHOUT_MAPPINGS
4490	/* Remove the hypervisor mappings from the shadow page table. */
4491	pgmMapDeactivateCR3(pVM, pOldShwPageCR3);
4492	# endif
4493	/* Mark the page as unlocked; allow flushing again. */
4494	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
4495
4496	pgmPoolFreeByPage(pPool, pOldShwPageCR3, iOldShwUser, iOldShwUserTable);
4497	}
4498	pgmUnlock(pVM);
4499	# endif
4500
4501	return rc;
4502	}
4503
4504	/**
4505	* Unmaps the shadow CR3.
4506	*
4507	* @returns VBox status, no specials.
4508	* @param pVCpu The VMCPU handle.
4509	*/
4510	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu)
4511	{
4512	LogFlow(("UnmapCR3\n"));
4513
4514	int rc = VINF_SUCCESS;
4515	PVM pVM = pVCpu->CTX_SUFF(pVM);
4516
4517	/*
4518	* Update guest paging info.
4519	*/
4520	#if PGM_GST_TYPE == PGM_TYPE_32BIT
4521	pVCpu->pgm.s.pGst32BitPdR3 = 0;
4522	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4523	pVCpu->pgm.s.pGst32BitPdR0 = 0;
4524	# endif
4525	pVCpu->pgm.s.pGst32BitPdRC = 0;
4526
4527	#elif PGM_GST_TYPE == PGM_TYPE_PAE
4528	pVCpu->pgm.s.pGstPaePdptR3 = 0;
4529	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4530	pVCpu->pgm.s.pGstPaePdptR0 = 0;
4531	# endif
4532	pVCpu->pgm.s.pGstPaePdptRC = 0;
4533	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4534	{
4535	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4536	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4537	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4538	# endif
4539	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4540	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4541	}
4542
4543	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4544	pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
4545	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4546	pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
4547	# endif
4548
4549	#else /* prot/real mode stub */
4550	/* nothing to do */
4551	#endif
4552
4553	#if !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
4554	/*
4555	* Update shadow paging info.
4556	*/
4557	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4558	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4559	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
4560
4561	# if PGM_GST_TYPE != PGM_TYPE_REAL
4562	Assert(!HWACCMIsNestedPagingActive(pVM));
4563	# endif
4564
4565	pgmLock(pVM);
4566
4567	# ifndef PGM_WITHOUT_MAPPINGS
4568	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4569	/* Remove the hypervisor mappings from the shadow page table. */
4570	pgmMapDeactivateCR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4571	# endif
4572
4573	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4574	{
4575	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4576
4577	Assert(pVCpu->pgm.s.iShwUser != PGMPOOL_IDX_NESTED_ROOT);
4578
4579	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4580	if (pPool->cDirtyPages)
4581	pgmPoolResetDirtyPages(pVM);
4582	# endif
4583
4584	/* Mark the page as unlocked; allow flushing again. */
4585	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4586
4587	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), pVCpu->pgm.s.iShwUser, pVCpu->pgm.s.iShwUserTable);
4588	pVCpu->pgm.s.pShwPageCR3R3 = 0;
4589	pVCpu->pgm.s.pShwPageCR3R0 = 0;
4590	pVCpu->pgm.s.pShwPageCR3RC = 0;
4591	pVCpu->pgm.s.iShwUser = 0;
4592	pVCpu->pgm.s.iShwUserTable = 0;
4593	}
4594	pgmUnlock(pVM);
4595	# endif
4596	#endif /* !IN_RC*/
4597
4598	return rc;
4599	}

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 27254

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