VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PDMAll.cpp@ 20037

最後變更 在這個檔案從20037是 20037,由 vboxsync 提交於 16 年 前

TPR read/write updates
  • 屬性 svn:eol-style 設為 native
  • 屬性 svn:keywords 設為 Id
檔案大小: 11.2 KB
行 
1/* $Id: PDMAll.cpp 20037 2009-05-26 13:25:48Z vboxsync $ */
2/** @file
3 * PDM Critical Sections
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.alldomusa.eu.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_PDM
27#include "PDMInternal.h"
28#include <VBox/pdm.h>
29#include <VBox/mm.h>
30#include <VBox/vm.h>
31#include <VBox/err.h>
32
33#include <VBox/log.h>
34#include <iprt/asm.h>
35#include <iprt/assert.h>
36
37
38/**
39 * Gets the pending interrupt.
40 *
41 * @returns VBox status code.
42 * @param pVCpu VMCPU handle.
43 * @param pu8Interrupt Where to store the interrupt on success.
44 */
45VMMDECL(int) PDMGetInterrupt(PVMCPU pVCpu, uint8_t *pu8Interrupt)
46{
47 PVM pVM = pVCpu->CTX_SUFF(pVM);
48
49 pdmLock(pVM);
50
51 /*
52 * The local APIC has a higer priority than the PIC.
53 */
54 if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INTERRUPT_APIC))
55 {
56 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_APIC);
57 Assert(pVM->pdm.s.Apic.CTX_SUFF(pDevIns));
58 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnGetInterrupt));
59 int i = pVM->pdm.s.Apic.CTX_SUFF(pfnGetInterrupt)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns));
60 AssertMsg(i <= 255 && i >= 0, ("i=%d\n", i));
61 if (i >= 0)
62 {
63 pdmUnlock(pVM);
64 *pu8Interrupt = (uint8_t)i;
65 return VINF_SUCCESS;
66 }
67 }
68
69 /*
70 * Check the PIC.
71 */
72 if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INTERRUPT_PIC))
73 {
74 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
75 Assert(pVM->pdm.s.Pic.CTX_SUFF(pDevIns));
76 Assert(pVM->pdm.s.Pic.CTX_SUFF(pfnGetInterrupt));
77 int i = pVM->pdm.s.Pic.CTX_SUFF(pfnGetInterrupt)(pVM->pdm.s.Pic.CTX_SUFF(pDevIns));
78 AssertMsg(i <= 255 && i >= 0, ("i=%d\n", i));
79 if (i >= 0)
80 {
81 pdmUnlock(pVM);
82 *pu8Interrupt = (uint8_t)i;
83 return VINF_SUCCESS;
84 }
85 }
86
87 /** @todo Figure out exactly why we can get here without anything being set. (REM) */
88
89 pdmUnlock(pVM);
90 return VERR_NO_DATA;
91}
92
93
94/**
95 * Sets the pending interrupt.
96 *
97 * @returns VBox status code.
98 * @param pVM VM handle.
99 * @param u8Irq The IRQ line.
100 * @param u8Level The new level.
101 */
102VMMDECL(int) PDMIsaSetIrq(PVM pVM, uint8_t u8Irq, uint8_t u8Level)
103{
104 pdmLock(pVM);
105
106 int rc = VERR_PDM_NO_PIC_INSTANCE;
107 if (pVM->pdm.s.Pic.CTX_SUFF(pDevIns))
108 {
109 Assert(pVM->pdm.s.Pic.CTX_SUFF(pfnSetIrq));
110 pVM->pdm.s.Pic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.Pic.CTX_SUFF(pDevIns), u8Irq, u8Level);
111 rc = VINF_SUCCESS;
112 }
113
114 if (pVM->pdm.s.IoApic.CTX_SUFF(pDevIns))
115 {
116 Assert(pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq));
117 pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), u8Irq, u8Level);
118 rc = VINF_SUCCESS;
119 }
120
121 pdmUnlock(pVM);
122 return rc;
123}
124
125
126/**
127 * Sets the pending I/O APIC interrupt.
128 *
129 * @returns VBox status code.
130 * @param pVM VM handle.
131 * @param u8Irq The IRQ line.
132 * @param u8Level The new level.
133 */
134VMMDECL(int) PDMIoApicSetIrq(PVM pVM, uint8_t u8Irq, uint8_t u8Level)
135{
136 if (pVM->pdm.s.IoApic.CTX_SUFF(pDevIns))
137 {
138 Assert(pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq));
139 pdmLock(pVM);
140 pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), u8Irq, u8Level);
141 pdmUnlock(pVM);
142 return VINF_SUCCESS;
143 }
144 return VERR_PDM_NO_PIC_INSTANCE;
145}
146
147
148/**
149 * Returns presence of an IO-APIC
150 *
151 * @returns VBox true if IO-APIC is present
152 * @param pVM VM handle.
153 */
154VMMDECL(bool) PDMHasIoApic(PVM pVM)
155{
156 return pVM->pdm.s.IoApic.CTX_SUFF(pDevIns) != NULL;
157}
158
159
160/**
161 * Set the APIC base.
162 *
163 * @returns VBox status code.
164 * @param pVM VM handle.
165 * @param u64Base The new base.
166 */
167VMMDECL(int) PDMApicSetBase(PVM pVM, uint64_t u64Base)
168{
169 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
170 {
171 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnSetBase));
172 pdmLock(pVM);
173 pVM->pdm.s.Apic.CTX_SUFF(pfnSetBase)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), u64Base);
174 pdmUnlock(pVM);
175 return VINF_SUCCESS;
176 }
177 return VERR_PDM_NO_APIC_INSTANCE;
178}
179
180
181/**
182 * Get the APIC base.
183 *
184 * @returns VBox status code.
185 * @param pVM VM handle.
186 * @param pu64Base Where to store the APIC base.
187 */
188VMMDECL(int) PDMApicGetBase(PVM pVM, uint64_t *pu64Base)
189{
190 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
191 {
192 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnGetBase));
193 pdmLock(pVM);
194 *pu64Base = pVM->pdm.s.Apic.CTX_SUFF(pfnGetBase)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns));
195 pdmUnlock(pVM);
196 return VINF_SUCCESS;
197 }
198 *pu64Base = 0;
199 return VERR_PDM_NO_APIC_INSTANCE;
200}
201
202
203/**
204 * Check if the APIC has a pending interrupt/if a TPR change would active one.
205 *
206 * @returns VINF_SUCCESS or VERR_PDM_NO_APIC_INSTANCE.
207 * @param pDevIns Device instance of the APIC.
208 * @param pfPending Pending state (out).
209 */
210VMMDECL(int) PDMApicHasPendingIrq(PVM pVM, bool *pfPending)
211{
212 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
213 {
214 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnSetTPR));
215 pdmLock(pVM);
216 *pfPending = pVM->pdm.s.Apic.CTX_SUFF(pfnHasPendingIrq)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns));
217 pdmUnlock(pVM);
218 return VINF_SUCCESS;
219 }
220 return VERR_PDM_NO_APIC_INSTANCE;
221}
222
223
224/**
225 * Set the TPR (task priority register).
226 *
227 * @returns VBox status code.
228 * @param pVCpu VMCPU handle.
229 * @param u8TPR The new TPR.
230 * @param fMMIOFormat Update as if MMIO write to ApicBase + 0x80
231 */
232VMMDECL(int) PDMApicSetTPREx(PVMCPU pVCpu, uint8_t u8TPR, bool fMMIOFormat)
233{
234 PVM pVM = pVCpu->CTX_SUFF(pVM);
235 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
236 {
237 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnSetTPR));
238 pdmLock(pVM);
239 pVM->pdm.s.Apic.CTX_SUFF(pfnSetTPR)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu->idCpu, u8TPR, fMMIOFormat);
240 pdmUnlock(pVM);
241 return VINF_SUCCESS;
242 }
243 return VERR_PDM_NO_APIC_INSTANCE;
244}
245
246/**
247 * Set the TPR (task priority register).
248 *
249 * @returns VBox status code.
250 * @param pVCpu VMCPU handle.
251 * @param u8TPR The new TPR.
252 */
253VMMDECL(int) PDMApicSetTPR(PVMCPU pVCpu, uint8_t u8TPR)
254{
255 return PDMApicSetTPREx(pVCpu, u8TPR, false /* TPR only */);
256}
257
258/**
259 * Get the TPR (task priority register).
260 *
261 * @returns The current TPR.
262 * @param pVCpu VMCPU handle.
263 * @param pu8TPR Where to store the TRP.
264 * @param fMMIOFormat Return as if MMIO read from ApicBase + 0x80
265 * @param pfPending Pending interrupt state (out).
266*/
267VMMDECL(int) PDMApicGetTPREx(PVMCPU pVCpu, uint8_t *pu8TPR, bool fMMIOFormat, bool *pfPending)
268{
269 PVM pVM = pVCpu->CTX_SUFF(pVM);
270 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
271 {
272 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnGetTPR));
273 pdmLock(pVM);
274 *pu8TPR = pVM->pdm.s.Apic.CTX_SUFF(pfnGetTPR)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu->idCpu, fMMIOFormat);
275 if (pfPending)
276 *pfPending = pVM->pdm.s.Apic.CTX_SUFF(pfnHasPendingIrq)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns));
277 pdmUnlock(pVM);
278 return VINF_SUCCESS;
279 }
280 *pu8TPR = 0;
281 return VERR_PDM_NO_APIC_INSTANCE;
282}
283
284
285/**
286 * Get the TPR (task priority register).
287 *
288 * @returns The current TPR.
289 * @param pVCpu VMCPU handle.
290 * @param pu8TPR Where to store the TRP.
291 * @param pfPending Pending interrupt state (out).
292*/
293VMMDECL(int) PDMApicGetTPR(PVMCPU pVCpu, uint8_t *pu8TPR, bool *pfPending)
294{
295 return PDMApicGetTPREx(pVCpu, pu8TPR, false /* TPR only */, pfPending);
296}
297
298/**
299 * Write MSR in APIC range.
300 *
301 * @returns VBox status code.
302 * @param pVM VM handle.
303 * @param iCpu Target CPU.
304 * @param u32Reg MSR to write.
305 * @param u64Value Value to write.
306 */
307VMMDECL(int) PDMApicWriteMSR(PVM pVM, VMCPUID iCpu, uint32_t u32Reg, uint64_t u64Value)
308{
309 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
310 {
311 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnWriteMSR));
312 pdmLock(pVM);
313 pVM->pdm.s.Apic.CTX_SUFF(pfnWriteMSR)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), iCpu, u32Reg, u64Value);
314 pdmUnlock(pVM);
315 return VINF_SUCCESS;
316 }
317 return VERR_PDM_NO_APIC_INSTANCE;
318}
319
320/**
321 * Read MSR in APIC range.
322 *
323 * @returns VBox status code.
324 * @param pVM VM handle.
325 * @param iCpu Target CPU.
326 * @param u32Reg MSR to read.
327 * @param pu64Value Value read.
328 */
329VMMDECL(int) PDMApicReadMSR(PVM pVM, VMCPUID iCpu, uint32_t u32Reg, uint64_t *pu64Value)
330{
331 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
332 {
333 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnReadMSR));
334 pdmLock(pVM);
335 pVM->pdm.s.Apic.CTX_SUFF(pfnReadMSR)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), iCpu, u32Reg, pu64Value);
336 pdmUnlock(pVM);
337 return VINF_SUCCESS;
338 }
339 return VERR_PDM_NO_APIC_INSTANCE;
340}
341
342
343/**
344 * Locks PDM.
345 * This might call back to Ring-3 in order to deal with lock contention in GC and R3.
346 *
347 * @param pVM The VM handle.
348 */
349void pdmLock(PVM pVM)
350{
351#ifdef IN_RING3
352 int rc = PDMCritSectEnter(&pVM->pdm.s.CritSect, VERR_INTERNAL_ERROR);
353#else
354 int rc = PDMCritSectEnter(&pVM->pdm.s.CritSect, VERR_GENERAL_FAILURE);
355 if (rc == VERR_GENERAL_FAILURE)
356 {
357# ifdef IN_RC
358 rc = VMMGCCallHost(pVM, VMMCALLHOST_PDM_LOCK, 0);
359# else
360 rc = VMMR0CallHost(pVM, VMMCALLHOST_PDM_LOCK, 0);
361# endif
362 }
363#endif
364 AssertRC(rc);
365}
366
367
368/**
369 * Locks PDM but don't go to ring-3 if it's owned by someone.
370 *
371 * @returns VINF_SUCCESS on success.
372 * @returns rc if we're in GC or R0 and can't get the lock.
373 * @param pVM The VM handle.
374 * @param rc The RC to return in GC or R0 when we can't get the lock.
375 */
376int pdmLockEx(PVM pVM, int rc)
377{
378 return PDMCritSectEnter(&pVM->pdm.s.CritSect, rc);
379}
380
381
382/**
383 * Unlocks PDM.
384 *
385 * @param pVM The VM handle.
386 */
387void pdmUnlock(PVM pVM)
388{
389 PDMCritSectLeave(&pVM->pdm.s.CritSect);
390}
391
392
393/**
394 * Converts ring 3 VMM heap pointer to a guest physical address
395 *
396 * @returns VBox status code.
397 * @param pVM VM handle.
398 * @param pv Ring-3 pointer.
399 * @param pGCPhys GC phys address (out).
400 */
401VMMDECL(int) PDMVMMDevHeapR3ToGCPhys(PVM pVM, RTR3PTR pv, RTGCPHYS *pGCPhys)
402{
403 AssertReturn(pv >= pVM->pdm.s.pvVMMDevHeap && (RTR3UINTPTR)pv < (RTR3UINTPTR)pVM->pdm.s.pvVMMDevHeap + pVM->pdm.s.cbVMMDevHeap, VERR_INVALID_PARAMETER);
404
405 *pGCPhys = (pVM->pdm.s.GCPhysVMMDevHeap + ((RTR3UINTPTR)pv - (RTR3UINTPTR)pVM->pdm.s.pvVMMDevHeap));
406 return VINF_SUCCESS;
407}
注意: 瀏覽 TracBrowser 來幫助您使用儲存庫瀏覽器

© 2025 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette